1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-mpi-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon mpi. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_MPI_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_MPI_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_MPI_CFG_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 60215976Sjmallett cvmx_warn("CVMX_MPI_CFG not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000001000ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallettstatic inline uint64_t CVMX_MPI_DATX(unsigned long offset) 68215976Sjmallett{ 69215976Sjmallett if (!( 70215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) || 71215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) || 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8))))) 73215976Sjmallett cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset); 74215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8; 75215976Sjmallett} 76215976Sjmallett#else 77215976Sjmallett#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallett#define CVMX_MPI_STS CVMX_MPI_STS_FUNC() 81215976Sjmallettstatic inline uint64_t CVMX_MPI_STS_FUNC(void) 82215976Sjmallett{ 83215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 84215976Sjmallett cvmx_warn("CVMX_MPI_STS not supported on this chip\n"); 85215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000001008ull); 86215976Sjmallett} 87215976Sjmallett#else 88215976Sjmallett#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull)) 89215976Sjmallett#endif 90215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 91215976Sjmallett#define CVMX_MPI_TX CVMX_MPI_TX_FUNC() 92215976Sjmallettstatic inline uint64_t CVMX_MPI_TX_FUNC(void) 93215976Sjmallett{ 94215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 95215976Sjmallett cvmx_warn("CVMX_MPI_TX not supported on this chip\n"); 96215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000001010ull); 97215976Sjmallett} 98215976Sjmallett#else 99215976Sjmallett#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull)) 100215976Sjmallett#endif 101215976Sjmallett 102215976Sjmallett/** 103215976Sjmallett * cvmx_mpi_cfg 104215976Sjmallett */ 105215976Sjmallettunion cvmx_mpi_cfg 106215976Sjmallett{ 107215976Sjmallett uint64_t u64; 108215976Sjmallett struct cvmx_mpi_cfg_s 109215976Sjmallett { 110215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 111215976Sjmallett uint64_t reserved_29_63 : 35; 112215976Sjmallett uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) 113215976Sjmallett CLKDIV = Feclk / (2 * Fsclk) */ 114215976Sjmallett uint64_t reserved_12_15 : 4; 115215976Sjmallett uint64_t cslate : 1; /**< If 0, MPI_CS asserts 1/2 SCLK before transaction 116215976Sjmallett 1, MPI_CS assert coincident with transaction 117215976Sjmallett NOTE: only used if CSENA == 1 */ 118215976Sjmallett uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not 119215976Sjmallett expected to be driving 120215976Sjmallett 1, MPI_TX pin is tristated when not transmitting 121215976Sjmallett NOTE: only used when WIREOR==1 */ 122215976Sjmallett uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between 123215976Sjmallett commands. */ 124215976Sjmallett uint64_t cshi : 1; /**< If 0, CS is low asserted 125215976Sjmallett 1, CS is high asserted */ 126215976Sjmallett uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX 127215976Sjmallett 1, CS is driven per MPI_TX intruction */ 128215976Sjmallett uint64_t int_ena : 1; /**< If 0, polling is required 129215976Sjmallett 1, MPI engine interrupts X end of transaction */ 130215976Sjmallett uint64_t lsbfirst : 1; /**< If 0, shift MSB first 131215976Sjmallett 1, shift LSB first */ 132215976Sjmallett uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI) 133215976Sjmallett MPI_TX pin is always driven 134215976Sjmallett 1, MPI_TX/RX is all from MPI_TX pin (MPI) 135215976Sjmallett MPI_TX pin is tristated when not transmitting 136215976Sjmallett NOTE: if WIREOR==1, MPI_RX pin is not used by the 137215976Sjmallett MPI engine */ 138215976Sjmallett uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after 139215976Sjmallett completion of MPI transaction 140215976Sjmallett 1, clock never idles, requires CS deassertion 141215976Sjmallett assertion between commands */ 142215976Sjmallett uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo 143215976Sjmallett 1, MPI_CLK idles low, 1st transition is lo->hi */ 144215976Sjmallett uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs 145215976Sjmallett 1, MPI_CLK, MPI_CS, and MPI_TX are driven */ 146215976Sjmallett#else 147215976Sjmallett uint64_t enable : 1; 148215976Sjmallett uint64_t idlelo : 1; 149215976Sjmallett uint64_t clk_cont : 1; 150215976Sjmallett uint64_t wireor : 1; 151215976Sjmallett uint64_t lsbfirst : 1; 152215976Sjmallett uint64_t int_ena : 1; 153215976Sjmallett uint64_t csena : 1; 154215976Sjmallett uint64_t cshi : 1; 155215976Sjmallett uint64_t idleclks : 2; 156215976Sjmallett uint64_t tritx : 1; 157215976Sjmallett uint64_t cslate : 1; 158215976Sjmallett uint64_t reserved_12_15 : 4; 159215976Sjmallett uint64_t clkdiv : 13; 160215976Sjmallett uint64_t reserved_29_63 : 35; 161215976Sjmallett#endif 162215976Sjmallett } s; 163215976Sjmallett struct cvmx_mpi_cfg_s cn30xx; 164215976Sjmallett struct cvmx_mpi_cfg_cn31xx 165215976Sjmallett { 166215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 167215976Sjmallett uint64_t reserved_29_63 : 35; 168215976Sjmallett uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) 169215976Sjmallett CLKDIV = Feclk / (2 * Fsclk) */ 170215976Sjmallett uint64_t reserved_11_15 : 5; 171215976Sjmallett uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not 172215976Sjmallett expected to be driving 173215976Sjmallett 1, MPI_TX pin is tristated when not transmitting 174215976Sjmallett NOTE: only used when WIREOR==1 */ 175215976Sjmallett uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between 176215976Sjmallett commands. */ 177215976Sjmallett uint64_t cshi : 1; /**< If 0, CS is low asserted 178215976Sjmallett 1, CS is high asserted */ 179215976Sjmallett uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX 180215976Sjmallett 1, CS is driven per MPI_TX intruction */ 181215976Sjmallett uint64_t int_ena : 1; /**< If 0, polling is required 182215976Sjmallett 1, MPI engine interrupts X end of transaction */ 183215976Sjmallett uint64_t lsbfirst : 1; /**< If 0, shift MSB first 184215976Sjmallett 1, shift LSB first */ 185215976Sjmallett uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI) 186215976Sjmallett MPI_TX pin is always driven 187215976Sjmallett 1, MPI_TX/RX is all from MPI_TX pin (MPI) 188215976Sjmallett MPI_TX pin is tristated when not transmitting 189215976Sjmallett NOTE: if WIREOR==1, MPI_RX pin is not used by the 190215976Sjmallett MPI engine */ 191215976Sjmallett uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after 192215976Sjmallett completion of MPI transaction 193215976Sjmallett 1, clock never idles, requires CS deassertion 194215976Sjmallett assertion between commands */ 195215976Sjmallett uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo 196215976Sjmallett 1, MPI_CLK idles low, 1st transition is lo->hi */ 197215976Sjmallett uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs 198215976Sjmallett 1, MPI_CLK, MPI_CS, and MPI_TX are driven */ 199215976Sjmallett#else 200215976Sjmallett uint64_t enable : 1; 201215976Sjmallett uint64_t idlelo : 1; 202215976Sjmallett uint64_t clk_cont : 1; 203215976Sjmallett uint64_t wireor : 1; 204215976Sjmallett uint64_t lsbfirst : 1; 205215976Sjmallett uint64_t int_ena : 1; 206215976Sjmallett uint64_t csena : 1; 207215976Sjmallett uint64_t cshi : 1; 208215976Sjmallett uint64_t idleclks : 2; 209215976Sjmallett uint64_t tritx : 1; 210215976Sjmallett uint64_t reserved_11_15 : 5; 211215976Sjmallett uint64_t clkdiv : 13; 212215976Sjmallett uint64_t reserved_29_63 : 35; 213215976Sjmallett#endif 214215976Sjmallett } cn31xx; 215215976Sjmallett struct cvmx_mpi_cfg_s cn50xx; 216215976Sjmallett}; 217215976Sjmalletttypedef union cvmx_mpi_cfg cvmx_mpi_cfg_t; 218215976Sjmallett 219215976Sjmallett/** 220215976Sjmallett * cvmx_mpi_dat# 221215976Sjmallett */ 222215976Sjmallettunion cvmx_mpi_datx 223215976Sjmallett{ 224215976Sjmallett uint64_t u64; 225215976Sjmallett struct cvmx_mpi_datx_s 226215976Sjmallett { 227215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 228215976Sjmallett uint64_t reserved_8_63 : 56; 229215976Sjmallett uint64_t data : 8; /**< Data to transmit/received */ 230215976Sjmallett#else 231215976Sjmallett uint64_t data : 8; 232215976Sjmallett uint64_t reserved_8_63 : 56; 233215976Sjmallett#endif 234215976Sjmallett } s; 235215976Sjmallett struct cvmx_mpi_datx_s cn30xx; 236215976Sjmallett struct cvmx_mpi_datx_s cn31xx; 237215976Sjmallett struct cvmx_mpi_datx_s cn50xx; 238215976Sjmallett}; 239215976Sjmalletttypedef union cvmx_mpi_datx cvmx_mpi_datx_t; 240215976Sjmallett 241215976Sjmallett/** 242215976Sjmallett * cvmx_mpi_sts 243215976Sjmallett */ 244215976Sjmallettunion cvmx_mpi_sts 245215976Sjmallett{ 246215976Sjmallett uint64_t u64; 247215976Sjmallett struct cvmx_mpi_sts_s 248215976Sjmallett { 249215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 250215976Sjmallett uint64_t reserved_13_63 : 51; 251215976Sjmallett uint64_t rxnum : 5; /**< Number of bytes written for transaction */ 252215976Sjmallett uint64_t reserved_1_7 : 7; 253215976Sjmallett uint64_t busy : 1; /**< If 0, no MPI transaction in progress 254215976Sjmallett 1, MPI engine is processing a transaction */ 255215976Sjmallett#else 256215976Sjmallett uint64_t busy : 1; 257215976Sjmallett uint64_t reserved_1_7 : 7; 258215976Sjmallett uint64_t rxnum : 5; 259215976Sjmallett uint64_t reserved_13_63 : 51; 260215976Sjmallett#endif 261215976Sjmallett } s; 262215976Sjmallett struct cvmx_mpi_sts_s cn30xx; 263215976Sjmallett struct cvmx_mpi_sts_s cn31xx; 264215976Sjmallett struct cvmx_mpi_sts_s cn50xx; 265215976Sjmallett}; 266215976Sjmalletttypedef union cvmx_mpi_sts cvmx_mpi_sts_t; 267215976Sjmallett 268215976Sjmallett/** 269215976Sjmallett * cvmx_mpi_tx 270215976Sjmallett */ 271215976Sjmallettunion cvmx_mpi_tx 272215976Sjmallett{ 273215976Sjmallett uint64_t u64; 274215976Sjmallett struct cvmx_mpi_tx_s 275215976Sjmallett { 276215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 277215976Sjmallett uint64_t reserved_17_63 : 47; 278215976Sjmallett uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done 279215976Sjmallett 1, leave CS asserted after transactrion is done */ 280215976Sjmallett uint64_t reserved_13_15 : 3; 281215976Sjmallett uint64_t txnum : 5; /**< Number of bytes to transmit */ 282215976Sjmallett uint64_t reserved_5_7 : 3; 283215976Sjmallett uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) */ 284215976Sjmallett#else 285215976Sjmallett uint64_t totnum : 5; 286215976Sjmallett uint64_t reserved_5_7 : 3; 287215976Sjmallett uint64_t txnum : 5; 288215976Sjmallett uint64_t reserved_13_15 : 3; 289215976Sjmallett uint64_t leavecs : 1; 290215976Sjmallett uint64_t reserved_17_63 : 47; 291215976Sjmallett#endif 292215976Sjmallett } s; 293215976Sjmallett struct cvmx_mpi_tx_s cn30xx; 294215976Sjmallett struct cvmx_mpi_tx_s cn31xx; 295215976Sjmallett struct cvmx_mpi_tx_s cn50xx; 296215976Sjmallett}; 297215976Sjmalletttypedef union cvmx_mpi_tx cvmx_mpi_tx_t; 298215976Sjmallett 299215976Sjmallett#endif 300