1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-l2t-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon l2t. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_L2T_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_L2T_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_L2T_ERR_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 60215976Sjmallett cvmx_warn("CVMX_L2T_ERR not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000008ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull)) 65215976Sjmallett#endif 66215976Sjmallett 67215976Sjmallett/** 68215976Sjmallett * cvmx_l2t_err 69215976Sjmallett * 70215976Sjmallett * L2T_ERR = L2 Tag Errors 71215976Sjmallett * 72215976Sjmallett * Description: L2 Tag ECC SEC/DED Errors and Interrupt Enable 73215976Sjmallett */ 74215976Sjmallettunion cvmx_l2t_err 75215976Sjmallett{ 76215976Sjmallett uint64_t u64; 77215976Sjmallett struct cvmx_l2t_err_s 78215976Sjmallett { 79215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 80215976Sjmallett uint64_t reserved_29_63 : 35; 81215976Sjmallett uint64_t fadru : 1; /**< Failing L2 Tag Upper Address Bit (Index[10]) 82215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 83215976Sjmallett the FADRU contains the upper(MSB bit) cacheline index 84215976Sjmallett into the L2 Tag Store. */ 85215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 86215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 87215976Sjmallett could not find an available/unlocked set (for 88215976Sjmallett replacement). 89215976Sjmallett Most likely, this is a result of SW mixing SET 90215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 91215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 92215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 93215976Sjmallett to determine a 'valid' replacement set (since LOCKED 94215976Sjmallett addresses should NEVER be replaced). 95215976Sjmallett If such an event occurs, the HW will select the smallest 96215976Sjmallett available SET(specified by UMSK'x)' as the replacement 97215976Sjmallett set, and the address is unlocked. */ 98215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 99215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 100215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 101215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 102215976Sjmallett successfully, however the address is NOT locked. 103215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 104215976Sjmallett into account. For example, if diagnostic PPx has 105215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 106215976Sjmallett been previously LOCKED, then an attempt to LOCK the 107215976Sjmallett last available SET0 would result in a LCKERR. (This 108215976Sjmallett is to ensure that at least 1 SET at each INDEX is 109215976Sjmallett not LOCKED for general use by other PPs). */ 110215976Sjmallett uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 111215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 112215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 113215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 114215976Sjmallett is specified by the L2C_DBG[SET]. */ 115215976Sjmallett uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index) 116215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 117215976Sjmallett the FADR contains the lower 10bit cacheline index 118215976Sjmallett into the L2 Tag Store. */ 119215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 120215976Sjmallett the contents of this register contain the 6-bit 121215976Sjmallett syndrome for the hit set only. 122215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 123215976Sjmallett the "non-hit" sets at the failing index(FADR). 124215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 125215976Sjmallett is specified by the L2C_DBG[SET]. 126215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 127215976Sjmallett hit set at the failing index(FADR) and failing 128215976Sjmallett set(FSET). 129215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 130215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 131215976Sjmallett read the other sets at the failing index(FADR). When 132215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 133215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 134215976Sjmallett SYNDROME and FADR). */ 135215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 136215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 137215976Sjmallett given index) are checked for double bit errors(DBEs). 138215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 139215976Sjmallett DBEs also generated an interrupt(if enabled). */ 140215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 141215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 142215976Sjmallett given index) are checked for single bit errors(SBEs). 143215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 144215976Sjmallett SBEs are auto corrected in HW and generate an 145215976Sjmallett interrupt(if enabled). */ 146215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 147215976Sjmallett Enable bit. When set, allows interrupts to be 148215976Sjmallett reported on double bit (uncorrectable) errors from 149215976Sjmallett the L2 Tag Arrays. */ 150215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 151215976Sjmallett Enable bit. When set, allows interrupts to be 152215976Sjmallett reported on single bit (correctable) errors from 153215976Sjmallett the L2 Tag Arrays. */ 154215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 155215976Sjmallett When set, enables 6-bit SEC/DED codeword for 19-bit 156215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:18]] */ 157215976Sjmallett#else 158215976Sjmallett uint64_t ecc_ena : 1; 159215976Sjmallett uint64_t sec_intena : 1; 160215976Sjmallett uint64_t ded_intena : 1; 161215976Sjmallett uint64_t sec_err : 1; 162215976Sjmallett uint64_t ded_err : 1; 163215976Sjmallett uint64_t fsyn : 6; 164215976Sjmallett uint64_t fadr : 10; 165215976Sjmallett uint64_t fset : 3; 166215976Sjmallett uint64_t lckerr : 1; 167215976Sjmallett uint64_t lck_intena : 1; 168215976Sjmallett uint64_t lckerr2 : 1; 169215976Sjmallett uint64_t lck_intena2 : 1; 170215976Sjmallett uint64_t fadru : 1; 171215976Sjmallett uint64_t reserved_29_63 : 35; 172215976Sjmallett#endif 173215976Sjmallett } s; 174215976Sjmallett struct cvmx_l2t_err_cn30xx 175215976Sjmallett { 176215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 177215976Sjmallett uint64_t reserved_28_63 : 36; 178215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 179215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 180215976Sjmallett could not find an available/unlocked set (for 181215976Sjmallett replacement). 182215976Sjmallett Most likely, this is a result of SW mixing SET 183215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 184215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 185215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 186215976Sjmallett to determine a 'valid' replacement set (since LOCKED 187215976Sjmallett addresses should NEVER be replaced). 188215976Sjmallett If such an event occurs, the HW will select the smallest 189215976Sjmallett available SET(specified by UMSK'x)' as the replacement 190215976Sjmallett set, and the address is unlocked. */ 191215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 192215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 193215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 194215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is 195215976Sjmallett completed successfully, however the address is NOT 196215976Sjmallett locked. 197215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 198215976Sjmallett into account. For example, if diagnostic PPx has 199215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 200215976Sjmallett been previously LOCKED, then an attempt to LOCK the 201215976Sjmallett last available SET0 would result in a LCKERR. (This 202215976Sjmallett is to ensure that at least 1 SET at each INDEX is 203215976Sjmallett not LOCKED for general use by other PPs). */ 204215976Sjmallett uint64_t reserved_23_23 : 1; 205215976Sjmallett uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4) 206215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 207215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 208215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 209215976Sjmallett is specified by the L2C_DBG[SET]. */ 210215976Sjmallett uint64_t reserved_19_20 : 2; 211215976Sjmallett uint64_t fadr : 8; /**< Failing L2 Tag Store Index (8-bit) 212215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 213215976Sjmallett the FADR contains the 8bit cacheline index into the 214215976Sjmallett L2 Tag Store. */ 215215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 216215976Sjmallett the contents of this register contain the 6-bit 217215976Sjmallett syndrome for the hit set only. 218215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 219215976Sjmallett the "non-hit" sets at the failing index(FADR). 220215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 221215976Sjmallett is specified by the L2C_DBG[SET]. 222215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 223215976Sjmallett hit set at the failing index(FADR) and failing 224215976Sjmallett set(FSET). 225215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 226215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 227215976Sjmallett read the other sets at the failing index(FADR). When 228215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 229215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 230215976Sjmallett SYNDROME and FADR). */ 231215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 232215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 233215976Sjmallett given index) are checked for double bit errors(DBEs). 234215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 235215976Sjmallett DBEs also generated an interrupt(if enabled). */ 236215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 237215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 238215976Sjmallett given index) are checked for single bit errors(SBEs). 239215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 240215976Sjmallett SBEs are auto corrected in HW and generate an 241215976Sjmallett interrupt(if enabled). */ 242215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 243215976Sjmallett Enable bit. When set, allows interrupts to be 244215976Sjmallett reported on double bit (uncorrectable) errors from 245215976Sjmallett the L2 Tag Arrays. */ 246215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 247215976Sjmallett Enable bit. When set, allows interrupts to be 248215976Sjmallett reported on single bit (correctable) errors from 249215976Sjmallett the L2 Tag Arrays. */ 250215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 251215976Sjmallett When set, enables 6-bit SEC/DED codeword for 22-bit 252215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:15]] */ 253215976Sjmallett#else 254215976Sjmallett uint64_t ecc_ena : 1; 255215976Sjmallett uint64_t sec_intena : 1; 256215976Sjmallett uint64_t ded_intena : 1; 257215976Sjmallett uint64_t sec_err : 1; 258215976Sjmallett uint64_t ded_err : 1; 259215976Sjmallett uint64_t fsyn : 6; 260215976Sjmallett uint64_t fadr : 8; 261215976Sjmallett uint64_t reserved_19_20 : 2; 262215976Sjmallett uint64_t fset : 2; 263215976Sjmallett uint64_t reserved_23_23 : 1; 264215976Sjmallett uint64_t lckerr : 1; 265215976Sjmallett uint64_t lck_intena : 1; 266215976Sjmallett uint64_t lckerr2 : 1; 267215976Sjmallett uint64_t lck_intena2 : 1; 268215976Sjmallett uint64_t reserved_28_63 : 36; 269215976Sjmallett#endif 270215976Sjmallett } cn30xx; 271215976Sjmallett struct cvmx_l2t_err_cn31xx 272215976Sjmallett { 273215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 274215976Sjmallett uint64_t reserved_28_63 : 36; 275215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 276215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 277215976Sjmallett could not find an available/unlocked set (for 278215976Sjmallett replacement). 279215976Sjmallett Most likely, this is a result of SW mixing SET 280215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 281215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 282215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 283215976Sjmallett to determine a 'valid' replacement set (since LOCKED 284215976Sjmallett addresses should NEVER be replaced). 285215976Sjmallett If such an event occurs, the HW will select the smallest 286215976Sjmallett available SET(specified by UMSK'x)' as the replacement 287215976Sjmallett set, and the address is unlocked. */ 288215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 289215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 290215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 291215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 292215976Sjmallett successfully, however the address is NOT locked. 293215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 294215976Sjmallett into account. For example, if diagnostic PPx has 295215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 296215976Sjmallett been previously LOCKED, then an attempt to LOCK the 297215976Sjmallett last available SET0 would result in a LCKERR. (This 298215976Sjmallett is to ensure that at least 1 SET at each INDEX is 299215976Sjmallett not LOCKED for general use by other PPs). */ 300215976Sjmallett uint64_t reserved_23_23 : 1; 301215976Sjmallett uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4) 302215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 303215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 304215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 305215976Sjmallett is specified by the L2C_DBG[SET]. */ 306215976Sjmallett uint64_t reserved_20_20 : 1; 307215976Sjmallett uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index) 308215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 309215976Sjmallett the FADR contains the 9-bit cacheline index into the 310215976Sjmallett L2 Tag Store. */ 311215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 312215976Sjmallett the contents of this register contain the 6-bit 313215976Sjmallett syndrome for the hit set only. 314215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 315215976Sjmallett the "non-hit" sets at the failing index(FADR). 316215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 317215976Sjmallett is specified by the L2C_DBG[SET]. 318215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 319215976Sjmallett hit set at the failing index(FADR) and failing 320215976Sjmallett set(FSET). 321215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 322215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 323215976Sjmallett read the other sets at the failing index(FADR). When 324215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 325215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 326215976Sjmallett SYNDROME and FADR). */ 327215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 328215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 329215976Sjmallett given index) are checked for double bit errors(DBEs). 330215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 331215976Sjmallett DBEs also generated an interrupt(if enabled). */ 332215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 333215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 334215976Sjmallett given index) are checked for single bit errors(SBEs). 335215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 336215976Sjmallett SBEs are auto corrected in HW and generate an 337215976Sjmallett interrupt(if enabled). */ 338215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 339215976Sjmallett Enable bit. When set, allows interrupts to be 340215976Sjmallett reported on double bit (uncorrectable) errors from 341215976Sjmallett the L2 Tag Arrays. */ 342215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 343215976Sjmallett Enable bit. When set, allows interrupts to be 344215976Sjmallett reported on single bit (correctable) errors from 345215976Sjmallett the L2 Tag Arrays. */ 346215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 347215976Sjmallett When set, enables 6-bit SEC/DED codeword for 21-bit 348215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:16]] */ 349215976Sjmallett#else 350215976Sjmallett uint64_t ecc_ena : 1; 351215976Sjmallett uint64_t sec_intena : 1; 352215976Sjmallett uint64_t ded_intena : 1; 353215976Sjmallett uint64_t sec_err : 1; 354215976Sjmallett uint64_t ded_err : 1; 355215976Sjmallett uint64_t fsyn : 6; 356215976Sjmallett uint64_t fadr : 9; 357215976Sjmallett uint64_t reserved_20_20 : 1; 358215976Sjmallett uint64_t fset : 2; 359215976Sjmallett uint64_t reserved_23_23 : 1; 360215976Sjmallett uint64_t lckerr : 1; 361215976Sjmallett uint64_t lck_intena : 1; 362215976Sjmallett uint64_t lckerr2 : 1; 363215976Sjmallett uint64_t lck_intena2 : 1; 364215976Sjmallett uint64_t reserved_28_63 : 36; 365215976Sjmallett#endif 366215976Sjmallett } cn31xx; 367215976Sjmallett struct cvmx_l2t_err_cn38xx 368215976Sjmallett { 369215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 370215976Sjmallett uint64_t reserved_28_63 : 36; 371215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 372215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 373215976Sjmallett could not find an available/unlocked set (for 374215976Sjmallett replacement). 375215976Sjmallett Most likely, this is a result of SW mixing SET 376215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 377215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 378215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 379215976Sjmallett to determine a 'valid' replacement set (since LOCKED 380215976Sjmallett addresses should NEVER be replaced). 381215976Sjmallett If such an event occurs, the HW will select the smallest 382215976Sjmallett available SET(specified by UMSK'x)' as the replacement 383215976Sjmallett set, and the address is unlocked. */ 384215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 385215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 386215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 387215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 388215976Sjmallett successfully, however the address is NOT locked. 389215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 390215976Sjmallett into account. For example, if diagnostic PPx has 391215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 392215976Sjmallett been previously LOCKED, then an attempt to LOCK the 393215976Sjmallett last available SET0 would result in a LCKERR. (This 394215976Sjmallett is to ensure that at least 1 SET at each INDEX is 395215976Sjmallett not LOCKED for general use by other PPs). */ 396215976Sjmallett uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 397215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 398215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 399215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 400215976Sjmallett is specified by the L2C_DBG[SET]. */ 401215976Sjmallett uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index) 402215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 403215976Sjmallett the FADR contains the 10bit cacheline index into the 404215976Sjmallett L2 Tag Store. */ 405215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 406215976Sjmallett the contents of this register contain the 6-bit 407215976Sjmallett syndrome for the hit set only. 408215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 409215976Sjmallett the "non-hit" sets at the failing index(FADR). 410215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 411215976Sjmallett is specified by the L2C_DBG[SET]. 412215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 413215976Sjmallett hit set at the failing index(FADR) and failing 414215976Sjmallett set(FSET). 415215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 416215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 417215976Sjmallett read the other sets at the failing index(FADR). When 418215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 419215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 420215976Sjmallett SYNDROME and FADR). */ 421215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 422215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 423215976Sjmallett given index) are checked for double bit errors(DBEs). 424215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 425215976Sjmallett DBEs also generated an interrupt(if enabled). */ 426215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 427215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 428215976Sjmallett given index) are checked for single bit errors(SBEs). 429215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 430215976Sjmallett SBEs are auto corrected in HW and generate an 431215976Sjmallett interrupt(if enabled). */ 432215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 433215976Sjmallett Enable bit. When set, allows interrupts to be 434215976Sjmallett reported on double bit (uncorrectable) errors from 435215976Sjmallett the L2 Tag Arrays. */ 436215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 437215976Sjmallett Enable bit. When set, allows interrupts to be 438215976Sjmallett reported on single bit (correctable) errors from 439215976Sjmallett the L2 Tag Arrays. */ 440215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 441215976Sjmallett When set, enables 6-bit SEC/DED codeword for 20-bit 442215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:17]] */ 443215976Sjmallett#else 444215976Sjmallett uint64_t ecc_ena : 1; 445215976Sjmallett uint64_t sec_intena : 1; 446215976Sjmallett uint64_t ded_intena : 1; 447215976Sjmallett uint64_t sec_err : 1; 448215976Sjmallett uint64_t ded_err : 1; 449215976Sjmallett uint64_t fsyn : 6; 450215976Sjmallett uint64_t fadr : 10; 451215976Sjmallett uint64_t fset : 3; 452215976Sjmallett uint64_t lckerr : 1; 453215976Sjmallett uint64_t lck_intena : 1; 454215976Sjmallett uint64_t lckerr2 : 1; 455215976Sjmallett uint64_t lck_intena2 : 1; 456215976Sjmallett uint64_t reserved_28_63 : 36; 457215976Sjmallett#endif 458215976Sjmallett } cn38xx; 459215976Sjmallett struct cvmx_l2t_err_cn38xx cn38xxp2; 460215976Sjmallett struct cvmx_l2t_err_cn50xx 461215976Sjmallett { 462215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 463215976Sjmallett uint64_t reserved_28_63 : 36; 464215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 465215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 466215976Sjmallett could not find an available/unlocked set (for 467215976Sjmallett replacement). 468215976Sjmallett Most likely, this is a result of SW mixing SET 469215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 470215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 471215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 472215976Sjmallett to determine a 'valid' replacement set (since LOCKED 473215976Sjmallett addresses should NEVER be replaced). 474215976Sjmallett If such an event occurs, the HW will select the smallest 475215976Sjmallett available SET(specified by UMSK'x)' as the replacement 476215976Sjmallett set, and the address is unlocked. */ 477215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 478215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 479215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 480215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 481215976Sjmallett successfully, however the address is NOT locked. 482215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 483215976Sjmallett into account. For example, if diagnostic PPx has 484215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 485215976Sjmallett been previously LOCKED, then an attempt to LOCK the 486215976Sjmallett last available SET0 would result in a LCKERR. (This 487215976Sjmallett is to ensure that at least 1 SET at each INDEX is 488215976Sjmallett not LOCKED for general use by other PPs). */ 489215976Sjmallett uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 490215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 491215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 492215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 493215976Sjmallett is specified by the L2C_DBG[SET]. */ 494215976Sjmallett uint64_t reserved_18_20 : 3; 495215976Sjmallett uint64_t fadr : 7; /**< Failing L2 Tag Address (7-bit Index) 496215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 497215976Sjmallett the FADR contains the lower 7bit cacheline index 498215976Sjmallett into the L2 Tag Store. */ 499215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 500215976Sjmallett the contents of this register contain the 6-bit 501215976Sjmallett syndrome for the hit set only. 502215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 503215976Sjmallett the "non-hit" sets at the failing index(FADR). 504215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 505215976Sjmallett is specified by the L2C_DBG[SET]. 506215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 507215976Sjmallett hit set at the failing index(FADR) and failing 508215976Sjmallett set(FSET). 509215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 510215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 511215976Sjmallett read the other sets at the failing index(FADR). When 512215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 513215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 514215976Sjmallett SYNDROME and FADR). */ 515215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 516215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 517215976Sjmallett given index) are checked for double bit errors(DBEs). 518215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 519215976Sjmallett DBEs also generated an interrupt(if enabled). */ 520215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 521215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 522215976Sjmallett given index) are checked for single bit errors(SBEs). 523215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 524215976Sjmallett SBEs are auto corrected in HW and generate an 525215976Sjmallett interrupt(if enabled). */ 526215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 527215976Sjmallett Enable bit. When set, allows interrupts to be 528215976Sjmallett reported on double bit (uncorrectable) errors from 529215976Sjmallett the L2 Tag Arrays. */ 530215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 531215976Sjmallett Enable bit. When set, allows interrupts to be 532215976Sjmallett reported on single bit (correctable) errors from 533215976Sjmallett the L2 Tag Arrays. */ 534215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 535215976Sjmallett When set, enables 6-bit SEC/DED codeword for 23-bit 536215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:14]] */ 537215976Sjmallett#else 538215976Sjmallett uint64_t ecc_ena : 1; 539215976Sjmallett uint64_t sec_intena : 1; 540215976Sjmallett uint64_t ded_intena : 1; 541215976Sjmallett uint64_t sec_err : 1; 542215976Sjmallett uint64_t ded_err : 1; 543215976Sjmallett uint64_t fsyn : 6; 544215976Sjmallett uint64_t fadr : 7; 545215976Sjmallett uint64_t reserved_18_20 : 3; 546215976Sjmallett uint64_t fset : 3; 547215976Sjmallett uint64_t lckerr : 1; 548215976Sjmallett uint64_t lck_intena : 1; 549215976Sjmallett uint64_t lckerr2 : 1; 550215976Sjmallett uint64_t lck_intena2 : 1; 551215976Sjmallett uint64_t reserved_28_63 : 36; 552215976Sjmallett#endif 553215976Sjmallett } cn50xx; 554215976Sjmallett struct cvmx_l2t_err_cn52xx 555215976Sjmallett { 556215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 557215976Sjmallett uint64_t reserved_28_63 : 36; 558215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 559215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 560215976Sjmallett could not find an available/unlocked set (for 561215976Sjmallett replacement). 562215976Sjmallett Most likely, this is a result of SW mixing SET 563215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 564215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 565215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 566215976Sjmallett to determine a 'valid' replacement set (since LOCKED 567215976Sjmallett addresses should NEVER be replaced). 568215976Sjmallett If such an event occurs, the HW will select the smallest 569215976Sjmallett available SET(specified by UMSK'x)' as the replacement 570215976Sjmallett set, and the address is unlocked. */ 571215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 572215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 573215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 574215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 575215976Sjmallett successfully, however the address is NOT locked. 576215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 577215976Sjmallett into account. For example, if diagnostic PPx has 578215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 579215976Sjmallett been previously LOCKED, then an attempt to LOCK the 580215976Sjmallett last available SET0 would result in a LCKERR. (This 581215976Sjmallett is to ensure that at least 1 SET at each INDEX is 582215976Sjmallett not LOCKED for general use by other PPs). */ 583215976Sjmallett uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 584215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 585215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 586215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 587215976Sjmallett is specified by the L2C_DBG[SET]. */ 588215976Sjmallett uint64_t reserved_20_20 : 1; 589215976Sjmallett uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index) 590215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 591215976Sjmallett the FADR contains the lower 9bit cacheline index 592215976Sjmallett into the L2 Tag Store. */ 593215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 594215976Sjmallett the contents of this register contain the 6-bit 595215976Sjmallett syndrome for the hit set only. 596215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 597215976Sjmallett the "non-hit" sets at the failing index(FADR). 598215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 599215976Sjmallett is specified by the L2C_DBG[SET]. 600215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 601215976Sjmallett hit set at the failing index(FADR) and failing 602215976Sjmallett set(FSET). 603215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 604215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 605215976Sjmallett read the other sets at the failing index(FADR). When 606215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 607215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 608215976Sjmallett SYNDROME and FADR). */ 609215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 610215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 611215976Sjmallett given index) are checked for double bit errors(DBEs). 612215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 613215976Sjmallett DBEs also generated an interrupt(if enabled). */ 614215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 615215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 616215976Sjmallett given index) are checked for single bit errors(SBEs). 617215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 618215976Sjmallett SBEs are auto corrected in HW and generate an 619215976Sjmallett interrupt(if enabled). */ 620215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 621215976Sjmallett Enable bit. When set, allows interrupts to be 622215976Sjmallett reported on double bit (uncorrectable) errors from 623215976Sjmallett the L2 Tag Arrays. */ 624215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 625215976Sjmallett Enable bit. When set, allows interrupts to be 626215976Sjmallett reported on single bit (correctable) errors from 627215976Sjmallett the L2 Tag Arrays. */ 628215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 629215976Sjmallett When set, enables 6-bit SEC/DED codeword for 21-bit 630215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:16]] */ 631215976Sjmallett#else 632215976Sjmallett uint64_t ecc_ena : 1; 633215976Sjmallett uint64_t sec_intena : 1; 634215976Sjmallett uint64_t ded_intena : 1; 635215976Sjmallett uint64_t sec_err : 1; 636215976Sjmallett uint64_t ded_err : 1; 637215976Sjmallett uint64_t fsyn : 6; 638215976Sjmallett uint64_t fadr : 9; 639215976Sjmallett uint64_t reserved_20_20 : 1; 640215976Sjmallett uint64_t fset : 3; 641215976Sjmallett uint64_t lckerr : 1; 642215976Sjmallett uint64_t lck_intena : 1; 643215976Sjmallett uint64_t lckerr2 : 1; 644215976Sjmallett uint64_t lck_intena2 : 1; 645215976Sjmallett uint64_t reserved_28_63 : 36; 646215976Sjmallett#endif 647215976Sjmallett } cn52xx; 648215976Sjmallett struct cvmx_l2t_err_cn52xx cn52xxp1; 649215976Sjmallett struct cvmx_l2t_err_s cn56xx; 650215976Sjmallett struct cvmx_l2t_err_s cn56xxp1; 651215976Sjmallett struct cvmx_l2t_err_s cn58xx; 652215976Sjmallett struct cvmx_l2t_err_s cn58xxp1; 653215976Sjmallett}; 654215976Sjmalletttypedef union cvmx_l2t_err cvmx_l2t_err_t; 655215976Sjmallett 656215976Sjmallett#endif 657