1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-ipd-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon ipd. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_IPD_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_IPD_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull)) 56215976Sjmallett#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull)) 57215976Sjmallett#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull)) 58215976Sjmallett#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull)) 59215976Sjmallett#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull)) 60215976Sjmallett#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull)) 61215976Sjmallett#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull)) 62215976Sjmallett#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull)) 63215976Sjmallett#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull)) 64215976Sjmallett#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull)) 65215976Sjmallett#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull)) 66215976Sjmallett#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull)) 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallettstatic inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset) 69215976Sjmallett{ 70215976Sjmallett if (!( 71215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) || 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 73215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 75215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 76215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 77215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 78215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))))) 79215976Sjmallett cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n", offset); 80215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8; 81215976Sjmallett} 82215976Sjmallett#else 83215976Sjmallett#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8) 84215976Sjmallett#endif 85215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86215976Sjmallettstatic inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset) 87215976Sjmallett{ 88215976Sjmallett if (!( 89215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) || 90215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) || 91215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))))) 92215976Sjmallett cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n", offset); 93215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36; 94215976Sjmallett} 95215976Sjmallett#else 96215976Sjmallett#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36) 97215976Sjmallett#endif 98215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 99215976Sjmallettstatic inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT3(unsigned long offset) 100215976Sjmallett{ 101215976Sjmallett if (!( 102215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 103215976Sjmallett cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT3(%lu) is invalid on this chip\n", offset); 104215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40; 105215976Sjmallett} 106215976Sjmallett#else 107215976Sjmallett#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40) 108215976Sjmallett#endif 109215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 110215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset) 111215976Sjmallett{ 112215976Sjmallett if (!( 113215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) || 114215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) || 115215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))))) 116215976Sjmallett cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n", offset); 117215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36; 118215976Sjmallett} 119215976Sjmallett#else 120215976Sjmallett#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36) 121215976Sjmallett#endif 122215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 123215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(unsigned long offset) 124215976Sjmallett{ 125215976Sjmallett if (!( 126215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 127215976Sjmallett cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(%lu) is invalid on this chip\n", offset); 128215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40; 129215976Sjmallett} 130215976Sjmallett#else 131215976Sjmallett#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40) 132215976Sjmallett#endif 133215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset) 135215976Sjmallett{ 136215976Sjmallett if (!( 137215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) || 138215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 139215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 140215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 141215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 142215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 143215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 144215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))))) 145215976Sjmallett cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n", offset); 146215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8; 147215976Sjmallett} 148215976Sjmallett#else 149215976Sjmallett#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8) 150215976Sjmallett#endif 151215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset) 153215976Sjmallett{ 154215976Sjmallett if (!( 155215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) || 156215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) || 157215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))))) 158215976Sjmallett cvmx_warn("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n", offset); 159215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8; 160215976Sjmallett} 161215976Sjmallett#else 162215976Sjmallett#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8) 163215976Sjmallett#endif 164215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 165215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset) 166215976Sjmallett{ 167215976Sjmallett if (!( 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) || 169215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) || 170215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))))) 171215976Sjmallett cvmx_warn("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n", offset); 172215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8; 173215976Sjmallett} 174215976Sjmallett#else 175215976Sjmallett#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8) 176215976Sjmallett#endif 177215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 178215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset) 179215976Sjmallett{ 180215976Sjmallett if (!( 181215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 319)))) || 182215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 319)))) || 183215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 351)))))) 184215976Sjmallett cvmx_warn("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n", offset); 185215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8; 186215976Sjmallett} 187215976Sjmallett#else 188215976Sjmallett#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8) 189215976Sjmallett#endif 190215976Sjmallett#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull)) 191215976Sjmallett#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull)) 192215976Sjmallett#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull)) 193215976Sjmallett#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull)) 194215976Sjmallett#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0) 195215976Sjmallett#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1) 196215976Sjmallett#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2) 197215976Sjmallett#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3) 198215976Sjmallett#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4) 199215976Sjmallett#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5) 200215976Sjmallett#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6) 201215976Sjmallett#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) 202215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 203215976Sjmallettstatic inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset) 204215976Sjmallett{ 205215976Sjmallett if (!( 206215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 207215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 208215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 209215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 210215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 211215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 212215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 214215976Sjmallett cvmx_warn("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n", offset); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8; 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8) 219215976Sjmallett#endif 220215976Sjmallett#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull)) 221215976Sjmallett#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull)) 222215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 223215976Sjmallett#define CVMX_IPD_RED_PORT_ENABLE2 CVMX_IPD_RED_PORT_ENABLE2_FUNC() 224215976Sjmallettstatic inline uint64_t CVMX_IPD_RED_PORT_ENABLE2_FUNC(void) 225215976Sjmallett{ 226215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 227215976Sjmallett cvmx_warn("CVMX_IPD_RED_PORT_ENABLE2 not supported on this chip\n"); 228215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000003A8ull); 229215976Sjmallett} 230215976Sjmallett#else 231215976Sjmallett#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull)) 232215976Sjmallett#endif 233215976Sjmallett#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0) 234215976Sjmallett#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1) 235215976Sjmallett#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2) 236215976Sjmallett#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3) 237215976Sjmallett#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4) 238215976Sjmallett#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5) 239215976Sjmallett#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6) 240215976Sjmallett#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7) 241215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 242215976Sjmallettstatic inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset) 243215976Sjmallett{ 244215976Sjmallett if (!( 245215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 246215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 247215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 248215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 249215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 250215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 251215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 252215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 253215976Sjmallett cvmx_warn("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n", offset); 254215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8; 255215976Sjmallett} 256215976Sjmallett#else 257215976Sjmallett#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8) 258215976Sjmallett#endif 259215976Sjmallett#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull)) 260215976Sjmallett#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull)) 261215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 262215976Sjmallett#define CVMX_IPD_SUB_PORT_QOS_CNT CVMX_IPD_SUB_PORT_QOS_CNT_FUNC() 263215976Sjmallettstatic inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void) 264215976Sjmallett{ 265215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 266215976Sjmallett cvmx_warn("CVMX_IPD_SUB_PORT_QOS_CNT not supported on this chip\n"); 267215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000800ull); 268215976Sjmallett} 269215976Sjmallett#else 270215976Sjmallett#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull)) 271215976Sjmallett#endif 272215976Sjmallett#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull)) 273215976Sjmallett#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull)) 274215976Sjmallett 275215976Sjmallett/** 276215976Sjmallett * cvmx_ipd_1st_mbuff_skip 277215976Sjmallett * 278215976Sjmallett * IPD_1ST_MBUFF_SKIP = IPD First MBUFF Word Skip Size 279215976Sjmallett * 280215976Sjmallett * The number of words that the IPD will skip when writing the first MBUFF. 281215976Sjmallett */ 282215976Sjmallettunion cvmx_ipd_1st_mbuff_skip 283215976Sjmallett{ 284215976Sjmallett uint64_t u64; 285215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s 286215976Sjmallett { 287215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 288215976Sjmallett uint64_t reserved_6_63 : 58; 289215976Sjmallett uint64_t skip_sz : 6; /**< The number of 8-byte words from the top of the 290215976Sjmallett 1st MBUFF that the IPD will store the next-pointer. 291215976Sjmallett Legal values are 0 to 32, where the MAX value 292215976Sjmallett is also limited to: 293215976Sjmallett IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 18. 294215976Sjmallett Must be at least 16 when IPD_CTL_STATUS[NO_WPTR] 295215976Sjmallett is set. */ 296215976Sjmallett#else 297215976Sjmallett uint64_t skip_sz : 6; 298215976Sjmallett uint64_t reserved_6_63 : 58; 299215976Sjmallett#endif 300215976Sjmallett } s; 301215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn30xx; 302215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn31xx; 303215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn38xx; 304215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2; 305215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn50xx; 306215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn52xx; 307215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1; 308215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn56xx; 309215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1; 310215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn58xx; 311215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1; 312215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn63xx; 313215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1; 314215976Sjmallett}; 315215976Sjmalletttypedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_1st_mbuff_skip_t; 316215976Sjmallett 317215976Sjmallett/** 318215976Sjmallett * cvmx_ipd_1st_next_ptr_back 319215976Sjmallett * 320215976Sjmallett * IPD_1st_NEXT_PTR_BACK = IPD First Next Pointer Back Values 321215976Sjmallett * 322215976Sjmallett * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF 323215976Sjmallett */ 324215976Sjmallettunion cvmx_ipd_1st_next_ptr_back 325215976Sjmallett{ 326215976Sjmallett uint64_t u64; 327215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s 328215976Sjmallett { 329215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 330215976Sjmallett uint64_t reserved_4_63 : 60; 331215976Sjmallett uint64_t back : 4; /**< Used to find head of buffer from the nxt-hdr-ptr. */ 332215976Sjmallett#else 333215976Sjmallett uint64_t back : 4; 334215976Sjmallett uint64_t reserved_4_63 : 60; 335215976Sjmallett#endif 336215976Sjmallett } s; 337215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn30xx; 338215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn31xx; 339215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn38xx; 340215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2; 341215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn50xx; 342215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn52xx; 343215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1; 344215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn56xx; 345215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1; 346215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn58xx; 347215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1; 348215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn63xx; 349215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1; 350215976Sjmallett}; 351215976Sjmalletttypedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_1st_next_ptr_back_t; 352215976Sjmallett 353215976Sjmallett/** 354215976Sjmallett * cvmx_ipd_2nd_next_ptr_back 355215976Sjmallett * 356215976Sjmallett * IPD_2nd_NEXT_PTR_BACK = IPD Second Next Pointer Back Value 357215976Sjmallett * 358215976Sjmallett * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF 359215976Sjmallett */ 360215976Sjmallettunion cvmx_ipd_2nd_next_ptr_back 361215976Sjmallett{ 362215976Sjmallett uint64_t u64; 363215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s 364215976Sjmallett { 365215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 366215976Sjmallett uint64_t reserved_4_63 : 60; 367215976Sjmallett uint64_t back : 4; /**< Used to find head of buffer from the nxt-hdr-ptr. */ 368215976Sjmallett#else 369215976Sjmallett uint64_t back : 4; 370215976Sjmallett uint64_t reserved_4_63 : 60; 371215976Sjmallett#endif 372215976Sjmallett } s; 373215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn30xx; 374215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn31xx; 375215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn38xx; 376215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2; 377215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn50xx; 378215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn52xx; 379215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1; 380215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn56xx; 381215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1; 382215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn58xx; 383215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1; 384215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn63xx; 385215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1; 386215976Sjmallett}; 387215976Sjmalletttypedef union cvmx_ipd_2nd_next_ptr_back cvmx_ipd_2nd_next_ptr_back_t; 388215976Sjmallett 389215976Sjmallett/** 390215976Sjmallett * cvmx_ipd_bist_status 391215976Sjmallett * 392215976Sjmallett * IPD_BIST_STATUS = IPD BIST STATUS 393215976Sjmallett * 394215976Sjmallett * BIST Status for IPD's Memories. 395215976Sjmallett */ 396215976Sjmallettunion cvmx_ipd_bist_status 397215976Sjmallett{ 398215976Sjmallett uint64_t u64; 399215976Sjmallett struct cvmx_ipd_bist_status_s 400215976Sjmallett { 401215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 402215976Sjmallett uint64_t reserved_18_63 : 46; 403215976Sjmallett uint64_t csr_mem : 1; /**< CSR Register Memory Bist Status. */ 404215976Sjmallett uint64_t csr_ncmd : 1; /**< CSR NCB Commands Memory Bist Status. */ 405215976Sjmallett uint64_t pwq_wqed : 1; /**< PWQ PIP WQE DONE Memory Bist Status. */ 406215976Sjmallett uint64_t pwq_wp1 : 1; /**< PWQ WQE PAGE1 PTR Memory Bist Status. */ 407215976Sjmallett uint64_t pwq_pow : 1; /**< PWQ POW MEM Memory Bist Status. */ 408215976Sjmallett uint64_t ipq_pbe1 : 1; /**< IPQ PBE1 Memory Bist Status. */ 409215976Sjmallett uint64_t ipq_pbe0 : 1; /**< IPQ PBE0 Memory Bist Status. */ 410215976Sjmallett uint64_t pbm3 : 1; /**< PBM3 Memory Bist Status. */ 411215976Sjmallett uint64_t pbm2 : 1; /**< PBM2 Memory Bist Status. */ 412215976Sjmallett uint64_t pbm1 : 1; /**< PBM1 Memory Bist Status. */ 413215976Sjmallett uint64_t pbm0 : 1; /**< PBM0 Memory Bist Status. */ 414215976Sjmallett uint64_t pbm_word : 1; /**< PBM_WORD Memory Bist Status. */ 415215976Sjmallett uint64_t pwq1 : 1; /**< PWQ1 Memory Bist Status. */ 416215976Sjmallett uint64_t pwq0 : 1; /**< PWQ0 Memory Bist Status. */ 417215976Sjmallett uint64_t prc_off : 1; /**< PRC_OFF Memory Bist Status. */ 418215976Sjmallett uint64_t ipd_old : 1; /**< IPD_OLD Memory Bist Status. */ 419215976Sjmallett uint64_t ipd_new : 1; /**< IPD_NEW Memory Bist Status. */ 420215976Sjmallett uint64_t pwp : 1; /**< PWP Memory Bist Status. */ 421215976Sjmallett#else 422215976Sjmallett uint64_t pwp : 1; 423215976Sjmallett uint64_t ipd_new : 1; 424215976Sjmallett uint64_t ipd_old : 1; 425215976Sjmallett uint64_t prc_off : 1; 426215976Sjmallett uint64_t pwq0 : 1; 427215976Sjmallett uint64_t pwq1 : 1; 428215976Sjmallett uint64_t pbm_word : 1; 429215976Sjmallett uint64_t pbm0 : 1; 430215976Sjmallett uint64_t pbm1 : 1; 431215976Sjmallett uint64_t pbm2 : 1; 432215976Sjmallett uint64_t pbm3 : 1; 433215976Sjmallett uint64_t ipq_pbe0 : 1; 434215976Sjmallett uint64_t ipq_pbe1 : 1; 435215976Sjmallett uint64_t pwq_pow : 1; 436215976Sjmallett uint64_t pwq_wp1 : 1; 437215976Sjmallett uint64_t pwq_wqed : 1; 438215976Sjmallett uint64_t csr_ncmd : 1; 439215976Sjmallett uint64_t csr_mem : 1; 440215976Sjmallett uint64_t reserved_18_63 : 46; 441215976Sjmallett#endif 442215976Sjmallett } s; 443215976Sjmallett struct cvmx_ipd_bist_status_cn30xx 444215976Sjmallett { 445215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 446215976Sjmallett uint64_t reserved_16_63 : 48; 447215976Sjmallett uint64_t pwq_wqed : 1; /**< PWQ PIP WQE DONE Memory Bist Status. */ 448215976Sjmallett uint64_t pwq_wp1 : 1; /**< PWQ WQE PAGE1 PTR Memory Bist Status. */ 449215976Sjmallett uint64_t pwq_pow : 1; /**< PWQ POW MEM Memory Bist Status. */ 450215976Sjmallett uint64_t ipq_pbe1 : 1; /**< IPQ PBE1 Memory Bist Status. */ 451215976Sjmallett uint64_t ipq_pbe0 : 1; /**< IPQ PBE0 Memory Bist Status. */ 452215976Sjmallett uint64_t pbm3 : 1; /**< PBM3 Memory Bist Status. */ 453215976Sjmallett uint64_t pbm2 : 1; /**< PBM2 Memory Bist Status. */ 454215976Sjmallett uint64_t pbm1 : 1; /**< PBM1 Memory Bist Status. */ 455215976Sjmallett uint64_t pbm0 : 1; /**< PBM0 Memory Bist Status. */ 456215976Sjmallett uint64_t pbm_word : 1; /**< PBM_WORD Memory Bist Status. */ 457215976Sjmallett uint64_t pwq1 : 1; /**< PWQ1 Memory Bist Status. */ 458215976Sjmallett uint64_t pwq0 : 1; /**< PWQ0 Memory Bist Status. */ 459215976Sjmallett uint64_t prc_off : 1; /**< PRC_OFF Memory Bist Status. */ 460215976Sjmallett uint64_t ipd_old : 1; /**< IPD_OLD Memory Bist Status. */ 461215976Sjmallett uint64_t ipd_new : 1; /**< IPD_NEW Memory Bist Status. */ 462215976Sjmallett uint64_t pwp : 1; /**< PWP Memory Bist Status. */ 463215976Sjmallett#else 464215976Sjmallett uint64_t pwp : 1; 465215976Sjmallett uint64_t ipd_new : 1; 466215976Sjmallett uint64_t ipd_old : 1; 467215976Sjmallett uint64_t prc_off : 1; 468215976Sjmallett uint64_t pwq0 : 1; 469215976Sjmallett uint64_t pwq1 : 1; 470215976Sjmallett uint64_t pbm_word : 1; 471215976Sjmallett uint64_t pbm0 : 1; 472215976Sjmallett uint64_t pbm1 : 1; 473215976Sjmallett uint64_t pbm2 : 1; 474215976Sjmallett uint64_t pbm3 : 1; 475215976Sjmallett uint64_t ipq_pbe0 : 1; 476215976Sjmallett uint64_t ipq_pbe1 : 1; 477215976Sjmallett uint64_t pwq_pow : 1; 478215976Sjmallett uint64_t pwq_wp1 : 1; 479215976Sjmallett uint64_t pwq_wqed : 1; 480215976Sjmallett uint64_t reserved_16_63 : 48; 481215976Sjmallett#endif 482215976Sjmallett } cn30xx; 483215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn31xx; 484215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn38xx; 485215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn38xxp2; 486215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn50xx; 487215976Sjmallett struct cvmx_ipd_bist_status_s cn52xx; 488215976Sjmallett struct cvmx_ipd_bist_status_s cn52xxp1; 489215976Sjmallett struct cvmx_ipd_bist_status_s cn56xx; 490215976Sjmallett struct cvmx_ipd_bist_status_s cn56xxp1; 491215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn58xx; 492215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn58xxp1; 493215976Sjmallett struct cvmx_ipd_bist_status_s cn63xx; 494215976Sjmallett struct cvmx_ipd_bist_status_s cn63xxp1; 495215976Sjmallett}; 496215976Sjmalletttypedef union cvmx_ipd_bist_status cvmx_ipd_bist_status_t; 497215976Sjmallett 498215976Sjmallett/** 499215976Sjmallett * cvmx_ipd_bp_prt_red_end 500215976Sjmallett * 501215976Sjmallett * IPD_BP_PRT_RED_END = IPD Backpressure Port RED Enable 502215976Sjmallett * 503215976Sjmallett * When IPD applies backpressure to a PORT and the corresponding bit in this register is set, 504215976Sjmallett * the RED Unit will drop packets for that port. 505215976Sjmallett */ 506215976Sjmallettunion cvmx_ipd_bp_prt_red_end 507215976Sjmallett{ 508215976Sjmallett uint64_t u64; 509215976Sjmallett struct cvmx_ipd_bp_prt_red_end_s 510215976Sjmallett { 511215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 512215976Sjmallett uint64_t reserved_44_63 : 20; 513215976Sjmallett uint64_t prt_enb : 44; /**< The port corresponding to the bit position in this 514215976Sjmallett field will drop all NON-RAW packets to that port 515215976Sjmallett when port level backpressure is applied to that 516215976Sjmallett port. The applying of port-level backpressure for 517215976Sjmallett this dropping does not take into consideration the 518215976Sjmallett value of IPD_PORTX_BP_PAGE_CNT[BP_ENB], nor 519215976Sjmallett IPD_RED_PORT_ENABLE[PRT_ENB]. */ 520215976Sjmallett#else 521215976Sjmallett uint64_t prt_enb : 44; 522215976Sjmallett uint64_t reserved_44_63 : 20; 523215976Sjmallett#endif 524215976Sjmallett } s; 525215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx 526215976Sjmallett { 527215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 528215976Sjmallett uint64_t reserved_36_63 : 28; 529215976Sjmallett uint64_t prt_enb : 36; /**< The port corresponding to the bit position in this 530215976Sjmallett field, will allow RED to drop back when port level 531215976Sjmallett backpressure is applied to the port. The applying 532215976Sjmallett of port-level backpressure for this RED dropping 533215976Sjmallett does not take into consideration the value of 534215976Sjmallett IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */ 535215976Sjmallett#else 536215976Sjmallett uint64_t prt_enb : 36; 537215976Sjmallett uint64_t reserved_36_63 : 28; 538215976Sjmallett#endif 539215976Sjmallett } cn30xx; 540215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx; 541215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx; 542215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2; 543215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx; 544215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn52xx 545215976Sjmallett { 546215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 547215976Sjmallett uint64_t reserved_40_63 : 24; 548215976Sjmallett uint64_t prt_enb : 40; /**< The port corresponding to the bit position in this 549215976Sjmallett field, will allow RED to drop back when port level 550215976Sjmallett backpressure is applied to the port. The applying 551215976Sjmallett of port-level backpressure for this RED dropping 552215976Sjmallett does not take into consideration the value of 553215976Sjmallett IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */ 554215976Sjmallett#else 555215976Sjmallett uint64_t prt_enb : 40; 556215976Sjmallett uint64_t reserved_40_63 : 24; 557215976Sjmallett#endif 558215976Sjmallett } cn52xx; 559215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1; 560215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx; 561215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1; 562215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx; 563215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1; 564215976Sjmallett struct cvmx_ipd_bp_prt_red_end_s cn63xx; 565215976Sjmallett struct cvmx_ipd_bp_prt_red_end_s cn63xxp1; 566215976Sjmallett}; 567215976Sjmalletttypedef union cvmx_ipd_bp_prt_red_end cvmx_ipd_bp_prt_red_end_t; 568215976Sjmallett 569215976Sjmallett/** 570215976Sjmallett * cvmx_ipd_clk_count 571215976Sjmallett * 572215976Sjmallett * IPD_CLK_COUNT = IPD Clock Count 573215976Sjmallett * 574215976Sjmallett * Counts the number of core clocks periods since the de-asserition of reset. 575215976Sjmallett */ 576215976Sjmallettunion cvmx_ipd_clk_count 577215976Sjmallett{ 578215976Sjmallett uint64_t u64; 579215976Sjmallett struct cvmx_ipd_clk_count_s 580215976Sjmallett { 581215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 582215976Sjmallett uint64_t clk_cnt : 64; /**< This counter will be zeroed when reset is applied 583215976Sjmallett and will increment every rising edge of the 584215976Sjmallett core-clock. */ 585215976Sjmallett#else 586215976Sjmallett uint64_t clk_cnt : 64; 587215976Sjmallett#endif 588215976Sjmallett } s; 589215976Sjmallett struct cvmx_ipd_clk_count_s cn30xx; 590215976Sjmallett struct cvmx_ipd_clk_count_s cn31xx; 591215976Sjmallett struct cvmx_ipd_clk_count_s cn38xx; 592215976Sjmallett struct cvmx_ipd_clk_count_s cn38xxp2; 593215976Sjmallett struct cvmx_ipd_clk_count_s cn50xx; 594215976Sjmallett struct cvmx_ipd_clk_count_s cn52xx; 595215976Sjmallett struct cvmx_ipd_clk_count_s cn52xxp1; 596215976Sjmallett struct cvmx_ipd_clk_count_s cn56xx; 597215976Sjmallett struct cvmx_ipd_clk_count_s cn56xxp1; 598215976Sjmallett struct cvmx_ipd_clk_count_s cn58xx; 599215976Sjmallett struct cvmx_ipd_clk_count_s cn58xxp1; 600215976Sjmallett struct cvmx_ipd_clk_count_s cn63xx; 601215976Sjmallett struct cvmx_ipd_clk_count_s cn63xxp1; 602215976Sjmallett}; 603215976Sjmalletttypedef union cvmx_ipd_clk_count cvmx_ipd_clk_count_t; 604215976Sjmallett 605215976Sjmallett/** 606215976Sjmallett * cvmx_ipd_ctl_status 607215976Sjmallett * 608215976Sjmallett * IPD_CTL_STATUS = IPD's Control Status Register 609215976Sjmallett * 610215976Sjmallett * The number of words in a MBUFF used for packet data store. 611215976Sjmallett */ 612215976Sjmallettunion cvmx_ipd_ctl_status 613215976Sjmallett{ 614215976Sjmallett uint64_t u64; 615215976Sjmallett struct cvmx_ipd_ctl_status_s 616215976Sjmallett { 617215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 618215976Sjmallett uint64_t reserved_18_63 : 46; 619215976Sjmallett uint64_t use_sop : 1; /**< When '1' the SOP sent by the MAC will be used in 620215976Sjmallett place of the SOP generated by the IPD. */ 621215976Sjmallett uint64_t rst_done : 1; /**< When '0' IPD has finished reset. No access 622215976Sjmallett except the reading of this bit should occur to the 623215976Sjmallett IPD until this is asserted. Or a 1000 core clock 624215976Sjmallett cycles has passed after the de-assertion of reset. */ 625215976Sjmallett uint64_t clken : 1; /**< Controls the conditional clocking within IPD 626215976Sjmallett 0=Allow HW to control the clocks 627215976Sjmallett 1=Force the clocks to be always on */ 628215976Sjmallett uint64_t no_wptr : 1; /**< When set '1' the WQE pointers will not be used and 629215976Sjmallett the WQE will be located at the front of the packet. 630215976Sjmallett When set: 631215976Sjmallett - IPD_WQE_FPA_QUEUE[WQE_QUE] is not used 632215976Sjmallett - IPD_1ST_MBUFF_SKIP[SKIP_SZ] must be at least 16 633215976Sjmallett - If 16 <= IPD_1ST_MBUFF_SKIP[SKIP_SZ] <= 31 then 634215976Sjmallett the WQE will be written into the first 128B 635215976Sjmallett cache block in the first buffer that contains 636215976Sjmallett the packet. 637215976Sjmallett - If IPD_1ST_MBUFF_SKIP[SKIP_SZ] == 32 then 638215976Sjmallett the WQE will be written into the second 128B 639215976Sjmallett cache block in the first buffer that contains 640215976Sjmallett the packet. */ 641215976Sjmallett uint64_t pq_apkt : 1; /**< When set IPD_PORT_QOS_X_CNT WILL be incremented 642215976Sjmallett by one for every work queue entry that is sent to 643215976Sjmallett POW. */ 644215976Sjmallett uint64_t pq_nabuf : 1; /**< When set IPD_PORT_QOS_X_CNT WILL NOT be 645215976Sjmallett incremented when IPD allocates a buffer for a 646215976Sjmallett packet. */ 647215976Sjmallett uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 648215976Sjmallett When set '1' the IPD drive the IPD_BUFF_FULL line to 649215976Sjmallett the IOB-arbiter, telling it to not give grants to 650215976Sjmallett NCB devices sending packet data. */ 651215976Sjmallett uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 652215976Sjmallett buffering the received packet data. When set '1' 653215976Sjmallett the IPD will not buffer the received packet data. */ 654215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 655215976Sjmallett data-length field in the header written to the 656215976Sjmallett POW and the top of a MBUFF. 657215976Sjmallett OCTEAN generates a length that includes the 658215976Sjmallett length of the data + 8 for the header-field. By 659215976Sjmallett setting this bit the 8 for the instr-field will 660215976Sjmallett not be included in the length field of the header. 661215976Sjmallett NOTE: IPD is compliant with the spec when this 662215976Sjmallett field is '1'. */ 663215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 664215976Sjmallett RSL. */ 665215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 666215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 667215976Sjmallett IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 668215976Sjmallett IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 669215976Sjmallett WILL be incremented by one for every work 670215976Sjmallett queue entry that is sent to POW. */ 671215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 672215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 673215976Sjmallett IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 674215976Sjmallett IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 675215976Sjmallett WILL NOT be incremented when IPD allocates a 676215976Sjmallett buffer for a packet on the port. */ 677215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 678215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 679215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 680215976Sjmallett the sending of port level backpressure to the 681215976Sjmallett Octane input-ports. The application should NOT 682215976Sjmallett de-assert this bit after asserting it. The 683215976Sjmallett receivers of this bit may have been put into 684215976Sjmallett backpressure mode and can only be released by 685215976Sjmallett IPD informing them that the backpressure has 686215976Sjmallett been released. 687215976Sjmallett GMXX_INF_MODE[EN] must be set to '1' for each 688215976Sjmallett packet interface which requires port back pressure 689215976Sjmallett prior to setting PBP_EN to '1'. */ 690215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 691215976Sjmallett is written through to memory. 692215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 693215976Sjmallett written into the cache. 694215976Sjmallett 2 ==> The first aligned cache block holding the 695215976Sjmallett packet data (and initial next buffer pointer) is 696215976Sjmallett written to the L2 cache, all remaining cache blocks 697215976Sjmallett are not written to the L2 cache. 698215976Sjmallett 3 ==> The first two aligned cache blocks holding 699215976Sjmallett the packet data (and initial next buffer pointer) 700215976Sjmallett are written to the L2 cache, all remaining cache 701215976Sjmallett blocks are not written to the L2 cache. */ 702215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 703215976Sjmallett When clear '0', the IPD will appear to the 704215976Sjmallett IOB-arbiter to be applying backpressure, this 705215976Sjmallett causes the IOB-Arbiter to not send grants to NCB 706215976Sjmallett devices requesting to send packet data to the IPD. */ 707215976Sjmallett#else 708215976Sjmallett uint64_t ipd_en : 1; 709215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 710215976Sjmallett uint64_t pbp_en : 1; 711215976Sjmallett uint64_t wqe_lend : 1; 712215976Sjmallett uint64_t pkt_lend : 1; 713215976Sjmallett uint64_t naddbuf : 1; 714215976Sjmallett uint64_t addpkt : 1; 715215976Sjmallett uint64_t reset : 1; 716215976Sjmallett uint64_t len_m8 : 1; 717215976Sjmallett uint64_t pkt_off : 1; 718215976Sjmallett uint64_t ipd_full : 1; 719215976Sjmallett uint64_t pq_nabuf : 1; 720215976Sjmallett uint64_t pq_apkt : 1; 721215976Sjmallett uint64_t no_wptr : 1; 722215976Sjmallett uint64_t clken : 1; 723215976Sjmallett uint64_t rst_done : 1; 724215976Sjmallett uint64_t use_sop : 1; 725215976Sjmallett uint64_t reserved_18_63 : 46; 726215976Sjmallett#endif 727215976Sjmallett } s; 728215976Sjmallett struct cvmx_ipd_ctl_status_cn30xx 729215976Sjmallett { 730215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 731215976Sjmallett uint64_t reserved_10_63 : 54; 732215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 733215976Sjmallett data-length field in the header written wo the 734215976Sjmallett POW and the top of a MBUFF. 735215976Sjmallett OCTEAN generates a length that includes the 736215976Sjmallett length of the data + 8 for the header-field. By 737215976Sjmallett setting this bit the 8 for the instr-field will 738215976Sjmallett not be included in the length field of the header. 739215976Sjmallett NOTE: IPD is compliant with the spec when this 740215976Sjmallett field is '1'. */ 741215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 742215976Sjmallett RSL. */ 743215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 744215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 745215976Sjmallett WILL be incremented by one for every work 746215976Sjmallett queue entry that is sent to POW. */ 747215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 748215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 749215976Sjmallett WILL NOT be incremented when IPD allocates a 750215976Sjmallett buffer for a packet on the port. */ 751215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 752215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 753215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 754215976Sjmallett the sending of port level backpressure to the 755215976Sjmallett Octane input-ports. Once enabled the sending of 756215976Sjmallett port-level-backpressure can not be disabled by 757215976Sjmallett changing the value of this bit. 758215976Sjmallett GMXX_INF_MODE[EN] must be set to '1' for each 759215976Sjmallett packet interface which requires port back pressure 760215976Sjmallett prior to setting PBP_EN to '1'. */ 761215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 762215976Sjmallett is written through to memory. 763215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 764215976Sjmallett written into the cache. 765215976Sjmallett 2 ==> The first aligned cache block holding the 766215976Sjmallett packet data (and initial next buffer pointer) is 767215976Sjmallett written to the L2 cache, all remaining cache blocks 768215976Sjmallett are not written to the L2 cache. 769215976Sjmallett 3 ==> The first two aligned cache blocks holding 770215976Sjmallett the packet data (and initial next buffer pointer) 771215976Sjmallett are written to the L2 cache, all remaining cache 772215976Sjmallett blocks are not written to the L2 cache. */ 773215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. */ 774215976Sjmallett#else 775215976Sjmallett uint64_t ipd_en : 1; 776215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 777215976Sjmallett uint64_t pbp_en : 1; 778215976Sjmallett uint64_t wqe_lend : 1; 779215976Sjmallett uint64_t pkt_lend : 1; 780215976Sjmallett uint64_t naddbuf : 1; 781215976Sjmallett uint64_t addpkt : 1; 782215976Sjmallett uint64_t reset : 1; 783215976Sjmallett uint64_t len_m8 : 1; 784215976Sjmallett uint64_t reserved_10_63 : 54; 785215976Sjmallett#endif 786215976Sjmallett } cn30xx; 787215976Sjmallett struct cvmx_ipd_ctl_status_cn30xx cn31xx; 788215976Sjmallett struct cvmx_ipd_ctl_status_cn30xx cn38xx; 789215976Sjmallett struct cvmx_ipd_ctl_status_cn38xxp2 790215976Sjmallett { 791215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 792215976Sjmallett uint64_t reserved_9_63 : 55; 793215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 794215976Sjmallett RSL. */ 795215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 796215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 797215976Sjmallett WILL be incremented by one for every work 798215976Sjmallett queue entry that is sent to POW. 799215976Sjmallett PASS-2 Field. */ 800215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 801215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 802215976Sjmallett WILL NOT be incremented when IPD allocates a 803215976Sjmallett buffer for a packet on the port. 804215976Sjmallett PASS-2 Field. */ 805215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 806215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 807215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 808215976Sjmallett the sending of port level backpressure to the 809215976Sjmallett Octane input-ports. Once enabled the sending of 810215976Sjmallett port-level-backpressure can not be disabled by 811215976Sjmallett changing the value of this bit. */ 812215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 813215976Sjmallett is written through to memory. 814215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 815215976Sjmallett written into the cache. 816215976Sjmallett 2 ==> The first aligned cache block holding the 817215976Sjmallett packet data (and initial next buffer pointer) is 818215976Sjmallett written to the L2 cache, all remaining cache blocks 819215976Sjmallett are not written to the L2 cache. 820215976Sjmallett 3 ==> The first two aligned cache blocks holding 821215976Sjmallett the packet data (and initial next buffer pointer) 822215976Sjmallett are written to the L2 cache, all remaining cache 823215976Sjmallett blocks are not written to the L2 cache. */ 824215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. */ 825215976Sjmallett#else 826215976Sjmallett uint64_t ipd_en : 1; 827215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 828215976Sjmallett uint64_t pbp_en : 1; 829215976Sjmallett uint64_t wqe_lend : 1; 830215976Sjmallett uint64_t pkt_lend : 1; 831215976Sjmallett uint64_t naddbuf : 1; 832215976Sjmallett uint64_t addpkt : 1; 833215976Sjmallett uint64_t reset : 1; 834215976Sjmallett uint64_t reserved_9_63 : 55; 835215976Sjmallett#endif 836215976Sjmallett } cn38xxp2; 837215976Sjmallett struct cvmx_ipd_ctl_status_cn50xx 838215976Sjmallett { 839215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 840215976Sjmallett uint64_t reserved_15_63 : 49; 841215976Sjmallett uint64_t no_wptr : 1; /**< When set '1' the WQE pointers will not be used and 842215976Sjmallett the WQE will be located at the front of the packet. */ 843215976Sjmallett uint64_t pq_apkt : 1; /**< Reserved. */ 844215976Sjmallett uint64_t pq_nabuf : 1; /**< Reserved. */ 845215976Sjmallett uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 846215976Sjmallett When set '1' the IPD drive the IPD_BUFF_FULL line to 847215976Sjmallett the IOB-arbiter, telling it to not give grants to 848215976Sjmallett NCB devices sending packet data. */ 849215976Sjmallett uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 850215976Sjmallett buffering the received packet data. When set '1' 851215976Sjmallett the IPD will not buffer the received packet data. */ 852215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 853215976Sjmallett data-length field in the header written wo the 854215976Sjmallett POW and the top of a MBUFF. 855215976Sjmallett OCTEAN generates a length that includes the 856215976Sjmallett length of the data + 8 for the header-field. By 857215976Sjmallett setting this bit the 8 for the instr-field will 858215976Sjmallett not be included in the length field of the header. 859215976Sjmallett NOTE: IPD is compliant with the spec when this 860215976Sjmallett field is '1'. */ 861215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 862215976Sjmallett RSL. */ 863215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 864215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 865215976Sjmallett WILL be incremented by one for every work 866215976Sjmallett queue entry that is sent to POW. */ 867215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 868215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 869215976Sjmallett WILL NOT be incremented when IPD allocates a 870215976Sjmallett buffer for a packet on the port. */ 871215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 872215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 873215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 874215976Sjmallett the sending of port level backpressure to the 875215976Sjmallett Octane input-ports. Once enabled the sending of 876215976Sjmallett port-level-backpressure can not be disabled by 877215976Sjmallett changing the value of this bit. 878215976Sjmallett GMXX_INF_MODE[EN] must be set to '1' for each 879215976Sjmallett packet interface which requires port back pressure 880215976Sjmallett prior to setting PBP_EN to '1'. */ 881215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 882215976Sjmallett is written through to memory. 883215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 884215976Sjmallett written into the cache. 885215976Sjmallett 2 ==> The first aligned cache block holding the 886215976Sjmallett packet data (and initial next buffer pointer) is 887215976Sjmallett written to the L2 cache, all remaining cache blocks 888215976Sjmallett are not written to the L2 cache. 889215976Sjmallett 3 ==> The first two aligned cache blocks holding 890215976Sjmallett the packet data (and initial next buffer pointer) 891215976Sjmallett are written to the L2 cache, all remaining cache 892215976Sjmallett blocks are not written to the L2 cache. */ 893215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 894215976Sjmallett When clear '0', the IPD will appear to the 895215976Sjmallett IOB-arbiter to be applying backpressure, this 896215976Sjmallett causes the IOB-Arbiter to not send grants to NCB 897215976Sjmallett devices requesting to send packet data to the IPD. */ 898215976Sjmallett#else 899215976Sjmallett uint64_t ipd_en : 1; 900215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 901215976Sjmallett uint64_t pbp_en : 1; 902215976Sjmallett uint64_t wqe_lend : 1; 903215976Sjmallett uint64_t pkt_lend : 1; 904215976Sjmallett uint64_t naddbuf : 1; 905215976Sjmallett uint64_t addpkt : 1; 906215976Sjmallett uint64_t reset : 1; 907215976Sjmallett uint64_t len_m8 : 1; 908215976Sjmallett uint64_t pkt_off : 1; 909215976Sjmallett uint64_t ipd_full : 1; 910215976Sjmallett uint64_t pq_nabuf : 1; 911215976Sjmallett uint64_t pq_apkt : 1; 912215976Sjmallett uint64_t no_wptr : 1; 913215976Sjmallett uint64_t reserved_15_63 : 49; 914215976Sjmallett#endif 915215976Sjmallett } cn50xx; 916215976Sjmallett struct cvmx_ipd_ctl_status_cn50xx cn52xx; 917215976Sjmallett struct cvmx_ipd_ctl_status_cn50xx cn52xxp1; 918215976Sjmallett struct cvmx_ipd_ctl_status_cn50xx cn56xx; 919215976Sjmallett struct cvmx_ipd_ctl_status_cn50xx cn56xxp1; 920215976Sjmallett struct cvmx_ipd_ctl_status_cn58xx 921215976Sjmallett { 922215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 923215976Sjmallett uint64_t reserved_12_63 : 52; 924215976Sjmallett uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 925215976Sjmallett When set '1' the IPD drive the IPD_BUFF_FULL line to 926215976Sjmallett the IOB-arbiter, telling it to not give grants to 927215976Sjmallett NCB devices sending packet data. */ 928215976Sjmallett uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 929215976Sjmallett buffering the received packet data. When set '1' 930215976Sjmallett the IPD will not buffer the received packet data. */ 931215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 932215976Sjmallett data-length field in the header written wo the 933215976Sjmallett POW and the top of a MBUFF. 934215976Sjmallett OCTEAN PASS2 generates a length that includes the 935215976Sjmallett length of the data + 8 for the header-field. By 936215976Sjmallett setting this bit the 8 for the instr-field will 937215976Sjmallett not be included in the length field of the header. 938215976Sjmallett NOTE: IPD is compliant with the spec when this 939215976Sjmallett field is '1'. */ 940215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 941215976Sjmallett RSL. */ 942215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 943215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 944215976Sjmallett WILL be incremented by one for every work 945215976Sjmallett queue entry that is sent to POW. 946215976Sjmallett PASS-2 Field. */ 947215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 948215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 949215976Sjmallett WILL NOT be incremented when IPD allocates a 950215976Sjmallett buffer for a packet on the port. 951215976Sjmallett PASS-2 Field. */ 952215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 953215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 954215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 955215976Sjmallett the sending of port level backpressure to the 956215976Sjmallett Octane input-ports. Once enabled the sending of 957215976Sjmallett port-level-backpressure can not be disabled by 958215976Sjmallett changing the value of this bit. */ 959215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 960215976Sjmallett is written through to memory. 961215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 962215976Sjmallett written into the cache. 963215976Sjmallett 2 ==> The first aligned cache block holding the 964215976Sjmallett packet data (and initial next buffer pointer) is 965215976Sjmallett written to the L2 cache, all remaining cache blocks 966215976Sjmallett are not written to the L2 cache. 967215976Sjmallett 3 ==> The first two aligned cache blocks holding 968215976Sjmallett the packet data (and initial next buffer pointer) 969215976Sjmallett are written to the L2 cache, all remaining cache 970215976Sjmallett blocks are not written to the L2 cache. */ 971215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 972215976Sjmallett When clear '0', the IPD will appear to the 973215976Sjmallett IOB-arbiter to be applying backpressure, this 974215976Sjmallett causes the IOB-Arbiter to not send grants to NCB 975215976Sjmallett devices requesting to send packet data to the IPD. */ 976215976Sjmallett#else 977215976Sjmallett uint64_t ipd_en : 1; 978215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 979215976Sjmallett uint64_t pbp_en : 1; 980215976Sjmallett uint64_t wqe_lend : 1; 981215976Sjmallett uint64_t pkt_lend : 1; 982215976Sjmallett uint64_t naddbuf : 1; 983215976Sjmallett uint64_t addpkt : 1; 984215976Sjmallett uint64_t reset : 1; 985215976Sjmallett uint64_t len_m8 : 1; 986215976Sjmallett uint64_t pkt_off : 1; 987215976Sjmallett uint64_t ipd_full : 1; 988215976Sjmallett uint64_t reserved_12_63 : 52; 989215976Sjmallett#endif 990215976Sjmallett } cn58xx; 991215976Sjmallett struct cvmx_ipd_ctl_status_cn58xx cn58xxp1; 992215976Sjmallett struct cvmx_ipd_ctl_status_s cn63xx; 993215976Sjmallett struct cvmx_ipd_ctl_status_cn63xxp1 994215976Sjmallett { 995215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 996215976Sjmallett uint64_t reserved_16_63 : 48; 997215976Sjmallett uint64_t clken : 1; /**< Controls the conditional clocking within IPD 998215976Sjmallett 0=Allow HW to control the clocks 999215976Sjmallett 1=Force the clocks to be always on */ 1000215976Sjmallett uint64_t no_wptr : 1; /**< When set '1' the WQE pointers will not be used and 1001215976Sjmallett the WQE will be located at the front of the packet. 1002215976Sjmallett When set: 1003215976Sjmallett - IPD_WQE_FPA_QUEUE[WQE_QUE] is not used 1004215976Sjmallett - IPD_1ST_MBUFF_SKIP[SKIP_SZ] must be at least 16 1005215976Sjmallett - If 16 <= IPD_1ST_MBUFF_SKIP[SKIP_SZ] <= 31 then 1006215976Sjmallett the WQE will be written into the first 128B 1007215976Sjmallett cache block in the first buffer that contains 1008215976Sjmallett the packet. 1009215976Sjmallett - If IPD_1ST_MBUFF_SKIP[SKIP_SZ] == 32 then 1010215976Sjmallett the WQE will be written into the second 128B 1011215976Sjmallett cache block in the first buffer that contains 1012215976Sjmallett the packet. */ 1013215976Sjmallett uint64_t pq_apkt : 1; /**< When set IPD_PORT_QOS_X_CNT WILL be incremented 1014215976Sjmallett by one for every work queue entry that is sent to 1015215976Sjmallett POW. */ 1016215976Sjmallett uint64_t pq_nabuf : 1; /**< When set IPD_PORT_QOS_X_CNT WILL NOT be 1017215976Sjmallett incremented when IPD allocates a buffer for a 1018215976Sjmallett packet. */ 1019215976Sjmallett uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 1020215976Sjmallett When set '1' the IPD drive the IPD_BUFF_FULL line to 1021215976Sjmallett the IOB-arbiter, telling it to not give grants to 1022215976Sjmallett NCB devices sending packet data. */ 1023215976Sjmallett uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 1024215976Sjmallett buffering the received packet data. When set '1' 1025215976Sjmallett the IPD will not buffer the received packet data. */ 1026215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1027215976Sjmallett data-length field in the header written to the 1028215976Sjmallett POW and the top of a MBUFF. 1029215976Sjmallett OCTEAN generates a length that includes the 1030215976Sjmallett length of the data + 8 for the header-field. By 1031215976Sjmallett setting this bit the 8 for the instr-field will 1032215976Sjmallett not be included in the length field of the header. 1033215976Sjmallett NOTE: IPD is compliant with the spec when this 1034215976Sjmallett field is '1'. */ 1035215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1036215976Sjmallett RSL. */ 1037215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1038215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1039215976Sjmallett IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1040215976Sjmallett IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1041215976Sjmallett WILL be incremented by one for every work 1042215976Sjmallett queue entry that is sent to POW. */ 1043215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1044215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1045215976Sjmallett IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1046215976Sjmallett IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1047215976Sjmallett WILL NOT be incremented when IPD allocates a 1048215976Sjmallett buffer for a packet on the port. */ 1049215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1050215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1051215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1052215976Sjmallett the sending of port level backpressure to the 1053215976Sjmallett Octane input-ports. The application should NOT 1054215976Sjmallett de-assert this bit after asserting it. The 1055215976Sjmallett receivers of this bit may have been put into 1056215976Sjmallett backpressure mode and can only be released by 1057215976Sjmallett IPD informing them that the backpressure has 1058215976Sjmallett been released. 1059215976Sjmallett GMXX_INF_MODE[EN] must be set to '1' for each 1060215976Sjmallett packet interface which requires port back pressure 1061215976Sjmallett prior to setting PBP_EN to '1'. */ 1062215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1063215976Sjmallett is written through to memory. 1064215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 1065215976Sjmallett written into the cache. 1066215976Sjmallett 2 ==> The first aligned cache block holding the 1067215976Sjmallett packet data (and initial next buffer pointer) is 1068215976Sjmallett written to the L2 cache, all remaining cache blocks 1069215976Sjmallett are not written to the L2 cache. 1070215976Sjmallett 3 ==> The first two aligned cache blocks holding 1071215976Sjmallett the packet data (and initial next buffer pointer) 1072215976Sjmallett are written to the L2 cache, all remaining cache 1073215976Sjmallett blocks are not written to the L2 cache. */ 1074215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 1075215976Sjmallett When clear '0', the IPD will appear to the 1076215976Sjmallett IOB-arbiter to be applying backpressure, this 1077215976Sjmallett causes the IOB-Arbiter to not send grants to NCB 1078215976Sjmallett devices requesting to send packet data to the IPD. */ 1079215976Sjmallett#else 1080215976Sjmallett uint64_t ipd_en : 1; 1081215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 1082215976Sjmallett uint64_t pbp_en : 1; 1083215976Sjmallett uint64_t wqe_lend : 1; 1084215976Sjmallett uint64_t pkt_lend : 1; 1085215976Sjmallett uint64_t naddbuf : 1; 1086215976Sjmallett uint64_t addpkt : 1; 1087215976Sjmallett uint64_t reset : 1; 1088215976Sjmallett uint64_t len_m8 : 1; 1089215976Sjmallett uint64_t pkt_off : 1; 1090215976Sjmallett uint64_t ipd_full : 1; 1091215976Sjmallett uint64_t pq_nabuf : 1; 1092215976Sjmallett uint64_t pq_apkt : 1; 1093215976Sjmallett uint64_t no_wptr : 1; 1094215976Sjmallett uint64_t clken : 1; 1095215976Sjmallett uint64_t reserved_16_63 : 48; 1096215976Sjmallett#endif 1097215976Sjmallett } cn63xxp1; 1098215976Sjmallett}; 1099215976Sjmalletttypedef union cvmx_ipd_ctl_status cvmx_ipd_ctl_status_t; 1100215976Sjmallett 1101215976Sjmallett/** 1102215976Sjmallett * cvmx_ipd_int_enb 1103215976Sjmallett * 1104215976Sjmallett * IPD_INTERRUPT_ENB = IPD Interrupt Enable Register 1105215976Sjmallett * 1106215976Sjmallett * Used to enable the various interrupting conditions of IPD 1107215976Sjmallett */ 1108215976Sjmallettunion cvmx_ipd_int_enb 1109215976Sjmallett{ 1110215976Sjmallett uint64_t u64; 1111215976Sjmallett struct cvmx_ipd_int_enb_s 1112215976Sjmallett { 1113215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1114215976Sjmallett uint64_t reserved_12_63 : 52; 1115215976Sjmallett uint64_t pq_sub : 1; /**< Allows an interrupt to be sent when the 1116215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1117215976Sjmallett uint64_t pq_add : 1; /**< Allows an interrupt to be sent when the 1118215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1119215976Sjmallett uint64_t bc_ovr : 1; /**< Allows an interrupt to be sent when the 1120215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1121215976Sjmallett uint64_t d_coll : 1; /**< Allows an interrupt to be sent when the 1122215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1123215976Sjmallett uint64_t c_coll : 1; /**< Allows an interrupt to be sent when the 1124215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1125215976Sjmallett uint64_t cc_ovr : 1; /**< Allows an interrupt to be sent when the 1126215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1127215976Sjmallett uint64_t dc_ovr : 1; /**< Allows an interrupt to be sent when the 1128215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1129215976Sjmallett uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1130215976Sjmallett has an illegal value. */ 1131215976Sjmallett uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1132215976Sjmallett [127:96] of the PBM memory. */ 1133215976Sjmallett uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1134215976Sjmallett [95:64] of the PBM memory. */ 1135215976Sjmallett uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1136215976Sjmallett [63:32] of the PBM memory. */ 1137215976Sjmallett uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1138215976Sjmallett [31:0] of the PBM memory. */ 1139215976Sjmallett#else 1140215976Sjmallett uint64_t prc_par0 : 1; 1141215976Sjmallett uint64_t prc_par1 : 1; 1142215976Sjmallett uint64_t prc_par2 : 1; 1143215976Sjmallett uint64_t prc_par3 : 1; 1144215976Sjmallett uint64_t bp_sub : 1; 1145215976Sjmallett uint64_t dc_ovr : 1; 1146215976Sjmallett uint64_t cc_ovr : 1; 1147215976Sjmallett uint64_t c_coll : 1; 1148215976Sjmallett uint64_t d_coll : 1; 1149215976Sjmallett uint64_t bc_ovr : 1; 1150215976Sjmallett uint64_t pq_add : 1; 1151215976Sjmallett uint64_t pq_sub : 1; 1152215976Sjmallett uint64_t reserved_12_63 : 52; 1153215976Sjmallett#endif 1154215976Sjmallett } s; 1155215976Sjmallett struct cvmx_ipd_int_enb_cn30xx 1156215976Sjmallett { 1157215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1158215976Sjmallett uint64_t reserved_5_63 : 59; 1159215976Sjmallett uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1160215976Sjmallett has an illegal value. */ 1161215976Sjmallett uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1162215976Sjmallett [127:96] of the PBM memory. */ 1163215976Sjmallett uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1164215976Sjmallett [95:64] of the PBM memory. */ 1165215976Sjmallett uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1166215976Sjmallett [63:32] of the PBM memory. */ 1167215976Sjmallett uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1168215976Sjmallett [31:0] of the PBM memory. */ 1169215976Sjmallett#else 1170215976Sjmallett uint64_t prc_par0 : 1; 1171215976Sjmallett uint64_t prc_par1 : 1; 1172215976Sjmallett uint64_t prc_par2 : 1; 1173215976Sjmallett uint64_t prc_par3 : 1; 1174215976Sjmallett uint64_t bp_sub : 1; 1175215976Sjmallett uint64_t reserved_5_63 : 59; 1176215976Sjmallett#endif 1177215976Sjmallett } cn30xx; 1178215976Sjmallett struct cvmx_ipd_int_enb_cn30xx cn31xx; 1179215976Sjmallett struct cvmx_ipd_int_enb_cn38xx 1180215976Sjmallett { 1181215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1182215976Sjmallett uint64_t reserved_10_63 : 54; 1183215976Sjmallett uint64_t bc_ovr : 1; /**< Allows an interrupt to be sent when the 1184215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1185215976Sjmallett This is a PASS-3 Field. */ 1186215976Sjmallett uint64_t d_coll : 1; /**< Allows an interrupt to be sent when the 1187215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1188215976Sjmallett This is a PASS-3 Field. */ 1189215976Sjmallett uint64_t c_coll : 1; /**< Allows an interrupt to be sent when the 1190215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1191215976Sjmallett This is a PASS-3 Field. */ 1192215976Sjmallett uint64_t cc_ovr : 1; /**< Allows an interrupt to be sent when the 1193215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1194215976Sjmallett This is a PASS-3 Field. */ 1195215976Sjmallett uint64_t dc_ovr : 1; /**< Allows an interrupt to be sent when the 1196215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1197215976Sjmallett This is a PASS-3 Field. */ 1198215976Sjmallett uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1199215976Sjmallett has an illegal value. */ 1200215976Sjmallett uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1201215976Sjmallett [127:96] of the PBM memory. */ 1202215976Sjmallett uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1203215976Sjmallett [95:64] of the PBM memory. */ 1204215976Sjmallett uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1205215976Sjmallett [63:32] of the PBM memory. */ 1206215976Sjmallett uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1207215976Sjmallett [31:0] of the PBM memory. */ 1208215976Sjmallett#else 1209215976Sjmallett uint64_t prc_par0 : 1; 1210215976Sjmallett uint64_t prc_par1 : 1; 1211215976Sjmallett uint64_t prc_par2 : 1; 1212215976Sjmallett uint64_t prc_par3 : 1; 1213215976Sjmallett uint64_t bp_sub : 1; 1214215976Sjmallett uint64_t dc_ovr : 1; 1215215976Sjmallett uint64_t cc_ovr : 1; 1216215976Sjmallett uint64_t c_coll : 1; 1217215976Sjmallett uint64_t d_coll : 1; 1218215976Sjmallett uint64_t bc_ovr : 1; 1219215976Sjmallett uint64_t reserved_10_63 : 54; 1220215976Sjmallett#endif 1221215976Sjmallett } cn38xx; 1222215976Sjmallett struct cvmx_ipd_int_enb_cn30xx cn38xxp2; 1223215976Sjmallett struct cvmx_ipd_int_enb_cn38xx cn50xx; 1224215976Sjmallett struct cvmx_ipd_int_enb_s cn52xx; 1225215976Sjmallett struct cvmx_ipd_int_enb_s cn52xxp1; 1226215976Sjmallett struct cvmx_ipd_int_enb_s cn56xx; 1227215976Sjmallett struct cvmx_ipd_int_enb_s cn56xxp1; 1228215976Sjmallett struct cvmx_ipd_int_enb_cn38xx cn58xx; 1229215976Sjmallett struct cvmx_ipd_int_enb_cn38xx cn58xxp1; 1230215976Sjmallett struct cvmx_ipd_int_enb_s cn63xx; 1231215976Sjmallett struct cvmx_ipd_int_enb_s cn63xxp1; 1232215976Sjmallett}; 1233215976Sjmalletttypedef union cvmx_ipd_int_enb cvmx_ipd_int_enb_t; 1234215976Sjmallett 1235215976Sjmallett/** 1236215976Sjmallett * cvmx_ipd_int_sum 1237215976Sjmallett * 1238215976Sjmallett * IPD_INTERRUPT_SUM = IPD Interrupt Summary Register 1239215976Sjmallett * 1240215976Sjmallett * Set when an interrupt condition occurs, write '1' to clear. 1241215976Sjmallett */ 1242215976Sjmallettunion cvmx_ipd_int_sum 1243215976Sjmallett{ 1244215976Sjmallett uint64_t u64; 1245215976Sjmallett struct cvmx_ipd_int_sum_s 1246215976Sjmallett { 1247215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1248215976Sjmallett uint64_t reserved_12_63 : 52; 1249215976Sjmallett uint64_t pq_sub : 1; /**< Set when a port-qos does an sub to the count 1250215976Sjmallett that causes the counter to wrap. */ 1251215976Sjmallett uint64_t pq_add : 1; /**< Set when a port-qos does an add to the count 1252215976Sjmallett that causes the counter to wrap. */ 1253215976Sjmallett uint64_t bc_ovr : 1; /**< Set when the byte-count to send to IOB overflows. */ 1254215976Sjmallett uint64_t d_coll : 1; /**< Set when the packet/WQE data to be sent to IOB 1255215976Sjmallett collides. */ 1256215976Sjmallett uint64_t c_coll : 1; /**< Set when the packet/WQE commands to be sent to IOB 1257215976Sjmallett collides. */ 1258215976Sjmallett uint64_t cc_ovr : 1; /**< Set when the command credits to the IOB overflow. */ 1259215976Sjmallett uint64_t dc_ovr : 1; /**< Set when the data credits to the IOB overflow. */ 1260215976Sjmallett uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 1261215976Sjmallett supplied illegal value. */ 1262215976Sjmallett uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 1263215976Sjmallett [127:96] of the PBM memory. */ 1264215976Sjmallett uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 1265215976Sjmallett [95:64] of the PBM memory. */ 1266215976Sjmallett uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 1267215976Sjmallett [63:32] of the PBM memory. */ 1268215976Sjmallett uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 1269215976Sjmallett [31:0] of the PBM memory. */ 1270215976Sjmallett#else 1271215976Sjmallett uint64_t prc_par0 : 1; 1272215976Sjmallett uint64_t prc_par1 : 1; 1273215976Sjmallett uint64_t prc_par2 : 1; 1274215976Sjmallett uint64_t prc_par3 : 1; 1275215976Sjmallett uint64_t bp_sub : 1; 1276215976Sjmallett uint64_t dc_ovr : 1; 1277215976Sjmallett uint64_t cc_ovr : 1; 1278215976Sjmallett uint64_t c_coll : 1; 1279215976Sjmallett uint64_t d_coll : 1; 1280215976Sjmallett uint64_t bc_ovr : 1; 1281215976Sjmallett uint64_t pq_add : 1; 1282215976Sjmallett uint64_t pq_sub : 1; 1283215976Sjmallett uint64_t reserved_12_63 : 52; 1284215976Sjmallett#endif 1285215976Sjmallett } s; 1286215976Sjmallett struct cvmx_ipd_int_sum_cn30xx 1287215976Sjmallett { 1288215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1289215976Sjmallett uint64_t reserved_5_63 : 59; 1290215976Sjmallett uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 1291215976Sjmallett supplied illegal value. */ 1292215976Sjmallett uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 1293215976Sjmallett [127:96] of the PBM memory. */ 1294215976Sjmallett uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 1295215976Sjmallett [95:64] of the PBM memory. */ 1296215976Sjmallett uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 1297215976Sjmallett [63:32] of the PBM memory. */ 1298215976Sjmallett uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 1299215976Sjmallett [31:0] of the PBM memory. */ 1300215976Sjmallett#else 1301215976Sjmallett uint64_t prc_par0 : 1; 1302215976Sjmallett uint64_t prc_par1 : 1; 1303215976Sjmallett uint64_t prc_par2 : 1; 1304215976Sjmallett uint64_t prc_par3 : 1; 1305215976Sjmallett uint64_t bp_sub : 1; 1306215976Sjmallett uint64_t reserved_5_63 : 59; 1307215976Sjmallett#endif 1308215976Sjmallett } cn30xx; 1309215976Sjmallett struct cvmx_ipd_int_sum_cn30xx cn31xx; 1310215976Sjmallett struct cvmx_ipd_int_sum_cn38xx 1311215976Sjmallett { 1312215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1313215976Sjmallett uint64_t reserved_10_63 : 54; 1314215976Sjmallett uint64_t bc_ovr : 1; /**< Set when the byte-count to send to IOB overflows. 1315215976Sjmallett This is a PASS-3 Field. */ 1316215976Sjmallett uint64_t d_coll : 1; /**< Set when the packet/WQE data to be sent to IOB 1317215976Sjmallett collides. 1318215976Sjmallett This is a PASS-3 Field. */ 1319215976Sjmallett uint64_t c_coll : 1; /**< Set when the packet/WQE commands to be sent to IOB 1320215976Sjmallett collides. 1321215976Sjmallett This is a PASS-3 Field. */ 1322215976Sjmallett uint64_t cc_ovr : 1; /**< Set when the command credits to the IOB overflow. 1323215976Sjmallett This is a PASS-3 Field. */ 1324215976Sjmallett uint64_t dc_ovr : 1; /**< Set when the data credits to the IOB overflow. 1325215976Sjmallett This is a PASS-3 Field. */ 1326215976Sjmallett uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 1327215976Sjmallett supplied illegal value. */ 1328215976Sjmallett uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 1329215976Sjmallett [127:96] of the PBM memory. */ 1330215976Sjmallett uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 1331215976Sjmallett [95:64] of the PBM memory. */ 1332215976Sjmallett uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 1333215976Sjmallett [63:32] of the PBM memory. */ 1334215976Sjmallett uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 1335215976Sjmallett [31:0] of the PBM memory. */ 1336215976Sjmallett#else 1337215976Sjmallett uint64_t prc_par0 : 1; 1338215976Sjmallett uint64_t prc_par1 : 1; 1339215976Sjmallett uint64_t prc_par2 : 1; 1340215976Sjmallett uint64_t prc_par3 : 1; 1341215976Sjmallett uint64_t bp_sub : 1; 1342215976Sjmallett uint64_t dc_ovr : 1; 1343215976Sjmallett uint64_t cc_ovr : 1; 1344215976Sjmallett uint64_t c_coll : 1; 1345215976Sjmallett uint64_t d_coll : 1; 1346215976Sjmallett uint64_t bc_ovr : 1; 1347215976Sjmallett uint64_t reserved_10_63 : 54; 1348215976Sjmallett#endif 1349215976Sjmallett } cn38xx; 1350215976Sjmallett struct cvmx_ipd_int_sum_cn30xx cn38xxp2; 1351215976Sjmallett struct cvmx_ipd_int_sum_cn38xx cn50xx; 1352215976Sjmallett struct cvmx_ipd_int_sum_s cn52xx; 1353215976Sjmallett struct cvmx_ipd_int_sum_s cn52xxp1; 1354215976Sjmallett struct cvmx_ipd_int_sum_s cn56xx; 1355215976Sjmallett struct cvmx_ipd_int_sum_s cn56xxp1; 1356215976Sjmallett struct cvmx_ipd_int_sum_cn38xx cn58xx; 1357215976Sjmallett struct cvmx_ipd_int_sum_cn38xx cn58xxp1; 1358215976Sjmallett struct cvmx_ipd_int_sum_s cn63xx; 1359215976Sjmallett struct cvmx_ipd_int_sum_s cn63xxp1; 1360215976Sjmallett}; 1361215976Sjmalletttypedef union cvmx_ipd_int_sum cvmx_ipd_int_sum_t; 1362215976Sjmallett 1363215976Sjmallett/** 1364215976Sjmallett * cvmx_ipd_not_1st_mbuff_skip 1365215976Sjmallett * 1366215976Sjmallett * IPD_NOT_1ST_MBUFF_SKIP = IPD Not First MBUFF Word Skip Size 1367215976Sjmallett * 1368215976Sjmallett * The number of words that the IPD will skip when writing any MBUFF that is not the first. 1369215976Sjmallett */ 1370215976Sjmallettunion cvmx_ipd_not_1st_mbuff_skip 1371215976Sjmallett{ 1372215976Sjmallett uint64_t u64; 1373215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s 1374215976Sjmallett { 1375215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1376215976Sjmallett uint64_t reserved_6_63 : 58; 1377215976Sjmallett uint64_t skip_sz : 6; /**< The number of 8-byte words from the top of any 1378215976Sjmallett MBUFF, that is not the 1st MBUFF, that the IPD 1379215976Sjmallett will write the next-pointer. 1380215976Sjmallett Legal values are 0 to 32, where the MAX value 1381215976Sjmallett is also limited to: 1382215976Sjmallett IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 16. */ 1383215976Sjmallett#else 1384215976Sjmallett uint64_t skip_sz : 6; 1385215976Sjmallett uint64_t reserved_6_63 : 58; 1386215976Sjmallett#endif 1387215976Sjmallett } s; 1388215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx; 1389215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx; 1390215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx; 1391215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2; 1392215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx; 1393215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx; 1394215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1; 1395215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx; 1396215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1; 1397215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx; 1398215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1; 1399215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx; 1400215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1; 1401215976Sjmallett}; 1402215976Sjmalletttypedef union cvmx_ipd_not_1st_mbuff_skip cvmx_ipd_not_1st_mbuff_skip_t; 1403215976Sjmallett 1404215976Sjmallett/** 1405215976Sjmallett * cvmx_ipd_packet_mbuff_size 1406215976Sjmallett * 1407215976Sjmallett * IPD_PACKET_MBUFF_SIZE = IPD's PACKET MUBUF Size In Words 1408215976Sjmallett * 1409215976Sjmallett * The number of words in a MBUFF used for packet data store. 1410215976Sjmallett */ 1411215976Sjmallettunion cvmx_ipd_packet_mbuff_size 1412215976Sjmallett{ 1413215976Sjmallett uint64_t u64; 1414215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s 1415215976Sjmallett { 1416215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1417215976Sjmallett uint64_t reserved_12_63 : 52; 1418215976Sjmallett uint64_t mb_size : 12; /**< The number of 8-byte words in a MBUF. 1419215976Sjmallett This must be a number in the range of 32 to 1420215976Sjmallett 2048. 1421215976Sjmallett This is also the size of the FPA's 1422215976Sjmallett Queue-0 Free-Page. */ 1423215976Sjmallett#else 1424215976Sjmallett uint64_t mb_size : 12; 1425215976Sjmallett uint64_t reserved_12_63 : 52; 1426215976Sjmallett#endif 1427215976Sjmallett } s; 1428215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn30xx; 1429215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn31xx; 1430215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn38xx; 1431215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn38xxp2; 1432215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn50xx; 1433215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn52xx; 1434215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn52xxp1; 1435215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn56xx; 1436215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn56xxp1; 1437215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn58xx; 1438215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn58xxp1; 1439215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn63xx; 1440215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn63xxp1; 1441215976Sjmallett}; 1442215976Sjmalletttypedef union cvmx_ipd_packet_mbuff_size cvmx_ipd_packet_mbuff_size_t; 1443215976Sjmallett 1444215976Sjmallett/** 1445215976Sjmallett * cvmx_ipd_pkt_ptr_valid 1446215976Sjmallett * 1447215976Sjmallett * IPD_PKT_PTR_VALID = IPD's Packet Pointer Valid 1448215976Sjmallett * 1449215976Sjmallett * The value of the packet-pointer fetched and in the valid register. 1450215976Sjmallett */ 1451215976Sjmallettunion cvmx_ipd_pkt_ptr_valid 1452215976Sjmallett{ 1453215976Sjmallett uint64_t u64; 1454215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s 1455215976Sjmallett { 1456215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1457215976Sjmallett uint64_t reserved_29_63 : 35; 1458215976Sjmallett uint64_t ptr : 29; /**< Pointer value. */ 1459215976Sjmallett#else 1460215976Sjmallett uint64_t ptr : 29; 1461215976Sjmallett uint64_t reserved_29_63 : 35; 1462215976Sjmallett#endif 1463215976Sjmallett } s; 1464215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn30xx; 1465215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn31xx; 1466215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn38xx; 1467215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn50xx; 1468215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn52xx; 1469215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1; 1470215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn56xx; 1471215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1; 1472215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn58xx; 1473215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1; 1474215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn63xx; 1475215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1; 1476215976Sjmallett}; 1477215976Sjmalletttypedef union cvmx_ipd_pkt_ptr_valid cvmx_ipd_pkt_ptr_valid_t; 1478215976Sjmallett 1479215976Sjmallett/** 1480215976Sjmallett * cvmx_ipd_port#_bp_page_cnt 1481215976Sjmallett * 1482215976Sjmallett * IPD_PORTX_BP_PAGE_CNT = IPD Port Backpressure Page Count 1483215976Sjmallett * 1484215976Sjmallett * The number of pages in use by the port that when exceeded, backpressure will be applied to the port. 1485215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT2 1486215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT3 1487215976Sjmallett */ 1488215976Sjmallettunion cvmx_ipd_portx_bp_page_cnt 1489215976Sjmallett{ 1490215976Sjmallett uint64_t u64; 1491215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s 1492215976Sjmallett { 1493215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1494215976Sjmallett uint64_t reserved_18_63 : 46; 1495215976Sjmallett uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 1496215976Sjmallett not be applied to port. */ 1497215976Sjmallett uint64_t page_cnt : 17; /**< The number of page pointers assigned to 1498215976Sjmallett the port, that when exceeded will cause 1499215976Sjmallett back-pressure to be applied to the port. 1500215976Sjmallett This value is in 256 page-pointer increments, 1501215976Sjmallett (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 1502215976Sjmallett#else 1503215976Sjmallett uint64_t page_cnt : 17; 1504215976Sjmallett uint64_t bp_enb : 1; 1505215976Sjmallett uint64_t reserved_18_63 : 46; 1506215976Sjmallett#endif 1507215976Sjmallett } s; 1508215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn30xx; 1509215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn31xx; 1510215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn38xx; 1511215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2; 1512215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn50xx; 1513215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn52xx; 1514215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1; 1515215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn56xx; 1516215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1; 1517215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn58xx; 1518215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1; 1519215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn63xx; 1520215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1; 1521215976Sjmallett}; 1522215976Sjmalletttypedef union cvmx_ipd_portx_bp_page_cnt cvmx_ipd_portx_bp_page_cnt_t; 1523215976Sjmallett 1524215976Sjmallett/** 1525215976Sjmallett * cvmx_ipd_port#_bp_page_cnt2 1526215976Sjmallett * 1527215976Sjmallett * IPD_PORTX_BP_PAGE_CNT2 = IPD Port Backpressure Page Count 1528215976Sjmallett * 1529215976Sjmallett * The number of pages in use by the port that when exceeded, backpressure will be applied to the port. 1530215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT 1531215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT3 1532215976Sjmallett */ 1533215976Sjmallettunion cvmx_ipd_portx_bp_page_cnt2 1534215976Sjmallett{ 1535215976Sjmallett uint64_t u64; 1536215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s 1537215976Sjmallett { 1538215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1539215976Sjmallett uint64_t reserved_18_63 : 46; 1540215976Sjmallett uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 1541215976Sjmallett not be applied to port. */ 1542215976Sjmallett uint64_t page_cnt : 17; /**< The number of page pointers assigned to 1543215976Sjmallett the port, that when exceeded will cause 1544215976Sjmallett back-pressure to be applied to the port. 1545215976Sjmallett This value is in 256 page-pointer increments, 1546215976Sjmallett (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 1547215976Sjmallett#else 1548215976Sjmallett uint64_t page_cnt : 17; 1549215976Sjmallett uint64_t bp_enb : 1; 1550215976Sjmallett uint64_t reserved_18_63 : 46; 1551215976Sjmallett#endif 1552215976Sjmallett } s; 1553215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx; 1554215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1; 1555215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx; 1556215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1; 1557215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx; 1558215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1; 1559215976Sjmallett}; 1560215976Sjmalletttypedef union cvmx_ipd_portx_bp_page_cnt2 cvmx_ipd_portx_bp_page_cnt2_t; 1561215976Sjmallett 1562215976Sjmallett/** 1563215976Sjmallett * cvmx_ipd_port#_bp_page_cnt3 1564215976Sjmallett * 1565215976Sjmallett * IPD_PORTX_BP_PAGE_CNT3 = IPD Port Backpressure Page Count 1566215976Sjmallett * 1567215976Sjmallett * The number of pages in use by the port that when exceeded, backpressure will be applied to the port. 1568215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT 1569215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT2 1570215976Sjmallett */ 1571215976Sjmallettunion cvmx_ipd_portx_bp_page_cnt3 1572215976Sjmallett{ 1573215976Sjmallett uint64_t u64; 1574215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt3_s 1575215976Sjmallett { 1576215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1577215976Sjmallett uint64_t reserved_18_63 : 46; 1578215976Sjmallett uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 1579215976Sjmallett not be applied to port. */ 1580215976Sjmallett uint64_t page_cnt : 17; /**< The number of page pointers assigned to 1581215976Sjmallett the port, that when exceeded will cause 1582215976Sjmallett back-pressure to be applied to the port. 1583215976Sjmallett This value is in 256 page-pointer increments, 1584215976Sjmallett (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 1585215976Sjmallett#else 1586215976Sjmallett uint64_t page_cnt : 17; 1587215976Sjmallett uint64_t bp_enb : 1; 1588215976Sjmallett uint64_t reserved_18_63 : 46; 1589215976Sjmallett#endif 1590215976Sjmallett } s; 1591215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx; 1592215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1; 1593215976Sjmallett}; 1594215976Sjmalletttypedef union cvmx_ipd_portx_bp_page_cnt3 cvmx_ipd_portx_bp_page_cnt3_t; 1595215976Sjmallett 1596215976Sjmallett/** 1597215976Sjmallett * cvmx_ipd_port_bp_counters2_pair# 1598215976Sjmallett * 1599215976Sjmallett * IPD_PORT_BP_COUNTERS2_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 1600215976Sjmallett * See also IPD_PORT_BP_COUNTERS_PAIRX 1601215976Sjmallett * See also IPD_PORT_BP_COUNTERS3_PAIRX 1602215976Sjmallett */ 1603215976Sjmallettunion cvmx_ipd_port_bp_counters2_pairx 1604215976Sjmallett{ 1605215976Sjmallett uint64_t u64; 1606215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s 1607215976Sjmallett { 1608215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1609215976Sjmallett uint64_t reserved_25_63 : 39; 1610215976Sjmallett uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 1611215976Sjmallett#else 1612215976Sjmallett uint64_t cnt_val : 25; 1613215976Sjmallett uint64_t reserved_25_63 : 39; 1614215976Sjmallett#endif 1615215976Sjmallett } s; 1616215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx; 1617215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1; 1618215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx; 1619215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1; 1620215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx; 1621215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1; 1622215976Sjmallett}; 1623215976Sjmalletttypedef union cvmx_ipd_port_bp_counters2_pairx cvmx_ipd_port_bp_counters2_pairx_t; 1624215976Sjmallett 1625215976Sjmallett/** 1626215976Sjmallett * cvmx_ipd_port_bp_counters3_pair# 1627215976Sjmallett * 1628215976Sjmallett * IPD_PORT_BP_COUNTERS3_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 1629215976Sjmallett * See also IPD_PORT_BP_COUNTERS_PAIRX 1630215976Sjmallett * See also IPD_PORT_BP_COUNTERS2_PAIRX 1631215976Sjmallett */ 1632215976Sjmallettunion cvmx_ipd_port_bp_counters3_pairx 1633215976Sjmallett{ 1634215976Sjmallett uint64_t u64; 1635215976Sjmallett struct cvmx_ipd_port_bp_counters3_pairx_s 1636215976Sjmallett { 1637215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1638215976Sjmallett uint64_t reserved_25_63 : 39; 1639215976Sjmallett uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 1640215976Sjmallett#else 1641215976Sjmallett uint64_t cnt_val : 25; 1642215976Sjmallett uint64_t reserved_25_63 : 39; 1643215976Sjmallett#endif 1644215976Sjmallett } s; 1645215976Sjmallett struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx; 1646215976Sjmallett struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1; 1647215976Sjmallett}; 1648215976Sjmalletttypedef union cvmx_ipd_port_bp_counters3_pairx cvmx_ipd_port_bp_counters3_pairx_t; 1649215976Sjmallett 1650215976Sjmallett/** 1651215976Sjmallett * cvmx_ipd_port_bp_counters_pair# 1652215976Sjmallett * 1653215976Sjmallett * IPD_PORT_BP_COUNTERS_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 1654215976Sjmallett * See also IPD_PORT_BP_COUNTERS2_PAIRX 1655215976Sjmallett * See also IPD_PORT_BP_COUNTERS3_PAIRX 1656215976Sjmallett */ 1657215976Sjmallettunion cvmx_ipd_port_bp_counters_pairx 1658215976Sjmallett{ 1659215976Sjmallett uint64_t u64; 1660215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s 1661215976Sjmallett { 1662215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1663215976Sjmallett uint64_t reserved_25_63 : 39; 1664215976Sjmallett uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 1665215976Sjmallett#else 1666215976Sjmallett uint64_t cnt_val : 25; 1667215976Sjmallett uint64_t reserved_25_63 : 39; 1668215976Sjmallett#endif 1669215976Sjmallett } s; 1670215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn30xx; 1671215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn31xx; 1672215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn38xx; 1673215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2; 1674215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn50xx; 1675215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn52xx; 1676215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1; 1677215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn56xx; 1678215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1; 1679215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn58xx; 1680215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1; 1681215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn63xx; 1682215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1; 1683215976Sjmallett}; 1684215976Sjmalletttypedef union cvmx_ipd_port_bp_counters_pairx cvmx_ipd_port_bp_counters_pairx_t; 1685215976Sjmallett 1686215976Sjmallett/** 1687215976Sjmallett * cvmx_ipd_port_qos_#_cnt 1688215976Sjmallett * 1689215976Sjmallett * IPD_PORT_QOS_X_CNT = IPD PortX QOS-0 Count 1690215976Sjmallett * 1691215976Sjmallett * A counter per port/qos. Counter are originzed in sequence where the first 8 counter (0-7) belong to Port-0 1692215976Sjmallett * QOS 0-7 respectively followed by port 1 at (8-15), etc 1693215976Sjmallett * Ports 0-3, 32-43 1694215976Sjmallett */ 1695215976Sjmallettunion cvmx_ipd_port_qos_x_cnt 1696215976Sjmallett{ 1697215976Sjmallett uint64_t u64; 1698215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s 1699215976Sjmallett { 1700215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1701215976Sjmallett uint64_t wmark : 32; /**< When the field CNT after being modified is equal to 1702215976Sjmallett or crosses this value (i.e. value was greater than 1703215976Sjmallett then becomes less then, or value was less than and 1704215976Sjmallett becomes greater than) the corresponding bit in 1705215976Sjmallett IPD_PORT_QOS_INTX is set. */ 1706215976Sjmallett uint64_t cnt : 32; /**< The packet related count that is incremented as 1707215976Sjmallett specified by IPD_SUB_PORT_QOS_CNT. */ 1708215976Sjmallett#else 1709215976Sjmallett uint64_t cnt : 32; 1710215976Sjmallett uint64_t wmark : 32; 1711215976Sjmallett#endif 1712215976Sjmallett } s; 1713215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn52xx; 1714215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1; 1715215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn56xx; 1716215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1; 1717215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn63xx; 1718215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1; 1719215976Sjmallett}; 1720215976Sjmalletttypedef union cvmx_ipd_port_qos_x_cnt cvmx_ipd_port_qos_x_cnt_t; 1721215976Sjmallett 1722215976Sjmallett/** 1723215976Sjmallett * cvmx_ipd_port_qos_int# 1724215976Sjmallett * 1725215976Sjmallett * IPD_PORT_QOS_INTX = IPD PORT-QOS Interrupt 1726215976Sjmallett * 1727215976Sjmallett * See the description for IPD_PORT_QOS_X_CNT 1728215976Sjmallett * 1729215976Sjmallett * 0=P0-7; 1=P8-15; 2=P16-23; 3=P24-31; 4=P32-39; 5=P40-47; 6=P48-55; 7=P56-63 1730215976Sjmallett * 1731215976Sjmallett * Only ports used are: P0-3, P32-39, and P40-43. Therefore only IPD_PORT_QOS_INT0, IPD_PORT_QOS_INT4, 1732215976Sjmallett * and IPD_PORT_QOS_INT5 exist and, furthermore: <63:32> of IPD_PORT_QOS_INT0 and IPD_PORT_QOS_INT5, 1733215976Sjmallett * are reserved. 1734215976Sjmallett */ 1735215976Sjmallettunion cvmx_ipd_port_qos_intx 1736215976Sjmallett{ 1737215976Sjmallett uint64_t u64; 1738215976Sjmallett struct cvmx_ipd_port_qos_intx_s 1739215976Sjmallett { 1740215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1741215976Sjmallett uint64_t intr : 64; /**< Interrupt bits. */ 1742215976Sjmallett#else 1743215976Sjmallett uint64_t intr : 64; 1744215976Sjmallett#endif 1745215976Sjmallett } s; 1746215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn52xx; 1747215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn52xxp1; 1748215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn56xx; 1749215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn56xxp1; 1750215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn63xx; 1751215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn63xxp1; 1752215976Sjmallett}; 1753215976Sjmalletttypedef union cvmx_ipd_port_qos_intx cvmx_ipd_port_qos_intx_t; 1754215976Sjmallett 1755215976Sjmallett/** 1756215976Sjmallett * cvmx_ipd_port_qos_int_enb# 1757215976Sjmallett * 1758215976Sjmallett * IPD_PORT_QOS_INT_ENBX = IPD PORT-QOS Interrupt Enable 1759215976Sjmallett * 1760215976Sjmallett * When the IPD_PORT_QOS_INTX[\#] is '1' and IPD_PORT_QOS_INT_ENBX[\#] is '1' a interrupt will be generated. 1761215976Sjmallett */ 1762215976Sjmallettunion cvmx_ipd_port_qos_int_enbx 1763215976Sjmallett{ 1764215976Sjmallett uint64_t u64; 1765215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s 1766215976Sjmallett { 1767215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1768215976Sjmallett uint64_t enb : 64; /**< Enable bits. */ 1769215976Sjmallett#else 1770215976Sjmallett uint64_t enb : 64; 1771215976Sjmallett#endif 1772215976Sjmallett } s; 1773215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn52xx; 1774215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1; 1775215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn56xx; 1776215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1; 1777215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn63xx; 1778215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1; 1779215976Sjmallett}; 1780215976Sjmalletttypedef union cvmx_ipd_port_qos_int_enbx cvmx_ipd_port_qos_int_enbx_t; 1781215976Sjmallett 1782215976Sjmallett/** 1783215976Sjmallett * cvmx_ipd_prc_hold_ptr_fifo_ctl 1784215976Sjmallett * 1785215976Sjmallett * IPD_PRC_HOLD_PTR_FIFO_CTL = IPD's PRC Holding Pointer FIFO Control 1786215976Sjmallett * 1787215976Sjmallett * Allows reading of the Page-Pointers stored in the IPD's PRC Holding Fifo. 1788215976Sjmallett */ 1789215976Sjmallettunion cvmx_ipd_prc_hold_ptr_fifo_ctl 1790215976Sjmallett{ 1791215976Sjmallett uint64_t u64; 1792215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s 1793215976Sjmallett { 1794215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1795215976Sjmallett uint64_t reserved_39_63 : 25; 1796215976Sjmallett uint64_t max_pkt : 3; /**< Maximum number of Packet-Pointers that COULD be 1797215976Sjmallett in the FIFO. */ 1798215976Sjmallett uint64_t praddr : 3; /**< Present Packet-Pointer read address. */ 1799215976Sjmallett uint64_t ptr : 29; /**< The output of the prc-holding-fifo. */ 1800215976Sjmallett uint64_t cena : 1; /**< Active low Chip Enable that controls the 1801215976Sjmallett MUX-select that steers [RADDR] to the fifo. 1802215976Sjmallett *WARNING - Setting this field to '0' will allow 1803215976Sjmallett reading of the memories thorugh the PTR field, 1804215976Sjmallett but will cause unpredictable operation of the IPD 1805215976Sjmallett under normal operation. */ 1806215976Sjmallett uint64_t raddr : 3; /**< Sets the address to read from in the holding. 1807215976Sjmallett fifo in the PRC. This FIFO holds Packet-Pointers 1808215976Sjmallett to be used for packet data storage. */ 1809215976Sjmallett#else 1810215976Sjmallett uint64_t raddr : 3; 1811215976Sjmallett uint64_t cena : 1; 1812215976Sjmallett uint64_t ptr : 29; 1813215976Sjmallett uint64_t praddr : 3; 1814215976Sjmallett uint64_t max_pkt : 3; 1815215976Sjmallett uint64_t reserved_39_63 : 25; 1816215976Sjmallett#endif 1817215976Sjmallett } s; 1818215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx; 1819215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx; 1820215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx; 1821215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx; 1822215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx; 1823215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1; 1824215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx; 1825215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1; 1826215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx; 1827215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1; 1828215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx; 1829215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1; 1830215976Sjmallett}; 1831215976Sjmalletttypedef union cvmx_ipd_prc_hold_ptr_fifo_ctl cvmx_ipd_prc_hold_ptr_fifo_ctl_t; 1832215976Sjmallett 1833215976Sjmallett/** 1834215976Sjmallett * cvmx_ipd_prc_port_ptr_fifo_ctl 1835215976Sjmallett * 1836215976Sjmallett * IPD_PRC_PORT_PTR_FIFO_CTL = IPD's PRC PORT Pointer FIFO Control 1837215976Sjmallett * 1838215976Sjmallett * Allows reading of the Page-Pointers stored in the IPD's PRC PORT Fifo. 1839215976Sjmallett */ 1840215976Sjmallettunion cvmx_ipd_prc_port_ptr_fifo_ctl 1841215976Sjmallett{ 1842215976Sjmallett uint64_t u64; 1843215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s 1844215976Sjmallett { 1845215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1846215976Sjmallett uint64_t reserved_44_63 : 20; 1847215976Sjmallett uint64_t max_pkt : 7; /**< Maximum number of Packet-Pointers that are in 1848215976Sjmallett in the FIFO. */ 1849215976Sjmallett uint64_t ptr : 29; /**< The output of the prc-port-ptr-fifo. */ 1850215976Sjmallett uint64_t cena : 1; /**< Active low Chip Enable to the read port of the 1851215976Sjmallett pwp_fifo. This bit also controls the MUX-select 1852215976Sjmallett that steers [RADDR] to the pwp_fifo. 1853215976Sjmallett *WARNING - Setting this field to '0' will allow 1854215976Sjmallett reading of the memories thorugh the PTR field, 1855215976Sjmallett but will cause unpredictable operation of the IPD 1856215976Sjmallett under normal operation. */ 1857215976Sjmallett uint64_t raddr : 7; /**< Sets the address to read from in the port 1858215976Sjmallett fifo in the PRC. This FIFO holds Packet-Pointers 1859215976Sjmallett to be used for packet data storage. */ 1860215976Sjmallett#else 1861215976Sjmallett uint64_t raddr : 7; 1862215976Sjmallett uint64_t cena : 1; 1863215976Sjmallett uint64_t ptr : 29; 1864215976Sjmallett uint64_t max_pkt : 7; 1865215976Sjmallett uint64_t reserved_44_63 : 20; 1866215976Sjmallett#endif 1867215976Sjmallett } s; 1868215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx; 1869215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx; 1870215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx; 1871215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx; 1872215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx; 1873215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1; 1874215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx; 1875215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1; 1876215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx; 1877215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1; 1878215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx; 1879215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1; 1880215976Sjmallett}; 1881215976Sjmalletttypedef union cvmx_ipd_prc_port_ptr_fifo_ctl cvmx_ipd_prc_port_ptr_fifo_ctl_t; 1882215976Sjmallett 1883215976Sjmallett/** 1884215976Sjmallett * cvmx_ipd_ptr_count 1885215976Sjmallett * 1886215976Sjmallett * IPD_PTR_COUNT = IPD Page Pointer Count 1887215976Sjmallett * 1888215976Sjmallett * Shows the number of WQE and Packet Page Pointers stored in the IPD. 1889215976Sjmallett */ 1890215976Sjmallettunion cvmx_ipd_ptr_count 1891215976Sjmallett{ 1892215976Sjmallett uint64_t u64; 1893215976Sjmallett struct cvmx_ipd_ptr_count_s 1894215976Sjmallett { 1895215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1896215976Sjmallett uint64_t reserved_19_63 : 45; 1897215976Sjmallett uint64_t pktv_cnt : 1; /**< PKT Ptr Valid. */ 1898215976Sjmallett uint64_t wqev_cnt : 1; /**< WQE Ptr Valid. This value is '1' when a WQE 1899215976Sjmallett is being for use by the IPD. The value of this 1900215976Sjmallett field should be added to tha value of the 1901215976Sjmallett WQE_PCNT field, of this register, for a total 1902215976Sjmallett count of the WQE Page Pointers being held by IPD. 1903215976Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 1904215976Sjmallett represents a Packet-Pointer NOT a WQE pointer. */ 1905215976Sjmallett uint64_t pfif_cnt : 3; /**< See PKT_PCNT. */ 1906215976Sjmallett uint64_t pkt_pcnt : 7; /**< This value plus PFIF_CNT plus 1907215976Sjmallett IPD_PRC_PORT_PTR_FIFO_CTL[MAX_PKT] is the number 1908215976Sjmallett of PKT Page Pointers in IPD. */ 1909215976Sjmallett uint64_t wqe_pcnt : 7; /**< Number of page pointers for WQE storage that are 1910215976Sjmallett buffered in the IPD. The total count is the value 1911215976Sjmallett of this buffer plus the field [WQEV_CNT]. For 1912215976Sjmallett PASS-1 (which does not have the WQEV_CNT field) 1913215976Sjmallett when the value of this register is '0' there still 1914215976Sjmallett may be 1 pointer being held by IPD. */ 1915215976Sjmallett#else 1916215976Sjmallett uint64_t wqe_pcnt : 7; 1917215976Sjmallett uint64_t pkt_pcnt : 7; 1918215976Sjmallett uint64_t pfif_cnt : 3; 1919215976Sjmallett uint64_t wqev_cnt : 1; 1920215976Sjmallett uint64_t pktv_cnt : 1; 1921215976Sjmallett uint64_t reserved_19_63 : 45; 1922215976Sjmallett#endif 1923215976Sjmallett } s; 1924215976Sjmallett struct cvmx_ipd_ptr_count_s cn30xx; 1925215976Sjmallett struct cvmx_ipd_ptr_count_s cn31xx; 1926215976Sjmallett struct cvmx_ipd_ptr_count_s cn38xx; 1927215976Sjmallett struct cvmx_ipd_ptr_count_s cn38xxp2; 1928215976Sjmallett struct cvmx_ipd_ptr_count_s cn50xx; 1929215976Sjmallett struct cvmx_ipd_ptr_count_s cn52xx; 1930215976Sjmallett struct cvmx_ipd_ptr_count_s cn52xxp1; 1931215976Sjmallett struct cvmx_ipd_ptr_count_s cn56xx; 1932215976Sjmallett struct cvmx_ipd_ptr_count_s cn56xxp1; 1933215976Sjmallett struct cvmx_ipd_ptr_count_s cn58xx; 1934215976Sjmallett struct cvmx_ipd_ptr_count_s cn58xxp1; 1935215976Sjmallett struct cvmx_ipd_ptr_count_s cn63xx; 1936215976Sjmallett struct cvmx_ipd_ptr_count_s cn63xxp1; 1937215976Sjmallett}; 1938215976Sjmalletttypedef union cvmx_ipd_ptr_count cvmx_ipd_ptr_count_t; 1939215976Sjmallett 1940215976Sjmallett/** 1941215976Sjmallett * cvmx_ipd_pwp_ptr_fifo_ctl 1942215976Sjmallett * 1943215976Sjmallett * IPD_PWP_PTR_FIFO_CTL = IPD's PWP Pointer FIFO Control 1944215976Sjmallett * 1945215976Sjmallett * Allows reading of the Page-Pointers stored in the IPD's PWP Fifo. 1946215976Sjmallett */ 1947215976Sjmallettunion cvmx_ipd_pwp_ptr_fifo_ctl 1948215976Sjmallett{ 1949215976Sjmallett uint64_t u64; 1950215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s 1951215976Sjmallett { 1952215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1953215976Sjmallett uint64_t reserved_61_63 : 3; 1954215976Sjmallett uint64_t max_cnts : 7; /**< Maximum number of Packet-Pointers or WQE-Pointers 1955215976Sjmallett that COULD be in the FIFO. 1956215976Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 1957215976Sjmallett only represents the Max number of Packet-Pointers, 1958215976Sjmallett WQE-Pointers are not used in this mode. */ 1959215976Sjmallett uint64_t wraddr : 8; /**< Present FIFO WQE Read address. */ 1960215976Sjmallett uint64_t praddr : 8; /**< Present FIFO Packet Read address. */ 1961215976Sjmallett uint64_t ptr : 29; /**< The output of the pwp_fifo. */ 1962215976Sjmallett uint64_t cena : 1; /**< Active low Chip Enable to the read port of the 1963215976Sjmallett pwp_fifo. This bit also controls the MUX-select 1964215976Sjmallett that steers [RADDR] to the pwp_fifo. 1965215976Sjmallett *WARNING - Setting this field to '0' will allow 1966215976Sjmallett reading of the memories thorugh the PTR field, 1967215976Sjmallett but will cause unpredictable operation of the IPD 1968215976Sjmallett under normal operation. */ 1969215976Sjmallett uint64_t raddr : 8; /**< Sets the address to read from in the pwp_fifo. 1970215976Sjmallett Addresses 0 through 63 contain Packet-Pointers and 1971215976Sjmallett addresses 64 through 127 contain WQE-Pointers. 1972215976Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' addresses 1973215976Sjmallett 64 through 127 are not valid. */ 1974215976Sjmallett#else 1975215976Sjmallett uint64_t raddr : 8; 1976215976Sjmallett uint64_t cena : 1; 1977215976Sjmallett uint64_t ptr : 29; 1978215976Sjmallett uint64_t praddr : 8; 1979215976Sjmallett uint64_t wraddr : 8; 1980215976Sjmallett uint64_t max_cnts : 7; 1981215976Sjmallett uint64_t reserved_61_63 : 3; 1982215976Sjmallett#endif 1983215976Sjmallett } s; 1984215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx; 1985215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx; 1986215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx; 1987215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx; 1988215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx; 1989215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1; 1990215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx; 1991215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1; 1992215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx; 1993215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1; 1994215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx; 1995215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1; 1996215976Sjmallett}; 1997215976Sjmalletttypedef union cvmx_ipd_pwp_ptr_fifo_ctl cvmx_ipd_pwp_ptr_fifo_ctl_t; 1998215976Sjmallett 1999215976Sjmallett/** 2000215976Sjmallett * cvmx_ipd_qos#_red_marks 2001215976Sjmallett * 2002215976Sjmallett * IPD_QOS0_RED_MARKS = IPD QOS 0 Marks Red High Low 2003215976Sjmallett * 2004215976Sjmallett * Set the pass-drop marks for qos level. 2005215976Sjmallett */ 2006215976Sjmallettunion cvmx_ipd_qosx_red_marks 2007215976Sjmallett{ 2008215976Sjmallett uint64_t u64; 2009215976Sjmallett struct cvmx_ipd_qosx_red_marks_s 2010215976Sjmallett { 2011215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2012215976Sjmallett uint64_t drop : 32; /**< Packets will be dropped when the average value of 2013215976Sjmallett IPD_QUE0_FREE_PAGE_CNT is equal to or less than 2014215976Sjmallett this value. */ 2015215976Sjmallett uint64_t pass : 32; /**< Packets will be passed when the average value of 2016215976Sjmallett IPD_QUE0_FREE_PAGE_CNT is larger than this value. */ 2017215976Sjmallett#else 2018215976Sjmallett uint64_t pass : 32; 2019215976Sjmallett uint64_t drop : 32; 2020215976Sjmallett#endif 2021215976Sjmallett } s; 2022215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn30xx; 2023215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn31xx; 2024215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn38xx; 2025215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn38xxp2; 2026215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn50xx; 2027215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn52xx; 2028215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn52xxp1; 2029215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn56xx; 2030215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn56xxp1; 2031215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn58xx; 2032215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn58xxp1; 2033215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn63xx; 2034215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn63xxp1; 2035215976Sjmallett}; 2036215976Sjmalletttypedef union cvmx_ipd_qosx_red_marks cvmx_ipd_qosx_red_marks_t; 2037215976Sjmallett 2038215976Sjmallett/** 2039215976Sjmallett * cvmx_ipd_que0_free_page_cnt 2040215976Sjmallett * 2041215976Sjmallett * IPD_QUE0_FREE_PAGE_CNT = IPD Queue0 Free Page Count 2042215976Sjmallett * 2043215976Sjmallett * Number of Free-Page Pointer that are available for use in the FPA for Queue-0. 2044215976Sjmallett */ 2045215976Sjmallettunion cvmx_ipd_que0_free_page_cnt 2046215976Sjmallett{ 2047215976Sjmallett uint64_t u64; 2048215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s 2049215976Sjmallett { 2050215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2051215976Sjmallett uint64_t reserved_32_63 : 32; 2052215976Sjmallett uint64_t q0_pcnt : 32; /**< Number of Queue-0 Page Pointers Available. */ 2053215976Sjmallett#else 2054215976Sjmallett uint64_t q0_pcnt : 32; 2055215976Sjmallett uint64_t reserved_32_63 : 32; 2056215976Sjmallett#endif 2057215976Sjmallett } s; 2058215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn30xx; 2059215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn31xx; 2060215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn38xx; 2061215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2; 2062215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn50xx; 2063215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn52xx; 2064215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1; 2065215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn56xx; 2066215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1; 2067215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn58xx; 2068215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1; 2069215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn63xx; 2070215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1; 2071215976Sjmallett}; 2072215976Sjmalletttypedef union cvmx_ipd_que0_free_page_cnt cvmx_ipd_que0_free_page_cnt_t; 2073215976Sjmallett 2074215976Sjmallett/** 2075215976Sjmallett * cvmx_ipd_red_port_enable 2076215976Sjmallett * 2077215976Sjmallett * IPD_RED_PORT_ENABLE = IPD RED Port Enable 2078215976Sjmallett * 2079215976Sjmallett * Set the pass-drop marks for qos level. 2080215976Sjmallett */ 2081215976Sjmallettunion cvmx_ipd_red_port_enable 2082215976Sjmallett{ 2083215976Sjmallett uint64_t u64; 2084215976Sjmallett struct cvmx_ipd_red_port_enable_s 2085215976Sjmallett { 2086215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2087215976Sjmallett uint64_t prb_dly : 14; /**< Number (core clocks periods + 68) * 8 to wait 2088215976Sjmallett before calculating the new packet drop 2089215976Sjmallett probability for each QOS level. */ 2090215976Sjmallett uint64_t avg_dly : 14; /**< Number (core clocks periods + 10) * 8 to wait 2091215976Sjmallett before calculating the moving average for each 2092215976Sjmallett QOS level. 2093215976Sjmallett Larger AVG_DLY values cause the moving averages 2094215976Sjmallett of ALL QOS levels to track changes in the actual 2095215976Sjmallett free space more slowly. Smaller NEW_CON (and 2096215976Sjmallett larger AVG_CON) values can have a similar effect, 2097215976Sjmallett but only affect an individual QOS level, rather 2098215976Sjmallett than all. */ 2099215976Sjmallett uint64_t prt_enb : 36; /**< The bit position will enable the corresponding 2100215976Sjmallett Ports ability to have packets dropped by RED 2101215976Sjmallett probability. */ 2102215976Sjmallett#else 2103215976Sjmallett uint64_t prt_enb : 36; 2104215976Sjmallett uint64_t avg_dly : 14; 2105215976Sjmallett uint64_t prb_dly : 14; 2106215976Sjmallett#endif 2107215976Sjmallett } s; 2108215976Sjmallett struct cvmx_ipd_red_port_enable_s cn30xx; 2109215976Sjmallett struct cvmx_ipd_red_port_enable_s cn31xx; 2110215976Sjmallett struct cvmx_ipd_red_port_enable_s cn38xx; 2111215976Sjmallett struct cvmx_ipd_red_port_enable_s cn38xxp2; 2112215976Sjmallett struct cvmx_ipd_red_port_enable_s cn50xx; 2113215976Sjmallett struct cvmx_ipd_red_port_enable_s cn52xx; 2114215976Sjmallett struct cvmx_ipd_red_port_enable_s cn52xxp1; 2115215976Sjmallett struct cvmx_ipd_red_port_enable_s cn56xx; 2116215976Sjmallett struct cvmx_ipd_red_port_enable_s cn56xxp1; 2117215976Sjmallett struct cvmx_ipd_red_port_enable_s cn58xx; 2118215976Sjmallett struct cvmx_ipd_red_port_enable_s cn58xxp1; 2119215976Sjmallett struct cvmx_ipd_red_port_enable_s cn63xx; 2120215976Sjmallett struct cvmx_ipd_red_port_enable_s cn63xxp1; 2121215976Sjmallett}; 2122215976Sjmalletttypedef union cvmx_ipd_red_port_enable cvmx_ipd_red_port_enable_t; 2123215976Sjmallett 2124215976Sjmallett/** 2125215976Sjmallett * cvmx_ipd_red_port_enable2 2126215976Sjmallett * 2127215976Sjmallett * IPD_RED_PORT_ENABLE2 = IPD RED Port Enable2 2128215976Sjmallett * 2129215976Sjmallett * Set the pass-drop marks for qos level. 2130215976Sjmallett */ 2131215976Sjmallettunion cvmx_ipd_red_port_enable2 2132215976Sjmallett{ 2133215976Sjmallett uint64_t u64; 2134215976Sjmallett struct cvmx_ipd_red_port_enable2_s 2135215976Sjmallett { 2136215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2137215976Sjmallett uint64_t reserved_8_63 : 56; 2138215976Sjmallett uint64_t prt_enb : 8; /**< Bits 7-0 corresponds to ports 43-36. These bits 2139215976Sjmallett have the same meaning as the PRT_ENB field of 2140215976Sjmallett IPD_RED_PORT_ENABLE. */ 2141215976Sjmallett#else 2142215976Sjmallett uint64_t prt_enb : 8; 2143215976Sjmallett uint64_t reserved_8_63 : 56; 2144215976Sjmallett#endif 2145215976Sjmallett } s; 2146215976Sjmallett struct cvmx_ipd_red_port_enable2_cn52xx 2147215976Sjmallett { 2148215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2149215976Sjmallett uint64_t reserved_4_63 : 60; 2150215976Sjmallett uint64_t prt_enb : 4; /**< Bits 3-0 cooresponds to ports 39-36. These bits 2151215976Sjmallett have the same meaning as the PRT_ENB field of 2152215976Sjmallett IPD_RED_PORT_ENABLE. */ 2153215976Sjmallett#else 2154215976Sjmallett uint64_t prt_enb : 4; 2155215976Sjmallett uint64_t reserved_4_63 : 60; 2156215976Sjmallett#endif 2157215976Sjmallett } cn52xx; 2158215976Sjmallett struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1; 2159215976Sjmallett struct cvmx_ipd_red_port_enable2_cn52xx cn56xx; 2160215976Sjmallett struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1; 2161215976Sjmallett struct cvmx_ipd_red_port_enable2_s cn63xx; 2162215976Sjmallett struct cvmx_ipd_red_port_enable2_s cn63xxp1; 2163215976Sjmallett}; 2164215976Sjmalletttypedef union cvmx_ipd_red_port_enable2 cvmx_ipd_red_port_enable2_t; 2165215976Sjmallett 2166215976Sjmallett/** 2167215976Sjmallett * cvmx_ipd_red_que#_param 2168215976Sjmallett * 2169215976Sjmallett * IPD_RED_QUE0_PARAM = IPD RED Queue-0 Parameters 2170215976Sjmallett * 2171215976Sjmallett * Value control the Passing and Dropping of packets by the red engine for QOS Level-0. 2172215976Sjmallett */ 2173215976Sjmallettunion cvmx_ipd_red_quex_param 2174215976Sjmallett{ 2175215976Sjmallett uint64_t u64; 2176215976Sjmallett struct cvmx_ipd_red_quex_param_s 2177215976Sjmallett { 2178215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2179215976Sjmallett uint64_t reserved_49_63 : 15; 2180215976Sjmallett uint64_t use_pcnt : 1; /**< When set '1' red will use the actual Packet-Page 2181215976Sjmallett Count in place of the Average for RED calculations. */ 2182215976Sjmallett uint64_t new_con : 8; /**< This value is used control how much of the present 2183215976Sjmallett Actual Queue Size is used to calculate the new 2184215976Sjmallett Average Queue Size. The value is a number from 0 2185215976Sjmallett 256, which represents NEW_CON/256 of the Actual 2186215976Sjmallett Queue Size that will be used in the calculation. 2187215976Sjmallett The number in this field plus the value of 2188215976Sjmallett AVG_CON must be equal to 256. 2189215976Sjmallett Larger AVG_DLY values cause the moving averages 2190215976Sjmallett of ALL QOS levels to track changes in the actual 2191215976Sjmallett free space more slowly. Smaller NEW_CON (and 2192215976Sjmallett larger AVG_CON) values can have a similar effect, 2193215976Sjmallett but only affect an individual QOS level, rather 2194215976Sjmallett than all. */ 2195215976Sjmallett uint64_t avg_con : 8; /**< This value is used control how much of the present 2196215976Sjmallett Average Queue Size is used to calculate the new 2197215976Sjmallett Average Queue Size. The value is a number from 0 2198215976Sjmallett 256, which represents AVG_CON/256 of the Average 2199215976Sjmallett Queue Size that will be used in the calculation. 2200215976Sjmallett The number in this field plus the value of 2201215976Sjmallett NEW_CON must be equal to 256. 2202215976Sjmallett Larger AVG_DLY values cause the moving averages 2203215976Sjmallett of ALL QOS levels to track changes in the actual 2204215976Sjmallett free space more slowly. Smaller NEW_CON (and 2205215976Sjmallett larger AVG_CON) values can have a similar effect, 2206215976Sjmallett but only affect an individual QOS level, rather 2207215976Sjmallett than all. */ 2208215976Sjmallett uint64_t prb_con : 32; /**< Used in computing the probability of a packet being 2209215976Sjmallett passed or drop by the WRED engine. The field is 2210215976Sjmallett calculated to be (255 * 2^24)/(PASS-DROP). Where 2211215976Sjmallett PASS and DROP are the field from the 2212215976Sjmallett IPD_QOS0_RED_MARKS CSR. */ 2213215976Sjmallett#else 2214215976Sjmallett uint64_t prb_con : 32; 2215215976Sjmallett uint64_t avg_con : 8; 2216215976Sjmallett uint64_t new_con : 8; 2217215976Sjmallett uint64_t use_pcnt : 1; 2218215976Sjmallett uint64_t reserved_49_63 : 15; 2219215976Sjmallett#endif 2220215976Sjmallett } s; 2221215976Sjmallett struct cvmx_ipd_red_quex_param_s cn30xx; 2222215976Sjmallett struct cvmx_ipd_red_quex_param_s cn31xx; 2223215976Sjmallett struct cvmx_ipd_red_quex_param_s cn38xx; 2224215976Sjmallett struct cvmx_ipd_red_quex_param_s cn38xxp2; 2225215976Sjmallett struct cvmx_ipd_red_quex_param_s cn50xx; 2226215976Sjmallett struct cvmx_ipd_red_quex_param_s cn52xx; 2227215976Sjmallett struct cvmx_ipd_red_quex_param_s cn52xxp1; 2228215976Sjmallett struct cvmx_ipd_red_quex_param_s cn56xx; 2229215976Sjmallett struct cvmx_ipd_red_quex_param_s cn56xxp1; 2230215976Sjmallett struct cvmx_ipd_red_quex_param_s cn58xx; 2231215976Sjmallett struct cvmx_ipd_red_quex_param_s cn58xxp1; 2232215976Sjmallett struct cvmx_ipd_red_quex_param_s cn63xx; 2233215976Sjmallett struct cvmx_ipd_red_quex_param_s cn63xxp1; 2234215976Sjmallett}; 2235215976Sjmalletttypedef union cvmx_ipd_red_quex_param cvmx_ipd_red_quex_param_t; 2236215976Sjmallett 2237215976Sjmallett/** 2238215976Sjmallett * cvmx_ipd_sub_port_bp_page_cnt 2239215976Sjmallett * 2240215976Sjmallett * IPD_SUB_PORT_BP_PAGE_CNT = IPD Subtract Port Backpressure Page Count 2241215976Sjmallett * 2242215976Sjmallett * Will add the value to the indicated port count register, the number of pages supplied. The value added should 2243215976Sjmallett * be the 2's complement of the value that needs to be subtracted. Users add 2's complement values to the 2244215976Sjmallett * port-mbuf-count register to return (lower the count) mbufs to the counter in order to avoid port-level 2245215976Sjmallett * backpressure being applied to the port. Backpressure is applied when the MBUF used count of a port exceeds the 2246215976Sjmallett * value in the IPD_PORTX_BP_PAGE_CNT, IPD_PORTX_BP_PAGE_CNT2, and IPD_PORTX_BP_PAGE_CNT3. 2247215976Sjmallett * 2248215976Sjmallett * This register can't be written from the PCI via a window write. 2249215976Sjmallett */ 2250215976Sjmallettunion cvmx_ipd_sub_port_bp_page_cnt 2251215976Sjmallett{ 2252215976Sjmallett uint64_t u64; 2253215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s 2254215976Sjmallett { 2255215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2256215976Sjmallett uint64_t reserved_31_63 : 33; 2257215976Sjmallett uint64_t port : 6; /**< The port to add the PAGE_CNT field to. */ 2258215976Sjmallett uint64_t page_cnt : 25; /**< The number of page pointers to add to 2259215976Sjmallett the port counter pointed to by the 2260215976Sjmallett PORT Field. */ 2261215976Sjmallett#else 2262215976Sjmallett uint64_t page_cnt : 25; 2263215976Sjmallett uint64_t port : 6; 2264215976Sjmallett uint64_t reserved_31_63 : 33; 2265215976Sjmallett#endif 2266215976Sjmallett } s; 2267215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx; 2268215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx; 2269215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx; 2270215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2; 2271215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx; 2272215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx; 2273215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1; 2274215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx; 2275215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1; 2276215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx; 2277215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1; 2278215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx; 2279215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1; 2280215976Sjmallett}; 2281215976Sjmalletttypedef union cvmx_ipd_sub_port_bp_page_cnt cvmx_ipd_sub_port_bp_page_cnt_t; 2282215976Sjmallett 2283215976Sjmallett/** 2284215976Sjmallett * cvmx_ipd_sub_port_fcs 2285215976Sjmallett * 2286215976Sjmallett * IPD_SUB_PORT_FCS = IPD Subtract Ports FCS Register 2287215976Sjmallett * 2288215976Sjmallett * When set '1' the port corresponding to the bit set will subtract 4 bytes from the end of 2289215976Sjmallett * the packet. 2290215976Sjmallett */ 2291215976Sjmallettunion cvmx_ipd_sub_port_fcs 2292215976Sjmallett{ 2293215976Sjmallett uint64_t u64; 2294215976Sjmallett struct cvmx_ipd_sub_port_fcs_s 2295215976Sjmallett { 2296215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2297215976Sjmallett uint64_t reserved_40_63 : 24; 2298215976Sjmallett uint64_t port_bit2 : 4; /**< When set '1', the port corresponding to the bit 2299215976Sjmallett position set, will subtract the FCS for packets 2300215976Sjmallett on that port. */ 2301215976Sjmallett uint64_t reserved_32_35 : 4; 2302215976Sjmallett uint64_t port_bit : 32; /**< When set '1', the port corresponding to the bit 2303215976Sjmallett position set, will subtract the FCS for packets 2304215976Sjmallett on that port. */ 2305215976Sjmallett#else 2306215976Sjmallett uint64_t port_bit : 32; 2307215976Sjmallett uint64_t reserved_32_35 : 4; 2308215976Sjmallett uint64_t port_bit2 : 4; 2309215976Sjmallett uint64_t reserved_40_63 : 24; 2310215976Sjmallett#endif 2311215976Sjmallett } s; 2312215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn30xx 2313215976Sjmallett { 2314215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2315215976Sjmallett uint64_t reserved_3_63 : 61; 2316215976Sjmallett uint64_t port_bit : 3; /**< When set '1', the port corresponding to the bit 2317215976Sjmallett position set, will subtract the FCS for packets 2318215976Sjmallett on that port. */ 2319215976Sjmallett#else 2320215976Sjmallett uint64_t port_bit : 3; 2321215976Sjmallett uint64_t reserved_3_63 : 61; 2322215976Sjmallett#endif 2323215976Sjmallett } cn30xx; 2324215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx; 2325215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn38xx 2326215976Sjmallett { 2327215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2328215976Sjmallett uint64_t reserved_32_63 : 32; 2329215976Sjmallett uint64_t port_bit : 32; /**< When set '1', the port corresponding to the bit 2330215976Sjmallett position set, will subtract the FCS for packets 2331215976Sjmallett on that port. */ 2332215976Sjmallett#else 2333215976Sjmallett uint64_t port_bit : 32; 2334215976Sjmallett uint64_t reserved_32_63 : 32; 2335215976Sjmallett#endif 2336215976Sjmallett } cn38xx; 2337215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2; 2338215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx; 2339215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn52xx; 2340215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn52xxp1; 2341215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn56xx; 2342215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn56xxp1; 2343215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx; 2344215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1; 2345215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn63xx; 2346215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn63xxp1; 2347215976Sjmallett}; 2348215976Sjmalletttypedef union cvmx_ipd_sub_port_fcs cvmx_ipd_sub_port_fcs_t; 2349215976Sjmallett 2350215976Sjmallett/** 2351215976Sjmallett * cvmx_ipd_sub_port_qos_cnt 2352215976Sjmallett * 2353215976Sjmallett * IPD_SUB_PORT_QOS_CNT = IPD Subtract Port QOS Count 2354215976Sjmallett * 2355215976Sjmallett * Will add the value (CNT) to the indicated Port-QOS register (PORT_QOS). The value added must be 2356215976Sjmallett * be the 2's complement of the value that needs to be subtracted. 2357215976Sjmallett */ 2358215976Sjmallettunion cvmx_ipd_sub_port_qos_cnt 2359215976Sjmallett{ 2360215976Sjmallett uint64_t u64; 2361215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s 2362215976Sjmallett { 2363215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2364215976Sjmallett uint64_t reserved_41_63 : 23; 2365215976Sjmallett uint64_t port_qos : 9; /**< The port to add the CNT field to. */ 2366215976Sjmallett uint64_t cnt : 32; /**< The value to be added to the register selected 2367215976Sjmallett in the PORT_QOS field. */ 2368215976Sjmallett#else 2369215976Sjmallett uint64_t cnt : 32; 2370215976Sjmallett uint64_t port_qos : 9; 2371215976Sjmallett uint64_t reserved_41_63 : 23; 2372215976Sjmallett#endif 2373215976Sjmallett } s; 2374215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn52xx; 2375215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1; 2376215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn56xx; 2377215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1; 2378215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn63xx; 2379215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1; 2380215976Sjmallett}; 2381215976Sjmalletttypedef union cvmx_ipd_sub_port_qos_cnt cvmx_ipd_sub_port_qos_cnt_t; 2382215976Sjmallett 2383215976Sjmallett/** 2384215976Sjmallett * cvmx_ipd_wqe_fpa_queue 2385215976Sjmallett * 2386215976Sjmallett * IPD_WQE_FPA_QUEUE = IPD Work-Queue-Entry FPA Page Size 2387215976Sjmallett * 2388215976Sjmallett * Which FPA Queue (0-7) to fetch page-pointers from for WQE's 2389215976Sjmallett */ 2390215976Sjmallettunion cvmx_ipd_wqe_fpa_queue 2391215976Sjmallett{ 2392215976Sjmallett uint64_t u64; 2393215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s 2394215976Sjmallett { 2395215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2396215976Sjmallett uint64_t reserved_3_63 : 61; 2397215976Sjmallett uint64_t wqe_pool : 3; /**< Which FPA Queue to fetch page-pointers 2398215976Sjmallett from for WQE's. 2399215976Sjmallett Not used when IPD_CTL_STATUS[NO_WPTR] is set. */ 2400215976Sjmallett#else 2401215976Sjmallett uint64_t wqe_pool : 3; 2402215976Sjmallett uint64_t reserved_3_63 : 61; 2403215976Sjmallett#endif 2404215976Sjmallett } s; 2405215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn30xx; 2406215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn31xx; 2407215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn38xx; 2408215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2; 2409215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn50xx; 2410215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn52xx; 2411215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1; 2412215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn56xx; 2413215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1; 2414215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn58xx; 2415215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1; 2416215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn63xx; 2417215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1; 2418215976Sjmallett}; 2419215976Sjmalletttypedef union cvmx_ipd_wqe_fpa_queue cvmx_ipd_wqe_fpa_queue_t; 2420215976Sjmallett 2421215976Sjmallett/** 2422215976Sjmallett * cvmx_ipd_wqe_ptr_valid 2423215976Sjmallett * 2424215976Sjmallett * IPD_WQE_PTR_VALID = IPD's WQE Pointer Valid 2425215976Sjmallett * 2426215976Sjmallett * The value of the WQE-pointer fetched and in the valid register. 2427215976Sjmallett */ 2428215976Sjmallettunion cvmx_ipd_wqe_ptr_valid 2429215976Sjmallett{ 2430215976Sjmallett uint64_t u64; 2431215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s 2432215976Sjmallett { 2433215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2434215976Sjmallett uint64_t reserved_29_63 : 35; 2435215976Sjmallett uint64_t ptr : 29; /**< Pointer value. 2436215976Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 2437215976Sjmallett represents a Packet-Pointer NOT a WQE pointer. */ 2438215976Sjmallett#else 2439215976Sjmallett uint64_t ptr : 29; 2440215976Sjmallett uint64_t reserved_29_63 : 35; 2441215976Sjmallett#endif 2442215976Sjmallett } s; 2443215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn30xx; 2444215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn31xx; 2445215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn38xx; 2446215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn50xx; 2447215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn52xx; 2448215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1; 2449215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn56xx; 2450215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1; 2451215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn58xx; 2452215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1; 2453215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn63xx; 2454215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1; 2455215976Sjmallett}; 2456215976Sjmalletttypedef union cvmx_ipd_wqe_ptr_valid cvmx_ipd_wqe_ptr_valid_t; 2457215976Sjmallett 2458215976Sjmallett#endif 2459