1210284Sjmallett/***********************license start*************** 2215990Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18215990Sjmallett * * Neither the name of Cavium Networks nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215990Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over 50210284Sjmallett * XAUI. 51210284Sjmallett * 52215990Sjmallett * <hr>$Revision: 49448 $<hr> 53210284Sjmallett */ 54210284Sjmallett 55210284Sjmallett#ifndef __CVMX_HIGIG_H__ 56210284Sjmallett#define __CVMX_HIGIG_H__ 57210284Sjmallett#include "cvmx-wqe.h" 58210284Sjmallett 59210284Sjmallett#ifdef __cplusplus 60210284Sjmallettextern "C" { 61210284Sjmallett#endif 62210284Sjmallett 63210284Sjmalletttypedef struct 64210284Sjmallett{ 65210284Sjmallett union 66210284Sjmallett { 67210284Sjmallett uint32_t u32; 68210284Sjmallett struct 69210284Sjmallett { 70210284Sjmallett uint32_t start : 8; /**< 8-bits of Preamble indicating start of frame */ 71210284Sjmallett uint32_t dst_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 72210284Sjmallett DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field 73210284Sjmallett value of b'01' this field should be b'1'. For all other values of HGI it is don't 74210284Sjmallett care. */ 75210284Sjmallett uint32_t src_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 76210284Sjmallett SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field 77210284Sjmallett value of b'01' this field should be b'0'. For all other values of HGI it is don't 78210284Sjmallett care. */ 79210284Sjmallett uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 80210284Sjmallett to the standard 12-bytes of XGS HiGig header. Each unit represents 4 81210284Sjmallett bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 82210284Sjmallett and b'111' are reserved. For HGI field value of b'01' this field should be 83210284Sjmallett b'01'. For all other values of HGI it is don't care. */ 84210284Sjmallett uint32_t cng_high : 1; /**< Congestion Bit High flag */ 85210284Sjmallett uint32_t hgi : 2; /**< HiGig interface format indicator 86210284Sjmallett 00 = Reserved 87210284Sjmallett 01 = Pure preamble - IEEE standard framing of 10GE 88210284Sjmallett 10 = XGS header - framing based on XGS family definition In this 89210284Sjmallett format, the default length of the header is 12 bytes and additional 90210284Sjmallett bytes are indicated by the HDR_EXT_LEN field 91210284Sjmallett 11 = Reserved */ 92210284Sjmallett uint32_t vid_high : 8; /**< 8-bits of the VLAN tag information */ 93210284Sjmallett uint32_t vid_low : 8; /**< 8 bits LSB of the VLAN tag information */ 94210284Sjmallett } s; 95210284Sjmallett } dw0; 96210284Sjmallett union 97210284Sjmallett { 98210284Sjmallett uint32_t u32; 99210284Sjmallett struct 100210284Sjmallett { 101210284Sjmallett uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 102210284Sjmallett 000 = Control frames used for CPU to CPU communications 103210284Sjmallett 001 = Unicast packet with destination resolved; The packet can be 104210284Sjmallett either Layer 2 unicast packet or L3 unicast packet that was 105210284Sjmallett routed in the ingress chip. 106210284Sjmallett 010 = Broadcast or unknown Unicast packet or unknown multicast, 107210284Sjmallett destined to all members of the VLAN 108210284Sjmallett 011 = L2 Multicast packet, destined to all ports of the group indicated 109210284Sjmallett in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 110210284Sjmallett 100 = IP Multicast packet, destined to all ports of the group indicated 111210284Sjmallett in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 112210284Sjmallett 101 = Reserved 113210284Sjmallett 110 = Reserved 114210284Sjmallett 111 = Reserved */ 115210284Sjmallett uint32_t src_modid_low : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit 116210284Sjmallett 5 is in Byte 9 and bit 6 Is in Byte 1) */ 117210284Sjmallett uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 118210284Sjmallett on, else it represents the physical port the packet ingressed on. */ 119210284Sjmallett uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 120210284Sjmallett multicast (unknown L2 multicast and IPMC) packets. This field is used 121210284Sjmallett when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 122210284Sjmallett For registered L2 multicast packets: 123210284Sjmallett PFM= 0 � Flood to VLAN 124210284Sjmallett PFM= 1 or 2 � Send to group members in the L2MC table 125210284Sjmallett For unregistered L2 multicast packets: 126210284Sjmallett PFM= 0 or 1 � Flood to VLAN 127210284Sjmallett PFM= 2 � Drop the packet */ 128210284Sjmallett uint32_t priority : 3; /**< This is the internal priority of the packet. This internal priority will go through 129210284Sjmallett COS_SEL mapping registers to map to the actual MMU queues. */ 130210284Sjmallett uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */ 131210284Sjmallett uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */ 132210284Sjmallett uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following 133210284Sjmallett encodings are to make it backward compatible: 134210284Sjmallett {CNG_HIGH, CNG_LOW] - COLOR 135210284Sjmallett [0, 0] � Packet is green 136210284Sjmallett [0, 1] � Packet is red 137210284Sjmallett [1, 1] � Packet is yellow 138210284Sjmallett [1, 0] � Undefined */ 139210284Sjmallett uint32_t header_type : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header 140210284Sjmallett 00 = Overlay 1 (default) 141210284Sjmallett 01 = Overlay 2 (Classification Tag) 142210284Sjmallett 10 = Reserved 143210284Sjmallett 11 = Reserved */ 144210284Sjmallett } s; 145210284Sjmallett } dw1; 146210284Sjmallett union 147210284Sjmallett { 148210284Sjmallett uint32_t u32; 149210284Sjmallett struct 150210284Sjmallett { 151210284Sjmallett uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 152210284Sjmallett packet was switched and only needs to be mirrored. */ 153210284Sjmallett uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 154210284Sjmallett may still need to be switched. */ 155210284Sjmallett uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 156210284Sjmallett needs to be mirrored. */ 157210284Sjmallett uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 158210284Sjmallett ingressed the system. */ 159210284Sjmallett uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 160210284Sjmallett DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 161210284Sjmallett uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 162210284Sjmallett group. */ 163210284Sjmallett uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */ 164210284Sjmallett uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 165210284Sjmallett added field. */ 166210284Sjmallett uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 167210284Sjmallett uint32_t dst_modid_5 : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6 168210284Sjmallett is in byte 1) */ 169210284Sjmallett uint32_t src_modid_5 : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in 170210284Sjmallett byte 1) */ 171210284Sjmallett uint32_t vc_label_0_15 : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */ 172210284Sjmallett } o1; 173210284Sjmallett struct 174210284Sjmallett { 175210284Sjmallett uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 176210284Sjmallett uint32_t reserved_0_15 : 16; 177210284Sjmallett 178210284Sjmallett } o2; 179210284Sjmallett } dw2; 180210284Sjmallett} cvmx_higig_header_t; 181210284Sjmallett 182215990Sjmalletttypedef struct 183215990Sjmallett{ 184215990Sjmallett union 185215990Sjmallett { 186215990Sjmallett uint32_t u32; 187215990Sjmallett struct 188215990Sjmallett { 189215990Sjmallett uint32_t k_sop : 8; /**< The delimiter indicating the start of a packet transmission */ 190215990Sjmallett uint32_t reserved_21_23 : 3; 191215990Sjmallett uint32_t mcst : 1; /**< MCST indicates whether the packet should be unicast or 192215990Sjmallett multicast forwarded through the XGS switching fabric 193215990Sjmallett - 0: Unicast 194215990Sjmallett - 1: Mulitcast */ 195215990Sjmallett uint32_t tc : 4; /**< Traffic Class [3:0] indicates the distinctive Quality of Service (QoS) 196215990Sjmallett the switching fabric will provide when forwarding the packet 197215990Sjmallett through the fabric */ 198215990Sjmallett uint32_t dst_modid_mgid : 8; /**< When MCST=0, this field indicates the destination XGS module to 199215990Sjmallett which the packet will be delivered. When MCST=1, this field indicates 200215990Sjmallett higher order bits of the Multicast Group ID. */ 201215990Sjmallett uint32_t dst_pid_mgid : 8; /**< When MCST=0, this field indicates a port associated with the 202215990Sjmallett module indicated by the DST_MODID, through which the packet 203215990Sjmallett will exit the system. When MCST=1, this field indicates lower order 204215990Sjmallett bits of the Multicast Group ID */ 205215990Sjmallett } s; 206215990Sjmallett } dw0; 207215990Sjmallett union 208215990Sjmallett { 209215990Sjmallett uint32_t u32; 210215990Sjmallett struct 211215990Sjmallett { 212215990Sjmallett uint32_t src_modid : 8; /**< Source Module ID indicates the source XGS module from which 213215990Sjmallett the packet is originated. (It can also be used for the fabric multicast 214215990Sjmallett load balancing purpose.) */ 215215990Sjmallett uint32_t src_pid : 8; /**< Source Port ID indicates a port associated with the module 216215990Sjmallett indicated by the SRC_MODID, through which the packet has 217215990Sjmallett entered the system */ 218215990Sjmallett uint32_t lbid : 8; /**< Load Balancing ID indicates a packet flow hashing index 219215990Sjmallett computed by the ingress XGS module for statistical distribution of 220215990Sjmallett packet flows through a multipath fabric */ 221215990Sjmallett uint32_t dp : 2; /**< Drop Precedence indicates the traffic rate violation status of the 222215990Sjmallett packet measured by the ingress module. 223215990Sjmallett - 00: GREEN 224215990Sjmallett - 01: RED 225215990Sjmallett - 10: Reserved 226215990Sjmallett - 11: Yellow */ 227215990Sjmallett uint32_t reserved_3_5 : 3; 228215990Sjmallett uint32_t ppd_type : 3; /**< Packet Processing Descriptor Type 229215990Sjmallett - 000: PPD Overlay1 230215990Sjmallett - 001: PPD Overlay2 231215990Sjmallett - 010~111: Reserved */ 232215990Sjmallett } s; 233215990Sjmallett } dw1; 234215990Sjmallett union 235215990Sjmallett { 236215990Sjmallett uint32_t u32; 237215990Sjmallett struct 238215990Sjmallett { 239215990Sjmallett uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 240215990Sjmallett group. */ 241215990Sjmallett uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 242215990Sjmallett DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 243215990Sjmallett uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 244215990Sjmallett ingressed the system. */ 245215990Sjmallett uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 246215990Sjmallett needs to be mirrored. */ 247215990Sjmallett uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 248215990Sjmallett may still need to be switched. */ 249215990Sjmallett uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 250215990Sjmallett packet was switched and only needs to be mirrored. */ 251215990Sjmallett uint32_t reserved_22_23 : 2; 252215990Sjmallett uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 253215990Sjmallett uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 254215990Sjmallett added field. */ 255215990Sjmallett uint32_t vc_label : 20; /**< Refer to the HiGig+ Architecture Specification */ 256215990Sjmallett } o1; 257215990Sjmallett struct 258215990Sjmallett { 259215990Sjmallett uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 260215990Sjmallett uint32_t reserved_0_15 : 16; 261215990Sjmallett } o2; 262215990Sjmallett } dw2; 263215990Sjmallett union 264215990Sjmallett { 265215990Sjmallett uint32_t u32; 266215990Sjmallett struct 267215990Sjmallett { 268215990Sjmallett uint32_t vid : 16; /**< VLAN tag information */ 269215990Sjmallett uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 270215990Sjmallett multicast (unknown L2 multicast and IPMC) packets. This field is used 271215990Sjmallett when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 272215990Sjmallett For registered L2 multicast packets: 273215990Sjmallett PFM= 0 � Flood to VLAN 274215990Sjmallett PFM= 1 or 2 � Send to group members in the L2MC table 275215990Sjmallett For unregistered L2 multicast packets: 276215990Sjmallett PFM= 0 or 1 � Flood to VLAN 277215990Sjmallett PFM= 2 � Drop the packet */ 278215990Sjmallett uint32_t src_t : 1; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 279215990Sjmallett on, else it represents the physical port the packet ingressed on. */ 280215990Sjmallett uint32_t reserved_11_12 : 2; 281215990Sjmallett uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 282215990Sjmallett 000 = Control frames used for CPU to CPU communications 283215990Sjmallett 001 = Unicast packet with destination resolved; The packet can be 284215990Sjmallett either Layer 2 unicast packet or L3 unicast packet that was 285215990Sjmallett routed in the ingress chip. 286215990Sjmallett 010 = Broadcast or unknown Unicast packet or unknown multicast, 287215990Sjmallett destined to all members of the VLAN 288215990Sjmallett 011 = L2 Multicast packet, destined to all ports of the group indicated 289215990Sjmallett in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 290215990Sjmallett 100 = IP Multicast packet, destined to all ports of the group indicated 291215990Sjmallett in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 292215990Sjmallett 101 = Reserved 293215990Sjmallett 110 = Reserved 294215990Sjmallett 111 = Reserved */ 295215990Sjmallett uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 296215990Sjmallett to the standard 12-bytes of XGS HiGig header. Each unit represents 4 297215990Sjmallett bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 298215990Sjmallett and b'111' are reserved. For HGI field value of b'01' this field should be 299215990Sjmallett b'01'. For all other values of HGI it is don't care. */ 300215990Sjmallett uint32_t reserved_0_4 : 5; 301215990Sjmallett } s; 302215990Sjmallett } dw3; 303215990Sjmallett} cvmx_higig2_header_t; 304210284Sjmallett 305215990Sjmallett 306210284Sjmallett/** 307210284Sjmallett * Initialize the HiGig aspects of a XAUI interface. This function 308210284Sjmallett * should be called before the cvmx-helper generic init. 309210284Sjmallett * 310210284Sjmallett * @param interface Interface to initialize HiGig on (0-1) 311210284Sjmallett * @param enable_higig2 312210284Sjmallett * Non zero to enable HiGig2 support. Zero to support HiGig 313210284Sjmallett * and HiGig+. 314210284Sjmallett * 315210284Sjmallett * @return Zero on success, negative on failure 316210284Sjmallett */ 317210284Sjmallettstatic inline int cvmx_higig_initialize(int interface, int enable_higig2) 318210284Sjmallett{ 319210284Sjmallett cvmx_pip_prt_cfgx_t pip_prt_cfg; 320210284Sjmallett cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp; 321210284Sjmallett cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt; 322210284Sjmallett cvmx_gmxx_txx_append_t gmx_tx_append; 323210284Sjmallett cvmx_gmxx_tx_ifg_t gmx_tx_ifg; 324210284Sjmallett cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp; 325210284Sjmallett cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl; 326210284Sjmallett cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl; 327210284Sjmallett int i; 328210284Sjmallett int header_size = (enable_higig2) ? 16 : 12; 329210284Sjmallett 330210284Sjmallett /* Setup PIP to handle HiGig */ 331210284Sjmallett pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(interface*16)); 332210284Sjmallett pip_prt_cfg.s.dsa_en = 0; 333210284Sjmallett pip_prt_cfg.s.higig_en = 1; 334210284Sjmallett pip_prt_cfg.s.hg_qos = 1; 335210284Sjmallett pip_prt_cfg.s.skip = header_size; 336210284Sjmallett cvmx_write_csr(CVMX_PIP_PRT_CFGX(interface*16), pip_prt_cfg.u64); 337210284Sjmallett 338210284Sjmallett /* Setup some sample QoS defaults. These can be changed later */ 339210284Sjmallett for (i=0; i<64; i++) 340210284Sjmallett { 341210284Sjmallett cvmx_pip_hg_pri_qos_t pip_hg_pri_qos; 342210284Sjmallett pip_hg_pri_qos.u64 = 0; 343210284Sjmallett pip_hg_pri_qos.s.up_qos = 1; 344210284Sjmallett pip_hg_pri_qos.s.pri = i; 345210284Sjmallett pip_hg_pri_qos.s.qos = i&7; 346210284Sjmallett cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64); 347210284Sjmallett } 348210284Sjmallett 349210284Sjmallett /* Setup GMX RX to treat the HiGig header as user data to ignore */ 350210284Sjmallett gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface)); 351210284Sjmallett gmx_rx_udd_skp.s.len = header_size; 352210284Sjmallett gmx_rx_udd_skp.s.fcssel = 0; 353210284Sjmallett cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64); 354210284Sjmallett 355210284Sjmallett /* Disable GMX preamble checking */ 356210284Sjmallett gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface)); 357210284Sjmallett gmx_rx_frm_ctl.s.pre_chk = 0; 358210284Sjmallett cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64); 359210284Sjmallett 360210284Sjmallett /* Setup GMX TX to pad properly min sized packets */ 361210284Sjmallett gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface)); 362210284Sjmallett gmx_tx_min_pkt.s.min_size = 59 + header_size; 363210284Sjmallett cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64); 364210284Sjmallett 365210284Sjmallett /* Setup GMX TX to not add a preamble */ 366210284Sjmallett gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface)); 367210284Sjmallett gmx_tx_append.s.preamble = 0; 368210284Sjmallett cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64); 369210284Sjmallett 370210284Sjmallett /* Reduce the inter frame gap to 8 bytes */ 371210284Sjmallett gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface)); 372210284Sjmallett gmx_tx_ifg.s.ifg1 = 4; 373210284Sjmallett gmx_tx_ifg.s.ifg2 = 4; 374210284Sjmallett cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64); 375210284Sjmallett 376210284Sjmallett /* Disable GMX backpressure */ 377210284Sjmallett gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); 378210284Sjmallett gmx_tx_ovr_bp.s.bp = 0; 379210284Sjmallett gmx_tx_ovr_bp.s.en = 0xf; 380210284Sjmallett gmx_tx_ovr_bp.s.ign_full = 0xf; 381210284Sjmallett cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); 382210284Sjmallett 383210284Sjmallett if (enable_higig2) 384210284Sjmallett { 385210284Sjmallett /* Enable HiGig2 support and forwarding of virtual port backpressure 386210284Sjmallett to PKO */ 387210284Sjmallett cvmx_gmxx_hg2_control_t gmx_hg2_control; 388210284Sjmallett gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); 389210284Sjmallett gmx_hg2_control.s.hg2rx_en = 1; 390210284Sjmallett gmx_hg2_control.s.hg2tx_en = 1; 391210284Sjmallett gmx_hg2_control.s.logl_en = 0xffff; 392210284Sjmallett gmx_hg2_control.s.phys_en = 1; 393210284Sjmallett cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64); 394210284Sjmallett } 395210284Sjmallett 396210284Sjmallett /* Enable HiGig */ 397210284Sjmallett gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); 398210284Sjmallett gmx_tx_xaui_ctl.s.hg_en = 1; 399210284Sjmallett cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64); 400210284Sjmallett 401210284Sjmallett return 0; 402210284Sjmallett} 403210284Sjmallett 404210284Sjmallett#ifdef __cplusplus 405210284Sjmallett} 406210284Sjmallett#endif 407210284Sjmallett 408210284Sjmallett#endif // __CVMX_HIGIG_H__ 409