1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-gpio-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon gpio. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_GPIO_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_GPIO_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 62215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) || 63215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) || 64215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) || 65215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 66215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))))) 67215976Sjmallett cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset); 68215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8; 69215976Sjmallett} 70215976Sjmallett#else 71215976Sjmallett#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8) 72215976Sjmallett#endif 73215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 74215976Sjmallett#define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC() 75215976Sjmallettstatic inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void) 76215976Sjmallett{ 77215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 78215976Sjmallett cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n"); 79215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008A8ull); 80215976Sjmallett} 81215976Sjmallett#else 82215976Sjmallett#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull)) 83215976Sjmallett#endif 84215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 85215976Sjmallettstatic inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset) 86215976Sjmallett{ 87215976Sjmallett if (!( 88215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 89215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) || 90215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))))) 91215976Sjmallett cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset); 92215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8; 93215976Sjmallett} 94215976Sjmallett#else 95215976Sjmallett#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8) 96215976Sjmallett#endif 97215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 98215976Sjmallettstatic inline uint64_t CVMX_GPIO_CLK_QLMX(unsigned long offset) 99215976Sjmallett{ 100215976Sjmallett if (!( 101215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 102215976Sjmallett cvmx_warn("CVMX_GPIO_CLK_QLMX(%lu) is invalid on this chip\n", offset); 103215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8; 104215976Sjmallett} 105215976Sjmallett#else 106215976Sjmallett#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8) 107215976Sjmallett#endif 108215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 109215976Sjmallett#define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC() 110215976Sjmallettstatic inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void) 111215976Sjmallett{ 112215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 113215976Sjmallett cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n"); 114215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008A0ull); 115215976Sjmallett} 116215976Sjmallett#else 117215976Sjmallett#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) 118215976Sjmallett#endif 119215976Sjmallett#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull)) 120215976Sjmallett#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull)) 121215976Sjmallett#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull)) 122215976Sjmallett#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull)) 123215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124215976Sjmallettstatic inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset) 125215976Sjmallett{ 126215976Sjmallett if (!( 127215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) || 128215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) || 129215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23)))))) 130215976Sjmallett cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset); 131215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16; 132215976Sjmallett} 133215976Sjmallett#else 134215976Sjmallett#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16) 135215976Sjmallett#endif 136215976Sjmallett 137215976Sjmallett/** 138215976Sjmallett * cvmx_gpio_bit_cfg# 139215976Sjmallett */ 140215976Sjmallettunion cvmx_gpio_bit_cfgx 141215976Sjmallett{ 142215976Sjmallett uint64_t u64; 143215976Sjmallett struct cvmx_gpio_bit_cfgx_s 144215976Sjmallett { 145215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 146215976Sjmallett uint64_t reserved_17_63 : 47; 147215976Sjmallett uint64_t synce_sel : 2; /**< Selects the QLM clock output 148215976Sjmallett x0=Normal GPIO output 149215976Sjmallett 01=GPIO QLM clock selected by GPIO_CLK_QLM0 150215976Sjmallett 11=GPIO QLM clock selected by GPIO_CLK_QLM1 */ 151215976Sjmallett uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */ 152215976Sjmallett uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */ 153215976Sjmallett uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */ 154215976Sjmallett uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */ 155215976Sjmallett uint64_t int_type : 1; /**< Type of interrupt 156215976Sjmallett 0 = level (default) 157215976Sjmallett 1 = rising edge */ 158215976Sjmallett uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */ 159215976Sjmallett uint64_t rx_xor : 1; /**< Invert the GPIO pin */ 160215976Sjmallett uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */ 161215976Sjmallett#else 162215976Sjmallett uint64_t tx_oe : 1; 163215976Sjmallett uint64_t rx_xor : 1; 164215976Sjmallett uint64_t int_en : 1; 165215976Sjmallett uint64_t int_type : 1; 166215976Sjmallett uint64_t fil_cnt : 4; 167215976Sjmallett uint64_t fil_sel : 4; 168215976Sjmallett uint64_t clk_sel : 2; 169215976Sjmallett uint64_t clk_gen : 1; 170215976Sjmallett uint64_t synce_sel : 2; 171215976Sjmallett uint64_t reserved_17_63 : 47; 172215976Sjmallett#endif 173215976Sjmallett } s; 174215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx 175215976Sjmallett { 176215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 177215976Sjmallett uint64_t reserved_12_63 : 52; 178215976Sjmallett uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */ 179215976Sjmallett uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */ 180215976Sjmallett uint64_t int_type : 1; /**< Type of interrupt 181215976Sjmallett 0 = level (default) 182215976Sjmallett 1 = rising edge */ 183215976Sjmallett uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */ 184215976Sjmallett uint64_t rx_xor : 1; /**< Invert the GPIO pin */ 185215976Sjmallett uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */ 186215976Sjmallett#else 187215976Sjmallett uint64_t tx_oe : 1; 188215976Sjmallett uint64_t rx_xor : 1; 189215976Sjmallett uint64_t int_en : 1; 190215976Sjmallett uint64_t int_type : 1; 191215976Sjmallett uint64_t fil_cnt : 4; 192215976Sjmallett uint64_t fil_sel : 4; 193215976Sjmallett uint64_t reserved_12_63 : 52; 194215976Sjmallett#endif 195215976Sjmallett } cn30xx; 196215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn31xx; 197215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; 198215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; 199215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; 200215976Sjmallett struct cvmx_gpio_bit_cfgx_cn52xx 201215976Sjmallett { 202215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 203215976Sjmallett uint64_t reserved_15_63 : 49; 204215976Sjmallett uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */ 205215976Sjmallett uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */ 206215976Sjmallett uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */ 207215976Sjmallett uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */ 208215976Sjmallett uint64_t int_type : 1; /**< Type of interrupt 209215976Sjmallett 0 = level (default) 210215976Sjmallett 1 = rising edge */ 211215976Sjmallett uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */ 212215976Sjmallett uint64_t rx_xor : 1; /**< Invert the GPIO pin */ 213215976Sjmallett uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */ 214215976Sjmallett#else 215215976Sjmallett uint64_t tx_oe : 1; 216215976Sjmallett uint64_t rx_xor : 1; 217215976Sjmallett uint64_t int_en : 1; 218215976Sjmallett uint64_t int_type : 1; 219215976Sjmallett uint64_t fil_cnt : 4; 220215976Sjmallett uint64_t fil_sel : 4; 221215976Sjmallett uint64_t clk_sel : 2; 222215976Sjmallett uint64_t clk_gen : 1; 223215976Sjmallett uint64_t reserved_15_63 : 49; 224215976Sjmallett#endif 225215976Sjmallett } cn52xx; 226215976Sjmallett struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1; 227215976Sjmallett struct cvmx_gpio_bit_cfgx_cn52xx cn56xx; 228215976Sjmallett struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1; 229215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; 230215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; 231215976Sjmallett struct cvmx_gpio_bit_cfgx_s cn63xx; 232215976Sjmallett struct cvmx_gpio_bit_cfgx_s cn63xxp1; 233215976Sjmallett}; 234215976Sjmalletttypedef union cvmx_gpio_bit_cfgx cvmx_gpio_bit_cfgx_t; 235215976Sjmallett 236215976Sjmallett/** 237215976Sjmallett * cvmx_gpio_boot_ena 238215976Sjmallett */ 239215976Sjmallettunion cvmx_gpio_boot_ena 240215976Sjmallett{ 241215976Sjmallett uint64_t u64; 242215976Sjmallett struct cvmx_gpio_boot_ena_s 243215976Sjmallett { 244215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 245215976Sjmallett uint64_t reserved_12_63 : 52; 246215976Sjmallett uint64_t boot_ena : 4; /**< Drive boot bus chip enables [7:4] on gpio [11:8] */ 247215976Sjmallett uint64_t reserved_0_7 : 8; 248215976Sjmallett#else 249215976Sjmallett uint64_t reserved_0_7 : 8; 250215976Sjmallett uint64_t boot_ena : 4; 251215976Sjmallett uint64_t reserved_12_63 : 52; 252215976Sjmallett#endif 253215976Sjmallett } s; 254215976Sjmallett struct cvmx_gpio_boot_ena_s cn30xx; 255215976Sjmallett struct cvmx_gpio_boot_ena_s cn31xx; 256215976Sjmallett struct cvmx_gpio_boot_ena_s cn50xx; 257215976Sjmallett}; 258215976Sjmalletttypedef union cvmx_gpio_boot_ena cvmx_gpio_boot_ena_t; 259215976Sjmallett 260215976Sjmallett/** 261215976Sjmallett * cvmx_gpio_clk_gen# 262215976Sjmallett */ 263215976Sjmallettunion cvmx_gpio_clk_genx 264215976Sjmallett{ 265215976Sjmallett uint64_t u64; 266215976Sjmallett struct cvmx_gpio_clk_genx_s 267215976Sjmallett { 268215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 269215976Sjmallett uint64_t reserved_32_63 : 32; 270215976Sjmallett uint64_t n : 32; /**< Determines the frequency of the GPIO clk generator 271215976Sjmallett NOTE: Fgpio_clk = Feclk * N / 2^32 272215976Sjmallett N = (Fgpio_clk / Feclk) * 2^32 273215976Sjmallett NOTE: writing N == 0 stops the clock generator 274215976Sjmallett N should be <= 2^31-1. */ 275215976Sjmallett#else 276215976Sjmallett uint64_t n : 32; 277215976Sjmallett uint64_t reserved_32_63 : 32; 278215976Sjmallett#endif 279215976Sjmallett } s; 280215976Sjmallett struct cvmx_gpio_clk_genx_s cn52xx; 281215976Sjmallett struct cvmx_gpio_clk_genx_s cn52xxp1; 282215976Sjmallett struct cvmx_gpio_clk_genx_s cn56xx; 283215976Sjmallett struct cvmx_gpio_clk_genx_s cn56xxp1; 284215976Sjmallett struct cvmx_gpio_clk_genx_s cn63xx; 285215976Sjmallett struct cvmx_gpio_clk_genx_s cn63xxp1; 286215976Sjmallett}; 287215976Sjmalletttypedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t; 288215976Sjmallett 289215976Sjmallett/** 290215976Sjmallett * cvmx_gpio_clk_qlm# 291215976Sjmallett * 292215976Sjmallett * Notes: 293215976Sjmallett * Clock speed output for different modes ... 294215976Sjmallett * 295215976Sjmallett * Speed With Speed with 296215976Sjmallett * SERDES speed (Gbaud) DIV=0 (MHz) DIV=1 (MHz) 297215976Sjmallett * ********************************************************** 298215976Sjmallett * 1.25 62.5 31.25 299215976Sjmallett * 2.5 125 62.5 300215976Sjmallett * 3.125 156.25 78.125 301215976Sjmallett * 5.0 250 125 302215976Sjmallett * 6.25 312.5 156.25 303215976Sjmallett */ 304215976Sjmallettunion cvmx_gpio_clk_qlmx 305215976Sjmallett{ 306215976Sjmallett uint64_t u64; 307215976Sjmallett struct cvmx_gpio_clk_qlmx_s 308215976Sjmallett { 309215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 310215976Sjmallett uint64_t reserved_3_63 : 61; 311215976Sjmallett uint64_t div : 1; /**< Internal clock divider 312215976Sjmallett 0=DIV2 313215976Sjmallett 1=DIV4 */ 314215976Sjmallett uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLM2 to use as 315215976Sjmallett the GPIO internal QLMx clock. The GPIO block can 316215976Sjmallett support upto two unique clocks to send out any 317215976Sjmallett GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL] 318215976Sjmallett The clock can either be a divided by 2 or divide 319215976Sjmallett by 4 of the selected RX lane clock. */ 320215976Sjmallett#else 321215976Sjmallett uint64_t lane_sel : 2; 322215976Sjmallett uint64_t div : 1; 323215976Sjmallett uint64_t reserved_3_63 : 61; 324215976Sjmallett#endif 325215976Sjmallett } s; 326215976Sjmallett struct cvmx_gpio_clk_qlmx_s cn63xx; 327215976Sjmallett struct cvmx_gpio_clk_qlmx_s cn63xxp1; 328215976Sjmallett}; 329215976Sjmalletttypedef union cvmx_gpio_clk_qlmx cvmx_gpio_clk_qlmx_t; 330215976Sjmallett 331215976Sjmallett/** 332215976Sjmallett * cvmx_gpio_dbg_ena 333215976Sjmallett */ 334215976Sjmallettunion cvmx_gpio_dbg_ena 335215976Sjmallett{ 336215976Sjmallett uint64_t u64; 337215976Sjmallett struct cvmx_gpio_dbg_ena_s 338215976Sjmallett { 339215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 340215976Sjmallett uint64_t reserved_21_63 : 43; 341215976Sjmallett uint64_t dbg_ena : 21; /**< Enable the debug port to be driven on the gpio */ 342215976Sjmallett#else 343215976Sjmallett uint64_t dbg_ena : 21; 344215976Sjmallett uint64_t reserved_21_63 : 43; 345215976Sjmallett#endif 346215976Sjmallett } s; 347215976Sjmallett struct cvmx_gpio_dbg_ena_s cn30xx; 348215976Sjmallett struct cvmx_gpio_dbg_ena_s cn31xx; 349215976Sjmallett struct cvmx_gpio_dbg_ena_s cn50xx; 350215976Sjmallett}; 351215976Sjmalletttypedef union cvmx_gpio_dbg_ena cvmx_gpio_dbg_ena_t; 352215976Sjmallett 353215976Sjmallett/** 354215976Sjmallett * cvmx_gpio_int_clr 355215976Sjmallett */ 356215976Sjmallettunion cvmx_gpio_int_clr 357215976Sjmallett{ 358215976Sjmallett uint64_t u64; 359215976Sjmallett struct cvmx_gpio_int_clr_s 360215976Sjmallett { 361215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 362215976Sjmallett uint64_t reserved_16_63 : 48; 363215976Sjmallett uint64_t type : 16; /**< Clear the interrupt rising edge detector */ 364215976Sjmallett#else 365215976Sjmallett uint64_t type : 16; 366215976Sjmallett uint64_t reserved_16_63 : 48; 367215976Sjmallett#endif 368215976Sjmallett } s; 369215976Sjmallett struct cvmx_gpio_int_clr_s cn30xx; 370215976Sjmallett struct cvmx_gpio_int_clr_s cn31xx; 371215976Sjmallett struct cvmx_gpio_int_clr_s cn38xx; 372215976Sjmallett struct cvmx_gpio_int_clr_s cn38xxp2; 373215976Sjmallett struct cvmx_gpio_int_clr_s cn50xx; 374215976Sjmallett struct cvmx_gpio_int_clr_s cn52xx; 375215976Sjmallett struct cvmx_gpio_int_clr_s cn52xxp1; 376215976Sjmallett struct cvmx_gpio_int_clr_s cn56xx; 377215976Sjmallett struct cvmx_gpio_int_clr_s cn56xxp1; 378215976Sjmallett struct cvmx_gpio_int_clr_s cn58xx; 379215976Sjmallett struct cvmx_gpio_int_clr_s cn58xxp1; 380215976Sjmallett struct cvmx_gpio_int_clr_s cn63xx; 381215976Sjmallett struct cvmx_gpio_int_clr_s cn63xxp1; 382215976Sjmallett}; 383215976Sjmalletttypedef union cvmx_gpio_int_clr cvmx_gpio_int_clr_t; 384215976Sjmallett 385215976Sjmallett/** 386215976Sjmallett * cvmx_gpio_rx_dat 387215976Sjmallett */ 388215976Sjmallettunion cvmx_gpio_rx_dat 389215976Sjmallett{ 390215976Sjmallett uint64_t u64; 391215976Sjmallett struct cvmx_gpio_rx_dat_s 392215976Sjmallett { 393215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 394215976Sjmallett uint64_t reserved_24_63 : 40; 395215976Sjmallett uint64_t dat : 24; /**< GPIO Read Data */ 396215976Sjmallett#else 397215976Sjmallett uint64_t dat : 24; 398215976Sjmallett uint64_t reserved_24_63 : 40; 399215976Sjmallett#endif 400215976Sjmallett } s; 401215976Sjmallett struct cvmx_gpio_rx_dat_s cn30xx; 402215976Sjmallett struct cvmx_gpio_rx_dat_s cn31xx; 403215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx 404215976Sjmallett { 405215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 406215976Sjmallett uint64_t reserved_16_63 : 48; 407215976Sjmallett uint64_t dat : 16; /**< GPIO Read Data */ 408215976Sjmallett#else 409215976Sjmallett uint64_t dat : 16; 410215976Sjmallett uint64_t reserved_16_63 : 48; 411215976Sjmallett#endif 412215976Sjmallett } cn38xx; 413215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn38xxp2; 414215976Sjmallett struct cvmx_gpio_rx_dat_s cn50xx; 415215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn52xx; 416215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn52xxp1; 417215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn56xx; 418215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; 419215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn58xx; 420215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; 421215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn63xx; 422215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn63xxp1; 423215976Sjmallett}; 424215976Sjmalletttypedef union cvmx_gpio_rx_dat cvmx_gpio_rx_dat_t; 425215976Sjmallett 426215976Sjmallett/** 427215976Sjmallett * cvmx_gpio_tx_clr 428215976Sjmallett */ 429215976Sjmallettunion cvmx_gpio_tx_clr 430215976Sjmallett{ 431215976Sjmallett uint64_t u64; 432215976Sjmallett struct cvmx_gpio_tx_clr_s 433215976Sjmallett { 434215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 435215976Sjmallett uint64_t reserved_24_63 : 40; 436215976Sjmallett uint64_t clr : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set 437215976Sjmallett to '0'. When read, CLR returns the GPIO_TX_DAT 438215976Sjmallett storage. */ 439215976Sjmallett#else 440215976Sjmallett uint64_t clr : 24; 441215976Sjmallett uint64_t reserved_24_63 : 40; 442215976Sjmallett#endif 443215976Sjmallett } s; 444215976Sjmallett struct cvmx_gpio_tx_clr_s cn30xx; 445215976Sjmallett struct cvmx_gpio_tx_clr_s cn31xx; 446215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx 447215976Sjmallett { 448215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 449215976Sjmallett uint64_t reserved_16_63 : 48; 450215976Sjmallett uint64_t clr : 16; /**< Bit mask to indicate which bits to drive to '0'. */ 451215976Sjmallett#else 452215976Sjmallett uint64_t clr : 16; 453215976Sjmallett uint64_t reserved_16_63 : 48; 454215976Sjmallett#endif 455215976Sjmallett } cn38xx; 456215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn38xxp2; 457215976Sjmallett struct cvmx_gpio_tx_clr_s cn50xx; 458215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn52xx; 459215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn52xxp1; 460215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn56xx; 461215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; 462215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn58xx; 463215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; 464215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn63xx; 465215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn63xxp1; 466215976Sjmallett}; 467215976Sjmalletttypedef union cvmx_gpio_tx_clr cvmx_gpio_tx_clr_t; 468215976Sjmallett 469215976Sjmallett/** 470215976Sjmallett * cvmx_gpio_tx_set 471215976Sjmallett */ 472215976Sjmallettunion cvmx_gpio_tx_set 473215976Sjmallett{ 474215976Sjmallett uint64_t u64; 475215976Sjmallett struct cvmx_gpio_tx_set_s 476215976Sjmallett { 477215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 478215976Sjmallett uint64_t reserved_24_63 : 40; 479215976Sjmallett uint64_t set : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set 480215976Sjmallett to '1'. When read, SET returns the GPIO_TX_DAT 481215976Sjmallett storage. */ 482215976Sjmallett#else 483215976Sjmallett uint64_t set : 24; 484215976Sjmallett uint64_t reserved_24_63 : 40; 485215976Sjmallett#endif 486215976Sjmallett } s; 487215976Sjmallett struct cvmx_gpio_tx_set_s cn30xx; 488215976Sjmallett struct cvmx_gpio_tx_set_s cn31xx; 489215976Sjmallett struct cvmx_gpio_tx_set_cn38xx 490215976Sjmallett { 491215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 492215976Sjmallett uint64_t reserved_16_63 : 48; 493215976Sjmallett uint64_t set : 16; /**< Bit mask to indicate which bits to drive to '1'. */ 494215976Sjmallett#else 495215976Sjmallett uint64_t set : 16; 496215976Sjmallett uint64_t reserved_16_63 : 48; 497215976Sjmallett#endif 498215976Sjmallett } cn38xx; 499215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn38xxp2; 500215976Sjmallett struct cvmx_gpio_tx_set_s cn50xx; 501215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn52xx; 502215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn52xxp1; 503215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn56xx; 504215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn56xxp1; 505215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn58xx; 506215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn58xxp1; 507215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn63xx; 508215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn63xxp1; 509215976Sjmallett}; 510215976Sjmalletttypedef union cvmx_gpio_tx_set cvmx_gpio_tx_set_t; 511215976Sjmallett 512215976Sjmallett/** 513215976Sjmallett * cvmx_gpio_xbit_cfg# 514215976Sjmallett */ 515215976Sjmallettunion cvmx_gpio_xbit_cfgx 516215976Sjmallett{ 517215976Sjmallett uint64_t u64; 518215976Sjmallett struct cvmx_gpio_xbit_cfgx_s 519215976Sjmallett { 520215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 521215976Sjmallett uint64_t reserved_12_63 : 52; 522215976Sjmallett uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */ 523215976Sjmallett uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */ 524215976Sjmallett uint64_t reserved_2_3 : 2; 525215976Sjmallett uint64_t rx_xor : 1; /**< Invert the GPIO pin */ 526215976Sjmallett uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */ 527215976Sjmallett#else 528215976Sjmallett uint64_t tx_oe : 1; 529215976Sjmallett uint64_t rx_xor : 1; 530215976Sjmallett uint64_t reserved_2_3 : 2; 531215976Sjmallett uint64_t fil_cnt : 4; 532215976Sjmallett uint64_t fil_sel : 4; 533215976Sjmallett uint64_t reserved_12_63 : 52; 534215976Sjmallett#endif 535215976Sjmallett } s; 536215976Sjmallett struct cvmx_gpio_xbit_cfgx_s cn30xx; 537215976Sjmallett struct cvmx_gpio_xbit_cfgx_s cn31xx; 538215976Sjmallett struct cvmx_gpio_xbit_cfgx_s cn50xx; 539215976Sjmallett}; 540215976Sjmalletttypedef union cvmx_gpio_xbit_cfgx cvmx_gpio_xbit_cfgx_t; 541215976Sjmallett 542215976Sjmallett#endif 543