1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * @file 43215976Sjmallett * 44215976Sjmallett * Automatically generated error messages for cn58xxp1. 45215976Sjmallett * 46215976Sjmallett * This file is auto generated. Do not edit. 47215976Sjmallett * 48215976Sjmallett * <hr>$Revision$<hr> 49215976Sjmallett * 50215976Sjmallett * <hr><h2>Error tree for CN58XXP1</h2> 51215976Sjmallett * @dot 52215976Sjmallett * digraph cn58xxp1 53215976Sjmallett * { 54215976Sjmallett * rankdir=LR; 55215976Sjmallett * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica]; 56215976Sjmallett * edge [fontsize=7, font=helvitica]; 57215976Sjmallett * cvmx_root [label="ROOT|<root>root"]; 58215976Sjmallett * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"]; 59215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"]; 60215976Sjmallett * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"]; 61215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"]; 62215976Sjmallett * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"]; 63215976Sjmallett * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"]; 64215976Sjmallett * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"]; 65215976Sjmallett * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"]; 66215976Sjmallett * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"]; 67215976Sjmallett * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"]; 68215976Sjmallett * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"]; 69215976Sjmallett * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"]; 70215976Sjmallett * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"]; 71215976Sjmallett * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 72215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"]; 73215976Sjmallett * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 74215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"]; 75215976Sjmallett * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 76215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"]; 77215976Sjmallett * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 78215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"]; 79215976Sjmallett * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 80215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"]; 81215976Sjmallett * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"]; 82215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"]; 83215976Sjmallett * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 84215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"]; 85215976Sjmallett * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 86215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"]; 87215976Sjmallett * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 88215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"]; 89215976Sjmallett * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 90215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"]; 91215976Sjmallett * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 92215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"]; 93215976Sjmallett * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"]; 94215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"]; 95215976Sjmallett * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"]; 96215976Sjmallett * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"]; 97215976Sjmallett * cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"]; 98215976Sjmallett * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"]; 99215976Sjmallett * cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"]; 100215976Sjmallett * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"]; 101215976Sjmallett * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"]; 102215976Sjmallett * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"]; 103215976Sjmallett * cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"]; 104215976Sjmallett * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"]; 105215976Sjmallett * cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"]; 106215976Sjmallett * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"]; 107215976Sjmallett * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"]; 108215976Sjmallett * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"]; 109215976Sjmallett * cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"]; 110215976Sjmallett * cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"]; 111215976Sjmallett * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"]; 112215976Sjmallett * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"]; 113215976Sjmallett * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"]; 114215976Sjmallett * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"]; 115215976Sjmallett * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"]; 116215976Sjmallett * cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"]; 117215976Sjmallett * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"]; 118215976Sjmallett * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"]; 119215976Sjmallett * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"]; 120215976Sjmallett * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"]; 121215976Sjmallett * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"]; 122215976Sjmallett * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"]; 123215976Sjmallett * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"]; 124215976Sjmallett * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"]; 125215976Sjmallett * cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"]; 126215976Sjmallett * cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"]; 127215976Sjmallett * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"]; 128215976Sjmallett * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"]; 129215976Sjmallett * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"]; 130215976Sjmallett * cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"]; 131215976Sjmallett * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis]; 132215976Sjmallett * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis]; 133215976Sjmallett * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis]; 134215976Sjmallett * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis]; 135215976Sjmallett * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis]; 136215976Sjmallett * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis]; 137215976Sjmallett * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis]; 138215976Sjmallett * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis]; 139215976Sjmallett * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis]; 140215976Sjmallett * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis]; 141215976Sjmallett * cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis]; 142215976Sjmallett * cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis]; 143215976Sjmallett * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"]; 144215976Sjmallett * } 145215976Sjmallett * @enddot 146215976Sjmallett */ 147215976Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 148215976Sjmallett#include <asm/octeon/cvmx.h> 149215976Sjmallett#include <asm/octeon/cvmx-error.h> 150215976Sjmallett#include <asm/octeon/cvmx-error-custom.h> 151215976Sjmallett#include <asm/octeon/cvmx-csr-typedefs.h> 152215976Sjmallett#else 153215976Sjmallett#include "cvmx.h" 154215976Sjmallett#include "cvmx-error.h" 155215976Sjmallett#include "cvmx-error-custom.h" 156215976Sjmallett#endif 157215976Sjmallett 158215990Sjmallettint cvmx_error_initialize_cn58xxp1(void); 159215990Sjmallett 160215976Sjmallettint cvmx_error_initialize_cn58xxp1(void) 161215976Sjmallett{ 162215976Sjmallett cvmx_error_info_t info; 163215976Sjmallett int fail = 0; 164215976Sjmallett 165215976Sjmallett /* CVMX_CIU_INTX_SUM0(0) */ 166215976Sjmallett /* CVMX_CIU_INT_SUM1 */ 167215976Sjmallett /* CVMX_NPI_RSL_INT_BLOCKS */ 168215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 169215976Sjmallett info.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 170215976Sjmallett info.status_mask = 0; 171215976Sjmallett info.enable_addr = 0; 172215976Sjmallett info.enable_mask = 0; 173215976Sjmallett info.flags = 0; 174215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 175215976Sjmallett info.group_index = 0; 176215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 177215976Sjmallett info.parent.status_addr = 0; 178215976Sjmallett info.parent.status_mask = 0; 179215976Sjmallett info.func = __cvmx_error_decode; 180215976Sjmallett info.user_info = 0; 181215976Sjmallett fail |= cvmx_error_add(&info); 182215976Sjmallett 183215976Sjmallett /* CVMX_L2D_ERR */ 184215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 185215976Sjmallett info.status_addr = CVMX_L2D_ERR; 186215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 187215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 188215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 189215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 190215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 191215976Sjmallett info.group_index = 0; 192215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 193215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 194215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 195215976Sjmallett info.func = __cvmx_error_handle_l2d_err_sec_err; 196215976Sjmallett info.user_info = (long) 197215976Sjmallett "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n"; 198215976Sjmallett fail |= cvmx_error_add(&info); 199215976Sjmallett 200215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 201215976Sjmallett info.status_addr = CVMX_L2D_ERR; 202215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 203215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 204215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 205215976Sjmallett info.flags = 0; 206215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 207215976Sjmallett info.group_index = 0; 208215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 209215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 210215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 211215976Sjmallett info.func = __cvmx_error_handle_l2d_err_ded_err; 212215976Sjmallett info.user_info = (long) 213215976Sjmallett "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n"; 214215976Sjmallett fail |= cvmx_error_add(&info); 215215976Sjmallett 216215976Sjmallett /* CVMX_L2T_ERR */ 217215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 218215976Sjmallett info.status_addr = CVMX_L2T_ERR; 219215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 220215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 221215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 222215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 223215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 224215976Sjmallett info.group_index = 0; 225215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 226215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 227215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 228215976Sjmallett info.func = __cvmx_error_handle_l2t_err_sec_err; 229215976Sjmallett info.user_info = (long) 230215976Sjmallett "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n" 231215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 232215976Sjmallett " given index) are checked for single bit errors(SBEs).\n" 233215976Sjmallett " This bit is set if ANY of the 8 sets contains an SBE.\n" 234215976Sjmallett " SBEs are auto corrected in HW and generate an\n" 235215976Sjmallett " interrupt(if enabled).\n"; 236215976Sjmallett fail |= cvmx_error_add(&info); 237215976Sjmallett 238215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 239215976Sjmallett info.status_addr = CVMX_L2T_ERR; 240215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 241215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 242215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 243215976Sjmallett info.flags = 0; 244215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 245215976Sjmallett info.group_index = 0; 246215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 247215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 248215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 249215976Sjmallett info.func = __cvmx_error_handle_l2t_err_ded_err; 250215976Sjmallett info.user_info = (long) 251215976Sjmallett "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n" 252215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 253215976Sjmallett " given index) are checked for double bit errors(DBEs).\n" 254215976Sjmallett " This bit is set if ANY of the 8 sets contains a DBE.\n" 255215976Sjmallett " DBEs also generated an interrupt(if enabled).\n"; 256215976Sjmallett fail |= cvmx_error_add(&info); 257215976Sjmallett 258215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 259215976Sjmallett info.status_addr = CVMX_L2T_ERR; 260215976Sjmallett info.status_mask = 1ull<<24 /* lckerr */; 261215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 262215976Sjmallett info.enable_mask = 1ull<<25 /* lck_intena */; 263215976Sjmallett info.flags = 0; 264215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 265215976Sjmallett info.group_index = 0; 266215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 267215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 268215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 269215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr; 270215976Sjmallett info.user_info = (long) 271215976Sjmallett "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n" 272215976Sjmallett " the INDEX (which is ignored by HW - but reported to SW).\n" 273215976Sjmallett " The LDD(L1 load-miss) for the LOCK operation is completed\n" 274215976Sjmallett " successfully, however the address is NOT locked.\n" 275215976Sjmallett " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n" 276215976Sjmallett " into account. For example, if diagnostic PPx has\n" 277215976Sjmallett " UMSKx defined to only use SETs [1:0], and SET1 had\n" 278215976Sjmallett " been previously LOCKED, then an attempt to LOCK the\n" 279215976Sjmallett " last available SET0 would result in a LCKERR. (This\n" 280215976Sjmallett " is to ensure that at least 1 SET at each INDEX is\n" 281215976Sjmallett " not LOCKED for general use by other PPs).\n"; 282215976Sjmallett fail |= cvmx_error_add(&info); 283215976Sjmallett 284215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 285215976Sjmallett info.status_addr = CVMX_L2T_ERR; 286215976Sjmallett info.status_mask = 1ull<<26 /* lckerr2 */; 287215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 288215976Sjmallett info.enable_mask = 1ull<<27 /* lck_intena2 */; 289215976Sjmallett info.flags = 0; 290215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 291215976Sjmallett info.group_index = 0; 292215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 293215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 294215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 295215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr2; 296215976Sjmallett info.user_info = (long) 297215976Sjmallett "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n" 298215976Sjmallett " could not find an available/unlocked set (for\n" 299215976Sjmallett " replacement).\n" 300215976Sjmallett " Most likely, this is a result of SW mixing SET\n" 301215976Sjmallett " PARTITIONING with ADDRESS LOCKING. If SW allows\n" 302215976Sjmallett " another PP to LOCKDOWN all SETs available to PP#n,\n" 303215976Sjmallett " then a Rd/Wr Miss from PP#n will be unable\n" 304215976Sjmallett " to determine a 'valid' replacement set (since LOCKED\n" 305215976Sjmallett " addresses should NEVER be replaced).\n" 306215976Sjmallett " If such an event occurs, the HW will select the smallest\n" 307215976Sjmallett " available SET(specified by UMSK'x)' as the replacement\n" 308215976Sjmallett " set, and the address is unlocked.\n"; 309215976Sjmallett fail |= cvmx_error_add(&info); 310215976Sjmallett 311215976Sjmallett /* CVMX_NPI_INT_SUM */ 312215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 313215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 314215976Sjmallett info.status_mask = 1ull<<0 /* rml_rto */; 315215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 316215976Sjmallett info.enable_mask = 1ull<<0 /* rml_rto */; 317215976Sjmallett info.flags = 0; 318215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 319215976Sjmallett info.group_index = 0; 320215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 321215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 322215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 323215976Sjmallett info.func = __cvmx_error_display; 324215976Sjmallett info.user_info = (long) 325215976Sjmallett "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n" 326215976Sjmallett " back from a RSL after sending a read command to\n" 327215976Sjmallett " a RSL.\n"; 328215976Sjmallett fail |= cvmx_error_add(&info); 329215976Sjmallett 330215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 331215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 332215976Sjmallett info.status_mask = 1ull<<1 /* rml_wto */; 333215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 334215976Sjmallett info.enable_mask = 1ull<<1 /* rml_wto */; 335215976Sjmallett info.flags = 0; 336215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 337215976Sjmallett info.group_index = 0; 338215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 339215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 340215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 341215976Sjmallett info.func = __cvmx_error_display; 342215976Sjmallett info.user_info = (long) 343215976Sjmallett "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n" 344215976Sjmallett " back from a RSL after sending a write command to\n" 345215976Sjmallett " a RSL.\n"; 346215976Sjmallett fail |= cvmx_error_add(&info); 347215976Sjmallett 348215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 349215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 350215976Sjmallett info.status_mask = 1ull<<3 /* po0_2sml */; 351215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 352215976Sjmallett info.enable_mask = 1ull<<3 /* po0_2sml */; 353215976Sjmallett info.flags = 0; 354215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 355215976Sjmallett info.group_index = 0; 356215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 357215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 358215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 359215976Sjmallett info.func = __cvmx_error_display; 360215976Sjmallett info.user_info = (long) 361215976Sjmallett "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n" 362215976Sjmallett " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n"; 363215976Sjmallett fail |= cvmx_error_add(&info); 364215976Sjmallett 365215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 366215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 367215976Sjmallett info.status_mask = 1ull<<4 /* po1_2sml */; 368215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 369215976Sjmallett info.enable_mask = 1ull<<4 /* po1_2sml */; 370215976Sjmallett info.flags = 0; 371215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 372215976Sjmallett info.group_index = 0; 373215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 374215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 375215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 376215976Sjmallett info.func = __cvmx_error_display; 377215976Sjmallett info.user_info = (long) 378215976Sjmallett "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n" 379215976Sjmallett " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n"; 380215976Sjmallett fail |= cvmx_error_add(&info); 381215976Sjmallett 382215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 383215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 384215976Sjmallett info.status_mask = 1ull<<5 /* po2_2sml */; 385215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 386215976Sjmallett info.enable_mask = 1ull<<5 /* po2_2sml */; 387215976Sjmallett info.flags = 0; 388215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 389215976Sjmallett info.group_index = 0; 390215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 391215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 392215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 393215976Sjmallett info.func = __cvmx_error_display; 394215976Sjmallett info.user_info = (long) 395215976Sjmallett "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n" 396215976Sjmallett " than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n"; 397215976Sjmallett fail |= cvmx_error_add(&info); 398215976Sjmallett 399215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 400215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 401215976Sjmallett info.status_mask = 1ull<<6 /* po3_2sml */; 402215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 403215976Sjmallett info.enable_mask = 1ull<<6 /* po3_2sml */; 404215976Sjmallett info.flags = 0; 405215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 406215976Sjmallett info.group_index = 0; 407215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 408215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 409215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 410215976Sjmallett info.func = __cvmx_error_display; 411215976Sjmallett info.user_info = (long) 412215976Sjmallett "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n" 413215976Sjmallett " than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n"; 414215976Sjmallett fail |= cvmx_error_add(&info); 415215976Sjmallett 416215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 417215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 418215976Sjmallett info.status_mask = 1ull<<7 /* i0_rtout */; 419215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 420215976Sjmallett info.enable_mask = 1ull<<7 /* i0_rtout */; 421215976Sjmallett info.flags = 0; 422215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 423215976Sjmallett info.group_index = 0; 424215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 425215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 426215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 427215976Sjmallett info.func = __cvmx_error_display; 428215976Sjmallett info.user_info = (long) 429215976Sjmallett "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n" 430215976Sjmallett " read instructions.\n"; 431215976Sjmallett fail |= cvmx_error_add(&info); 432215976Sjmallett 433215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 434215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 435215976Sjmallett info.status_mask = 1ull<<8 /* i1_rtout */; 436215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 437215976Sjmallett info.enable_mask = 1ull<<8 /* i1_rtout */; 438215976Sjmallett info.flags = 0; 439215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 440215976Sjmallett info.group_index = 0; 441215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 442215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 443215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 444215976Sjmallett info.func = __cvmx_error_display; 445215976Sjmallett info.user_info = (long) 446215976Sjmallett "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n" 447215976Sjmallett " read instructions.\n"; 448215976Sjmallett fail |= cvmx_error_add(&info); 449215976Sjmallett 450215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 451215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 452215976Sjmallett info.status_mask = 1ull<<9 /* i2_rtout */; 453215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 454215976Sjmallett info.enable_mask = 1ull<<9 /* i2_rtout */; 455215976Sjmallett info.flags = 0; 456215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 457215976Sjmallett info.group_index = 0; 458215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 459215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 460215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 461215976Sjmallett info.func = __cvmx_error_display; 462215976Sjmallett info.user_info = (long) 463215976Sjmallett "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n" 464215976Sjmallett " read instructions.\n"; 465215976Sjmallett fail |= cvmx_error_add(&info); 466215976Sjmallett 467215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 468215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 469215976Sjmallett info.status_mask = 1ull<<10 /* i3_rtout */; 470215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 471215976Sjmallett info.enable_mask = 1ull<<10 /* i3_rtout */; 472215976Sjmallett info.flags = 0; 473215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 474215976Sjmallett info.group_index = 0; 475215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 476215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 477215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 478215976Sjmallett info.func = __cvmx_error_display; 479215976Sjmallett info.user_info = (long) 480215976Sjmallett "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n" 481215976Sjmallett " read instructions.\n"; 482215976Sjmallett fail |= cvmx_error_add(&info); 483215976Sjmallett 484215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 485215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 486215976Sjmallett info.status_mask = 1ull<<11 /* i0_overf */; 487215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 488215976Sjmallett info.enable_mask = 1ull<<11 /* i0_overf */; 489215976Sjmallett info.flags = 0; 490215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 491215976Sjmallett info.group_index = 0; 492215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 493215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 494215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 495215976Sjmallett info.func = __cvmx_error_display; 496215976Sjmallett info.user_info = (long) 497215976Sjmallett "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n" 498215976Sjmallett " doorbell count was set.\n"; 499215976Sjmallett fail |= cvmx_error_add(&info); 500215976Sjmallett 501215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 502215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 503215976Sjmallett info.status_mask = 1ull<<12 /* i1_overf */; 504215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 505215976Sjmallett info.enable_mask = 1ull<<12 /* i1_overf */; 506215976Sjmallett info.flags = 0; 507215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 508215976Sjmallett info.group_index = 0; 509215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 510215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 511215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 512215976Sjmallett info.func = __cvmx_error_display; 513215976Sjmallett info.user_info = (long) 514215976Sjmallett "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n" 515215976Sjmallett " doorbell count was set.\n"; 516215976Sjmallett fail |= cvmx_error_add(&info); 517215976Sjmallett 518215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 519215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 520215976Sjmallett info.status_mask = 1ull<<13 /* i2_overf */; 521215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 522215976Sjmallett info.enable_mask = 1ull<<13 /* i2_overf */; 523215976Sjmallett info.flags = 0; 524215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 525215976Sjmallett info.group_index = 0; 526215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 527215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 528215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 529215976Sjmallett info.func = __cvmx_error_display; 530215976Sjmallett info.user_info = (long) 531215976Sjmallett "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n" 532215976Sjmallett " doorbell count was set.\n"; 533215976Sjmallett fail |= cvmx_error_add(&info); 534215976Sjmallett 535215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 536215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 537215976Sjmallett info.status_mask = 1ull<<14 /* i3_overf */; 538215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 539215976Sjmallett info.enable_mask = 1ull<<14 /* i3_overf */; 540215976Sjmallett info.flags = 0; 541215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 542215976Sjmallett info.group_index = 0; 543215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 544215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 545215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 546215976Sjmallett info.func = __cvmx_error_display; 547215976Sjmallett info.user_info = (long) 548215976Sjmallett "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n" 549215976Sjmallett " doorbell count was set.\n"; 550215976Sjmallett fail |= cvmx_error_add(&info); 551215976Sjmallett 552215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 553215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 554215976Sjmallett info.status_mask = 1ull<<15 /* p0_rtout */; 555215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 556215976Sjmallett info.enable_mask = 1ull<<15 /* p0_rtout */; 557215976Sjmallett info.flags = 0; 558215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 559215976Sjmallett info.group_index = 0; 560215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 561215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 562215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 563215976Sjmallett info.func = __cvmx_error_display; 564215976Sjmallett info.user_info = (long) 565215976Sjmallett "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n" 566215976Sjmallett " read packet data.\n"; 567215976Sjmallett fail |= cvmx_error_add(&info); 568215976Sjmallett 569215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 570215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 571215976Sjmallett info.status_mask = 1ull<<16 /* p1_rtout */; 572215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 573215976Sjmallett info.enable_mask = 1ull<<16 /* p1_rtout */; 574215976Sjmallett info.flags = 0; 575215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 576215976Sjmallett info.group_index = 0; 577215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 578215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 579215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 580215976Sjmallett info.func = __cvmx_error_display; 581215976Sjmallett info.user_info = (long) 582215976Sjmallett "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n" 583215976Sjmallett " read packet data.\n"; 584215976Sjmallett fail |= cvmx_error_add(&info); 585215976Sjmallett 586215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 587215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 588215976Sjmallett info.status_mask = 1ull<<17 /* p2_rtout */; 589215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 590215976Sjmallett info.enable_mask = 1ull<<17 /* p2_rtout */; 591215976Sjmallett info.flags = 0; 592215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 593215976Sjmallett info.group_index = 0; 594215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 595215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 596215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 597215976Sjmallett info.func = __cvmx_error_display; 598215976Sjmallett info.user_info = (long) 599215976Sjmallett "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n" 600215976Sjmallett " read packet data.\n"; 601215976Sjmallett fail |= cvmx_error_add(&info); 602215976Sjmallett 603215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 604215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 605215976Sjmallett info.status_mask = 1ull<<18 /* p3_rtout */; 606215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 607215976Sjmallett info.enable_mask = 1ull<<18 /* p3_rtout */; 608215976Sjmallett info.flags = 0; 609215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 610215976Sjmallett info.group_index = 0; 611215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 612215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 613215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 614215976Sjmallett info.func = __cvmx_error_display; 615215976Sjmallett info.user_info = (long) 616215976Sjmallett "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n" 617215976Sjmallett " read packet data.\n"; 618215976Sjmallett fail |= cvmx_error_add(&info); 619215976Sjmallett 620215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 621215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 622215976Sjmallett info.status_mask = 1ull<<19 /* p0_perr */; 623215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 624215976Sjmallett info.enable_mask = 1ull<<19 /* p0_perr */; 625215976Sjmallett info.flags = 0; 626215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 627215976Sjmallett info.group_index = 0; 628215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 629215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 630215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 631215976Sjmallett info.func = __cvmx_error_display; 632215976Sjmallett info.user_info = (long) 633215976Sjmallett "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n" 634215976Sjmallett " data this bit may be set.\n"; 635215976Sjmallett fail |= cvmx_error_add(&info); 636215976Sjmallett 637215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 638215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 639215976Sjmallett info.status_mask = 1ull<<20 /* p1_perr */; 640215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 641215976Sjmallett info.enable_mask = 1ull<<20 /* p1_perr */; 642215976Sjmallett info.flags = 0; 643215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 644215976Sjmallett info.group_index = 0; 645215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 646215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 647215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 648215976Sjmallett info.func = __cvmx_error_display; 649215976Sjmallett info.user_info = (long) 650215976Sjmallett "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n" 651215976Sjmallett " data this bit may be set.\n"; 652215976Sjmallett fail |= cvmx_error_add(&info); 653215976Sjmallett 654215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 655215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 656215976Sjmallett info.status_mask = 1ull<<21 /* p2_perr */; 657215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 658215976Sjmallett info.enable_mask = 1ull<<21 /* p2_perr */; 659215976Sjmallett info.flags = 0; 660215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 661215976Sjmallett info.group_index = 0; 662215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 663215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 664215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 665215976Sjmallett info.func = __cvmx_error_display; 666215976Sjmallett info.user_info = (long) 667215976Sjmallett "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n" 668215976Sjmallett " data this bit may be set.\n"; 669215976Sjmallett fail |= cvmx_error_add(&info); 670215976Sjmallett 671215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 672215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 673215976Sjmallett info.status_mask = 1ull<<22 /* p3_perr */; 674215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 675215976Sjmallett info.enable_mask = 1ull<<22 /* p3_perr */; 676215976Sjmallett info.flags = 0; 677215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 678215976Sjmallett info.group_index = 0; 679215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 680215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 681215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 682215976Sjmallett info.func = __cvmx_error_display; 683215976Sjmallett info.user_info = (long) 684215976Sjmallett "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n" 685215976Sjmallett " data this bit may be set.\n"; 686215976Sjmallett fail |= cvmx_error_add(&info); 687215976Sjmallett 688215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 689215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 690215976Sjmallett info.status_mask = 1ull<<23 /* g0_rtout */; 691215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 692215976Sjmallett info.enable_mask = 1ull<<23 /* g0_rtout */; 693215976Sjmallett info.flags = 0; 694215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 695215976Sjmallett info.group_index = 0; 696215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 697215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 698215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 699215976Sjmallett info.func = __cvmx_error_display; 700215976Sjmallett info.user_info = (long) 701215976Sjmallett "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n" 702215976Sjmallett " read a gather list.\n"; 703215976Sjmallett fail |= cvmx_error_add(&info); 704215976Sjmallett 705215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 706215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 707215976Sjmallett info.status_mask = 1ull<<24 /* g1_rtout */; 708215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 709215976Sjmallett info.enable_mask = 1ull<<24 /* g1_rtout */; 710215976Sjmallett info.flags = 0; 711215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 712215976Sjmallett info.group_index = 0; 713215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 714215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 715215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 716215976Sjmallett info.func = __cvmx_error_display; 717215976Sjmallett info.user_info = (long) 718215976Sjmallett "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n" 719215976Sjmallett " read a gather list.\n"; 720215976Sjmallett fail |= cvmx_error_add(&info); 721215976Sjmallett 722215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 723215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 724215976Sjmallett info.status_mask = 1ull<<25 /* g2_rtout */; 725215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 726215976Sjmallett info.enable_mask = 1ull<<25 /* g2_rtout */; 727215976Sjmallett info.flags = 0; 728215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 729215976Sjmallett info.group_index = 0; 730215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 731215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 732215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 733215976Sjmallett info.func = __cvmx_error_display; 734215976Sjmallett info.user_info = (long) 735215976Sjmallett "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n" 736215976Sjmallett " read a gather list.\n"; 737215976Sjmallett fail |= cvmx_error_add(&info); 738215976Sjmallett 739215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 740215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 741215976Sjmallett info.status_mask = 1ull<<26 /* g3_rtout */; 742215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 743215976Sjmallett info.enable_mask = 1ull<<26 /* g3_rtout */; 744215976Sjmallett info.flags = 0; 745215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 746215976Sjmallett info.group_index = 0; 747215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 748215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 749215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 750215976Sjmallett info.func = __cvmx_error_display; 751215976Sjmallett info.user_info = (long) 752215976Sjmallett "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n" 753215976Sjmallett " read a gather list.\n"; 754215976Sjmallett fail |= cvmx_error_add(&info); 755215976Sjmallett 756215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 757215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 758215976Sjmallett info.status_mask = 1ull<<27 /* p0_pperr */; 759215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 760215976Sjmallett info.enable_mask = 1ull<<27 /* p0_pperr */; 761215976Sjmallett info.flags = 0; 762215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 763215976Sjmallett info.group_index = 0; 764215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 765215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 766215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 767215976Sjmallett info.func = __cvmx_error_display; 768215976Sjmallett info.user_info = (long) 769215976Sjmallett "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n" 770215976Sjmallett " pointer-pair, this bit may be set.\n"; 771215976Sjmallett fail |= cvmx_error_add(&info); 772215976Sjmallett 773215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 774215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 775215976Sjmallett info.status_mask = 1ull<<28 /* p1_pperr */; 776215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 777215976Sjmallett info.enable_mask = 1ull<<28 /* p1_pperr */; 778215976Sjmallett info.flags = 0; 779215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 780215976Sjmallett info.group_index = 0; 781215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 782215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 783215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 784215976Sjmallett info.func = __cvmx_error_display; 785215976Sjmallett info.user_info = (long) 786215976Sjmallett "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n" 787215976Sjmallett " pointer-pair, this bit may be set.\n"; 788215976Sjmallett fail |= cvmx_error_add(&info); 789215976Sjmallett 790215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 791215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 792215976Sjmallett info.status_mask = 1ull<<29 /* p2_pperr */; 793215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 794215976Sjmallett info.enable_mask = 1ull<<29 /* p2_pperr */; 795215976Sjmallett info.flags = 0; 796215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 797215976Sjmallett info.group_index = 0; 798215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 799215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 800215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 801215976Sjmallett info.func = __cvmx_error_display; 802215976Sjmallett info.user_info = (long) 803215976Sjmallett "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n" 804215976Sjmallett " pointer-pair, this bit may be set.\n"; 805215976Sjmallett fail |= cvmx_error_add(&info); 806215976Sjmallett 807215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 808215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 809215976Sjmallett info.status_mask = 1ull<<30 /* p3_pperr */; 810215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 811215976Sjmallett info.enable_mask = 1ull<<30 /* p3_pperr */; 812215976Sjmallett info.flags = 0; 813215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 814215976Sjmallett info.group_index = 0; 815215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 816215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 817215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 818215976Sjmallett info.func = __cvmx_error_display; 819215976Sjmallett info.user_info = (long) 820215976Sjmallett "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n" 821215976Sjmallett " pointer-pair, this bit may be set.\n"; 822215976Sjmallett fail |= cvmx_error_add(&info); 823215976Sjmallett 824215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 825215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 826215976Sjmallett info.status_mask = 1ull<<31 /* p0_ptout */; 827215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 828215976Sjmallett info.enable_mask = 1ull<<31 /* p0_ptout */; 829215976Sjmallett info.flags = 0; 830215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 831215976Sjmallett info.group_index = 0; 832215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 833215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 834215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 835215976Sjmallett info.func = __cvmx_error_display; 836215976Sjmallett info.user_info = (long) 837215976Sjmallett "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n" 838215976Sjmallett " pair.\n"; 839215976Sjmallett fail |= cvmx_error_add(&info); 840215976Sjmallett 841215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 842215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 843215976Sjmallett info.status_mask = 1ull<<32 /* p1_ptout */; 844215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 845215976Sjmallett info.enable_mask = 1ull<<32 /* p1_ptout */; 846215976Sjmallett info.flags = 0; 847215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 848215976Sjmallett info.group_index = 0; 849215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 850215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 851215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 852215976Sjmallett info.func = __cvmx_error_display; 853215976Sjmallett info.user_info = (long) 854215976Sjmallett "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n" 855215976Sjmallett " pair.\n"; 856215976Sjmallett fail |= cvmx_error_add(&info); 857215976Sjmallett 858215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 859215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 860215976Sjmallett info.status_mask = 1ull<<33 /* p2_ptout */; 861215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 862215976Sjmallett info.enable_mask = 1ull<<33 /* p2_ptout */; 863215976Sjmallett info.flags = 0; 864215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 865215976Sjmallett info.group_index = 0; 866215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 867215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 868215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 869215976Sjmallett info.func = __cvmx_error_display; 870215976Sjmallett info.user_info = (long) 871215976Sjmallett "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n" 872215976Sjmallett " pair.\n"; 873215976Sjmallett fail |= cvmx_error_add(&info); 874215976Sjmallett 875215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 876215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 877215976Sjmallett info.status_mask = 1ull<<34 /* p3_ptout */; 878215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 879215976Sjmallett info.enable_mask = 1ull<<34 /* p3_ptout */; 880215976Sjmallett info.flags = 0; 881215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 882215976Sjmallett info.group_index = 0; 883215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 884215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 885215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 886215976Sjmallett info.func = __cvmx_error_display; 887215976Sjmallett info.user_info = (long) 888215976Sjmallett "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n" 889215976Sjmallett " pair.\n"; 890215976Sjmallett fail |= cvmx_error_add(&info); 891215976Sjmallett 892215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 893215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 894215976Sjmallett info.status_mask = 1ull<<35 /* i0_pperr */; 895215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 896215976Sjmallett info.enable_mask = 1ull<<35 /* i0_pperr */; 897215976Sjmallett info.flags = 0; 898215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 899215976Sjmallett info.group_index = 0; 900215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 901215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 902215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 903215976Sjmallett info.func = __cvmx_error_display; 904215976Sjmallett info.user_info = (long) 905215976Sjmallett "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n" 906215976Sjmallett " this bit may be set.\n"; 907215976Sjmallett fail |= cvmx_error_add(&info); 908215976Sjmallett 909215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 910215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 911215976Sjmallett info.status_mask = 1ull<<36 /* i1_pperr */; 912215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 913215976Sjmallett info.enable_mask = 1ull<<36 /* i1_pperr */; 914215976Sjmallett info.flags = 0; 915215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 916215976Sjmallett info.group_index = 0; 917215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 918215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 919215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 920215976Sjmallett info.func = __cvmx_error_display; 921215976Sjmallett info.user_info = (long) 922215976Sjmallett "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n" 923215976Sjmallett " this bit may be set.\n"; 924215976Sjmallett fail |= cvmx_error_add(&info); 925215976Sjmallett 926215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 927215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 928215976Sjmallett info.status_mask = 1ull<<37 /* i2_pperr */; 929215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 930215976Sjmallett info.enable_mask = 1ull<<37 /* i2_pperr */; 931215976Sjmallett info.flags = 0; 932215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 933215976Sjmallett info.group_index = 0; 934215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 935215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 936215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 937215976Sjmallett info.func = __cvmx_error_display; 938215976Sjmallett info.user_info = (long) 939215976Sjmallett "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n" 940215976Sjmallett " this bit may be set.\n"; 941215976Sjmallett fail |= cvmx_error_add(&info); 942215976Sjmallett 943215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 944215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 945215976Sjmallett info.status_mask = 1ull<<38 /* i3_pperr */; 946215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 947215976Sjmallett info.enable_mask = 1ull<<38 /* i3_pperr */; 948215976Sjmallett info.flags = 0; 949215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 950215976Sjmallett info.group_index = 0; 951215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 952215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 953215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 954215976Sjmallett info.func = __cvmx_error_display; 955215976Sjmallett info.user_info = (long) 956215976Sjmallett "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n" 957215976Sjmallett " this bit may be set.\n"; 958215976Sjmallett fail |= cvmx_error_add(&info); 959215976Sjmallett 960215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 961215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 962215976Sjmallett info.status_mask = 1ull<<39 /* win_rto */; 963215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 964215976Sjmallett info.enable_mask = 1ull<<39 /* win_rto */; 965215976Sjmallett info.flags = 0; 966215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 967215976Sjmallett info.group_index = 0; 968215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 969215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 970215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 971215976Sjmallett info.func = __cvmx_error_display; 972215976Sjmallett info.user_info = (long) 973215976Sjmallett "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n"; 974215976Sjmallett fail |= cvmx_error_add(&info); 975215976Sjmallett 976215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 977215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 978215976Sjmallett info.status_mask = 1ull<<40 /* p_dperr */; 979215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 980215976Sjmallett info.enable_mask = 1ull<<40 /* p_dperr */; 981215976Sjmallett info.flags = 0; 982215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 983215976Sjmallett info.group_index = 0; 984215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 985215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 986215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 987215976Sjmallett info.func = __cvmx_error_display; 988215976Sjmallett info.user_info = (long) 989215976Sjmallett "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n" 990215976Sjmallett " from the PCI this bit may be set.\n"; 991215976Sjmallett fail |= cvmx_error_add(&info); 992215976Sjmallett 993215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 994215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 995215976Sjmallett info.status_mask = 1ull<<41 /* iobdma */; 996215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 997215976Sjmallett info.enable_mask = 1ull<<41 /* iobdma */; 998215976Sjmallett info.flags = 0; 999215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1000215976Sjmallett info.group_index = 0; 1001215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1002215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1003215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1004215976Sjmallett info.func = __cvmx_error_display; 1005215976Sjmallett info.user_info = (long) 1006215976Sjmallett "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n"; 1007215976Sjmallett fail |= cvmx_error_add(&info); 1008215976Sjmallett 1009215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1010215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1011215976Sjmallett info.status_mask = 1ull<<42 /* fcr_s_e */; 1012215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1013215976Sjmallett info.enable_mask = 1ull<<42 /* fcr_s_e */; 1014215976Sjmallett info.flags = 0; 1015215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1016215976Sjmallett info.group_index = 0; 1017215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1018215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1019215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1020215976Sjmallett info.func = __cvmx_error_display; 1021215976Sjmallett info.user_info = (long) 1022215976Sjmallett "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n" 1023215976Sjmallett " PASS3 Field.\n"; 1024215976Sjmallett fail |= cvmx_error_add(&info); 1025215976Sjmallett 1026215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1027215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1028215976Sjmallett info.status_mask = 1ull<<43 /* fcr_a_f */; 1029215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1030215976Sjmallett info.enable_mask = 1ull<<43 /* fcr_a_f */; 1031215976Sjmallett info.flags = 0; 1032215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1033215976Sjmallett info.group_index = 0; 1034215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1035215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1036215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1037215976Sjmallett info.func = __cvmx_error_display; 1038215976Sjmallett info.user_info = (long) 1039215976Sjmallett "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n" 1040215976Sjmallett " PASS3 Field.\n"; 1041215976Sjmallett fail |= cvmx_error_add(&info); 1042215976Sjmallett 1043215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1044215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1045215976Sjmallett info.status_mask = 1ull<<44 /* pcr_s_e */; 1046215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1047215976Sjmallett info.enable_mask = 1ull<<44 /* pcr_s_e */; 1048215976Sjmallett info.flags = 0; 1049215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1050215976Sjmallett info.group_index = 0; 1051215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1052215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1053215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1054215976Sjmallett info.func = __cvmx_error_display; 1055215976Sjmallett info.user_info = (long) 1056215976Sjmallett "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n" 1057215976Sjmallett " PASS3 Field.\n"; 1058215976Sjmallett fail |= cvmx_error_add(&info); 1059215976Sjmallett 1060215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1061215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1062215976Sjmallett info.status_mask = 1ull<<45 /* pcr_a_f */; 1063215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1064215976Sjmallett info.enable_mask = 1ull<<45 /* pcr_a_f */; 1065215976Sjmallett info.flags = 0; 1066215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1067215976Sjmallett info.group_index = 0; 1068215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1069215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1070215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1071215976Sjmallett info.func = __cvmx_error_display; 1072215976Sjmallett info.user_info = (long) 1073215976Sjmallett "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n" 1074215976Sjmallett " PASS3 Field.\n"; 1075215976Sjmallett fail |= cvmx_error_add(&info); 1076215976Sjmallett 1077215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1078215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1079215976Sjmallett info.status_mask = 1ull<<46 /* q2_s_e */; 1080215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1081215976Sjmallett info.enable_mask = 1ull<<46 /* q2_s_e */; 1082215976Sjmallett info.flags = 0; 1083215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1084215976Sjmallett info.group_index = 0; 1085215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1086215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1087215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1088215976Sjmallett info.func = __cvmx_error_display; 1089215976Sjmallett info.user_info = (long) 1090215976Sjmallett "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n" 1091215976Sjmallett " PASS3 Field.\n"; 1092215976Sjmallett fail |= cvmx_error_add(&info); 1093215976Sjmallett 1094215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1095215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1096215976Sjmallett info.status_mask = 1ull<<47 /* q2_a_f */; 1097215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1098215976Sjmallett info.enable_mask = 1ull<<47 /* q2_a_f */; 1099215976Sjmallett info.flags = 0; 1100215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1101215976Sjmallett info.group_index = 0; 1102215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1103215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1104215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1105215976Sjmallett info.func = __cvmx_error_display; 1106215976Sjmallett info.user_info = (long) 1107215976Sjmallett "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n" 1108215976Sjmallett " PASS3 Field.\n"; 1109215976Sjmallett fail |= cvmx_error_add(&info); 1110215976Sjmallett 1111215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1112215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1113215976Sjmallett info.status_mask = 1ull<<48 /* q3_s_e */; 1114215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1115215976Sjmallett info.enable_mask = 1ull<<48 /* q3_s_e */; 1116215976Sjmallett info.flags = 0; 1117215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1118215976Sjmallett info.group_index = 0; 1119215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1120215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1121215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1122215976Sjmallett info.func = __cvmx_error_display; 1123215976Sjmallett info.user_info = (long) 1124215976Sjmallett "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n" 1125215976Sjmallett " PASS3 Field.\n"; 1126215976Sjmallett fail |= cvmx_error_add(&info); 1127215976Sjmallett 1128215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1129215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1130215976Sjmallett info.status_mask = 1ull<<49 /* q3_a_f */; 1131215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1132215976Sjmallett info.enable_mask = 1ull<<49 /* q3_a_f */; 1133215976Sjmallett info.flags = 0; 1134215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1135215976Sjmallett info.group_index = 0; 1136215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1137215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1138215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1139215976Sjmallett info.func = __cvmx_error_display; 1140215976Sjmallett info.user_info = (long) 1141215976Sjmallett "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n" 1142215976Sjmallett " PASS3 Field.\n"; 1143215976Sjmallett fail |= cvmx_error_add(&info); 1144215976Sjmallett 1145215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1146215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1147215976Sjmallett info.status_mask = 1ull<<50 /* com_s_e */; 1148215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1149215976Sjmallett info.enable_mask = 1ull<<50 /* com_s_e */; 1150215976Sjmallett info.flags = 0; 1151215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1152215976Sjmallett info.group_index = 0; 1153215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1154215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1155215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1156215976Sjmallett info.func = __cvmx_error_display; 1157215976Sjmallett info.user_info = (long) 1158215976Sjmallett "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n" 1159215976Sjmallett " PASS3 Field.\n"; 1160215976Sjmallett fail |= cvmx_error_add(&info); 1161215976Sjmallett 1162215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1163215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1164215976Sjmallett info.status_mask = 1ull<<51 /* com_a_f */; 1165215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1166215976Sjmallett info.enable_mask = 1ull<<51 /* com_a_f */; 1167215976Sjmallett info.flags = 0; 1168215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1169215976Sjmallett info.group_index = 0; 1170215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1171215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1172215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1173215976Sjmallett info.func = __cvmx_error_display; 1174215976Sjmallett info.user_info = (long) 1175215976Sjmallett "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n" 1176215976Sjmallett " PASS3 Field.\n"; 1177215976Sjmallett fail |= cvmx_error_add(&info); 1178215976Sjmallett 1179215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1180215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1181215976Sjmallett info.status_mask = 1ull<<52 /* pnc_s_e */; 1182215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1183215976Sjmallett info.enable_mask = 1ull<<52 /* pnc_s_e */; 1184215976Sjmallett info.flags = 0; 1185215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1186215976Sjmallett info.group_index = 0; 1187215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1188215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1189215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1190215976Sjmallett info.func = __cvmx_error_display; 1191215976Sjmallett info.user_info = (long) 1192215976Sjmallett "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n" 1193215976Sjmallett " PASS3 Field.\n"; 1194215976Sjmallett fail |= cvmx_error_add(&info); 1195215976Sjmallett 1196215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1197215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1198215976Sjmallett info.status_mask = 1ull<<53 /* pnc_a_f */; 1199215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1200215976Sjmallett info.enable_mask = 1ull<<53 /* pnc_a_f */; 1201215976Sjmallett info.flags = 0; 1202215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1203215976Sjmallett info.group_index = 0; 1204215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1205215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1206215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1207215976Sjmallett info.func = __cvmx_error_display; 1208215976Sjmallett info.user_info = (long) 1209215976Sjmallett "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n" 1210215976Sjmallett " PASS3 Field.\n"; 1211215976Sjmallett fail |= cvmx_error_add(&info); 1212215976Sjmallett 1213215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1214215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1215215976Sjmallett info.status_mask = 1ull<<54 /* rwx_s_e */; 1216215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1217215976Sjmallett info.enable_mask = 1ull<<54 /* rwx_s_e */; 1218215976Sjmallett info.flags = 0; 1219215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1220215976Sjmallett info.group_index = 0; 1221215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1222215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1223215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1224215976Sjmallett info.func = __cvmx_error_display; 1225215976Sjmallett info.user_info = (long) 1226215976Sjmallett "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n" 1227215976Sjmallett " PASS3 Field.\n"; 1228215976Sjmallett fail |= cvmx_error_add(&info); 1229215976Sjmallett 1230215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1231215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1232215976Sjmallett info.status_mask = 1ull<<55 /* rdx_s_e */; 1233215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1234215976Sjmallett info.enable_mask = 1ull<<55 /* rdx_s_e */; 1235215976Sjmallett info.flags = 0; 1236215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1237215976Sjmallett info.group_index = 0; 1238215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1239215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1240215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1241215976Sjmallett info.func = __cvmx_error_display; 1242215976Sjmallett info.user_info = (long) 1243215976Sjmallett "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n" 1244215976Sjmallett " PASS3 Field.\n"; 1245215976Sjmallett fail |= cvmx_error_add(&info); 1246215976Sjmallett 1247215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1248215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1249215976Sjmallett info.status_mask = 1ull<<56 /* pcf_p_e */; 1250215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1251215976Sjmallett info.enable_mask = 1ull<<56 /* pcf_p_e */; 1252215976Sjmallett info.flags = 0; 1253215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1254215976Sjmallett info.group_index = 0; 1255215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1256215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1257215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1258215976Sjmallett info.func = __cvmx_error_display; 1259215976Sjmallett info.user_info = (long) 1260215976Sjmallett "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n" 1261215976Sjmallett " PASS3 Field.\n"; 1262215976Sjmallett fail |= cvmx_error_add(&info); 1263215976Sjmallett 1264215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1265215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1266215976Sjmallett info.status_mask = 1ull<<57 /* pcf_p_f */; 1267215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1268215976Sjmallett info.enable_mask = 1ull<<57 /* pcf_p_f */; 1269215976Sjmallett info.flags = 0; 1270215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1271215976Sjmallett info.group_index = 0; 1272215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1273215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1274215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1275215976Sjmallett info.func = __cvmx_error_display; 1276215976Sjmallett info.user_info = (long) 1277215976Sjmallett "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n" 1278215976Sjmallett " PASS3 Field.\n"; 1279215976Sjmallett fail |= cvmx_error_add(&info); 1280215976Sjmallett 1281215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1282215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1283215976Sjmallett info.status_mask = 1ull<<58 /* pdf_p_e */; 1284215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1285215976Sjmallett info.enable_mask = 1ull<<58 /* pdf_p_e */; 1286215976Sjmallett info.flags = 0; 1287215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1288215976Sjmallett info.group_index = 0; 1289215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1290215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1291215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1292215976Sjmallett info.func = __cvmx_error_display; 1293215976Sjmallett info.user_info = (long) 1294215976Sjmallett "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n" 1295215976Sjmallett " PASS3 Field.\n"; 1296215976Sjmallett fail |= cvmx_error_add(&info); 1297215976Sjmallett 1298215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1299215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1300215976Sjmallett info.status_mask = 1ull<<59 /* pdf_p_f */; 1301215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1302215976Sjmallett info.enable_mask = 1ull<<59 /* pdf_p_f */; 1303215976Sjmallett info.flags = 0; 1304215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1305215976Sjmallett info.group_index = 0; 1306215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1307215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1308215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1309215976Sjmallett info.func = __cvmx_error_display; 1310215976Sjmallett info.user_info = (long) 1311215976Sjmallett "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n" 1312215976Sjmallett " PASS3 Field.\n"; 1313215976Sjmallett fail |= cvmx_error_add(&info); 1314215976Sjmallett 1315215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1316215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1317215976Sjmallett info.status_mask = 1ull<<60 /* q1_s_e */; 1318215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1319215976Sjmallett info.enable_mask = 1ull<<60 /* q1_s_e */; 1320215976Sjmallett info.flags = 0; 1321215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1322215976Sjmallett info.group_index = 0; 1323215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1324215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1325215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1326215976Sjmallett info.func = __cvmx_error_display; 1327215976Sjmallett info.user_info = (long) 1328215976Sjmallett "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n" 1329215976Sjmallett " PASS3 Field.\n"; 1330215976Sjmallett fail |= cvmx_error_add(&info); 1331215976Sjmallett 1332215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1333215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1334215976Sjmallett info.status_mask = 1ull<<61 /* q1_a_f */; 1335215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1336215976Sjmallett info.enable_mask = 1ull<<61 /* q1_a_f */; 1337215976Sjmallett info.flags = 0; 1338215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1339215976Sjmallett info.group_index = 0; 1340215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1341215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1342215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1343215976Sjmallett info.func = __cvmx_error_display; 1344215976Sjmallett info.user_info = (long) 1345215976Sjmallett "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n" 1346215976Sjmallett " PASS3 Field.\n"; 1347215976Sjmallett fail |= cvmx_error_add(&info); 1348215976Sjmallett 1349215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1350215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1351215976Sjmallett info.status_mask = 0; 1352215976Sjmallett info.enable_addr = 0; 1353215976Sjmallett info.enable_mask = 0; 1354215976Sjmallett info.flags = 0; 1355215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1356215976Sjmallett info.group_index = 0; 1357215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1358215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1359215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1360215976Sjmallett info.func = __cvmx_error_decode; 1361215976Sjmallett info.user_info = 0; 1362215976Sjmallett fail |= cvmx_error_add(&info); 1363215976Sjmallett 1364215976Sjmallett /* CVMX_NPI_PCI_INT_SUM2 */ 1365215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1366215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1367215976Sjmallett info.status_mask = 1ull<<0 /* tr_wabt */; 1368215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1369215976Sjmallett info.enable_mask = 1ull<<0 /* rtr_wabt */; 1370215976Sjmallett info.flags = 0; 1371215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1372215976Sjmallett info.group_index = 0; 1373215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1374215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1375215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1376215976Sjmallett info.func = __cvmx_error_display; 1377215976Sjmallett info.user_info = (long) 1378215976Sjmallett "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n"; 1379215976Sjmallett fail |= cvmx_error_add(&info); 1380215976Sjmallett 1381215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1382215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1383215976Sjmallett info.status_mask = 1ull<<1 /* mr_wabt */; 1384215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1385215976Sjmallett info.enable_mask = 1ull<<1 /* rmr_wabt */; 1386215976Sjmallett info.flags = 0; 1387215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1388215976Sjmallett info.group_index = 0; 1389215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1390215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1391215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1392215976Sjmallett info.func = __cvmx_error_display; 1393215976Sjmallett info.user_info = (long) 1394215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n"; 1395215976Sjmallett fail |= cvmx_error_add(&info); 1396215976Sjmallett 1397215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1398215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1399215976Sjmallett info.status_mask = 1ull<<2 /* mr_wtto */; 1400215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1401215976Sjmallett info.enable_mask = 1ull<<2 /* rmr_wtto */; 1402215976Sjmallett info.flags = 0; 1403215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1404215976Sjmallett info.group_index = 0; 1405215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1406215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1407215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1408215976Sjmallett info.func = __cvmx_error_display; 1409215976Sjmallett info.user_info = (long) 1410215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n"; 1411215976Sjmallett fail |= cvmx_error_add(&info); 1412215976Sjmallett 1413215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1414215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1415215976Sjmallett info.status_mask = 1ull<<3 /* tr_abt */; 1416215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1417215976Sjmallett info.enable_mask = 1ull<<3 /* rtr_abt */; 1418215976Sjmallett info.flags = 0; 1419215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1420215976Sjmallett info.group_index = 0; 1421215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1422215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1423215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1424215976Sjmallett info.func = __cvmx_error_display; 1425215976Sjmallett info.user_info = (long) 1426215976Sjmallett "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n"; 1427215976Sjmallett fail |= cvmx_error_add(&info); 1428215976Sjmallett 1429215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1430215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1431215976Sjmallett info.status_mask = 1ull<<4 /* mr_abt */; 1432215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1433215976Sjmallett info.enable_mask = 1ull<<4 /* rmr_abt */; 1434215976Sjmallett info.flags = 0; 1435215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1436215976Sjmallett info.group_index = 0; 1437215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1438215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1439215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1440215976Sjmallett info.func = __cvmx_error_display; 1441215976Sjmallett info.user_info = (long) 1442215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n"; 1443215976Sjmallett fail |= cvmx_error_add(&info); 1444215976Sjmallett 1445215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1446215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1447215976Sjmallett info.status_mask = 1ull<<5 /* mr_tto */; 1448215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1449215976Sjmallett info.enable_mask = 1ull<<5 /* rmr_tto */; 1450215976Sjmallett info.flags = 0; 1451215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1452215976Sjmallett info.group_index = 0; 1453215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1454215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1455215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1456215976Sjmallett info.func = __cvmx_error_display; 1457215976Sjmallett info.user_info = (long) 1458215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n"; 1459215976Sjmallett fail |= cvmx_error_add(&info); 1460215976Sjmallett 1461215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1462215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1463215976Sjmallett info.status_mask = 1ull<<6 /* msi_per */; 1464215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1465215976Sjmallett info.enable_mask = 1ull<<6 /* rmsi_per */; 1466215976Sjmallett info.flags = 0; 1467215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1468215976Sjmallett info.group_index = 0; 1469215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1470215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1471215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1472215976Sjmallett info.func = __cvmx_error_display; 1473215976Sjmallett info.user_info = (long) 1474215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n"; 1475215976Sjmallett fail |= cvmx_error_add(&info); 1476215976Sjmallett 1477215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1478215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1479215976Sjmallett info.status_mask = 1ull<<7 /* msi_tabt */; 1480215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1481215976Sjmallett info.enable_mask = 1ull<<7 /* rmsi_tabt */; 1482215976Sjmallett info.flags = 0; 1483215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1484215976Sjmallett info.group_index = 0; 1485215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1486215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1487215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1488215976Sjmallett info.func = __cvmx_error_display; 1489215976Sjmallett info.user_info = (long) 1490215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n"; 1491215976Sjmallett fail |= cvmx_error_add(&info); 1492215976Sjmallett 1493215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1494215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1495215976Sjmallett info.status_mask = 1ull<<8 /* msi_mabt */; 1496215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1497215976Sjmallett info.enable_mask = 1ull<<8 /* rmsi_mabt */; 1498215976Sjmallett info.flags = 0; 1499215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1500215976Sjmallett info.group_index = 0; 1501215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1502215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1503215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1504215976Sjmallett info.func = __cvmx_error_display; 1505215976Sjmallett info.user_info = (long) 1506215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n"; 1507215976Sjmallett fail |= cvmx_error_add(&info); 1508215976Sjmallett 1509215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1510215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1511215976Sjmallett info.status_mask = 1ull<<9 /* msc_msg */; 1512215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1513215976Sjmallett info.enable_mask = 1ull<<9 /* rmsc_msg */; 1514215976Sjmallett info.flags = 0; 1515215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1516215976Sjmallett info.group_index = 0; 1517215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1518215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1519215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1520215976Sjmallett info.func = __cvmx_error_display; 1521215976Sjmallett info.user_info = (long) 1522215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n"; 1523215976Sjmallett fail |= cvmx_error_add(&info); 1524215976Sjmallett 1525215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1526215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1527215976Sjmallett info.status_mask = 1ull<<10 /* tsr_abt */; 1528215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1529215976Sjmallett info.enable_mask = 1ull<<10 /* rtsr_abt */; 1530215976Sjmallett info.flags = 0; 1531215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1532215976Sjmallett info.group_index = 0; 1533215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1534215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1535215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1536215976Sjmallett info.func = __cvmx_error_display; 1537215976Sjmallett info.user_info = (long) 1538215976Sjmallett "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n"; 1539215976Sjmallett fail |= cvmx_error_add(&info); 1540215976Sjmallett 1541215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1542215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1543215976Sjmallett info.status_mask = 1ull<<11 /* serr */; 1544215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1545215976Sjmallett info.enable_mask = 1ull<<11 /* rserr */; 1546215976Sjmallett info.flags = 0; 1547215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1548215976Sjmallett info.group_index = 0; 1549215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1550215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1551215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1552215976Sjmallett info.func = __cvmx_error_display; 1553215976Sjmallett info.user_info = (long) 1554215976Sjmallett "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n"; 1555215976Sjmallett fail |= cvmx_error_add(&info); 1556215976Sjmallett 1557215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1558215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1559215976Sjmallett info.status_mask = 1ull<<12 /* aperr */; 1560215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1561215976Sjmallett info.enable_mask = 1ull<<12 /* raperr */; 1562215976Sjmallett info.flags = 0; 1563215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1564215976Sjmallett info.group_index = 0; 1565215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1566215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1567215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1568215976Sjmallett info.func = __cvmx_error_display; 1569215976Sjmallett info.user_info = (long) 1570215976Sjmallett "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n"; 1571215976Sjmallett fail |= cvmx_error_add(&info); 1572215976Sjmallett 1573215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1574215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1575215976Sjmallett info.status_mask = 1ull<<13 /* dperr */; 1576215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1577215976Sjmallett info.enable_mask = 1ull<<13 /* rdperr */; 1578215976Sjmallett info.flags = 0; 1579215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1580215976Sjmallett info.group_index = 0; 1581215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1582215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1583215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1584215976Sjmallett info.func = __cvmx_error_display; 1585215976Sjmallett info.user_info = (long) 1586215976Sjmallett "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n"; 1587215976Sjmallett fail |= cvmx_error_add(&info); 1588215976Sjmallett 1589215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1590215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1591215976Sjmallett info.status_mask = 1ull<<14 /* ill_rwr */; 1592215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1593215976Sjmallett info.enable_mask = 1ull<<14 /* ill_rwr */; 1594215976Sjmallett info.flags = 0; 1595215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1596215976Sjmallett info.group_index = 0; 1597215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1598215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1599215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1600215976Sjmallett info.func = __cvmx_error_display; 1601215976Sjmallett info.user_info = (long) 1602215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n"; 1603215976Sjmallett fail |= cvmx_error_add(&info); 1604215976Sjmallett 1605215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1606215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1607215976Sjmallett info.status_mask = 1ull<<15 /* ill_rrd */; 1608215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1609215976Sjmallett info.enable_mask = 1ull<<15 /* ill_rrd */; 1610215976Sjmallett info.flags = 0; 1611215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1612215976Sjmallett info.group_index = 0; 1613215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1614215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1615215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1616215976Sjmallett info.func = __cvmx_error_display; 1617215976Sjmallett info.user_info = (long) 1618215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n"; 1619215976Sjmallett fail |= cvmx_error_add(&info); 1620215976Sjmallett 1621215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1622215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1623215976Sjmallett info.status_mask = 1ull<<31 /* win_wr */; 1624215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1625215976Sjmallett info.enable_mask = 1ull<<31 /* win_wr */; 1626215976Sjmallett info.flags = 0; 1627215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1628215976Sjmallett info.group_index = 0; 1629215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1630215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1631215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1632215976Sjmallett info.func = __cvmx_error_display; 1633215976Sjmallett info.user_info = (long) 1634215976Sjmallett "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n" 1635215976Sjmallett " Read-Address Register took place.\n"; 1636215976Sjmallett fail |= cvmx_error_add(&info); 1637215976Sjmallett 1638215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1639215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1640215976Sjmallett info.status_mask = 1ull<<32 /* ill_wr */; 1641215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1642215976Sjmallett info.enable_mask = 1ull<<32 /* ill_wr */; 1643215976Sjmallett info.flags = 0; 1644215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1645215976Sjmallett info.group_index = 0; 1646215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1647215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1648215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1649215976Sjmallett info.func = __cvmx_error_display; 1650215976Sjmallett info.user_info = (long) 1651215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n" 1652215976Sjmallett " when the mem area is disabled.\n"; 1653215976Sjmallett fail |= cvmx_error_add(&info); 1654215976Sjmallett 1655215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1656215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1657215976Sjmallett info.status_mask = 1ull<<33 /* ill_rd */; 1658215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1659215976Sjmallett info.enable_mask = 1ull<<33 /* ill_rd */; 1660215976Sjmallett info.flags = 0; 1661215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1662215976Sjmallett info.group_index = 0; 1663215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1664215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1665215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1666215976Sjmallett info.func = __cvmx_error_display; 1667215976Sjmallett info.user_info = (long) 1668215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n" 1669215976Sjmallett " when the mem area is disabled.\n"; 1670215976Sjmallett fail |= cvmx_error_add(&info); 1671215976Sjmallett 1672215976Sjmallett /* CVMX_GMXX_BAD_REG(0) */ 1673215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1674215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1675215976Sjmallett info.status_mask = 1ull<<0 /* out_col */; 1676215976Sjmallett info.enable_addr = 0; 1677215976Sjmallett info.enable_mask = 0; 1678215976Sjmallett info.flags = 0; 1679215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1680215976Sjmallett info.group_index = 0; 1681215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1682215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1683215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1684215976Sjmallett info.func = __cvmx_error_display; 1685215976Sjmallett info.user_info = (long) 1686215976Sjmallett "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n"; 1687215976Sjmallett fail |= cvmx_error_add(&info); 1688215976Sjmallett 1689215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1690215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1691215976Sjmallett info.status_mask = 1ull<<1 /* ncb_ovr */; 1692215976Sjmallett info.enable_addr = 0; 1693215976Sjmallett info.enable_mask = 0; 1694215976Sjmallett info.flags = 0; 1695215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1696215976Sjmallett info.group_index = 0; 1697215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1698215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1699215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1700215976Sjmallett info.func = __cvmx_error_display; 1701215976Sjmallett info.user_info = (long) 1702215976Sjmallett "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n"; 1703215976Sjmallett fail |= cvmx_error_add(&info); 1704215976Sjmallett 1705215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1706215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1707215976Sjmallett info.status_mask = 0xffffull<<2 /* out_ovr */; 1708215976Sjmallett info.enable_addr = 0; 1709215976Sjmallett info.enable_mask = 0; 1710215976Sjmallett info.flags = 0; 1711215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1712215976Sjmallett info.group_index = 0; 1713215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1714215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1715215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1716215976Sjmallett info.func = __cvmx_error_display; 1717215976Sjmallett info.user_info = (long) 1718215976Sjmallett "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 1719215976Sjmallett fail |= cvmx_error_add(&info); 1720215976Sjmallett 1721215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1722215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1723215976Sjmallett info.status_mask = 0xfull<<22 /* loststat */; 1724215976Sjmallett info.enable_addr = 0; 1725215976Sjmallett info.enable_mask = 0; 1726215976Sjmallett info.flags = 0; 1727215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1728215976Sjmallett info.group_index = 0; 1729215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1730215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1731215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1732215976Sjmallett info.func = __cvmx_error_display; 1733215976Sjmallett info.user_info = (long) 1734215976Sjmallett "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n" 1735215976Sjmallett " TX Stats are corrupted\n"; 1736215976Sjmallett fail |= cvmx_error_add(&info); 1737215976Sjmallett 1738215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1739215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1740215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 1741215976Sjmallett info.enable_addr = 0; 1742215976Sjmallett info.enable_mask = 0; 1743215976Sjmallett info.flags = 0; 1744215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1745215976Sjmallett info.group_index = 0; 1746215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1747215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1748215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1749215976Sjmallett info.func = __cvmx_error_display; 1750215976Sjmallett info.user_info = (long) 1751215976Sjmallett "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"; 1752215976Sjmallett fail |= cvmx_error_add(&info); 1753215976Sjmallett 1754215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1755215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1756215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 1757215976Sjmallett info.enable_addr = 0; 1758215976Sjmallett info.enable_mask = 0; 1759215976Sjmallett info.flags = 0; 1760215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1761215976Sjmallett info.group_index = 0; 1762215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1763215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1764215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1765215976Sjmallett info.func = __cvmx_error_display; 1766215976Sjmallett info.user_info = (long) 1767215976Sjmallett "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 1768215976Sjmallett fail |= cvmx_error_add(&info); 1769215976Sjmallett 1770215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,0) */ 1771215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1772215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1773215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1774215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1775215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1776215976Sjmallett info.flags = 0; 1777215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1778215976Sjmallett info.group_index = 0; 1779215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1780215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1781215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1782215976Sjmallett info.func = __cvmx_error_display; 1783215976Sjmallett info.user_info = (long) 1784215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n"; 1785215976Sjmallett fail |= cvmx_error_add(&info); 1786215976Sjmallett 1787215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1788215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1789215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 1790215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1791215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 1792215976Sjmallett info.flags = 0; 1793215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1794215976Sjmallett info.group_index = 0; 1795215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1796215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1797215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1798215976Sjmallett info.func = __cvmx_error_display; 1799215976Sjmallett info.user_info = (long) 1800215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n"; 1801215976Sjmallett fail |= cvmx_error_add(&info); 1802215976Sjmallett 1803215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1804215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1805215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 1806215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1807215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 1808215976Sjmallett info.flags = 0; 1809215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1810215976Sjmallett info.group_index = 0; 1811215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1812215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1813215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1814215976Sjmallett info.func = __cvmx_error_display; 1815215976Sjmallett info.user_info = (long) 1816215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n"; 1817215976Sjmallett fail |= cvmx_error_add(&info); 1818215976Sjmallett 1819215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1820215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1821215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 1822215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1823215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 1824215976Sjmallett info.flags = 0; 1825215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1826215976Sjmallett info.group_index = 0; 1827215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1828215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1829215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1830215976Sjmallett info.func = __cvmx_error_display; 1831215976Sjmallett info.user_info = (long) 1832215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n"; 1833215976Sjmallett fail |= cvmx_error_add(&info); 1834215976Sjmallett 1835215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1836215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1837215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1838215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1839215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1840215976Sjmallett info.flags = 0; 1841215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1842215976Sjmallett info.group_index = 0; 1843215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1844215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1845215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1846215976Sjmallett info.func = __cvmx_error_display; 1847215976Sjmallett info.user_info = (long) 1848215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n"; 1849215976Sjmallett fail |= cvmx_error_add(&info); 1850215976Sjmallett 1851215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1852215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1853215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 1854215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1855215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 1856215976Sjmallett info.flags = 0; 1857215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1858215976Sjmallett info.group_index = 0; 1859215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1860215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1861215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1862215976Sjmallett info.func = __cvmx_error_display; 1863215976Sjmallett info.user_info = (long) 1864215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 1865215976Sjmallett fail |= cvmx_error_add(&info); 1866215976Sjmallett 1867215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1868215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1869215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1870215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1871215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1872215976Sjmallett info.flags = 0; 1873215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1874215976Sjmallett info.group_index = 0; 1875215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1876215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1877215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1878215976Sjmallett info.func = __cvmx_error_display; 1879215976Sjmallett info.user_info = (long) 1880215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1881215976Sjmallett " This interrupt should never assert\n"; 1882215976Sjmallett fail |= cvmx_error_add(&info); 1883215976Sjmallett 1884215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,0) */ 1885215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1886215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1887215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1888215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1889215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1890215976Sjmallett info.flags = 0; 1891215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1892215976Sjmallett info.group_index = 1; 1893215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1894215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1895215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1896215976Sjmallett info.func = __cvmx_error_display; 1897215976Sjmallett info.user_info = (long) 1898215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n"; 1899215976Sjmallett fail |= cvmx_error_add(&info); 1900215976Sjmallett 1901215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1902215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1903215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 1904215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1905215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 1906215976Sjmallett info.flags = 0; 1907215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1908215976Sjmallett info.group_index = 1; 1909215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1910215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1911215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1912215976Sjmallett info.func = __cvmx_error_display; 1913215976Sjmallett info.user_info = (long) 1914215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n"; 1915215976Sjmallett fail |= cvmx_error_add(&info); 1916215976Sjmallett 1917215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1918215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1919215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 1920215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1921215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 1922215976Sjmallett info.flags = 0; 1923215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1924215976Sjmallett info.group_index = 1; 1925215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1926215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1927215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1928215976Sjmallett info.func = __cvmx_error_display; 1929215976Sjmallett info.user_info = (long) 1930215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n"; 1931215976Sjmallett fail |= cvmx_error_add(&info); 1932215976Sjmallett 1933215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1934215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1935215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 1936215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1937215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 1938215976Sjmallett info.flags = 0; 1939215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1940215976Sjmallett info.group_index = 1; 1941215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1942215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1943215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1944215976Sjmallett info.func = __cvmx_error_display; 1945215976Sjmallett info.user_info = (long) 1946215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n"; 1947215976Sjmallett fail |= cvmx_error_add(&info); 1948215976Sjmallett 1949215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1950215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1951215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1952215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1953215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1954215976Sjmallett info.flags = 0; 1955215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1956215976Sjmallett info.group_index = 1; 1957215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1958215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1959215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1960215976Sjmallett info.func = __cvmx_error_display; 1961215976Sjmallett info.user_info = (long) 1962215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n"; 1963215976Sjmallett fail |= cvmx_error_add(&info); 1964215976Sjmallett 1965215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1966215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1967215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 1968215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1969215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 1970215976Sjmallett info.flags = 0; 1971215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1972215976Sjmallett info.group_index = 1; 1973215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1974215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1975215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1976215976Sjmallett info.func = __cvmx_error_display; 1977215976Sjmallett info.user_info = (long) 1978215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 1979215976Sjmallett fail |= cvmx_error_add(&info); 1980215976Sjmallett 1981215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1982215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1983215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1984215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1985215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1986215976Sjmallett info.flags = 0; 1987215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1988215976Sjmallett info.group_index = 1; 1989215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1990215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1991215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1992215976Sjmallett info.func = __cvmx_error_display; 1993215976Sjmallett info.user_info = (long) 1994215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1995215976Sjmallett " This interrupt should never assert\n"; 1996215976Sjmallett fail |= cvmx_error_add(&info); 1997215976Sjmallett 1998215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,0) */ 1999215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2000215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2001215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2002215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2003215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2004215976Sjmallett info.flags = 0; 2005215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2006215976Sjmallett info.group_index = 2; 2007215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2008215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2009215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2010215976Sjmallett info.func = __cvmx_error_display; 2011215976Sjmallett info.user_info = (long) 2012215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n"; 2013215976Sjmallett fail |= cvmx_error_add(&info); 2014215976Sjmallett 2015215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2016215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2017215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 2018215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2019215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 2020215976Sjmallett info.flags = 0; 2021215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2022215976Sjmallett info.group_index = 2; 2023215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2024215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2025215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2026215976Sjmallett info.func = __cvmx_error_display; 2027215976Sjmallett info.user_info = (long) 2028215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n"; 2029215976Sjmallett fail |= cvmx_error_add(&info); 2030215976Sjmallett 2031215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2032215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2033215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 2034215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2035215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 2036215976Sjmallett info.flags = 0; 2037215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2038215976Sjmallett info.group_index = 2; 2039215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2040215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2041215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2042215976Sjmallett info.func = __cvmx_error_display; 2043215976Sjmallett info.user_info = (long) 2044215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n"; 2045215976Sjmallett fail |= cvmx_error_add(&info); 2046215976Sjmallett 2047215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2048215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2049215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 2050215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2051215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 2052215976Sjmallett info.flags = 0; 2053215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2054215976Sjmallett info.group_index = 2; 2055215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2056215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2057215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2058215976Sjmallett info.func = __cvmx_error_display; 2059215976Sjmallett info.user_info = (long) 2060215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n"; 2061215976Sjmallett fail |= cvmx_error_add(&info); 2062215976Sjmallett 2063215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2064215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2065215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2066215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2067215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2068215976Sjmallett info.flags = 0; 2069215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2070215976Sjmallett info.group_index = 2; 2071215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2072215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2073215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2074215976Sjmallett info.func = __cvmx_error_display; 2075215976Sjmallett info.user_info = (long) 2076215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n"; 2077215976Sjmallett fail |= cvmx_error_add(&info); 2078215976Sjmallett 2079215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2080215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2081215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 2082215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2083215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 2084215976Sjmallett info.flags = 0; 2085215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2086215976Sjmallett info.group_index = 2; 2087215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2088215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2089215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2090215976Sjmallett info.func = __cvmx_error_display; 2091215976Sjmallett info.user_info = (long) 2092215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 2093215976Sjmallett fail |= cvmx_error_add(&info); 2094215976Sjmallett 2095215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2096215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2097215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2098215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2099215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2100215976Sjmallett info.flags = 0; 2101215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2102215976Sjmallett info.group_index = 2; 2103215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2104215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2105215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2106215976Sjmallett info.func = __cvmx_error_display; 2107215976Sjmallett info.user_info = (long) 2108215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n" 2109215976Sjmallett " This interrupt should never assert\n"; 2110215976Sjmallett fail |= cvmx_error_add(&info); 2111215976Sjmallett 2112215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(3,0) */ 2113215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2114215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 2115215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2116215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 2117215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2118215976Sjmallett info.flags = 0; 2119215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2120215976Sjmallett info.group_index = 3; 2121215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2122215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2123215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2124215976Sjmallett info.func = __cvmx_error_display; 2125215976Sjmallett info.user_info = (long) 2126215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n"; 2127215976Sjmallett fail |= cvmx_error_add(&info); 2128215976Sjmallett 2129215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2130215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 2131215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 2132215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 2133215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 2134215976Sjmallett info.flags = 0; 2135215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2136215976Sjmallett info.group_index = 3; 2137215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2138215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2139215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2140215976Sjmallett info.func = __cvmx_error_display; 2141215976Sjmallett info.user_info = (long) 2142215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n"; 2143215976Sjmallett fail |= cvmx_error_add(&info); 2144215976Sjmallett 2145215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2146215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 2147215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 2148215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 2149215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 2150215976Sjmallett info.flags = 0; 2151215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2152215976Sjmallett info.group_index = 3; 2153215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2154215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2155215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2156215976Sjmallett info.func = __cvmx_error_display; 2157215976Sjmallett info.user_info = (long) 2158215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n"; 2159215976Sjmallett fail |= cvmx_error_add(&info); 2160215976Sjmallett 2161215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2162215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 2163215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 2164215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 2165215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 2166215976Sjmallett info.flags = 0; 2167215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2168215976Sjmallett info.group_index = 3; 2169215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2170215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2171215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2172215976Sjmallett info.func = __cvmx_error_display; 2173215976Sjmallett info.user_info = (long) 2174215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n"; 2175215976Sjmallett fail |= cvmx_error_add(&info); 2176215976Sjmallett 2177215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2178215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 2179215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2180215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 2181215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2182215976Sjmallett info.flags = 0; 2183215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2184215976Sjmallett info.group_index = 3; 2185215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2186215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2187215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2188215976Sjmallett info.func = __cvmx_error_display; 2189215976Sjmallett info.user_info = (long) 2190215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n"; 2191215976Sjmallett fail |= cvmx_error_add(&info); 2192215976Sjmallett 2193215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2194215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 2195215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 2196215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 2197215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 2198215976Sjmallett info.flags = 0; 2199215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2200215976Sjmallett info.group_index = 3; 2201215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2202215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2203215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2204215976Sjmallett info.func = __cvmx_error_display; 2205215976Sjmallett info.user_info = (long) 2206215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 2207215976Sjmallett fail |= cvmx_error_add(&info); 2208215976Sjmallett 2209215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2210215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 2211215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2212215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 2213215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2214215976Sjmallett info.flags = 0; 2215215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2216215976Sjmallett info.group_index = 3; 2217215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2218215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2219215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2220215976Sjmallett info.func = __cvmx_error_display; 2221215976Sjmallett info.user_info = (long) 2222215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n" 2223215976Sjmallett " This interrupt should never assert\n"; 2224215976Sjmallett fail |= cvmx_error_add(&info); 2225215976Sjmallett 2226215976Sjmallett /* CVMX_GMXX_TX_INT_REG(0) */ 2227215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2228215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 2229215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 2230215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 2231215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 2232215976Sjmallett info.flags = 0; 2233215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2234215976Sjmallett info.group_index = 0; 2235215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2236215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2237215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2238215976Sjmallett info.func = __cvmx_error_display; 2239215976Sjmallett info.user_info = (long) 2240215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 2241215976Sjmallett fail |= cvmx_error_add(&info); 2242215976Sjmallett 2243215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2244215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 2245215976Sjmallett info.status_mask = 1ull<<1 /* ncb_nxa */; 2246215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 2247215976Sjmallett info.enable_mask = 1ull<<1 /* ncb_nxa */; 2248215976Sjmallett info.flags = 0; 2249215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2250215976Sjmallett info.group_index = 0; 2251215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2252215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2253215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2254215976Sjmallett info.func = __cvmx_error_display; 2255215976Sjmallett info.user_info = (long) 2256215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n"; 2257215976Sjmallett fail |= cvmx_error_add(&info); 2258215976Sjmallett 2259215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2260215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 2261215976Sjmallett info.status_mask = 0xfull<<2 /* undflw */; 2262215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 2263215976Sjmallett info.enable_mask = 0xfull<<2 /* undflw */; 2264215976Sjmallett info.flags = 0; 2265215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2266215976Sjmallett info.group_index = 0; 2267215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2268215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2269215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2270215976Sjmallett info.func = __cvmx_error_display; 2271215976Sjmallett info.user_info = (long) 2272215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n"; 2273215976Sjmallett fail |= cvmx_error_add(&info); 2274215976Sjmallett 2275215976Sjmallett /* CVMX_GMXX_BAD_REG(1) */ 2276215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2277215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 2278215976Sjmallett info.status_mask = 1ull<<0 /* out_col */; 2279215976Sjmallett info.enable_addr = 0; 2280215976Sjmallett info.enable_mask = 0; 2281215976Sjmallett info.flags = 0; 2282215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2283215976Sjmallett info.group_index = 16; 2284215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2285215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2286215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2287215976Sjmallett info.func = __cvmx_error_display; 2288215976Sjmallett info.user_info = (long) 2289215976Sjmallett "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n"; 2290215976Sjmallett fail |= cvmx_error_add(&info); 2291215976Sjmallett 2292215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2293215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 2294215976Sjmallett info.status_mask = 1ull<<1 /* ncb_ovr */; 2295215976Sjmallett info.enable_addr = 0; 2296215976Sjmallett info.enable_mask = 0; 2297215976Sjmallett info.flags = 0; 2298215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2299215976Sjmallett info.group_index = 16; 2300215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2301215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2302215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2303215976Sjmallett info.func = __cvmx_error_display; 2304215976Sjmallett info.user_info = (long) 2305215976Sjmallett "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n"; 2306215976Sjmallett fail |= cvmx_error_add(&info); 2307215976Sjmallett 2308215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2309215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 2310215976Sjmallett info.status_mask = 0xffffull<<2 /* out_ovr */; 2311215976Sjmallett info.enable_addr = 0; 2312215976Sjmallett info.enable_mask = 0; 2313215976Sjmallett info.flags = 0; 2314215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2315215976Sjmallett info.group_index = 16; 2316215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2317215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2318215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2319215976Sjmallett info.func = __cvmx_error_display; 2320215976Sjmallett info.user_info = (long) 2321215976Sjmallett "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 2322215976Sjmallett fail |= cvmx_error_add(&info); 2323215976Sjmallett 2324215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2325215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 2326215976Sjmallett info.status_mask = 0xfull<<22 /* loststat */; 2327215976Sjmallett info.enable_addr = 0; 2328215976Sjmallett info.enable_mask = 0; 2329215976Sjmallett info.flags = 0; 2330215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2331215976Sjmallett info.group_index = 16; 2332215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2333215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2334215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2335215976Sjmallett info.func = __cvmx_error_display; 2336215976Sjmallett info.user_info = (long) 2337215976Sjmallett "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n" 2338215976Sjmallett " TX Stats are corrupted\n"; 2339215976Sjmallett fail |= cvmx_error_add(&info); 2340215976Sjmallett 2341215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2342215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 2343215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 2344215976Sjmallett info.enable_addr = 0; 2345215976Sjmallett info.enable_mask = 0; 2346215976Sjmallett info.flags = 0; 2347215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2348215976Sjmallett info.group_index = 16; 2349215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2350215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2351215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2352215976Sjmallett info.func = __cvmx_error_display; 2353215976Sjmallett info.user_info = (long) 2354215976Sjmallett "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"; 2355215976Sjmallett fail |= cvmx_error_add(&info); 2356215976Sjmallett 2357215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2358215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 2359215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 2360215976Sjmallett info.enable_addr = 0; 2361215976Sjmallett info.enable_mask = 0; 2362215976Sjmallett info.flags = 0; 2363215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2364215976Sjmallett info.group_index = 16; 2365215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2366215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2367215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2368215976Sjmallett info.func = __cvmx_error_display; 2369215976Sjmallett info.user_info = (long) 2370215976Sjmallett "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 2371215976Sjmallett fail |= cvmx_error_add(&info); 2372215976Sjmallett 2373215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,1) */ 2374215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2375215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2376215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2377215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2378215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2379215976Sjmallett info.flags = 0; 2380215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2381215976Sjmallett info.group_index = 16; 2382215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2383215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2384215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2385215976Sjmallett info.func = __cvmx_error_display; 2386215976Sjmallett info.user_info = (long) 2387215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n"; 2388215976Sjmallett fail |= cvmx_error_add(&info); 2389215976Sjmallett 2390215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2391215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2392215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 2393215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2394215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 2395215976Sjmallett info.flags = 0; 2396215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2397215976Sjmallett info.group_index = 16; 2398215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2399215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2400215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2401215976Sjmallett info.func = __cvmx_error_display; 2402215976Sjmallett info.user_info = (long) 2403215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n"; 2404215976Sjmallett fail |= cvmx_error_add(&info); 2405215976Sjmallett 2406215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2407215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2408215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 2409215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2410215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 2411215976Sjmallett info.flags = 0; 2412215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2413215976Sjmallett info.group_index = 16; 2414215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2415215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2416215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2417215976Sjmallett info.func = __cvmx_error_display; 2418215976Sjmallett info.user_info = (long) 2419215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n"; 2420215976Sjmallett fail |= cvmx_error_add(&info); 2421215976Sjmallett 2422215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2423215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2424215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 2425215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2426215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 2427215976Sjmallett info.flags = 0; 2428215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2429215976Sjmallett info.group_index = 16; 2430215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2431215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2432215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2433215976Sjmallett info.func = __cvmx_error_display; 2434215976Sjmallett info.user_info = (long) 2435215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n"; 2436215976Sjmallett fail |= cvmx_error_add(&info); 2437215976Sjmallett 2438215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2439215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2440215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2441215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2442215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2443215976Sjmallett info.flags = 0; 2444215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2445215976Sjmallett info.group_index = 16; 2446215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2447215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2448215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2449215976Sjmallett info.func = __cvmx_error_display; 2450215976Sjmallett info.user_info = (long) 2451215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n"; 2452215976Sjmallett fail |= cvmx_error_add(&info); 2453215976Sjmallett 2454215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2455215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2456215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 2457215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2458215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 2459215976Sjmallett info.flags = 0; 2460215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2461215976Sjmallett info.group_index = 16; 2462215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2463215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2464215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2465215976Sjmallett info.func = __cvmx_error_display; 2466215976Sjmallett info.user_info = (long) 2467215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 2468215976Sjmallett fail |= cvmx_error_add(&info); 2469215976Sjmallett 2470215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2471215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2472215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2473215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2474215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2475215976Sjmallett info.flags = 0; 2476215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2477215976Sjmallett info.group_index = 16; 2478215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2479215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2480215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2481215976Sjmallett info.func = __cvmx_error_display; 2482215976Sjmallett info.user_info = (long) 2483215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n" 2484215976Sjmallett " This interrupt should never assert\n"; 2485215976Sjmallett fail |= cvmx_error_add(&info); 2486215976Sjmallett 2487215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,1) */ 2488215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2489215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2490215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2491215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2492215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2493215976Sjmallett info.flags = 0; 2494215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2495215976Sjmallett info.group_index = 17; 2496215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2497215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2498215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2499215976Sjmallett info.func = __cvmx_error_display; 2500215976Sjmallett info.user_info = (long) 2501215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n"; 2502215976Sjmallett fail |= cvmx_error_add(&info); 2503215976Sjmallett 2504215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2505215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2506215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 2507215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2508215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 2509215976Sjmallett info.flags = 0; 2510215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2511215976Sjmallett info.group_index = 17; 2512215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2513215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2514215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2515215976Sjmallett info.func = __cvmx_error_display; 2516215976Sjmallett info.user_info = (long) 2517215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n"; 2518215976Sjmallett fail |= cvmx_error_add(&info); 2519215976Sjmallett 2520215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2521215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2522215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 2523215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2524215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 2525215976Sjmallett info.flags = 0; 2526215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2527215976Sjmallett info.group_index = 17; 2528215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2529215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2530215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2531215976Sjmallett info.func = __cvmx_error_display; 2532215976Sjmallett info.user_info = (long) 2533215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n"; 2534215976Sjmallett fail |= cvmx_error_add(&info); 2535215976Sjmallett 2536215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2537215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2538215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 2539215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2540215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 2541215976Sjmallett info.flags = 0; 2542215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2543215976Sjmallett info.group_index = 17; 2544215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2545215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2546215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2547215976Sjmallett info.func = __cvmx_error_display; 2548215976Sjmallett info.user_info = (long) 2549215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n"; 2550215976Sjmallett fail |= cvmx_error_add(&info); 2551215976Sjmallett 2552215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2553215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2554215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2555215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2556215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2557215976Sjmallett info.flags = 0; 2558215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2559215976Sjmallett info.group_index = 17; 2560215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2561215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2562215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2563215976Sjmallett info.func = __cvmx_error_display; 2564215976Sjmallett info.user_info = (long) 2565215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n"; 2566215976Sjmallett fail |= cvmx_error_add(&info); 2567215976Sjmallett 2568215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2569215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2570215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 2571215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2572215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 2573215976Sjmallett info.flags = 0; 2574215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2575215976Sjmallett info.group_index = 17; 2576215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2577215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2578215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2579215976Sjmallett info.func = __cvmx_error_display; 2580215976Sjmallett info.user_info = (long) 2581215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 2582215976Sjmallett fail |= cvmx_error_add(&info); 2583215976Sjmallett 2584215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2585215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2586215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2587215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2588215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2589215976Sjmallett info.flags = 0; 2590215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2591215976Sjmallett info.group_index = 17; 2592215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2593215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2594215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2595215976Sjmallett info.func = __cvmx_error_display; 2596215976Sjmallett info.user_info = (long) 2597215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n" 2598215976Sjmallett " This interrupt should never assert\n"; 2599215976Sjmallett fail |= cvmx_error_add(&info); 2600215976Sjmallett 2601215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,1) */ 2602215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2603215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2604215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2605215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2606215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2607215976Sjmallett info.flags = 0; 2608215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2609215976Sjmallett info.group_index = 18; 2610215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2611215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2612215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2613215976Sjmallett info.func = __cvmx_error_display; 2614215976Sjmallett info.user_info = (long) 2615215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n"; 2616215976Sjmallett fail |= cvmx_error_add(&info); 2617215976Sjmallett 2618215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2619215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2620215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 2621215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2622215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 2623215976Sjmallett info.flags = 0; 2624215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2625215976Sjmallett info.group_index = 18; 2626215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2627215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2628215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2629215976Sjmallett info.func = __cvmx_error_display; 2630215976Sjmallett info.user_info = (long) 2631215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n"; 2632215976Sjmallett fail |= cvmx_error_add(&info); 2633215976Sjmallett 2634215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2635215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2636215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 2637215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2638215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 2639215976Sjmallett info.flags = 0; 2640215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2641215976Sjmallett info.group_index = 18; 2642215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2643215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2644215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2645215976Sjmallett info.func = __cvmx_error_display; 2646215976Sjmallett info.user_info = (long) 2647215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n"; 2648215976Sjmallett fail |= cvmx_error_add(&info); 2649215976Sjmallett 2650215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2651215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2652215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 2653215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2654215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 2655215976Sjmallett info.flags = 0; 2656215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2657215976Sjmallett info.group_index = 18; 2658215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2659215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2660215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2661215976Sjmallett info.func = __cvmx_error_display; 2662215976Sjmallett info.user_info = (long) 2663215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n"; 2664215976Sjmallett fail |= cvmx_error_add(&info); 2665215976Sjmallett 2666215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2667215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2668215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2669215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2670215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2671215976Sjmallett info.flags = 0; 2672215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2673215976Sjmallett info.group_index = 18; 2674215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2675215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2676215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2677215976Sjmallett info.func = __cvmx_error_display; 2678215976Sjmallett info.user_info = (long) 2679215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n"; 2680215976Sjmallett fail |= cvmx_error_add(&info); 2681215976Sjmallett 2682215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2683215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2684215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 2685215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2686215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 2687215976Sjmallett info.flags = 0; 2688215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2689215976Sjmallett info.group_index = 18; 2690215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2691215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2692215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2693215976Sjmallett info.func = __cvmx_error_display; 2694215976Sjmallett info.user_info = (long) 2695215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 2696215976Sjmallett fail |= cvmx_error_add(&info); 2697215976Sjmallett 2698215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2699215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2700215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2701215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2702215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2703215976Sjmallett info.flags = 0; 2704215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2705215976Sjmallett info.group_index = 18; 2706215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2707215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2708215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2709215976Sjmallett info.func = __cvmx_error_display; 2710215976Sjmallett info.user_info = (long) 2711215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n" 2712215976Sjmallett " This interrupt should never assert\n"; 2713215976Sjmallett fail |= cvmx_error_add(&info); 2714215976Sjmallett 2715215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(3,1) */ 2716215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2717215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2718215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2719215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2720215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2721215976Sjmallett info.flags = 0; 2722215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2723215976Sjmallett info.group_index = 19; 2724215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2725215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2726215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2727215976Sjmallett info.func = __cvmx_error_display; 2728215976Sjmallett info.user_info = (long) 2729215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n"; 2730215976Sjmallett fail |= cvmx_error_add(&info); 2731215976Sjmallett 2732215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2733215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2734215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 2735215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2736215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 2737215976Sjmallett info.flags = 0; 2738215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2739215976Sjmallett info.group_index = 19; 2740215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2741215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2742215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2743215976Sjmallett info.func = __cvmx_error_display; 2744215976Sjmallett info.user_info = (long) 2745215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n"; 2746215976Sjmallett fail |= cvmx_error_add(&info); 2747215976Sjmallett 2748215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2749215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2750215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 2751215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2752215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 2753215976Sjmallett info.flags = 0; 2754215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2755215976Sjmallett info.group_index = 19; 2756215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2757215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2758215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2759215976Sjmallett info.func = __cvmx_error_display; 2760215976Sjmallett info.user_info = (long) 2761215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n"; 2762215976Sjmallett fail |= cvmx_error_add(&info); 2763215976Sjmallett 2764215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2765215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2766215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 2767215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2768215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 2769215976Sjmallett info.flags = 0; 2770215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2771215976Sjmallett info.group_index = 19; 2772215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2773215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2774215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2775215976Sjmallett info.func = __cvmx_error_display; 2776215976Sjmallett info.user_info = (long) 2777215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n"; 2778215976Sjmallett fail |= cvmx_error_add(&info); 2779215976Sjmallett 2780215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2781215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2782215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2783215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2784215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2785215976Sjmallett info.flags = 0; 2786215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2787215976Sjmallett info.group_index = 19; 2788215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2789215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2790215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2791215976Sjmallett info.func = __cvmx_error_display; 2792215976Sjmallett info.user_info = (long) 2793215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n"; 2794215976Sjmallett fail |= cvmx_error_add(&info); 2795215976Sjmallett 2796215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2797215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2798215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 2799215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2800215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 2801215976Sjmallett info.flags = 0; 2802215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2803215976Sjmallett info.group_index = 19; 2804215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2805215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2806215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2807215976Sjmallett info.func = __cvmx_error_display; 2808215976Sjmallett info.user_info = (long) 2809215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 2810215976Sjmallett fail |= cvmx_error_add(&info); 2811215976Sjmallett 2812215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2813215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2814215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2815215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2816215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2817215976Sjmallett info.flags = 0; 2818215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2819215976Sjmallett info.group_index = 19; 2820215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2821215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2822215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2823215976Sjmallett info.func = __cvmx_error_display; 2824215976Sjmallett info.user_info = (long) 2825215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n" 2826215976Sjmallett " This interrupt should never assert\n"; 2827215976Sjmallett fail |= cvmx_error_add(&info); 2828215976Sjmallett 2829215976Sjmallett /* CVMX_GMXX_TX_INT_REG(1) */ 2830215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2831215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(1); 2832215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 2833215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(1); 2834215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 2835215976Sjmallett info.flags = 0; 2836215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2837215976Sjmallett info.group_index = 16; 2838215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2839215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2840215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2841215976Sjmallett info.func = __cvmx_error_display; 2842215976Sjmallett info.user_info = (long) 2843215976Sjmallett "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 2844215976Sjmallett fail |= cvmx_error_add(&info); 2845215976Sjmallett 2846215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2847215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(1); 2848215976Sjmallett info.status_mask = 1ull<<1 /* ncb_nxa */; 2849215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(1); 2850215976Sjmallett info.enable_mask = 1ull<<1 /* ncb_nxa */; 2851215976Sjmallett info.flags = 0; 2852215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2853215976Sjmallett info.group_index = 16; 2854215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2855215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2856215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2857215976Sjmallett info.func = __cvmx_error_display; 2858215976Sjmallett info.user_info = (long) 2859215976Sjmallett "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n"; 2860215976Sjmallett fail |= cvmx_error_add(&info); 2861215976Sjmallett 2862215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2863215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(1); 2864215976Sjmallett info.status_mask = 0xfull<<2 /* undflw */; 2865215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(1); 2866215976Sjmallett info.enable_mask = 0xfull<<2 /* undflw */; 2867215976Sjmallett info.flags = 0; 2868215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2869215976Sjmallett info.group_index = 16; 2870215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2871215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2872215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2873215976Sjmallett info.func = __cvmx_error_display; 2874215976Sjmallett info.user_info = (long) 2875215976Sjmallett "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n"; 2876215976Sjmallett fail |= cvmx_error_add(&info); 2877215976Sjmallett 2878215976Sjmallett /* CVMX_IPD_INT_SUM */ 2879215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2880215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2881215976Sjmallett info.status_mask = 1ull<<0 /* prc_par0 */; 2882215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2883215976Sjmallett info.enable_mask = 1ull<<0 /* prc_par0 */; 2884215976Sjmallett info.flags = 0; 2885215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2886215976Sjmallett info.group_index = 0; 2887215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2888215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2889215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2890215976Sjmallett info.func = __cvmx_error_display; 2891215976Sjmallett info.user_info = (long) 2892215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n" 2893215976Sjmallett " [31:0] of the PBM memory.\n"; 2894215976Sjmallett fail |= cvmx_error_add(&info); 2895215976Sjmallett 2896215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2897215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2898215976Sjmallett info.status_mask = 1ull<<1 /* prc_par1 */; 2899215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2900215976Sjmallett info.enable_mask = 1ull<<1 /* prc_par1 */; 2901215976Sjmallett info.flags = 0; 2902215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2903215976Sjmallett info.group_index = 0; 2904215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2905215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2906215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2907215976Sjmallett info.func = __cvmx_error_display; 2908215976Sjmallett info.user_info = (long) 2909215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n" 2910215976Sjmallett " [63:32] of the PBM memory.\n"; 2911215976Sjmallett fail |= cvmx_error_add(&info); 2912215976Sjmallett 2913215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2914215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2915215976Sjmallett info.status_mask = 1ull<<2 /* prc_par2 */; 2916215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2917215976Sjmallett info.enable_mask = 1ull<<2 /* prc_par2 */; 2918215976Sjmallett info.flags = 0; 2919215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2920215976Sjmallett info.group_index = 0; 2921215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2922215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2923215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2924215976Sjmallett info.func = __cvmx_error_display; 2925215976Sjmallett info.user_info = (long) 2926215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n" 2927215976Sjmallett " [95:64] of the PBM memory.\n"; 2928215976Sjmallett fail |= cvmx_error_add(&info); 2929215976Sjmallett 2930215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2931215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2932215976Sjmallett info.status_mask = 1ull<<3 /* prc_par3 */; 2933215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2934215976Sjmallett info.enable_mask = 1ull<<3 /* prc_par3 */; 2935215976Sjmallett info.flags = 0; 2936215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2937215976Sjmallett info.group_index = 0; 2938215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2939215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2940215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2941215976Sjmallett info.func = __cvmx_error_display; 2942215976Sjmallett info.user_info = (long) 2943215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n" 2944215976Sjmallett " [127:96] of the PBM memory.\n"; 2945215976Sjmallett fail |= cvmx_error_add(&info); 2946215976Sjmallett 2947215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2948215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2949215976Sjmallett info.status_mask = 1ull<<4 /* bp_sub */; 2950215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2951215976Sjmallett info.enable_mask = 1ull<<4 /* bp_sub */; 2952215976Sjmallett info.flags = 0; 2953215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2954215976Sjmallett info.group_index = 0; 2955215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2956215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2957215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2958215976Sjmallett info.func = __cvmx_error_display; 2959215976Sjmallett info.user_info = (long) 2960215976Sjmallett "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n" 2961215976Sjmallett " supplied illegal value.\n"; 2962215976Sjmallett fail |= cvmx_error_add(&info); 2963215976Sjmallett 2964215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2965215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2966215976Sjmallett info.status_mask = 1ull<<5 /* dc_ovr */; 2967215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2968215976Sjmallett info.enable_mask = 1ull<<5 /* dc_ovr */; 2969215976Sjmallett info.flags = 0; 2970215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2971215976Sjmallett info.group_index = 0; 2972215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2973215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2974215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2975215976Sjmallett info.func = __cvmx_error_display; 2976215976Sjmallett info.user_info = (long) 2977215976Sjmallett "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n" 2978215976Sjmallett " This is a PASS-3 Field.\n"; 2979215976Sjmallett fail |= cvmx_error_add(&info); 2980215976Sjmallett 2981215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2982215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2983215976Sjmallett info.status_mask = 1ull<<6 /* cc_ovr */; 2984215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2985215976Sjmallett info.enable_mask = 1ull<<6 /* cc_ovr */; 2986215976Sjmallett info.flags = 0; 2987215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2988215976Sjmallett info.group_index = 0; 2989215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2990215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2991215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2992215976Sjmallett info.func = __cvmx_error_display; 2993215976Sjmallett info.user_info = (long) 2994215976Sjmallett "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n" 2995215976Sjmallett " This is a PASS-3 Field.\n"; 2996215976Sjmallett fail |= cvmx_error_add(&info); 2997215976Sjmallett 2998215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2999215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 3000215976Sjmallett info.status_mask = 1ull<<7 /* c_coll */; 3001215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 3002215976Sjmallett info.enable_mask = 1ull<<7 /* c_coll */; 3003215976Sjmallett info.flags = 0; 3004215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3005215976Sjmallett info.group_index = 0; 3006215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3007215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3008215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 3009215976Sjmallett info.func = __cvmx_error_display; 3010215976Sjmallett info.user_info = (long) 3011215976Sjmallett "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n" 3012215976Sjmallett " collides.\n" 3013215976Sjmallett " This is a PASS-3 Field.\n"; 3014215976Sjmallett fail |= cvmx_error_add(&info); 3015215976Sjmallett 3016215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3017215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 3018215976Sjmallett info.status_mask = 1ull<<8 /* d_coll */; 3019215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 3020215976Sjmallett info.enable_mask = 1ull<<8 /* d_coll */; 3021215976Sjmallett info.flags = 0; 3022215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3023215976Sjmallett info.group_index = 0; 3024215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3025215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3026215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 3027215976Sjmallett info.func = __cvmx_error_display; 3028215976Sjmallett info.user_info = (long) 3029215976Sjmallett "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n" 3030215976Sjmallett " collides.\n" 3031215976Sjmallett " This is a PASS-3 Field.\n"; 3032215976Sjmallett fail |= cvmx_error_add(&info); 3033215976Sjmallett 3034215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3035215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 3036215976Sjmallett info.status_mask = 1ull<<9 /* bc_ovr */; 3037215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 3038215976Sjmallett info.enable_mask = 1ull<<9 /* bc_ovr */; 3039215976Sjmallett info.flags = 0; 3040215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3041215976Sjmallett info.group_index = 0; 3042215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3043215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3044215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 3045215976Sjmallett info.func = __cvmx_error_display; 3046215976Sjmallett info.user_info = (long) 3047215976Sjmallett "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n" 3048215976Sjmallett " This is a PASS-3 Field.\n"; 3049215976Sjmallett fail |= cvmx_error_add(&info); 3050215976Sjmallett 3051215976Sjmallett /* CVMX_SPXX_INT_REG(0) */ 3052215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3053215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3054215976Sjmallett info.status_mask = 1ull<<0 /* prtnxa */; 3055215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3056215976Sjmallett info.enable_mask = 1ull<<0 /* prtnxa */; 3057215976Sjmallett info.flags = 0; 3058215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3059215976Sjmallett info.group_index = 0; 3060215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3061215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3062215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3063215976Sjmallett info.func = __cvmx_error_display; 3064215976Sjmallett info.user_info = (long) 3065215976Sjmallett "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n"; 3066215976Sjmallett fail |= cvmx_error_add(&info); 3067215976Sjmallett 3068215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3069215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3070215976Sjmallett info.status_mask = 1ull<<1 /* abnorm */; 3071215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3072215976Sjmallett info.enable_mask = 1ull<<1 /* abnorm */; 3073215976Sjmallett info.flags = 0; 3074215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3075215976Sjmallett info.group_index = 0; 3076215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3077215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3078215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3079215976Sjmallett info.func = __cvmx_error_display; 3080215976Sjmallett info.user_info = (long) 3081215976Sjmallett "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n"; 3082215976Sjmallett fail |= cvmx_error_add(&info); 3083215976Sjmallett 3084215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3085215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3086215976Sjmallett info.status_mask = 1ull<<4 /* spiovr */; 3087215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3088215976Sjmallett info.enable_mask = 1ull<<4 /* spiovr */; 3089215976Sjmallett info.flags = 0; 3090215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3091215976Sjmallett info.group_index = 0; 3092215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3093215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3094215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3095215976Sjmallett info.func = __cvmx_error_display; 3096215976Sjmallett info.user_info = (long) 3097215976Sjmallett "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n"; 3098215976Sjmallett fail |= cvmx_error_add(&info); 3099215976Sjmallett 3100215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3101215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3102215976Sjmallett info.status_mask = 1ull<<5 /* clserr */; 3103215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3104215976Sjmallett info.enable_mask = 1ull<<5 /* clserr */; 3105215976Sjmallett info.flags = 0; 3106215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3107215976Sjmallett info.group_index = 0; 3108215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3109215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3110215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3111215976Sjmallett info.func = __cvmx_error_display; 3112215976Sjmallett info.user_info = (long) 3113215976Sjmallett "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n"; 3114215976Sjmallett fail |= cvmx_error_add(&info); 3115215976Sjmallett 3116215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3117215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3118215976Sjmallett info.status_mask = 1ull<<6 /* drwnng */; 3119215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3120215976Sjmallett info.enable_mask = 1ull<<6 /* drwnng */; 3121215976Sjmallett info.flags = 0; 3122215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3123215976Sjmallett info.group_index = 0; 3124215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3125215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3126215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3127215976Sjmallett info.func = __cvmx_error_display; 3128215976Sjmallett info.user_info = (long) 3129215976Sjmallett "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n"; 3130215976Sjmallett fail |= cvmx_error_add(&info); 3131215976Sjmallett 3132215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3133215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3134215976Sjmallett info.status_mask = 1ull<<7 /* rsverr */; 3135215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3136215976Sjmallett info.enable_mask = 1ull<<7 /* rsverr */; 3137215976Sjmallett info.flags = 0; 3138215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3139215976Sjmallett info.group_index = 0; 3140215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3141215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3142215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3143215976Sjmallett info.func = __cvmx_error_display; 3144215976Sjmallett info.user_info = (long) 3145215976Sjmallett "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n"; 3146215976Sjmallett fail |= cvmx_error_add(&info); 3147215976Sjmallett 3148215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3149215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3150215976Sjmallett info.status_mask = 1ull<<8 /* tpaovr */; 3151215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3152215976Sjmallett info.enable_mask = 1ull<<8 /* tpaovr */; 3153215976Sjmallett info.flags = 0; 3154215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3155215976Sjmallett info.group_index = 0; 3156215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3157215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3158215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3159215976Sjmallett info.func = __cvmx_error_display; 3160215976Sjmallett info.user_info = (long) 3161215976Sjmallett "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n"; 3162215976Sjmallett fail |= cvmx_error_add(&info); 3163215976Sjmallett 3164215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3165215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3166215976Sjmallett info.status_mask = 1ull<<9 /* diperr */; 3167215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3168215976Sjmallett info.enable_mask = 1ull<<9 /* diperr */; 3169215976Sjmallett info.flags = 0; 3170215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3171215976Sjmallett info.group_index = 0; 3172215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3173215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3174215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3175215976Sjmallett info.func = __cvmx_error_display; 3176215976Sjmallett info.user_info = (long) 3177215976Sjmallett "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n"; 3178215976Sjmallett fail |= cvmx_error_add(&info); 3179215976Sjmallett 3180215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3181215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3182215976Sjmallett info.status_mask = 1ull<<10 /* syncerr */; 3183215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3184215976Sjmallett info.enable_mask = 1ull<<10 /* syncerr */; 3185215976Sjmallett info.flags = 0; 3186215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3187215976Sjmallett info.group_index = 0; 3188215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3189215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3190215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3191215976Sjmallett info.func = __cvmx_error_display; 3192215976Sjmallett info.user_info = (long) 3193215976Sjmallett "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n" 3194215976Sjmallett " SPX_ERR_CTL[ERRCNT]\n"; 3195215976Sjmallett fail |= cvmx_error_add(&info); 3196215976Sjmallett 3197215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3198215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(0); 3199215976Sjmallett info.status_mask = 1ull<<11 /* calerr */; 3200215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(0); 3201215976Sjmallett info.enable_mask = 1ull<<11 /* calerr */; 3202215976Sjmallett info.flags = 0; 3203215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3204215976Sjmallett info.group_index = 0; 3205215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3206215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3207215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3208215976Sjmallett info.func = __cvmx_error_display; 3209215976Sjmallett info.user_info = (long) 3210215976Sjmallett "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n"; 3211215976Sjmallett fail |= cvmx_error_add(&info); 3212215976Sjmallett 3213215976Sjmallett /* CVMX_STXX_INT_REG(0) */ 3214215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3215215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(0); 3216215976Sjmallett info.status_mask = 1ull<<0 /* calpar0 */; 3217215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(0); 3218215976Sjmallett info.enable_mask = 1ull<<0 /* calpar0 */; 3219215976Sjmallett info.flags = 0; 3220215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3221215976Sjmallett info.group_index = 0; 3222215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3223215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3224215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3225215976Sjmallett info.func = __cvmx_error_display; 3226215976Sjmallett info.user_info = (long) 3227215976Sjmallett "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n"; 3228215976Sjmallett fail |= cvmx_error_add(&info); 3229215976Sjmallett 3230215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3231215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(0); 3232215976Sjmallett info.status_mask = 1ull<<1 /* calpar1 */; 3233215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(0); 3234215976Sjmallett info.enable_mask = 1ull<<1 /* calpar1 */; 3235215976Sjmallett info.flags = 0; 3236215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3237215976Sjmallett info.group_index = 0; 3238215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3239215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3240215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3241215976Sjmallett info.func = __cvmx_error_display; 3242215976Sjmallett info.user_info = (long) 3243215976Sjmallett "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n"; 3244215976Sjmallett fail |= cvmx_error_add(&info); 3245215976Sjmallett 3246215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3247215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(0); 3248215976Sjmallett info.status_mask = 1ull<<2 /* ovrbst */; 3249215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(0); 3250215976Sjmallett info.enable_mask = 1ull<<2 /* ovrbst */; 3251215976Sjmallett info.flags = 0; 3252215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3253215976Sjmallett info.group_index = 0; 3254215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3255215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3256215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3257215976Sjmallett info.func = __cvmx_error_display; 3258215976Sjmallett info.user_info = (long) 3259215976Sjmallett "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n"; 3260215976Sjmallett fail |= cvmx_error_add(&info); 3261215976Sjmallett 3262215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3263215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(0); 3264215976Sjmallett info.status_mask = 1ull<<3 /* datovr */; 3265215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(0); 3266215976Sjmallett info.enable_mask = 1ull<<3 /* datovr */; 3267215976Sjmallett info.flags = 0; 3268215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3269215976Sjmallett info.group_index = 0; 3270215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3271215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3272215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3273215976Sjmallett info.func = __cvmx_error_display; 3274215976Sjmallett info.user_info = (long) 3275215976Sjmallett "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n"; 3276215976Sjmallett fail |= cvmx_error_add(&info); 3277215976Sjmallett 3278215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3279215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(0); 3280215976Sjmallett info.status_mask = 1ull<<4 /* diperr */; 3281215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(0); 3282215976Sjmallett info.enable_mask = 1ull<<4 /* diperr */; 3283215976Sjmallett info.flags = 0; 3284215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3285215976Sjmallett info.group_index = 0; 3286215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3287215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3288215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3289215976Sjmallett info.func = __cvmx_error_display; 3290215976Sjmallett info.user_info = (long) 3291215976Sjmallett "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n"; 3292215976Sjmallett fail |= cvmx_error_add(&info); 3293215976Sjmallett 3294215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3295215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(0); 3296215976Sjmallett info.status_mask = 1ull<<5 /* nosync */; 3297215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(0); 3298215976Sjmallett info.enable_mask = 1ull<<5 /* nosync */; 3299215976Sjmallett info.flags = 0; 3300215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3301215976Sjmallett info.group_index = 0; 3302215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3303215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3304215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3305215976Sjmallett info.func = __cvmx_error_display; 3306215976Sjmallett info.user_info = (long) 3307215976Sjmallett "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n"; 3308215976Sjmallett fail |= cvmx_error_add(&info); 3309215976Sjmallett 3310215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3311215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(0); 3312215976Sjmallett info.status_mask = 1ull<<6 /* unxfrm */; 3313215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(0); 3314215976Sjmallett info.enable_mask = 1ull<<6 /* unxfrm */; 3315215976Sjmallett info.flags = 0; 3316215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3317215976Sjmallett info.group_index = 0; 3318215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3319215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3320215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3321215976Sjmallett info.func = __cvmx_error_display; 3322215976Sjmallett info.user_info = (long) 3323215976Sjmallett "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n"; 3324215976Sjmallett fail |= cvmx_error_add(&info); 3325215976Sjmallett 3326215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3327215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(0); 3328215976Sjmallett info.status_mask = 1ull<<7 /* frmerr */; 3329215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(0); 3330215976Sjmallett info.enable_mask = 1ull<<7 /* frmerr */; 3331215976Sjmallett info.flags = 0; 3332215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3333215976Sjmallett info.group_index = 0; 3334215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3335215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3336215976Sjmallett info.parent.status_mask = 1ull<<18 /* spx0 */; 3337215976Sjmallett info.func = __cvmx_error_display; 3338215976Sjmallett info.user_info = (long) 3339215976Sjmallett "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n"; 3340215976Sjmallett fail |= cvmx_error_add(&info); 3341215976Sjmallett 3342215976Sjmallett /* CVMX_POW_ECC_ERR */ 3343215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3344215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 3345215976Sjmallett info.status_mask = 1ull<<0 /* sbe */; 3346215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 3347215976Sjmallett info.enable_mask = 1ull<<2 /* sbe_ie */; 3348215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 3349215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3350215976Sjmallett info.group_index = 0; 3351215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3352215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3353215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 3354215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_sbe; 3355215976Sjmallett info.user_info = (long) 3356215976Sjmallett "ERROR POW_ECC_ERR[SBE]: Single bit error\n"; 3357215976Sjmallett fail |= cvmx_error_add(&info); 3358215976Sjmallett 3359215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3360215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 3361215976Sjmallett info.status_mask = 1ull<<1 /* dbe */; 3362215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 3363215976Sjmallett info.enable_mask = 1ull<<3 /* dbe_ie */; 3364215976Sjmallett info.flags = 0; 3365215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3366215976Sjmallett info.group_index = 0; 3367215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3368215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3369215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 3370215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_dbe; 3371215976Sjmallett info.user_info = (long) 3372215976Sjmallett "ERROR POW_ECC_ERR[DBE]: Double bit error\n"; 3373215976Sjmallett fail |= cvmx_error_add(&info); 3374215976Sjmallett 3375215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3376215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 3377215976Sjmallett info.status_mask = 1ull<<12 /* rpe */; 3378215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 3379215976Sjmallett info.enable_mask = 1ull<<13 /* rpe_ie */; 3380215976Sjmallett info.flags = 0; 3381215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3382215976Sjmallett info.group_index = 0; 3383215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3384215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3385215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 3386215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_rpe; 3387215976Sjmallett info.user_info = (long) 3388215976Sjmallett "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n"; 3389215976Sjmallett fail |= cvmx_error_add(&info); 3390215976Sjmallett 3391215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3392215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 3393215976Sjmallett info.status_mask = 0x1fffull<<16 /* iop */; 3394215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 3395215976Sjmallett info.enable_mask = 0x1fffull<<32 /* iop_ie */; 3396215976Sjmallett info.flags = 0; 3397215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3398215976Sjmallett info.group_index = 0; 3399215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3400215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3401215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 3402215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_iop; 3403215976Sjmallett info.user_info = (long) 3404215976Sjmallett "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n"; 3405215976Sjmallett fail |= cvmx_error_add(&info); 3406215976Sjmallett 3407215976Sjmallett /* CVMX_SPXX_INT_REG(1) */ 3408215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3409215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3410215976Sjmallett info.status_mask = 1ull<<0 /* prtnxa */; 3411215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3412215976Sjmallett info.enable_mask = 1ull<<0 /* prtnxa */; 3413215976Sjmallett info.flags = 0; 3414215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3415215976Sjmallett info.group_index = 16; 3416215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3417215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3418215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3419215976Sjmallett info.func = __cvmx_error_display; 3420215976Sjmallett info.user_info = (long) 3421215976Sjmallett "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n"; 3422215976Sjmallett fail |= cvmx_error_add(&info); 3423215976Sjmallett 3424215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3425215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3426215976Sjmallett info.status_mask = 1ull<<1 /* abnorm */; 3427215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3428215976Sjmallett info.enable_mask = 1ull<<1 /* abnorm */; 3429215976Sjmallett info.flags = 0; 3430215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3431215976Sjmallett info.group_index = 16; 3432215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3433215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3434215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3435215976Sjmallett info.func = __cvmx_error_display; 3436215976Sjmallett info.user_info = (long) 3437215976Sjmallett "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n"; 3438215976Sjmallett fail |= cvmx_error_add(&info); 3439215976Sjmallett 3440215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3441215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3442215976Sjmallett info.status_mask = 1ull<<4 /* spiovr */; 3443215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3444215976Sjmallett info.enable_mask = 1ull<<4 /* spiovr */; 3445215976Sjmallett info.flags = 0; 3446215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3447215976Sjmallett info.group_index = 16; 3448215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3449215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3450215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3451215976Sjmallett info.func = __cvmx_error_display; 3452215976Sjmallett info.user_info = (long) 3453215976Sjmallett "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n"; 3454215976Sjmallett fail |= cvmx_error_add(&info); 3455215976Sjmallett 3456215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3457215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3458215976Sjmallett info.status_mask = 1ull<<5 /* clserr */; 3459215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3460215976Sjmallett info.enable_mask = 1ull<<5 /* clserr */; 3461215976Sjmallett info.flags = 0; 3462215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3463215976Sjmallett info.group_index = 16; 3464215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3465215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3466215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3467215976Sjmallett info.func = __cvmx_error_display; 3468215976Sjmallett info.user_info = (long) 3469215976Sjmallett "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n"; 3470215976Sjmallett fail |= cvmx_error_add(&info); 3471215976Sjmallett 3472215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3473215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3474215976Sjmallett info.status_mask = 1ull<<6 /* drwnng */; 3475215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3476215976Sjmallett info.enable_mask = 1ull<<6 /* drwnng */; 3477215976Sjmallett info.flags = 0; 3478215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3479215976Sjmallett info.group_index = 16; 3480215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3481215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3482215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3483215976Sjmallett info.func = __cvmx_error_display; 3484215976Sjmallett info.user_info = (long) 3485215976Sjmallett "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n"; 3486215976Sjmallett fail |= cvmx_error_add(&info); 3487215976Sjmallett 3488215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3489215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3490215976Sjmallett info.status_mask = 1ull<<7 /* rsverr */; 3491215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3492215976Sjmallett info.enable_mask = 1ull<<7 /* rsverr */; 3493215976Sjmallett info.flags = 0; 3494215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3495215976Sjmallett info.group_index = 16; 3496215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3497215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3498215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3499215976Sjmallett info.func = __cvmx_error_display; 3500215976Sjmallett info.user_info = (long) 3501215976Sjmallett "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n"; 3502215976Sjmallett fail |= cvmx_error_add(&info); 3503215976Sjmallett 3504215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3505215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3506215976Sjmallett info.status_mask = 1ull<<8 /* tpaovr */; 3507215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3508215976Sjmallett info.enable_mask = 1ull<<8 /* tpaovr */; 3509215976Sjmallett info.flags = 0; 3510215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3511215976Sjmallett info.group_index = 16; 3512215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3513215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3514215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3515215976Sjmallett info.func = __cvmx_error_display; 3516215976Sjmallett info.user_info = (long) 3517215976Sjmallett "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n"; 3518215976Sjmallett fail |= cvmx_error_add(&info); 3519215976Sjmallett 3520215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3521215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3522215976Sjmallett info.status_mask = 1ull<<9 /* diperr */; 3523215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3524215976Sjmallett info.enable_mask = 1ull<<9 /* diperr */; 3525215976Sjmallett info.flags = 0; 3526215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3527215976Sjmallett info.group_index = 16; 3528215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3529215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3530215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3531215976Sjmallett info.func = __cvmx_error_display; 3532215976Sjmallett info.user_info = (long) 3533215976Sjmallett "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n"; 3534215976Sjmallett fail |= cvmx_error_add(&info); 3535215976Sjmallett 3536215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3537215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3538215976Sjmallett info.status_mask = 1ull<<10 /* syncerr */; 3539215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3540215976Sjmallett info.enable_mask = 1ull<<10 /* syncerr */; 3541215976Sjmallett info.flags = 0; 3542215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3543215976Sjmallett info.group_index = 16; 3544215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3545215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3546215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3547215976Sjmallett info.func = __cvmx_error_display; 3548215976Sjmallett info.user_info = (long) 3549215976Sjmallett "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n" 3550215976Sjmallett " SPX_ERR_CTL[ERRCNT]\n"; 3551215976Sjmallett fail |= cvmx_error_add(&info); 3552215976Sjmallett 3553215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3554215976Sjmallett info.status_addr = CVMX_SPXX_INT_REG(1); 3555215976Sjmallett info.status_mask = 1ull<<11 /* calerr */; 3556215976Sjmallett info.enable_addr = CVMX_SPXX_INT_MSK(1); 3557215976Sjmallett info.enable_mask = 1ull<<11 /* calerr */; 3558215976Sjmallett info.flags = 0; 3559215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3560215976Sjmallett info.group_index = 16; 3561215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3562215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3563215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3564215976Sjmallett info.func = __cvmx_error_display; 3565215976Sjmallett info.user_info = (long) 3566215976Sjmallett "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n"; 3567215976Sjmallett fail |= cvmx_error_add(&info); 3568215976Sjmallett 3569215976Sjmallett /* CVMX_STXX_INT_REG(1) */ 3570215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3571215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(1); 3572215976Sjmallett info.status_mask = 1ull<<0 /* calpar0 */; 3573215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(1); 3574215976Sjmallett info.enable_mask = 1ull<<0 /* calpar0 */; 3575215976Sjmallett info.flags = 0; 3576215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3577215976Sjmallett info.group_index = 16; 3578215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3579215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3580215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3581215976Sjmallett info.func = __cvmx_error_display; 3582215976Sjmallett info.user_info = (long) 3583215976Sjmallett "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n"; 3584215976Sjmallett fail |= cvmx_error_add(&info); 3585215976Sjmallett 3586215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3587215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(1); 3588215976Sjmallett info.status_mask = 1ull<<1 /* calpar1 */; 3589215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(1); 3590215976Sjmallett info.enable_mask = 1ull<<1 /* calpar1 */; 3591215976Sjmallett info.flags = 0; 3592215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3593215976Sjmallett info.group_index = 16; 3594215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3595215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3596215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3597215976Sjmallett info.func = __cvmx_error_display; 3598215976Sjmallett info.user_info = (long) 3599215976Sjmallett "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n"; 3600215976Sjmallett fail |= cvmx_error_add(&info); 3601215976Sjmallett 3602215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3603215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(1); 3604215976Sjmallett info.status_mask = 1ull<<2 /* ovrbst */; 3605215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(1); 3606215976Sjmallett info.enable_mask = 1ull<<2 /* ovrbst */; 3607215976Sjmallett info.flags = 0; 3608215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3609215976Sjmallett info.group_index = 16; 3610215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3611215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3612215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3613215976Sjmallett info.func = __cvmx_error_display; 3614215976Sjmallett info.user_info = (long) 3615215976Sjmallett "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n"; 3616215976Sjmallett fail |= cvmx_error_add(&info); 3617215976Sjmallett 3618215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3619215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(1); 3620215976Sjmallett info.status_mask = 1ull<<3 /* datovr */; 3621215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(1); 3622215976Sjmallett info.enable_mask = 1ull<<3 /* datovr */; 3623215976Sjmallett info.flags = 0; 3624215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3625215976Sjmallett info.group_index = 16; 3626215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3627215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3628215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3629215976Sjmallett info.func = __cvmx_error_display; 3630215976Sjmallett info.user_info = (long) 3631215976Sjmallett "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n"; 3632215976Sjmallett fail |= cvmx_error_add(&info); 3633215976Sjmallett 3634215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3635215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(1); 3636215976Sjmallett info.status_mask = 1ull<<4 /* diperr */; 3637215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(1); 3638215976Sjmallett info.enable_mask = 1ull<<4 /* diperr */; 3639215976Sjmallett info.flags = 0; 3640215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3641215976Sjmallett info.group_index = 16; 3642215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3643215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3644215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3645215976Sjmallett info.func = __cvmx_error_display; 3646215976Sjmallett info.user_info = (long) 3647215976Sjmallett "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n"; 3648215976Sjmallett fail |= cvmx_error_add(&info); 3649215976Sjmallett 3650215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3651215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(1); 3652215976Sjmallett info.status_mask = 1ull<<5 /* nosync */; 3653215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(1); 3654215976Sjmallett info.enable_mask = 1ull<<5 /* nosync */; 3655215976Sjmallett info.flags = 0; 3656215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3657215976Sjmallett info.group_index = 16; 3658215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3659215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3660215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3661215976Sjmallett info.func = __cvmx_error_display; 3662215976Sjmallett info.user_info = (long) 3663215976Sjmallett "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n"; 3664215976Sjmallett fail |= cvmx_error_add(&info); 3665215976Sjmallett 3666215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3667215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(1); 3668215976Sjmallett info.status_mask = 1ull<<6 /* unxfrm */; 3669215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(1); 3670215976Sjmallett info.enable_mask = 1ull<<6 /* unxfrm */; 3671215976Sjmallett info.flags = 0; 3672215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3673215976Sjmallett info.group_index = 16; 3674215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3675215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3676215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3677215976Sjmallett info.func = __cvmx_error_display; 3678215976Sjmallett info.user_info = (long) 3679215976Sjmallett "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n"; 3680215976Sjmallett fail |= cvmx_error_add(&info); 3681215976Sjmallett 3682215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3683215976Sjmallett info.status_addr = CVMX_STXX_INT_REG(1); 3684215976Sjmallett info.status_mask = 1ull<<7 /* frmerr */; 3685215976Sjmallett info.enable_addr = CVMX_STXX_INT_MSK(1); 3686215976Sjmallett info.enable_mask = 1ull<<7 /* frmerr */; 3687215976Sjmallett info.flags = 0; 3688215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3689215976Sjmallett info.group_index = 16; 3690215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3691215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3692215976Sjmallett info.parent.status_mask = 1ull<<19 /* spx1 */; 3693215976Sjmallett info.func = __cvmx_error_display; 3694215976Sjmallett info.user_info = (long) 3695215976Sjmallett "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n"; 3696215976Sjmallett fail |= cvmx_error_add(&info); 3697215976Sjmallett 3698215976Sjmallett /* CVMX_ASXX_INT_REG(0) */ 3699215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3700215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(0); 3701215976Sjmallett info.status_mask = 0xfull<<8 /* txpsh */; 3702215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(0); 3703215976Sjmallett info.enable_mask = 0xfull<<8 /* txpsh */; 3704215976Sjmallett info.flags = 0; 3705215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3706215976Sjmallett info.group_index = 0; 3707215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3708215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3709215976Sjmallett info.parent.status_mask = 1ull<<22 /* asx0 */; 3710215976Sjmallett info.func = __cvmx_error_display; 3711215976Sjmallett info.user_info = (long) 3712215976Sjmallett "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n"; 3713215976Sjmallett fail |= cvmx_error_add(&info); 3714215976Sjmallett 3715215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3716215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(0); 3717215976Sjmallett info.status_mask = 0xfull<<4 /* txpop */; 3718215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(0); 3719215976Sjmallett info.enable_mask = 0xfull<<4 /* txpop */; 3720215976Sjmallett info.flags = 0; 3721215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3722215976Sjmallett info.group_index = 0; 3723215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3724215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3725215976Sjmallett info.parent.status_mask = 1ull<<22 /* asx0 */; 3726215976Sjmallett info.func = __cvmx_error_display; 3727215976Sjmallett info.user_info = (long) 3728215976Sjmallett "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n"; 3729215976Sjmallett fail |= cvmx_error_add(&info); 3730215976Sjmallett 3731215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3732215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(0); 3733215976Sjmallett info.status_mask = 0xfull<<0 /* ovrflw */; 3734215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(0); 3735215976Sjmallett info.enable_mask = 0xfull<<0 /* ovrflw */; 3736215976Sjmallett info.flags = 0; 3737215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3738215976Sjmallett info.group_index = 0; 3739215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3740215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3741215976Sjmallett info.parent.status_mask = 1ull<<22 /* asx0 */; 3742215976Sjmallett info.func = __cvmx_error_display; 3743215976Sjmallett info.user_info = (long) 3744215976Sjmallett "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n"; 3745215976Sjmallett fail |= cvmx_error_add(&info); 3746215976Sjmallett 3747215976Sjmallett /* CVMX_ASXX_INT_REG(1) */ 3748215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3749215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(1); 3750215976Sjmallett info.status_mask = 0xfull<<8 /* txpsh */; 3751215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(1); 3752215976Sjmallett info.enable_mask = 0xfull<<8 /* txpsh */; 3753215976Sjmallett info.flags = 0; 3754215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3755215976Sjmallett info.group_index = 16; 3756215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3757215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3758215976Sjmallett info.parent.status_mask = 1ull<<23 /* asx1 */; 3759215976Sjmallett info.func = __cvmx_error_display; 3760215976Sjmallett info.user_info = (long) 3761215976Sjmallett "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n"; 3762215976Sjmallett fail |= cvmx_error_add(&info); 3763215976Sjmallett 3764215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3765215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(1); 3766215976Sjmallett info.status_mask = 0xfull<<4 /* txpop */; 3767215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(1); 3768215976Sjmallett info.enable_mask = 0xfull<<4 /* txpop */; 3769215976Sjmallett info.flags = 0; 3770215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3771215976Sjmallett info.group_index = 16; 3772215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3773215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3774215976Sjmallett info.parent.status_mask = 1ull<<23 /* asx1 */; 3775215976Sjmallett info.func = __cvmx_error_display; 3776215976Sjmallett info.user_info = (long) 3777215976Sjmallett "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n"; 3778215976Sjmallett fail |= cvmx_error_add(&info); 3779215976Sjmallett 3780215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3781215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(1); 3782215976Sjmallett info.status_mask = 0xfull<<0 /* ovrflw */; 3783215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(1); 3784215976Sjmallett info.enable_mask = 0xfull<<0 /* ovrflw */; 3785215976Sjmallett info.flags = 0; 3786215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 3787215976Sjmallett info.group_index = 16; 3788215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3789215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3790215976Sjmallett info.parent.status_mask = 1ull<<23 /* asx1 */; 3791215976Sjmallett info.func = __cvmx_error_display; 3792215976Sjmallett info.user_info = (long) 3793215976Sjmallett "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n"; 3794215976Sjmallett fail |= cvmx_error_add(&info); 3795215976Sjmallett 3796215976Sjmallett /* CVMX_PKO_REG_ERROR */ 3797215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3798215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 3799215976Sjmallett info.status_mask = 1ull<<0 /* parity */; 3800215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 3801215976Sjmallett info.enable_mask = 1ull<<0 /* parity */; 3802215976Sjmallett info.flags = 0; 3803215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3804215976Sjmallett info.group_index = 0; 3805215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3806215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3807215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 3808215976Sjmallett info.func = __cvmx_error_display; 3809215976Sjmallett info.user_info = (long) 3810215976Sjmallett "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n"; 3811215976Sjmallett fail |= cvmx_error_add(&info); 3812215976Sjmallett 3813215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3814215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 3815215976Sjmallett info.status_mask = 1ull<<1 /* doorbell */; 3816215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 3817215976Sjmallett info.enable_mask = 1ull<<1 /* doorbell */; 3818215976Sjmallett info.flags = 0; 3819215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3820215976Sjmallett info.group_index = 0; 3821215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3822215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3823215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 3824215976Sjmallett info.func = __cvmx_error_display; 3825215976Sjmallett info.user_info = (long) 3826215976Sjmallett "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 3827215976Sjmallett fail |= cvmx_error_add(&info); 3828215976Sjmallett 3829215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3830215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 3831215976Sjmallett info.status_mask = 1ull<<2 /* currzero */; 3832215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 3833215976Sjmallett info.enable_mask = 1ull<<2 /* currzero */; 3834215976Sjmallett info.flags = 0; 3835215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3836215976Sjmallett info.group_index = 0; 3837215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3838215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3839215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 3840215976Sjmallett info.func = __cvmx_error_display; 3841215976Sjmallett info.user_info = (long) 3842215976Sjmallett "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n"; 3843215976Sjmallett fail |= cvmx_error_add(&info); 3844215976Sjmallett 3845215976Sjmallett /* CVMX_TIM_REG_ERROR */ 3846215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3847215976Sjmallett info.status_addr = CVMX_TIM_REG_ERROR; 3848215976Sjmallett info.status_mask = 0xffffull<<0 /* mask */; 3849215976Sjmallett info.enable_addr = CVMX_TIM_REG_INT_MASK; 3850215976Sjmallett info.enable_mask = 0xffffull<<0 /* mask */; 3851215976Sjmallett info.flags = 0; 3852215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3853215976Sjmallett info.group_index = 0; 3854215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3855215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3856215976Sjmallett info.parent.status_mask = 1ull<<11 /* tim */; 3857215976Sjmallett info.func = __cvmx_error_display; 3858215976Sjmallett info.user_info = (long) 3859215976Sjmallett "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n"; 3860215976Sjmallett fail |= cvmx_error_add(&info); 3861215976Sjmallett 3862215976Sjmallett /* CVMX_KEY_INT_SUM */ 3863215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3864215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 3865215976Sjmallett info.status_mask = 1ull<<0 /* ked0_sbe */; 3866215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 3867215976Sjmallett info.enable_mask = 1ull<<0 /* ked0_sbe */; 3868215976Sjmallett info.flags = 0; 3869215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3870215976Sjmallett info.group_index = 0; 3871215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3872215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3873215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 3874215976Sjmallett info.func = __cvmx_error_display; 3875215976Sjmallett info.user_info = (long) 3876215976Sjmallett "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n" 3877215976Sjmallett; 3878215976Sjmallett fail |= cvmx_error_add(&info); 3879215976Sjmallett 3880215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3881215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 3882215976Sjmallett info.status_mask = 1ull<<1 /* ked0_dbe */; 3883215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 3884215976Sjmallett info.enable_mask = 1ull<<1 /* ked0_dbe */; 3885215976Sjmallett info.flags = 0; 3886215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3887215976Sjmallett info.group_index = 0; 3888215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3889215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3890215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 3891215976Sjmallett info.func = __cvmx_error_display; 3892215976Sjmallett info.user_info = (long) 3893215976Sjmallett "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n" 3894215976Sjmallett; 3895215976Sjmallett fail |= cvmx_error_add(&info); 3896215976Sjmallett 3897215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3898215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 3899215976Sjmallett info.status_mask = 1ull<<2 /* ked1_sbe */; 3900215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 3901215976Sjmallett info.enable_mask = 1ull<<2 /* ked1_sbe */; 3902215976Sjmallett info.flags = 0; 3903215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3904215976Sjmallett info.group_index = 0; 3905215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3906215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3907215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 3908215976Sjmallett info.func = __cvmx_error_display; 3909215976Sjmallett info.user_info = (long) 3910215976Sjmallett "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n" 3911215976Sjmallett; 3912215976Sjmallett fail |= cvmx_error_add(&info); 3913215976Sjmallett 3914215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3915215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 3916215976Sjmallett info.status_mask = 1ull<<3 /* ked1_dbe */; 3917215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 3918215976Sjmallett info.enable_mask = 1ull<<3 /* ked1_dbe */; 3919215976Sjmallett info.flags = 0; 3920215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3921215976Sjmallett info.group_index = 0; 3922215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3923215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3924215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 3925215976Sjmallett info.func = __cvmx_error_display; 3926215976Sjmallett info.user_info = (long) 3927215976Sjmallett "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n" 3928215976Sjmallett; 3929215976Sjmallett fail |= cvmx_error_add(&info); 3930215976Sjmallett 3931215976Sjmallett /* CVMX_MIO_BOOT_ERR */ 3932215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3933215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 3934215976Sjmallett info.status_mask = 1ull<<0 /* adr_err */; 3935215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 3936215976Sjmallett info.enable_mask = 1ull<<0 /* adr_int */; 3937215976Sjmallett info.flags = 0; 3938215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3939215976Sjmallett info.group_index = 0; 3940215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3941215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3942215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 3943215976Sjmallett info.func = __cvmx_error_display; 3944215976Sjmallett info.user_info = (long) 3945215976Sjmallett "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n"; 3946215976Sjmallett fail |= cvmx_error_add(&info); 3947215976Sjmallett 3948215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3949215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 3950215976Sjmallett info.status_mask = 1ull<<1 /* wait_err */; 3951215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 3952215976Sjmallett info.enable_mask = 1ull<<1 /* wait_int */; 3953215976Sjmallett info.flags = 0; 3954215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3955215976Sjmallett info.group_index = 0; 3956215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3957215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3958215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 3959215976Sjmallett info.func = __cvmx_error_display; 3960215976Sjmallett info.user_info = (long) 3961215976Sjmallett "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n"; 3962215976Sjmallett fail |= cvmx_error_add(&info); 3963215976Sjmallett 3964215976Sjmallett /* CVMX_PIP_INT_REG */ 3965215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3966215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 3967215976Sjmallett info.status_mask = 1ull<<3 /* prtnxa */; 3968215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 3969215976Sjmallett info.enable_mask = 1ull<<3 /* prtnxa */; 3970215976Sjmallett info.flags = 0; 3971215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3972215976Sjmallett info.group_index = 0; 3973215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3974215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3975215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 3976215976Sjmallett info.func = __cvmx_error_display; 3977215976Sjmallett info.user_info = (long) 3978215976Sjmallett "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n"; 3979215976Sjmallett fail |= cvmx_error_add(&info); 3980215976Sjmallett 3981215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3982215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 3983215976Sjmallett info.status_mask = 1ull<<4 /* badtag */; 3984215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 3985215976Sjmallett info.enable_mask = 1ull<<4 /* badtag */; 3986215976Sjmallett info.flags = 0; 3987215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3988215976Sjmallett info.group_index = 0; 3989215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3990215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3991215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 3992215976Sjmallett info.func = __cvmx_error_display; 3993215976Sjmallett info.user_info = (long) 3994215976Sjmallett "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n"; 3995215976Sjmallett fail |= cvmx_error_add(&info); 3996215976Sjmallett 3997215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3998215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 3999215976Sjmallett info.status_mask = 1ull<<5 /* skprunt */; 4000215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 4001215976Sjmallett info.enable_mask = 1ull<<5 /* skprunt */; 4002215976Sjmallett info.flags = 0; 4003215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4004215976Sjmallett info.group_index = 0; 4005215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4006215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4007215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 4008215976Sjmallett info.func = __cvmx_error_display; 4009215976Sjmallett info.user_info = (long) 4010215976Sjmallett "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n" 4011215976Sjmallett " This interrupt can occur with received PARTIAL\n" 4012215976Sjmallett " packets that are truncated to SKIP bytes or\n" 4013215976Sjmallett " smaller.\n"; 4014215976Sjmallett fail |= cvmx_error_add(&info); 4015215976Sjmallett 4016215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4017215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 4018215976Sjmallett info.status_mask = 1ull<<6 /* todoovr */; 4019215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 4020215976Sjmallett info.enable_mask = 1ull<<6 /* todoovr */; 4021215976Sjmallett info.flags = 0; 4022215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4023215976Sjmallett info.group_index = 0; 4024215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4025215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4026215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 4027215976Sjmallett info.func = __cvmx_error_display; 4028215976Sjmallett info.user_info = (long) 4029215976Sjmallett "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n"; 4030215976Sjmallett fail |= cvmx_error_add(&info); 4031215976Sjmallett 4032215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4033215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 4034215976Sjmallett info.status_mask = 1ull<<7 /* feperr */; 4035215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 4036215976Sjmallett info.enable_mask = 1ull<<7 /* feperr */; 4037215976Sjmallett info.flags = 0; 4038215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4039215976Sjmallett info.group_index = 0; 4040215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4041215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4042215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 4043215976Sjmallett info.func = __cvmx_error_display; 4044215976Sjmallett info.user_info = (long) 4045215976Sjmallett "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n"; 4046215976Sjmallett fail |= cvmx_error_add(&info); 4047215976Sjmallett 4048215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4049215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 4050215976Sjmallett info.status_mask = 1ull<<8 /* beperr */; 4051215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 4052215976Sjmallett info.enable_mask = 1ull<<8 /* beperr */; 4053215976Sjmallett info.flags = 0; 4054215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4055215976Sjmallett info.group_index = 0; 4056215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4057215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4058215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 4059215976Sjmallett info.func = __cvmx_error_display; 4060215976Sjmallett info.user_info = (long) 4061215976Sjmallett "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n"; 4062215976Sjmallett fail |= cvmx_error_add(&info); 4063215976Sjmallett 4064215976Sjmallett /* CVMX_FPA_INT_SUM */ 4065215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4066215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4067215976Sjmallett info.status_mask = 1ull<<0 /* fed0_sbe */; 4068215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4069215976Sjmallett info.enable_mask = 1ull<<0 /* fed0_sbe */; 4070215976Sjmallett info.flags = 0; 4071215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4072215976Sjmallett info.group_index = 0; 4073215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4074215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4075215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4076215976Sjmallett info.func = __cvmx_error_display; 4077215976Sjmallett info.user_info = (long) 4078215976Sjmallett "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n"; 4079215976Sjmallett fail |= cvmx_error_add(&info); 4080215976Sjmallett 4081215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4082215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4083215976Sjmallett info.status_mask = 1ull<<1 /* fed0_dbe */; 4084215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4085215976Sjmallett info.enable_mask = 1ull<<1 /* fed0_dbe */; 4086215976Sjmallett info.flags = 0; 4087215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4088215976Sjmallett info.group_index = 0; 4089215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4090215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4091215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4092215976Sjmallett info.func = __cvmx_error_display; 4093215976Sjmallett info.user_info = (long) 4094215976Sjmallett "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n"; 4095215976Sjmallett fail |= cvmx_error_add(&info); 4096215976Sjmallett 4097215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4098215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4099215976Sjmallett info.status_mask = 1ull<<2 /* fed1_sbe */; 4100215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4101215976Sjmallett info.enable_mask = 1ull<<2 /* fed1_sbe */; 4102215976Sjmallett info.flags = 0; 4103215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4104215976Sjmallett info.group_index = 0; 4105215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4106215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4107215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4108215976Sjmallett info.func = __cvmx_error_display; 4109215976Sjmallett info.user_info = (long) 4110215976Sjmallett "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n"; 4111215976Sjmallett fail |= cvmx_error_add(&info); 4112215976Sjmallett 4113215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4114215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4115215976Sjmallett info.status_mask = 1ull<<3 /* fed1_dbe */; 4116215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4117215976Sjmallett info.enable_mask = 1ull<<3 /* fed1_dbe */; 4118215976Sjmallett info.flags = 0; 4119215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4120215976Sjmallett info.group_index = 0; 4121215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4122215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4123215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4124215976Sjmallett info.func = __cvmx_error_display; 4125215976Sjmallett info.user_info = (long) 4126215976Sjmallett "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n"; 4127215976Sjmallett fail |= cvmx_error_add(&info); 4128215976Sjmallett 4129215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4130215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4131215976Sjmallett info.status_mask = 1ull<<4 /* q0_und */; 4132215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4133215976Sjmallett info.enable_mask = 1ull<<4 /* q0_und */; 4134215976Sjmallett info.flags = 0; 4135215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4136215976Sjmallett info.group_index = 0; 4137215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4138215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4139215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4140215976Sjmallett info.func = __cvmx_error_display; 4141215976Sjmallett info.user_info = (long) 4142215976Sjmallett "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n" 4143215976Sjmallett " negative.\n"; 4144215976Sjmallett fail |= cvmx_error_add(&info); 4145215976Sjmallett 4146215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4147215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4148215976Sjmallett info.status_mask = 1ull<<5 /* q0_coff */; 4149215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4150215976Sjmallett info.enable_mask = 1ull<<5 /* q0_coff */; 4151215976Sjmallett info.flags = 0; 4152215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4153215976Sjmallett info.group_index = 0; 4154215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4155215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4156215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4157215976Sjmallett info.func = __cvmx_error_display; 4158215976Sjmallett info.user_info = (long) 4159215976Sjmallett "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n" 4160215976Sjmallett " the count available is greater than pointers\n" 4161215976Sjmallett " present in the FPA.\n"; 4162215976Sjmallett fail |= cvmx_error_add(&info); 4163215976Sjmallett 4164215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4165215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4166215976Sjmallett info.status_mask = 1ull<<6 /* q0_perr */; 4167215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4168215976Sjmallett info.enable_mask = 1ull<<6 /* q0_perr */; 4169215976Sjmallett info.flags = 0; 4170215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4171215976Sjmallett info.group_index = 0; 4172215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4173215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4174215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4175215976Sjmallett info.func = __cvmx_error_display; 4176215976Sjmallett info.user_info = (long) 4177215976Sjmallett "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n" 4178215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 4179215976Sjmallett fail |= cvmx_error_add(&info); 4180215976Sjmallett 4181215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4182215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4183215976Sjmallett info.status_mask = 1ull<<7 /* q1_und */; 4184215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4185215976Sjmallett info.enable_mask = 1ull<<7 /* q1_und */; 4186215976Sjmallett info.flags = 0; 4187215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4188215976Sjmallett info.group_index = 0; 4189215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4190215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4191215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4192215976Sjmallett info.func = __cvmx_error_display; 4193215976Sjmallett info.user_info = (long) 4194215976Sjmallett "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n" 4195215976Sjmallett " negative.\n"; 4196215976Sjmallett fail |= cvmx_error_add(&info); 4197215976Sjmallett 4198215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4199215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4200215976Sjmallett info.status_mask = 1ull<<8 /* q1_coff */; 4201215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4202215976Sjmallett info.enable_mask = 1ull<<8 /* q1_coff */; 4203215976Sjmallett info.flags = 0; 4204215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4205215976Sjmallett info.group_index = 0; 4206215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4207215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4208215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4209215976Sjmallett info.func = __cvmx_error_display; 4210215976Sjmallett info.user_info = (long) 4211215976Sjmallett "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n" 4212215976Sjmallett " the count available is greater than pointers\n" 4213215976Sjmallett " present in the FPA.\n"; 4214215976Sjmallett fail |= cvmx_error_add(&info); 4215215976Sjmallett 4216215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4217215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4218215976Sjmallett info.status_mask = 1ull<<9 /* q1_perr */; 4219215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4220215976Sjmallett info.enable_mask = 1ull<<9 /* q1_perr */; 4221215976Sjmallett info.flags = 0; 4222215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4223215976Sjmallett info.group_index = 0; 4224215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4225215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4226215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4227215976Sjmallett info.func = __cvmx_error_display; 4228215976Sjmallett info.user_info = (long) 4229215976Sjmallett "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n" 4230215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 4231215976Sjmallett fail |= cvmx_error_add(&info); 4232215976Sjmallett 4233215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4234215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4235215976Sjmallett info.status_mask = 1ull<<10 /* q2_und */; 4236215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4237215976Sjmallett info.enable_mask = 1ull<<10 /* q2_und */; 4238215976Sjmallett info.flags = 0; 4239215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4240215976Sjmallett info.group_index = 0; 4241215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4242215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4243215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4244215976Sjmallett info.func = __cvmx_error_display; 4245215976Sjmallett info.user_info = (long) 4246215976Sjmallett "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n" 4247215976Sjmallett " negative.\n"; 4248215976Sjmallett fail |= cvmx_error_add(&info); 4249215976Sjmallett 4250215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4251215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4252215976Sjmallett info.status_mask = 1ull<<11 /* q2_coff */; 4253215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4254215976Sjmallett info.enable_mask = 1ull<<11 /* q2_coff */; 4255215976Sjmallett info.flags = 0; 4256215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4257215976Sjmallett info.group_index = 0; 4258215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4259215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4260215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4261215976Sjmallett info.func = __cvmx_error_display; 4262215976Sjmallett info.user_info = (long) 4263215976Sjmallett "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n" 4264215976Sjmallett " the count available is greater than than pointers\n" 4265215976Sjmallett " present in the FPA.\n"; 4266215976Sjmallett fail |= cvmx_error_add(&info); 4267215976Sjmallett 4268215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4269215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4270215976Sjmallett info.status_mask = 1ull<<12 /* q2_perr */; 4271215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4272215976Sjmallett info.enable_mask = 1ull<<12 /* q2_perr */; 4273215976Sjmallett info.flags = 0; 4274215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4275215976Sjmallett info.group_index = 0; 4276215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4277215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4278215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4279215976Sjmallett info.func = __cvmx_error_display; 4280215976Sjmallett info.user_info = (long) 4281215976Sjmallett "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n" 4282215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 4283215976Sjmallett fail |= cvmx_error_add(&info); 4284215976Sjmallett 4285215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4286215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4287215976Sjmallett info.status_mask = 1ull<<13 /* q3_und */; 4288215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4289215976Sjmallett info.enable_mask = 1ull<<13 /* q3_und */; 4290215976Sjmallett info.flags = 0; 4291215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4292215976Sjmallett info.group_index = 0; 4293215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4294215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4295215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4296215976Sjmallett info.func = __cvmx_error_display; 4297215976Sjmallett info.user_info = (long) 4298215976Sjmallett "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n" 4299215976Sjmallett " negative.\n"; 4300215976Sjmallett fail |= cvmx_error_add(&info); 4301215976Sjmallett 4302215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4303215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4304215976Sjmallett info.status_mask = 1ull<<14 /* q3_coff */; 4305215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4306215976Sjmallett info.enable_mask = 1ull<<14 /* q3_coff */; 4307215976Sjmallett info.flags = 0; 4308215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4309215976Sjmallett info.group_index = 0; 4310215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4311215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4312215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4313215976Sjmallett info.func = __cvmx_error_display; 4314215976Sjmallett info.user_info = (long) 4315215976Sjmallett "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n" 4316215976Sjmallett " the count available is greater than than pointers\n" 4317215976Sjmallett " present in the FPA.\n"; 4318215976Sjmallett fail |= cvmx_error_add(&info); 4319215976Sjmallett 4320215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4321215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4322215976Sjmallett info.status_mask = 1ull<<15 /* q3_perr */; 4323215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4324215976Sjmallett info.enable_mask = 1ull<<15 /* q3_perr */; 4325215976Sjmallett info.flags = 0; 4326215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4327215976Sjmallett info.group_index = 0; 4328215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4329215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4330215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4331215976Sjmallett info.func = __cvmx_error_display; 4332215976Sjmallett info.user_info = (long) 4333215976Sjmallett "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n" 4334215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 4335215976Sjmallett fail |= cvmx_error_add(&info); 4336215976Sjmallett 4337215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4338215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4339215976Sjmallett info.status_mask = 1ull<<16 /* q4_und */; 4340215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4341215976Sjmallett info.enable_mask = 1ull<<16 /* q4_und */; 4342215976Sjmallett info.flags = 0; 4343215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4344215976Sjmallett info.group_index = 0; 4345215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4346215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4347215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4348215976Sjmallett info.func = __cvmx_error_display; 4349215976Sjmallett info.user_info = (long) 4350215976Sjmallett "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n" 4351215976Sjmallett " negative.\n"; 4352215976Sjmallett fail |= cvmx_error_add(&info); 4353215976Sjmallett 4354215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4355215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4356215976Sjmallett info.status_mask = 1ull<<17 /* q4_coff */; 4357215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4358215976Sjmallett info.enable_mask = 1ull<<17 /* q4_coff */; 4359215976Sjmallett info.flags = 0; 4360215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4361215976Sjmallett info.group_index = 0; 4362215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4363215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4364215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4365215976Sjmallett info.func = __cvmx_error_display; 4366215976Sjmallett info.user_info = (long) 4367215976Sjmallett "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n" 4368215976Sjmallett " the count available is greater than than pointers\n" 4369215976Sjmallett " present in the FPA.\n"; 4370215976Sjmallett fail |= cvmx_error_add(&info); 4371215976Sjmallett 4372215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4373215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4374215976Sjmallett info.status_mask = 1ull<<18 /* q4_perr */; 4375215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4376215976Sjmallett info.enable_mask = 1ull<<18 /* q4_perr */; 4377215976Sjmallett info.flags = 0; 4378215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4379215976Sjmallett info.group_index = 0; 4380215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4381215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4382215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4383215976Sjmallett info.func = __cvmx_error_display; 4384215976Sjmallett info.user_info = (long) 4385215976Sjmallett "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n" 4386215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 4387215976Sjmallett fail |= cvmx_error_add(&info); 4388215976Sjmallett 4389215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4390215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4391215976Sjmallett info.status_mask = 1ull<<19 /* q5_und */; 4392215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4393215976Sjmallett info.enable_mask = 1ull<<19 /* q5_und */; 4394215976Sjmallett info.flags = 0; 4395215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4396215976Sjmallett info.group_index = 0; 4397215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4398215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4399215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4400215976Sjmallett info.func = __cvmx_error_display; 4401215976Sjmallett info.user_info = (long) 4402215976Sjmallett "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n" 4403215976Sjmallett " negative.\n"; 4404215976Sjmallett fail |= cvmx_error_add(&info); 4405215976Sjmallett 4406215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4407215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4408215976Sjmallett info.status_mask = 1ull<<20 /* q5_coff */; 4409215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4410215976Sjmallett info.enable_mask = 1ull<<20 /* q5_coff */; 4411215976Sjmallett info.flags = 0; 4412215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4413215976Sjmallett info.group_index = 0; 4414215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4415215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4416215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4417215976Sjmallett info.func = __cvmx_error_display; 4418215976Sjmallett info.user_info = (long) 4419215976Sjmallett "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n" 4420215976Sjmallett " the count available is greater than than pointers\n" 4421215976Sjmallett " present in the FPA.\n"; 4422215976Sjmallett fail |= cvmx_error_add(&info); 4423215976Sjmallett 4424215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4425215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4426215976Sjmallett info.status_mask = 1ull<<21 /* q5_perr */; 4427215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4428215976Sjmallett info.enable_mask = 1ull<<21 /* q5_perr */; 4429215976Sjmallett info.flags = 0; 4430215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4431215976Sjmallett info.group_index = 0; 4432215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4433215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4434215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4435215976Sjmallett info.func = __cvmx_error_display; 4436215976Sjmallett info.user_info = (long) 4437215976Sjmallett "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n" 4438215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 4439215976Sjmallett fail |= cvmx_error_add(&info); 4440215976Sjmallett 4441215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4442215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4443215976Sjmallett info.status_mask = 1ull<<22 /* q6_und */; 4444215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4445215976Sjmallett info.enable_mask = 1ull<<22 /* q6_und */; 4446215976Sjmallett info.flags = 0; 4447215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4448215976Sjmallett info.group_index = 0; 4449215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4450215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4451215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4452215976Sjmallett info.func = __cvmx_error_display; 4453215976Sjmallett info.user_info = (long) 4454215976Sjmallett "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n" 4455215976Sjmallett " negative.\n"; 4456215976Sjmallett fail |= cvmx_error_add(&info); 4457215976Sjmallett 4458215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4459215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4460215976Sjmallett info.status_mask = 1ull<<23 /* q6_coff */; 4461215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4462215976Sjmallett info.enable_mask = 1ull<<23 /* q6_coff */; 4463215976Sjmallett info.flags = 0; 4464215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4465215976Sjmallett info.group_index = 0; 4466215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4467215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4468215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4469215976Sjmallett info.func = __cvmx_error_display; 4470215976Sjmallett info.user_info = (long) 4471215976Sjmallett "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n" 4472215976Sjmallett " the count available is greater than than pointers\n" 4473215976Sjmallett " present in the FPA.\n"; 4474215976Sjmallett fail |= cvmx_error_add(&info); 4475215976Sjmallett 4476215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4477215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4478215976Sjmallett info.status_mask = 1ull<<24 /* q6_perr */; 4479215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4480215976Sjmallett info.enable_mask = 1ull<<24 /* q6_perr */; 4481215976Sjmallett info.flags = 0; 4482215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4483215976Sjmallett info.group_index = 0; 4484215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4485215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4486215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4487215976Sjmallett info.func = __cvmx_error_display; 4488215976Sjmallett info.user_info = (long) 4489215976Sjmallett "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n" 4490215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 4491215976Sjmallett fail |= cvmx_error_add(&info); 4492215976Sjmallett 4493215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4494215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4495215976Sjmallett info.status_mask = 1ull<<25 /* q7_und */; 4496215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4497215976Sjmallett info.enable_mask = 1ull<<25 /* q7_und */; 4498215976Sjmallett info.flags = 0; 4499215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4500215976Sjmallett info.group_index = 0; 4501215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4502215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4503215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4504215976Sjmallett info.func = __cvmx_error_display; 4505215976Sjmallett info.user_info = (long) 4506215976Sjmallett "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n" 4507215976Sjmallett " negative.\n"; 4508215976Sjmallett fail |= cvmx_error_add(&info); 4509215976Sjmallett 4510215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4511215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4512215976Sjmallett info.status_mask = 1ull<<26 /* q7_coff */; 4513215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4514215976Sjmallett info.enable_mask = 1ull<<26 /* q7_coff */; 4515215976Sjmallett info.flags = 0; 4516215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4517215976Sjmallett info.group_index = 0; 4518215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4519215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4520215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4521215976Sjmallett info.func = __cvmx_error_display; 4522215976Sjmallett info.user_info = (long) 4523215976Sjmallett "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n" 4524215976Sjmallett " the count available is greater than than pointers\n" 4525215976Sjmallett " present in the FPA.\n"; 4526215976Sjmallett fail |= cvmx_error_add(&info); 4527215976Sjmallett 4528215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4529215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 4530215976Sjmallett info.status_mask = 1ull<<27 /* q7_perr */; 4531215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 4532215976Sjmallett info.enable_mask = 1ull<<27 /* q7_perr */; 4533215976Sjmallett info.flags = 0; 4534215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4535215976Sjmallett info.group_index = 0; 4536215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4537215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4538215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 4539215976Sjmallett info.func = __cvmx_error_display; 4540215976Sjmallett info.user_info = (long) 4541215976Sjmallett "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n" 4542215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 4543215976Sjmallett fail |= cvmx_error_add(&info); 4544215976Sjmallett 4545215976Sjmallett /* CVMX_LMCX_MEM_CFG0(0) */ 4546215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4547215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 4548215976Sjmallett info.status_mask = 0xfull<<21 /* sec_err */; 4549215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 4550215976Sjmallett info.enable_mask = 1ull<<19 /* intr_sec_ena */; 4551215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 4552215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 4553215976Sjmallett info.group_index = 0; 4554215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4555215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4556215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc */; 4557215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err; 4558215976Sjmallett info.user_info = (long) 4559215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n" 4560215976Sjmallett " In 128b mode, ecc is calulated on 1 cycle worth of data\n" 4561215976Sjmallett " [21] corresponds to DQ[63:0], Phase0\n" 4562215976Sjmallett " [22] corresponds to DQ[127:64], Phase0\n" 4563215976Sjmallett " [23] corresponds to DQ[63:0], Phase1\n" 4564215976Sjmallett " [24] corresponds to DQ[127:64], Phase1\n" 4565215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 4566215976Sjmallett " [21] corresponds to DQ[63:0], Phase0, cycle0\n" 4567215976Sjmallett " [22] corresponds to DQ[63:0], Phase0, cycle1\n" 4568215976Sjmallett " [23] corresponds to DQ[63:0], Phase1, cycle0\n" 4569215976Sjmallett " [24] corresponds to DQ[63:0], Phase1, cycle1\n" 4570215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4571215976Sjmallett fail |= cvmx_error_add(&info); 4572215976Sjmallett 4573215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4574215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 4575215976Sjmallett info.status_mask = 0xfull<<25 /* ded_err */; 4576215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 4577215976Sjmallett info.enable_mask = 1ull<<20 /* intr_ded_ena */; 4578215976Sjmallett info.flags = 0; 4579215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 4580215976Sjmallett info.group_index = 0; 4581215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4582215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4583215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc */; 4584215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err; 4585215976Sjmallett info.user_info = (long) 4586215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n" 4587215976Sjmallett " In 128b mode, ecc is calulated on 1 cycle worth of data\n" 4588215976Sjmallett " [25] corresponds to DQ[63:0], Phase0\n" 4589215976Sjmallett " [26] corresponds to DQ[127:64], Phase0\n" 4590215976Sjmallett " [27] corresponds to DQ[63:0], Phase1\n" 4591215976Sjmallett " [28] corresponds to DQ[127:64], Phase1\n" 4592215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 4593215976Sjmallett " [25] corresponds to DQ[63:0], Phase0, cycle0\n" 4594215976Sjmallett " [26] corresponds to DQ[63:0], Phase0, cycle1\n" 4595215976Sjmallett " [27] corresponds to DQ[63:0], Phase1, cycle0\n" 4596215976Sjmallett " [28] corresponds to DQ[63:0], Phase1, cycle1\n" 4597215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4598215976Sjmallett fail |= cvmx_error_add(&info); 4599215976Sjmallett 4600215976Sjmallett /* CVMX_DFA_ERR */ 4601215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4602215976Sjmallett info.status_addr = CVMX_DFA_ERR; 4603215976Sjmallett info.status_mask = 1ull<<1 /* cp2sbe */; 4604215976Sjmallett info.enable_addr = 0; 4605215976Sjmallett info.enable_mask = 0; 4606215976Sjmallett info.flags = 0; 4607215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4608215976Sjmallett info.group_index = 0; 4609215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4610215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4611215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 4612215976Sjmallett info.func = __cvmx_error_handle_dfa_err_cp2sbe; 4613215976Sjmallett info.user_info = (long) 4614215976Sjmallett "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n" 4615215976Sjmallett " When set, a single bit error had been detected and\n" 4616215976Sjmallett " corrected for a PP-generated QW Mode read\n" 4617215976Sjmallett " transaction.\n" 4618215976Sjmallett " If the CP2DBE=0, then the CP2SYN contains the\n" 4619215976Sjmallett " failing syndrome (used during correction).\n" 4620215976Sjmallett " Refer to CP2ECCENA.\n" 4621215976Sjmallett " If the CP2SBINA had previously been enabled(set),\n" 4622215976Sjmallett " an interrupt will be posted. Software can clear\n" 4623215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 4624215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 4625215976Sjmallett " about the memory address/control to help isolate\n" 4626215976Sjmallett " the failure.\n" 4627215976Sjmallett " NOTE: PP-generated LW Mode Read transactions\n" 4628215976Sjmallett " do not participate in ECC check/correct).\n"; 4629215976Sjmallett fail |= cvmx_error_add(&info); 4630215976Sjmallett 4631215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4632215976Sjmallett info.status_addr = CVMX_DFA_ERR; 4633215976Sjmallett info.status_mask = 1ull<<2 /* cp2dbe */; 4634215976Sjmallett info.enable_addr = 0; 4635215976Sjmallett info.enable_mask = 0; 4636215976Sjmallett info.flags = 0; 4637215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4638215976Sjmallett info.group_index = 0; 4639215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4640215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4641215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 4642215976Sjmallett info.func = __cvmx_error_handle_dfa_err_cp2dbe; 4643215976Sjmallett info.user_info = (long) 4644215976Sjmallett "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n" 4645215976Sjmallett " When set, a double bit error had been detected\n" 4646215976Sjmallett " for a PP-generated QW Mode read transaction.\n" 4647215976Sjmallett " The CP2SYN contains the failing syndrome.\n" 4648215976Sjmallett " NOTE: PP-generated LW Mode Read transactions\n" 4649215976Sjmallett " do not participate in ECC check/correct).\n" 4650215976Sjmallett " Refer to CP2ECCENA.\n" 4651215976Sjmallett " If the CP2DBINA had previously been enabled(set),\n" 4652215976Sjmallett " an interrupt will be posted. Software can clear\n" 4653215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 4654215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 4655215976Sjmallett " about the memory address/control to help isolate\n" 4656215976Sjmallett " the failure.\n"; 4657215976Sjmallett fail |= cvmx_error_add(&info); 4658215976Sjmallett 4659215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4660215976Sjmallett info.status_addr = CVMX_DFA_ERR; 4661215976Sjmallett info.status_mask = 1ull<<14 /* dtesbe */; 4662215976Sjmallett info.enable_addr = 0; 4663215976Sjmallett info.enable_mask = 0; 4664215976Sjmallett info.flags = 0; 4665215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4666215976Sjmallett info.group_index = 0; 4667215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4668215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4669215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 4670215976Sjmallett info.func = __cvmx_error_handle_dfa_err_dtesbe; 4671215976Sjmallett info.user_info = (long) 4672215976Sjmallett "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n" 4673215976Sjmallett " When set, a single bit error had been detected and\n" 4674215976Sjmallett " corrected for a DTE-generated 36b SIMPLE Mode read\n" 4675215976Sjmallett " transaction.\n" 4676215976Sjmallett " If the DTEDBE=0, then the DTESYN contains the\n" 4677215976Sjmallett " failing syndrome (used during correction).\n" 4678215976Sjmallett " NOTE: DTE-generated 18b SIMPLE Mode Read\n" 4679215976Sjmallett " transactions do not participate in ECC check/correct).\n" 4680215976Sjmallett " If the DTESBINA had previously been enabled(set),\n" 4681215976Sjmallett " an interrupt will be posted. Software can clear\n" 4682215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 4683215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 4684215976Sjmallett " about the memory address/control to help isolate\n" 4685215976Sjmallett " the failure.\n"; 4686215976Sjmallett fail |= cvmx_error_add(&info); 4687215976Sjmallett 4688215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4689215976Sjmallett info.status_addr = CVMX_DFA_ERR; 4690215976Sjmallett info.status_mask = 1ull<<15 /* dtedbe */; 4691215976Sjmallett info.enable_addr = 0; 4692215976Sjmallett info.enable_mask = 0; 4693215976Sjmallett info.flags = 0; 4694215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4695215976Sjmallett info.group_index = 0; 4696215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4697215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4698215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 4699215976Sjmallett info.func = __cvmx_error_handle_dfa_err_dtedbe; 4700215976Sjmallett info.user_info = (long) 4701215976Sjmallett "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n" 4702215976Sjmallett " When set, a double bit error had been detected\n" 4703215976Sjmallett " for a DTE-generated 36b SIMPLE Mode read transaction.\n" 4704215976Sjmallett " The DTESYN contains the failing syndrome.\n" 4705215976Sjmallett " If the DTEDBINA had previously been enabled(set),\n" 4706215976Sjmallett " an interrupt will be posted. Software can clear\n" 4707215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 4708215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 4709215976Sjmallett " about the memory address/control to help isolate\n" 4710215976Sjmallett " the failure.\n" 4711215976Sjmallett " NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n" 4712215976Sjmallett " do not participate in ECC check/correct).\n"; 4713215976Sjmallett fail |= cvmx_error_add(&info); 4714215976Sjmallett 4715215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4716215976Sjmallett info.status_addr = CVMX_DFA_ERR; 4717215976Sjmallett info.status_mask = 1ull<<26 /* dteperr */; 4718215976Sjmallett info.enable_addr = 0; 4719215976Sjmallett info.enable_mask = 0; 4720215976Sjmallett info.flags = 0; 4721215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4722215976Sjmallett info.group_index = 0; 4723215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4724215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4725215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 4726215976Sjmallett info.func = __cvmx_error_handle_dfa_err_dteperr; 4727215976Sjmallett info.user_info = (long) 4728215976Sjmallett "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n" 4729215976Sjmallett " When set, all DTE-generated 18b SIMPLE Mode read\n" 4730215976Sjmallett " transactions which encounter a parity error (across\n" 4731215976Sjmallett " the 17b of data) are reported.\n"; 4732215976Sjmallett fail |= cvmx_error_add(&info); 4733215976Sjmallett 4734215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4735215976Sjmallett info.status_addr = CVMX_DFA_ERR; 4736215976Sjmallett info.status_mask = 1ull<<29 /* cp2perr */; 4737215976Sjmallett info.enable_addr = 0; 4738215976Sjmallett info.enable_mask = 0; 4739215976Sjmallett info.flags = 0; 4740215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4741215976Sjmallett info.group_index = 0; 4742215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4743215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4744215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 4745215976Sjmallett info.func = __cvmx_error_handle_dfa_err_cp2perr; 4746215976Sjmallett info.user_info = (long) 4747215976Sjmallett "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n" 4748215976Sjmallett " When set, a parity error had been detected for a\n" 4749215976Sjmallett " PP-generated LW Mode read transaction.\n" 4750215976Sjmallett " If the CP2PINA had previously been enabled(set),\n" 4751215976Sjmallett " an interrupt will be posted. Software can clear\n" 4752215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 4753215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 4754215976Sjmallett " about the memory address/control to help isolate\n" 4755215976Sjmallett " the failure.\n"; 4756215976Sjmallett fail |= cvmx_error_add(&info); 4757215976Sjmallett 4758215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4759215976Sjmallett info.status_addr = CVMX_DFA_ERR; 4760215976Sjmallett info.status_mask = 1ull<<31 /* dblovf */; 4761215976Sjmallett info.enable_addr = 0; 4762215976Sjmallett info.enable_mask = 0; 4763215976Sjmallett info.flags = 0; 4764215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4765215976Sjmallett info.group_index = 0; 4766215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4767215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4768215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 4769215976Sjmallett info.func = __cvmx_error_handle_dfa_err_dblovf; 4770215976Sjmallett info.user_info = (long) 4771215976Sjmallett "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n" 4772215976Sjmallett " When set, the 20b accumulated doorbell register\n" 4773215976Sjmallett " had overflowed (SW wrote too many doorbell requests).\n" 4774215976Sjmallett " If the DBLINA had previously been enabled(set),\n" 4775215976Sjmallett " an interrupt will be posted. Software can clear\n" 4776215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 4777215976Sjmallett " NOTE: Detection of a Doorbell Register overflow\n" 4778215976Sjmallett " is a catastrophic error which may leave the DFA\n" 4779215976Sjmallett " HW in an unrecoverable state.\n"; 4780215976Sjmallett fail |= cvmx_error_add(&info); 4781215976Sjmallett 4782215976Sjmallett /* CVMX_IOB_INT_SUM */ 4783215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4784215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 4785215976Sjmallett info.status_mask = 1ull<<0 /* np_sop */; 4786215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 4787215976Sjmallett info.enable_mask = 1ull<<0 /* np_sop */; 4788215976Sjmallett info.flags = 0; 4789215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4790215976Sjmallett info.group_index = 0; 4791215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4792215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4793215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 4794215976Sjmallett info.func = __cvmx_error_display; 4795215976Sjmallett info.user_info = (long) 4796215976Sjmallett "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n" 4797215976Sjmallett " port for a non-passthrough packet.\n" 4798215976Sjmallett " The first detected error associated with bits [5:0]\n" 4799215976Sjmallett " of this register will only be set here. A new bit\n" 4800215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 4801215976Sjmallett fail |= cvmx_error_add(&info); 4802215976Sjmallett 4803215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4804215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 4805215976Sjmallett info.status_mask = 1ull<<1 /* np_eop */; 4806215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 4807215976Sjmallett info.enable_mask = 1ull<<1 /* np_eop */; 4808215976Sjmallett info.flags = 0; 4809215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4810215976Sjmallett info.group_index = 0; 4811215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4812215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4813215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 4814215976Sjmallett info.func = __cvmx_error_display; 4815215976Sjmallett info.user_info = (long) 4816215976Sjmallett "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n" 4817215976Sjmallett " port for a non-passthrough packet.\n" 4818215976Sjmallett " The first detected error associated with bits [5:0]\n" 4819215976Sjmallett " of this register will only be set here. A new bit\n" 4820215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 4821215976Sjmallett fail |= cvmx_error_add(&info); 4822215976Sjmallett 4823215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4824215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 4825215976Sjmallett info.status_mask = 1ull<<2 /* p_sop */; 4826215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 4827215976Sjmallett info.enable_mask = 1ull<<2 /* p_sop */; 4828215976Sjmallett info.flags = 0; 4829215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4830215976Sjmallett info.group_index = 0; 4831215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4832215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4833215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 4834215976Sjmallett info.func = __cvmx_error_display; 4835215976Sjmallett info.user_info = (long) 4836215976Sjmallett "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n" 4837215976Sjmallett " port for a passthrough packet.\n" 4838215976Sjmallett " The first detected error associated with bits [5:0]\n" 4839215976Sjmallett " of this register will only be set here. A new bit\n" 4840215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 4841215976Sjmallett fail |= cvmx_error_add(&info); 4842215976Sjmallett 4843215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4844215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 4845215976Sjmallett info.status_mask = 1ull<<3 /* p_eop */; 4846215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 4847215976Sjmallett info.enable_mask = 1ull<<3 /* p_eop */; 4848215976Sjmallett info.flags = 0; 4849215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4850215976Sjmallett info.group_index = 0; 4851215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4852215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4853215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 4854215976Sjmallett info.func = __cvmx_error_display; 4855215976Sjmallett info.user_info = (long) 4856215976Sjmallett "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n" 4857215976Sjmallett " port for a passthrough packet.\n" 4858215976Sjmallett " The first detected error associated with bits [5:0]\n" 4859215976Sjmallett " of this register will only be set here. A new bit\n" 4860215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 4861215976Sjmallett fail |= cvmx_error_add(&info); 4862215976Sjmallett 4863215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4864215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 4865215976Sjmallett info.status_mask = 1ull<<4 /* np_dat */; 4866215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 4867215976Sjmallett info.enable_mask = 1ull<<4 /* np_dat */; 4868215976Sjmallett info.flags = 0; 4869215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4870215976Sjmallett info.group_index = 0; 4871215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4872215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4873215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 4874215976Sjmallett info.func = __cvmx_error_display; 4875215976Sjmallett info.user_info = (long) 4876215976Sjmallett "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n" 4877215976Sjmallett " port for a non-passthrough packet.\n" 4878215976Sjmallett " The first detected error associated with bits [5:0]\n" 4879215976Sjmallett " of this register will only be set here. A new bit\n" 4880215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 4881215976Sjmallett fail |= cvmx_error_add(&info); 4882215976Sjmallett 4883215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4884215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 4885215976Sjmallett info.status_mask = 1ull<<5 /* p_dat */; 4886215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 4887215976Sjmallett info.enable_mask = 1ull<<5 /* p_dat */; 4888215976Sjmallett info.flags = 0; 4889215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4890215976Sjmallett info.group_index = 0; 4891215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4892215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4893215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 4894215976Sjmallett info.func = __cvmx_error_display; 4895215976Sjmallett info.user_info = (long) 4896215976Sjmallett "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n" 4897215976Sjmallett " port for a passthrough packet.\n" 4898215976Sjmallett " The first detected error associated with bits [5:0]\n" 4899215976Sjmallett " of this register will only be set here. A new bit\n" 4900215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 4901215976Sjmallett fail |= cvmx_error_add(&info); 4902215976Sjmallett 4903215976Sjmallett /* CVMX_ZIP_ERROR */ 4904215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4905215976Sjmallett info.status_addr = CVMX_ZIP_ERROR; 4906215976Sjmallett info.status_mask = 1ull<<0 /* doorbell */; 4907215976Sjmallett info.enable_addr = CVMX_ZIP_INT_MASK; 4908215976Sjmallett info.enable_mask = 1ull<<0 /* doorbell */; 4909215976Sjmallett info.flags = 0; 4910215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4911215976Sjmallett info.group_index = 0; 4912215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4913215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 4914215976Sjmallett info.parent.status_mask = 1ull<<7 /* zip */; 4915215976Sjmallett info.func = __cvmx_error_display; 4916215976Sjmallett info.user_info = (long) 4917215976Sjmallett "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 4918215976Sjmallett fail |= cvmx_error_add(&info); 4919215976Sjmallett 4920215976Sjmallett return fail; 4921215976Sjmallett} 4922215976Sjmallett 4923