1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * @file 43215976Sjmallett * 44215976Sjmallett * Automatically generated error messages for cn56xxp1. 45215976Sjmallett * 46215976Sjmallett * This file is auto generated. Do not edit. 47215976Sjmallett * 48215976Sjmallett * <hr>$Revision$<hr> 49215976Sjmallett * 50215976Sjmallett * <hr><h2>Error tree for CN56XXP1</h2> 51215976Sjmallett * @dot 52215976Sjmallett * digraph cn56xxp1 53215976Sjmallett * { 54215976Sjmallett * rankdir=LR; 55215976Sjmallett * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica]; 56215976Sjmallett * edge [fontsize=7, font=helvitica]; 57215976Sjmallett * cvmx_root [label="ROOT|<root>root"]; 58215976Sjmallett * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"]; 59215976Sjmallett * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"]; 60215976Sjmallett * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"]; 61215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"]; 62215976Sjmallett * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"]; 63215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"]; 64215976Sjmallett * cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<tim>tim|<pko>pko|<pow>pow|<npei>npei|<rad>rad|<lmc1>lmc1|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<zip>zip|<usb>usb"]; 65215976Sjmallett * cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"]; 66215976Sjmallett * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"]; 67215976Sjmallett * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"]; 68215976Sjmallett * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"]; 69215976Sjmallett * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"]; 70215976Sjmallett * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"]; 71215976Sjmallett * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<out_ovr>out_ovr|<loststat>loststat"]; 72215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"]; 73215976Sjmallett * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"]; 74215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"]; 75215976Sjmallett * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"]; 76215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"]; 77215976Sjmallett * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 78215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"]; 79215976Sjmallett * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"]; 80215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"]; 81215976Sjmallett * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"]; 82215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"]; 83215976Sjmallett * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"]; 84215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"]; 85215976Sjmallett * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"]; 86215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"]; 87215976Sjmallett * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"]; 88215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"]; 89215976Sjmallett * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 90215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"]; 91215976Sjmallett * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"]; 92215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"]; 93215976Sjmallett * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"]; 94215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"]; 95215976Sjmallett * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"]; 96215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"]; 97215976Sjmallett * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"]; 98215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"]; 99215976Sjmallett * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw"]; 100215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"]; 101215976Sjmallett * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"]; 102215976Sjmallett * cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"]; 103215976Sjmallett * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"]; 104215976Sjmallett * cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"]; 105215976Sjmallett * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"]; 106215976Sjmallett * cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"]; 107215976Sjmallett * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"]; 108215976Sjmallett * cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"]; 109215976Sjmallett * cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"]; 110215976Sjmallett * cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"]; 111215976Sjmallett * cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"]; 112215976Sjmallett * cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"]; 113215976Sjmallett * cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"]; 114215976Sjmallett * cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"]; 115215976Sjmallett * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"]; 116215976Sjmallett * cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"]; 117215976Sjmallett * cvmx_lmc1_mem_cfg0 [label="LMCX_MEM_CFG0(1)|<sec_err>sec_err|<ded_err>ded_err"]; 118215976Sjmallett * cvmx_npei_rsl_int_blocks:lmc1:e -> cvmx_lmc1_mem_cfg0 [label="lmc1"]; 119215976Sjmallett * cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 120215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"]; 121215976Sjmallett * cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 122215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"]; 123215976Sjmallett * cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 124215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"]; 125215976Sjmallett * cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 126215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"]; 127215976Sjmallett * cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"]; 128215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"]; 129215976Sjmallett * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 130215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"]; 131215976Sjmallett * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 132215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"]; 133215976Sjmallett * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 134215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"]; 135215976Sjmallett * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 136215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"]; 137215976Sjmallett * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"]; 138215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"]; 139215976Sjmallett * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"]; 140215976Sjmallett * cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"]; 141215976Sjmallett * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"]; 142215976Sjmallett * cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"]; 143215976Sjmallett * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"]; 144215976Sjmallett * cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"]; 145215976Sjmallett * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"]; 146215976Sjmallett * cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"]; 147215976Sjmallett * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"]; 148215976Sjmallett * cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"]; 149215976Sjmallett * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"]; 150215976Sjmallett * cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"]; 151215976Sjmallett * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"]; 152215976Sjmallett * cvmx_npei_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"]; 153215976Sjmallett * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"]; 154215976Sjmallett * cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"]; 155215976Sjmallett * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis]; 156215976Sjmallett * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis]; 157215976Sjmallett * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis]; 158215976Sjmallett * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis]; 159215976Sjmallett * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis]; 160215976Sjmallett * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis]; 161215976Sjmallett * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis]; 162215976Sjmallett * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis]; 163215976Sjmallett * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis]; 164215976Sjmallett * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis]; 165215976Sjmallett * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis]; 166215976Sjmallett * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis]; 167215976Sjmallett * cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis]; 168215976Sjmallett * cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis]; 169215976Sjmallett * cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis]; 170215976Sjmallett * cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis]; 171215976Sjmallett * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis]; 172215976Sjmallett * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis]; 173215976Sjmallett * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis]; 174215976Sjmallett * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis]; 175215976Sjmallett * cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"]; 176215976Sjmallett * } 177215976Sjmallett * @enddot 178215976Sjmallett */ 179215976Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 180215976Sjmallett#include <asm/octeon/cvmx.h> 181215976Sjmallett#include <asm/octeon/cvmx-error.h> 182215976Sjmallett#include <asm/octeon/cvmx-error-custom.h> 183215976Sjmallett#include <asm/octeon/cvmx-csr-typedefs.h> 184215976Sjmallett#else 185215976Sjmallett#include "cvmx.h" 186215976Sjmallett#include "cvmx-error.h" 187215976Sjmallett#include "cvmx-error-custom.h" 188215976Sjmallett#endif 189215976Sjmallett 190215990Sjmallettint cvmx_error_initialize_cn56xxp1(void); 191215990Sjmallett 192215976Sjmallettint cvmx_error_initialize_cn56xxp1(void) 193215976Sjmallett{ 194215976Sjmallett cvmx_error_info_t info; 195215976Sjmallett int fail = 0; 196215976Sjmallett 197215976Sjmallett /* CVMX_CIU_INTX_SUM0(0) */ 198215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 199215976Sjmallett info.status_addr = CVMX_CIU_INTX_SUM0(0); 200215976Sjmallett info.status_mask = 0; 201215976Sjmallett info.enable_addr = 0; 202215976Sjmallett info.enable_mask = 0; 203215976Sjmallett info.flags = 0; 204215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 205215976Sjmallett info.group_index = 0; 206215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 207215976Sjmallett info.parent.status_addr = 0; 208215976Sjmallett info.parent.status_mask = 0; 209215976Sjmallett info.func = __cvmx_error_decode; 210215976Sjmallett info.user_info = 0; 211215976Sjmallett fail |= cvmx_error_add(&info); 212215976Sjmallett 213215976Sjmallett /* CVMX_MIXX_ISR(0) */ 214215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 215215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 216215976Sjmallett info.status_mask = 1ull<<0 /* odblovf */; 217215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 218215976Sjmallett info.enable_mask = 1ull<<0 /* ovfena */; 219215976Sjmallett info.flags = 0; 220215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 221215976Sjmallett info.group_index = 0; 222215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 223215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 224215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 225215976Sjmallett info.func = __cvmx_error_display; 226215976Sjmallett info.user_info = (long) 227215976Sjmallett "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n" 228215976Sjmallett " If SW attempts to write to the MIX_ORING2[ODBELL]\n" 229215976Sjmallett " with a value greater than the remaining #of\n" 230215976Sjmallett " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n" 231215976Sjmallett " the following occurs:\n" 232215976Sjmallett " 1) The MIX_ORING2[ODBELL] write is IGNORED\n" 233215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 234215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 235215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 236215976Sjmallett " and the local interrupt mask bit(OVFENA) is set, than an\n" 237215976Sjmallett " interrupt is reported for this event.\n" 238215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 239215976Sjmallett " (ie: cumulative # of ODBELL writes), and ensure that\n" 240215976Sjmallett " future ODBELL writes don't exceed the size of the\n" 241215976Sjmallett " O-Ring Buffer (MIX_ORING2[OSIZE]).\n" 242215976Sjmallett " SW must reclaim O-Ring Entries by writing to the\n" 243215976Sjmallett " MIX_ORCNT[ORCNT]. .\n" 244215976Sjmallett " NOTE: There is no recovery from an ODBLOVF Interrupt.\n" 245215976Sjmallett " If it occurs, it's an indication that SW has\n" 246215976Sjmallett " overwritten the O-Ring buffer, and the only recourse\n" 247215976Sjmallett " is a HW reset.\n"; 248215976Sjmallett fail |= cvmx_error_add(&info); 249215976Sjmallett 250215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 251215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 252215976Sjmallett info.status_mask = 1ull<<1 /* idblovf */; 253215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 254215976Sjmallett info.enable_mask = 1ull<<1 /* ivfena */; 255215976Sjmallett info.flags = 0; 256215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 257215976Sjmallett info.group_index = 0; 258215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 259215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 260215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 261215976Sjmallett info.func = __cvmx_error_display; 262215976Sjmallett info.user_info = (long) 263215976Sjmallett "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n" 264215976Sjmallett " If SW attempts to write to the MIX_IRING2[IDBELL]\n" 265215976Sjmallett " with a value greater than the remaining #of\n" 266215976Sjmallett " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n" 267215976Sjmallett " the following occurs:\n" 268215976Sjmallett " 1) The MIX_IRING2[IDBELL] write is IGNORED\n" 269215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 270215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 271215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 272215976Sjmallett " and the local interrupt mask bit(IVFENA) is set, than an\n" 273215976Sjmallett " interrupt is reported for this event.\n" 274215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 275215976Sjmallett " (ie: cumulative # of IDBELL writes), and ensure that\n" 276215976Sjmallett " future IDBELL writes don't exceed the size of the\n" 277215976Sjmallett " I-Ring Buffer (MIX_IRING2[ISIZE]).\n" 278215976Sjmallett " SW must reclaim I-Ring Entries by keeping track of the\n" 279215976Sjmallett " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n" 280215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] register represents the\n" 281215976Sjmallett " total #packets(not IRing Entries) and SW must further\n" 282215976Sjmallett " keep track of the # of I-Ring Entries associated with\n" 283215976Sjmallett " each packet as they are processed.\n" 284215976Sjmallett " NOTE: There is no recovery from an IDBLOVF Interrupt.\n" 285215976Sjmallett " If it occurs, it's an indication that SW has\n" 286215976Sjmallett " overwritten the I-Ring buffer, and the only recourse\n" 287215976Sjmallett " is a HW reset.\n"; 288215976Sjmallett fail |= cvmx_error_add(&info); 289215976Sjmallett 290215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 291215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 292215976Sjmallett info.status_mask = 1ull<<4 /* data_drp */; 293215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 294215976Sjmallett info.enable_mask = 1ull<<4 /* data_drpena */; 295215976Sjmallett info.flags = 0; 296215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 297215976Sjmallett info.group_index = 0; 298215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 299215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 300215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 301215976Sjmallett info.func = __cvmx_error_display; 302215976Sjmallett info.user_info = (long) 303215976Sjmallett "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n" 304215976Sjmallett " If this does occur, the DATA_DRP is set and the\n" 305215976Sjmallett " CIU_INTx_SUM0,4[MII] bits are set.\n" 306215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 307215976Sjmallett " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n" 308215976Sjmallett " interrupt is reported for this event.\n"; 309215976Sjmallett fail |= cvmx_error_add(&info); 310215976Sjmallett 311215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 312215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 313215976Sjmallett info.status_mask = 1ull<<5 /* irun */; 314215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 315215976Sjmallett info.enable_mask = 1ull<<5 /* irunena */; 316215976Sjmallett info.flags = 0; 317215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 318215976Sjmallett info.group_index = 0; 319215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 320215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 321215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 322215976Sjmallett info.func = __cvmx_error_display; 323215976Sjmallett info.user_info = (long) 324215976Sjmallett "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n" 325215976Sjmallett " If SW writes a larger value than what is currently\n" 326215976Sjmallett " in the MIX_IRCNT[IRCNT], then HW will report the\n" 327215976Sjmallett " underflow condition.\n" 328215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n" 329215976Sjmallett " NOTE: If an IRUN underflow condition is detected,\n" 330215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 331215976Sjmallett " been compromised. To recover, SW must issue a\n" 332215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 333215976Sjmallett fail |= cvmx_error_add(&info); 334215976Sjmallett 335215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 336215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 337215976Sjmallett info.status_mask = 1ull<<6 /* orun */; 338215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 339215976Sjmallett info.enable_mask = 1ull<<6 /* orunena */; 340215976Sjmallett info.flags = 0; 341215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 342215976Sjmallett info.group_index = 0; 343215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 344215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 345215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 346215976Sjmallett info.func = __cvmx_error_display; 347215976Sjmallett info.user_info = (long) 348215976Sjmallett "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n" 349215976Sjmallett " If SW writes a larger value than what is currently\n" 350215976Sjmallett " in the MIX_ORCNT[ORCNT], then HW will report the\n" 351215976Sjmallett " underflow condition.\n" 352215976Sjmallett " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n" 353215976Sjmallett " NOTE: If an ORUN underflow condition is detected,\n" 354215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 355215976Sjmallett " been compromised. To recover, SW must issue a\n" 356215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 357215976Sjmallett fail |= cvmx_error_add(&info); 358215976Sjmallett 359215976Sjmallett /* CVMX_CIU_INT_SUM1 */ 360215976Sjmallett /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */ 361215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 362215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 363215976Sjmallett info.status_mask = 0; 364215976Sjmallett info.enable_addr = 0; 365215976Sjmallett info.enable_mask = 0; 366215976Sjmallett info.flags = 0; 367215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 368215976Sjmallett info.group_index = 0; 369215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 370215976Sjmallett info.parent.status_addr = 0; 371215976Sjmallett info.parent.status_mask = 0; 372215976Sjmallett info.func = __cvmx_error_decode; 373215976Sjmallett info.user_info = 0; 374215976Sjmallett fail |= cvmx_error_add(&info); 375215976Sjmallett 376215976Sjmallett /* CVMX_L2C_INT_STAT */ 377215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 378215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 379215976Sjmallett info.status_mask = 1ull<<3 /* l2tsec */; 380215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 381215976Sjmallett info.enable_mask = 1ull<<3 /* l2tsecen */; 382215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 383215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 384215976Sjmallett info.group_index = 0; 385215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 386215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 387215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 388215976Sjmallett info.func = __cvmx_error_display; 389215976Sjmallett info.user_info = (long) 390215976Sjmallett "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n" 391215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 392215976Sjmallett " given index) are checked for single bit errors(SBEs).\n" 393215976Sjmallett " This bit is set if ANY of the 8 sets contains an SBE.\n" 394215976Sjmallett " SBEs are auto corrected in HW and generate an\n" 395215976Sjmallett " interrupt(if enabled).\n" 396215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n"; 397215976Sjmallett fail |= cvmx_error_add(&info); 398215976Sjmallett 399215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 400215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 401215976Sjmallett info.status_mask = 1ull<<5 /* l2dsec */; 402215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 403215976Sjmallett info.enable_mask = 1ull<<5 /* l2dsecen */; 404215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 405215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 406215976Sjmallett info.group_index = 0; 407215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 408215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 409215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 410215976Sjmallett info.func = __cvmx_error_display; 411215976Sjmallett info.user_info = (long) 412215976Sjmallett "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n" 413215976Sjmallett " NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n"; 414215976Sjmallett fail |= cvmx_error_add(&info); 415215976Sjmallett 416215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 417215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 418215976Sjmallett info.status_mask = 1ull<<0 /* oob1 */; 419215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 420215976Sjmallett info.enable_mask = 1ull<<0 /* oob1en */; 421215976Sjmallett info.flags = 0; 422215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 423215976Sjmallett info.group_index = 0; 424215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 425215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 426215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 427215976Sjmallett info.func = __cvmx_error_display; 428215976Sjmallett info.user_info = (long) 429215976Sjmallett "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n"; 430215976Sjmallett fail |= cvmx_error_add(&info); 431215976Sjmallett 432215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 433215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 434215976Sjmallett info.status_mask = 1ull<<1 /* oob2 */; 435215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 436215976Sjmallett info.enable_mask = 1ull<<1 /* oob2en */; 437215976Sjmallett info.flags = 0; 438215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 439215976Sjmallett info.group_index = 0; 440215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 441215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 442215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 443215976Sjmallett info.func = __cvmx_error_display; 444215976Sjmallett info.user_info = (long) 445215976Sjmallett "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n"; 446215976Sjmallett fail |= cvmx_error_add(&info); 447215976Sjmallett 448215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 449215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 450215976Sjmallett info.status_mask = 1ull<<2 /* oob3 */; 451215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 452215976Sjmallett info.enable_mask = 1ull<<2 /* oob3en */; 453215976Sjmallett info.flags = 0; 454215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 455215976Sjmallett info.group_index = 0; 456215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 457215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 458215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 459215976Sjmallett info.func = __cvmx_error_display; 460215976Sjmallett info.user_info = (long) 461215976Sjmallett "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n"; 462215976Sjmallett fail |= cvmx_error_add(&info); 463215976Sjmallett 464215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 465215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 466215976Sjmallett info.status_mask = 1ull<<4 /* l2tded */; 467215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 468215976Sjmallett info.enable_mask = 1ull<<4 /* l2tdeden */; 469215976Sjmallett info.flags = 0; 470215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 471215976Sjmallett info.group_index = 0; 472215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 473215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 474215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 475215976Sjmallett info.func = __cvmx_error_display; 476215976Sjmallett info.user_info = (long) 477215976Sjmallett "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n" 478215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 479215976Sjmallett " given index) are checked for double bit errors(DBEs).\n" 480215976Sjmallett " This bit is set if ANY of the 8 sets contains a DBE.\n" 481215976Sjmallett " DBEs also generated an interrupt(if enabled).\n" 482215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n"; 483215976Sjmallett fail |= cvmx_error_add(&info); 484215976Sjmallett 485215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 486215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 487215976Sjmallett info.status_mask = 1ull<<6 /* l2dded */; 488215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 489215976Sjmallett info.enable_mask = 1ull<<6 /* l2ddeden */; 490215976Sjmallett info.flags = 0; 491215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 492215976Sjmallett info.group_index = 0; 493215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 494215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 495215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 496215976Sjmallett info.func = __cvmx_error_display; 497215976Sjmallett info.user_info = (long) 498215976Sjmallett "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n" 499215976Sjmallett " NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n"; 500215976Sjmallett fail |= cvmx_error_add(&info); 501215976Sjmallett 502215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 503215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 504215976Sjmallett info.status_mask = 1ull<<7 /* lck */; 505215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 506215976Sjmallett info.enable_mask = 1ull<<7 /* lckena */; 507215976Sjmallett info.flags = 0; 508215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 509215976Sjmallett info.group_index = 0; 510215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 511215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 512215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 513215976Sjmallett info.func = __cvmx_error_display; 514215976Sjmallett info.user_info = (long) 515215976Sjmallett "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n" 516215976Sjmallett " the INDEX (which is ignored by HW - but reported to SW).\n" 517215976Sjmallett " The LDD(L1 load-miss) for the LOCK operation is completed\n" 518215976Sjmallett " successfully, however the address is NOT locked.\n" 519215976Sjmallett " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n" 520215976Sjmallett " into account. For example, if diagnostic PPx has\n" 521215976Sjmallett " UMSKx defined to only use SETs [1:0], and SET1 had\n" 522215976Sjmallett " been previously LOCKED, then an attempt to LOCK the\n" 523215976Sjmallett " last available SET0 would result in a LCKERR. (This\n" 524215976Sjmallett " is to ensure that at least 1 SET at each INDEX is\n" 525215976Sjmallett " not LOCKED for general use by other PPs).\n" 526215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n"; 527215976Sjmallett fail |= cvmx_error_add(&info); 528215976Sjmallett 529215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 530215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 531215976Sjmallett info.status_mask = 1ull<<8 /* lck2 */; 532215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 533215976Sjmallett info.enable_mask = 1ull<<8 /* lck2ena */; 534215976Sjmallett info.flags = 0; 535215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 536215976Sjmallett info.group_index = 0; 537215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 538215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 539215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 540215976Sjmallett info.func = __cvmx_error_display; 541215976Sjmallett info.user_info = (long) 542215976Sjmallett "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n" 543215976Sjmallett " could not find an available/unlocked set (for\n" 544215976Sjmallett " replacement).\n" 545215976Sjmallett " Most likely, this is a result of SW mixing SET\n" 546215976Sjmallett " PARTITIONING with ADDRESS LOCKING. If SW allows\n" 547215976Sjmallett " another PP to LOCKDOWN all SETs available to PP#n,\n" 548215976Sjmallett " then a Rd/Wr Miss from PP#n will be unable\n" 549215976Sjmallett " to determine a 'valid' replacement set (since LOCKED\n" 550215976Sjmallett " addresses should NEVER be replaced).\n" 551215976Sjmallett " If such an event occurs, the HW will select the smallest\n" 552215976Sjmallett " available SET(specified by UMSK'x)' as the replacement\n" 553215976Sjmallett " set, and the address is unlocked.\n" 554215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n"; 555215976Sjmallett fail |= cvmx_error_add(&info); 556215976Sjmallett 557215976Sjmallett /* CVMX_L2D_ERR */ 558215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 559215976Sjmallett info.status_addr = CVMX_L2D_ERR; 560215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 561215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 562215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 563215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 564215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 565215976Sjmallett info.group_index = 0; 566215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 567215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 568215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 569215976Sjmallett info.func = __cvmx_error_handle_l2d_err_sec_err; 570215976Sjmallett info.user_info = (long) 571215976Sjmallett "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n"; 572215976Sjmallett fail |= cvmx_error_add(&info); 573215976Sjmallett 574215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 575215976Sjmallett info.status_addr = CVMX_L2D_ERR; 576215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 577215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 578215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 579215976Sjmallett info.flags = 0; 580215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 581215976Sjmallett info.group_index = 0; 582215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 583215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 584215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 585215976Sjmallett info.func = __cvmx_error_handle_l2d_err_ded_err; 586215976Sjmallett info.user_info = (long) 587215976Sjmallett "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n"; 588215976Sjmallett fail |= cvmx_error_add(&info); 589215976Sjmallett 590215976Sjmallett /* CVMX_L2T_ERR */ 591215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 592215976Sjmallett info.status_addr = CVMX_L2T_ERR; 593215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 594215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 595215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 596215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 597215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 598215976Sjmallett info.group_index = 0; 599215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 600215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 601215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 602215976Sjmallett info.func = __cvmx_error_handle_l2t_err_sec_err; 603215976Sjmallett info.user_info = (long) 604215976Sjmallett "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n" 605215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 606215976Sjmallett " given index) are checked for single bit errors(SBEs).\n" 607215976Sjmallett " This bit is set if ANY of the 8 sets contains an SBE.\n" 608215976Sjmallett " SBEs are auto corrected in HW and generate an\n" 609215976Sjmallett " interrupt(if enabled).\n"; 610215976Sjmallett fail |= cvmx_error_add(&info); 611215976Sjmallett 612215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 613215976Sjmallett info.status_addr = CVMX_L2T_ERR; 614215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 615215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 616215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 617215976Sjmallett info.flags = 0; 618215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 619215976Sjmallett info.group_index = 0; 620215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 621215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 622215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 623215976Sjmallett info.func = __cvmx_error_handle_l2t_err_ded_err; 624215976Sjmallett info.user_info = (long) 625215976Sjmallett "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n" 626215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 627215976Sjmallett " given index) are checked for double bit errors(DBEs).\n" 628215976Sjmallett " This bit is set if ANY of the 8 sets contains a DBE.\n" 629215976Sjmallett " DBEs also generated an interrupt(if enabled).\n"; 630215976Sjmallett fail |= cvmx_error_add(&info); 631215976Sjmallett 632215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 633215976Sjmallett info.status_addr = CVMX_L2T_ERR; 634215976Sjmallett info.status_mask = 1ull<<24 /* lckerr */; 635215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 636215976Sjmallett info.enable_mask = 1ull<<25 /* lck_intena */; 637215976Sjmallett info.flags = 0; 638215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 639215976Sjmallett info.group_index = 0; 640215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 641215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 642215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 643215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr; 644215976Sjmallett info.user_info = (long) 645215976Sjmallett "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n" 646215976Sjmallett " the INDEX (which is ignored by HW - but reported to SW).\n" 647215976Sjmallett " The LDD(L1 load-miss) for the LOCK operation is completed\n" 648215976Sjmallett " successfully, however the address is NOT locked.\n" 649215976Sjmallett " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n" 650215976Sjmallett " into account. For example, if diagnostic PPx has\n" 651215976Sjmallett " UMSKx defined to only use SETs [1:0], and SET1 had\n" 652215976Sjmallett " been previously LOCKED, then an attempt to LOCK the\n" 653215976Sjmallett " last available SET0 would result in a LCKERR. (This\n" 654215976Sjmallett " is to ensure that at least 1 SET at each INDEX is\n" 655215976Sjmallett " not LOCKED for general use by other PPs).\n"; 656215976Sjmallett fail |= cvmx_error_add(&info); 657215976Sjmallett 658215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 659215976Sjmallett info.status_addr = CVMX_L2T_ERR; 660215976Sjmallett info.status_mask = 1ull<<26 /* lckerr2 */; 661215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 662215976Sjmallett info.enable_mask = 1ull<<27 /* lck_intena2 */; 663215976Sjmallett info.flags = 0; 664215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 665215976Sjmallett info.group_index = 0; 666215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 667215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 668215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 669215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr2; 670215976Sjmallett info.user_info = (long) 671215976Sjmallett "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n" 672215976Sjmallett " could not find an available/unlocked set (for\n" 673215976Sjmallett " replacement).\n" 674215976Sjmallett " Most likely, this is a result of SW mixing SET\n" 675215976Sjmallett " PARTITIONING with ADDRESS LOCKING. If SW allows\n" 676215976Sjmallett " another PP to LOCKDOWN all SETs available to PP#n,\n" 677215976Sjmallett " then a Rd/Wr Miss from PP#n will be unable\n" 678215976Sjmallett " to determine a 'valid' replacement set (since LOCKED\n" 679215976Sjmallett " addresses should NEVER be replaced).\n" 680215976Sjmallett " If such an event occurs, the HW will select the smallest\n" 681215976Sjmallett " available SET(specified by UMSK'x)' as the replacement\n" 682215976Sjmallett " set, and the address is unlocked.\n"; 683215976Sjmallett fail |= cvmx_error_add(&info); 684215976Sjmallett 685215976Sjmallett /* CVMX_AGL_GMX_BAD_REG */ 686215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 687215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 688215976Sjmallett info.status_mask = 1ull<<32 /* ovrflw */; 689215976Sjmallett info.enable_addr = 0; 690215976Sjmallett info.enable_mask = 0; 691215976Sjmallett info.flags = 0; 692215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 693215976Sjmallett info.group_index = 0; 694215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 695215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 696215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 697215976Sjmallett info.func = __cvmx_error_display; 698215976Sjmallett info.user_info = (long) 699215976Sjmallett "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow\n"; 700215976Sjmallett fail |= cvmx_error_add(&info); 701215976Sjmallett 702215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 703215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 704215976Sjmallett info.status_mask = 1ull<<33 /* txpop */; 705215976Sjmallett info.enable_addr = 0; 706215976Sjmallett info.enable_mask = 0; 707215976Sjmallett info.flags = 0; 708215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 709215976Sjmallett info.group_index = 0; 710215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 711215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 712215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 713215976Sjmallett info.func = __cvmx_error_display; 714215976Sjmallett info.user_info = (long) 715215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow\n"; 716215976Sjmallett fail |= cvmx_error_add(&info); 717215976Sjmallett 718215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 719215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 720215976Sjmallett info.status_mask = 1ull<<34 /* txpsh */; 721215976Sjmallett info.enable_addr = 0; 722215976Sjmallett info.enable_mask = 0; 723215976Sjmallett info.flags = 0; 724215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 725215976Sjmallett info.group_index = 0; 726215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 727215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 728215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 729215976Sjmallett info.func = __cvmx_error_display; 730215976Sjmallett info.user_info = (long) 731215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow\n"; 732215976Sjmallett fail |= cvmx_error_add(&info); 733215976Sjmallett 734215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 735215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 736215976Sjmallett info.status_mask = 1ull<<2 /* out_ovr */; 737215976Sjmallett info.enable_addr = 0; 738215976Sjmallett info.enable_mask = 0; 739215976Sjmallett info.flags = 0; 740215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 741215976Sjmallett info.group_index = 0; 742215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 743215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 744215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 745215976Sjmallett info.func = __cvmx_error_display; 746215976Sjmallett info.user_info = (long) 747215976Sjmallett "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n"; 748215976Sjmallett fail |= cvmx_error_add(&info); 749215976Sjmallett 750215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 751215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 752215976Sjmallett info.status_mask = 1ull<<22 /* loststat */; 753215976Sjmallett info.enable_addr = 0; 754215976Sjmallett info.enable_mask = 0; 755215976Sjmallett info.flags = 0; 756215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 757215976Sjmallett info.group_index = 0; 758215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 759215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 760215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 761215976Sjmallett info.func = __cvmx_error_display; 762215976Sjmallett info.user_info = (long) 763215976Sjmallett "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n" 764215976Sjmallett " TX Stats are corrupted\n"; 765215976Sjmallett fail |= cvmx_error_add(&info); 766215976Sjmallett 767215976Sjmallett /* CVMX_AGL_GMX_RXX_INT_REG(0) */ 768215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 769215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0); 770215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 771215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0); 772215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 773215976Sjmallett info.flags = 0; 774215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 775215976Sjmallett info.group_index = 0; 776215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 777215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 778215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 779215976Sjmallett info.func = __cvmx_error_display; 780215976Sjmallett info.user_info = (long) 781215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n"; 782215976Sjmallett fail |= cvmx_error_add(&info); 783215976Sjmallett 784215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 785215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0); 786215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 787215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0); 788215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 789215976Sjmallett info.flags = 0; 790215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 791215976Sjmallett info.group_index = 0; 792215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 793215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 794215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 795215976Sjmallett info.func = __cvmx_error_display; 796215976Sjmallett info.user_info = (long) 797215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n" 798215976Sjmallett " This interrupt should never assert\n"; 799215976Sjmallett fail |= cvmx_error_add(&info); 800215976Sjmallett 801215976Sjmallett /* CVMX_AGL_GMX_TX_INT_REG */ 802215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 803215976Sjmallett info.status_addr = CVMX_AGL_GMX_TX_INT_REG; 804215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 805215976Sjmallett info.enable_addr = CVMX_AGL_GMX_TX_INT_EN; 806215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 807215976Sjmallett info.flags = 0; 808215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 809215976Sjmallett info.group_index = 0; 810215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 811215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 812215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 813215976Sjmallett info.func = __cvmx_error_display; 814215976Sjmallett info.user_info = (long) 815215976Sjmallett "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 816215976Sjmallett fail |= cvmx_error_add(&info); 817215976Sjmallett 818215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 819215976Sjmallett info.status_addr = CVMX_AGL_GMX_TX_INT_REG; 820215976Sjmallett info.status_mask = 1ull<<2 /* undflw */; 821215976Sjmallett info.enable_addr = CVMX_AGL_GMX_TX_INT_EN; 822215976Sjmallett info.enable_mask = 1ull<<2 /* undflw */; 823215976Sjmallett info.flags = 0; 824215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 825215976Sjmallett info.group_index = 0; 826215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 827215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 828215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 829215976Sjmallett info.func = __cvmx_error_display; 830215976Sjmallett info.user_info = (long) 831215976Sjmallett "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n"; 832215976Sjmallett fail |= cvmx_error_add(&info); 833215976Sjmallett 834215976Sjmallett /* CVMX_GMXX_BAD_REG(0) */ 835215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 836215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 837215976Sjmallett info.status_mask = 0xfull<<2 /* out_ovr */; 838215976Sjmallett info.enable_addr = 0; 839215976Sjmallett info.enable_mask = 0; 840215976Sjmallett info.flags = 0; 841215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 842215976Sjmallett info.group_index = 0; 843215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 844215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 845215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 846215976Sjmallett info.func = __cvmx_error_display; 847215976Sjmallett info.user_info = (long) 848215976Sjmallett "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 849215976Sjmallett fail |= cvmx_error_add(&info); 850215976Sjmallett 851215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 852215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 853215976Sjmallett info.status_mask = 0xfull<<22 /* loststat */; 854215976Sjmallett info.enable_addr = 0; 855215976Sjmallett info.enable_mask = 0; 856215976Sjmallett info.flags = 0; 857215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 858215976Sjmallett info.group_index = 0; 859215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 860215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 861215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 862215976Sjmallett info.func = __cvmx_error_display; 863215976Sjmallett info.user_info = (long) 864215976Sjmallett "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n" 865215976Sjmallett " In SGMII, one bit per port\n" 866215976Sjmallett " In XAUI, only port0 is used\n" 867215976Sjmallett " TX Stats are corrupted\n"; 868215976Sjmallett fail |= cvmx_error_add(&info); 869215976Sjmallett 870215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 871215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 872215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 873215976Sjmallett info.enable_addr = 0; 874215976Sjmallett info.enable_mask = 0; 875215976Sjmallett info.flags = 0; 876215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 877215976Sjmallett info.group_index = 0; 878215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 879215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 880215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 881215976Sjmallett info.func = __cvmx_error_display; 882215976Sjmallett info.user_info = (long) 883215976Sjmallett "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n" 884215976Sjmallett " The common FIFO to SGMII and XAUI had an overflow\n" 885215976Sjmallett " TX Stats are corrupted\n"; 886215976Sjmallett fail |= cvmx_error_add(&info); 887215976Sjmallett 888215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 889215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 890215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 891215976Sjmallett info.enable_addr = 0; 892215976Sjmallett info.enable_mask = 0; 893215976Sjmallett info.flags = 0; 894215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 895215976Sjmallett info.group_index = 0; 896215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 897215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 898215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 899215976Sjmallett info.func = __cvmx_error_display; 900215976Sjmallett info.user_info = (long) 901215976Sjmallett "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 902215976Sjmallett fail |= cvmx_error_add(&info); 903215976Sjmallett 904215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,0) */ 905215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 906215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 907215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 908215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 909215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 910215976Sjmallett info.flags = 0; 911215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 912215976Sjmallett info.group_index = 0; 913215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 914215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 915215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 916215976Sjmallett info.func = __cvmx_error_display; 917215976Sjmallett info.user_info = (long) 918215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n" 919215976Sjmallett " (SGMII/1000Base-X only)\n"; 920215976Sjmallett fail |= cvmx_error_add(&info); 921215976Sjmallett 922215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 923215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 924215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 925215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 926215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 927215976Sjmallett info.flags = 0; 928215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 929215976Sjmallett info.group_index = 0; 930215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 931215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 932215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 933215976Sjmallett info.func = __cvmx_error_display; 934215976Sjmallett info.user_info = (long) 935215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n"; 936215976Sjmallett fail |= cvmx_error_add(&info); 937215976Sjmallett 938215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 939215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 940215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 941215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 942215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 943215976Sjmallett info.flags = 0; 944215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 945215976Sjmallett info.group_index = 0; 946215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 947215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 948215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 949215976Sjmallett info.func = __cvmx_error_display; 950215976Sjmallett info.user_info = (long) 951215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n" 952215976Sjmallett " This interrupt should never assert\n" 953215976Sjmallett " (SGMII/1000Base-X only)\n"; 954215976Sjmallett fail |= cvmx_error_add(&info); 955215976Sjmallett 956215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 957215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 958215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 959215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 960215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 961215976Sjmallett info.flags = 0; 962215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 963215976Sjmallett info.group_index = 0; 964215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 965215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 966215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 967215976Sjmallett info.func = __cvmx_error_display; 968215976Sjmallett info.user_info = (long) 969215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 970215976Sjmallett " (XAUI Mode only)\n"; 971215976Sjmallett fail |= cvmx_error_add(&info); 972215976Sjmallett 973215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 974215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 975215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 976215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 977215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 978215976Sjmallett info.flags = 0; 979215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 980215976Sjmallett info.group_index = 0; 981215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 982215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 983215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 984215976Sjmallett info.func = __cvmx_error_display; 985215976Sjmallett info.user_info = (long) 986215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 987215976Sjmallett " (XAUI Mode only)\n"; 988215976Sjmallett fail |= cvmx_error_add(&info); 989215976Sjmallett 990215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 991215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 992215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 993215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 994215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 995215976Sjmallett info.flags = 0; 996215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 997215976Sjmallett info.group_index = 0; 998215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 999215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1000215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1001215976Sjmallett info.func = __cvmx_error_display; 1002215976Sjmallett info.user_info = (long) 1003215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1004215976Sjmallett " (XAUI Mode only)\n"; 1005215976Sjmallett fail |= cvmx_error_add(&info); 1006215976Sjmallett 1007215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1008215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1009215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1010215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1011215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1012215976Sjmallett info.flags = 0; 1013215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1014215976Sjmallett info.group_index = 0; 1015215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1016215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1017215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1018215976Sjmallett info.func = __cvmx_error_display; 1019215976Sjmallett info.user_info = (long) 1020215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n" 1021215976Sjmallett " than /T/. The error propagation control\n" 1022215976Sjmallett " character /E/ will be included as part of the\n" 1023215976Sjmallett " frame and does not cause a frame termination.\n" 1024215976Sjmallett " (XAUI Mode only)\n"; 1025215976Sjmallett fail |= cvmx_error_add(&info); 1026215976Sjmallett 1027215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1028215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1029215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1030215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1031215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1032215976Sjmallett info.flags = 0; 1033215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1034215976Sjmallett info.group_index = 0; 1035215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1036215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1037215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1038215976Sjmallett info.func = __cvmx_error_display; 1039215976Sjmallett info.user_info = (long) 1040215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n" 1041215976Sjmallett " (XAUI Mode only)\n"; 1042215976Sjmallett fail |= cvmx_error_add(&info); 1043215976Sjmallett 1044215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1045215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1046215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1047215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1048215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1049215976Sjmallett info.flags = 0; 1050215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1051215976Sjmallett info.group_index = 0; 1052215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1053215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1054215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1055215976Sjmallett info.func = __cvmx_error_display; 1056215976Sjmallett info.user_info = (long) 1057215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n" 1058215976Sjmallett " (XAUI Mode only)\n"; 1059215976Sjmallett fail |= cvmx_error_add(&info); 1060215976Sjmallett 1061215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1062215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1063215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1064215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1065215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1066215976Sjmallett info.flags = 0; 1067215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1068215976Sjmallett info.group_index = 0; 1069215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1070215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1071215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1072215976Sjmallett info.func = __cvmx_error_display; 1073215976Sjmallett info.user_info = (long) 1074215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n" 1075215976Sjmallett " (XAUI Mode only)\n"; 1076215976Sjmallett fail |= cvmx_error_add(&info); 1077215976Sjmallett 1078215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,0) */ 1079215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1080215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1081215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1082215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1083215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1084215976Sjmallett info.flags = 0; 1085215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1086215976Sjmallett info.group_index = 1; 1087215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1088215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1089215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1090215976Sjmallett info.func = __cvmx_error_display; 1091215976Sjmallett info.user_info = (long) 1092215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n" 1093215976Sjmallett " (SGMII/1000Base-X only)\n"; 1094215976Sjmallett fail |= cvmx_error_add(&info); 1095215976Sjmallett 1096215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1097215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1098215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1099215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1100215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1101215976Sjmallett info.flags = 0; 1102215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1103215976Sjmallett info.group_index = 1; 1104215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1105215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1106215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1107215976Sjmallett info.func = __cvmx_error_display; 1108215976Sjmallett info.user_info = (long) 1109215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n"; 1110215976Sjmallett fail |= cvmx_error_add(&info); 1111215976Sjmallett 1112215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1113215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1114215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1115215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1116215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1117215976Sjmallett info.flags = 0; 1118215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1119215976Sjmallett info.group_index = 1; 1120215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1121215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1122215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1123215976Sjmallett info.func = __cvmx_error_display; 1124215976Sjmallett info.user_info = (long) 1125215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1126215976Sjmallett " This interrupt should never assert\n" 1127215976Sjmallett " (SGMII/1000Base-X only)\n"; 1128215976Sjmallett fail |= cvmx_error_add(&info); 1129215976Sjmallett 1130215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1131215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1132215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1133215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1134215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1135215976Sjmallett info.flags = 0; 1136215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1137215976Sjmallett info.group_index = 1; 1138215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1139215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1140215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1141215976Sjmallett info.func = __cvmx_error_display; 1142215976Sjmallett info.user_info = (long) 1143215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1144215976Sjmallett " (XAUI Mode only)\n"; 1145215976Sjmallett fail |= cvmx_error_add(&info); 1146215976Sjmallett 1147215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1148215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1149215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1150215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1151215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1152215976Sjmallett info.flags = 0; 1153215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1154215976Sjmallett info.group_index = 1; 1155215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1156215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1157215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1158215976Sjmallett info.func = __cvmx_error_display; 1159215976Sjmallett info.user_info = (long) 1160215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1161215976Sjmallett " (XAUI Mode only)\n"; 1162215976Sjmallett fail |= cvmx_error_add(&info); 1163215976Sjmallett 1164215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1165215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1166215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1167215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1168215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1169215976Sjmallett info.flags = 0; 1170215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1171215976Sjmallett info.group_index = 1; 1172215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1173215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1174215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1175215976Sjmallett info.func = __cvmx_error_display; 1176215976Sjmallett info.user_info = (long) 1177215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1178215976Sjmallett " (XAUI Mode only)\n"; 1179215976Sjmallett fail |= cvmx_error_add(&info); 1180215976Sjmallett 1181215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1182215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1183215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1184215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1185215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1186215976Sjmallett info.flags = 0; 1187215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1188215976Sjmallett info.group_index = 1; 1189215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1190215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1191215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1192215976Sjmallett info.func = __cvmx_error_display; 1193215976Sjmallett info.user_info = (long) 1194215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n" 1195215976Sjmallett " than /T/. The error propagation control\n" 1196215976Sjmallett " character /E/ will be included as part of the\n" 1197215976Sjmallett " frame and does not cause a frame termination.\n" 1198215976Sjmallett " (XAUI Mode only)\n"; 1199215976Sjmallett fail |= cvmx_error_add(&info); 1200215976Sjmallett 1201215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1202215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1203215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1204215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1205215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1206215976Sjmallett info.flags = 0; 1207215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1208215976Sjmallett info.group_index = 1; 1209215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1210215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1211215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1212215976Sjmallett info.func = __cvmx_error_display; 1213215976Sjmallett info.user_info = (long) 1214215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n" 1215215976Sjmallett " (XAUI Mode only)\n"; 1216215976Sjmallett fail |= cvmx_error_add(&info); 1217215976Sjmallett 1218215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1219215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1220215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1221215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1222215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1223215976Sjmallett info.flags = 0; 1224215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1225215976Sjmallett info.group_index = 1; 1226215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1227215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1228215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1229215976Sjmallett info.func = __cvmx_error_display; 1230215976Sjmallett info.user_info = (long) 1231215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n" 1232215976Sjmallett " (XAUI Mode only)\n"; 1233215976Sjmallett fail |= cvmx_error_add(&info); 1234215976Sjmallett 1235215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1236215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1237215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1238215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1239215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1240215976Sjmallett info.flags = 0; 1241215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1242215976Sjmallett info.group_index = 1; 1243215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1244215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1245215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1246215976Sjmallett info.func = __cvmx_error_display; 1247215976Sjmallett info.user_info = (long) 1248215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n" 1249215976Sjmallett " (XAUI Mode only)\n"; 1250215976Sjmallett fail |= cvmx_error_add(&info); 1251215976Sjmallett 1252215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,0) */ 1253215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1254215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1255215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1256215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1257215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1258215976Sjmallett info.flags = 0; 1259215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1260215976Sjmallett info.group_index = 2; 1261215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1262215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1263215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1264215976Sjmallett info.func = __cvmx_error_display; 1265215976Sjmallett info.user_info = (long) 1266215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n" 1267215976Sjmallett " (SGMII/1000Base-X only)\n"; 1268215976Sjmallett fail |= cvmx_error_add(&info); 1269215976Sjmallett 1270215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1271215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1272215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1273215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1274215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1275215976Sjmallett info.flags = 0; 1276215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1277215976Sjmallett info.group_index = 2; 1278215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1279215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1280215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1281215976Sjmallett info.func = __cvmx_error_display; 1282215976Sjmallett info.user_info = (long) 1283215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n"; 1284215976Sjmallett fail |= cvmx_error_add(&info); 1285215976Sjmallett 1286215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1287215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1288215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1289215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1290215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1291215976Sjmallett info.flags = 0; 1292215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1293215976Sjmallett info.group_index = 2; 1294215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1295215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1296215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1297215976Sjmallett info.func = __cvmx_error_display; 1298215976Sjmallett info.user_info = (long) 1299215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1300215976Sjmallett " This interrupt should never assert\n" 1301215976Sjmallett " (SGMII/1000Base-X only)\n"; 1302215976Sjmallett fail |= cvmx_error_add(&info); 1303215976Sjmallett 1304215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1305215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1306215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1307215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1308215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1309215976Sjmallett info.flags = 0; 1310215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1311215976Sjmallett info.group_index = 2; 1312215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1313215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1314215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1315215976Sjmallett info.func = __cvmx_error_display; 1316215976Sjmallett info.user_info = (long) 1317215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1318215976Sjmallett " (XAUI Mode only)\n"; 1319215976Sjmallett fail |= cvmx_error_add(&info); 1320215976Sjmallett 1321215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1322215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1323215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1324215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1325215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1326215976Sjmallett info.flags = 0; 1327215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1328215976Sjmallett info.group_index = 2; 1329215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1330215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1331215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1332215976Sjmallett info.func = __cvmx_error_display; 1333215976Sjmallett info.user_info = (long) 1334215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1335215976Sjmallett " (XAUI Mode only)\n"; 1336215976Sjmallett fail |= cvmx_error_add(&info); 1337215976Sjmallett 1338215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1339215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1340215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1341215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1342215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1343215976Sjmallett info.flags = 0; 1344215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1345215976Sjmallett info.group_index = 2; 1346215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1347215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1348215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1349215976Sjmallett info.func = __cvmx_error_display; 1350215976Sjmallett info.user_info = (long) 1351215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1352215976Sjmallett " (XAUI Mode only)\n"; 1353215976Sjmallett fail |= cvmx_error_add(&info); 1354215976Sjmallett 1355215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1356215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1357215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1358215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1359215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1360215976Sjmallett info.flags = 0; 1361215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1362215976Sjmallett info.group_index = 2; 1363215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1364215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1365215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1366215976Sjmallett info.func = __cvmx_error_display; 1367215976Sjmallett info.user_info = (long) 1368215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n" 1369215976Sjmallett " than /T/. The error propagation control\n" 1370215976Sjmallett " character /E/ will be included as part of the\n" 1371215976Sjmallett " frame and does not cause a frame termination.\n" 1372215976Sjmallett " (XAUI Mode only)\n"; 1373215976Sjmallett fail |= cvmx_error_add(&info); 1374215976Sjmallett 1375215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1376215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1377215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1378215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1379215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1380215976Sjmallett info.flags = 0; 1381215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1382215976Sjmallett info.group_index = 2; 1383215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1384215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1385215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1386215976Sjmallett info.func = __cvmx_error_display; 1387215976Sjmallett info.user_info = (long) 1388215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n" 1389215976Sjmallett " (XAUI Mode only)\n"; 1390215976Sjmallett fail |= cvmx_error_add(&info); 1391215976Sjmallett 1392215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1393215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1394215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1395215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1396215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1397215976Sjmallett info.flags = 0; 1398215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1399215976Sjmallett info.group_index = 2; 1400215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1401215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1402215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1403215976Sjmallett info.func = __cvmx_error_display; 1404215976Sjmallett info.user_info = (long) 1405215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n" 1406215976Sjmallett " (XAUI Mode only)\n"; 1407215976Sjmallett fail |= cvmx_error_add(&info); 1408215976Sjmallett 1409215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1410215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1411215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1412215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1413215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1414215976Sjmallett info.flags = 0; 1415215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1416215976Sjmallett info.group_index = 2; 1417215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1418215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1419215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1420215976Sjmallett info.func = __cvmx_error_display; 1421215976Sjmallett info.user_info = (long) 1422215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n" 1423215976Sjmallett " (XAUI Mode only)\n"; 1424215976Sjmallett fail |= cvmx_error_add(&info); 1425215976Sjmallett 1426215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(3,0) */ 1427215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1428215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1429215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1430215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1431215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1432215976Sjmallett info.flags = 0; 1433215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1434215976Sjmallett info.group_index = 3; 1435215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1436215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1437215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1438215976Sjmallett info.func = __cvmx_error_display; 1439215976Sjmallett info.user_info = (long) 1440215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n" 1441215976Sjmallett " (SGMII/1000Base-X only)\n"; 1442215976Sjmallett fail |= cvmx_error_add(&info); 1443215976Sjmallett 1444215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1445215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1446215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1447215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1448215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1449215976Sjmallett info.flags = 0; 1450215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1451215976Sjmallett info.group_index = 3; 1452215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1453215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1454215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1455215976Sjmallett info.func = __cvmx_error_display; 1456215976Sjmallett info.user_info = (long) 1457215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n"; 1458215976Sjmallett fail |= cvmx_error_add(&info); 1459215976Sjmallett 1460215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1461215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1462215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1463215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1464215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1465215976Sjmallett info.flags = 0; 1466215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1467215976Sjmallett info.group_index = 3; 1468215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1469215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1470215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1471215976Sjmallett info.func = __cvmx_error_display; 1472215976Sjmallett info.user_info = (long) 1473215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1474215976Sjmallett " This interrupt should never assert\n" 1475215976Sjmallett " (SGMII/1000Base-X only)\n"; 1476215976Sjmallett fail |= cvmx_error_add(&info); 1477215976Sjmallett 1478215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1479215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1480215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1481215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1482215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1483215976Sjmallett info.flags = 0; 1484215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1485215976Sjmallett info.group_index = 3; 1486215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1487215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1488215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1489215976Sjmallett info.func = __cvmx_error_display; 1490215976Sjmallett info.user_info = (long) 1491215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1492215976Sjmallett " (XAUI Mode only)\n"; 1493215976Sjmallett fail |= cvmx_error_add(&info); 1494215976Sjmallett 1495215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1496215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1497215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1498215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1499215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1500215976Sjmallett info.flags = 0; 1501215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1502215976Sjmallett info.group_index = 3; 1503215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1504215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1505215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1506215976Sjmallett info.func = __cvmx_error_display; 1507215976Sjmallett info.user_info = (long) 1508215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1509215976Sjmallett " (XAUI Mode only)\n"; 1510215976Sjmallett fail |= cvmx_error_add(&info); 1511215976Sjmallett 1512215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1513215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1514215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1515215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1516215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1517215976Sjmallett info.flags = 0; 1518215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1519215976Sjmallett info.group_index = 3; 1520215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1521215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1522215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1523215976Sjmallett info.func = __cvmx_error_display; 1524215976Sjmallett info.user_info = (long) 1525215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1526215976Sjmallett " (XAUI Mode only)\n"; 1527215976Sjmallett fail |= cvmx_error_add(&info); 1528215976Sjmallett 1529215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1530215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1531215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1532215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1533215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1534215976Sjmallett info.flags = 0; 1535215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1536215976Sjmallett info.group_index = 3; 1537215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1538215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1539215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1540215976Sjmallett info.func = __cvmx_error_display; 1541215976Sjmallett info.user_info = (long) 1542215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n" 1543215976Sjmallett " than /T/. The error propagation control\n" 1544215976Sjmallett " character /E/ will be included as part of the\n" 1545215976Sjmallett " frame and does not cause a frame termination.\n" 1546215976Sjmallett " (XAUI Mode only)\n"; 1547215976Sjmallett fail |= cvmx_error_add(&info); 1548215976Sjmallett 1549215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1550215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1551215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1552215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1553215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1554215976Sjmallett info.flags = 0; 1555215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1556215976Sjmallett info.group_index = 3; 1557215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1558215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1559215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1560215976Sjmallett info.func = __cvmx_error_display; 1561215976Sjmallett info.user_info = (long) 1562215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n" 1563215976Sjmallett " (XAUI Mode only)\n"; 1564215976Sjmallett fail |= cvmx_error_add(&info); 1565215976Sjmallett 1566215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1567215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1568215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1569215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1570215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1571215976Sjmallett info.flags = 0; 1572215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1573215976Sjmallett info.group_index = 3; 1574215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1575215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1576215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1577215976Sjmallett info.func = __cvmx_error_display; 1578215976Sjmallett info.user_info = (long) 1579215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n" 1580215976Sjmallett " (XAUI Mode only)\n"; 1581215976Sjmallett fail |= cvmx_error_add(&info); 1582215976Sjmallett 1583215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1584215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1585215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1586215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1587215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1588215976Sjmallett info.flags = 0; 1589215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1590215976Sjmallett info.group_index = 3; 1591215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1592215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1593215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1594215976Sjmallett info.func = __cvmx_error_display; 1595215976Sjmallett info.user_info = (long) 1596215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n" 1597215976Sjmallett " (XAUI Mode only)\n"; 1598215976Sjmallett fail |= cvmx_error_add(&info); 1599215976Sjmallett 1600215976Sjmallett /* CVMX_GMXX_TX_INT_REG(0) */ 1601215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1602215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 1603215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 1604215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 1605215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 1606215976Sjmallett info.flags = 0; 1607215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1608215976Sjmallett info.group_index = 0; 1609215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1610215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1611215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1612215976Sjmallett info.func = __cvmx_error_display; 1613215976Sjmallett info.user_info = (long) 1614215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 1615215976Sjmallett fail |= cvmx_error_add(&info); 1616215976Sjmallett 1617215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1618215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 1619215976Sjmallett info.status_mask = 0xfull<<2 /* undflw */; 1620215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 1621215976Sjmallett info.enable_mask = 0xfull<<2 /* undflw */; 1622215976Sjmallett info.flags = 0; 1623215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1624215976Sjmallett info.group_index = 0; 1625215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1626215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1627215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1628215976Sjmallett info.func = __cvmx_error_display; 1629215976Sjmallett info.user_info = (long) 1630215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n"; 1631215976Sjmallett fail |= cvmx_error_add(&info); 1632215976Sjmallett 1633215976Sjmallett /* CVMX_GMXX_BAD_REG(1) */ 1634215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1635215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 1636215976Sjmallett info.status_mask = 0xfull<<2 /* out_ovr */; 1637215976Sjmallett info.enable_addr = 0; 1638215976Sjmallett info.enable_mask = 0; 1639215976Sjmallett info.flags = 0; 1640215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1641215976Sjmallett info.group_index = 16; 1642215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1643215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1644215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1645215976Sjmallett info.func = __cvmx_error_display; 1646215976Sjmallett info.user_info = (long) 1647215976Sjmallett "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 1648215976Sjmallett fail |= cvmx_error_add(&info); 1649215976Sjmallett 1650215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1651215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 1652215976Sjmallett info.status_mask = 0xfull<<22 /* loststat */; 1653215976Sjmallett info.enable_addr = 0; 1654215976Sjmallett info.enable_mask = 0; 1655215976Sjmallett info.flags = 0; 1656215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1657215976Sjmallett info.group_index = 16; 1658215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1659215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1660215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1661215976Sjmallett info.func = __cvmx_error_display; 1662215976Sjmallett info.user_info = (long) 1663215976Sjmallett "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n" 1664215976Sjmallett " In SGMII, one bit per port\n" 1665215976Sjmallett " In XAUI, only port0 is used\n" 1666215976Sjmallett " TX Stats are corrupted\n"; 1667215976Sjmallett fail |= cvmx_error_add(&info); 1668215976Sjmallett 1669215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1670215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 1671215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 1672215976Sjmallett info.enable_addr = 0; 1673215976Sjmallett info.enable_mask = 0; 1674215976Sjmallett info.flags = 0; 1675215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1676215976Sjmallett info.group_index = 16; 1677215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1678215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1679215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1680215976Sjmallett info.func = __cvmx_error_display; 1681215976Sjmallett info.user_info = (long) 1682215976Sjmallett "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n" 1683215976Sjmallett " The common FIFO to SGMII and XAUI had an overflow\n" 1684215976Sjmallett " TX Stats are corrupted\n"; 1685215976Sjmallett fail |= cvmx_error_add(&info); 1686215976Sjmallett 1687215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1688215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 1689215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 1690215976Sjmallett info.enable_addr = 0; 1691215976Sjmallett info.enable_mask = 0; 1692215976Sjmallett info.flags = 0; 1693215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1694215976Sjmallett info.group_index = 16; 1695215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1696215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1697215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1698215976Sjmallett info.func = __cvmx_error_display; 1699215976Sjmallett info.user_info = (long) 1700215976Sjmallett "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 1701215976Sjmallett fail |= cvmx_error_add(&info); 1702215976Sjmallett 1703215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,1) */ 1704215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1705215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1706215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1707215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1708215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1709215976Sjmallett info.flags = 0; 1710215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1711215976Sjmallett info.group_index = 16; 1712215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1713215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1714215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1715215976Sjmallett info.func = __cvmx_error_display; 1716215976Sjmallett info.user_info = (long) 1717215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n" 1718215976Sjmallett " (SGMII/1000Base-X only)\n"; 1719215976Sjmallett fail |= cvmx_error_add(&info); 1720215976Sjmallett 1721215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1722215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1723215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1724215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1725215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1726215976Sjmallett info.flags = 0; 1727215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1728215976Sjmallett info.group_index = 16; 1729215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1730215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1731215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1732215976Sjmallett info.func = __cvmx_error_display; 1733215976Sjmallett info.user_info = (long) 1734215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n"; 1735215976Sjmallett fail |= cvmx_error_add(&info); 1736215976Sjmallett 1737215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1738215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1739215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1740215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1741215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1742215976Sjmallett info.flags = 0; 1743215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1744215976Sjmallett info.group_index = 16; 1745215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1746215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1747215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1748215976Sjmallett info.func = __cvmx_error_display; 1749215976Sjmallett info.user_info = (long) 1750215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n" 1751215976Sjmallett " This interrupt should never assert\n" 1752215976Sjmallett " (SGMII/1000Base-X only)\n"; 1753215976Sjmallett fail |= cvmx_error_add(&info); 1754215976Sjmallett 1755215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1756215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1757215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1758215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1759215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1760215976Sjmallett info.flags = 0; 1761215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1762215976Sjmallett info.group_index = 16; 1763215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1764215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1765215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1766215976Sjmallett info.func = __cvmx_error_display; 1767215976Sjmallett info.user_info = (long) 1768215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1769215976Sjmallett " (XAUI Mode only)\n"; 1770215976Sjmallett fail |= cvmx_error_add(&info); 1771215976Sjmallett 1772215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1773215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1774215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1775215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1776215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1777215976Sjmallett info.flags = 0; 1778215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1779215976Sjmallett info.group_index = 16; 1780215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1781215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1782215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1783215976Sjmallett info.func = __cvmx_error_display; 1784215976Sjmallett info.user_info = (long) 1785215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1786215976Sjmallett " (XAUI Mode only)\n"; 1787215976Sjmallett fail |= cvmx_error_add(&info); 1788215976Sjmallett 1789215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1790215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1791215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1792215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1793215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1794215976Sjmallett info.flags = 0; 1795215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1796215976Sjmallett info.group_index = 16; 1797215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1798215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1799215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1800215976Sjmallett info.func = __cvmx_error_display; 1801215976Sjmallett info.user_info = (long) 1802215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n" 1803215976Sjmallett " (XAUI Mode only)\n"; 1804215976Sjmallett fail |= cvmx_error_add(&info); 1805215976Sjmallett 1806215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1807215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1808215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1809215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1810215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1811215976Sjmallett info.flags = 0; 1812215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1813215976Sjmallett info.group_index = 16; 1814215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1815215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1816215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1817215976Sjmallett info.func = __cvmx_error_display; 1818215976Sjmallett info.user_info = (long) 1819215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n" 1820215976Sjmallett " than /T/. The error propagation control\n" 1821215976Sjmallett " character /E/ will be included as part of the\n" 1822215976Sjmallett " frame and does not cause a frame termination.\n" 1823215976Sjmallett " (XAUI Mode only)\n"; 1824215976Sjmallett fail |= cvmx_error_add(&info); 1825215976Sjmallett 1826215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1827215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1828215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1829215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1830215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1831215976Sjmallett info.flags = 0; 1832215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1833215976Sjmallett info.group_index = 16; 1834215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1835215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1836215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1837215976Sjmallett info.func = __cvmx_error_display; 1838215976Sjmallett info.user_info = (long) 1839215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n" 1840215976Sjmallett " (XAUI Mode only)\n"; 1841215976Sjmallett fail |= cvmx_error_add(&info); 1842215976Sjmallett 1843215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1844215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1845215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1846215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1847215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1848215976Sjmallett info.flags = 0; 1849215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1850215976Sjmallett info.group_index = 16; 1851215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1852215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1853215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1854215976Sjmallett info.func = __cvmx_error_display; 1855215976Sjmallett info.user_info = (long) 1856215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n" 1857215976Sjmallett " (XAUI Mode only)\n"; 1858215976Sjmallett fail |= cvmx_error_add(&info); 1859215976Sjmallett 1860215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1861215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1862215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1863215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1864215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1865215976Sjmallett info.flags = 0; 1866215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1867215976Sjmallett info.group_index = 16; 1868215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1869215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1870215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1871215976Sjmallett info.func = __cvmx_error_display; 1872215976Sjmallett info.user_info = (long) 1873215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n" 1874215976Sjmallett " (XAUI Mode only)\n"; 1875215976Sjmallett fail |= cvmx_error_add(&info); 1876215976Sjmallett 1877215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,1) */ 1878215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1879215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 1880215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1881215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 1882215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1883215976Sjmallett info.flags = 0; 1884215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1885215976Sjmallett info.group_index = 17; 1886215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1887215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1888215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1889215976Sjmallett info.func = __cvmx_error_display; 1890215976Sjmallett info.user_info = (long) 1891215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n" 1892215976Sjmallett " (SGMII/1000Base-X only)\n"; 1893215976Sjmallett fail |= cvmx_error_add(&info); 1894215976Sjmallett 1895215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1896215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 1897215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1898215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 1899215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1900215976Sjmallett info.flags = 0; 1901215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1902215976Sjmallett info.group_index = 17; 1903215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1904215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1905215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1906215976Sjmallett info.func = __cvmx_error_display; 1907215976Sjmallett info.user_info = (long) 1908215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n"; 1909215976Sjmallett fail |= cvmx_error_add(&info); 1910215976Sjmallett 1911215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1912215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 1913215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1914215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 1915215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1916215976Sjmallett info.flags = 0; 1917215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1918215976Sjmallett info.group_index = 17; 1919215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1920215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1921215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1922215976Sjmallett info.func = __cvmx_error_display; 1923215976Sjmallett info.user_info = (long) 1924215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n" 1925215976Sjmallett " This interrupt should never assert\n" 1926215976Sjmallett " (SGMII/1000Base-X only)\n"; 1927215976Sjmallett fail |= cvmx_error_add(&info); 1928215976Sjmallett 1929215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1930215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 1931215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1932215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 1933215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1934215976Sjmallett info.flags = 0; 1935215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1936215976Sjmallett info.group_index = 17; 1937215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1938215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1939215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1940215976Sjmallett info.func = __cvmx_error_display; 1941215976Sjmallett info.user_info = (long) 1942215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1943215976Sjmallett " (XAUI Mode only)\n"; 1944215976Sjmallett fail |= cvmx_error_add(&info); 1945215976Sjmallett 1946215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1947215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 1948215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1949215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 1950215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1951215976Sjmallett info.flags = 0; 1952215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1953215976Sjmallett info.group_index = 17; 1954215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1955215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1956215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1957215976Sjmallett info.func = __cvmx_error_display; 1958215976Sjmallett info.user_info = (long) 1959215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1960215976Sjmallett " (XAUI Mode only)\n"; 1961215976Sjmallett fail |= cvmx_error_add(&info); 1962215976Sjmallett 1963215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1964215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 1965215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1966215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 1967215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1968215976Sjmallett info.flags = 0; 1969215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1970215976Sjmallett info.group_index = 17; 1971215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1972215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1973215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1974215976Sjmallett info.func = __cvmx_error_display; 1975215976Sjmallett info.user_info = (long) 1976215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n" 1977215976Sjmallett " (XAUI Mode only)\n"; 1978215976Sjmallett fail |= cvmx_error_add(&info); 1979215976Sjmallett 1980215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1981215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 1982215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1983215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 1984215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1985215976Sjmallett info.flags = 0; 1986215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1987215976Sjmallett info.group_index = 17; 1988215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1989215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1990215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1991215976Sjmallett info.func = __cvmx_error_display; 1992215976Sjmallett info.user_info = (long) 1993215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n" 1994215976Sjmallett " than /T/. The error propagation control\n" 1995215976Sjmallett " character /E/ will be included as part of the\n" 1996215976Sjmallett " frame and does not cause a frame termination.\n" 1997215976Sjmallett " (XAUI Mode only)\n"; 1998215976Sjmallett fail |= cvmx_error_add(&info); 1999215976Sjmallett 2000215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2001215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2002215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 2003215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2004215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 2005215976Sjmallett info.flags = 0; 2006215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2007215976Sjmallett info.group_index = 17; 2008215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2009215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2010215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2011215976Sjmallett info.func = __cvmx_error_display; 2012215976Sjmallett info.user_info = (long) 2013215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n" 2014215976Sjmallett " (XAUI Mode only)\n"; 2015215976Sjmallett fail |= cvmx_error_add(&info); 2016215976Sjmallett 2017215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2018215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2019215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 2020215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2021215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 2022215976Sjmallett info.flags = 0; 2023215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2024215976Sjmallett info.group_index = 17; 2025215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2026215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2027215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2028215976Sjmallett info.func = __cvmx_error_display; 2029215976Sjmallett info.user_info = (long) 2030215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n" 2031215976Sjmallett " (XAUI Mode only)\n"; 2032215976Sjmallett fail |= cvmx_error_add(&info); 2033215976Sjmallett 2034215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2035215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2036215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 2037215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2038215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 2039215976Sjmallett info.flags = 0; 2040215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2041215976Sjmallett info.group_index = 17; 2042215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2043215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2044215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2045215976Sjmallett info.func = __cvmx_error_display; 2046215976Sjmallett info.user_info = (long) 2047215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n" 2048215976Sjmallett " (XAUI Mode only)\n"; 2049215976Sjmallett fail |= cvmx_error_add(&info); 2050215976Sjmallett 2051215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,1) */ 2052215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2053215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2054215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2055215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2056215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2057215976Sjmallett info.flags = 0; 2058215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2059215976Sjmallett info.group_index = 18; 2060215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2061215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2062215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2063215976Sjmallett info.func = __cvmx_error_display; 2064215976Sjmallett info.user_info = (long) 2065215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n" 2066215976Sjmallett " (SGMII/1000Base-X only)\n"; 2067215976Sjmallett fail |= cvmx_error_add(&info); 2068215976Sjmallett 2069215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2070215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2071215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2072215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2073215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2074215976Sjmallett info.flags = 0; 2075215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2076215976Sjmallett info.group_index = 18; 2077215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2078215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2079215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2080215976Sjmallett info.func = __cvmx_error_display; 2081215976Sjmallett info.user_info = (long) 2082215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n"; 2083215976Sjmallett fail |= cvmx_error_add(&info); 2084215976Sjmallett 2085215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2086215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2087215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2088215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2089215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2090215976Sjmallett info.flags = 0; 2091215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2092215976Sjmallett info.group_index = 18; 2093215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2094215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2095215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2096215976Sjmallett info.func = __cvmx_error_display; 2097215976Sjmallett info.user_info = (long) 2098215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n" 2099215976Sjmallett " This interrupt should never assert\n" 2100215976Sjmallett " (SGMII/1000Base-X only)\n"; 2101215976Sjmallett fail |= cvmx_error_add(&info); 2102215976Sjmallett 2103215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2104215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2105215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 2106215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2107215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 2108215976Sjmallett info.flags = 0; 2109215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2110215976Sjmallett info.group_index = 18; 2111215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2112215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2113215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2114215976Sjmallett info.func = __cvmx_error_display; 2115215976Sjmallett info.user_info = (long) 2116215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n" 2117215976Sjmallett " (XAUI Mode only)\n"; 2118215976Sjmallett fail |= cvmx_error_add(&info); 2119215976Sjmallett 2120215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2121215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2122215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 2123215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2124215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 2125215976Sjmallett info.flags = 0; 2126215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2127215976Sjmallett info.group_index = 18; 2128215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2129215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2130215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2131215976Sjmallett info.func = __cvmx_error_display; 2132215976Sjmallett info.user_info = (long) 2133215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n" 2134215976Sjmallett " (XAUI Mode only)\n"; 2135215976Sjmallett fail |= cvmx_error_add(&info); 2136215976Sjmallett 2137215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2138215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2139215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 2140215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2141215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 2142215976Sjmallett info.flags = 0; 2143215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2144215976Sjmallett info.group_index = 18; 2145215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2146215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2147215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2148215976Sjmallett info.func = __cvmx_error_display; 2149215976Sjmallett info.user_info = (long) 2150215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n" 2151215976Sjmallett " (XAUI Mode only)\n"; 2152215976Sjmallett fail |= cvmx_error_add(&info); 2153215976Sjmallett 2154215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2155215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2156215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 2157215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2158215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 2159215976Sjmallett info.flags = 0; 2160215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2161215976Sjmallett info.group_index = 18; 2162215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2163215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2164215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2165215976Sjmallett info.func = __cvmx_error_display; 2166215976Sjmallett info.user_info = (long) 2167215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n" 2168215976Sjmallett " than /T/. The error propagation control\n" 2169215976Sjmallett " character /E/ will be included as part of the\n" 2170215976Sjmallett " frame and does not cause a frame termination.\n" 2171215976Sjmallett " (XAUI Mode only)\n"; 2172215976Sjmallett fail |= cvmx_error_add(&info); 2173215976Sjmallett 2174215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2175215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2176215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 2177215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2178215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 2179215976Sjmallett info.flags = 0; 2180215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2181215976Sjmallett info.group_index = 18; 2182215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2183215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2184215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2185215976Sjmallett info.func = __cvmx_error_display; 2186215976Sjmallett info.user_info = (long) 2187215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n" 2188215976Sjmallett " (XAUI Mode only)\n"; 2189215976Sjmallett fail |= cvmx_error_add(&info); 2190215976Sjmallett 2191215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2192215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2193215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 2194215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2195215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 2196215976Sjmallett info.flags = 0; 2197215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2198215976Sjmallett info.group_index = 18; 2199215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2200215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2201215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2202215976Sjmallett info.func = __cvmx_error_display; 2203215976Sjmallett info.user_info = (long) 2204215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n" 2205215976Sjmallett " (XAUI Mode only)\n"; 2206215976Sjmallett fail |= cvmx_error_add(&info); 2207215976Sjmallett 2208215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2209215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2210215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 2211215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2212215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 2213215976Sjmallett info.flags = 0; 2214215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2215215976Sjmallett info.group_index = 18; 2216215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2217215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2218215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2219215976Sjmallett info.func = __cvmx_error_display; 2220215976Sjmallett info.user_info = (long) 2221215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n" 2222215976Sjmallett " (XAUI Mode only)\n"; 2223215976Sjmallett fail |= cvmx_error_add(&info); 2224215976Sjmallett 2225215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(3,1) */ 2226215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2227215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2228215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2229215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2230215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2231215976Sjmallett info.flags = 0; 2232215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2233215976Sjmallett info.group_index = 19; 2234215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2235215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2236215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2237215976Sjmallett info.func = __cvmx_error_display; 2238215976Sjmallett info.user_info = (long) 2239215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n" 2240215976Sjmallett " (SGMII/1000Base-X only)\n"; 2241215976Sjmallett fail |= cvmx_error_add(&info); 2242215976Sjmallett 2243215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2244215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2245215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2246215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2247215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2248215976Sjmallett info.flags = 0; 2249215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2250215976Sjmallett info.group_index = 19; 2251215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2252215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2253215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2254215976Sjmallett info.func = __cvmx_error_display; 2255215976Sjmallett info.user_info = (long) 2256215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n"; 2257215976Sjmallett fail |= cvmx_error_add(&info); 2258215976Sjmallett 2259215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2260215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2261215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2262215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2263215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2264215976Sjmallett info.flags = 0; 2265215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2266215976Sjmallett info.group_index = 19; 2267215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2268215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2269215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2270215976Sjmallett info.func = __cvmx_error_display; 2271215976Sjmallett info.user_info = (long) 2272215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n" 2273215976Sjmallett " This interrupt should never assert\n" 2274215976Sjmallett " (SGMII/1000Base-X only)\n"; 2275215976Sjmallett fail |= cvmx_error_add(&info); 2276215976Sjmallett 2277215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2278215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2279215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 2280215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2281215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 2282215976Sjmallett info.flags = 0; 2283215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2284215976Sjmallett info.group_index = 19; 2285215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2286215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2287215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2288215976Sjmallett info.func = __cvmx_error_display; 2289215976Sjmallett info.user_info = (long) 2290215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n" 2291215976Sjmallett " (XAUI Mode only)\n"; 2292215976Sjmallett fail |= cvmx_error_add(&info); 2293215976Sjmallett 2294215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2295215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2296215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 2297215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2298215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 2299215976Sjmallett info.flags = 0; 2300215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2301215976Sjmallett info.group_index = 19; 2302215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2303215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2304215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2305215976Sjmallett info.func = __cvmx_error_display; 2306215976Sjmallett info.user_info = (long) 2307215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n" 2308215976Sjmallett " (XAUI Mode only)\n"; 2309215976Sjmallett fail |= cvmx_error_add(&info); 2310215976Sjmallett 2311215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2312215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2313215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 2314215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2315215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 2316215976Sjmallett info.flags = 0; 2317215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2318215976Sjmallett info.group_index = 19; 2319215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2320215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2321215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2322215976Sjmallett info.func = __cvmx_error_display; 2323215976Sjmallett info.user_info = (long) 2324215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n" 2325215976Sjmallett " (XAUI Mode only)\n"; 2326215976Sjmallett fail |= cvmx_error_add(&info); 2327215976Sjmallett 2328215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2329215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2330215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 2331215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2332215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 2333215976Sjmallett info.flags = 0; 2334215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2335215976Sjmallett info.group_index = 19; 2336215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2337215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2338215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2339215976Sjmallett info.func = __cvmx_error_display; 2340215976Sjmallett info.user_info = (long) 2341215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n" 2342215976Sjmallett " than /T/. The error propagation control\n" 2343215976Sjmallett " character /E/ will be included as part of the\n" 2344215976Sjmallett " frame and does not cause a frame termination.\n" 2345215976Sjmallett " (XAUI Mode only)\n"; 2346215976Sjmallett fail |= cvmx_error_add(&info); 2347215976Sjmallett 2348215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2349215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2350215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 2351215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2352215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 2353215976Sjmallett info.flags = 0; 2354215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2355215976Sjmallett info.group_index = 19; 2356215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2357215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2358215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2359215976Sjmallett info.func = __cvmx_error_display; 2360215976Sjmallett info.user_info = (long) 2361215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n" 2362215976Sjmallett " (XAUI Mode only)\n"; 2363215976Sjmallett fail |= cvmx_error_add(&info); 2364215976Sjmallett 2365215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2366215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2367215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 2368215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2369215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 2370215976Sjmallett info.flags = 0; 2371215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2372215976Sjmallett info.group_index = 19; 2373215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2374215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2375215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2376215976Sjmallett info.func = __cvmx_error_display; 2377215976Sjmallett info.user_info = (long) 2378215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n" 2379215976Sjmallett " (XAUI Mode only)\n"; 2380215976Sjmallett fail |= cvmx_error_add(&info); 2381215976Sjmallett 2382215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2383215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2384215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 2385215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2386215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 2387215976Sjmallett info.flags = 0; 2388215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2389215976Sjmallett info.group_index = 19; 2390215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2391215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2392215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2393215976Sjmallett info.func = __cvmx_error_display; 2394215976Sjmallett info.user_info = (long) 2395215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n" 2396215976Sjmallett " (XAUI Mode only)\n"; 2397215976Sjmallett fail |= cvmx_error_add(&info); 2398215976Sjmallett 2399215976Sjmallett /* CVMX_GMXX_TX_INT_REG(1) */ 2400215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2401215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(1); 2402215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 2403215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(1); 2404215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 2405215976Sjmallett info.flags = 0; 2406215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2407215976Sjmallett info.group_index = 16; 2408215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2409215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2410215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2411215976Sjmallett info.func = __cvmx_error_display; 2412215976Sjmallett info.user_info = (long) 2413215976Sjmallett "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 2414215976Sjmallett fail |= cvmx_error_add(&info); 2415215976Sjmallett 2416215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2417215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(1); 2418215976Sjmallett info.status_mask = 0xfull<<2 /* undflw */; 2419215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(1); 2420215976Sjmallett info.enable_mask = 0xfull<<2 /* undflw */; 2421215976Sjmallett info.flags = 0; 2422215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2423215976Sjmallett info.group_index = 16; 2424215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2425215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2426215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2427215976Sjmallett info.func = __cvmx_error_display; 2428215976Sjmallett info.user_info = (long) 2429215976Sjmallett "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n"; 2430215976Sjmallett fail |= cvmx_error_add(&info); 2431215976Sjmallett 2432215976Sjmallett /* CVMX_IPD_INT_SUM */ 2433215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2434215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2435215976Sjmallett info.status_mask = 1ull<<0 /* prc_par0 */; 2436215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2437215976Sjmallett info.enable_mask = 1ull<<0 /* prc_par0 */; 2438215976Sjmallett info.flags = 0; 2439215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2440215976Sjmallett info.group_index = 0; 2441215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2442215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2443215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2444215976Sjmallett info.func = __cvmx_error_display; 2445215976Sjmallett info.user_info = (long) 2446215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n" 2447215976Sjmallett " [31:0] of the PBM memory.\n"; 2448215976Sjmallett fail |= cvmx_error_add(&info); 2449215976Sjmallett 2450215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2451215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2452215976Sjmallett info.status_mask = 1ull<<1 /* prc_par1 */; 2453215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2454215976Sjmallett info.enable_mask = 1ull<<1 /* prc_par1 */; 2455215976Sjmallett info.flags = 0; 2456215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2457215976Sjmallett info.group_index = 0; 2458215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2459215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2460215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2461215976Sjmallett info.func = __cvmx_error_display; 2462215976Sjmallett info.user_info = (long) 2463215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n" 2464215976Sjmallett " [63:32] of the PBM memory.\n"; 2465215976Sjmallett fail |= cvmx_error_add(&info); 2466215976Sjmallett 2467215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2468215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2469215976Sjmallett info.status_mask = 1ull<<2 /* prc_par2 */; 2470215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2471215976Sjmallett info.enable_mask = 1ull<<2 /* prc_par2 */; 2472215976Sjmallett info.flags = 0; 2473215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2474215976Sjmallett info.group_index = 0; 2475215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2476215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2477215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2478215976Sjmallett info.func = __cvmx_error_display; 2479215976Sjmallett info.user_info = (long) 2480215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n" 2481215976Sjmallett " [95:64] of the PBM memory.\n"; 2482215976Sjmallett fail |= cvmx_error_add(&info); 2483215976Sjmallett 2484215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2485215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2486215976Sjmallett info.status_mask = 1ull<<3 /* prc_par3 */; 2487215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2488215976Sjmallett info.enable_mask = 1ull<<3 /* prc_par3 */; 2489215976Sjmallett info.flags = 0; 2490215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2491215976Sjmallett info.group_index = 0; 2492215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2493215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2494215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2495215976Sjmallett info.func = __cvmx_error_display; 2496215976Sjmallett info.user_info = (long) 2497215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n" 2498215976Sjmallett " [127:96] of the PBM memory.\n"; 2499215976Sjmallett fail |= cvmx_error_add(&info); 2500215976Sjmallett 2501215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2502215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2503215976Sjmallett info.status_mask = 1ull<<4 /* bp_sub */; 2504215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2505215976Sjmallett info.enable_mask = 1ull<<4 /* bp_sub */; 2506215976Sjmallett info.flags = 0; 2507215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2508215976Sjmallett info.group_index = 0; 2509215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2510215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2511215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2512215976Sjmallett info.func = __cvmx_error_display; 2513215976Sjmallett info.user_info = (long) 2514215976Sjmallett "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n" 2515215976Sjmallett " supplied illegal value.\n"; 2516215976Sjmallett fail |= cvmx_error_add(&info); 2517215976Sjmallett 2518215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2519215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2520215976Sjmallett info.status_mask = 1ull<<5 /* dc_ovr */; 2521215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2522215976Sjmallett info.enable_mask = 1ull<<5 /* dc_ovr */; 2523215976Sjmallett info.flags = 0; 2524215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2525215976Sjmallett info.group_index = 0; 2526215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2527215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2528215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2529215976Sjmallett info.func = __cvmx_error_display; 2530215976Sjmallett info.user_info = (long) 2531215976Sjmallett "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"; 2532215976Sjmallett fail |= cvmx_error_add(&info); 2533215976Sjmallett 2534215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2535215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2536215976Sjmallett info.status_mask = 1ull<<6 /* cc_ovr */; 2537215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2538215976Sjmallett info.enable_mask = 1ull<<6 /* cc_ovr */; 2539215976Sjmallett info.flags = 0; 2540215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2541215976Sjmallett info.group_index = 0; 2542215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2543215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2544215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2545215976Sjmallett info.func = __cvmx_error_display; 2546215976Sjmallett info.user_info = (long) 2547215976Sjmallett "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"; 2548215976Sjmallett fail |= cvmx_error_add(&info); 2549215976Sjmallett 2550215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2551215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2552215976Sjmallett info.status_mask = 1ull<<7 /* c_coll */; 2553215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2554215976Sjmallett info.enable_mask = 1ull<<7 /* c_coll */; 2555215976Sjmallett info.flags = 0; 2556215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2557215976Sjmallett info.group_index = 0; 2558215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2559215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2560215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2561215976Sjmallett info.func = __cvmx_error_display; 2562215976Sjmallett info.user_info = (long) 2563215976Sjmallett "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n" 2564215976Sjmallett " collides.\n"; 2565215976Sjmallett fail |= cvmx_error_add(&info); 2566215976Sjmallett 2567215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2568215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2569215976Sjmallett info.status_mask = 1ull<<8 /* d_coll */; 2570215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2571215976Sjmallett info.enable_mask = 1ull<<8 /* d_coll */; 2572215976Sjmallett info.flags = 0; 2573215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2574215976Sjmallett info.group_index = 0; 2575215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2576215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2577215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2578215976Sjmallett info.func = __cvmx_error_display; 2579215976Sjmallett info.user_info = (long) 2580215976Sjmallett "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n" 2581215976Sjmallett " collides.\n"; 2582215976Sjmallett fail |= cvmx_error_add(&info); 2583215976Sjmallett 2584215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2585215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2586215976Sjmallett info.status_mask = 1ull<<9 /* bc_ovr */; 2587215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2588215976Sjmallett info.enable_mask = 1ull<<9 /* bc_ovr */; 2589215976Sjmallett info.flags = 0; 2590215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2591215976Sjmallett info.group_index = 0; 2592215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2593215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2594215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2595215976Sjmallett info.func = __cvmx_error_display; 2596215976Sjmallett info.user_info = (long) 2597215976Sjmallett "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"; 2598215976Sjmallett fail |= cvmx_error_add(&info); 2599215976Sjmallett 2600215976Sjmallett /* CVMX_TIM_REG_ERROR */ 2601215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2602215976Sjmallett info.status_addr = CVMX_TIM_REG_ERROR; 2603215976Sjmallett info.status_mask = 0xffffull<<0 /* mask */; 2604215976Sjmallett info.enable_addr = CVMX_TIM_REG_INT_MASK; 2605215976Sjmallett info.enable_mask = 0xffffull<<0 /* mask */; 2606215976Sjmallett info.flags = 0; 2607215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2608215976Sjmallett info.group_index = 0; 2609215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2610215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2611215976Sjmallett info.parent.status_mask = 1ull<<11 /* tim */; 2612215976Sjmallett info.func = __cvmx_error_display; 2613215976Sjmallett info.user_info = (long) 2614215976Sjmallett "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n"; 2615215976Sjmallett fail |= cvmx_error_add(&info); 2616215976Sjmallett 2617215976Sjmallett /* CVMX_PKO_REG_ERROR */ 2618215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2619215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 2620215976Sjmallett info.status_mask = 1ull<<0 /* parity */; 2621215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 2622215976Sjmallett info.enable_mask = 1ull<<0 /* parity */; 2623215976Sjmallett info.flags = 0; 2624215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2625215976Sjmallett info.group_index = 0; 2626215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2627215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2628215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 2629215976Sjmallett info.func = __cvmx_error_display; 2630215976Sjmallett info.user_info = (long) 2631215976Sjmallett "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n"; 2632215976Sjmallett fail |= cvmx_error_add(&info); 2633215976Sjmallett 2634215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2635215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 2636215976Sjmallett info.status_mask = 1ull<<1 /* doorbell */; 2637215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 2638215976Sjmallett info.enable_mask = 1ull<<1 /* doorbell */; 2639215976Sjmallett info.flags = 0; 2640215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2641215976Sjmallett info.group_index = 0; 2642215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2643215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2644215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 2645215976Sjmallett info.func = __cvmx_error_display; 2646215976Sjmallett info.user_info = (long) 2647215976Sjmallett "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 2648215976Sjmallett fail |= cvmx_error_add(&info); 2649215976Sjmallett 2650215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2651215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 2652215976Sjmallett info.status_mask = 1ull<<2 /* currzero */; 2653215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 2654215976Sjmallett info.enable_mask = 1ull<<2 /* currzero */; 2655215976Sjmallett info.flags = 0; 2656215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2657215976Sjmallett info.group_index = 0; 2658215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2659215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2660215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 2661215976Sjmallett info.func = __cvmx_error_display; 2662215976Sjmallett info.user_info = (long) 2663215976Sjmallett "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n"; 2664215976Sjmallett fail |= cvmx_error_add(&info); 2665215976Sjmallett 2666215976Sjmallett /* CVMX_POW_ECC_ERR */ 2667215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2668215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2669215976Sjmallett info.status_mask = 1ull<<0 /* sbe */; 2670215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2671215976Sjmallett info.enable_mask = 1ull<<2 /* sbe_ie */; 2672215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 2673215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2674215976Sjmallett info.group_index = 0; 2675215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2676215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2677215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2678215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_sbe; 2679215976Sjmallett info.user_info = (long) 2680215976Sjmallett "ERROR POW_ECC_ERR[SBE]: Single bit error\n"; 2681215976Sjmallett fail |= cvmx_error_add(&info); 2682215976Sjmallett 2683215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2684215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2685215976Sjmallett info.status_mask = 1ull<<1 /* dbe */; 2686215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2687215976Sjmallett info.enable_mask = 1ull<<3 /* dbe_ie */; 2688215976Sjmallett info.flags = 0; 2689215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2690215976Sjmallett info.group_index = 0; 2691215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2692215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2693215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2694215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_dbe; 2695215976Sjmallett info.user_info = (long) 2696215976Sjmallett "ERROR POW_ECC_ERR[DBE]: Double bit error\n"; 2697215976Sjmallett fail |= cvmx_error_add(&info); 2698215976Sjmallett 2699215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2700215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2701215976Sjmallett info.status_mask = 1ull<<12 /* rpe */; 2702215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2703215976Sjmallett info.enable_mask = 1ull<<13 /* rpe_ie */; 2704215976Sjmallett info.flags = 0; 2705215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2706215976Sjmallett info.group_index = 0; 2707215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2708215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2709215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2710215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_rpe; 2711215976Sjmallett info.user_info = (long) 2712215976Sjmallett "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n"; 2713215976Sjmallett fail |= cvmx_error_add(&info); 2714215976Sjmallett 2715215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2716215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2717215976Sjmallett info.status_mask = 0x1fffull<<16 /* iop */; 2718215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2719215976Sjmallett info.enable_mask = 0x1fffull<<32 /* iop_ie */; 2720215976Sjmallett info.flags = 0; 2721215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2722215976Sjmallett info.group_index = 0; 2723215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2724215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2725215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2726215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_iop; 2727215976Sjmallett info.user_info = (long) 2728215976Sjmallett "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n"; 2729215976Sjmallett fail |= cvmx_error_add(&info); 2730215976Sjmallett 2731215976Sjmallett /* CVMX_PEXP_NPEI_INT_SUM */ 2732215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2733215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2734215976Sjmallett info.status_mask = 1ull<<59 /* c0_ldwn */; 2735215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2736215976Sjmallett info.enable_mask = 1ull<<59 /* c0_ldwn */; 2737215976Sjmallett info.flags = 0; 2738215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2739215976Sjmallett info.group_index = 0; 2740215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2741215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2742215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2743215976Sjmallett info.func = __cvmx_error_display; 2744215976Sjmallett info.user_info = (long) 2745215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n"; 2746215976Sjmallett fail |= cvmx_error_add(&info); 2747215976Sjmallett 2748215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2749215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2750215976Sjmallett info.status_mask = 1ull<<21 /* c0_se */; 2751215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2752215976Sjmallett info.enable_mask = 1ull<<21 /* c0_se */; 2753215976Sjmallett info.flags = 0; 2754215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2755215976Sjmallett info.group_index = 0; 2756215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2757215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2758215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2759215976Sjmallett info.func = __cvmx_error_display; 2760215976Sjmallett info.user_info = (long) 2761215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n" 2762215976Sjmallett " Pcie Core 0. (cfg_sys_err_rc)\n"; 2763215976Sjmallett fail |= cvmx_error_add(&info); 2764215976Sjmallett 2765215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2766215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2767215976Sjmallett info.status_mask = 1ull<<38 /* c0_un_b0 */; 2768215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2769215976Sjmallett info.enable_mask = 1ull<<38 /* c0_un_b0 */; 2770215976Sjmallett info.flags = 0; 2771215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2772215976Sjmallett info.group_index = 0; 2773215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2774215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2775215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2776215976Sjmallett info.func = __cvmx_error_display; 2777215976Sjmallett info.user_info = (long) 2778215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n" 2779215976Sjmallett " Core 0.\n"; 2780215976Sjmallett fail |= cvmx_error_add(&info); 2781215976Sjmallett 2782215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2783215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2784215976Sjmallett info.status_mask = 1ull<<39 /* c0_un_b1 */; 2785215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2786215976Sjmallett info.enable_mask = 1ull<<39 /* c0_un_b1 */; 2787215976Sjmallett info.flags = 0; 2788215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2789215976Sjmallett info.group_index = 0; 2790215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2791215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2792215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2793215976Sjmallett info.func = __cvmx_error_display; 2794215976Sjmallett info.user_info = (long) 2795215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n" 2796215976Sjmallett " Core 0.\n"; 2797215976Sjmallett fail |= cvmx_error_add(&info); 2798215976Sjmallett 2799215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2800215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2801215976Sjmallett info.status_mask = 1ull<<40 /* c0_un_b2 */; 2802215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2803215976Sjmallett info.enable_mask = 1ull<<40 /* c0_un_b2 */; 2804215976Sjmallett info.flags = 0; 2805215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2806215976Sjmallett info.group_index = 0; 2807215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2808215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2809215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2810215976Sjmallett info.func = __cvmx_error_display; 2811215976Sjmallett info.user_info = (long) 2812215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n" 2813215976Sjmallett " Core 0.\n"; 2814215976Sjmallett fail |= cvmx_error_add(&info); 2815215976Sjmallett 2816215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2817215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2818215976Sjmallett info.status_mask = 1ull<<42 /* c0_un_bx */; 2819215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2820215976Sjmallett info.enable_mask = 1ull<<42 /* c0_un_bx */; 2821215976Sjmallett info.flags = 0; 2822215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2823215976Sjmallett info.group_index = 0; 2824215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2825215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2826215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2827215976Sjmallett info.func = __cvmx_error_display; 2828215976Sjmallett info.user_info = (long) 2829215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n" 2830215976Sjmallett " Core 0.\n"; 2831215976Sjmallett fail |= cvmx_error_add(&info); 2832215976Sjmallett 2833215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2834215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2835215976Sjmallett info.status_mask = 1ull<<53 /* c0_un_wf */; 2836215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2837215976Sjmallett info.enable_mask = 1ull<<53 /* c0_un_wf */; 2838215976Sjmallett info.flags = 0; 2839215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2840215976Sjmallett info.group_index = 0; 2841215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2842215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2843215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2844215976Sjmallett info.func = __cvmx_error_display; 2845215976Sjmallett info.user_info = (long) 2846215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n" 2847215976Sjmallett " register. Core0.\n"; 2848215976Sjmallett fail |= cvmx_error_add(&info); 2849215976Sjmallett 2850215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2851215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2852215976Sjmallett info.status_mask = 1ull<<41 /* c0_un_wi */; 2853215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2854215976Sjmallett info.enable_mask = 1ull<<41 /* c0_un_wi */; 2855215976Sjmallett info.flags = 0; 2856215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2857215976Sjmallett info.group_index = 0; 2858215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2859215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2860215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2861215976Sjmallett info.func = __cvmx_error_display; 2862215976Sjmallett info.user_info = (long) 2863215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n" 2864215976Sjmallett " Core 0.\n"; 2865215976Sjmallett fail |= cvmx_error_add(&info); 2866215976Sjmallett 2867215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2868215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2869215976Sjmallett info.status_mask = 1ull<<33 /* c0_up_b0 */; 2870215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2871215976Sjmallett info.enable_mask = 1ull<<33 /* c0_up_b0 */; 2872215976Sjmallett info.flags = 0; 2873215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2874215976Sjmallett info.group_index = 0; 2875215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2876215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2877215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2878215976Sjmallett info.func = __cvmx_error_display; 2879215976Sjmallett info.user_info = (long) 2880215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n" 2881215976Sjmallett " Core 0.\n"; 2882215976Sjmallett fail |= cvmx_error_add(&info); 2883215976Sjmallett 2884215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2885215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2886215976Sjmallett info.status_mask = 1ull<<34 /* c0_up_b1 */; 2887215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2888215976Sjmallett info.enable_mask = 1ull<<34 /* c0_up_b1 */; 2889215976Sjmallett info.flags = 0; 2890215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2891215976Sjmallett info.group_index = 0; 2892215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2893215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2894215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2895215976Sjmallett info.func = __cvmx_error_display; 2896215976Sjmallett info.user_info = (long) 2897215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n" 2898215976Sjmallett " Core 0.\n"; 2899215976Sjmallett fail |= cvmx_error_add(&info); 2900215976Sjmallett 2901215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2902215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2903215976Sjmallett info.status_mask = 1ull<<35 /* c0_up_b2 */; 2904215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2905215976Sjmallett info.enable_mask = 1ull<<35 /* c0_up_b2 */; 2906215976Sjmallett info.flags = 0; 2907215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2908215976Sjmallett info.group_index = 0; 2909215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2910215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2911215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2912215976Sjmallett info.func = __cvmx_error_display; 2913215976Sjmallett info.user_info = (long) 2914215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n" 2915215976Sjmallett " Core 0.\n"; 2916215976Sjmallett fail |= cvmx_error_add(&info); 2917215976Sjmallett 2918215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2919215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2920215976Sjmallett info.status_mask = 1ull<<37 /* c0_up_bx */; 2921215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2922215976Sjmallett info.enable_mask = 1ull<<37 /* c0_up_bx */; 2923215976Sjmallett info.flags = 0; 2924215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2925215976Sjmallett info.group_index = 0; 2926215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2927215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2928215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2929215976Sjmallett info.func = __cvmx_error_display; 2930215976Sjmallett info.user_info = (long) 2931215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n" 2932215976Sjmallett " Core 0.\n"; 2933215976Sjmallett fail |= cvmx_error_add(&info); 2934215976Sjmallett 2935215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2936215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2937215976Sjmallett info.status_mask = 1ull<<55 /* c0_up_wf */; 2938215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2939215976Sjmallett info.enable_mask = 1ull<<55 /* c0_up_wf */; 2940215976Sjmallett info.flags = 0; 2941215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2942215976Sjmallett info.group_index = 0; 2943215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2944215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2945215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2946215976Sjmallett info.func = __cvmx_error_display; 2947215976Sjmallett info.user_info = (long) 2948215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n" 2949215976Sjmallett " register. Core0.\n"; 2950215976Sjmallett fail |= cvmx_error_add(&info); 2951215976Sjmallett 2952215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2953215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2954215976Sjmallett info.status_mask = 1ull<<36 /* c0_up_wi */; 2955215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2956215976Sjmallett info.enable_mask = 1ull<<36 /* c0_up_wi */; 2957215976Sjmallett info.flags = 0; 2958215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2959215976Sjmallett info.group_index = 0; 2960215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2961215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2962215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2963215976Sjmallett info.func = __cvmx_error_display; 2964215976Sjmallett info.user_info = (long) 2965215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n" 2966215976Sjmallett " Core 0.\n"; 2967215976Sjmallett fail |= cvmx_error_add(&info); 2968215976Sjmallett 2969215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2970215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2971215976Sjmallett info.status_mask = 1ull<<23 /* c0_wake */; 2972215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2973215976Sjmallett info.enable_mask = 1ull<<23 /* c0_wake */; 2974215976Sjmallett info.flags = 0; 2975215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2976215976Sjmallett info.group_index = 0; 2977215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2978215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2979215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2980215976Sjmallett info.func = __cvmx_error_display; 2981215976Sjmallett info.user_info = (long) 2982215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n" 2983215976Sjmallett " Pcie Core 0. (wake_n)\n" 2984215976Sjmallett " Octeon will never generate this interrupt.\n"; 2985215976Sjmallett fail |= cvmx_error_add(&info); 2986215976Sjmallett 2987215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2988215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2989215976Sjmallett info.status_mask = 1ull<<60 /* c1_ldwn */; 2990215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2991215976Sjmallett info.enable_mask = 1ull<<60 /* c1_ldwn */; 2992215976Sjmallett info.flags = 0; 2993215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2994215976Sjmallett info.group_index = 1; 2995215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2996215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2997215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2998215976Sjmallett info.func = __cvmx_error_display; 2999215976Sjmallett info.user_info = (long) 3000215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n"; 3001215976Sjmallett fail |= cvmx_error_add(&info); 3002215976Sjmallett 3003215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3004215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3005215976Sjmallett info.status_mask = 1ull<<28 /* c1_se */; 3006215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3007215976Sjmallett info.enable_mask = 1ull<<28 /* c1_se */; 3008215976Sjmallett info.flags = 0; 3009215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3010215976Sjmallett info.group_index = 1; 3011215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3012215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3013215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3014215976Sjmallett info.func = __cvmx_error_display; 3015215976Sjmallett info.user_info = (long) 3016215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n" 3017215976Sjmallett " Pcie Core 1. (cfg_sys_err_rc)\n"; 3018215976Sjmallett fail |= cvmx_error_add(&info); 3019215976Sjmallett 3020215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3021215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3022215976Sjmallett info.status_mask = 1ull<<48 /* c1_un_b0 */; 3023215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3024215976Sjmallett info.enable_mask = 1ull<<48 /* c1_un_b0 */; 3025215976Sjmallett info.flags = 0; 3026215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3027215976Sjmallett info.group_index = 1; 3028215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3029215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3030215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3031215976Sjmallett info.func = __cvmx_error_display; 3032215976Sjmallett info.user_info = (long) 3033215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n" 3034215976Sjmallett " Core 1.\n"; 3035215976Sjmallett fail |= cvmx_error_add(&info); 3036215976Sjmallett 3037215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3038215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3039215976Sjmallett info.status_mask = 1ull<<49 /* c1_un_b1 */; 3040215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3041215976Sjmallett info.enable_mask = 1ull<<49 /* c1_un_b1 */; 3042215976Sjmallett info.flags = 0; 3043215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3044215976Sjmallett info.group_index = 1; 3045215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3046215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3047215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3048215976Sjmallett info.func = __cvmx_error_display; 3049215976Sjmallett info.user_info = (long) 3050215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n" 3051215976Sjmallett " Core 1.\n"; 3052215976Sjmallett fail |= cvmx_error_add(&info); 3053215976Sjmallett 3054215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3055215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3056215976Sjmallett info.status_mask = 1ull<<50 /* c1_un_b2 */; 3057215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3058215976Sjmallett info.enable_mask = 1ull<<50 /* c1_un_b2 */; 3059215976Sjmallett info.flags = 0; 3060215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3061215976Sjmallett info.group_index = 1; 3062215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3063215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3064215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3065215976Sjmallett info.func = __cvmx_error_display; 3066215976Sjmallett info.user_info = (long) 3067215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n" 3068215976Sjmallett " Core 1.\n"; 3069215976Sjmallett fail |= cvmx_error_add(&info); 3070215976Sjmallett 3071215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3072215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3073215976Sjmallett info.status_mask = 1ull<<52 /* c1_un_bx */; 3074215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3075215976Sjmallett info.enable_mask = 1ull<<52 /* c1_un_bx */; 3076215976Sjmallett info.flags = 0; 3077215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3078215976Sjmallett info.group_index = 1; 3079215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3080215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3081215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3082215976Sjmallett info.func = __cvmx_error_display; 3083215976Sjmallett info.user_info = (long) 3084215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n" 3085215976Sjmallett " Core 1.\n"; 3086215976Sjmallett fail |= cvmx_error_add(&info); 3087215976Sjmallett 3088215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3089215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3090215976Sjmallett info.status_mask = 1ull<<54 /* c1_un_wf */; 3091215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3092215976Sjmallett info.enable_mask = 1ull<<54 /* c1_un_wf */; 3093215976Sjmallett info.flags = 0; 3094215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3095215976Sjmallett info.group_index = 1; 3096215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3097215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3098215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3099215976Sjmallett info.func = __cvmx_error_display; 3100215976Sjmallett info.user_info = (long) 3101215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n" 3102215976Sjmallett " register. Core1.\n"; 3103215976Sjmallett fail |= cvmx_error_add(&info); 3104215976Sjmallett 3105215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3106215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3107215976Sjmallett info.status_mask = 1ull<<51 /* c1_un_wi */; 3108215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3109215976Sjmallett info.enable_mask = 1ull<<51 /* c1_un_wi */; 3110215976Sjmallett info.flags = 0; 3111215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3112215976Sjmallett info.group_index = 1; 3113215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3114215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3115215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3116215976Sjmallett info.func = __cvmx_error_display; 3117215976Sjmallett info.user_info = (long) 3118215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n" 3119215976Sjmallett " Core 1.\n"; 3120215976Sjmallett fail |= cvmx_error_add(&info); 3121215976Sjmallett 3122215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3123215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3124215976Sjmallett info.status_mask = 1ull<<43 /* c1_up_b0 */; 3125215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3126215976Sjmallett info.enable_mask = 1ull<<43 /* c1_up_b0 */; 3127215976Sjmallett info.flags = 0; 3128215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3129215976Sjmallett info.group_index = 1; 3130215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3131215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3132215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3133215976Sjmallett info.func = __cvmx_error_display; 3134215976Sjmallett info.user_info = (long) 3135215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n" 3136215976Sjmallett " Core 1.\n"; 3137215976Sjmallett fail |= cvmx_error_add(&info); 3138215976Sjmallett 3139215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3140215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3141215976Sjmallett info.status_mask = 1ull<<44 /* c1_up_b1 */; 3142215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3143215976Sjmallett info.enable_mask = 1ull<<44 /* c1_up_b1 */; 3144215976Sjmallett info.flags = 0; 3145215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3146215976Sjmallett info.group_index = 1; 3147215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3148215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3149215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3150215976Sjmallett info.func = __cvmx_error_display; 3151215976Sjmallett info.user_info = (long) 3152215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n" 3153215976Sjmallett " Core 1.\n"; 3154215976Sjmallett fail |= cvmx_error_add(&info); 3155215976Sjmallett 3156215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3157215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3158215976Sjmallett info.status_mask = 1ull<<45 /* c1_up_b2 */; 3159215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3160215976Sjmallett info.enable_mask = 1ull<<45 /* c1_up_b2 */; 3161215976Sjmallett info.flags = 0; 3162215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3163215976Sjmallett info.group_index = 1; 3164215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3165215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3166215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3167215976Sjmallett info.func = __cvmx_error_display; 3168215976Sjmallett info.user_info = (long) 3169215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n" 3170215976Sjmallett " Core 1.\n"; 3171215976Sjmallett fail |= cvmx_error_add(&info); 3172215976Sjmallett 3173215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3174215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3175215976Sjmallett info.status_mask = 1ull<<47 /* c1_up_bx */; 3176215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3177215976Sjmallett info.enable_mask = 1ull<<47 /* c1_up_bx */; 3178215976Sjmallett info.flags = 0; 3179215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3180215976Sjmallett info.group_index = 1; 3181215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3182215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3183215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3184215976Sjmallett info.func = __cvmx_error_display; 3185215976Sjmallett info.user_info = (long) 3186215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n" 3187215976Sjmallett " Core 1.\n"; 3188215976Sjmallett fail |= cvmx_error_add(&info); 3189215976Sjmallett 3190215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3191215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3192215976Sjmallett info.status_mask = 1ull<<56 /* c1_up_wf */; 3193215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3194215976Sjmallett info.enable_mask = 1ull<<56 /* c1_up_wf */; 3195215976Sjmallett info.flags = 0; 3196215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3197215976Sjmallett info.group_index = 1; 3198215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3199215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3200215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3201215976Sjmallett info.func = __cvmx_error_display; 3202215976Sjmallett info.user_info = (long) 3203215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n" 3204215976Sjmallett " register. Core1.\n"; 3205215976Sjmallett fail |= cvmx_error_add(&info); 3206215976Sjmallett 3207215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3208215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3209215976Sjmallett info.status_mask = 1ull<<46 /* c1_up_wi */; 3210215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3211215976Sjmallett info.enable_mask = 1ull<<46 /* c1_up_wi */; 3212215976Sjmallett info.flags = 0; 3213215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3214215976Sjmallett info.group_index = 1; 3215215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3216215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3217215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3218215976Sjmallett info.func = __cvmx_error_display; 3219215976Sjmallett info.user_info = (long) 3220215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n" 3221215976Sjmallett " Core 1.\n"; 3222215976Sjmallett fail |= cvmx_error_add(&info); 3223215976Sjmallett 3224215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3225215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3226215976Sjmallett info.status_mask = 1ull<<30 /* c1_wake */; 3227215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3228215976Sjmallett info.enable_mask = 1ull<<30 /* c1_wake */; 3229215976Sjmallett info.flags = 0; 3230215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3231215976Sjmallett info.group_index = 1; 3232215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3233215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3234215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3235215976Sjmallett info.func = __cvmx_error_display; 3236215976Sjmallett info.user_info = (long) 3237215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n" 3238215976Sjmallett " Pcie Core 1. (wake_n)\n" 3239215976Sjmallett " Octeon will never generate this interrupt.\n"; 3240215976Sjmallett fail |= cvmx_error_add(&info); 3241215976Sjmallett 3242215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3243215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3244215976Sjmallett info.status_mask = 1ull<<2 /* bar0_to */; 3245215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3246215976Sjmallett info.enable_mask = 1ull<<2 /* bar0_to */; 3247215976Sjmallett info.flags = 0; 3248215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3249215976Sjmallett info.group_index = 0; 3250215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3251215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3252215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3253215976Sjmallett info.func = __cvmx_error_display; 3254215976Sjmallett info.user_info = (long) 3255215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n" 3256215976Sjmallett " read-data/commit in 0xffff core clocks.\n"; 3257215976Sjmallett fail |= cvmx_error_add(&info); 3258215976Sjmallett 3259215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3260215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3261215976Sjmallett info.status_mask = 1ull<<4 /* dma0dbo */; 3262215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3263215976Sjmallett info.enable_mask = 1ull<<4 /* dma0dbo */; 3264215976Sjmallett info.flags = 0; 3265215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3266215976Sjmallett info.group_index = 0; 3267215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3268215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3269215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3270215976Sjmallett info.func = __cvmx_error_display; 3271215976Sjmallett info.user_info = (long) 3272215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n" 3273215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3274215976Sjmallett fail |= cvmx_error_add(&info); 3275215976Sjmallett 3276215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3277215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3278215976Sjmallett info.status_mask = 1ull<<5 /* dma1dbo */; 3279215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3280215976Sjmallett info.enable_mask = 1ull<<5 /* dma1dbo */; 3281215976Sjmallett info.flags = 0; 3282215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3283215976Sjmallett info.group_index = 0; 3284215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3285215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3286215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3287215976Sjmallett info.func = __cvmx_error_display; 3288215976Sjmallett info.user_info = (long) 3289215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n" 3290215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3291215976Sjmallett fail |= cvmx_error_add(&info); 3292215976Sjmallett 3293215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3294215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3295215976Sjmallett info.status_mask = 1ull<<6 /* dma2dbo */; 3296215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3297215976Sjmallett info.enable_mask = 1ull<<6 /* dma2dbo */; 3298215976Sjmallett info.flags = 0; 3299215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3300215976Sjmallett info.group_index = 0; 3301215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3302215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3303215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3304215976Sjmallett info.func = __cvmx_error_display; 3305215976Sjmallett info.user_info = (long) 3306215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n" 3307215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3308215976Sjmallett fail |= cvmx_error_add(&info); 3309215976Sjmallett 3310215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3311215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3312215976Sjmallett info.status_mask = 1ull<<7 /* dma3dbo */; 3313215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3314215976Sjmallett info.enable_mask = 1ull<<7 /* dma3dbo */; 3315215976Sjmallett info.flags = 0; 3316215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3317215976Sjmallett info.group_index = 0; 3318215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3319215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3320215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3321215976Sjmallett info.func = __cvmx_error_display; 3322215976Sjmallett info.user_info = (long) 3323215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n" 3324215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3325215976Sjmallett fail |= cvmx_error_add(&info); 3326215976Sjmallett 3327215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3328215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3329215976Sjmallett info.status_mask = 1ull<<3 /* iob2big */; 3330215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3331215976Sjmallett info.enable_mask = 1ull<<3 /* iob2big */; 3332215976Sjmallett info.flags = 0; 3333215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3334215976Sjmallett info.group_index = 0; 3335215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3336215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3337215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3338215976Sjmallett info.func = __cvmx_error_display; 3339215976Sjmallett info.user_info = (long) 3340215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n"; 3341215976Sjmallett fail |= cvmx_error_add(&info); 3342215976Sjmallett 3343215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3344215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3345215976Sjmallett info.status_mask = 1ull<<0 /* rml_rto */; 3346215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3347215976Sjmallett info.enable_mask = 1ull<<0 /* rml_rto */; 3348215976Sjmallett info.flags = 0; 3349215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3350215976Sjmallett info.group_index = 0; 3351215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3352215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3353215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3354215976Sjmallett info.func = __cvmx_error_display; 3355215976Sjmallett info.user_info = (long) 3356215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n"; 3357215976Sjmallett fail |= cvmx_error_add(&info); 3358215976Sjmallett 3359215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3360215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3361215976Sjmallett info.status_mask = 1ull<<1 /* rml_wto */; 3362215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3363215976Sjmallett info.enable_mask = 1ull<<1 /* rml_wto */; 3364215976Sjmallett info.flags = 0; 3365215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3366215976Sjmallett info.group_index = 0; 3367215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3368215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3369215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3370215976Sjmallett info.func = __cvmx_error_display; 3371215976Sjmallett info.user_info = (long) 3372215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n"; 3373215976Sjmallett fail |= cvmx_error_add(&info); 3374215976Sjmallett 3375215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3376215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3377215976Sjmallett info.status_mask = 1ull<<8 /* dma4dbo */; 3378215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3379215976Sjmallett info.enable_mask = 1ull<<8 /* dma4dbo */; 3380215976Sjmallett info.flags = 0; 3381215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3382215976Sjmallett info.group_index = 0; 3383215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3384215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3385215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3386215976Sjmallett info.func = __cvmx_error_display; 3387215976Sjmallett info.user_info = (long) 3388215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n" 3389215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3390215976Sjmallett fail |= cvmx_error_add(&info); 3391215976Sjmallett 3392215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3393215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3394215976Sjmallett info.status_mask = 0; 3395215976Sjmallett info.enable_addr = 0; 3396215976Sjmallett info.enable_mask = 0; 3397215976Sjmallett info.flags = 0; 3398215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3399215976Sjmallett info.group_index = 0; 3400215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3401215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3402215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3403215976Sjmallett info.func = __cvmx_error_decode; 3404215976Sjmallett info.user_info = 0; 3405215976Sjmallett fail |= cvmx_error_add(&info); 3406215976Sjmallett 3407215976Sjmallett /* CVMX_PESCX_DBG_INFO(0) */ 3408215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3409215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3410215976Sjmallett info.status_mask = 1ull<<0 /* spoison */; 3411215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3412215976Sjmallett info.enable_mask = 1ull<<0 /* spoison */; 3413215976Sjmallett info.flags = 0; 3414215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3415215976Sjmallett info.group_index = 0; 3416215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3417215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3418215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3419215976Sjmallett info.func = __cvmx_error_display; 3420215976Sjmallett info.user_info = (long) 3421215976Sjmallett "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n" 3422215976Sjmallett " peai__client0_tlp_ep & peai__client0_tlp_hv\n"; 3423215976Sjmallett fail |= cvmx_error_add(&info); 3424215976Sjmallett 3425215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3426215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3427215976Sjmallett info.status_mask = 1ull<<2 /* rtlplle */; 3428215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3429215976Sjmallett info.enable_mask = 1ull<<2 /* rtlplle */; 3430215976Sjmallett info.flags = 0; 3431215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3432215976Sjmallett info.group_index = 0; 3433215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3434215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3435215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3436215976Sjmallett info.func = __cvmx_error_display; 3437215976Sjmallett info.user_info = (long) 3438215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n" 3439215976Sjmallett " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n"; 3440215976Sjmallett fail |= cvmx_error_add(&info); 3441215976Sjmallett 3442215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3443215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3444215976Sjmallett info.status_mask = 1ull<<3 /* recrce */; 3445215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3446215976Sjmallett info.enable_mask = 1ull<<3 /* recrce */; 3447215976Sjmallett info.flags = 0; 3448215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3449215976Sjmallett info.group_index = 0; 3450215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3451215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3452215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3453215976Sjmallett info.func = __cvmx_error_display; 3454215976Sjmallett info.user_info = (long) 3455215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n" 3456215976Sjmallett " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n"; 3457215976Sjmallett fail |= cvmx_error_add(&info); 3458215976Sjmallett 3459215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3460215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3461215976Sjmallett info.status_mask = 1ull<<4 /* rpoison */; 3462215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3463215976Sjmallett info.enable_mask = 1ull<<4 /* rpoison */; 3464215976Sjmallett info.flags = 0; 3465215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3466215976Sjmallett info.group_index = 0; 3467215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3468215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3469215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3470215976Sjmallett info.func = __cvmx_error_display; 3471215976Sjmallett info.user_info = (long) 3472215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n" 3473215976Sjmallett " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n"; 3474215976Sjmallett fail |= cvmx_error_add(&info); 3475215976Sjmallett 3476215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3477215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3478215976Sjmallett info.status_mask = 1ull<<5 /* rcemrc */; 3479215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3480215976Sjmallett info.enable_mask = 1ull<<5 /* rcemrc */; 3481215976Sjmallett info.flags = 0; 3482215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3483215976Sjmallett info.group_index = 0; 3484215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3485215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3486215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3487215976Sjmallett info.func = __cvmx_error_display; 3488215976Sjmallett info.user_info = (long) 3489215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n" 3490215976Sjmallett " pedc_radm_correctable_err\n"; 3491215976Sjmallett fail |= cvmx_error_add(&info); 3492215976Sjmallett 3493215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3494215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3495215976Sjmallett info.status_mask = 1ull<<6 /* rnfemrc */; 3496215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3497215976Sjmallett info.enable_mask = 1ull<<6 /* rnfemrc */; 3498215976Sjmallett info.flags = 0; 3499215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3500215976Sjmallett info.group_index = 0; 3501215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3502215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3503215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3504215976Sjmallett info.func = __cvmx_error_display; 3505215976Sjmallett info.user_info = (long) 3506215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n" 3507215976Sjmallett " pedc_radm_nonfatal_err\n"; 3508215976Sjmallett fail |= cvmx_error_add(&info); 3509215976Sjmallett 3510215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3511215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3512215976Sjmallett info.status_mask = 1ull<<7 /* rfemrc */; 3513215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3514215976Sjmallett info.enable_mask = 1ull<<7 /* rfemrc */; 3515215976Sjmallett info.flags = 0; 3516215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3517215976Sjmallett info.group_index = 0; 3518215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3519215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3520215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3521215976Sjmallett info.func = __cvmx_error_display; 3522215976Sjmallett info.user_info = (long) 3523215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n" 3524215976Sjmallett " pedc_radm_fatal_err\n" 3525215976Sjmallett " Bit set when a message with ERR_FATAL is set.\n"; 3526215976Sjmallett fail |= cvmx_error_add(&info); 3527215976Sjmallett 3528215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3529215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3530215976Sjmallett info.status_mask = 1ull<<8 /* rpmerc */; 3531215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3532215976Sjmallett info.enable_mask = 1ull<<8 /* rpmerc */; 3533215976Sjmallett info.flags = 0; 3534215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3535215976Sjmallett info.group_index = 0; 3536215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3537215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3538215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3539215976Sjmallett info.func = __cvmx_error_display; 3540215976Sjmallett info.user_info = (long) 3541215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n" 3542215976Sjmallett " pedc_radm_pm_pme\n"; 3543215976Sjmallett fail |= cvmx_error_add(&info); 3544215976Sjmallett 3545215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3546215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3547215976Sjmallett info.status_mask = 1ull<<9 /* rptamrc */; 3548215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3549215976Sjmallett info.enable_mask = 1ull<<9 /* rptamrc */; 3550215976Sjmallett info.flags = 0; 3551215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3552215976Sjmallett info.group_index = 0; 3553215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3554215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3555215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3556215976Sjmallett info.func = __cvmx_error_display; 3557215976Sjmallett info.user_info = (long) 3558215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n" 3559215976Sjmallett " (RC Mode only)\n" 3560215976Sjmallett " pedc_radm_pm_to_ack\n"; 3561215976Sjmallett fail |= cvmx_error_add(&info); 3562215976Sjmallett 3563215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3564215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3565215976Sjmallett info.status_mask = 1ull<<10 /* rumep */; 3566215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3567215976Sjmallett info.enable_mask = 1ull<<10 /* rumep */; 3568215976Sjmallett info.flags = 0; 3569215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3570215976Sjmallett info.group_index = 0; 3571215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3572215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3573215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3574215976Sjmallett info.func = __cvmx_error_display; 3575215976Sjmallett info.user_info = (long) 3576215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n" 3577215976Sjmallett " pedc_radm_msg_unlock\n"; 3578215976Sjmallett fail |= cvmx_error_add(&info); 3579215976Sjmallett 3580215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3581215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3582215976Sjmallett info.status_mask = 1ull<<11 /* rvdm */; 3583215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3584215976Sjmallett info.enable_mask = 1ull<<11 /* rvdm */; 3585215976Sjmallett info.flags = 0; 3586215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3587215976Sjmallett info.group_index = 0; 3588215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3589215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3590215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3591215976Sjmallett info.func = __cvmx_error_display; 3592215976Sjmallett info.user_info = (long) 3593215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n" 3594215976Sjmallett " pedc_radm_vendor_msg\n"; 3595215976Sjmallett fail |= cvmx_error_add(&info); 3596215976Sjmallett 3597215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3598215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3599215976Sjmallett info.status_mask = 1ull<<12 /* acto */; 3600215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3601215976Sjmallett info.enable_mask = 1ull<<12 /* acto */; 3602215976Sjmallett info.flags = 0; 3603215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3604215976Sjmallett info.group_index = 0; 3605215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3606215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3607215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3608215976Sjmallett info.func = __cvmx_error_display; 3609215976Sjmallett info.user_info = (long) 3610215976Sjmallett "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n" 3611215976Sjmallett " pedc_radm_cpl_timeout\n"; 3612215976Sjmallett fail |= cvmx_error_add(&info); 3613215976Sjmallett 3614215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3615215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3616215976Sjmallett info.status_mask = 1ull<<13 /* rte */; 3617215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3618215976Sjmallett info.enable_mask = 1ull<<13 /* rte */; 3619215976Sjmallett info.flags = 0; 3620215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3621215976Sjmallett info.group_index = 0; 3622215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3623215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3624215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3625215976Sjmallett info.func = __cvmx_error_display; 3626215976Sjmallett info.user_info = (long) 3627215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n" 3628215976Sjmallett " xdlh_replay_timeout_err\n" 3629215976Sjmallett " This bit is set when the REPLAY_TIMER expires in\n" 3630215976Sjmallett " the PCIE core. The probability of this bit being\n" 3631215976Sjmallett " set will increase with the traffic load.\n"; 3632215976Sjmallett fail |= cvmx_error_add(&info); 3633215976Sjmallett 3634215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3635215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3636215976Sjmallett info.status_mask = 1ull<<14 /* mre */; 3637215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3638215976Sjmallett info.enable_mask = 1ull<<14 /* mre */; 3639215976Sjmallett info.flags = 0; 3640215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3641215976Sjmallett info.group_index = 0; 3642215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3643215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3644215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3645215976Sjmallett info.func = __cvmx_error_display; 3646215976Sjmallett info.user_info = (long) 3647215976Sjmallett "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n" 3648215976Sjmallett " xdlh_replay_num_rlover_err\n"; 3649215976Sjmallett fail |= cvmx_error_add(&info); 3650215976Sjmallett 3651215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3652215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3653215976Sjmallett info.status_mask = 1ull<<15 /* rdwdle */; 3654215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3655215976Sjmallett info.enable_mask = 1ull<<15 /* rdwdle */; 3656215976Sjmallett info.flags = 0; 3657215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3658215976Sjmallett info.group_index = 0; 3659215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3660215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3661215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3662215976Sjmallett info.func = __cvmx_error_display; 3663215976Sjmallett info.user_info = (long) 3664215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n" 3665215976Sjmallett " rdlh_bad_dllp_err\n"; 3666215976Sjmallett fail |= cvmx_error_add(&info); 3667215976Sjmallett 3668215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3669215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3670215976Sjmallett info.status_mask = 1ull<<16 /* rtwdle */; 3671215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3672215976Sjmallett info.enable_mask = 1ull<<16 /* rtwdle */; 3673215976Sjmallett info.flags = 0; 3674215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3675215976Sjmallett info.group_index = 0; 3676215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3677215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3678215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3679215976Sjmallett info.func = __cvmx_error_display; 3680215976Sjmallett info.user_info = (long) 3681215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n" 3682215976Sjmallett " rdlh_bad_tlp_err\n"; 3683215976Sjmallett fail |= cvmx_error_add(&info); 3684215976Sjmallett 3685215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3686215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3687215976Sjmallett info.status_mask = 1ull<<17 /* dpeoosd */; 3688215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3689215976Sjmallett info.enable_mask = 1ull<<17 /* dpeoosd */; 3690215976Sjmallett info.flags = 0; 3691215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3692215976Sjmallett info.group_index = 0; 3693215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3694215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3695215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3696215976Sjmallett info.func = __cvmx_error_display; 3697215976Sjmallett info.user_info = (long) 3698215976Sjmallett "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n" 3699215976Sjmallett " rdlh_prot_err\n"; 3700215976Sjmallett fail |= cvmx_error_add(&info); 3701215976Sjmallett 3702215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3703215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3704215976Sjmallett info.status_mask = 1ull<<18 /* fcpvwt */; 3705215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3706215976Sjmallett info.enable_mask = 1ull<<18 /* fcpvwt */; 3707215976Sjmallett info.flags = 0; 3708215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3709215976Sjmallett info.group_index = 0; 3710215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3711215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3712215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3713215976Sjmallett info.func = __cvmx_error_display; 3714215976Sjmallett info.user_info = (long) 3715215976Sjmallett "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n" 3716215976Sjmallett " rtlh_fc_prot_err\n"; 3717215976Sjmallett fail |= cvmx_error_add(&info); 3718215976Sjmallett 3719215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3720215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3721215976Sjmallett info.status_mask = 1ull<<19 /* rpe */; 3722215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3723215976Sjmallett info.enable_mask = 1ull<<19 /* rpe */; 3724215976Sjmallett info.flags = 0; 3725215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3726215976Sjmallett info.group_index = 0; 3727215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3728215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3729215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3730215976Sjmallett info.func = __cvmx_error_display; 3731215976Sjmallett info.user_info = (long) 3732215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n" 3733215976Sjmallett " (RxStatus = 3b100) or disparity error\n" 3734215976Sjmallett " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n" 3735215976Sjmallett " be asserted.\n" 3736215976Sjmallett " rmlh_rcvd_err\n"; 3737215976Sjmallett fail |= cvmx_error_add(&info); 3738215976Sjmallett 3739215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3740215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3741215976Sjmallett info.status_mask = 1ull<<20 /* fcuv */; 3742215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3743215976Sjmallett info.enable_mask = 1ull<<20 /* fcuv */; 3744215976Sjmallett info.flags = 0; 3745215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3746215976Sjmallett info.group_index = 0; 3747215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3748215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3749215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3750215976Sjmallett info.func = __cvmx_error_display; 3751215976Sjmallett info.user_info = (long) 3752215976Sjmallett "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n" 3753215976Sjmallett " int_xadm_fc_prot_err\n"; 3754215976Sjmallett fail |= cvmx_error_add(&info); 3755215976Sjmallett 3756215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3757215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3758215976Sjmallett info.status_mask = 1ull<<21 /* rqo */; 3759215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3760215976Sjmallett info.enable_mask = 1ull<<21 /* rqo */; 3761215976Sjmallett info.flags = 0; 3762215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3763215976Sjmallett info.group_index = 0; 3764215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3765215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3766215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3767215976Sjmallett info.func = __cvmx_error_display; 3768215976Sjmallett info.user_info = (long) 3769215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n" 3770215976Sjmallett " flow control advertisements are ignored\n" 3771215976Sjmallett " radm_qoverflow\n"; 3772215976Sjmallett fail |= cvmx_error_add(&info); 3773215976Sjmallett 3774215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3775215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3776215976Sjmallett info.status_mask = 1ull<<22 /* rauc */; 3777215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3778215976Sjmallett info.enable_mask = 1ull<<22 /* rauc */; 3779215976Sjmallett info.flags = 0; 3780215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3781215976Sjmallett info.group_index = 0; 3782215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3783215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3784215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3785215976Sjmallett info.func = __cvmx_error_display; 3786215976Sjmallett info.user_info = (long) 3787215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n" 3788215976Sjmallett " radm_unexp_cpl_err\n"; 3789215976Sjmallett fail |= cvmx_error_add(&info); 3790215976Sjmallett 3791215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3792215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3793215976Sjmallett info.status_mask = 1ull<<23 /* racur */; 3794215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3795215976Sjmallett info.enable_mask = 1ull<<23 /* racur */; 3796215976Sjmallett info.flags = 0; 3797215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3798215976Sjmallett info.group_index = 0; 3799215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3800215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3801215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3802215976Sjmallett info.func = __cvmx_error_display; 3803215976Sjmallett info.user_info = (long) 3804215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n" 3805215976Sjmallett " radm_rcvd_cpl_ur\n"; 3806215976Sjmallett fail |= cvmx_error_add(&info); 3807215976Sjmallett 3808215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3809215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3810215976Sjmallett info.status_mask = 1ull<<24 /* racca */; 3811215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3812215976Sjmallett info.enable_mask = 1ull<<24 /* racca */; 3813215976Sjmallett info.flags = 0; 3814215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3815215976Sjmallett info.group_index = 0; 3816215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3817215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3818215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3819215976Sjmallett info.func = __cvmx_error_display; 3820215976Sjmallett info.user_info = (long) 3821215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n" 3822215976Sjmallett " radm_rcvd_cpl_ca\n"; 3823215976Sjmallett fail |= cvmx_error_add(&info); 3824215976Sjmallett 3825215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3826215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3827215976Sjmallett info.status_mask = 1ull<<25 /* caar */; 3828215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3829215976Sjmallett info.enable_mask = 1ull<<25 /* caar */; 3830215976Sjmallett info.flags = 0; 3831215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3832215976Sjmallett info.group_index = 0; 3833215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3834215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3835215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3836215976Sjmallett info.func = __cvmx_error_display; 3837215976Sjmallett info.user_info = (long) 3838215976Sjmallett "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n" 3839215976Sjmallett " radm_rcvd_ca_req\n" 3840215976Sjmallett " This bit will never be set because Octeon does\n" 3841215976Sjmallett " not generate Completer Aborts.\n"; 3842215976Sjmallett fail |= cvmx_error_add(&info); 3843215976Sjmallett 3844215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3845215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3846215976Sjmallett info.status_mask = 1ull<<26 /* rarwdns */; 3847215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3848215976Sjmallett info.enable_mask = 1ull<<26 /* rarwdns */; 3849215976Sjmallett info.flags = 0; 3850215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3851215976Sjmallett info.group_index = 0; 3852215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3853215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3854215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3855215976Sjmallett info.func = __cvmx_error_display; 3856215976Sjmallett info.user_info = (long) 3857215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n" 3858215976Sjmallett " radm_rcvd_ur_req\n"; 3859215976Sjmallett fail |= cvmx_error_add(&info); 3860215976Sjmallett 3861215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3862215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3863215976Sjmallett info.status_mask = 1ull<<27 /* ramtlp */; 3864215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3865215976Sjmallett info.enable_mask = 1ull<<27 /* ramtlp */; 3866215976Sjmallett info.flags = 0; 3867215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3868215976Sjmallett info.group_index = 0; 3869215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3870215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3871215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3872215976Sjmallett info.func = __cvmx_error_display; 3873215976Sjmallett info.user_info = (long) 3874215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n" 3875215976Sjmallett " radm_mlf_tlp_err\n"; 3876215976Sjmallett fail |= cvmx_error_add(&info); 3877215976Sjmallett 3878215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3879215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3880215976Sjmallett info.status_mask = 1ull<<28 /* racpp */; 3881215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3882215976Sjmallett info.enable_mask = 1ull<<28 /* racpp */; 3883215976Sjmallett info.flags = 0; 3884215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3885215976Sjmallett info.group_index = 0; 3886215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3887215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3888215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3889215976Sjmallett info.func = __cvmx_error_display; 3890215976Sjmallett info.user_info = (long) 3891215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n" 3892215976Sjmallett " radm_rcvd_cpl_poisoned\n"; 3893215976Sjmallett fail |= cvmx_error_add(&info); 3894215976Sjmallett 3895215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3896215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3897215976Sjmallett info.status_mask = 1ull<<29 /* rawwpp */; 3898215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3899215976Sjmallett info.enable_mask = 1ull<<29 /* rawwpp */; 3900215976Sjmallett info.flags = 0; 3901215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3902215976Sjmallett info.group_index = 0; 3903215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3904215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3905215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3906215976Sjmallett info.func = __cvmx_error_display; 3907215976Sjmallett info.user_info = (long) 3908215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n" 3909215976Sjmallett " radm_rcvd_wreq_poisoned\n"; 3910215976Sjmallett fail |= cvmx_error_add(&info); 3911215976Sjmallett 3912215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3913215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3914215976Sjmallett info.status_mask = 1ull<<30 /* ecrc_e */; 3915215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3916215976Sjmallett info.enable_mask = 1ull<<30 /* ecrc_e */; 3917215976Sjmallett info.flags = 0; 3918215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3919215976Sjmallett info.group_index = 0; 3920215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3921215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3922215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3923215976Sjmallett info.func = __cvmx_error_display; 3924215976Sjmallett info.user_info = (long) 3925215976Sjmallett "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n" 3926215976Sjmallett " radm_ecrc_err\n"; 3927215976Sjmallett fail |= cvmx_error_add(&info); 3928215976Sjmallett 3929215976Sjmallett /* CVMX_PESCX_DBG_INFO(1) */ 3930215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3931215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 3932215976Sjmallett info.status_mask = 1ull<<0 /* spoison */; 3933215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 3934215976Sjmallett info.enable_mask = 1ull<<0 /* spoison */; 3935215976Sjmallett info.flags = 0; 3936215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3937215976Sjmallett info.group_index = 1; 3938215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3939215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3940215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 3941215976Sjmallett info.func = __cvmx_error_display; 3942215976Sjmallett info.user_info = (long) 3943215976Sjmallett "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n" 3944215976Sjmallett " peai__client0_tlp_ep & peai__client0_tlp_hv\n"; 3945215976Sjmallett fail |= cvmx_error_add(&info); 3946215976Sjmallett 3947215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3948215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 3949215976Sjmallett info.status_mask = 1ull<<2 /* rtlplle */; 3950215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 3951215976Sjmallett info.enable_mask = 1ull<<2 /* rtlplle */; 3952215976Sjmallett info.flags = 0; 3953215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3954215976Sjmallett info.group_index = 1; 3955215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3956215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3957215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 3958215976Sjmallett info.func = __cvmx_error_display; 3959215976Sjmallett info.user_info = (long) 3960215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n" 3961215976Sjmallett " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n"; 3962215976Sjmallett fail |= cvmx_error_add(&info); 3963215976Sjmallett 3964215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3965215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 3966215976Sjmallett info.status_mask = 1ull<<3 /* recrce */; 3967215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 3968215976Sjmallett info.enable_mask = 1ull<<3 /* recrce */; 3969215976Sjmallett info.flags = 0; 3970215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3971215976Sjmallett info.group_index = 1; 3972215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3973215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3974215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 3975215976Sjmallett info.func = __cvmx_error_display; 3976215976Sjmallett info.user_info = (long) 3977215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n" 3978215976Sjmallett " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n"; 3979215976Sjmallett fail |= cvmx_error_add(&info); 3980215976Sjmallett 3981215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3982215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 3983215976Sjmallett info.status_mask = 1ull<<4 /* rpoison */; 3984215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 3985215976Sjmallett info.enable_mask = 1ull<<4 /* rpoison */; 3986215976Sjmallett info.flags = 0; 3987215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3988215976Sjmallett info.group_index = 1; 3989215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3990215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3991215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 3992215976Sjmallett info.func = __cvmx_error_display; 3993215976Sjmallett info.user_info = (long) 3994215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n" 3995215976Sjmallett " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n"; 3996215976Sjmallett fail |= cvmx_error_add(&info); 3997215976Sjmallett 3998215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3999215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4000215976Sjmallett info.status_mask = 1ull<<5 /* rcemrc */; 4001215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4002215976Sjmallett info.enable_mask = 1ull<<5 /* rcemrc */; 4003215976Sjmallett info.flags = 0; 4004215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4005215976Sjmallett info.group_index = 1; 4006215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4007215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4008215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4009215976Sjmallett info.func = __cvmx_error_display; 4010215976Sjmallett info.user_info = (long) 4011215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n" 4012215976Sjmallett " pedc_radm_correctable_err\n"; 4013215976Sjmallett fail |= cvmx_error_add(&info); 4014215976Sjmallett 4015215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4016215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4017215976Sjmallett info.status_mask = 1ull<<6 /* rnfemrc */; 4018215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4019215976Sjmallett info.enable_mask = 1ull<<6 /* rnfemrc */; 4020215976Sjmallett info.flags = 0; 4021215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4022215976Sjmallett info.group_index = 1; 4023215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4024215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4025215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4026215976Sjmallett info.func = __cvmx_error_display; 4027215976Sjmallett info.user_info = (long) 4028215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n" 4029215976Sjmallett " pedc_radm_nonfatal_err\n"; 4030215976Sjmallett fail |= cvmx_error_add(&info); 4031215976Sjmallett 4032215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4033215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4034215976Sjmallett info.status_mask = 1ull<<7 /* rfemrc */; 4035215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4036215976Sjmallett info.enable_mask = 1ull<<7 /* rfemrc */; 4037215976Sjmallett info.flags = 0; 4038215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4039215976Sjmallett info.group_index = 1; 4040215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4041215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4042215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4043215976Sjmallett info.func = __cvmx_error_display; 4044215976Sjmallett info.user_info = (long) 4045215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n" 4046215976Sjmallett " pedc_radm_fatal_err\n" 4047215976Sjmallett " Bit set when a message with ERR_FATAL is set.\n"; 4048215976Sjmallett fail |= cvmx_error_add(&info); 4049215976Sjmallett 4050215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4051215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4052215976Sjmallett info.status_mask = 1ull<<8 /* rpmerc */; 4053215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4054215976Sjmallett info.enable_mask = 1ull<<8 /* rpmerc */; 4055215976Sjmallett info.flags = 0; 4056215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4057215976Sjmallett info.group_index = 1; 4058215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4059215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4060215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4061215976Sjmallett info.func = __cvmx_error_display; 4062215976Sjmallett info.user_info = (long) 4063215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n" 4064215976Sjmallett " pedc_radm_pm_pme\n"; 4065215976Sjmallett fail |= cvmx_error_add(&info); 4066215976Sjmallett 4067215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4068215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4069215976Sjmallett info.status_mask = 1ull<<9 /* rptamrc */; 4070215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4071215976Sjmallett info.enable_mask = 1ull<<9 /* rptamrc */; 4072215976Sjmallett info.flags = 0; 4073215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4074215976Sjmallett info.group_index = 1; 4075215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4076215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4077215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4078215976Sjmallett info.func = __cvmx_error_display; 4079215976Sjmallett info.user_info = (long) 4080215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n" 4081215976Sjmallett " (RC Mode only)\n" 4082215976Sjmallett " pedc_radm_pm_to_ack\n"; 4083215976Sjmallett fail |= cvmx_error_add(&info); 4084215976Sjmallett 4085215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4086215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4087215976Sjmallett info.status_mask = 1ull<<10 /* rumep */; 4088215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4089215976Sjmallett info.enable_mask = 1ull<<10 /* rumep */; 4090215976Sjmallett info.flags = 0; 4091215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4092215976Sjmallett info.group_index = 1; 4093215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4094215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4095215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4096215976Sjmallett info.func = __cvmx_error_display; 4097215976Sjmallett info.user_info = (long) 4098215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n" 4099215976Sjmallett " pedc_radm_msg_unlock\n"; 4100215976Sjmallett fail |= cvmx_error_add(&info); 4101215976Sjmallett 4102215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4103215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4104215976Sjmallett info.status_mask = 1ull<<11 /* rvdm */; 4105215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4106215976Sjmallett info.enable_mask = 1ull<<11 /* rvdm */; 4107215976Sjmallett info.flags = 0; 4108215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4109215976Sjmallett info.group_index = 1; 4110215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4111215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4112215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4113215976Sjmallett info.func = __cvmx_error_display; 4114215976Sjmallett info.user_info = (long) 4115215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n" 4116215976Sjmallett " pedc_radm_vendor_msg\n"; 4117215976Sjmallett fail |= cvmx_error_add(&info); 4118215976Sjmallett 4119215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4120215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4121215976Sjmallett info.status_mask = 1ull<<12 /* acto */; 4122215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4123215976Sjmallett info.enable_mask = 1ull<<12 /* acto */; 4124215976Sjmallett info.flags = 0; 4125215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4126215976Sjmallett info.group_index = 1; 4127215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4128215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4129215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4130215976Sjmallett info.func = __cvmx_error_display; 4131215976Sjmallett info.user_info = (long) 4132215976Sjmallett "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n" 4133215976Sjmallett " pedc_radm_cpl_timeout\n"; 4134215976Sjmallett fail |= cvmx_error_add(&info); 4135215976Sjmallett 4136215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4137215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4138215976Sjmallett info.status_mask = 1ull<<13 /* rte */; 4139215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4140215976Sjmallett info.enable_mask = 1ull<<13 /* rte */; 4141215976Sjmallett info.flags = 0; 4142215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4143215976Sjmallett info.group_index = 1; 4144215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4145215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4146215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4147215976Sjmallett info.func = __cvmx_error_display; 4148215976Sjmallett info.user_info = (long) 4149215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n" 4150215976Sjmallett " xdlh_replay_timeout_err\n" 4151215976Sjmallett " This bit is set when the REPLAY_TIMER expires in\n" 4152215976Sjmallett " the PCIE core. The probability of this bit being\n" 4153215976Sjmallett " set will increase with the traffic load.\n"; 4154215976Sjmallett fail |= cvmx_error_add(&info); 4155215976Sjmallett 4156215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4157215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4158215976Sjmallett info.status_mask = 1ull<<14 /* mre */; 4159215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4160215976Sjmallett info.enable_mask = 1ull<<14 /* mre */; 4161215976Sjmallett info.flags = 0; 4162215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4163215976Sjmallett info.group_index = 1; 4164215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4165215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4166215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4167215976Sjmallett info.func = __cvmx_error_display; 4168215976Sjmallett info.user_info = (long) 4169215976Sjmallett "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n" 4170215976Sjmallett " xdlh_replay_num_rlover_err\n"; 4171215976Sjmallett fail |= cvmx_error_add(&info); 4172215976Sjmallett 4173215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4174215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4175215976Sjmallett info.status_mask = 1ull<<15 /* rdwdle */; 4176215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4177215976Sjmallett info.enable_mask = 1ull<<15 /* rdwdle */; 4178215976Sjmallett info.flags = 0; 4179215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4180215976Sjmallett info.group_index = 1; 4181215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4182215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4183215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4184215976Sjmallett info.func = __cvmx_error_display; 4185215976Sjmallett info.user_info = (long) 4186215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n" 4187215976Sjmallett " rdlh_bad_dllp_err\n"; 4188215976Sjmallett fail |= cvmx_error_add(&info); 4189215976Sjmallett 4190215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4191215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4192215976Sjmallett info.status_mask = 1ull<<16 /* rtwdle */; 4193215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4194215976Sjmallett info.enable_mask = 1ull<<16 /* rtwdle */; 4195215976Sjmallett info.flags = 0; 4196215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4197215976Sjmallett info.group_index = 1; 4198215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4199215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4200215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4201215976Sjmallett info.func = __cvmx_error_display; 4202215976Sjmallett info.user_info = (long) 4203215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n" 4204215976Sjmallett " rdlh_bad_tlp_err\n"; 4205215976Sjmallett fail |= cvmx_error_add(&info); 4206215976Sjmallett 4207215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4208215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4209215976Sjmallett info.status_mask = 1ull<<17 /* dpeoosd */; 4210215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4211215976Sjmallett info.enable_mask = 1ull<<17 /* dpeoosd */; 4212215976Sjmallett info.flags = 0; 4213215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4214215976Sjmallett info.group_index = 1; 4215215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4216215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4217215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4218215976Sjmallett info.func = __cvmx_error_display; 4219215976Sjmallett info.user_info = (long) 4220215976Sjmallett "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n" 4221215976Sjmallett " rdlh_prot_err\n"; 4222215976Sjmallett fail |= cvmx_error_add(&info); 4223215976Sjmallett 4224215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4225215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4226215976Sjmallett info.status_mask = 1ull<<18 /* fcpvwt */; 4227215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4228215976Sjmallett info.enable_mask = 1ull<<18 /* fcpvwt */; 4229215976Sjmallett info.flags = 0; 4230215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4231215976Sjmallett info.group_index = 1; 4232215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4233215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4234215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4235215976Sjmallett info.func = __cvmx_error_display; 4236215976Sjmallett info.user_info = (long) 4237215976Sjmallett "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n" 4238215976Sjmallett " rtlh_fc_prot_err\n"; 4239215976Sjmallett fail |= cvmx_error_add(&info); 4240215976Sjmallett 4241215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4242215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4243215976Sjmallett info.status_mask = 1ull<<19 /* rpe */; 4244215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4245215976Sjmallett info.enable_mask = 1ull<<19 /* rpe */; 4246215976Sjmallett info.flags = 0; 4247215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4248215976Sjmallett info.group_index = 1; 4249215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4250215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4251215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4252215976Sjmallett info.func = __cvmx_error_display; 4253215976Sjmallett info.user_info = (long) 4254215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n" 4255215976Sjmallett " (RxStatus = 3b100) or disparity error\n" 4256215976Sjmallett " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n" 4257215976Sjmallett " be asserted.\n" 4258215976Sjmallett " rmlh_rcvd_err\n"; 4259215976Sjmallett fail |= cvmx_error_add(&info); 4260215976Sjmallett 4261215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4262215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4263215976Sjmallett info.status_mask = 1ull<<20 /* fcuv */; 4264215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4265215976Sjmallett info.enable_mask = 1ull<<20 /* fcuv */; 4266215976Sjmallett info.flags = 0; 4267215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4268215976Sjmallett info.group_index = 1; 4269215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4270215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4271215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4272215976Sjmallett info.func = __cvmx_error_display; 4273215976Sjmallett info.user_info = (long) 4274215976Sjmallett "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n" 4275215976Sjmallett " int_xadm_fc_prot_err\n"; 4276215976Sjmallett fail |= cvmx_error_add(&info); 4277215976Sjmallett 4278215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4279215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4280215976Sjmallett info.status_mask = 1ull<<21 /* rqo */; 4281215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4282215976Sjmallett info.enable_mask = 1ull<<21 /* rqo */; 4283215976Sjmallett info.flags = 0; 4284215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4285215976Sjmallett info.group_index = 1; 4286215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4287215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4288215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4289215976Sjmallett info.func = __cvmx_error_display; 4290215976Sjmallett info.user_info = (long) 4291215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n" 4292215976Sjmallett " flow control advertisements are ignored\n" 4293215976Sjmallett " radm_qoverflow\n"; 4294215976Sjmallett fail |= cvmx_error_add(&info); 4295215976Sjmallett 4296215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4297215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4298215976Sjmallett info.status_mask = 1ull<<22 /* rauc */; 4299215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4300215976Sjmallett info.enable_mask = 1ull<<22 /* rauc */; 4301215976Sjmallett info.flags = 0; 4302215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4303215976Sjmallett info.group_index = 1; 4304215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4305215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4306215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4307215976Sjmallett info.func = __cvmx_error_display; 4308215976Sjmallett info.user_info = (long) 4309215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n" 4310215976Sjmallett " radm_unexp_cpl_err\n"; 4311215976Sjmallett fail |= cvmx_error_add(&info); 4312215976Sjmallett 4313215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4314215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4315215976Sjmallett info.status_mask = 1ull<<23 /* racur */; 4316215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4317215976Sjmallett info.enable_mask = 1ull<<23 /* racur */; 4318215976Sjmallett info.flags = 0; 4319215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4320215976Sjmallett info.group_index = 1; 4321215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4322215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4323215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4324215976Sjmallett info.func = __cvmx_error_display; 4325215976Sjmallett info.user_info = (long) 4326215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n" 4327215976Sjmallett " radm_rcvd_cpl_ur\n"; 4328215976Sjmallett fail |= cvmx_error_add(&info); 4329215976Sjmallett 4330215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4331215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4332215976Sjmallett info.status_mask = 1ull<<24 /* racca */; 4333215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4334215976Sjmallett info.enable_mask = 1ull<<24 /* racca */; 4335215976Sjmallett info.flags = 0; 4336215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4337215976Sjmallett info.group_index = 1; 4338215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4339215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4340215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4341215976Sjmallett info.func = __cvmx_error_display; 4342215976Sjmallett info.user_info = (long) 4343215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n" 4344215976Sjmallett " radm_rcvd_cpl_ca\n"; 4345215976Sjmallett fail |= cvmx_error_add(&info); 4346215976Sjmallett 4347215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4348215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4349215976Sjmallett info.status_mask = 1ull<<25 /* caar */; 4350215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4351215976Sjmallett info.enable_mask = 1ull<<25 /* caar */; 4352215976Sjmallett info.flags = 0; 4353215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4354215976Sjmallett info.group_index = 1; 4355215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4356215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4357215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4358215976Sjmallett info.func = __cvmx_error_display; 4359215976Sjmallett info.user_info = (long) 4360215976Sjmallett "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n" 4361215976Sjmallett " radm_rcvd_ca_req\n" 4362215976Sjmallett " This bit will never be set because Octeon does\n" 4363215976Sjmallett " not generate Completer Aborts.\n"; 4364215976Sjmallett fail |= cvmx_error_add(&info); 4365215976Sjmallett 4366215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4367215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4368215976Sjmallett info.status_mask = 1ull<<26 /* rarwdns */; 4369215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4370215976Sjmallett info.enable_mask = 1ull<<26 /* rarwdns */; 4371215976Sjmallett info.flags = 0; 4372215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4373215976Sjmallett info.group_index = 1; 4374215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4375215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4376215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4377215976Sjmallett info.func = __cvmx_error_display; 4378215976Sjmallett info.user_info = (long) 4379215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n" 4380215976Sjmallett " radm_rcvd_ur_req\n"; 4381215976Sjmallett fail |= cvmx_error_add(&info); 4382215976Sjmallett 4383215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4384215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4385215976Sjmallett info.status_mask = 1ull<<27 /* ramtlp */; 4386215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4387215976Sjmallett info.enable_mask = 1ull<<27 /* ramtlp */; 4388215976Sjmallett info.flags = 0; 4389215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4390215976Sjmallett info.group_index = 1; 4391215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4392215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4393215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4394215976Sjmallett info.func = __cvmx_error_display; 4395215976Sjmallett info.user_info = (long) 4396215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n" 4397215976Sjmallett " radm_mlf_tlp_err\n"; 4398215976Sjmallett fail |= cvmx_error_add(&info); 4399215976Sjmallett 4400215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4401215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4402215976Sjmallett info.status_mask = 1ull<<28 /* racpp */; 4403215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4404215976Sjmallett info.enable_mask = 1ull<<28 /* racpp */; 4405215976Sjmallett info.flags = 0; 4406215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4407215976Sjmallett info.group_index = 1; 4408215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4409215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4410215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4411215976Sjmallett info.func = __cvmx_error_display; 4412215976Sjmallett info.user_info = (long) 4413215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n" 4414215976Sjmallett " radm_rcvd_cpl_poisoned\n"; 4415215976Sjmallett fail |= cvmx_error_add(&info); 4416215976Sjmallett 4417215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4418215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4419215976Sjmallett info.status_mask = 1ull<<29 /* rawwpp */; 4420215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4421215976Sjmallett info.enable_mask = 1ull<<29 /* rawwpp */; 4422215976Sjmallett info.flags = 0; 4423215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4424215976Sjmallett info.group_index = 1; 4425215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4426215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4427215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4428215976Sjmallett info.func = __cvmx_error_display; 4429215976Sjmallett info.user_info = (long) 4430215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n" 4431215976Sjmallett " radm_rcvd_wreq_poisoned\n"; 4432215976Sjmallett fail |= cvmx_error_add(&info); 4433215976Sjmallett 4434215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4435215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4436215976Sjmallett info.status_mask = 1ull<<30 /* ecrc_e */; 4437215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4438215976Sjmallett info.enable_mask = 1ull<<30 /* ecrc_e */; 4439215976Sjmallett info.flags = 0; 4440215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4441215976Sjmallett info.group_index = 1; 4442215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4443215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4444215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4445215976Sjmallett info.func = __cvmx_error_display; 4446215976Sjmallett info.user_info = (long) 4447215976Sjmallett "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n" 4448215976Sjmallett " radm_ecrc_err\n"; 4449215976Sjmallett fail |= cvmx_error_add(&info); 4450215976Sjmallett 4451215976Sjmallett /* CVMX_RAD_REG_ERROR */ 4452215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4453215976Sjmallett info.status_addr = CVMX_RAD_REG_ERROR; 4454215976Sjmallett info.status_mask = 1ull<<0 /* doorbell */; 4455215976Sjmallett info.enable_addr = CVMX_RAD_REG_INT_MASK; 4456215976Sjmallett info.enable_mask = 1ull<<0 /* doorbell */; 4457215976Sjmallett info.flags = 0; 4458215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4459215976Sjmallett info.group_index = 0; 4460215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4461215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4462215976Sjmallett info.parent.status_mask = 1ull<<14 /* rad */; 4463215976Sjmallett info.func = __cvmx_error_display; 4464215976Sjmallett info.user_info = (long) 4465215976Sjmallett "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 4466215976Sjmallett fail |= cvmx_error_add(&info); 4467215976Sjmallett 4468215976Sjmallett /* CVMX_LMCX_MEM_CFG0(1) */ 4469215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4470215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(1); 4471215976Sjmallett info.status_mask = 0xfull<<21 /* sec_err */; 4472215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(1); 4473215976Sjmallett info.enable_mask = 1ull<<19 /* intr_sec_ena */; 4474215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 4475215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 4476215976Sjmallett info.group_index = 1; 4477215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4478215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4479215976Sjmallett info.parent.status_mask = 1ull<<29 /* lmc1 */; 4480215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err; 4481215976Sjmallett info.user_info = (long) 4482215976Sjmallett "ERROR LMCX_MEM_CFG0(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n" 4483215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 4484215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 4485215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 4486215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 4487215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 4488215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 4489215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 4490215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 4491215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 4492215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 4493215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 4494215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4495215976Sjmallett fail |= cvmx_error_add(&info); 4496215976Sjmallett 4497215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4498215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(1); 4499215976Sjmallett info.status_mask = 0xfull<<25 /* ded_err */; 4500215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(1); 4501215976Sjmallett info.enable_mask = 1ull<<20 /* intr_ded_ena */; 4502215976Sjmallett info.flags = 0; 4503215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 4504215976Sjmallett info.group_index = 1; 4505215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4506215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4507215976Sjmallett info.parent.status_mask = 1ull<<29 /* lmc1 */; 4508215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err; 4509215976Sjmallett info.user_info = (long) 4510215976Sjmallett "ERROR LMCX_MEM_CFG0(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n" 4511215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 4512215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 4513215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 4514215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 4515215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 4516215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 4517215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 4518215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 4519215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 4520215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 4521215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 4522215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4523215976Sjmallett fail |= cvmx_error_add(&info); 4524215976Sjmallett 4525215976Sjmallett /* CVMX_PCSX_INTX_REG(0,1) */ 4526215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4527215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4528215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 4529215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4530215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 4531215976Sjmallett info.flags = 0; 4532215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4533215976Sjmallett info.group_index = 16; 4534215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4535215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4536215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4537215976Sjmallett info.func = __cvmx_error_display; 4538215976Sjmallett info.user_info = (long) 4539215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n"; 4540215976Sjmallett fail |= cvmx_error_add(&info); 4541215976Sjmallett 4542215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4543215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4544215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 4545215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4546215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 4547215976Sjmallett info.flags = 0; 4548215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4549215976Sjmallett info.group_index = 16; 4550215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4551215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4552215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4553215976Sjmallett info.func = __cvmx_error_display; 4554215976Sjmallett info.user_info = (long) 4555215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 4556215976Sjmallett " condition\n"; 4557215976Sjmallett fail |= cvmx_error_add(&info); 4558215976Sjmallett 4559215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4560215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4561215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 4562215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4563215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 4564215976Sjmallett info.flags = 0; 4565215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4566215976Sjmallett info.group_index = 16; 4567215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4568215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4569215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4570215976Sjmallett info.func = __cvmx_error_display; 4571215976Sjmallett info.user_info = (long) 4572215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 4573215976Sjmallett " condition\n"; 4574215976Sjmallett fail |= cvmx_error_add(&info); 4575215976Sjmallett 4576215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4577215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4578215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 4579215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4580215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 4581215976Sjmallett info.flags = 0; 4582215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4583215976Sjmallett info.group_index = 16; 4584215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4585215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4586215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4587215976Sjmallett info.func = __cvmx_error_display; 4588215976Sjmallett info.user_info = (long) 4589215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 4590215976Sjmallett " state. Should never be set during normal operation\n"; 4591215976Sjmallett fail |= cvmx_error_add(&info); 4592215976Sjmallett 4593215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4594215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4595215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 4596215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4597215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 4598215976Sjmallett info.flags = 0; 4599215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4600215976Sjmallett info.group_index = 16; 4601215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4602215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4603215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4604215976Sjmallett info.func = __cvmx_error_display; 4605215976Sjmallett info.user_info = (long) 4606215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 4607215976Sjmallett " state. Should never be set during normal operation\n"; 4608215976Sjmallett fail |= cvmx_error_add(&info); 4609215976Sjmallett 4610215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4611215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4612215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 4613215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4614215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 4615215976Sjmallett info.flags = 0; 4616215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4617215976Sjmallett info.group_index = 16; 4618215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4619215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4620215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4621215976Sjmallett info.func = __cvmx_error_display; 4622215976Sjmallett info.user_info = (long) 4623215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 4624215976Sjmallett " failure occurs\n" 4625215976Sjmallett " Cannot fire in loopback1 mode\n"; 4626215976Sjmallett fail |= cvmx_error_add(&info); 4627215976Sjmallett 4628215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4629215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4630215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 4631215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4632215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 4633215976Sjmallett info.flags = 0; 4634215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4635215976Sjmallett info.group_index = 16; 4636215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4637215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4638215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4639215976Sjmallett info.func = __cvmx_error_display; 4640215976Sjmallett info.user_info = (long) 4641215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 4642215976Sjmallett " state. Should never be set during normal operation\n"; 4643215976Sjmallett fail |= cvmx_error_add(&info); 4644215976Sjmallett 4645215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4646215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4647215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 4648215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4649215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 4650215976Sjmallett info.flags = 0; 4651215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4652215976Sjmallett info.group_index = 16; 4653215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4654215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4655215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4656215976Sjmallett info.func = __cvmx_error_display; 4657215976Sjmallett info.user_info = (long) 4658215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 4659215976Sjmallett " state. Should never be set during normal operation\n"; 4660215976Sjmallett fail |= cvmx_error_add(&info); 4661215976Sjmallett 4662215976Sjmallett /* CVMX_PCSX_INTX_REG(1,1) */ 4663215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4664215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 4665215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 4666215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 4667215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 4668215976Sjmallett info.flags = 0; 4669215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4670215976Sjmallett info.group_index = 17; 4671215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4672215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4673215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4674215976Sjmallett info.func = __cvmx_error_display; 4675215976Sjmallett info.user_info = (long) 4676215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n"; 4677215976Sjmallett fail |= cvmx_error_add(&info); 4678215976Sjmallett 4679215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4680215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 4681215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 4682215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 4683215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 4684215976Sjmallett info.flags = 0; 4685215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4686215976Sjmallett info.group_index = 17; 4687215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4688215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4689215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4690215976Sjmallett info.func = __cvmx_error_display; 4691215976Sjmallett info.user_info = (long) 4692215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 4693215976Sjmallett " condition\n"; 4694215976Sjmallett fail |= cvmx_error_add(&info); 4695215976Sjmallett 4696215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4697215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 4698215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 4699215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 4700215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 4701215976Sjmallett info.flags = 0; 4702215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4703215976Sjmallett info.group_index = 17; 4704215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4705215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4706215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4707215976Sjmallett info.func = __cvmx_error_display; 4708215976Sjmallett info.user_info = (long) 4709215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 4710215976Sjmallett " condition\n"; 4711215976Sjmallett fail |= cvmx_error_add(&info); 4712215976Sjmallett 4713215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4714215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 4715215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 4716215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 4717215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 4718215976Sjmallett info.flags = 0; 4719215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4720215976Sjmallett info.group_index = 17; 4721215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4722215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4723215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4724215976Sjmallett info.func = __cvmx_error_display; 4725215976Sjmallett info.user_info = (long) 4726215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 4727215976Sjmallett " state. Should never be set during normal operation\n"; 4728215976Sjmallett fail |= cvmx_error_add(&info); 4729215976Sjmallett 4730215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4731215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 4732215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 4733215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 4734215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 4735215976Sjmallett info.flags = 0; 4736215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4737215976Sjmallett info.group_index = 17; 4738215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4739215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4740215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4741215976Sjmallett info.func = __cvmx_error_display; 4742215976Sjmallett info.user_info = (long) 4743215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 4744215976Sjmallett " state. Should never be set during normal operation\n"; 4745215976Sjmallett fail |= cvmx_error_add(&info); 4746215976Sjmallett 4747215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4748215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 4749215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 4750215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 4751215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 4752215976Sjmallett info.flags = 0; 4753215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4754215976Sjmallett info.group_index = 17; 4755215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4756215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4757215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4758215976Sjmallett info.func = __cvmx_error_display; 4759215976Sjmallett info.user_info = (long) 4760215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 4761215976Sjmallett " failure occurs\n" 4762215976Sjmallett " Cannot fire in loopback1 mode\n"; 4763215976Sjmallett fail |= cvmx_error_add(&info); 4764215976Sjmallett 4765215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4766215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 4767215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 4768215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 4769215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 4770215976Sjmallett info.flags = 0; 4771215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4772215976Sjmallett info.group_index = 17; 4773215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4774215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4775215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4776215976Sjmallett info.func = __cvmx_error_display; 4777215976Sjmallett info.user_info = (long) 4778215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 4779215976Sjmallett " state. Should never be set during normal operation\n"; 4780215976Sjmallett fail |= cvmx_error_add(&info); 4781215976Sjmallett 4782215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4783215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 4784215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 4785215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 4786215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 4787215976Sjmallett info.flags = 0; 4788215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4789215976Sjmallett info.group_index = 17; 4790215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4791215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4792215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4793215976Sjmallett info.func = __cvmx_error_display; 4794215976Sjmallett info.user_info = (long) 4795215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 4796215976Sjmallett " state. Should never be set during normal operation\n"; 4797215976Sjmallett fail |= cvmx_error_add(&info); 4798215976Sjmallett 4799215976Sjmallett /* CVMX_PCSX_INTX_REG(2,1) */ 4800215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4801215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 4802215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 4803215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 4804215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 4805215976Sjmallett info.flags = 0; 4806215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4807215976Sjmallett info.group_index = 18; 4808215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4809215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4810215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4811215976Sjmallett info.func = __cvmx_error_display; 4812215976Sjmallett info.user_info = (long) 4813215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n"; 4814215976Sjmallett fail |= cvmx_error_add(&info); 4815215976Sjmallett 4816215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4817215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 4818215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 4819215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 4820215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 4821215976Sjmallett info.flags = 0; 4822215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4823215976Sjmallett info.group_index = 18; 4824215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4825215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4826215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4827215976Sjmallett info.func = __cvmx_error_display; 4828215976Sjmallett info.user_info = (long) 4829215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 4830215976Sjmallett " condition\n"; 4831215976Sjmallett fail |= cvmx_error_add(&info); 4832215976Sjmallett 4833215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4834215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 4835215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 4836215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 4837215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 4838215976Sjmallett info.flags = 0; 4839215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4840215976Sjmallett info.group_index = 18; 4841215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4842215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4843215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4844215976Sjmallett info.func = __cvmx_error_display; 4845215976Sjmallett info.user_info = (long) 4846215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 4847215976Sjmallett " condition\n"; 4848215976Sjmallett fail |= cvmx_error_add(&info); 4849215976Sjmallett 4850215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4851215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 4852215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 4853215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 4854215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 4855215976Sjmallett info.flags = 0; 4856215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4857215976Sjmallett info.group_index = 18; 4858215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4859215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4860215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4861215976Sjmallett info.func = __cvmx_error_display; 4862215976Sjmallett info.user_info = (long) 4863215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 4864215976Sjmallett " state. Should never be set during normal operation\n"; 4865215976Sjmallett fail |= cvmx_error_add(&info); 4866215976Sjmallett 4867215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4868215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 4869215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 4870215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 4871215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 4872215976Sjmallett info.flags = 0; 4873215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4874215976Sjmallett info.group_index = 18; 4875215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4876215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4877215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4878215976Sjmallett info.func = __cvmx_error_display; 4879215976Sjmallett info.user_info = (long) 4880215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 4881215976Sjmallett " state. Should never be set during normal operation\n"; 4882215976Sjmallett fail |= cvmx_error_add(&info); 4883215976Sjmallett 4884215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4885215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 4886215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 4887215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 4888215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 4889215976Sjmallett info.flags = 0; 4890215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4891215976Sjmallett info.group_index = 18; 4892215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4893215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4894215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4895215976Sjmallett info.func = __cvmx_error_display; 4896215976Sjmallett info.user_info = (long) 4897215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 4898215976Sjmallett " failure occurs\n" 4899215976Sjmallett " Cannot fire in loopback1 mode\n"; 4900215976Sjmallett fail |= cvmx_error_add(&info); 4901215976Sjmallett 4902215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4903215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 4904215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 4905215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 4906215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 4907215976Sjmallett info.flags = 0; 4908215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4909215976Sjmallett info.group_index = 18; 4910215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4911215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4912215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4913215976Sjmallett info.func = __cvmx_error_display; 4914215976Sjmallett info.user_info = (long) 4915215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 4916215976Sjmallett " state. Should never be set during normal operation\n"; 4917215976Sjmallett fail |= cvmx_error_add(&info); 4918215976Sjmallett 4919215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4920215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 4921215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 4922215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 4923215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 4924215976Sjmallett info.flags = 0; 4925215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4926215976Sjmallett info.group_index = 18; 4927215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4928215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4929215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4930215976Sjmallett info.func = __cvmx_error_display; 4931215976Sjmallett info.user_info = (long) 4932215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 4933215976Sjmallett " state. Should never be set during normal operation\n"; 4934215976Sjmallett fail |= cvmx_error_add(&info); 4935215976Sjmallett 4936215976Sjmallett /* CVMX_PCSX_INTX_REG(3,1) */ 4937215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4938215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 4939215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 4940215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 4941215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 4942215976Sjmallett info.flags = 0; 4943215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4944215976Sjmallett info.group_index = 19; 4945215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4946215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4947215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4948215976Sjmallett info.func = __cvmx_error_display; 4949215976Sjmallett info.user_info = (long) 4950215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n"; 4951215976Sjmallett fail |= cvmx_error_add(&info); 4952215976Sjmallett 4953215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4954215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 4955215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 4956215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 4957215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 4958215976Sjmallett info.flags = 0; 4959215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4960215976Sjmallett info.group_index = 19; 4961215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4962215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4963215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4964215976Sjmallett info.func = __cvmx_error_display; 4965215976Sjmallett info.user_info = (long) 4966215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 4967215976Sjmallett " condition\n"; 4968215976Sjmallett fail |= cvmx_error_add(&info); 4969215976Sjmallett 4970215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4971215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 4972215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 4973215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 4974215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 4975215976Sjmallett info.flags = 0; 4976215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4977215976Sjmallett info.group_index = 19; 4978215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4979215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4980215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4981215976Sjmallett info.func = __cvmx_error_display; 4982215976Sjmallett info.user_info = (long) 4983215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 4984215976Sjmallett " condition\n"; 4985215976Sjmallett fail |= cvmx_error_add(&info); 4986215976Sjmallett 4987215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4988215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 4989215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 4990215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 4991215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 4992215976Sjmallett info.flags = 0; 4993215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4994215976Sjmallett info.group_index = 19; 4995215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4996215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4997215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4998215976Sjmallett info.func = __cvmx_error_display; 4999215976Sjmallett info.user_info = (long) 5000215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5001215976Sjmallett " state. Should never be set during normal operation\n"; 5002215976Sjmallett fail |= cvmx_error_add(&info); 5003215976Sjmallett 5004215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5005215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5006215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5007215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5008215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5009215976Sjmallett info.flags = 0; 5010215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5011215976Sjmallett info.group_index = 19; 5012215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5013215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5014215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5015215976Sjmallett info.func = __cvmx_error_display; 5016215976Sjmallett info.user_info = (long) 5017215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5018215976Sjmallett " state. Should never be set during normal operation\n"; 5019215976Sjmallett fail |= cvmx_error_add(&info); 5020215976Sjmallett 5021215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5022215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5023215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5024215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5025215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5026215976Sjmallett info.flags = 0; 5027215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5028215976Sjmallett info.group_index = 19; 5029215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5030215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5031215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5032215976Sjmallett info.func = __cvmx_error_display; 5033215976Sjmallett info.user_info = (long) 5034215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5035215976Sjmallett " failure occurs\n" 5036215976Sjmallett " Cannot fire in loopback1 mode\n"; 5037215976Sjmallett fail |= cvmx_error_add(&info); 5038215976Sjmallett 5039215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5040215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5041215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5042215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5043215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5044215976Sjmallett info.flags = 0; 5045215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5046215976Sjmallett info.group_index = 19; 5047215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5048215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5049215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5050215976Sjmallett info.func = __cvmx_error_display; 5051215976Sjmallett info.user_info = (long) 5052215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5053215976Sjmallett " state. Should never be set during normal operation\n"; 5054215976Sjmallett fail |= cvmx_error_add(&info); 5055215976Sjmallett 5056215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5057215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5058215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5059215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5060215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5061215976Sjmallett info.flags = 0; 5062215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5063215976Sjmallett info.group_index = 19; 5064215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5065215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5066215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5067215976Sjmallett info.func = __cvmx_error_display; 5068215976Sjmallett info.user_info = (long) 5069215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5070215976Sjmallett " state. Should never be set during normal operation\n"; 5071215976Sjmallett fail |= cvmx_error_add(&info); 5072215976Sjmallett 5073215976Sjmallett /* CVMX_PCSXX_INT_REG(1) */ 5074215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5075215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5076215976Sjmallett info.status_mask = 1ull<<0 /* txflt */; 5077215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5078215976Sjmallett info.enable_mask = 1ull<<0 /* txflt_en */; 5079215976Sjmallett info.flags = 0; 5080215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5081215976Sjmallett info.group_index = 16; 5082215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5083215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5084215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5085215976Sjmallett info.func = __cvmx_error_display; 5086215976Sjmallett info.user_info = (long) 5087215976Sjmallett "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n"; 5088215976Sjmallett fail |= cvmx_error_add(&info); 5089215976Sjmallett 5090215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5091215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5092215976Sjmallett info.status_mask = 1ull<<1 /* rxbad */; 5093215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5094215976Sjmallett info.enable_mask = 1ull<<1 /* rxbad_en */; 5095215976Sjmallett info.flags = 0; 5096215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5097215976Sjmallett info.group_index = 16; 5098215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5099215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5100215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5101215976Sjmallett info.func = __cvmx_error_display; 5102215976Sjmallett info.user_info = (long) 5103215976Sjmallett "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n"; 5104215976Sjmallett fail |= cvmx_error_add(&info); 5105215976Sjmallett 5106215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5107215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5108215976Sjmallett info.status_mask = 1ull<<2 /* rxsynbad */; 5109215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5110215976Sjmallett info.enable_mask = 1ull<<2 /* rxsynbad_en */; 5111215976Sjmallett info.flags = 0; 5112215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5113215976Sjmallett info.group_index = 16; 5114215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5115215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5116215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5117215976Sjmallett info.func = __cvmx_error_display; 5118215976Sjmallett info.user_info = (long) 5119215976Sjmallett "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n" 5120215976Sjmallett " in one of the 4 xaui lanes\n"; 5121215976Sjmallett fail |= cvmx_error_add(&info); 5122215976Sjmallett 5123215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5124215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5125215976Sjmallett info.status_mask = 1ull<<4 /* synlos */; 5126215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5127215976Sjmallett info.enable_mask = 1ull<<4 /* synlos_en */; 5128215976Sjmallett info.flags = 0; 5129215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5130215976Sjmallett info.group_index = 16; 5131215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5132215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5133215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5134215976Sjmallett info.func = __cvmx_error_display; 5135215976Sjmallett info.user_info = (long) 5136215976Sjmallett "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n"; 5137215976Sjmallett fail |= cvmx_error_add(&info); 5138215976Sjmallett 5139215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5140215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5141215976Sjmallett info.status_mask = 1ull<<5 /* algnlos */; 5142215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5143215976Sjmallett info.enable_mask = 1ull<<5 /* algnlos_en */; 5144215976Sjmallett info.flags = 0; 5145215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5146215976Sjmallett info.group_index = 16; 5147215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5148215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5149215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5150215976Sjmallett info.func = __cvmx_error_display; 5151215976Sjmallett info.user_info = (long) 5152215976Sjmallett "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n"; 5153215976Sjmallett fail |= cvmx_error_add(&info); 5154215976Sjmallett 5155215976Sjmallett /* CVMX_PCSX_INTX_REG(0,0) */ 5156215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5157215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5158215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5159215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5160215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5161215976Sjmallett info.flags = 0; 5162215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5163215976Sjmallett info.group_index = 0; 5164215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5165215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5166215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5167215976Sjmallett info.func = __cvmx_error_display; 5168215976Sjmallett info.user_info = (long) 5169215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 5170215976Sjmallett fail |= cvmx_error_add(&info); 5171215976Sjmallett 5172215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5173215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5174215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5175215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5176215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5177215976Sjmallett info.flags = 0; 5178215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5179215976Sjmallett info.group_index = 0; 5180215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5181215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5182215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5183215976Sjmallett info.func = __cvmx_error_display; 5184215976Sjmallett info.user_info = (long) 5185215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5186215976Sjmallett " condition\n"; 5187215976Sjmallett fail |= cvmx_error_add(&info); 5188215976Sjmallett 5189215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5190215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5191215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5192215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5193215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5194215976Sjmallett info.flags = 0; 5195215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5196215976Sjmallett info.group_index = 0; 5197215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5198215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5199215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5200215976Sjmallett info.func = __cvmx_error_display; 5201215976Sjmallett info.user_info = (long) 5202215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5203215976Sjmallett " condition\n"; 5204215976Sjmallett fail |= cvmx_error_add(&info); 5205215976Sjmallett 5206215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5207215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5208215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5209215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5210215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5211215976Sjmallett info.flags = 0; 5212215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5213215976Sjmallett info.group_index = 0; 5214215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5215215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5216215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5217215976Sjmallett info.func = __cvmx_error_display; 5218215976Sjmallett info.user_info = (long) 5219215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5220215976Sjmallett " state. Should never be set during normal operation\n"; 5221215976Sjmallett fail |= cvmx_error_add(&info); 5222215976Sjmallett 5223215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5224215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5225215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5226215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5227215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5228215976Sjmallett info.flags = 0; 5229215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5230215976Sjmallett info.group_index = 0; 5231215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5232215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5233215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5234215976Sjmallett info.func = __cvmx_error_display; 5235215976Sjmallett info.user_info = (long) 5236215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5237215976Sjmallett " state. Should never be set during normal operation\n"; 5238215976Sjmallett fail |= cvmx_error_add(&info); 5239215976Sjmallett 5240215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5241215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5242215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5243215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5244215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5245215976Sjmallett info.flags = 0; 5246215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5247215976Sjmallett info.group_index = 0; 5248215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5249215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5250215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5251215976Sjmallett info.func = __cvmx_error_display; 5252215976Sjmallett info.user_info = (long) 5253215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5254215976Sjmallett " failure occurs\n" 5255215976Sjmallett " Cannot fire in loopback1 mode\n"; 5256215976Sjmallett fail |= cvmx_error_add(&info); 5257215976Sjmallett 5258215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5259215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5260215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5261215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5262215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5263215976Sjmallett info.flags = 0; 5264215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5265215976Sjmallett info.group_index = 0; 5266215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5267215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5268215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5269215976Sjmallett info.func = __cvmx_error_display; 5270215976Sjmallett info.user_info = (long) 5271215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5272215976Sjmallett " state. Should never be set during normal operation\n"; 5273215976Sjmallett fail |= cvmx_error_add(&info); 5274215976Sjmallett 5275215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5276215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5277215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5278215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5279215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5280215976Sjmallett info.flags = 0; 5281215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5282215976Sjmallett info.group_index = 0; 5283215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5284215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5285215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5286215976Sjmallett info.func = __cvmx_error_display; 5287215976Sjmallett info.user_info = (long) 5288215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5289215976Sjmallett " state. Should never be set during normal operation\n"; 5290215976Sjmallett fail |= cvmx_error_add(&info); 5291215976Sjmallett 5292215976Sjmallett /* CVMX_PCSX_INTX_REG(1,0) */ 5293215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5294215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5295215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5296215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5297215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5298215976Sjmallett info.flags = 0; 5299215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5300215976Sjmallett info.group_index = 1; 5301215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5302215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5303215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5304215976Sjmallett info.func = __cvmx_error_display; 5305215976Sjmallett info.user_info = (long) 5306215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 5307215976Sjmallett fail |= cvmx_error_add(&info); 5308215976Sjmallett 5309215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5310215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5311215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5312215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5313215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5314215976Sjmallett info.flags = 0; 5315215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5316215976Sjmallett info.group_index = 1; 5317215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5318215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5319215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5320215976Sjmallett info.func = __cvmx_error_display; 5321215976Sjmallett info.user_info = (long) 5322215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5323215976Sjmallett " condition\n"; 5324215976Sjmallett fail |= cvmx_error_add(&info); 5325215976Sjmallett 5326215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5327215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5328215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5329215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5330215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5331215976Sjmallett info.flags = 0; 5332215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5333215976Sjmallett info.group_index = 1; 5334215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5335215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5336215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5337215976Sjmallett info.func = __cvmx_error_display; 5338215976Sjmallett info.user_info = (long) 5339215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5340215976Sjmallett " condition\n"; 5341215976Sjmallett fail |= cvmx_error_add(&info); 5342215976Sjmallett 5343215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5344215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5345215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5346215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5347215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5348215976Sjmallett info.flags = 0; 5349215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5350215976Sjmallett info.group_index = 1; 5351215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5352215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5353215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5354215976Sjmallett info.func = __cvmx_error_display; 5355215976Sjmallett info.user_info = (long) 5356215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5357215976Sjmallett " state. Should never be set during normal operation\n"; 5358215976Sjmallett fail |= cvmx_error_add(&info); 5359215976Sjmallett 5360215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5361215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5362215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5363215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5364215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5365215976Sjmallett info.flags = 0; 5366215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5367215976Sjmallett info.group_index = 1; 5368215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5369215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5370215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5371215976Sjmallett info.func = __cvmx_error_display; 5372215976Sjmallett info.user_info = (long) 5373215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5374215976Sjmallett " state. Should never be set during normal operation\n"; 5375215976Sjmallett fail |= cvmx_error_add(&info); 5376215976Sjmallett 5377215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5378215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5379215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5380215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5381215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5382215976Sjmallett info.flags = 0; 5383215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5384215976Sjmallett info.group_index = 1; 5385215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5386215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5387215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5388215976Sjmallett info.func = __cvmx_error_display; 5389215976Sjmallett info.user_info = (long) 5390215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5391215976Sjmallett " failure occurs\n" 5392215976Sjmallett " Cannot fire in loopback1 mode\n"; 5393215976Sjmallett fail |= cvmx_error_add(&info); 5394215976Sjmallett 5395215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5396215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5397215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5398215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5399215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5400215976Sjmallett info.flags = 0; 5401215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5402215976Sjmallett info.group_index = 1; 5403215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5404215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5405215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5406215976Sjmallett info.func = __cvmx_error_display; 5407215976Sjmallett info.user_info = (long) 5408215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5409215976Sjmallett " state. Should never be set during normal operation\n"; 5410215976Sjmallett fail |= cvmx_error_add(&info); 5411215976Sjmallett 5412215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5413215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5414215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5415215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5416215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5417215976Sjmallett info.flags = 0; 5418215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5419215976Sjmallett info.group_index = 1; 5420215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5421215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5422215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5423215976Sjmallett info.func = __cvmx_error_display; 5424215976Sjmallett info.user_info = (long) 5425215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5426215976Sjmallett " state. Should never be set during normal operation\n"; 5427215976Sjmallett fail |= cvmx_error_add(&info); 5428215976Sjmallett 5429215976Sjmallett /* CVMX_PCSX_INTX_REG(2,0) */ 5430215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5431215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5432215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5433215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5434215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5435215976Sjmallett info.flags = 0; 5436215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5437215976Sjmallett info.group_index = 2; 5438215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5439215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5440215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5441215976Sjmallett info.func = __cvmx_error_display; 5442215976Sjmallett info.user_info = (long) 5443215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 5444215976Sjmallett fail |= cvmx_error_add(&info); 5445215976Sjmallett 5446215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5447215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5448215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5449215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5450215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5451215976Sjmallett info.flags = 0; 5452215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5453215976Sjmallett info.group_index = 2; 5454215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5455215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5456215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5457215976Sjmallett info.func = __cvmx_error_display; 5458215976Sjmallett info.user_info = (long) 5459215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5460215976Sjmallett " condition\n"; 5461215976Sjmallett fail |= cvmx_error_add(&info); 5462215976Sjmallett 5463215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5464215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5465215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5466215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5467215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5468215976Sjmallett info.flags = 0; 5469215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5470215976Sjmallett info.group_index = 2; 5471215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5472215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5473215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5474215976Sjmallett info.func = __cvmx_error_display; 5475215976Sjmallett info.user_info = (long) 5476215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5477215976Sjmallett " condition\n"; 5478215976Sjmallett fail |= cvmx_error_add(&info); 5479215976Sjmallett 5480215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5481215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5482215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5483215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5484215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5485215976Sjmallett info.flags = 0; 5486215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5487215976Sjmallett info.group_index = 2; 5488215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5489215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5490215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5491215976Sjmallett info.func = __cvmx_error_display; 5492215976Sjmallett info.user_info = (long) 5493215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5494215976Sjmallett " state. Should never be set during normal operation\n"; 5495215976Sjmallett fail |= cvmx_error_add(&info); 5496215976Sjmallett 5497215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5498215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5499215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5500215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5501215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5502215976Sjmallett info.flags = 0; 5503215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5504215976Sjmallett info.group_index = 2; 5505215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5506215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5507215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5508215976Sjmallett info.func = __cvmx_error_display; 5509215976Sjmallett info.user_info = (long) 5510215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5511215976Sjmallett " state. Should never be set during normal operation\n"; 5512215976Sjmallett fail |= cvmx_error_add(&info); 5513215976Sjmallett 5514215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5515215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5516215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5517215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5518215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5519215976Sjmallett info.flags = 0; 5520215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5521215976Sjmallett info.group_index = 2; 5522215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5523215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5524215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5525215976Sjmallett info.func = __cvmx_error_display; 5526215976Sjmallett info.user_info = (long) 5527215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5528215976Sjmallett " failure occurs\n" 5529215976Sjmallett " Cannot fire in loopback1 mode\n"; 5530215976Sjmallett fail |= cvmx_error_add(&info); 5531215976Sjmallett 5532215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5533215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5534215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5535215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5536215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5537215976Sjmallett info.flags = 0; 5538215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5539215976Sjmallett info.group_index = 2; 5540215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5541215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5542215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5543215976Sjmallett info.func = __cvmx_error_display; 5544215976Sjmallett info.user_info = (long) 5545215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5546215976Sjmallett " state. Should never be set during normal operation\n"; 5547215976Sjmallett fail |= cvmx_error_add(&info); 5548215976Sjmallett 5549215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5550215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5551215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5552215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5553215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5554215976Sjmallett info.flags = 0; 5555215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5556215976Sjmallett info.group_index = 2; 5557215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5558215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5559215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5560215976Sjmallett info.func = __cvmx_error_display; 5561215976Sjmallett info.user_info = (long) 5562215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5563215976Sjmallett " state. Should never be set during normal operation\n"; 5564215976Sjmallett fail |= cvmx_error_add(&info); 5565215976Sjmallett 5566215976Sjmallett /* CVMX_PCSX_INTX_REG(3,0) */ 5567215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5568215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5569215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5570215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5571215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5572215976Sjmallett info.flags = 0; 5573215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5574215976Sjmallett info.group_index = 3; 5575215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5576215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5577215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5578215976Sjmallett info.func = __cvmx_error_display; 5579215976Sjmallett info.user_info = (long) 5580215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 5581215976Sjmallett fail |= cvmx_error_add(&info); 5582215976Sjmallett 5583215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5584215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5585215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5586215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5587215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5588215976Sjmallett info.flags = 0; 5589215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5590215976Sjmallett info.group_index = 3; 5591215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5592215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5593215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5594215976Sjmallett info.func = __cvmx_error_display; 5595215976Sjmallett info.user_info = (long) 5596215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5597215976Sjmallett " condition\n"; 5598215976Sjmallett fail |= cvmx_error_add(&info); 5599215976Sjmallett 5600215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5601215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5602215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5603215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5604215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5605215976Sjmallett info.flags = 0; 5606215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5607215976Sjmallett info.group_index = 3; 5608215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5609215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5610215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5611215976Sjmallett info.func = __cvmx_error_display; 5612215976Sjmallett info.user_info = (long) 5613215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5614215976Sjmallett " condition\n"; 5615215976Sjmallett fail |= cvmx_error_add(&info); 5616215976Sjmallett 5617215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5618215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5619215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5620215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5621215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5622215976Sjmallett info.flags = 0; 5623215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5624215976Sjmallett info.group_index = 3; 5625215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5626215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5627215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5628215976Sjmallett info.func = __cvmx_error_display; 5629215976Sjmallett info.user_info = (long) 5630215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5631215976Sjmallett " state. Should never be set during normal operation\n"; 5632215976Sjmallett fail |= cvmx_error_add(&info); 5633215976Sjmallett 5634215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5635215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5636215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5637215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5638215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5639215976Sjmallett info.flags = 0; 5640215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5641215976Sjmallett info.group_index = 3; 5642215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5643215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5644215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5645215976Sjmallett info.func = __cvmx_error_display; 5646215976Sjmallett info.user_info = (long) 5647215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5648215976Sjmallett " state. Should never be set during normal operation\n"; 5649215976Sjmallett fail |= cvmx_error_add(&info); 5650215976Sjmallett 5651215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5652215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5653215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5654215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5655215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5656215976Sjmallett info.flags = 0; 5657215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5658215976Sjmallett info.group_index = 3; 5659215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5660215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5661215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5662215976Sjmallett info.func = __cvmx_error_display; 5663215976Sjmallett info.user_info = (long) 5664215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5665215976Sjmallett " failure occurs\n" 5666215976Sjmallett " Cannot fire in loopback1 mode\n"; 5667215976Sjmallett fail |= cvmx_error_add(&info); 5668215976Sjmallett 5669215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5670215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5671215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5672215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5673215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5674215976Sjmallett info.flags = 0; 5675215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5676215976Sjmallett info.group_index = 3; 5677215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5678215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5679215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5680215976Sjmallett info.func = __cvmx_error_display; 5681215976Sjmallett info.user_info = (long) 5682215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5683215976Sjmallett " state. Should never be set during normal operation\n"; 5684215976Sjmallett fail |= cvmx_error_add(&info); 5685215976Sjmallett 5686215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5687215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5688215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5689215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5690215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5691215976Sjmallett info.flags = 0; 5692215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5693215976Sjmallett info.group_index = 3; 5694215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5695215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5696215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5697215976Sjmallett info.func = __cvmx_error_display; 5698215976Sjmallett info.user_info = (long) 5699215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5700215976Sjmallett " state. Should never be set during normal operation\n"; 5701215976Sjmallett fail |= cvmx_error_add(&info); 5702215976Sjmallett 5703215976Sjmallett /* CVMX_PCSXX_INT_REG(0) */ 5704215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5705215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5706215976Sjmallett info.status_mask = 1ull<<0 /* txflt */; 5707215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5708215976Sjmallett info.enable_mask = 1ull<<0 /* txflt_en */; 5709215976Sjmallett info.flags = 0; 5710215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5711215976Sjmallett info.group_index = 0; 5712215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5713215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5714215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5715215976Sjmallett info.func = __cvmx_error_display; 5716215976Sjmallett info.user_info = (long) 5717215976Sjmallett "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n"; 5718215976Sjmallett fail |= cvmx_error_add(&info); 5719215976Sjmallett 5720215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5721215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5722215976Sjmallett info.status_mask = 1ull<<1 /* rxbad */; 5723215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5724215976Sjmallett info.enable_mask = 1ull<<1 /* rxbad_en */; 5725215976Sjmallett info.flags = 0; 5726215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5727215976Sjmallett info.group_index = 0; 5728215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5729215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5730215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5731215976Sjmallett info.func = __cvmx_error_display; 5732215976Sjmallett info.user_info = (long) 5733215976Sjmallett "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n"; 5734215976Sjmallett fail |= cvmx_error_add(&info); 5735215976Sjmallett 5736215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5737215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5738215976Sjmallett info.status_mask = 1ull<<2 /* rxsynbad */; 5739215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5740215976Sjmallett info.enable_mask = 1ull<<2 /* rxsynbad_en */; 5741215976Sjmallett info.flags = 0; 5742215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5743215976Sjmallett info.group_index = 0; 5744215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5745215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5746215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5747215976Sjmallett info.func = __cvmx_error_display; 5748215976Sjmallett info.user_info = (long) 5749215976Sjmallett "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n" 5750215976Sjmallett " in one of the 4 xaui lanes\n"; 5751215976Sjmallett fail |= cvmx_error_add(&info); 5752215976Sjmallett 5753215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5754215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5755215976Sjmallett info.status_mask = 1ull<<4 /* synlos */; 5756215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5757215976Sjmallett info.enable_mask = 1ull<<4 /* synlos_en */; 5758215976Sjmallett info.flags = 0; 5759215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5760215976Sjmallett info.group_index = 0; 5761215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5762215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5763215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5764215976Sjmallett info.func = __cvmx_error_display; 5765215976Sjmallett info.user_info = (long) 5766215976Sjmallett "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n"; 5767215976Sjmallett fail |= cvmx_error_add(&info); 5768215976Sjmallett 5769215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5770215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5771215976Sjmallett info.status_mask = 1ull<<5 /* algnlos */; 5772215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5773215976Sjmallett info.enable_mask = 1ull<<5 /* algnlos_en */; 5774215976Sjmallett info.flags = 0; 5775215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5776215976Sjmallett info.group_index = 0; 5777215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5778215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5779215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5780215976Sjmallett info.func = __cvmx_error_display; 5781215976Sjmallett info.user_info = (long) 5782215976Sjmallett "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n"; 5783215976Sjmallett fail |= cvmx_error_add(&info); 5784215976Sjmallett 5785215976Sjmallett /* CVMX_KEY_INT_SUM */ 5786215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5787215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 5788215976Sjmallett info.status_mask = 1ull<<0 /* ked0_sbe */; 5789215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 5790215976Sjmallett info.enable_mask = 1ull<<0 /* ked0_sbe */; 5791215976Sjmallett info.flags = 0; 5792215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5793215976Sjmallett info.group_index = 0; 5794215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5795215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5796215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 5797215976Sjmallett info.func = __cvmx_error_display; 5798215976Sjmallett info.user_info = (long) 5799215976Sjmallett "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n" 5800215976Sjmallett; 5801215976Sjmallett fail |= cvmx_error_add(&info); 5802215976Sjmallett 5803215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5804215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 5805215976Sjmallett info.status_mask = 1ull<<1 /* ked0_dbe */; 5806215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 5807215976Sjmallett info.enable_mask = 1ull<<1 /* ked0_dbe */; 5808215976Sjmallett info.flags = 0; 5809215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5810215976Sjmallett info.group_index = 0; 5811215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5812215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5813215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 5814215976Sjmallett info.func = __cvmx_error_display; 5815215976Sjmallett info.user_info = (long) 5816215976Sjmallett "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n" 5817215976Sjmallett; 5818215976Sjmallett fail |= cvmx_error_add(&info); 5819215976Sjmallett 5820215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5821215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 5822215976Sjmallett info.status_mask = 1ull<<2 /* ked1_sbe */; 5823215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 5824215976Sjmallett info.enable_mask = 1ull<<2 /* ked1_sbe */; 5825215976Sjmallett info.flags = 0; 5826215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5827215976Sjmallett info.group_index = 0; 5828215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5829215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5830215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 5831215976Sjmallett info.func = __cvmx_error_display; 5832215976Sjmallett info.user_info = (long) 5833215976Sjmallett "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n" 5834215976Sjmallett; 5835215976Sjmallett fail |= cvmx_error_add(&info); 5836215976Sjmallett 5837215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5838215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 5839215976Sjmallett info.status_mask = 1ull<<3 /* ked1_dbe */; 5840215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 5841215976Sjmallett info.enable_mask = 1ull<<3 /* ked1_dbe */; 5842215976Sjmallett info.flags = 0; 5843215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5844215976Sjmallett info.group_index = 0; 5845215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5846215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5847215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 5848215976Sjmallett info.func = __cvmx_error_display; 5849215976Sjmallett info.user_info = (long) 5850215976Sjmallett "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n" 5851215976Sjmallett; 5852215976Sjmallett fail |= cvmx_error_add(&info); 5853215976Sjmallett 5854215976Sjmallett /* CVMX_MIO_BOOT_ERR */ 5855215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5856215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 5857215976Sjmallett info.status_mask = 1ull<<0 /* adr_err */; 5858215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 5859215976Sjmallett info.enable_mask = 1ull<<0 /* adr_int */; 5860215976Sjmallett info.flags = 0; 5861215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5862215976Sjmallett info.group_index = 0; 5863215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5864215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5865215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 5866215976Sjmallett info.func = __cvmx_error_display; 5867215976Sjmallett info.user_info = (long) 5868215976Sjmallett "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n"; 5869215976Sjmallett fail |= cvmx_error_add(&info); 5870215976Sjmallett 5871215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5872215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 5873215976Sjmallett info.status_mask = 1ull<<1 /* wait_err */; 5874215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 5875215976Sjmallett info.enable_mask = 1ull<<1 /* wait_int */; 5876215976Sjmallett info.flags = 0; 5877215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5878215976Sjmallett info.group_index = 0; 5879215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5880215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5881215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 5882215976Sjmallett info.func = __cvmx_error_display; 5883215976Sjmallett info.user_info = (long) 5884215976Sjmallett "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n"; 5885215976Sjmallett fail |= cvmx_error_add(&info); 5886215976Sjmallett 5887215976Sjmallett /* CVMX_PIP_INT_REG */ 5888215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5889215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5890215976Sjmallett info.status_mask = 1ull<<3 /* prtnxa */; 5891215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5892215976Sjmallett info.enable_mask = 1ull<<3 /* prtnxa */; 5893215976Sjmallett info.flags = 0; 5894215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5895215976Sjmallett info.group_index = 0; 5896215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5897215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5898215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5899215976Sjmallett info.func = __cvmx_error_display; 5900215976Sjmallett info.user_info = (long) 5901215976Sjmallett "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n"; 5902215976Sjmallett fail |= cvmx_error_add(&info); 5903215976Sjmallett 5904215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5905215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5906215976Sjmallett info.status_mask = 1ull<<4 /* badtag */; 5907215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5908215976Sjmallett info.enable_mask = 1ull<<4 /* badtag */; 5909215976Sjmallett info.flags = 0; 5910215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5911215976Sjmallett info.group_index = 0; 5912215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5913215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5914215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5915215976Sjmallett info.func = __cvmx_error_display; 5916215976Sjmallett info.user_info = (long) 5917215976Sjmallett "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n"; 5918215976Sjmallett fail |= cvmx_error_add(&info); 5919215976Sjmallett 5920215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5921215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5922215976Sjmallett info.status_mask = 1ull<<5 /* skprunt */; 5923215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5924215976Sjmallett info.enable_mask = 1ull<<5 /* skprunt */; 5925215976Sjmallett info.flags = 0; 5926215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5927215976Sjmallett info.group_index = 0; 5928215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5929215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5930215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5931215976Sjmallett info.func = __cvmx_error_display; 5932215976Sjmallett info.user_info = (long) 5933215976Sjmallett "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n" 5934215976Sjmallett " This interrupt can occur with received PARTIAL\n" 5935215976Sjmallett " packets that are truncated to SKIP bytes or\n" 5936215976Sjmallett " smaller.\n"; 5937215976Sjmallett fail |= cvmx_error_add(&info); 5938215976Sjmallett 5939215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5940215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5941215976Sjmallett info.status_mask = 1ull<<6 /* todoovr */; 5942215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5943215976Sjmallett info.enable_mask = 1ull<<6 /* todoovr */; 5944215976Sjmallett info.flags = 0; 5945215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5946215976Sjmallett info.group_index = 0; 5947215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5948215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5949215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5950215976Sjmallett info.func = __cvmx_error_display; 5951215976Sjmallett info.user_info = (long) 5952215976Sjmallett "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n"; 5953215976Sjmallett fail |= cvmx_error_add(&info); 5954215976Sjmallett 5955215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5956215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5957215976Sjmallett info.status_mask = 1ull<<7 /* feperr */; 5958215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5959215976Sjmallett info.enable_mask = 1ull<<7 /* feperr */; 5960215976Sjmallett info.flags = 0; 5961215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5962215976Sjmallett info.group_index = 0; 5963215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5964215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5965215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5966215976Sjmallett info.func = __cvmx_error_display; 5967215976Sjmallett info.user_info = (long) 5968215976Sjmallett "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n"; 5969215976Sjmallett fail |= cvmx_error_add(&info); 5970215976Sjmallett 5971215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5972215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5973215976Sjmallett info.status_mask = 1ull<<8 /* beperr */; 5974215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5975215976Sjmallett info.enable_mask = 1ull<<8 /* beperr */; 5976215976Sjmallett info.flags = 0; 5977215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5978215976Sjmallett info.group_index = 0; 5979215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5980215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5981215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5982215976Sjmallett info.func = __cvmx_error_display; 5983215976Sjmallett info.user_info = (long) 5984215976Sjmallett "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n"; 5985215976Sjmallett fail |= cvmx_error_add(&info); 5986215976Sjmallett 5987215976Sjmallett /* CVMX_FPA_INT_SUM */ 5988215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5989215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5990215976Sjmallett info.status_mask = 1ull<<0 /* fed0_sbe */; 5991215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5992215976Sjmallett info.enable_mask = 1ull<<0 /* fed0_sbe */; 5993215976Sjmallett info.flags = 0; 5994215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5995215976Sjmallett info.group_index = 0; 5996215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5997215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5998215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5999215976Sjmallett info.func = __cvmx_error_display; 6000215976Sjmallett info.user_info = (long) 6001215976Sjmallett "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n"; 6002215976Sjmallett fail |= cvmx_error_add(&info); 6003215976Sjmallett 6004215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6005215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6006215976Sjmallett info.status_mask = 1ull<<1 /* fed0_dbe */; 6007215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6008215976Sjmallett info.enable_mask = 1ull<<1 /* fed0_dbe */; 6009215976Sjmallett info.flags = 0; 6010215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6011215976Sjmallett info.group_index = 0; 6012215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6013215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6014215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6015215976Sjmallett info.func = __cvmx_error_display; 6016215976Sjmallett info.user_info = (long) 6017215976Sjmallett "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n"; 6018215976Sjmallett fail |= cvmx_error_add(&info); 6019215976Sjmallett 6020215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6021215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6022215976Sjmallett info.status_mask = 1ull<<2 /* fed1_sbe */; 6023215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6024215976Sjmallett info.enable_mask = 1ull<<2 /* fed1_sbe */; 6025215976Sjmallett info.flags = 0; 6026215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6027215976Sjmallett info.group_index = 0; 6028215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6029215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6030215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6031215976Sjmallett info.func = __cvmx_error_display; 6032215976Sjmallett info.user_info = (long) 6033215976Sjmallett "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n"; 6034215976Sjmallett fail |= cvmx_error_add(&info); 6035215976Sjmallett 6036215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6037215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6038215976Sjmallett info.status_mask = 1ull<<3 /* fed1_dbe */; 6039215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6040215976Sjmallett info.enable_mask = 1ull<<3 /* fed1_dbe */; 6041215976Sjmallett info.flags = 0; 6042215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6043215976Sjmallett info.group_index = 0; 6044215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6045215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6046215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6047215976Sjmallett info.func = __cvmx_error_display; 6048215976Sjmallett info.user_info = (long) 6049215976Sjmallett "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n"; 6050215976Sjmallett fail |= cvmx_error_add(&info); 6051215976Sjmallett 6052215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6053215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6054215976Sjmallett info.status_mask = 1ull<<4 /* q0_und */; 6055215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6056215976Sjmallett info.enable_mask = 1ull<<4 /* q0_und */; 6057215976Sjmallett info.flags = 0; 6058215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6059215976Sjmallett info.group_index = 0; 6060215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6061215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6062215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6063215976Sjmallett info.func = __cvmx_error_display; 6064215976Sjmallett info.user_info = (long) 6065215976Sjmallett "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n" 6066215976Sjmallett " negative.\n"; 6067215976Sjmallett fail |= cvmx_error_add(&info); 6068215976Sjmallett 6069215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6070215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6071215976Sjmallett info.status_mask = 1ull<<5 /* q0_coff */; 6072215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6073215976Sjmallett info.enable_mask = 1ull<<5 /* q0_coff */; 6074215976Sjmallett info.flags = 0; 6075215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6076215976Sjmallett info.group_index = 0; 6077215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6078215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6079215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6080215976Sjmallett info.func = __cvmx_error_display; 6081215976Sjmallett info.user_info = (long) 6082215976Sjmallett "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n" 6083215976Sjmallett " the count available is greater than pointers\n" 6084215976Sjmallett " present in the FPA.\n"; 6085215976Sjmallett fail |= cvmx_error_add(&info); 6086215976Sjmallett 6087215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6088215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6089215976Sjmallett info.status_mask = 1ull<<6 /* q0_perr */; 6090215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6091215976Sjmallett info.enable_mask = 1ull<<6 /* q0_perr */; 6092215976Sjmallett info.flags = 0; 6093215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6094215976Sjmallett info.group_index = 0; 6095215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6096215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6097215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6098215976Sjmallett info.func = __cvmx_error_display; 6099215976Sjmallett info.user_info = (long) 6100215976Sjmallett "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n" 6101215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6102215976Sjmallett fail |= cvmx_error_add(&info); 6103215976Sjmallett 6104215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6105215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6106215976Sjmallett info.status_mask = 1ull<<7 /* q1_und */; 6107215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6108215976Sjmallett info.enable_mask = 1ull<<7 /* q1_und */; 6109215976Sjmallett info.flags = 0; 6110215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6111215976Sjmallett info.group_index = 0; 6112215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6113215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6114215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6115215976Sjmallett info.func = __cvmx_error_display; 6116215976Sjmallett info.user_info = (long) 6117215976Sjmallett "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n" 6118215976Sjmallett " negative.\n"; 6119215976Sjmallett fail |= cvmx_error_add(&info); 6120215976Sjmallett 6121215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6122215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6123215976Sjmallett info.status_mask = 1ull<<8 /* q1_coff */; 6124215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6125215976Sjmallett info.enable_mask = 1ull<<8 /* q1_coff */; 6126215976Sjmallett info.flags = 0; 6127215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6128215976Sjmallett info.group_index = 0; 6129215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6130215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6131215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6132215976Sjmallett info.func = __cvmx_error_display; 6133215976Sjmallett info.user_info = (long) 6134215976Sjmallett "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n" 6135215976Sjmallett " the count available is greater than pointers\n" 6136215976Sjmallett " present in the FPA.\n"; 6137215976Sjmallett fail |= cvmx_error_add(&info); 6138215976Sjmallett 6139215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6140215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6141215976Sjmallett info.status_mask = 1ull<<9 /* q1_perr */; 6142215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6143215976Sjmallett info.enable_mask = 1ull<<9 /* q1_perr */; 6144215976Sjmallett info.flags = 0; 6145215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6146215976Sjmallett info.group_index = 0; 6147215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6148215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6149215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6150215976Sjmallett info.func = __cvmx_error_display; 6151215976Sjmallett info.user_info = (long) 6152215976Sjmallett "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n" 6153215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6154215976Sjmallett fail |= cvmx_error_add(&info); 6155215976Sjmallett 6156215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6157215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6158215976Sjmallett info.status_mask = 1ull<<10 /* q2_und */; 6159215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6160215976Sjmallett info.enable_mask = 1ull<<10 /* q2_und */; 6161215976Sjmallett info.flags = 0; 6162215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6163215976Sjmallett info.group_index = 0; 6164215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6165215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6166215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6167215976Sjmallett info.func = __cvmx_error_display; 6168215976Sjmallett info.user_info = (long) 6169215976Sjmallett "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n" 6170215976Sjmallett " negative.\n"; 6171215976Sjmallett fail |= cvmx_error_add(&info); 6172215976Sjmallett 6173215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6174215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6175215976Sjmallett info.status_mask = 1ull<<11 /* q2_coff */; 6176215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6177215976Sjmallett info.enable_mask = 1ull<<11 /* q2_coff */; 6178215976Sjmallett info.flags = 0; 6179215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6180215976Sjmallett info.group_index = 0; 6181215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6182215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6183215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6184215976Sjmallett info.func = __cvmx_error_display; 6185215976Sjmallett info.user_info = (long) 6186215976Sjmallett "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n" 6187215976Sjmallett " the count available is greater than than pointers\n" 6188215976Sjmallett " present in the FPA.\n"; 6189215976Sjmallett fail |= cvmx_error_add(&info); 6190215976Sjmallett 6191215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6192215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6193215976Sjmallett info.status_mask = 1ull<<12 /* q2_perr */; 6194215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6195215976Sjmallett info.enable_mask = 1ull<<12 /* q2_perr */; 6196215976Sjmallett info.flags = 0; 6197215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6198215976Sjmallett info.group_index = 0; 6199215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6200215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6201215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6202215976Sjmallett info.func = __cvmx_error_display; 6203215976Sjmallett info.user_info = (long) 6204215976Sjmallett "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n" 6205215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6206215976Sjmallett fail |= cvmx_error_add(&info); 6207215976Sjmallett 6208215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6209215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6210215976Sjmallett info.status_mask = 1ull<<13 /* q3_und */; 6211215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6212215976Sjmallett info.enable_mask = 1ull<<13 /* q3_und */; 6213215976Sjmallett info.flags = 0; 6214215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6215215976Sjmallett info.group_index = 0; 6216215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6217215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6218215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6219215976Sjmallett info.func = __cvmx_error_display; 6220215976Sjmallett info.user_info = (long) 6221215976Sjmallett "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n" 6222215976Sjmallett " negative.\n"; 6223215976Sjmallett fail |= cvmx_error_add(&info); 6224215976Sjmallett 6225215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6226215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6227215976Sjmallett info.status_mask = 1ull<<14 /* q3_coff */; 6228215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6229215976Sjmallett info.enable_mask = 1ull<<14 /* q3_coff */; 6230215976Sjmallett info.flags = 0; 6231215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6232215976Sjmallett info.group_index = 0; 6233215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6234215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6235215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6236215976Sjmallett info.func = __cvmx_error_display; 6237215976Sjmallett info.user_info = (long) 6238215976Sjmallett "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n" 6239215976Sjmallett " the count available is greater than than pointers\n" 6240215976Sjmallett " present in the FPA.\n"; 6241215976Sjmallett fail |= cvmx_error_add(&info); 6242215976Sjmallett 6243215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6244215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6245215976Sjmallett info.status_mask = 1ull<<15 /* q3_perr */; 6246215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6247215976Sjmallett info.enable_mask = 1ull<<15 /* q3_perr */; 6248215976Sjmallett info.flags = 0; 6249215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6250215976Sjmallett info.group_index = 0; 6251215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6252215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6253215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6254215976Sjmallett info.func = __cvmx_error_display; 6255215976Sjmallett info.user_info = (long) 6256215976Sjmallett "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n" 6257215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6258215976Sjmallett fail |= cvmx_error_add(&info); 6259215976Sjmallett 6260215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6261215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6262215976Sjmallett info.status_mask = 1ull<<16 /* q4_und */; 6263215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6264215976Sjmallett info.enable_mask = 1ull<<16 /* q4_und */; 6265215976Sjmallett info.flags = 0; 6266215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6267215976Sjmallett info.group_index = 0; 6268215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6269215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6270215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6271215976Sjmallett info.func = __cvmx_error_display; 6272215976Sjmallett info.user_info = (long) 6273215976Sjmallett "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n" 6274215976Sjmallett " negative.\n"; 6275215976Sjmallett fail |= cvmx_error_add(&info); 6276215976Sjmallett 6277215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6278215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6279215976Sjmallett info.status_mask = 1ull<<17 /* q4_coff */; 6280215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6281215976Sjmallett info.enable_mask = 1ull<<17 /* q4_coff */; 6282215976Sjmallett info.flags = 0; 6283215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6284215976Sjmallett info.group_index = 0; 6285215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6286215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6287215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6288215976Sjmallett info.func = __cvmx_error_display; 6289215976Sjmallett info.user_info = (long) 6290215976Sjmallett "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n" 6291215976Sjmallett " the count available is greater than than pointers\n" 6292215976Sjmallett " present in the FPA.\n"; 6293215976Sjmallett fail |= cvmx_error_add(&info); 6294215976Sjmallett 6295215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6296215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6297215976Sjmallett info.status_mask = 1ull<<18 /* q4_perr */; 6298215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6299215976Sjmallett info.enable_mask = 1ull<<18 /* q4_perr */; 6300215976Sjmallett info.flags = 0; 6301215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6302215976Sjmallett info.group_index = 0; 6303215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6304215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6305215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6306215976Sjmallett info.func = __cvmx_error_display; 6307215976Sjmallett info.user_info = (long) 6308215976Sjmallett "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n" 6309215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6310215976Sjmallett fail |= cvmx_error_add(&info); 6311215976Sjmallett 6312215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6313215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6314215976Sjmallett info.status_mask = 1ull<<19 /* q5_und */; 6315215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6316215976Sjmallett info.enable_mask = 1ull<<19 /* q5_und */; 6317215976Sjmallett info.flags = 0; 6318215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6319215976Sjmallett info.group_index = 0; 6320215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6321215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6322215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6323215976Sjmallett info.func = __cvmx_error_display; 6324215976Sjmallett info.user_info = (long) 6325215976Sjmallett "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n" 6326215976Sjmallett " negative.\n"; 6327215976Sjmallett fail |= cvmx_error_add(&info); 6328215976Sjmallett 6329215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6330215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6331215976Sjmallett info.status_mask = 1ull<<20 /* q5_coff */; 6332215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6333215976Sjmallett info.enable_mask = 1ull<<20 /* q5_coff */; 6334215976Sjmallett info.flags = 0; 6335215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6336215976Sjmallett info.group_index = 0; 6337215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6338215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6339215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6340215976Sjmallett info.func = __cvmx_error_display; 6341215976Sjmallett info.user_info = (long) 6342215976Sjmallett "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n" 6343215976Sjmallett " the count available is greater than than pointers\n" 6344215976Sjmallett " present in the FPA.\n"; 6345215976Sjmallett fail |= cvmx_error_add(&info); 6346215976Sjmallett 6347215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6348215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6349215976Sjmallett info.status_mask = 1ull<<21 /* q5_perr */; 6350215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6351215976Sjmallett info.enable_mask = 1ull<<21 /* q5_perr */; 6352215976Sjmallett info.flags = 0; 6353215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6354215976Sjmallett info.group_index = 0; 6355215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6356215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6357215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6358215976Sjmallett info.func = __cvmx_error_display; 6359215976Sjmallett info.user_info = (long) 6360215976Sjmallett "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n" 6361215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6362215976Sjmallett fail |= cvmx_error_add(&info); 6363215976Sjmallett 6364215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6365215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6366215976Sjmallett info.status_mask = 1ull<<22 /* q6_und */; 6367215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6368215976Sjmallett info.enable_mask = 1ull<<22 /* q6_und */; 6369215976Sjmallett info.flags = 0; 6370215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6371215976Sjmallett info.group_index = 0; 6372215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6373215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6374215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6375215976Sjmallett info.func = __cvmx_error_display; 6376215976Sjmallett info.user_info = (long) 6377215976Sjmallett "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n" 6378215976Sjmallett " negative.\n"; 6379215976Sjmallett fail |= cvmx_error_add(&info); 6380215976Sjmallett 6381215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6382215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6383215976Sjmallett info.status_mask = 1ull<<23 /* q6_coff */; 6384215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6385215976Sjmallett info.enable_mask = 1ull<<23 /* q6_coff */; 6386215976Sjmallett info.flags = 0; 6387215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6388215976Sjmallett info.group_index = 0; 6389215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6390215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6391215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6392215976Sjmallett info.func = __cvmx_error_display; 6393215976Sjmallett info.user_info = (long) 6394215976Sjmallett "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n" 6395215976Sjmallett " the count available is greater than than pointers\n" 6396215976Sjmallett " present in the FPA.\n"; 6397215976Sjmallett fail |= cvmx_error_add(&info); 6398215976Sjmallett 6399215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6400215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6401215976Sjmallett info.status_mask = 1ull<<24 /* q6_perr */; 6402215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6403215976Sjmallett info.enable_mask = 1ull<<24 /* q6_perr */; 6404215976Sjmallett info.flags = 0; 6405215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6406215976Sjmallett info.group_index = 0; 6407215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6408215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6409215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6410215976Sjmallett info.func = __cvmx_error_display; 6411215976Sjmallett info.user_info = (long) 6412215976Sjmallett "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n" 6413215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6414215976Sjmallett fail |= cvmx_error_add(&info); 6415215976Sjmallett 6416215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6417215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6418215976Sjmallett info.status_mask = 1ull<<25 /* q7_und */; 6419215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6420215976Sjmallett info.enable_mask = 1ull<<25 /* q7_und */; 6421215976Sjmallett info.flags = 0; 6422215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6423215976Sjmallett info.group_index = 0; 6424215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6425215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6426215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6427215976Sjmallett info.func = __cvmx_error_display; 6428215976Sjmallett info.user_info = (long) 6429215976Sjmallett "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n" 6430215976Sjmallett " negative.\n"; 6431215976Sjmallett fail |= cvmx_error_add(&info); 6432215976Sjmallett 6433215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6434215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6435215976Sjmallett info.status_mask = 1ull<<26 /* q7_coff */; 6436215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6437215976Sjmallett info.enable_mask = 1ull<<26 /* q7_coff */; 6438215976Sjmallett info.flags = 0; 6439215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6440215976Sjmallett info.group_index = 0; 6441215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6442215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6443215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6444215976Sjmallett info.func = __cvmx_error_display; 6445215976Sjmallett info.user_info = (long) 6446215976Sjmallett "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n" 6447215976Sjmallett " the count available is greater than than pointers\n" 6448215976Sjmallett " present in the FPA.\n"; 6449215976Sjmallett fail |= cvmx_error_add(&info); 6450215976Sjmallett 6451215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6452215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6453215976Sjmallett info.status_mask = 1ull<<27 /* q7_perr */; 6454215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6455215976Sjmallett info.enable_mask = 1ull<<27 /* q7_perr */; 6456215976Sjmallett info.flags = 0; 6457215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6458215976Sjmallett info.group_index = 0; 6459215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6460215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6461215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6462215976Sjmallett info.func = __cvmx_error_display; 6463215976Sjmallett info.user_info = (long) 6464215976Sjmallett "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n" 6465215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6466215976Sjmallett fail |= cvmx_error_add(&info); 6467215976Sjmallett 6468215976Sjmallett /* CVMX_LMCX_MEM_CFG0(0) */ 6469215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6470215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 6471215976Sjmallett info.status_mask = 0xfull<<21 /* sec_err */; 6472215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 6473215976Sjmallett info.enable_mask = 1ull<<19 /* intr_sec_ena */; 6474215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 6475215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 6476215976Sjmallett info.group_index = 0; 6477215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6478215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6479215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc0 */; 6480215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err; 6481215976Sjmallett info.user_info = (long) 6482215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n" 6483215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 6484215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 6485215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 6486215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 6487215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 6488215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 6489215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 6490215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 6491215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 6492215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 6493215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 6494215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 6495215976Sjmallett fail |= cvmx_error_add(&info); 6496215976Sjmallett 6497215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6498215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 6499215976Sjmallett info.status_mask = 0xfull<<25 /* ded_err */; 6500215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 6501215976Sjmallett info.enable_mask = 1ull<<20 /* intr_ded_ena */; 6502215976Sjmallett info.flags = 0; 6503215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 6504215976Sjmallett info.group_index = 0; 6505215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6506215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6507215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc0 */; 6508215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err; 6509215976Sjmallett info.user_info = (long) 6510215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n" 6511215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 6512215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 6513215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 6514215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 6515215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 6516215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 6517215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 6518215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 6519215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 6520215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 6521215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 6522215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 6523215976Sjmallett fail |= cvmx_error_add(&info); 6524215976Sjmallett 6525215976Sjmallett /* CVMX_IOB_INT_SUM */ 6526215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6527215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6528215976Sjmallett info.status_mask = 1ull<<0 /* np_sop */; 6529215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6530215976Sjmallett info.enable_mask = 1ull<<0 /* np_sop */; 6531215976Sjmallett info.flags = 0; 6532215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6533215976Sjmallett info.group_index = 0; 6534215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6535215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6536215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6537215976Sjmallett info.func = __cvmx_error_display; 6538215976Sjmallett info.user_info = (long) 6539215976Sjmallett "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n" 6540215976Sjmallett " port for a non-passthrough packet.\n" 6541215976Sjmallett " The first detected error associated with bits [5:0]\n" 6542215976Sjmallett " of this register will only be set here. A new bit\n" 6543215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6544215976Sjmallett fail |= cvmx_error_add(&info); 6545215976Sjmallett 6546215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6547215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6548215976Sjmallett info.status_mask = 1ull<<1 /* np_eop */; 6549215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6550215976Sjmallett info.enable_mask = 1ull<<1 /* np_eop */; 6551215976Sjmallett info.flags = 0; 6552215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6553215976Sjmallett info.group_index = 0; 6554215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6555215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6556215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6557215976Sjmallett info.func = __cvmx_error_display; 6558215976Sjmallett info.user_info = (long) 6559215976Sjmallett "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n" 6560215976Sjmallett " port for a non-passthrough packet.\n" 6561215976Sjmallett " The first detected error associated with bits [5:0]\n" 6562215976Sjmallett " of this register will only be set here. A new bit\n" 6563215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6564215976Sjmallett fail |= cvmx_error_add(&info); 6565215976Sjmallett 6566215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6567215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6568215976Sjmallett info.status_mask = 1ull<<2 /* p_sop */; 6569215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6570215976Sjmallett info.enable_mask = 1ull<<2 /* p_sop */; 6571215976Sjmallett info.flags = 0; 6572215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6573215976Sjmallett info.group_index = 0; 6574215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6575215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6576215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6577215976Sjmallett info.func = __cvmx_error_display; 6578215976Sjmallett info.user_info = (long) 6579215976Sjmallett "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n" 6580215976Sjmallett " port for a passthrough packet.\n" 6581215976Sjmallett " The first detected error associated with bits [5:0]\n" 6582215976Sjmallett " of this register will only be set here. A new bit\n" 6583215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6584215976Sjmallett fail |= cvmx_error_add(&info); 6585215976Sjmallett 6586215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6587215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6588215976Sjmallett info.status_mask = 1ull<<3 /* p_eop */; 6589215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6590215976Sjmallett info.enable_mask = 1ull<<3 /* p_eop */; 6591215976Sjmallett info.flags = 0; 6592215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6593215976Sjmallett info.group_index = 0; 6594215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6595215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6596215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6597215976Sjmallett info.func = __cvmx_error_display; 6598215976Sjmallett info.user_info = (long) 6599215976Sjmallett "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n" 6600215976Sjmallett " port for a passthrough packet.\n" 6601215976Sjmallett " The first detected error associated with bits [5:0]\n" 6602215976Sjmallett " of this register will only be set here. A new bit\n" 6603215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6604215976Sjmallett fail |= cvmx_error_add(&info); 6605215976Sjmallett 6606215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6607215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6608215976Sjmallett info.status_mask = 1ull<<4 /* np_dat */; 6609215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6610215976Sjmallett info.enable_mask = 1ull<<4 /* np_dat */; 6611215976Sjmallett info.flags = 0; 6612215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6613215976Sjmallett info.group_index = 0; 6614215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6615215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6616215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6617215976Sjmallett info.func = __cvmx_error_display; 6618215976Sjmallett info.user_info = (long) 6619215976Sjmallett "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n" 6620215976Sjmallett " port for a non-passthrough packet.\n" 6621215976Sjmallett " The first detected error associated with bits [5:0]\n" 6622215976Sjmallett " of this register will only be set here. A new bit\n" 6623215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6624215976Sjmallett fail |= cvmx_error_add(&info); 6625215976Sjmallett 6626215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6627215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6628215976Sjmallett info.status_mask = 1ull<<5 /* p_dat */; 6629215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6630215976Sjmallett info.enable_mask = 1ull<<5 /* p_dat */; 6631215976Sjmallett info.flags = 0; 6632215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6633215976Sjmallett info.group_index = 0; 6634215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6635215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6636215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6637215976Sjmallett info.func = __cvmx_error_display; 6638215976Sjmallett info.user_info = (long) 6639215976Sjmallett "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n" 6640215976Sjmallett " port for a passthrough packet.\n" 6641215976Sjmallett " The first detected error associated with bits [5:0]\n" 6642215976Sjmallett " of this register will only be set here. A new bit\n" 6643215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6644215976Sjmallett fail |= cvmx_error_add(&info); 6645215976Sjmallett 6646215976Sjmallett /* CVMX_ZIP_ERROR */ 6647215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6648215976Sjmallett info.status_addr = CVMX_ZIP_ERROR; 6649215976Sjmallett info.status_mask = 1ull<<0 /* doorbell */; 6650215976Sjmallett info.enable_addr = CVMX_ZIP_INT_MASK; 6651215976Sjmallett info.enable_mask = 1ull<<0 /* doorbell */; 6652215976Sjmallett info.flags = 0; 6653215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6654215976Sjmallett info.group_index = 0; 6655215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6656215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6657215976Sjmallett info.parent.status_mask = 1ull<<7 /* zip */; 6658215976Sjmallett info.func = __cvmx_error_display; 6659215976Sjmallett info.user_info = (long) 6660215976Sjmallett "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 6661215976Sjmallett fail |= cvmx_error_add(&info); 6662215976Sjmallett 6663215976Sjmallett /* CVMX_USBNX_INT_SUM(0) */ 6664215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6665215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6666215976Sjmallett info.status_mask = 1ull<<0 /* pr_po_e */; 6667215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6668215976Sjmallett info.enable_mask = 1ull<<0 /* pr_po_e */; 6669215976Sjmallett info.flags = 0; 6670215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6671215976Sjmallett info.group_index = 0; 6672215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6673215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6674215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6675215976Sjmallett info.func = __cvmx_error_display; 6676215976Sjmallett info.user_info = (long) 6677215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n"; 6678215976Sjmallett fail |= cvmx_error_add(&info); 6679215976Sjmallett 6680215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6681215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6682215976Sjmallett info.status_mask = 1ull<<1 /* pr_pu_f */; 6683215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6684215976Sjmallett info.enable_mask = 1ull<<1 /* pr_pu_f */; 6685215976Sjmallett info.flags = 0; 6686215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6687215976Sjmallett info.group_index = 0; 6688215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6689215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6690215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6691215976Sjmallett info.func = __cvmx_error_display; 6692215976Sjmallett info.user_info = (long) 6693215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n"; 6694215976Sjmallett fail |= cvmx_error_add(&info); 6695215976Sjmallett 6696215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6697215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6698215976Sjmallett info.status_mask = 1ull<<2 /* nr_po_e */; 6699215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6700215976Sjmallett info.enable_mask = 1ull<<2 /* nr_po_e */; 6701215976Sjmallett info.flags = 0; 6702215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6703215976Sjmallett info.group_index = 0; 6704215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6705215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6706215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6707215976Sjmallett info.func = __cvmx_error_display; 6708215976Sjmallett info.user_info = (long) 6709215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n"; 6710215976Sjmallett fail |= cvmx_error_add(&info); 6711215976Sjmallett 6712215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6713215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6714215976Sjmallett info.status_mask = 1ull<<3 /* nr_pu_f */; 6715215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6716215976Sjmallett info.enable_mask = 1ull<<3 /* nr_pu_f */; 6717215976Sjmallett info.flags = 0; 6718215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6719215976Sjmallett info.group_index = 0; 6720215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6721215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6722215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6723215976Sjmallett info.func = __cvmx_error_display; 6724215976Sjmallett info.user_info = (long) 6725215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n"; 6726215976Sjmallett fail |= cvmx_error_add(&info); 6727215976Sjmallett 6728215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6729215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6730215976Sjmallett info.status_mask = 1ull<<4 /* lr_po_e */; 6731215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6732215976Sjmallett info.enable_mask = 1ull<<4 /* lr_po_e */; 6733215976Sjmallett info.flags = 0; 6734215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6735215976Sjmallett info.group_index = 0; 6736215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6737215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6738215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6739215976Sjmallett info.func = __cvmx_error_display; 6740215976Sjmallett info.user_info = (long) 6741215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n"; 6742215976Sjmallett fail |= cvmx_error_add(&info); 6743215976Sjmallett 6744215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6745215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6746215976Sjmallett info.status_mask = 1ull<<5 /* lr_pu_f */; 6747215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6748215976Sjmallett info.enable_mask = 1ull<<5 /* lr_pu_f */; 6749215976Sjmallett info.flags = 0; 6750215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6751215976Sjmallett info.group_index = 0; 6752215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6753215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6754215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6755215976Sjmallett info.func = __cvmx_error_display; 6756215976Sjmallett info.user_info = (long) 6757215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n"; 6758215976Sjmallett fail |= cvmx_error_add(&info); 6759215976Sjmallett 6760215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6761215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6762215976Sjmallett info.status_mask = 1ull<<6 /* pt_po_e */; 6763215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6764215976Sjmallett info.enable_mask = 1ull<<6 /* pt_po_e */; 6765215976Sjmallett info.flags = 0; 6766215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6767215976Sjmallett info.group_index = 0; 6768215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6769215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6770215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6771215976Sjmallett info.func = __cvmx_error_display; 6772215976Sjmallett info.user_info = (long) 6773215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n"; 6774215976Sjmallett fail |= cvmx_error_add(&info); 6775215976Sjmallett 6776215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6777215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6778215976Sjmallett info.status_mask = 1ull<<7 /* pt_pu_f */; 6779215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6780215976Sjmallett info.enable_mask = 1ull<<7 /* pt_pu_f */; 6781215976Sjmallett info.flags = 0; 6782215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6783215976Sjmallett info.group_index = 0; 6784215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6785215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6786215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6787215976Sjmallett info.func = __cvmx_error_display; 6788215976Sjmallett info.user_info = (long) 6789215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n"; 6790215976Sjmallett fail |= cvmx_error_add(&info); 6791215976Sjmallett 6792215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6793215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6794215976Sjmallett info.status_mask = 1ull<<8 /* nt_po_e */; 6795215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6796215976Sjmallett info.enable_mask = 1ull<<8 /* nt_po_e */; 6797215976Sjmallett info.flags = 0; 6798215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6799215976Sjmallett info.group_index = 0; 6800215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6801215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6802215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6803215976Sjmallett info.func = __cvmx_error_display; 6804215976Sjmallett info.user_info = (long) 6805215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n"; 6806215976Sjmallett fail |= cvmx_error_add(&info); 6807215976Sjmallett 6808215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6809215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6810215976Sjmallett info.status_mask = 1ull<<9 /* nt_pu_f */; 6811215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6812215976Sjmallett info.enable_mask = 1ull<<9 /* nt_pu_f */; 6813215976Sjmallett info.flags = 0; 6814215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6815215976Sjmallett info.group_index = 0; 6816215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6817215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6818215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6819215976Sjmallett info.func = __cvmx_error_display; 6820215976Sjmallett info.user_info = (long) 6821215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n"; 6822215976Sjmallett fail |= cvmx_error_add(&info); 6823215976Sjmallett 6824215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6825215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6826215976Sjmallett info.status_mask = 1ull<<10 /* lt_po_e */; 6827215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6828215976Sjmallett info.enable_mask = 1ull<<10 /* lt_po_e */; 6829215976Sjmallett info.flags = 0; 6830215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6831215976Sjmallett info.group_index = 0; 6832215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6833215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6834215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6835215976Sjmallett info.func = __cvmx_error_display; 6836215976Sjmallett info.user_info = (long) 6837215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n"; 6838215976Sjmallett fail |= cvmx_error_add(&info); 6839215976Sjmallett 6840215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6841215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6842215976Sjmallett info.status_mask = 1ull<<11 /* lt_pu_f */; 6843215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6844215976Sjmallett info.enable_mask = 1ull<<11 /* lt_pu_f */; 6845215976Sjmallett info.flags = 0; 6846215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6847215976Sjmallett info.group_index = 0; 6848215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6849215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6850215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6851215976Sjmallett info.func = __cvmx_error_display; 6852215976Sjmallett info.user_info = (long) 6853215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n"; 6854215976Sjmallett fail |= cvmx_error_add(&info); 6855215976Sjmallett 6856215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6857215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6858215976Sjmallett info.status_mask = 1ull<<12 /* dcred_e */; 6859215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6860215976Sjmallett info.enable_mask = 1ull<<12 /* dcred_e */; 6861215976Sjmallett info.flags = 0; 6862215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6863215976Sjmallett info.group_index = 0; 6864215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6865215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6866215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6867215976Sjmallett info.func = __cvmx_error_display; 6868215976Sjmallett info.user_info = (long) 6869215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n"; 6870215976Sjmallett fail |= cvmx_error_add(&info); 6871215976Sjmallett 6872215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6873215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6874215976Sjmallett info.status_mask = 1ull<<13 /* dcred_f */; 6875215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6876215976Sjmallett info.enable_mask = 1ull<<13 /* dcred_f */; 6877215976Sjmallett info.flags = 0; 6878215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6879215976Sjmallett info.group_index = 0; 6880215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6881215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6882215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6883215976Sjmallett info.func = __cvmx_error_display; 6884215976Sjmallett info.user_info = (long) 6885215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n"; 6886215976Sjmallett fail |= cvmx_error_add(&info); 6887215976Sjmallett 6888215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6889215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6890215976Sjmallett info.status_mask = 1ull<<14 /* l2c_s_e */; 6891215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6892215976Sjmallett info.enable_mask = 1ull<<14 /* l2c_s_e */; 6893215976Sjmallett info.flags = 0; 6894215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6895215976Sjmallett info.group_index = 0; 6896215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6897215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6898215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6899215976Sjmallett info.func = __cvmx_error_display; 6900215976Sjmallett info.user_info = (long) 6901215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n"; 6902215976Sjmallett fail |= cvmx_error_add(&info); 6903215976Sjmallett 6904215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6905215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6906215976Sjmallett info.status_mask = 1ull<<15 /* l2c_a_f */; 6907215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6908215976Sjmallett info.enable_mask = 1ull<<15 /* l2c_a_f */; 6909215976Sjmallett info.flags = 0; 6910215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6911215976Sjmallett info.group_index = 0; 6912215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6913215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6914215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6915215976Sjmallett info.func = __cvmx_error_display; 6916215976Sjmallett info.user_info = (long) 6917215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n"; 6918215976Sjmallett fail |= cvmx_error_add(&info); 6919215976Sjmallett 6920215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6921215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6922215976Sjmallett info.status_mask = 1ull<<16 /* lt_fi_e */; 6923215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6924215976Sjmallett info.enable_mask = 1ull<<16 /* l2_fi_e */; 6925215976Sjmallett info.flags = 0; 6926215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6927215976Sjmallett info.group_index = 0; 6928215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6929215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6930215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6931215976Sjmallett info.func = __cvmx_error_display; 6932215976Sjmallett info.user_info = (long) 6933215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n"; 6934215976Sjmallett fail |= cvmx_error_add(&info); 6935215976Sjmallett 6936215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6937215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6938215976Sjmallett info.status_mask = 1ull<<17 /* lt_fi_f */; 6939215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6940215976Sjmallett info.enable_mask = 1ull<<17 /* l2_fi_f */; 6941215976Sjmallett info.flags = 0; 6942215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6943215976Sjmallett info.group_index = 0; 6944215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6945215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6946215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6947215976Sjmallett info.func = __cvmx_error_display; 6948215976Sjmallett info.user_info = (long) 6949215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n"; 6950215976Sjmallett fail |= cvmx_error_add(&info); 6951215976Sjmallett 6952215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6953215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6954215976Sjmallett info.status_mask = 1ull<<18 /* rg_fi_e */; 6955215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6956215976Sjmallett info.enable_mask = 1ull<<18 /* rg_fi_e */; 6957215976Sjmallett info.flags = 0; 6958215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6959215976Sjmallett info.group_index = 0; 6960215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6961215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6962215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6963215976Sjmallett info.func = __cvmx_error_display; 6964215976Sjmallett info.user_info = (long) 6965215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n"; 6966215976Sjmallett fail |= cvmx_error_add(&info); 6967215976Sjmallett 6968215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6969215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6970215976Sjmallett info.status_mask = 1ull<<19 /* rg_fi_f */; 6971215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6972215976Sjmallett info.enable_mask = 1ull<<19 /* rg_fi_f */; 6973215976Sjmallett info.flags = 0; 6974215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6975215976Sjmallett info.group_index = 0; 6976215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6977215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6978215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6979215976Sjmallett info.func = __cvmx_error_display; 6980215976Sjmallett info.user_info = (long) 6981215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n"; 6982215976Sjmallett fail |= cvmx_error_add(&info); 6983215976Sjmallett 6984215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6985215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6986215976Sjmallett info.status_mask = 1ull<<20 /* rq_q2_f */; 6987215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6988215976Sjmallett info.enable_mask = 1ull<<20 /* rq_q2_f */; 6989215976Sjmallett info.flags = 0; 6990215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6991215976Sjmallett info.group_index = 0; 6992215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6993215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6994215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6995215976Sjmallett info.func = __cvmx_error_display; 6996215976Sjmallett info.user_info = (long) 6997215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n"; 6998215976Sjmallett fail |= cvmx_error_add(&info); 6999215976Sjmallett 7000215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7001215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7002215976Sjmallett info.status_mask = 1ull<<21 /* rq_q2_e */; 7003215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7004215976Sjmallett info.enable_mask = 1ull<<21 /* rq_q2_e */; 7005215976Sjmallett info.flags = 0; 7006215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7007215976Sjmallett info.group_index = 0; 7008215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7009215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7010215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7011215976Sjmallett info.func = __cvmx_error_display; 7012215976Sjmallett info.user_info = (long) 7013215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n"; 7014215976Sjmallett fail |= cvmx_error_add(&info); 7015215976Sjmallett 7016215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7017215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7018215976Sjmallett info.status_mask = 1ull<<22 /* rq_q3_f */; 7019215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7020215976Sjmallett info.enable_mask = 1ull<<22 /* rq_q3_f */; 7021215976Sjmallett info.flags = 0; 7022215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7023215976Sjmallett info.group_index = 0; 7024215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7025215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7026215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7027215976Sjmallett info.func = __cvmx_error_display; 7028215976Sjmallett info.user_info = (long) 7029215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n"; 7030215976Sjmallett fail |= cvmx_error_add(&info); 7031215976Sjmallett 7032215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7033215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7034215976Sjmallett info.status_mask = 1ull<<23 /* rq_q3_e */; 7035215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7036215976Sjmallett info.enable_mask = 1ull<<23 /* rq_q3_e */; 7037215976Sjmallett info.flags = 0; 7038215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7039215976Sjmallett info.group_index = 0; 7040215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7041215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7042215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7043215976Sjmallett info.func = __cvmx_error_display; 7044215976Sjmallett info.user_info = (long) 7045215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n"; 7046215976Sjmallett fail |= cvmx_error_add(&info); 7047215976Sjmallett 7048215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7049215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7050215976Sjmallett info.status_mask = 1ull<<24 /* uod_pe */; 7051215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7052215976Sjmallett info.enable_mask = 1ull<<24 /* uod_pe */; 7053215976Sjmallett info.flags = 0; 7054215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7055215976Sjmallett info.group_index = 0; 7056215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7057215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7058215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7059215976Sjmallett info.func = __cvmx_error_display; 7060215976Sjmallett info.user_info = (long) 7061215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n"; 7062215976Sjmallett fail |= cvmx_error_add(&info); 7063215976Sjmallett 7064215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7065215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7066215976Sjmallett info.status_mask = 1ull<<25 /* uod_pf */; 7067215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7068215976Sjmallett info.enable_mask = 1ull<<25 /* uod_pf */; 7069215976Sjmallett info.flags = 0; 7070215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7071215976Sjmallett info.group_index = 0; 7072215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7073215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7074215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7075215976Sjmallett info.func = __cvmx_error_display; 7076215976Sjmallett info.user_info = (long) 7077215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n"; 7078215976Sjmallett fail |= cvmx_error_add(&info); 7079215976Sjmallett 7080215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7081215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7082215976Sjmallett info.status_mask = 1ull<<32 /* ltl_f_pe */; 7083215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7084215976Sjmallett info.enable_mask = 1ull<<32 /* ltl_f_pe */; 7085215976Sjmallett info.flags = 0; 7086215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7087215976Sjmallett info.group_index = 0; 7088215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7089215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7090215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7091215976Sjmallett info.func = __cvmx_error_display; 7092215976Sjmallett info.user_info = (long) 7093215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n"; 7094215976Sjmallett fail |= cvmx_error_add(&info); 7095215976Sjmallett 7096215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7097215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7098215976Sjmallett info.status_mask = 1ull<<33 /* ltl_f_pf */; 7099215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7100215976Sjmallett info.enable_mask = 1ull<<33 /* ltl_f_pf */; 7101215976Sjmallett info.flags = 0; 7102215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7103215976Sjmallett info.group_index = 0; 7104215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7105215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7106215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7107215976Sjmallett info.func = __cvmx_error_display; 7108215976Sjmallett info.user_info = (long) 7109215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n"; 7110215976Sjmallett fail |= cvmx_error_add(&info); 7111215976Sjmallett 7112215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7113215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7114215976Sjmallett info.status_mask = 1ull<<34 /* nd4o_rpe */; 7115215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7116215976Sjmallett info.enable_mask = 1ull<<34 /* nd4o_rpe */; 7117215976Sjmallett info.flags = 0; 7118215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7119215976Sjmallett info.group_index = 0; 7120215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7121215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7122215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7123215976Sjmallett info.func = __cvmx_error_display; 7124215976Sjmallett info.user_info = (long) 7125215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n"; 7126215976Sjmallett fail |= cvmx_error_add(&info); 7127215976Sjmallett 7128215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7129215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7130215976Sjmallett info.status_mask = 1ull<<35 /* nd4o_rpf */; 7131215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7132215976Sjmallett info.enable_mask = 1ull<<35 /* nd4o_rpf */; 7133215976Sjmallett info.flags = 0; 7134215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7135215976Sjmallett info.group_index = 0; 7136215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7137215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7138215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7139215976Sjmallett info.func = __cvmx_error_display; 7140215976Sjmallett info.user_info = (long) 7141215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n"; 7142215976Sjmallett fail |= cvmx_error_add(&info); 7143215976Sjmallett 7144215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7145215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7146215976Sjmallett info.status_mask = 1ull<<36 /* nd4o_dpe */; 7147215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7148215976Sjmallett info.enable_mask = 1ull<<36 /* nd4o_dpe */; 7149215976Sjmallett info.flags = 0; 7150215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7151215976Sjmallett info.group_index = 0; 7152215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7153215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7154215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7155215976Sjmallett info.func = __cvmx_error_display; 7156215976Sjmallett info.user_info = (long) 7157215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n"; 7158215976Sjmallett fail |= cvmx_error_add(&info); 7159215976Sjmallett 7160215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7161215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7162215976Sjmallett info.status_mask = 1ull<<37 /* nd4o_dpf */; 7163215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7164215976Sjmallett info.enable_mask = 1ull<<37 /* nd4o_dpf */; 7165215976Sjmallett info.flags = 0; 7166215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7167215976Sjmallett info.group_index = 0; 7168215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7169215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7170215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7171215976Sjmallett info.func = __cvmx_error_display; 7172215976Sjmallett info.user_info = (long) 7173215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n"; 7174215976Sjmallett fail |= cvmx_error_add(&info); 7175215976Sjmallett 7176215976Sjmallett return fail; 7177215976Sjmallett} 7178215976Sjmallett 7179