1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * @file 43215976Sjmallett * 44215976Sjmallett * Automatically generated error messages for cn56xx. 45215976Sjmallett * 46215976Sjmallett * This file is auto generated. Do not edit. 47215976Sjmallett * 48215976Sjmallett * <hr>$Revision$<hr> 49215976Sjmallett * 50215976Sjmallett * <hr><h2>Error tree for CN56XX</h2> 51215976Sjmallett * @dot 52215976Sjmallett * digraph cn56xx 53215976Sjmallett * { 54215976Sjmallett * rankdir=LR; 55215976Sjmallett * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica]; 56215976Sjmallett * edge [fontsize=7, font=helvitica]; 57215976Sjmallett * cvmx_root [label="ROOT|<root>root"]; 58215976Sjmallett * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"]; 59215976Sjmallett * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"]; 60215976Sjmallett * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"]; 61215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"]; 62215976Sjmallett * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"]; 63215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"]; 64215976Sjmallett * cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<tim>tim|<pko>pko|<pow>pow|<npei>npei|<rad>rad|<lmc1>lmc1|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<zip>zip|<usb>usb"]; 65215976Sjmallett * cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"]; 66215976Sjmallett * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"]; 67215976Sjmallett * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"]; 68215976Sjmallett * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"]; 69215976Sjmallett * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"]; 70215976Sjmallett * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"]; 71215976Sjmallett * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<out_ovr>out_ovr|<loststat>loststat"]; 72215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"]; 73215976Sjmallett * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"]; 74215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"]; 75215976Sjmallett * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"]; 76215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"]; 77215976Sjmallett * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 78215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"]; 79215976Sjmallett * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 80215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"]; 81215976Sjmallett * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 82215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"]; 83215976Sjmallett * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 84215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"]; 85215976Sjmallett * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 86215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"]; 87215976Sjmallett * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"]; 88215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"]; 89215976Sjmallett * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 90215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"]; 91215976Sjmallett * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 92215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"]; 93215976Sjmallett * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 94215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"]; 95215976Sjmallett * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 96215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"]; 97215976Sjmallett * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 98215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"]; 99215976Sjmallett * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw"]; 100215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"]; 101215976Sjmallett * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"]; 102215976Sjmallett * cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"]; 103215976Sjmallett * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"]; 104215976Sjmallett * cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"]; 105215976Sjmallett * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"]; 106215976Sjmallett * cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"]; 107215976Sjmallett * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"]; 108215976Sjmallett * cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"]; 109215976Sjmallett * cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"]; 110215976Sjmallett * cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"]; 111215976Sjmallett * cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"]; 112215976Sjmallett * cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"]; 113215976Sjmallett * cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"]; 114215976Sjmallett * cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"]; 115215976Sjmallett * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"]; 116215976Sjmallett * cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"]; 117215976Sjmallett * cvmx_lmc1_mem_cfg0 [label="LMCX_MEM_CFG0(1)|<sec_err>sec_err|<ded_err>ded_err"]; 118215976Sjmallett * cvmx_npei_rsl_int_blocks:lmc1:e -> cvmx_lmc1_mem_cfg0 [label="lmc1"]; 119215976Sjmallett * cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 120215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"]; 121215976Sjmallett * cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 122215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"]; 123215976Sjmallett * cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 124215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"]; 125215976Sjmallett * cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 126215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"]; 127215976Sjmallett * cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"]; 128215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"]; 129215976Sjmallett * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 130215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"]; 131215976Sjmallett * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 132215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"]; 133215976Sjmallett * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 134215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"]; 135215976Sjmallett * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 136215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"]; 137215976Sjmallett * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"]; 138215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"]; 139215976Sjmallett * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"]; 140215976Sjmallett * cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"]; 141215976Sjmallett * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"]; 142215976Sjmallett * cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"]; 143215976Sjmallett * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"]; 144215976Sjmallett * cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"]; 145215976Sjmallett * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"]; 146215976Sjmallett * cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"]; 147215976Sjmallett * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"]; 148215976Sjmallett * cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"]; 149215976Sjmallett * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"]; 150215976Sjmallett * cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"]; 151215976Sjmallett * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"]; 152215976Sjmallett * cvmx_npei_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"]; 153215976Sjmallett * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"]; 154215976Sjmallett * cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"]; 155215976Sjmallett * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis]; 156215976Sjmallett * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis]; 157215976Sjmallett * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis]; 158215976Sjmallett * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis]; 159215976Sjmallett * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis]; 160215976Sjmallett * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis]; 161215976Sjmallett * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis]; 162215976Sjmallett * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis]; 163215976Sjmallett * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis]; 164215976Sjmallett * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis]; 165215976Sjmallett * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis]; 166215976Sjmallett * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis]; 167215976Sjmallett * cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis]; 168215976Sjmallett * cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis]; 169215976Sjmallett * cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis]; 170215976Sjmallett * cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis]; 171215976Sjmallett * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis]; 172215976Sjmallett * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis]; 173215976Sjmallett * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis]; 174215976Sjmallett * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis]; 175215976Sjmallett * cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"]; 176215976Sjmallett * } 177215976Sjmallett * @enddot 178215976Sjmallett */ 179215976Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 180215976Sjmallett#include <asm/octeon/cvmx.h> 181215976Sjmallett#include <asm/octeon/cvmx-error.h> 182215976Sjmallett#include <asm/octeon/cvmx-error-custom.h> 183215976Sjmallett#include <asm/octeon/cvmx-csr-typedefs.h> 184215976Sjmallett#else 185215976Sjmallett#include "cvmx.h" 186215976Sjmallett#include "cvmx-error.h" 187215976Sjmallett#include "cvmx-error-custom.h" 188215976Sjmallett#endif 189215976Sjmallett 190215990Sjmallettint cvmx_error_initialize_cn56xx(void); 191215990Sjmallett 192215976Sjmallettint cvmx_error_initialize_cn56xx(void) 193215976Sjmallett{ 194215976Sjmallett cvmx_error_info_t info; 195215976Sjmallett int fail = 0; 196215976Sjmallett 197215976Sjmallett /* CVMX_CIU_INTX_SUM0(0) */ 198215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 199215976Sjmallett info.status_addr = CVMX_CIU_INTX_SUM0(0); 200215976Sjmallett info.status_mask = 0; 201215976Sjmallett info.enable_addr = 0; 202215976Sjmallett info.enable_mask = 0; 203215976Sjmallett info.flags = 0; 204215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 205215976Sjmallett info.group_index = 0; 206215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 207215976Sjmallett info.parent.status_addr = 0; 208215976Sjmallett info.parent.status_mask = 0; 209215976Sjmallett info.func = __cvmx_error_decode; 210215976Sjmallett info.user_info = 0; 211215976Sjmallett fail |= cvmx_error_add(&info); 212215976Sjmallett 213215976Sjmallett /* CVMX_MIXX_ISR(0) */ 214215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 215215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 216215976Sjmallett info.status_mask = 1ull<<0 /* odblovf */; 217215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 218215976Sjmallett info.enable_mask = 1ull<<0 /* ovfena */; 219215976Sjmallett info.flags = 0; 220215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 221215976Sjmallett info.group_index = 0; 222215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 223215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 224215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 225215976Sjmallett info.func = __cvmx_error_display; 226215976Sjmallett info.user_info = (long) 227215976Sjmallett "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n" 228215976Sjmallett " If SW attempts to write to the MIX_ORING2[ODBELL]\n" 229215976Sjmallett " with a value greater than the remaining #of\n" 230215976Sjmallett " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n" 231215976Sjmallett " the following occurs:\n" 232215976Sjmallett " 1) The MIX_ORING2[ODBELL] write is IGNORED\n" 233215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 234215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 235215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 236215976Sjmallett " and the local interrupt mask bit(OVFENA) is set, than an\n" 237215976Sjmallett " interrupt is reported for this event.\n" 238215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 239215976Sjmallett " (ie: cumulative # of ODBELL writes), and ensure that\n" 240215976Sjmallett " future ODBELL writes don't exceed the size of the\n" 241215976Sjmallett " O-Ring Buffer (MIX_ORING2[OSIZE]).\n" 242215976Sjmallett " SW must reclaim O-Ring Entries by writing to the\n" 243215976Sjmallett " MIX_ORCNT[ORCNT]. .\n" 244215976Sjmallett " NOTE: There is no recovery from an ODBLOVF Interrupt.\n" 245215976Sjmallett " If it occurs, it's an indication that SW has\n" 246215976Sjmallett " overwritten the O-Ring buffer, and the only recourse\n" 247215976Sjmallett " is a HW reset.\n"; 248215976Sjmallett fail |= cvmx_error_add(&info); 249215976Sjmallett 250215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 251215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 252215976Sjmallett info.status_mask = 1ull<<1 /* idblovf */; 253215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 254215976Sjmallett info.enable_mask = 1ull<<1 /* ivfena */; 255215976Sjmallett info.flags = 0; 256215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 257215976Sjmallett info.group_index = 0; 258215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 259215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 260215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 261215976Sjmallett info.func = __cvmx_error_display; 262215976Sjmallett info.user_info = (long) 263215976Sjmallett "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n" 264215976Sjmallett " If SW attempts to write to the MIX_IRING2[IDBELL]\n" 265215976Sjmallett " with a value greater than the remaining #of\n" 266215976Sjmallett " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n" 267215976Sjmallett " the following occurs:\n" 268215976Sjmallett " 1) The MIX_IRING2[IDBELL] write is IGNORED\n" 269215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 270215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 271215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 272215976Sjmallett " and the local interrupt mask bit(IVFENA) is set, than an\n" 273215976Sjmallett " interrupt is reported for this event.\n" 274215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 275215976Sjmallett " (ie: cumulative # of IDBELL writes), and ensure that\n" 276215976Sjmallett " future IDBELL writes don't exceed the size of the\n" 277215976Sjmallett " I-Ring Buffer (MIX_IRING2[ISIZE]).\n" 278215976Sjmallett " SW must reclaim I-Ring Entries by keeping track of the\n" 279215976Sjmallett " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n" 280215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] register represents the\n" 281215976Sjmallett " total #packets(not IRing Entries) and SW must further\n" 282215976Sjmallett " keep track of the # of I-Ring Entries associated with\n" 283215976Sjmallett " each packet as they are processed.\n" 284215976Sjmallett " NOTE: There is no recovery from an IDBLOVF Interrupt.\n" 285215976Sjmallett " If it occurs, it's an indication that SW has\n" 286215976Sjmallett " overwritten the I-Ring buffer, and the only recourse\n" 287215976Sjmallett " is a HW reset.\n"; 288215976Sjmallett fail |= cvmx_error_add(&info); 289215976Sjmallett 290215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 291215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 292215976Sjmallett info.status_mask = 1ull<<4 /* data_drp */; 293215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 294215976Sjmallett info.enable_mask = 1ull<<4 /* data_drpena */; 295215976Sjmallett info.flags = 0; 296215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 297215976Sjmallett info.group_index = 0; 298215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 299215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 300215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 301215976Sjmallett info.func = __cvmx_error_display; 302215976Sjmallett info.user_info = (long) 303215976Sjmallett "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n" 304215976Sjmallett " If this does occur, the DATA_DRP is set and the\n" 305215976Sjmallett " CIU_INTx_SUM0,4[MII] bits are set.\n" 306215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 307215976Sjmallett " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n" 308215976Sjmallett " interrupt is reported for this event.\n"; 309215976Sjmallett fail |= cvmx_error_add(&info); 310215976Sjmallett 311215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 312215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 313215976Sjmallett info.status_mask = 1ull<<5 /* irun */; 314215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 315215976Sjmallett info.enable_mask = 1ull<<5 /* irunena */; 316215976Sjmallett info.flags = 0; 317215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 318215976Sjmallett info.group_index = 0; 319215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 320215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 321215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 322215976Sjmallett info.func = __cvmx_error_display; 323215976Sjmallett info.user_info = (long) 324215976Sjmallett "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n" 325215976Sjmallett " If SW writes a larger value than what is currently\n" 326215976Sjmallett " in the MIX_IRCNT[IRCNT], then HW will report the\n" 327215976Sjmallett " underflow condition.\n" 328215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n" 329215976Sjmallett " NOTE: If an IRUN underflow condition is detected,\n" 330215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 331215976Sjmallett " been compromised. To recover, SW must issue a\n" 332215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 333215976Sjmallett fail |= cvmx_error_add(&info); 334215976Sjmallett 335215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 336215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 337215976Sjmallett info.status_mask = 1ull<<6 /* orun */; 338215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 339215976Sjmallett info.enable_mask = 1ull<<6 /* orunena */; 340215976Sjmallett info.flags = 0; 341215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 342215976Sjmallett info.group_index = 0; 343215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 344215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 345215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 346215976Sjmallett info.func = __cvmx_error_display; 347215976Sjmallett info.user_info = (long) 348215976Sjmallett "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n" 349215976Sjmallett " If SW writes a larger value than what is currently\n" 350215976Sjmallett " in the MIX_ORCNT[ORCNT], then HW will report the\n" 351215976Sjmallett " underflow condition.\n" 352215976Sjmallett " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n" 353215976Sjmallett " NOTE: If an ORUN underflow condition is detected,\n" 354215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 355215976Sjmallett " been compromised. To recover, SW must issue a\n" 356215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 357215976Sjmallett fail |= cvmx_error_add(&info); 358215976Sjmallett 359215976Sjmallett /* CVMX_CIU_INT_SUM1 */ 360215976Sjmallett /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */ 361215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 362215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 363215976Sjmallett info.status_mask = 0; 364215976Sjmallett info.enable_addr = 0; 365215976Sjmallett info.enable_mask = 0; 366215976Sjmallett info.flags = 0; 367215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 368215976Sjmallett info.group_index = 0; 369215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 370215976Sjmallett info.parent.status_addr = 0; 371215976Sjmallett info.parent.status_mask = 0; 372215976Sjmallett info.func = __cvmx_error_decode; 373215976Sjmallett info.user_info = 0; 374215976Sjmallett fail |= cvmx_error_add(&info); 375215976Sjmallett 376215976Sjmallett /* CVMX_L2C_INT_STAT */ 377215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 378215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 379215976Sjmallett info.status_mask = 1ull<<3 /* l2tsec */; 380215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 381215976Sjmallett info.enable_mask = 1ull<<3 /* l2tsecen */; 382215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 383215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 384215976Sjmallett info.group_index = 0; 385215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 386215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 387215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 388215976Sjmallett info.func = __cvmx_error_display; 389215976Sjmallett info.user_info = (long) 390215976Sjmallett "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n" 391215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 392215976Sjmallett " given index) are checked for single bit errors(SBEs).\n" 393215976Sjmallett " This bit is set if ANY of the 8 sets contains an SBE.\n" 394215976Sjmallett " SBEs are auto corrected in HW and generate an\n" 395215976Sjmallett " interrupt(if enabled).\n" 396215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n"; 397215976Sjmallett fail |= cvmx_error_add(&info); 398215976Sjmallett 399215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 400215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 401215976Sjmallett info.status_mask = 1ull<<5 /* l2dsec */; 402215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 403215976Sjmallett info.enable_mask = 1ull<<5 /* l2dsecen */; 404215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 405215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 406215976Sjmallett info.group_index = 0; 407215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 408215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 409215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 410215976Sjmallett info.func = __cvmx_error_display; 411215976Sjmallett info.user_info = (long) 412215976Sjmallett "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n" 413215976Sjmallett " NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n"; 414215976Sjmallett fail |= cvmx_error_add(&info); 415215976Sjmallett 416215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 417215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 418215976Sjmallett info.status_mask = 1ull<<0 /* oob1 */; 419215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 420215976Sjmallett info.enable_mask = 1ull<<0 /* oob1en */; 421215976Sjmallett info.flags = 0; 422215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 423215976Sjmallett info.group_index = 0; 424215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 425215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 426215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 427215976Sjmallett info.func = __cvmx_error_display; 428215976Sjmallett info.user_info = (long) 429215976Sjmallett "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n"; 430215976Sjmallett fail |= cvmx_error_add(&info); 431215976Sjmallett 432215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 433215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 434215976Sjmallett info.status_mask = 1ull<<1 /* oob2 */; 435215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 436215976Sjmallett info.enable_mask = 1ull<<1 /* oob2en */; 437215976Sjmallett info.flags = 0; 438215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 439215976Sjmallett info.group_index = 0; 440215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 441215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 442215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 443215976Sjmallett info.func = __cvmx_error_display; 444215976Sjmallett info.user_info = (long) 445215976Sjmallett "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n"; 446215976Sjmallett fail |= cvmx_error_add(&info); 447215976Sjmallett 448215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 449215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 450215976Sjmallett info.status_mask = 1ull<<2 /* oob3 */; 451215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 452215976Sjmallett info.enable_mask = 1ull<<2 /* oob3en */; 453215976Sjmallett info.flags = 0; 454215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 455215976Sjmallett info.group_index = 0; 456215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 457215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 458215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 459215976Sjmallett info.func = __cvmx_error_display; 460215976Sjmallett info.user_info = (long) 461215976Sjmallett "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n"; 462215976Sjmallett fail |= cvmx_error_add(&info); 463215976Sjmallett 464215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 465215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 466215976Sjmallett info.status_mask = 1ull<<4 /* l2tded */; 467215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 468215976Sjmallett info.enable_mask = 1ull<<4 /* l2tdeden */; 469215976Sjmallett info.flags = 0; 470215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 471215976Sjmallett info.group_index = 0; 472215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 473215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 474215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 475215976Sjmallett info.func = __cvmx_error_display; 476215976Sjmallett info.user_info = (long) 477215976Sjmallett "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n" 478215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 479215976Sjmallett " given index) are checked for double bit errors(DBEs).\n" 480215976Sjmallett " This bit is set if ANY of the 8 sets contains a DBE.\n" 481215976Sjmallett " DBEs also generated an interrupt(if enabled).\n" 482215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n"; 483215976Sjmallett fail |= cvmx_error_add(&info); 484215976Sjmallett 485215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 486215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 487215976Sjmallett info.status_mask = 1ull<<6 /* l2dded */; 488215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 489215976Sjmallett info.enable_mask = 1ull<<6 /* l2ddeden */; 490215976Sjmallett info.flags = 0; 491215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 492215976Sjmallett info.group_index = 0; 493215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 494215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 495215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 496215976Sjmallett info.func = __cvmx_error_display; 497215976Sjmallett info.user_info = (long) 498215976Sjmallett "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n" 499215976Sjmallett " NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n"; 500215976Sjmallett fail |= cvmx_error_add(&info); 501215976Sjmallett 502215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 503215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 504215976Sjmallett info.status_mask = 1ull<<7 /* lck */; 505215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 506215976Sjmallett info.enable_mask = 1ull<<7 /* lckena */; 507215976Sjmallett info.flags = 0; 508215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 509215976Sjmallett info.group_index = 0; 510215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 511215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 512215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 513215976Sjmallett info.func = __cvmx_error_display; 514215976Sjmallett info.user_info = (long) 515215976Sjmallett "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n" 516215976Sjmallett " the INDEX (which is ignored by HW - but reported to SW).\n" 517215976Sjmallett " The LDD(L1 load-miss) for the LOCK operation is completed\n" 518215976Sjmallett " successfully, however the address is NOT locked.\n" 519215976Sjmallett " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n" 520215976Sjmallett " into account. For example, if diagnostic PPx has\n" 521215976Sjmallett " UMSKx defined to only use SETs [1:0], and SET1 had\n" 522215976Sjmallett " been previously LOCKED, then an attempt to LOCK the\n" 523215976Sjmallett " last available SET0 would result in a LCKERR. (This\n" 524215976Sjmallett " is to ensure that at least 1 SET at each INDEX is\n" 525215976Sjmallett " not LOCKED for general use by other PPs).\n" 526215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n"; 527215976Sjmallett fail |= cvmx_error_add(&info); 528215976Sjmallett 529215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 530215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 531215976Sjmallett info.status_mask = 1ull<<8 /* lck2 */; 532215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 533215976Sjmallett info.enable_mask = 1ull<<8 /* lck2ena */; 534215976Sjmallett info.flags = 0; 535215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 536215976Sjmallett info.group_index = 0; 537215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 538215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 539215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 540215976Sjmallett info.func = __cvmx_error_display; 541215976Sjmallett info.user_info = (long) 542215976Sjmallett "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n" 543215976Sjmallett " could not find an available/unlocked set (for\n" 544215976Sjmallett " replacement).\n" 545215976Sjmallett " Most likely, this is a result of SW mixing SET\n" 546215976Sjmallett " PARTITIONING with ADDRESS LOCKING. If SW allows\n" 547215976Sjmallett " another PP to LOCKDOWN all SETs available to PP#n,\n" 548215976Sjmallett " then a Rd/Wr Miss from PP#n will be unable\n" 549215976Sjmallett " to determine a 'valid' replacement set (since LOCKED\n" 550215976Sjmallett " addresses should NEVER be replaced).\n" 551215976Sjmallett " If such an event occurs, the HW will select the smallest\n" 552215976Sjmallett " available SET(specified by UMSK'x)' as the replacement\n" 553215976Sjmallett " set, and the address is unlocked.\n" 554215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n"; 555215976Sjmallett fail |= cvmx_error_add(&info); 556215976Sjmallett 557215976Sjmallett /* CVMX_L2D_ERR */ 558215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 559215976Sjmallett info.status_addr = CVMX_L2D_ERR; 560215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 561215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 562215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 563215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 564215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 565215976Sjmallett info.group_index = 0; 566215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 567215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 568215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 569215976Sjmallett info.func = __cvmx_error_handle_l2d_err_sec_err; 570215976Sjmallett info.user_info = (long) 571215976Sjmallett "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n"; 572215976Sjmallett fail |= cvmx_error_add(&info); 573215976Sjmallett 574215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 575215976Sjmallett info.status_addr = CVMX_L2D_ERR; 576215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 577215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 578215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 579215976Sjmallett info.flags = 0; 580215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 581215976Sjmallett info.group_index = 0; 582215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 583215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 584215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 585215976Sjmallett info.func = __cvmx_error_handle_l2d_err_ded_err; 586215976Sjmallett info.user_info = (long) 587215976Sjmallett "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n"; 588215976Sjmallett fail |= cvmx_error_add(&info); 589215976Sjmallett 590215976Sjmallett /* CVMX_L2T_ERR */ 591215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 592215976Sjmallett info.status_addr = CVMX_L2T_ERR; 593215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 594215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 595215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 596215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 597215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 598215976Sjmallett info.group_index = 0; 599215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 600215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 601215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 602215976Sjmallett info.func = __cvmx_error_handle_l2t_err_sec_err; 603215976Sjmallett info.user_info = (long) 604215976Sjmallett "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n" 605215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 606215976Sjmallett " given index) are checked for single bit errors(SBEs).\n" 607215976Sjmallett " This bit is set if ANY of the 8 sets contains an SBE.\n" 608215976Sjmallett " SBEs are auto corrected in HW and generate an\n" 609215976Sjmallett " interrupt(if enabled).\n"; 610215976Sjmallett fail |= cvmx_error_add(&info); 611215976Sjmallett 612215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 613215976Sjmallett info.status_addr = CVMX_L2T_ERR; 614215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 615215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 616215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 617215976Sjmallett info.flags = 0; 618215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 619215976Sjmallett info.group_index = 0; 620215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 621215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 622215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 623215976Sjmallett info.func = __cvmx_error_handle_l2t_err_ded_err; 624215976Sjmallett info.user_info = (long) 625215976Sjmallett "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n" 626215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 627215976Sjmallett " given index) are checked for double bit errors(DBEs).\n" 628215976Sjmallett " This bit is set if ANY of the 8 sets contains a DBE.\n" 629215976Sjmallett " DBEs also generated an interrupt(if enabled).\n"; 630215976Sjmallett fail |= cvmx_error_add(&info); 631215976Sjmallett 632215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 633215976Sjmallett info.status_addr = CVMX_L2T_ERR; 634215976Sjmallett info.status_mask = 1ull<<24 /* lckerr */; 635215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 636215976Sjmallett info.enable_mask = 1ull<<25 /* lck_intena */; 637215976Sjmallett info.flags = 0; 638215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 639215976Sjmallett info.group_index = 0; 640215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 641215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 642215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 643215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr; 644215976Sjmallett info.user_info = (long) 645215976Sjmallett "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n" 646215976Sjmallett " the INDEX (which is ignored by HW - but reported to SW).\n" 647215976Sjmallett " The LDD(L1 load-miss) for the LOCK operation is completed\n" 648215976Sjmallett " successfully, however the address is NOT locked.\n" 649215976Sjmallett " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n" 650215976Sjmallett " into account. For example, if diagnostic PPx has\n" 651215976Sjmallett " UMSKx defined to only use SETs [1:0], and SET1 had\n" 652215976Sjmallett " been previously LOCKED, then an attempt to LOCK the\n" 653215976Sjmallett " last available SET0 would result in a LCKERR. (This\n" 654215976Sjmallett " is to ensure that at least 1 SET at each INDEX is\n" 655215976Sjmallett " not LOCKED for general use by other PPs).\n"; 656215976Sjmallett fail |= cvmx_error_add(&info); 657215976Sjmallett 658215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 659215976Sjmallett info.status_addr = CVMX_L2T_ERR; 660215976Sjmallett info.status_mask = 1ull<<26 /* lckerr2 */; 661215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 662215976Sjmallett info.enable_mask = 1ull<<27 /* lck_intena2 */; 663215976Sjmallett info.flags = 0; 664215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 665215976Sjmallett info.group_index = 0; 666215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 667215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 668215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 669215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr2; 670215976Sjmallett info.user_info = (long) 671215976Sjmallett "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n" 672215976Sjmallett " could not find an available/unlocked set (for\n" 673215976Sjmallett " replacement).\n" 674215976Sjmallett " Most likely, this is a result of SW mixing SET\n" 675215976Sjmallett " PARTITIONING with ADDRESS LOCKING. If SW allows\n" 676215976Sjmallett " another PP to LOCKDOWN all SETs available to PP#n,\n" 677215976Sjmallett " then a Rd/Wr Miss from PP#n will be unable\n" 678215976Sjmallett " to determine a 'valid' replacement set (since LOCKED\n" 679215976Sjmallett " addresses should NEVER be replaced).\n" 680215976Sjmallett " If such an event occurs, the HW will select the smallest\n" 681215976Sjmallett " available SET(specified by UMSK'x)' as the replacement\n" 682215976Sjmallett " set, and the address is unlocked.\n"; 683215976Sjmallett fail |= cvmx_error_add(&info); 684215976Sjmallett 685215976Sjmallett /* CVMX_AGL_GMX_BAD_REG */ 686215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 687215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 688215976Sjmallett info.status_mask = 1ull<<32 /* ovrflw */; 689215976Sjmallett info.enable_addr = 0; 690215976Sjmallett info.enable_mask = 0; 691215976Sjmallett info.flags = 0; 692215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 693215976Sjmallett info.group_index = 0; 694215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 695215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 696215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 697215976Sjmallett info.func = __cvmx_error_display; 698215976Sjmallett info.user_info = (long) 699215976Sjmallett "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow\n"; 700215976Sjmallett fail |= cvmx_error_add(&info); 701215976Sjmallett 702215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 703215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 704215976Sjmallett info.status_mask = 1ull<<33 /* txpop */; 705215976Sjmallett info.enable_addr = 0; 706215976Sjmallett info.enable_mask = 0; 707215976Sjmallett info.flags = 0; 708215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 709215976Sjmallett info.group_index = 0; 710215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 711215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 712215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 713215976Sjmallett info.func = __cvmx_error_display; 714215976Sjmallett info.user_info = (long) 715215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow\n"; 716215976Sjmallett fail |= cvmx_error_add(&info); 717215976Sjmallett 718215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 719215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 720215976Sjmallett info.status_mask = 1ull<<34 /* txpsh */; 721215976Sjmallett info.enable_addr = 0; 722215976Sjmallett info.enable_mask = 0; 723215976Sjmallett info.flags = 0; 724215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 725215976Sjmallett info.group_index = 0; 726215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 727215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 728215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 729215976Sjmallett info.func = __cvmx_error_display; 730215976Sjmallett info.user_info = (long) 731215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow\n"; 732215976Sjmallett fail |= cvmx_error_add(&info); 733215976Sjmallett 734215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 735215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 736215976Sjmallett info.status_mask = 1ull<<2 /* out_ovr */; 737215976Sjmallett info.enable_addr = 0; 738215976Sjmallett info.enable_mask = 0; 739215976Sjmallett info.flags = 0; 740215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 741215976Sjmallett info.group_index = 0; 742215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 743215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 744215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 745215976Sjmallett info.func = __cvmx_error_display; 746215976Sjmallett info.user_info = (long) 747215976Sjmallett "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n"; 748215976Sjmallett fail |= cvmx_error_add(&info); 749215976Sjmallett 750215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 751215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 752215976Sjmallett info.status_mask = 1ull<<22 /* loststat */; 753215976Sjmallett info.enable_addr = 0; 754215976Sjmallett info.enable_mask = 0; 755215976Sjmallett info.flags = 0; 756215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 757215976Sjmallett info.group_index = 0; 758215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 759215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 760215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 761215976Sjmallett info.func = __cvmx_error_display; 762215976Sjmallett info.user_info = (long) 763215976Sjmallett "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n" 764215976Sjmallett " TX Stats are corrupted\n"; 765215976Sjmallett fail |= cvmx_error_add(&info); 766215976Sjmallett 767215976Sjmallett /* CVMX_AGL_GMX_RXX_INT_REG(0) */ 768215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 769215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0); 770215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 771215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0); 772215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 773215976Sjmallett info.flags = 0; 774215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 775215976Sjmallett info.group_index = 0; 776215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 777215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 778215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 779215976Sjmallett info.func = __cvmx_error_display; 780215976Sjmallett info.user_info = (long) 781215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n"; 782215976Sjmallett fail |= cvmx_error_add(&info); 783215976Sjmallett 784215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 785215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0); 786215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 787215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0); 788215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 789215976Sjmallett info.flags = 0; 790215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 791215976Sjmallett info.group_index = 0; 792215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 793215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 794215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 795215976Sjmallett info.func = __cvmx_error_display; 796215976Sjmallett info.user_info = (long) 797215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n" 798215976Sjmallett " This interrupt should never assert\n"; 799215976Sjmallett fail |= cvmx_error_add(&info); 800215976Sjmallett 801215976Sjmallett /* CVMX_AGL_GMX_TX_INT_REG */ 802215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 803215976Sjmallett info.status_addr = CVMX_AGL_GMX_TX_INT_REG; 804215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 805215976Sjmallett info.enable_addr = CVMX_AGL_GMX_TX_INT_EN; 806215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 807215976Sjmallett info.flags = 0; 808215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 809215976Sjmallett info.group_index = 0; 810215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 811215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 812215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 813215976Sjmallett info.func = __cvmx_error_display; 814215976Sjmallett info.user_info = (long) 815215976Sjmallett "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 816215976Sjmallett fail |= cvmx_error_add(&info); 817215976Sjmallett 818215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 819215976Sjmallett info.status_addr = CVMX_AGL_GMX_TX_INT_REG; 820215976Sjmallett info.status_mask = 1ull<<2 /* undflw */; 821215976Sjmallett info.enable_addr = CVMX_AGL_GMX_TX_INT_EN; 822215976Sjmallett info.enable_mask = 1ull<<2 /* undflw */; 823215976Sjmallett info.flags = 0; 824215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 825215976Sjmallett info.group_index = 0; 826215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 827215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 828215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 829215976Sjmallett info.func = __cvmx_error_display; 830215976Sjmallett info.user_info = (long) 831215976Sjmallett "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n"; 832215976Sjmallett fail |= cvmx_error_add(&info); 833215976Sjmallett 834215976Sjmallett /* CVMX_GMXX_BAD_REG(0) */ 835215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 836215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 837215976Sjmallett info.status_mask = 0xfull<<2 /* out_ovr */; 838215976Sjmallett info.enable_addr = 0; 839215976Sjmallett info.enable_mask = 0; 840215976Sjmallett info.flags = 0; 841215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 842215976Sjmallett info.group_index = 0; 843215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 844215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 845215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 846215976Sjmallett info.func = __cvmx_error_display; 847215976Sjmallett info.user_info = (long) 848215976Sjmallett "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 849215976Sjmallett fail |= cvmx_error_add(&info); 850215976Sjmallett 851215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 852215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 853215976Sjmallett info.status_mask = 0xfull<<22 /* loststat */; 854215976Sjmallett info.enable_addr = 0; 855215976Sjmallett info.enable_mask = 0; 856215976Sjmallett info.flags = 0; 857215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 858215976Sjmallett info.group_index = 0; 859215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 860215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 861215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 862215976Sjmallett info.func = __cvmx_error_display; 863215976Sjmallett info.user_info = (long) 864215976Sjmallett "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n" 865215976Sjmallett " In SGMII, one bit per port\n" 866215976Sjmallett " In XAUI, only port0 is used\n" 867215976Sjmallett " TX Stats are corrupted\n"; 868215976Sjmallett fail |= cvmx_error_add(&info); 869215976Sjmallett 870215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 871215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 872215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 873215976Sjmallett info.enable_addr = 0; 874215976Sjmallett info.enable_mask = 0; 875215976Sjmallett info.flags = 0; 876215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 877215976Sjmallett info.group_index = 0; 878215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 879215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 880215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 881215976Sjmallett info.func = __cvmx_error_display; 882215976Sjmallett info.user_info = (long) 883215976Sjmallett "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n" 884215976Sjmallett " The common FIFO to SGMII and XAUI had an overflow\n" 885215976Sjmallett " TX Stats are corrupted\n"; 886215976Sjmallett fail |= cvmx_error_add(&info); 887215976Sjmallett 888215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 889215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 890215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 891215976Sjmallett info.enable_addr = 0; 892215976Sjmallett info.enable_mask = 0; 893215976Sjmallett info.flags = 0; 894215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 895215976Sjmallett info.group_index = 0; 896215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 897215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 898215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 899215976Sjmallett info.func = __cvmx_error_display; 900215976Sjmallett info.user_info = (long) 901215976Sjmallett "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 902215976Sjmallett fail |= cvmx_error_add(&info); 903215976Sjmallett 904215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,0) */ 905215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 906215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 907215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 908215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 909215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 910215976Sjmallett info.flags = 0; 911215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 912215976Sjmallett info.group_index = 0; 913215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 914215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 915215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 916215976Sjmallett info.func = __cvmx_error_display; 917215976Sjmallett info.user_info = (long) 918215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n" 919215976Sjmallett " (SGMII/1000Base-X only)\n"; 920215976Sjmallett fail |= cvmx_error_add(&info); 921215976Sjmallett 922215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 923215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 924215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 925215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 926215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 927215976Sjmallett info.flags = 0; 928215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 929215976Sjmallett info.group_index = 0; 930215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 931215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 932215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 933215976Sjmallett info.func = __cvmx_error_display; 934215976Sjmallett info.user_info = (long) 935215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n"; 936215976Sjmallett fail |= cvmx_error_add(&info); 937215976Sjmallett 938215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 939215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 940215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 941215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 942215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 943215976Sjmallett info.flags = 0; 944215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 945215976Sjmallett info.group_index = 0; 946215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 947215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 948215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 949215976Sjmallett info.func = __cvmx_error_display; 950215976Sjmallett info.user_info = (long) 951215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n" 952215976Sjmallett " This interrupt should never assert\n" 953215976Sjmallett " (SGMII/1000Base-X only)\n"; 954215976Sjmallett fail |= cvmx_error_add(&info); 955215976Sjmallett 956215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 957215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 958215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 959215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 960215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 961215976Sjmallett info.flags = 0; 962215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 963215976Sjmallett info.group_index = 0; 964215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 965215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 966215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 967215976Sjmallett info.func = __cvmx_error_display; 968215976Sjmallett info.user_info = (long) 969215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 970215976Sjmallett " (XAUI Mode only)\n"; 971215976Sjmallett fail |= cvmx_error_add(&info); 972215976Sjmallett 973215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 974215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 975215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 976215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 977215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 978215976Sjmallett info.flags = 0; 979215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 980215976Sjmallett info.group_index = 0; 981215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 982215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 983215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 984215976Sjmallett info.func = __cvmx_error_display; 985215976Sjmallett info.user_info = (long) 986215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 987215976Sjmallett " (XAUI Mode only)\n"; 988215976Sjmallett fail |= cvmx_error_add(&info); 989215976Sjmallett 990215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 991215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 992215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 993215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 994215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 995215976Sjmallett info.flags = 0; 996215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 997215976Sjmallett info.group_index = 0; 998215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 999215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1000215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1001215976Sjmallett info.func = __cvmx_error_display; 1002215976Sjmallett info.user_info = (long) 1003215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1004215976Sjmallett " (XAUI Mode only)\n"; 1005215976Sjmallett fail |= cvmx_error_add(&info); 1006215976Sjmallett 1007215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1008215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1009215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1010215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1011215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1012215976Sjmallett info.flags = 0; 1013215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1014215976Sjmallett info.group_index = 0; 1015215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1016215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1017215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1018215976Sjmallett info.func = __cvmx_error_display; 1019215976Sjmallett info.user_info = (long) 1020215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n" 1021215976Sjmallett " than /T/. The error propagation control\n" 1022215976Sjmallett " character /E/ will be included as part of the\n" 1023215976Sjmallett " frame and does not cause a frame termination.\n" 1024215976Sjmallett " (XAUI Mode only)\n"; 1025215976Sjmallett fail |= cvmx_error_add(&info); 1026215976Sjmallett 1027215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1028215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1029215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1030215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1031215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1032215976Sjmallett info.flags = 0; 1033215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1034215976Sjmallett info.group_index = 0; 1035215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1036215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1037215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1038215976Sjmallett info.func = __cvmx_error_display; 1039215976Sjmallett info.user_info = (long) 1040215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n" 1041215976Sjmallett " (XAUI Mode only)\n"; 1042215976Sjmallett fail |= cvmx_error_add(&info); 1043215976Sjmallett 1044215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1045215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1046215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1047215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1048215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1049215976Sjmallett info.flags = 0; 1050215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1051215976Sjmallett info.group_index = 0; 1052215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1053215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1054215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1055215976Sjmallett info.func = __cvmx_error_display; 1056215976Sjmallett info.user_info = (long) 1057215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n" 1058215976Sjmallett " (XAUI Mode only)\n"; 1059215976Sjmallett fail |= cvmx_error_add(&info); 1060215976Sjmallett 1061215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1062215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1063215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1064215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1065215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1066215976Sjmallett info.flags = 0; 1067215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1068215976Sjmallett info.group_index = 0; 1069215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1070215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1071215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1072215976Sjmallett info.func = __cvmx_error_display; 1073215976Sjmallett info.user_info = (long) 1074215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n" 1075215976Sjmallett " (XAUI Mode only)\n"; 1076215976Sjmallett fail |= cvmx_error_add(&info); 1077215976Sjmallett 1078215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1079215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1080215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 1081215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1082215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 1083215976Sjmallett info.flags = 0; 1084215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1085215976Sjmallett info.group_index = 0; 1086215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1087215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1088215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1089215976Sjmallett info.func = __cvmx_error_display; 1090215976Sjmallett info.user_info = (long) 1091215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n" 1092215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 1093215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 1094215976Sjmallett " is the only defined type for HiGig2\n" 1095215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 1096215976Sjmallett " which is the only defined type for HiGig2\n" 1097215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 1098215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 1099215976Sjmallett " Those are the only two defined types in HiGig2\n"; 1100215976Sjmallett fail |= cvmx_error_add(&info); 1101215976Sjmallett 1102215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1103215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1104215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 1105215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1106215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 1107215976Sjmallett info.flags = 0; 1108215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1109215976Sjmallett info.group_index = 0; 1110215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1111215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1112215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1113215976Sjmallett info.func = __cvmx_error_display; 1114215976Sjmallett info.user_info = (long) 1115215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 1116215976Sjmallett " Set when either CRC8 error detected or when\n" 1117215976Sjmallett " a Control Character is found in the message\n" 1118215976Sjmallett " bytes after the K.SOM\n" 1119215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 1120215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 1121215976Sjmallett " getting set, will never set HG2FLD.\n"; 1122215976Sjmallett fail |= cvmx_error_add(&info); 1123215976Sjmallett 1124215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,0) */ 1125215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1126215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1127215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1128215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1129215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1130215976Sjmallett info.flags = 0; 1131215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1132215976Sjmallett info.group_index = 1; 1133215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1134215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1135215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1136215976Sjmallett info.func = __cvmx_error_display; 1137215976Sjmallett info.user_info = (long) 1138215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n" 1139215976Sjmallett " (SGMII/1000Base-X only)\n"; 1140215976Sjmallett fail |= cvmx_error_add(&info); 1141215976Sjmallett 1142215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1143215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1144215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1145215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1146215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1147215976Sjmallett info.flags = 0; 1148215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1149215976Sjmallett info.group_index = 1; 1150215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1151215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1152215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1153215976Sjmallett info.func = __cvmx_error_display; 1154215976Sjmallett info.user_info = (long) 1155215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n"; 1156215976Sjmallett fail |= cvmx_error_add(&info); 1157215976Sjmallett 1158215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1159215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1160215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1161215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1162215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1163215976Sjmallett info.flags = 0; 1164215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1165215976Sjmallett info.group_index = 1; 1166215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1167215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1168215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1169215976Sjmallett info.func = __cvmx_error_display; 1170215976Sjmallett info.user_info = (long) 1171215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1172215976Sjmallett " This interrupt should never assert\n" 1173215976Sjmallett " (SGMII/1000Base-X only)\n"; 1174215976Sjmallett fail |= cvmx_error_add(&info); 1175215976Sjmallett 1176215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1177215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1178215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1179215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1180215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1181215976Sjmallett info.flags = 0; 1182215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1183215976Sjmallett info.group_index = 1; 1184215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1185215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1186215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1187215976Sjmallett info.func = __cvmx_error_display; 1188215976Sjmallett info.user_info = (long) 1189215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1190215976Sjmallett " (XAUI Mode only)\n"; 1191215976Sjmallett fail |= cvmx_error_add(&info); 1192215976Sjmallett 1193215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1194215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1195215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1196215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1197215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1198215976Sjmallett info.flags = 0; 1199215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1200215976Sjmallett info.group_index = 1; 1201215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1202215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1203215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1204215976Sjmallett info.func = __cvmx_error_display; 1205215976Sjmallett info.user_info = (long) 1206215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1207215976Sjmallett " (XAUI Mode only)\n"; 1208215976Sjmallett fail |= cvmx_error_add(&info); 1209215976Sjmallett 1210215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1211215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1212215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1213215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1214215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1215215976Sjmallett info.flags = 0; 1216215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1217215976Sjmallett info.group_index = 1; 1218215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1219215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1220215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1221215976Sjmallett info.func = __cvmx_error_display; 1222215976Sjmallett info.user_info = (long) 1223215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1224215976Sjmallett " (XAUI Mode only)\n"; 1225215976Sjmallett fail |= cvmx_error_add(&info); 1226215976Sjmallett 1227215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1228215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1229215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1230215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1231215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1232215976Sjmallett info.flags = 0; 1233215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1234215976Sjmallett info.group_index = 1; 1235215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1236215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1237215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1238215976Sjmallett info.func = __cvmx_error_display; 1239215976Sjmallett info.user_info = (long) 1240215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n" 1241215976Sjmallett " than /T/. The error propagation control\n" 1242215976Sjmallett " character /E/ will be included as part of the\n" 1243215976Sjmallett " frame and does not cause a frame termination.\n" 1244215976Sjmallett " (XAUI Mode only)\n"; 1245215976Sjmallett fail |= cvmx_error_add(&info); 1246215976Sjmallett 1247215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1248215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1249215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1250215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1251215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1252215976Sjmallett info.flags = 0; 1253215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1254215976Sjmallett info.group_index = 1; 1255215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1256215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1257215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1258215976Sjmallett info.func = __cvmx_error_display; 1259215976Sjmallett info.user_info = (long) 1260215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n" 1261215976Sjmallett " (XAUI Mode only)\n"; 1262215976Sjmallett fail |= cvmx_error_add(&info); 1263215976Sjmallett 1264215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1265215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1266215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1267215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1268215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1269215976Sjmallett info.flags = 0; 1270215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1271215976Sjmallett info.group_index = 1; 1272215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1273215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1274215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1275215976Sjmallett info.func = __cvmx_error_display; 1276215976Sjmallett info.user_info = (long) 1277215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n" 1278215976Sjmallett " (XAUI Mode only)\n"; 1279215976Sjmallett fail |= cvmx_error_add(&info); 1280215976Sjmallett 1281215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1282215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1283215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1284215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1285215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1286215976Sjmallett info.flags = 0; 1287215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1288215976Sjmallett info.group_index = 1; 1289215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1290215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1291215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1292215976Sjmallett info.func = __cvmx_error_display; 1293215976Sjmallett info.user_info = (long) 1294215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n" 1295215976Sjmallett " (XAUI Mode only)\n"; 1296215976Sjmallett fail |= cvmx_error_add(&info); 1297215976Sjmallett 1298215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1299215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1300215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 1301215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1302215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 1303215976Sjmallett info.flags = 0; 1304215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1305215976Sjmallett info.group_index = 1; 1306215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1307215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1308215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1309215976Sjmallett info.func = __cvmx_error_display; 1310215976Sjmallett info.user_info = (long) 1311215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n" 1312215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 1313215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 1314215976Sjmallett " is the only defined type for HiGig2\n" 1315215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 1316215976Sjmallett " which is the only defined type for HiGig2\n" 1317215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 1318215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 1319215976Sjmallett " Those are the only two defined types in HiGig2\n"; 1320215976Sjmallett fail |= cvmx_error_add(&info); 1321215976Sjmallett 1322215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1323215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1324215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 1325215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1326215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 1327215976Sjmallett info.flags = 0; 1328215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1329215976Sjmallett info.group_index = 1; 1330215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1331215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1332215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1333215976Sjmallett info.func = __cvmx_error_display; 1334215976Sjmallett info.user_info = (long) 1335215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 1336215976Sjmallett " Set when either CRC8 error detected or when\n" 1337215976Sjmallett " a Control Character is found in the message\n" 1338215976Sjmallett " bytes after the K.SOM\n" 1339215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 1340215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 1341215976Sjmallett " getting set, will never set HG2FLD.\n"; 1342215976Sjmallett fail |= cvmx_error_add(&info); 1343215976Sjmallett 1344215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,0) */ 1345215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1346215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1347215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1348215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1349215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1350215976Sjmallett info.flags = 0; 1351215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1352215976Sjmallett info.group_index = 2; 1353215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1354215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1355215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1356215976Sjmallett info.func = __cvmx_error_display; 1357215976Sjmallett info.user_info = (long) 1358215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n" 1359215976Sjmallett " (SGMII/1000Base-X only)\n"; 1360215976Sjmallett fail |= cvmx_error_add(&info); 1361215976Sjmallett 1362215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1363215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1364215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1365215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1366215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1367215976Sjmallett info.flags = 0; 1368215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1369215976Sjmallett info.group_index = 2; 1370215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1371215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1372215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1373215976Sjmallett info.func = __cvmx_error_display; 1374215976Sjmallett info.user_info = (long) 1375215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n"; 1376215976Sjmallett fail |= cvmx_error_add(&info); 1377215976Sjmallett 1378215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1379215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1380215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1381215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1382215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1383215976Sjmallett info.flags = 0; 1384215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1385215976Sjmallett info.group_index = 2; 1386215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1387215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1388215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1389215976Sjmallett info.func = __cvmx_error_display; 1390215976Sjmallett info.user_info = (long) 1391215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1392215976Sjmallett " This interrupt should never assert\n" 1393215976Sjmallett " (SGMII/1000Base-X only)\n"; 1394215976Sjmallett fail |= cvmx_error_add(&info); 1395215976Sjmallett 1396215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1397215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1398215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1399215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1400215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1401215976Sjmallett info.flags = 0; 1402215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1403215976Sjmallett info.group_index = 2; 1404215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1405215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1406215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1407215976Sjmallett info.func = __cvmx_error_display; 1408215976Sjmallett info.user_info = (long) 1409215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1410215976Sjmallett " (XAUI Mode only)\n"; 1411215976Sjmallett fail |= cvmx_error_add(&info); 1412215976Sjmallett 1413215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1414215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1415215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1416215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1417215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1418215976Sjmallett info.flags = 0; 1419215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1420215976Sjmallett info.group_index = 2; 1421215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1422215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1423215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1424215976Sjmallett info.func = __cvmx_error_display; 1425215976Sjmallett info.user_info = (long) 1426215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1427215976Sjmallett " (XAUI Mode only)\n"; 1428215976Sjmallett fail |= cvmx_error_add(&info); 1429215976Sjmallett 1430215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1431215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1432215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1433215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1434215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1435215976Sjmallett info.flags = 0; 1436215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1437215976Sjmallett info.group_index = 2; 1438215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1439215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1440215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1441215976Sjmallett info.func = __cvmx_error_display; 1442215976Sjmallett info.user_info = (long) 1443215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1444215976Sjmallett " (XAUI Mode only)\n"; 1445215976Sjmallett fail |= cvmx_error_add(&info); 1446215976Sjmallett 1447215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1448215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1449215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1450215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1451215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1452215976Sjmallett info.flags = 0; 1453215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1454215976Sjmallett info.group_index = 2; 1455215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1456215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1457215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1458215976Sjmallett info.func = __cvmx_error_display; 1459215976Sjmallett info.user_info = (long) 1460215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n" 1461215976Sjmallett " than /T/. The error propagation control\n" 1462215976Sjmallett " character /E/ will be included as part of the\n" 1463215976Sjmallett " frame and does not cause a frame termination.\n" 1464215976Sjmallett " (XAUI Mode only)\n"; 1465215976Sjmallett fail |= cvmx_error_add(&info); 1466215976Sjmallett 1467215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1468215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1469215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1470215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1471215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1472215976Sjmallett info.flags = 0; 1473215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1474215976Sjmallett info.group_index = 2; 1475215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1476215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1477215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1478215976Sjmallett info.func = __cvmx_error_display; 1479215976Sjmallett info.user_info = (long) 1480215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n" 1481215976Sjmallett " (XAUI Mode only)\n"; 1482215976Sjmallett fail |= cvmx_error_add(&info); 1483215976Sjmallett 1484215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1485215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1486215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1487215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1488215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1489215976Sjmallett info.flags = 0; 1490215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1491215976Sjmallett info.group_index = 2; 1492215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1493215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1494215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1495215976Sjmallett info.func = __cvmx_error_display; 1496215976Sjmallett info.user_info = (long) 1497215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n" 1498215976Sjmallett " (XAUI Mode only)\n"; 1499215976Sjmallett fail |= cvmx_error_add(&info); 1500215976Sjmallett 1501215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1502215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1503215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1504215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1505215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1506215976Sjmallett info.flags = 0; 1507215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1508215976Sjmallett info.group_index = 2; 1509215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1510215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1511215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1512215976Sjmallett info.func = __cvmx_error_display; 1513215976Sjmallett info.user_info = (long) 1514215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n" 1515215976Sjmallett " (XAUI Mode only)\n"; 1516215976Sjmallett fail |= cvmx_error_add(&info); 1517215976Sjmallett 1518215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1519215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1520215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 1521215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1522215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 1523215976Sjmallett info.flags = 0; 1524215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1525215976Sjmallett info.group_index = 2; 1526215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1527215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1528215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1529215976Sjmallett info.func = __cvmx_error_display; 1530215976Sjmallett info.user_info = (long) 1531215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n" 1532215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 1533215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 1534215976Sjmallett " is the only defined type for HiGig2\n" 1535215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 1536215976Sjmallett " which is the only defined type for HiGig2\n" 1537215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 1538215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 1539215976Sjmallett " Those are the only two defined types in HiGig2\n"; 1540215976Sjmallett fail |= cvmx_error_add(&info); 1541215976Sjmallett 1542215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1543215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1544215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 1545215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1546215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 1547215976Sjmallett info.flags = 0; 1548215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1549215976Sjmallett info.group_index = 2; 1550215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1551215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1552215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1553215976Sjmallett info.func = __cvmx_error_display; 1554215976Sjmallett info.user_info = (long) 1555215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 1556215976Sjmallett " Set when either CRC8 error detected or when\n" 1557215976Sjmallett " a Control Character is found in the message\n" 1558215976Sjmallett " bytes after the K.SOM\n" 1559215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 1560215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 1561215976Sjmallett " getting set, will never set HG2FLD.\n"; 1562215976Sjmallett fail |= cvmx_error_add(&info); 1563215976Sjmallett 1564215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(3,0) */ 1565215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1566215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1567215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1568215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1569215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1570215976Sjmallett info.flags = 0; 1571215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1572215976Sjmallett info.group_index = 3; 1573215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1574215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1575215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1576215976Sjmallett info.func = __cvmx_error_display; 1577215976Sjmallett info.user_info = (long) 1578215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n" 1579215976Sjmallett " (SGMII/1000Base-X only)\n"; 1580215976Sjmallett fail |= cvmx_error_add(&info); 1581215976Sjmallett 1582215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1583215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1584215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1585215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1586215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1587215976Sjmallett info.flags = 0; 1588215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1589215976Sjmallett info.group_index = 3; 1590215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1591215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1592215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1593215976Sjmallett info.func = __cvmx_error_display; 1594215976Sjmallett info.user_info = (long) 1595215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n"; 1596215976Sjmallett fail |= cvmx_error_add(&info); 1597215976Sjmallett 1598215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1599215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1600215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1601215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1602215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1603215976Sjmallett info.flags = 0; 1604215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1605215976Sjmallett info.group_index = 3; 1606215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1607215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1608215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1609215976Sjmallett info.func = __cvmx_error_display; 1610215976Sjmallett info.user_info = (long) 1611215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1612215976Sjmallett " This interrupt should never assert\n" 1613215976Sjmallett " (SGMII/1000Base-X only)\n"; 1614215976Sjmallett fail |= cvmx_error_add(&info); 1615215976Sjmallett 1616215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1617215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1618215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1619215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1620215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1621215976Sjmallett info.flags = 0; 1622215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1623215976Sjmallett info.group_index = 3; 1624215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1625215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1626215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1627215976Sjmallett info.func = __cvmx_error_display; 1628215976Sjmallett info.user_info = (long) 1629215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1630215976Sjmallett " (XAUI Mode only)\n"; 1631215976Sjmallett fail |= cvmx_error_add(&info); 1632215976Sjmallett 1633215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1634215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1635215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1636215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1637215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1638215976Sjmallett info.flags = 0; 1639215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1640215976Sjmallett info.group_index = 3; 1641215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1642215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1643215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1644215976Sjmallett info.func = __cvmx_error_display; 1645215976Sjmallett info.user_info = (long) 1646215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1647215976Sjmallett " (XAUI Mode only)\n"; 1648215976Sjmallett fail |= cvmx_error_add(&info); 1649215976Sjmallett 1650215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1651215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1652215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1653215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1654215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1655215976Sjmallett info.flags = 0; 1656215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1657215976Sjmallett info.group_index = 3; 1658215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1659215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1660215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1661215976Sjmallett info.func = __cvmx_error_display; 1662215976Sjmallett info.user_info = (long) 1663215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1664215976Sjmallett " (XAUI Mode only)\n"; 1665215976Sjmallett fail |= cvmx_error_add(&info); 1666215976Sjmallett 1667215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1668215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1669215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1670215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1671215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1672215976Sjmallett info.flags = 0; 1673215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1674215976Sjmallett info.group_index = 3; 1675215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1676215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1677215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1678215976Sjmallett info.func = __cvmx_error_display; 1679215976Sjmallett info.user_info = (long) 1680215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n" 1681215976Sjmallett " than /T/. The error propagation control\n" 1682215976Sjmallett " character /E/ will be included as part of the\n" 1683215976Sjmallett " frame and does not cause a frame termination.\n" 1684215976Sjmallett " (XAUI Mode only)\n"; 1685215976Sjmallett fail |= cvmx_error_add(&info); 1686215976Sjmallett 1687215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1688215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1689215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1690215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1691215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1692215976Sjmallett info.flags = 0; 1693215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1694215976Sjmallett info.group_index = 3; 1695215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1696215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1697215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1698215976Sjmallett info.func = __cvmx_error_display; 1699215976Sjmallett info.user_info = (long) 1700215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n" 1701215976Sjmallett " (XAUI Mode only)\n"; 1702215976Sjmallett fail |= cvmx_error_add(&info); 1703215976Sjmallett 1704215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1705215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1706215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1707215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1708215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1709215976Sjmallett info.flags = 0; 1710215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1711215976Sjmallett info.group_index = 3; 1712215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1713215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1714215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1715215976Sjmallett info.func = __cvmx_error_display; 1716215976Sjmallett info.user_info = (long) 1717215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n" 1718215976Sjmallett " (XAUI Mode only)\n"; 1719215976Sjmallett fail |= cvmx_error_add(&info); 1720215976Sjmallett 1721215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1722215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1723215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1724215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1725215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1726215976Sjmallett info.flags = 0; 1727215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1728215976Sjmallett info.group_index = 3; 1729215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1730215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1731215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1732215976Sjmallett info.func = __cvmx_error_display; 1733215976Sjmallett info.user_info = (long) 1734215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n" 1735215976Sjmallett " (XAUI Mode only)\n"; 1736215976Sjmallett fail |= cvmx_error_add(&info); 1737215976Sjmallett 1738215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1739215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1740215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 1741215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1742215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 1743215976Sjmallett info.flags = 0; 1744215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1745215976Sjmallett info.group_index = 3; 1746215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1747215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1748215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1749215976Sjmallett info.func = __cvmx_error_display; 1750215976Sjmallett info.user_info = (long) 1751215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n" 1752215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 1753215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 1754215976Sjmallett " is the only defined type for HiGig2\n" 1755215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 1756215976Sjmallett " which is the only defined type for HiGig2\n" 1757215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 1758215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 1759215976Sjmallett " Those are the only two defined types in HiGig2\n"; 1760215976Sjmallett fail |= cvmx_error_add(&info); 1761215976Sjmallett 1762215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1763215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1764215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 1765215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1766215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 1767215976Sjmallett info.flags = 0; 1768215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1769215976Sjmallett info.group_index = 3; 1770215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1771215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1772215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1773215976Sjmallett info.func = __cvmx_error_display; 1774215976Sjmallett info.user_info = (long) 1775215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 1776215976Sjmallett " Set when either CRC8 error detected or when\n" 1777215976Sjmallett " a Control Character is found in the message\n" 1778215976Sjmallett " bytes after the K.SOM\n" 1779215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 1780215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 1781215976Sjmallett " getting set, will never set HG2FLD.\n"; 1782215976Sjmallett fail |= cvmx_error_add(&info); 1783215976Sjmallett 1784215976Sjmallett /* CVMX_GMXX_TX_INT_REG(0) */ 1785215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1786215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 1787215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 1788215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 1789215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 1790215976Sjmallett info.flags = 0; 1791215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1792215976Sjmallett info.group_index = 0; 1793215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1794215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1795215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1796215976Sjmallett info.func = __cvmx_error_display; 1797215976Sjmallett info.user_info = (long) 1798215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 1799215976Sjmallett fail |= cvmx_error_add(&info); 1800215976Sjmallett 1801215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1802215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 1803215976Sjmallett info.status_mask = 0xfull<<2 /* undflw */; 1804215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 1805215976Sjmallett info.enable_mask = 0xfull<<2 /* undflw */; 1806215976Sjmallett info.flags = 0; 1807215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1808215976Sjmallett info.group_index = 0; 1809215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1810215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1811215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1812215976Sjmallett info.func = __cvmx_error_display; 1813215976Sjmallett info.user_info = (long) 1814215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n"; 1815215976Sjmallett fail |= cvmx_error_add(&info); 1816215976Sjmallett 1817215976Sjmallett /* CVMX_GMXX_BAD_REG(1) */ 1818215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1819215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 1820215976Sjmallett info.status_mask = 0xfull<<2 /* out_ovr */; 1821215976Sjmallett info.enable_addr = 0; 1822215976Sjmallett info.enable_mask = 0; 1823215976Sjmallett info.flags = 0; 1824215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1825215976Sjmallett info.group_index = 16; 1826215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1827215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1828215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1829215976Sjmallett info.func = __cvmx_error_display; 1830215976Sjmallett info.user_info = (long) 1831215976Sjmallett "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 1832215976Sjmallett fail |= cvmx_error_add(&info); 1833215976Sjmallett 1834215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1835215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 1836215976Sjmallett info.status_mask = 0xfull<<22 /* loststat */; 1837215976Sjmallett info.enable_addr = 0; 1838215976Sjmallett info.enable_mask = 0; 1839215976Sjmallett info.flags = 0; 1840215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1841215976Sjmallett info.group_index = 16; 1842215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1843215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1844215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1845215976Sjmallett info.func = __cvmx_error_display; 1846215976Sjmallett info.user_info = (long) 1847215976Sjmallett "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n" 1848215976Sjmallett " In SGMII, one bit per port\n" 1849215976Sjmallett " In XAUI, only port0 is used\n" 1850215976Sjmallett " TX Stats are corrupted\n"; 1851215976Sjmallett fail |= cvmx_error_add(&info); 1852215976Sjmallett 1853215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1854215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 1855215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 1856215976Sjmallett info.enable_addr = 0; 1857215976Sjmallett info.enable_mask = 0; 1858215976Sjmallett info.flags = 0; 1859215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1860215976Sjmallett info.group_index = 16; 1861215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1862215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1863215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1864215976Sjmallett info.func = __cvmx_error_display; 1865215976Sjmallett info.user_info = (long) 1866215976Sjmallett "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n" 1867215976Sjmallett " The common FIFO to SGMII and XAUI had an overflow\n" 1868215976Sjmallett " TX Stats are corrupted\n"; 1869215976Sjmallett fail |= cvmx_error_add(&info); 1870215976Sjmallett 1871215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1872215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(1); 1873215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 1874215976Sjmallett info.enable_addr = 0; 1875215976Sjmallett info.enable_mask = 0; 1876215976Sjmallett info.flags = 0; 1877215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1878215976Sjmallett info.group_index = 16; 1879215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1880215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1881215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1882215976Sjmallett info.func = __cvmx_error_display; 1883215976Sjmallett info.user_info = (long) 1884215976Sjmallett "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 1885215976Sjmallett fail |= cvmx_error_add(&info); 1886215976Sjmallett 1887215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,1) */ 1888215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1889215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1890215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1891215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1892215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1893215976Sjmallett info.flags = 0; 1894215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1895215976Sjmallett info.group_index = 16; 1896215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1897215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1898215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1899215976Sjmallett info.func = __cvmx_error_display; 1900215976Sjmallett info.user_info = (long) 1901215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n" 1902215976Sjmallett " (SGMII/1000Base-X only)\n"; 1903215976Sjmallett fail |= cvmx_error_add(&info); 1904215976Sjmallett 1905215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1906215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1907215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1908215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1909215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1910215976Sjmallett info.flags = 0; 1911215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1912215976Sjmallett info.group_index = 16; 1913215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1914215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1915215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1916215976Sjmallett info.func = __cvmx_error_display; 1917215976Sjmallett info.user_info = (long) 1918215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n"; 1919215976Sjmallett fail |= cvmx_error_add(&info); 1920215976Sjmallett 1921215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1922215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1923215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1924215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1925215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1926215976Sjmallett info.flags = 0; 1927215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1928215976Sjmallett info.group_index = 16; 1929215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1930215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1931215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1932215976Sjmallett info.func = __cvmx_error_display; 1933215976Sjmallett info.user_info = (long) 1934215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n" 1935215976Sjmallett " This interrupt should never assert\n" 1936215976Sjmallett " (SGMII/1000Base-X only)\n"; 1937215976Sjmallett fail |= cvmx_error_add(&info); 1938215976Sjmallett 1939215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1940215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1941215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1942215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1943215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1944215976Sjmallett info.flags = 0; 1945215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1946215976Sjmallett info.group_index = 16; 1947215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1948215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1949215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1950215976Sjmallett info.func = __cvmx_error_display; 1951215976Sjmallett info.user_info = (long) 1952215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1953215976Sjmallett " (XAUI Mode only)\n"; 1954215976Sjmallett fail |= cvmx_error_add(&info); 1955215976Sjmallett 1956215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1957215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1958215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1959215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1960215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1961215976Sjmallett info.flags = 0; 1962215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1963215976Sjmallett info.group_index = 16; 1964215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1965215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1966215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1967215976Sjmallett info.func = __cvmx_error_display; 1968215976Sjmallett info.user_info = (long) 1969215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1970215976Sjmallett " (XAUI Mode only)\n"; 1971215976Sjmallett fail |= cvmx_error_add(&info); 1972215976Sjmallett 1973215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1974215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1975215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1976215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1977215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1978215976Sjmallett info.flags = 0; 1979215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1980215976Sjmallett info.group_index = 16; 1981215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1982215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1983215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 1984215976Sjmallett info.func = __cvmx_error_display; 1985215976Sjmallett info.user_info = (long) 1986215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n" 1987215976Sjmallett " (XAUI Mode only)\n"; 1988215976Sjmallett fail |= cvmx_error_add(&info); 1989215976Sjmallett 1990215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1991215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 1992215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1993215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 1994215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1995215976Sjmallett info.flags = 0; 1996215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1997215976Sjmallett info.group_index = 16; 1998215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1999215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2000215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2001215976Sjmallett info.func = __cvmx_error_display; 2002215976Sjmallett info.user_info = (long) 2003215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n" 2004215976Sjmallett " than /T/. The error propagation control\n" 2005215976Sjmallett " character /E/ will be included as part of the\n" 2006215976Sjmallett " frame and does not cause a frame termination.\n" 2007215976Sjmallett " (XAUI Mode only)\n"; 2008215976Sjmallett fail |= cvmx_error_add(&info); 2009215976Sjmallett 2010215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2011215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2012215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 2013215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2014215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 2015215976Sjmallett info.flags = 0; 2016215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2017215976Sjmallett info.group_index = 16; 2018215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2019215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2020215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2021215976Sjmallett info.func = __cvmx_error_display; 2022215976Sjmallett info.user_info = (long) 2023215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n" 2024215976Sjmallett " (XAUI Mode only)\n"; 2025215976Sjmallett fail |= cvmx_error_add(&info); 2026215976Sjmallett 2027215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2028215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2029215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 2030215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2031215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 2032215976Sjmallett info.flags = 0; 2033215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2034215976Sjmallett info.group_index = 16; 2035215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2036215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2037215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2038215976Sjmallett info.func = __cvmx_error_display; 2039215976Sjmallett info.user_info = (long) 2040215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n" 2041215976Sjmallett " (XAUI Mode only)\n"; 2042215976Sjmallett fail |= cvmx_error_add(&info); 2043215976Sjmallett 2044215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2045215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2046215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 2047215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2048215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 2049215976Sjmallett info.flags = 0; 2050215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2051215976Sjmallett info.group_index = 16; 2052215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2053215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2054215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2055215976Sjmallett info.func = __cvmx_error_display; 2056215976Sjmallett info.user_info = (long) 2057215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n" 2058215976Sjmallett " (XAUI Mode only)\n"; 2059215976Sjmallett fail |= cvmx_error_add(&info); 2060215976Sjmallett 2061215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2062215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2063215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 2064215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2065215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 2066215976Sjmallett info.flags = 0; 2067215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2068215976Sjmallett info.group_index = 16; 2069215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2070215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2071215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2072215976Sjmallett info.func = __cvmx_error_display; 2073215976Sjmallett info.user_info = (long) 2074215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n" 2075215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 2076215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 2077215976Sjmallett " is the only defined type for HiGig2\n" 2078215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 2079215976Sjmallett " which is the only defined type for HiGig2\n" 2080215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 2081215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 2082215976Sjmallett " Those are the only two defined types in HiGig2\n"; 2083215976Sjmallett fail |= cvmx_error_add(&info); 2084215976Sjmallett 2085215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2086215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1); 2087215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 2088215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1); 2089215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 2090215976Sjmallett info.flags = 0; 2091215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2092215976Sjmallett info.group_index = 16; 2093215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2094215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2095215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2096215976Sjmallett info.func = __cvmx_error_display; 2097215976Sjmallett info.user_info = (long) 2098215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char error\n" 2099215976Sjmallett " Set when either CRC8 error detected or when\n" 2100215976Sjmallett " a Control Character is found in the message\n" 2101215976Sjmallett " bytes after the K.SOM\n" 2102215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 2103215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 2104215976Sjmallett " getting set, will never set HG2FLD.\n"; 2105215976Sjmallett fail |= cvmx_error_add(&info); 2106215976Sjmallett 2107215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,1) */ 2108215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2109215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2110215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2111215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2112215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2113215976Sjmallett info.flags = 0; 2114215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2115215976Sjmallett info.group_index = 17; 2116215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2117215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2118215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2119215976Sjmallett info.func = __cvmx_error_display; 2120215976Sjmallett info.user_info = (long) 2121215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n" 2122215976Sjmallett " (SGMII/1000Base-X only)\n"; 2123215976Sjmallett fail |= cvmx_error_add(&info); 2124215976Sjmallett 2125215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2126215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2127215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2128215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2129215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2130215976Sjmallett info.flags = 0; 2131215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2132215976Sjmallett info.group_index = 17; 2133215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2134215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2135215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2136215976Sjmallett info.func = __cvmx_error_display; 2137215976Sjmallett info.user_info = (long) 2138215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n"; 2139215976Sjmallett fail |= cvmx_error_add(&info); 2140215976Sjmallett 2141215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2142215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2143215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2144215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2145215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2146215976Sjmallett info.flags = 0; 2147215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2148215976Sjmallett info.group_index = 17; 2149215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2150215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2151215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2152215976Sjmallett info.func = __cvmx_error_display; 2153215976Sjmallett info.user_info = (long) 2154215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n" 2155215976Sjmallett " This interrupt should never assert\n" 2156215976Sjmallett " (SGMII/1000Base-X only)\n"; 2157215976Sjmallett fail |= cvmx_error_add(&info); 2158215976Sjmallett 2159215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2160215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2161215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 2162215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2163215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 2164215976Sjmallett info.flags = 0; 2165215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2166215976Sjmallett info.group_index = 17; 2167215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2168215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2169215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2170215976Sjmallett info.func = __cvmx_error_display; 2171215976Sjmallett info.user_info = (long) 2172215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n" 2173215976Sjmallett " (XAUI Mode only)\n"; 2174215976Sjmallett fail |= cvmx_error_add(&info); 2175215976Sjmallett 2176215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2177215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2178215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 2179215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2180215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 2181215976Sjmallett info.flags = 0; 2182215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2183215976Sjmallett info.group_index = 17; 2184215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2185215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2186215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2187215976Sjmallett info.func = __cvmx_error_display; 2188215976Sjmallett info.user_info = (long) 2189215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n" 2190215976Sjmallett " (XAUI Mode only)\n"; 2191215976Sjmallett fail |= cvmx_error_add(&info); 2192215976Sjmallett 2193215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2194215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2195215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 2196215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2197215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 2198215976Sjmallett info.flags = 0; 2199215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2200215976Sjmallett info.group_index = 17; 2201215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2202215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2203215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2204215976Sjmallett info.func = __cvmx_error_display; 2205215976Sjmallett info.user_info = (long) 2206215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n" 2207215976Sjmallett " (XAUI Mode only)\n"; 2208215976Sjmallett fail |= cvmx_error_add(&info); 2209215976Sjmallett 2210215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2211215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2212215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 2213215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2214215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 2215215976Sjmallett info.flags = 0; 2216215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2217215976Sjmallett info.group_index = 17; 2218215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2219215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2220215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2221215976Sjmallett info.func = __cvmx_error_display; 2222215976Sjmallett info.user_info = (long) 2223215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n" 2224215976Sjmallett " than /T/. The error propagation control\n" 2225215976Sjmallett " character /E/ will be included as part of the\n" 2226215976Sjmallett " frame and does not cause a frame termination.\n" 2227215976Sjmallett " (XAUI Mode only)\n"; 2228215976Sjmallett fail |= cvmx_error_add(&info); 2229215976Sjmallett 2230215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2231215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2232215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 2233215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2234215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 2235215976Sjmallett info.flags = 0; 2236215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2237215976Sjmallett info.group_index = 17; 2238215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2239215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2240215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2241215976Sjmallett info.func = __cvmx_error_display; 2242215976Sjmallett info.user_info = (long) 2243215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n" 2244215976Sjmallett " (XAUI Mode only)\n"; 2245215976Sjmallett fail |= cvmx_error_add(&info); 2246215976Sjmallett 2247215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2248215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2249215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 2250215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2251215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 2252215976Sjmallett info.flags = 0; 2253215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2254215976Sjmallett info.group_index = 17; 2255215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2256215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2257215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2258215976Sjmallett info.func = __cvmx_error_display; 2259215976Sjmallett info.user_info = (long) 2260215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n" 2261215976Sjmallett " (XAUI Mode only)\n"; 2262215976Sjmallett fail |= cvmx_error_add(&info); 2263215976Sjmallett 2264215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2265215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2266215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 2267215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2268215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 2269215976Sjmallett info.flags = 0; 2270215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2271215976Sjmallett info.group_index = 17; 2272215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2273215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2274215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2275215976Sjmallett info.func = __cvmx_error_display; 2276215976Sjmallett info.user_info = (long) 2277215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n" 2278215976Sjmallett " (XAUI Mode only)\n"; 2279215976Sjmallett fail |= cvmx_error_add(&info); 2280215976Sjmallett 2281215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2282215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2283215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 2284215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2285215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 2286215976Sjmallett info.flags = 0; 2287215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2288215976Sjmallett info.group_index = 17; 2289215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2290215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2291215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2292215976Sjmallett info.func = __cvmx_error_display; 2293215976Sjmallett info.user_info = (long) 2294215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below\n" 2295215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 2296215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 2297215976Sjmallett " is the only defined type for HiGig2\n" 2298215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 2299215976Sjmallett " which is the only defined type for HiGig2\n" 2300215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 2301215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 2302215976Sjmallett " Those are the only two defined types in HiGig2\n"; 2303215976Sjmallett fail |= cvmx_error_add(&info); 2304215976Sjmallett 2305215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2306215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1); 2307215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 2308215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1); 2309215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 2310215976Sjmallett info.flags = 0; 2311215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2312215976Sjmallett info.group_index = 17; 2313215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2314215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2315215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2316215976Sjmallett info.func = __cvmx_error_display; 2317215976Sjmallett info.user_info = (long) 2318215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char error\n" 2319215976Sjmallett " Set when either CRC8 error detected or when\n" 2320215976Sjmallett " a Control Character is found in the message\n" 2321215976Sjmallett " bytes after the K.SOM\n" 2322215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 2323215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 2324215976Sjmallett " getting set, will never set HG2FLD.\n"; 2325215976Sjmallett fail |= cvmx_error_add(&info); 2326215976Sjmallett 2327215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,1) */ 2328215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2329215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2330215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2331215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2332215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2333215976Sjmallett info.flags = 0; 2334215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2335215976Sjmallett info.group_index = 18; 2336215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2337215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2338215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2339215976Sjmallett info.func = __cvmx_error_display; 2340215976Sjmallett info.user_info = (long) 2341215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n" 2342215976Sjmallett " (SGMII/1000Base-X only)\n"; 2343215976Sjmallett fail |= cvmx_error_add(&info); 2344215976Sjmallett 2345215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2346215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2347215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2348215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2349215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2350215976Sjmallett info.flags = 0; 2351215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2352215976Sjmallett info.group_index = 18; 2353215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2354215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2355215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2356215976Sjmallett info.func = __cvmx_error_display; 2357215976Sjmallett info.user_info = (long) 2358215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n"; 2359215976Sjmallett fail |= cvmx_error_add(&info); 2360215976Sjmallett 2361215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2362215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2363215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2364215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2365215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2366215976Sjmallett info.flags = 0; 2367215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2368215976Sjmallett info.group_index = 18; 2369215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2370215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2371215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2372215976Sjmallett info.func = __cvmx_error_display; 2373215976Sjmallett info.user_info = (long) 2374215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n" 2375215976Sjmallett " This interrupt should never assert\n" 2376215976Sjmallett " (SGMII/1000Base-X only)\n"; 2377215976Sjmallett fail |= cvmx_error_add(&info); 2378215976Sjmallett 2379215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2380215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2381215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 2382215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2383215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 2384215976Sjmallett info.flags = 0; 2385215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2386215976Sjmallett info.group_index = 18; 2387215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2388215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2389215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2390215976Sjmallett info.func = __cvmx_error_display; 2391215976Sjmallett info.user_info = (long) 2392215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n" 2393215976Sjmallett " (XAUI Mode only)\n"; 2394215976Sjmallett fail |= cvmx_error_add(&info); 2395215976Sjmallett 2396215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2397215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2398215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 2399215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2400215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 2401215976Sjmallett info.flags = 0; 2402215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2403215976Sjmallett info.group_index = 18; 2404215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2405215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2406215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2407215976Sjmallett info.func = __cvmx_error_display; 2408215976Sjmallett info.user_info = (long) 2409215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n" 2410215976Sjmallett " (XAUI Mode only)\n"; 2411215976Sjmallett fail |= cvmx_error_add(&info); 2412215976Sjmallett 2413215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2414215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2415215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 2416215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2417215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 2418215976Sjmallett info.flags = 0; 2419215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2420215976Sjmallett info.group_index = 18; 2421215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2422215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2423215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2424215976Sjmallett info.func = __cvmx_error_display; 2425215976Sjmallett info.user_info = (long) 2426215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n" 2427215976Sjmallett " (XAUI Mode only)\n"; 2428215976Sjmallett fail |= cvmx_error_add(&info); 2429215976Sjmallett 2430215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2431215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2432215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 2433215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2434215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 2435215976Sjmallett info.flags = 0; 2436215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2437215976Sjmallett info.group_index = 18; 2438215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2439215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2440215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2441215976Sjmallett info.func = __cvmx_error_display; 2442215976Sjmallett info.user_info = (long) 2443215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n" 2444215976Sjmallett " than /T/. The error propagation control\n" 2445215976Sjmallett " character /E/ will be included as part of the\n" 2446215976Sjmallett " frame and does not cause a frame termination.\n" 2447215976Sjmallett " (XAUI Mode only)\n"; 2448215976Sjmallett fail |= cvmx_error_add(&info); 2449215976Sjmallett 2450215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2451215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2452215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 2453215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2454215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 2455215976Sjmallett info.flags = 0; 2456215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2457215976Sjmallett info.group_index = 18; 2458215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2459215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2460215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2461215976Sjmallett info.func = __cvmx_error_display; 2462215976Sjmallett info.user_info = (long) 2463215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n" 2464215976Sjmallett " (XAUI Mode only)\n"; 2465215976Sjmallett fail |= cvmx_error_add(&info); 2466215976Sjmallett 2467215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2468215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2469215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 2470215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2471215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 2472215976Sjmallett info.flags = 0; 2473215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2474215976Sjmallett info.group_index = 18; 2475215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2476215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2477215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2478215976Sjmallett info.func = __cvmx_error_display; 2479215976Sjmallett info.user_info = (long) 2480215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n" 2481215976Sjmallett " (XAUI Mode only)\n"; 2482215976Sjmallett fail |= cvmx_error_add(&info); 2483215976Sjmallett 2484215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2485215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2486215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 2487215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2488215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 2489215976Sjmallett info.flags = 0; 2490215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2491215976Sjmallett info.group_index = 18; 2492215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2493215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2494215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2495215976Sjmallett info.func = __cvmx_error_display; 2496215976Sjmallett info.user_info = (long) 2497215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n" 2498215976Sjmallett " (XAUI Mode only)\n"; 2499215976Sjmallett fail |= cvmx_error_add(&info); 2500215976Sjmallett 2501215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2502215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2503215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 2504215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2505215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 2506215976Sjmallett info.flags = 0; 2507215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2508215976Sjmallett info.group_index = 18; 2509215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2510215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2511215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2512215976Sjmallett info.func = __cvmx_error_display; 2513215976Sjmallett info.user_info = (long) 2514215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below\n" 2515215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 2516215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 2517215976Sjmallett " is the only defined type for HiGig2\n" 2518215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 2519215976Sjmallett " which is the only defined type for HiGig2\n" 2520215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 2521215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 2522215976Sjmallett " Those are the only two defined types in HiGig2\n"; 2523215976Sjmallett fail |= cvmx_error_add(&info); 2524215976Sjmallett 2525215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2526215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1); 2527215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 2528215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1); 2529215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 2530215976Sjmallett info.flags = 0; 2531215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2532215976Sjmallett info.group_index = 18; 2533215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2534215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2535215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2536215976Sjmallett info.func = __cvmx_error_display; 2537215976Sjmallett info.user_info = (long) 2538215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char error\n" 2539215976Sjmallett " Set when either CRC8 error detected or when\n" 2540215976Sjmallett " a Control Character is found in the message\n" 2541215976Sjmallett " bytes after the K.SOM\n" 2542215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 2543215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 2544215976Sjmallett " getting set, will never set HG2FLD.\n"; 2545215976Sjmallett fail |= cvmx_error_add(&info); 2546215976Sjmallett 2547215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(3,1) */ 2548215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2549215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2550215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2551215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2552215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2553215976Sjmallett info.flags = 0; 2554215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2555215976Sjmallett info.group_index = 19; 2556215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2557215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2558215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2559215976Sjmallett info.func = __cvmx_error_display; 2560215976Sjmallett info.user_info = (long) 2561215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n" 2562215976Sjmallett " (SGMII/1000Base-X only)\n"; 2563215976Sjmallett fail |= cvmx_error_add(&info); 2564215976Sjmallett 2565215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2566215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2567215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2568215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2569215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2570215976Sjmallett info.flags = 0; 2571215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2572215976Sjmallett info.group_index = 19; 2573215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2574215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2575215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2576215976Sjmallett info.func = __cvmx_error_display; 2577215976Sjmallett info.user_info = (long) 2578215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n"; 2579215976Sjmallett fail |= cvmx_error_add(&info); 2580215976Sjmallett 2581215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2582215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2583215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2584215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2585215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2586215976Sjmallett info.flags = 0; 2587215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2588215976Sjmallett info.group_index = 19; 2589215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2590215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2591215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2592215976Sjmallett info.func = __cvmx_error_display; 2593215976Sjmallett info.user_info = (long) 2594215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n" 2595215976Sjmallett " This interrupt should never assert\n" 2596215976Sjmallett " (SGMII/1000Base-X only)\n"; 2597215976Sjmallett fail |= cvmx_error_add(&info); 2598215976Sjmallett 2599215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2600215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2601215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 2602215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2603215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 2604215976Sjmallett info.flags = 0; 2605215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2606215976Sjmallett info.group_index = 19; 2607215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2608215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2609215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2610215976Sjmallett info.func = __cvmx_error_display; 2611215976Sjmallett info.user_info = (long) 2612215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n" 2613215976Sjmallett " (XAUI Mode only)\n"; 2614215976Sjmallett fail |= cvmx_error_add(&info); 2615215976Sjmallett 2616215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2617215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2618215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 2619215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2620215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 2621215976Sjmallett info.flags = 0; 2622215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2623215976Sjmallett info.group_index = 19; 2624215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2625215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2626215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2627215976Sjmallett info.func = __cvmx_error_display; 2628215976Sjmallett info.user_info = (long) 2629215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n" 2630215976Sjmallett " (XAUI Mode only)\n"; 2631215976Sjmallett fail |= cvmx_error_add(&info); 2632215976Sjmallett 2633215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2634215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2635215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 2636215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2637215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 2638215976Sjmallett info.flags = 0; 2639215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2640215976Sjmallett info.group_index = 19; 2641215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2642215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2643215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2644215976Sjmallett info.func = __cvmx_error_display; 2645215976Sjmallett info.user_info = (long) 2646215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n" 2647215976Sjmallett " (XAUI Mode only)\n"; 2648215976Sjmallett fail |= cvmx_error_add(&info); 2649215976Sjmallett 2650215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2651215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2652215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 2653215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2654215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 2655215976Sjmallett info.flags = 0; 2656215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2657215976Sjmallett info.group_index = 19; 2658215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2659215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2660215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2661215976Sjmallett info.func = __cvmx_error_display; 2662215976Sjmallett info.user_info = (long) 2663215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n" 2664215976Sjmallett " than /T/. The error propagation control\n" 2665215976Sjmallett " character /E/ will be included as part of the\n" 2666215976Sjmallett " frame and does not cause a frame termination.\n" 2667215976Sjmallett " (XAUI Mode only)\n"; 2668215976Sjmallett fail |= cvmx_error_add(&info); 2669215976Sjmallett 2670215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2671215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2672215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 2673215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2674215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 2675215976Sjmallett info.flags = 0; 2676215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2677215976Sjmallett info.group_index = 19; 2678215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2679215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2680215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2681215976Sjmallett info.func = __cvmx_error_display; 2682215976Sjmallett info.user_info = (long) 2683215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n" 2684215976Sjmallett " (XAUI Mode only)\n"; 2685215976Sjmallett fail |= cvmx_error_add(&info); 2686215976Sjmallett 2687215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2688215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2689215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 2690215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2691215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 2692215976Sjmallett info.flags = 0; 2693215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2694215976Sjmallett info.group_index = 19; 2695215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2696215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2697215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2698215976Sjmallett info.func = __cvmx_error_display; 2699215976Sjmallett info.user_info = (long) 2700215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n" 2701215976Sjmallett " (XAUI Mode only)\n"; 2702215976Sjmallett fail |= cvmx_error_add(&info); 2703215976Sjmallett 2704215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2705215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2706215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 2707215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2708215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 2709215976Sjmallett info.flags = 0; 2710215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2711215976Sjmallett info.group_index = 19; 2712215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2713215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2714215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2715215976Sjmallett info.func = __cvmx_error_display; 2716215976Sjmallett info.user_info = (long) 2717215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n" 2718215976Sjmallett " (XAUI Mode only)\n"; 2719215976Sjmallett fail |= cvmx_error_add(&info); 2720215976Sjmallett 2721215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2722215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2723215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 2724215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2725215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 2726215976Sjmallett info.flags = 0; 2727215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2728215976Sjmallett info.group_index = 19; 2729215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2730215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2731215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2732215976Sjmallett info.func = __cvmx_error_display; 2733215976Sjmallett info.user_info = (long) 2734215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below\n" 2735215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 2736215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 2737215976Sjmallett " is the only defined type for HiGig2\n" 2738215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 2739215976Sjmallett " which is the only defined type for HiGig2\n" 2740215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 2741215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 2742215976Sjmallett " Those are the only two defined types in HiGig2\n"; 2743215976Sjmallett fail |= cvmx_error_add(&info); 2744215976Sjmallett 2745215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2746215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1); 2747215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 2748215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1); 2749215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 2750215976Sjmallett info.flags = 0; 2751215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2752215976Sjmallett info.group_index = 19; 2753215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2754215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2755215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2756215976Sjmallett info.func = __cvmx_error_display; 2757215976Sjmallett info.user_info = (long) 2758215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char error\n" 2759215976Sjmallett " Set when either CRC8 error detected or when\n" 2760215976Sjmallett " a Control Character is found in the message\n" 2761215976Sjmallett " bytes after the K.SOM\n" 2762215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 2763215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 2764215976Sjmallett " getting set, will never set HG2FLD.\n"; 2765215976Sjmallett fail |= cvmx_error_add(&info); 2766215976Sjmallett 2767215976Sjmallett /* CVMX_GMXX_TX_INT_REG(1) */ 2768215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2769215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(1); 2770215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 2771215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(1); 2772215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 2773215976Sjmallett info.flags = 0; 2774215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2775215976Sjmallett info.group_index = 16; 2776215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2777215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2778215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2779215976Sjmallett info.func = __cvmx_error_display; 2780215976Sjmallett info.user_info = (long) 2781215976Sjmallett "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 2782215976Sjmallett fail |= cvmx_error_add(&info); 2783215976Sjmallett 2784215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2785215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(1); 2786215976Sjmallett info.status_mask = 0xfull<<2 /* undflw */; 2787215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(1); 2788215976Sjmallett info.enable_mask = 0xfull<<2 /* undflw */; 2789215976Sjmallett info.flags = 0; 2790215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2791215976Sjmallett info.group_index = 16; 2792215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2793215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2794215976Sjmallett info.parent.status_mask = 1ull<<2 /* gmx1 */; 2795215976Sjmallett info.func = __cvmx_error_display; 2796215976Sjmallett info.user_info = (long) 2797215976Sjmallett "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n"; 2798215976Sjmallett fail |= cvmx_error_add(&info); 2799215976Sjmallett 2800215976Sjmallett /* CVMX_IPD_INT_SUM */ 2801215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2802215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2803215976Sjmallett info.status_mask = 1ull<<0 /* prc_par0 */; 2804215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2805215976Sjmallett info.enable_mask = 1ull<<0 /* prc_par0 */; 2806215976Sjmallett info.flags = 0; 2807215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2808215976Sjmallett info.group_index = 0; 2809215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2810215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2811215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2812215976Sjmallett info.func = __cvmx_error_display; 2813215976Sjmallett info.user_info = (long) 2814215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n" 2815215976Sjmallett " [31:0] of the PBM memory.\n"; 2816215976Sjmallett fail |= cvmx_error_add(&info); 2817215976Sjmallett 2818215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2819215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2820215976Sjmallett info.status_mask = 1ull<<1 /* prc_par1 */; 2821215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2822215976Sjmallett info.enable_mask = 1ull<<1 /* prc_par1 */; 2823215976Sjmallett info.flags = 0; 2824215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2825215976Sjmallett info.group_index = 0; 2826215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2827215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2828215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2829215976Sjmallett info.func = __cvmx_error_display; 2830215976Sjmallett info.user_info = (long) 2831215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n" 2832215976Sjmallett " [63:32] of the PBM memory.\n"; 2833215976Sjmallett fail |= cvmx_error_add(&info); 2834215976Sjmallett 2835215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2836215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2837215976Sjmallett info.status_mask = 1ull<<2 /* prc_par2 */; 2838215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2839215976Sjmallett info.enable_mask = 1ull<<2 /* prc_par2 */; 2840215976Sjmallett info.flags = 0; 2841215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2842215976Sjmallett info.group_index = 0; 2843215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2844215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2845215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2846215976Sjmallett info.func = __cvmx_error_display; 2847215976Sjmallett info.user_info = (long) 2848215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n" 2849215976Sjmallett " [95:64] of the PBM memory.\n"; 2850215976Sjmallett fail |= cvmx_error_add(&info); 2851215976Sjmallett 2852215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2853215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2854215976Sjmallett info.status_mask = 1ull<<3 /* prc_par3 */; 2855215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2856215976Sjmallett info.enable_mask = 1ull<<3 /* prc_par3 */; 2857215976Sjmallett info.flags = 0; 2858215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2859215976Sjmallett info.group_index = 0; 2860215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2861215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2862215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2863215976Sjmallett info.func = __cvmx_error_display; 2864215976Sjmallett info.user_info = (long) 2865215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n" 2866215976Sjmallett " [127:96] of the PBM memory.\n"; 2867215976Sjmallett fail |= cvmx_error_add(&info); 2868215976Sjmallett 2869215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2870215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2871215976Sjmallett info.status_mask = 1ull<<4 /* bp_sub */; 2872215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2873215976Sjmallett info.enable_mask = 1ull<<4 /* bp_sub */; 2874215976Sjmallett info.flags = 0; 2875215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2876215976Sjmallett info.group_index = 0; 2877215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2878215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2879215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2880215976Sjmallett info.func = __cvmx_error_display; 2881215976Sjmallett info.user_info = (long) 2882215976Sjmallett "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n" 2883215976Sjmallett " supplied illegal value.\n"; 2884215976Sjmallett fail |= cvmx_error_add(&info); 2885215976Sjmallett 2886215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2887215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2888215976Sjmallett info.status_mask = 1ull<<5 /* dc_ovr */; 2889215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2890215976Sjmallett info.enable_mask = 1ull<<5 /* dc_ovr */; 2891215976Sjmallett info.flags = 0; 2892215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2893215976Sjmallett info.group_index = 0; 2894215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2895215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2896215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2897215976Sjmallett info.func = __cvmx_error_display; 2898215976Sjmallett info.user_info = (long) 2899215976Sjmallett "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"; 2900215976Sjmallett fail |= cvmx_error_add(&info); 2901215976Sjmallett 2902215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2903215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2904215976Sjmallett info.status_mask = 1ull<<6 /* cc_ovr */; 2905215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2906215976Sjmallett info.enable_mask = 1ull<<6 /* cc_ovr */; 2907215976Sjmallett info.flags = 0; 2908215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2909215976Sjmallett info.group_index = 0; 2910215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2911215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2912215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2913215976Sjmallett info.func = __cvmx_error_display; 2914215976Sjmallett info.user_info = (long) 2915215976Sjmallett "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"; 2916215976Sjmallett fail |= cvmx_error_add(&info); 2917215976Sjmallett 2918215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2919215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2920215976Sjmallett info.status_mask = 1ull<<7 /* c_coll */; 2921215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2922215976Sjmallett info.enable_mask = 1ull<<7 /* c_coll */; 2923215976Sjmallett info.flags = 0; 2924215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2925215976Sjmallett info.group_index = 0; 2926215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2927215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2928215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2929215976Sjmallett info.func = __cvmx_error_display; 2930215976Sjmallett info.user_info = (long) 2931215976Sjmallett "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n" 2932215976Sjmallett " collides.\n"; 2933215976Sjmallett fail |= cvmx_error_add(&info); 2934215976Sjmallett 2935215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2936215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2937215976Sjmallett info.status_mask = 1ull<<8 /* d_coll */; 2938215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2939215976Sjmallett info.enable_mask = 1ull<<8 /* d_coll */; 2940215976Sjmallett info.flags = 0; 2941215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2942215976Sjmallett info.group_index = 0; 2943215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2944215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2945215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2946215976Sjmallett info.func = __cvmx_error_display; 2947215976Sjmallett info.user_info = (long) 2948215976Sjmallett "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n" 2949215976Sjmallett " collides.\n"; 2950215976Sjmallett fail |= cvmx_error_add(&info); 2951215976Sjmallett 2952215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2953215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2954215976Sjmallett info.status_mask = 1ull<<9 /* bc_ovr */; 2955215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2956215976Sjmallett info.enable_mask = 1ull<<9 /* bc_ovr */; 2957215976Sjmallett info.flags = 0; 2958215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2959215976Sjmallett info.group_index = 0; 2960215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2961215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2962215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2963215976Sjmallett info.func = __cvmx_error_display; 2964215976Sjmallett info.user_info = (long) 2965215976Sjmallett "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"; 2966215976Sjmallett fail |= cvmx_error_add(&info); 2967215976Sjmallett 2968215976Sjmallett /* CVMX_TIM_REG_ERROR */ 2969215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2970215976Sjmallett info.status_addr = CVMX_TIM_REG_ERROR; 2971215976Sjmallett info.status_mask = 0xffffull<<0 /* mask */; 2972215976Sjmallett info.enable_addr = CVMX_TIM_REG_INT_MASK; 2973215976Sjmallett info.enable_mask = 0xffffull<<0 /* mask */; 2974215976Sjmallett info.flags = 0; 2975215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2976215976Sjmallett info.group_index = 0; 2977215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2978215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2979215976Sjmallett info.parent.status_mask = 1ull<<11 /* tim */; 2980215976Sjmallett info.func = __cvmx_error_display; 2981215976Sjmallett info.user_info = (long) 2982215976Sjmallett "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n"; 2983215976Sjmallett fail |= cvmx_error_add(&info); 2984215976Sjmallett 2985215976Sjmallett /* CVMX_PKO_REG_ERROR */ 2986215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2987215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 2988215976Sjmallett info.status_mask = 1ull<<0 /* parity */; 2989215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 2990215976Sjmallett info.enable_mask = 1ull<<0 /* parity */; 2991215976Sjmallett info.flags = 0; 2992215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2993215976Sjmallett info.group_index = 0; 2994215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2995215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2996215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 2997215976Sjmallett info.func = __cvmx_error_display; 2998215976Sjmallett info.user_info = (long) 2999215976Sjmallett "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n"; 3000215976Sjmallett fail |= cvmx_error_add(&info); 3001215976Sjmallett 3002215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3003215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 3004215976Sjmallett info.status_mask = 1ull<<1 /* doorbell */; 3005215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 3006215976Sjmallett info.enable_mask = 1ull<<1 /* doorbell */; 3007215976Sjmallett info.flags = 0; 3008215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3009215976Sjmallett info.group_index = 0; 3010215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3011215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3012215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 3013215976Sjmallett info.func = __cvmx_error_display; 3014215976Sjmallett info.user_info = (long) 3015215976Sjmallett "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 3016215976Sjmallett fail |= cvmx_error_add(&info); 3017215976Sjmallett 3018215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3019215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 3020215976Sjmallett info.status_mask = 1ull<<2 /* currzero */; 3021215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 3022215976Sjmallett info.enable_mask = 1ull<<2 /* currzero */; 3023215976Sjmallett info.flags = 0; 3024215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3025215976Sjmallett info.group_index = 0; 3026215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3027215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3028215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 3029215976Sjmallett info.func = __cvmx_error_display; 3030215976Sjmallett info.user_info = (long) 3031215976Sjmallett "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n"; 3032215976Sjmallett fail |= cvmx_error_add(&info); 3033215976Sjmallett 3034215976Sjmallett /* CVMX_POW_ECC_ERR */ 3035215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3036215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 3037215976Sjmallett info.status_mask = 1ull<<0 /* sbe */; 3038215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 3039215976Sjmallett info.enable_mask = 1ull<<2 /* sbe_ie */; 3040215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 3041215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3042215976Sjmallett info.group_index = 0; 3043215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3044215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3045215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 3046215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_sbe; 3047215976Sjmallett info.user_info = (long) 3048215976Sjmallett "ERROR POW_ECC_ERR[SBE]: Single bit error\n"; 3049215976Sjmallett fail |= cvmx_error_add(&info); 3050215976Sjmallett 3051215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3052215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 3053215976Sjmallett info.status_mask = 1ull<<1 /* dbe */; 3054215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 3055215976Sjmallett info.enable_mask = 1ull<<3 /* dbe_ie */; 3056215976Sjmallett info.flags = 0; 3057215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3058215976Sjmallett info.group_index = 0; 3059215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3060215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3061215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 3062215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_dbe; 3063215976Sjmallett info.user_info = (long) 3064215976Sjmallett "ERROR POW_ECC_ERR[DBE]: Double bit error\n"; 3065215976Sjmallett fail |= cvmx_error_add(&info); 3066215976Sjmallett 3067215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3068215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 3069215976Sjmallett info.status_mask = 1ull<<12 /* rpe */; 3070215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 3071215976Sjmallett info.enable_mask = 1ull<<13 /* rpe_ie */; 3072215976Sjmallett info.flags = 0; 3073215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3074215976Sjmallett info.group_index = 0; 3075215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3076215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3077215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 3078215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_rpe; 3079215976Sjmallett info.user_info = (long) 3080215976Sjmallett "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n"; 3081215976Sjmallett fail |= cvmx_error_add(&info); 3082215976Sjmallett 3083215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3084215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 3085215976Sjmallett info.status_mask = 0x1fffull<<16 /* iop */; 3086215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 3087215976Sjmallett info.enable_mask = 0x1fffull<<32 /* iop_ie */; 3088215976Sjmallett info.flags = 0; 3089215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3090215976Sjmallett info.group_index = 0; 3091215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3092215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3093215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 3094215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_iop; 3095215976Sjmallett info.user_info = (long) 3096215976Sjmallett "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n"; 3097215976Sjmallett fail |= cvmx_error_add(&info); 3098215976Sjmallett 3099215976Sjmallett /* CVMX_PEXP_NPEI_INT_SUM */ 3100215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3101215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3102215976Sjmallett info.status_mask = 1ull<<59 /* c0_ldwn */; 3103215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3104215976Sjmallett info.enable_mask = 1ull<<59 /* c0_ldwn */; 3105215976Sjmallett info.flags = 0; 3106215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3107215976Sjmallett info.group_index = 0; 3108215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3109215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3110215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3111215976Sjmallett info.func = __cvmx_error_display; 3112215976Sjmallett info.user_info = (long) 3113215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n"; 3114215976Sjmallett fail |= cvmx_error_add(&info); 3115215976Sjmallett 3116215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3117215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3118215976Sjmallett info.status_mask = 1ull<<21 /* c0_se */; 3119215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3120215976Sjmallett info.enable_mask = 1ull<<21 /* c0_se */; 3121215976Sjmallett info.flags = 0; 3122215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3123215976Sjmallett info.group_index = 0; 3124215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3125215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3126215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3127215976Sjmallett info.func = __cvmx_error_display; 3128215976Sjmallett info.user_info = (long) 3129215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n" 3130215976Sjmallett " Pcie Core 0. (cfg_sys_err_rc)\n"; 3131215976Sjmallett fail |= cvmx_error_add(&info); 3132215976Sjmallett 3133215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3134215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3135215976Sjmallett info.status_mask = 1ull<<38 /* c0_un_b0 */; 3136215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3137215976Sjmallett info.enable_mask = 1ull<<38 /* c0_un_b0 */; 3138215976Sjmallett info.flags = 0; 3139215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3140215976Sjmallett info.group_index = 0; 3141215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3142215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3143215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3144215976Sjmallett info.func = __cvmx_error_display; 3145215976Sjmallett info.user_info = (long) 3146215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n" 3147215976Sjmallett " Core 0.\n"; 3148215976Sjmallett fail |= cvmx_error_add(&info); 3149215976Sjmallett 3150215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3151215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3152215976Sjmallett info.status_mask = 1ull<<39 /* c0_un_b1 */; 3153215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3154215976Sjmallett info.enable_mask = 1ull<<39 /* c0_un_b1 */; 3155215976Sjmallett info.flags = 0; 3156215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3157215976Sjmallett info.group_index = 0; 3158215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3159215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3160215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3161215976Sjmallett info.func = __cvmx_error_display; 3162215976Sjmallett info.user_info = (long) 3163215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n" 3164215976Sjmallett " Core 0.\n"; 3165215976Sjmallett fail |= cvmx_error_add(&info); 3166215976Sjmallett 3167215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3168215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3169215976Sjmallett info.status_mask = 1ull<<40 /* c0_un_b2 */; 3170215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3171215976Sjmallett info.enable_mask = 1ull<<40 /* c0_un_b2 */; 3172215976Sjmallett info.flags = 0; 3173215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3174215976Sjmallett info.group_index = 0; 3175215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3176215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3177215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3178215976Sjmallett info.func = __cvmx_error_display; 3179215976Sjmallett info.user_info = (long) 3180215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n" 3181215976Sjmallett " Core 0.\n"; 3182215976Sjmallett fail |= cvmx_error_add(&info); 3183215976Sjmallett 3184215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3185215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3186215976Sjmallett info.status_mask = 1ull<<42 /* c0_un_bx */; 3187215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3188215976Sjmallett info.enable_mask = 1ull<<42 /* c0_un_bx */; 3189215976Sjmallett info.flags = 0; 3190215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3191215976Sjmallett info.group_index = 0; 3192215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3193215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3194215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3195215976Sjmallett info.func = __cvmx_error_display; 3196215976Sjmallett info.user_info = (long) 3197215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n" 3198215976Sjmallett " Core 0.\n"; 3199215976Sjmallett fail |= cvmx_error_add(&info); 3200215976Sjmallett 3201215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3202215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3203215976Sjmallett info.status_mask = 1ull<<53 /* c0_un_wf */; 3204215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3205215976Sjmallett info.enable_mask = 1ull<<53 /* c0_un_wf */; 3206215976Sjmallett info.flags = 0; 3207215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3208215976Sjmallett info.group_index = 0; 3209215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3210215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3211215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3212215976Sjmallett info.func = __cvmx_error_display; 3213215976Sjmallett info.user_info = (long) 3214215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n" 3215215976Sjmallett " register. Core0.\n"; 3216215976Sjmallett fail |= cvmx_error_add(&info); 3217215976Sjmallett 3218215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3219215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3220215976Sjmallett info.status_mask = 1ull<<41 /* c0_un_wi */; 3221215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3222215976Sjmallett info.enable_mask = 1ull<<41 /* c0_un_wi */; 3223215976Sjmallett info.flags = 0; 3224215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3225215976Sjmallett info.group_index = 0; 3226215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3227215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3228215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3229215976Sjmallett info.func = __cvmx_error_display; 3230215976Sjmallett info.user_info = (long) 3231215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n" 3232215976Sjmallett " Core 0.\n"; 3233215976Sjmallett fail |= cvmx_error_add(&info); 3234215976Sjmallett 3235215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3236215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3237215976Sjmallett info.status_mask = 1ull<<33 /* c0_up_b0 */; 3238215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3239215976Sjmallett info.enable_mask = 1ull<<33 /* c0_up_b0 */; 3240215976Sjmallett info.flags = 0; 3241215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3242215976Sjmallett info.group_index = 0; 3243215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3244215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3245215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3246215976Sjmallett info.func = __cvmx_error_display; 3247215976Sjmallett info.user_info = (long) 3248215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n" 3249215976Sjmallett " Core 0.\n"; 3250215976Sjmallett fail |= cvmx_error_add(&info); 3251215976Sjmallett 3252215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3253215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3254215976Sjmallett info.status_mask = 1ull<<34 /* c0_up_b1 */; 3255215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3256215976Sjmallett info.enable_mask = 1ull<<34 /* c0_up_b1 */; 3257215976Sjmallett info.flags = 0; 3258215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3259215976Sjmallett info.group_index = 0; 3260215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3261215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3262215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3263215976Sjmallett info.func = __cvmx_error_display; 3264215976Sjmallett info.user_info = (long) 3265215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n" 3266215976Sjmallett " Core 0.\n"; 3267215976Sjmallett fail |= cvmx_error_add(&info); 3268215976Sjmallett 3269215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3270215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3271215976Sjmallett info.status_mask = 1ull<<35 /* c0_up_b2 */; 3272215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3273215976Sjmallett info.enable_mask = 1ull<<35 /* c0_up_b2 */; 3274215976Sjmallett info.flags = 0; 3275215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3276215976Sjmallett info.group_index = 0; 3277215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3278215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3279215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3280215976Sjmallett info.func = __cvmx_error_display; 3281215976Sjmallett info.user_info = (long) 3282215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n" 3283215976Sjmallett " Core 0.\n"; 3284215976Sjmallett fail |= cvmx_error_add(&info); 3285215976Sjmallett 3286215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3287215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3288215976Sjmallett info.status_mask = 1ull<<37 /* c0_up_bx */; 3289215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3290215976Sjmallett info.enable_mask = 1ull<<37 /* c0_up_bx */; 3291215976Sjmallett info.flags = 0; 3292215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3293215976Sjmallett info.group_index = 0; 3294215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3295215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3296215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3297215976Sjmallett info.func = __cvmx_error_display; 3298215976Sjmallett info.user_info = (long) 3299215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n" 3300215976Sjmallett " Core 0.\n"; 3301215976Sjmallett fail |= cvmx_error_add(&info); 3302215976Sjmallett 3303215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3304215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3305215976Sjmallett info.status_mask = 1ull<<55 /* c0_up_wf */; 3306215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3307215976Sjmallett info.enable_mask = 1ull<<55 /* c0_up_wf */; 3308215976Sjmallett info.flags = 0; 3309215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3310215976Sjmallett info.group_index = 0; 3311215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3312215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3313215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3314215976Sjmallett info.func = __cvmx_error_display; 3315215976Sjmallett info.user_info = (long) 3316215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n" 3317215976Sjmallett " register. Core0.\n"; 3318215976Sjmallett fail |= cvmx_error_add(&info); 3319215976Sjmallett 3320215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3321215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3322215976Sjmallett info.status_mask = 1ull<<36 /* c0_up_wi */; 3323215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3324215976Sjmallett info.enable_mask = 1ull<<36 /* c0_up_wi */; 3325215976Sjmallett info.flags = 0; 3326215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3327215976Sjmallett info.group_index = 0; 3328215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3329215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3330215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3331215976Sjmallett info.func = __cvmx_error_display; 3332215976Sjmallett info.user_info = (long) 3333215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n" 3334215976Sjmallett " Core 0.\n"; 3335215976Sjmallett fail |= cvmx_error_add(&info); 3336215976Sjmallett 3337215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3338215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3339215976Sjmallett info.status_mask = 1ull<<23 /* c0_wake */; 3340215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3341215976Sjmallett info.enable_mask = 1ull<<23 /* c0_wake */; 3342215976Sjmallett info.flags = 0; 3343215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3344215976Sjmallett info.group_index = 0; 3345215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3346215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3347215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3348215976Sjmallett info.func = __cvmx_error_display; 3349215976Sjmallett info.user_info = (long) 3350215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n" 3351215976Sjmallett " Pcie Core 0. (wake_n)\n" 3352215976Sjmallett " Octeon will never generate this interrupt.\n"; 3353215976Sjmallett fail |= cvmx_error_add(&info); 3354215976Sjmallett 3355215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3356215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3357215976Sjmallett info.status_mask = 1ull<<22 /* crs0_dr */; 3358215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3359215976Sjmallett info.enable_mask = 1ull<<22 /* crs0_dr */; 3360215976Sjmallett info.flags = 0; 3361215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3362215976Sjmallett info.group_index = 0; 3363215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3364215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3365215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3366215976Sjmallett info.func = __cvmx_error_display; 3367215976Sjmallett info.user_info = (long) 3368215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n"; 3369215976Sjmallett fail |= cvmx_error_add(&info); 3370215976Sjmallett 3371215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3372215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3373215976Sjmallett info.status_mask = 1ull<<20 /* crs0_er */; 3374215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3375215976Sjmallett info.enable_mask = 1ull<<20 /* crs0_er */; 3376215976Sjmallett info.flags = 0; 3377215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3378215976Sjmallett info.group_index = 0; 3379215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3380215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3381215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3382215976Sjmallett info.func = __cvmx_error_display; 3383215976Sjmallett info.user_info = (long) 3384215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n"; 3385215976Sjmallett fail |= cvmx_error_add(&info); 3386215976Sjmallett 3387215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3388215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3389215976Sjmallett info.status_mask = 1ull<<60 /* c1_ldwn */; 3390215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3391215976Sjmallett info.enable_mask = 1ull<<60 /* c1_ldwn */; 3392215976Sjmallett info.flags = 0; 3393215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3394215976Sjmallett info.group_index = 1; 3395215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3396215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3397215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3398215976Sjmallett info.func = __cvmx_error_display; 3399215976Sjmallett info.user_info = (long) 3400215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n"; 3401215976Sjmallett fail |= cvmx_error_add(&info); 3402215976Sjmallett 3403215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3404215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3405215976Sjmallett info.status_mask = 1ull<<28 /* c1_se */; 3406215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3407215976Sjmallett info.enable_mask = 1ull<<28 /* c1_se */; 3408215976Sjmallett info.flags = 0; 3409215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3410215976Sjmallett info.group_index = 1; 3411215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3412215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3413215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3414215976Sjmallett info.func = __cvmx_error_display; 3415215976Sjmallett info.user_info = (long) 3416215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n" 3417215976Sjmallett " Pcie Core 1. (cfg_sys_err_rc)\n"; 3418215976Sjmallett fail |= cvmx_error_add(&info); 3419215976Sjmallett 3420215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3421215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3422215976Sjmallett info.status_mask = 1ull<<48 /* c1_un_b0 */; 3423215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3424215976Sjmallett info.enable_mask = 1ull<<48 /* c1_un_b0 */; 3425215976Sjmallett info.flags = 0; 3426215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3427215976Sjmallett info.group_index = 1; 3428215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3429215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3430215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3431215976Sjmallett info.func = __cvmx_error_display; 3432215976Sjmallett info.user_info = (long) 3433215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n" 3434215976Sjmallett " Core 1.\n"; 3435215976Sjmallett fail |= cvmx_error_add(&info); 3436215976Sjmallett 3437215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3438215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3439215976Sjmallett info.status_mask = 1ull<<49 /* c1_un_b1 */; 3440215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3441215976Sjmallett info.enable_mask = 1ull<<49 /* c1_un_b1 */; 3442215976Sjmallett info.flags = 0; 3443215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3444215976Sjmallett info.group_index = 1; 3445215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3446215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3447215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3448215976Sjmallett info.func = __cvmx_error_display; 3449215976Sjmallett info.user_info = (long) 3450215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n" 3451215976Sjmallett " Core 1.\n"; 3452215976Sjmallett fail |= cvmx_error_add(&info); 3453215976Sjmallett 3454215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3455215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3456215976Sjmallett info.status_mask = 1ull<<50 /* c1_un_b2 */; 3457215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3458215976Sjmallett info.enable_mask = 1ull<<50 /* c1_un_b2 */; 3459215976Sjmallett info.flags = 0; 3460215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3461215976Sjmallett info.group_index = 1; 3462215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3463215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3464215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3465215976Sjmallett info.func = __cvmx_error_display; 3466215976Sjmallett info.user_info = (long) 3467215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n" 3468215976Sjmallett " Core 1.\n"; 3469215976Sjmallett fail |= cvmx_error_add(&info); 3470215976Sjmallett 3471215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3472215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3473215976Sjmallett info.status_mask = 1ull<<52 /* c1_un_bx */; 3474215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3475215976Sjmallett info.enable_mask = 1ull<<52 /* c1_un_bx */; 3476215976Sjmallett info.flags = 0; 3477215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3478215976Sjmallett info.group_index = 1; 3479215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3480215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3481215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3482215976Sjmallett info.func = __cvmx_error_display; 3483215976Sjmallett info.user_info = (long) 3484215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n" 3485215976Sjmallett " Core 1.\n"; 3486215976Sjmallett fail |= cvmx_error_add(&info); 3487215976Sjmallett 3488215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3489215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3490215976Sjmallett info.status_mask = 1ull<<54 /* c1_un_wf */; 3491215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3492215976Sjmallett info.enable_mask = 1ull<<54 /* c1_un_wf */; 3493215976Sjmallett info.flags = 0; 3494215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3495215976Sjmallett info.group_index = 1; 3496215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3497215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3498215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3499215976Sjmallett info.func = __cvmx_error_display; 3500215976Sjmallett info.user_info = (long) 3501215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n" 3502215976Sjmallett " register. Core1.\n"; 3503215976Sjmallett fail |= cvmx_error_add(&info); 3504215976Sjmallett 3505215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3506215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3507215976Sjmallett info.status_mask = 1ull<<51 /* c1_un_wi */; 3508215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3509215976Sjmallett info.enable_mask = 1ull<<51 /* c1_un_wi */; 3510215976Sjmallett info.flags = 0; 3511215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3512215976Sjmallett info.group_index = 1; 3513215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3514215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3515215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3516215976Sjmallett info.func = __cvmx_error_display; 3517215976Sjmallett info.user_info = (long) 3518215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n" 3519215976Sjmallett " Core 1.\n"; 3520215976Sjmallett fail |= cvmx_error_add(&info); 3521215976Sjmallett 3522215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3523215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3524215976Sjmallett info.status_mask = 1ull<<43 /* c1_up_b0 */; 3525215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3526215976Sjmallett info.enable_mask = 1ull<<43 /* c1_up_b0 */; 3527215976Sjmallett info.flags = 0; 3528215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3529215976Sjmallett info.group_index = 1; 3530215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3531215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3532215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3533215976Sjmallett info.func = __cvmx_error_display; 3534215976Sjmallett info.user_info = (long) 3535215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n" 3536215976Sjmallett " Core 1.\n"; 3537215976Sjmallett fail |= cvmx_error_add(&info); 3538215976Sjmallett 3539215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3540215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3541215976Sjmallett info.status_mask = 1ull<<44 /* c1_up_b1 */; 3542215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3543215976Sjmallett info.enable_mask = 1ull<<44 /* c1_up_b1 */; 3544215976Sjmallett info.flags = 0; 3545215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3546215976Sjmallett info.group_index = 1; 3547215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3548215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3549215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3550215976Sjmallett info.func = __cvmx_error_display; 3551215976Sjmallett info.user_info = (long) 3552215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsuppored P-TLP for Bar1.\n" 3553215976Sjmallett " Core 1.\n"; 3554215976Sjmallett fail |= cvmx_error_add(&info); 3555215976Sjmallett 3556215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3557215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3558215976Sjmallett info.status_mask = 1ull<<45 /* c1_up_b2 */; 3559215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3560215976Sjmallett info.enable_mask = 1ull<<45 /* c1_up_b2 */; 3561215976Sjmallett info.flags = 0; 3562215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3563215976Sjmallett info.group_index = 1; 3564215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3565215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3566215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3567215976Sjmallett info.func = __cvmx_error_display; 3568215976Sjmallett info.user_info = (long) 3569215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n" 3570215976Sjmallett " Core 1.\n"; 3571215976Sjmallett fail |= cvmx_error_add(&info); 3572215976Sjmallett 3573215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3574215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3575215976Sjmallett info.status_mask = 1ull<<47 /* c1_up_bx */; 3576215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3577215976Sjmallett info.enable_mask = 1ull<<47 /* c1_up_bx */; 3578215976Sjmallett info.flags = 0; 3579215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3580215976Sjmallett info.group_index = 1; 3581215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3582215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3583215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3584215976Sjmallett info.func = __cvmx_error_display; 3585215976Sjmallett info.user_info = (long) 3586215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n" 3587215976Sjmallett " Core 1.\n"; 3588215976Sjmallett fail |= cvmx_error_add(&info); 3589215976Sjmallett 3590215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3591215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3592215976Sjmallett info.status_mask = 1ull<<56 /* c1_up_wf */; 3593215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3594215976Sjmallett info.enable_mask = 1ull<<56 /* c1_up_wf */; 3595215976Sjmallett info.flags = 0; 3596215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3597215976Sjmallett info.group_index = 1; 3598215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3599215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3600215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3601215976Sjmallett info.func = __cvmx_error_display; 3602215976Sjmallett info.user_info = (long) 3603215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n" 3604215976Sjmallett " register. Core1.\n"; 3605215976Sjmallett fail |= cvmx_error_add(&info); 3606215976Sjmallett 3607215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3608215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3609215976Sjmallett info.status_mask = 1ull<<46 /* c1_up_wi */; 3610215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3611215976Sjmallett info.enable_mask = 1ull<<46 /* c1_up_wi */; 3612215976Sjmallett info.flags = 0; 3613215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3614215976Sjmallett info.group_index = 1; 3615215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3616215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3617215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3618215976Sjmallett info.func = __cvmx_error_display; 3619215976Sjmallett info.user_info = (long) 3620215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n" 3621215976Sjmallett " Core 1.\n"; 3622215976Sjmallett fail |= cvmx_error_add(&info); 3623215976Sjmallett 3624215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3625215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3626215976Sjmallett info.status_mask = 1ull<<30 /* c1_wake */; 3627215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3628215976Sjmallett info.enable_mask = 1ull<<30 /* c1_wake */; 3629215976Sjmallett info.flags = 0; 3630215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3631215976Sjmallett info.group_index = 1; 3632215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3633215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3634215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3635215976Sjmallett info.func = __cvmx_error_display; 3636215976Sjmallett info.user_info = (long) 3637215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n" 3638215976Sjmallett " Pcie Core 1. (wake_n)\n" 3639215976Sjmallett " Octeon will never generate this interrupt.\n"; 3640215976Sjmallett fail |= cvmx_error_add(&info); 3641215976Sjmallett 3642215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3643215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3644215976Sjmallett info.status_mask = 1ull<<29 /* crs1_dr */; 3645215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3646215976Sjmallett info.enable_mask = 1ull<<29 /* crs1_dr */; 3647215976Sjmallett info.flags = 0; 3648215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3649215976Sjmallett info.group_index = 1; 3650215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3651215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3652215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3653215976Sjmallett info.func = __cvmx_error_display; 3654215976Sjmallett info.user_info = (long) 3655215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n"; 3656215976Sjmallett fail |= cvmx_error_add(&info); 3657215976Sjmallett 3658215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3659215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3660215976Sjmallett info.status_mask = 1ull<<27 /* crs1_er */; 3661215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3662215976Sjmallett info.enable_mask = 1ull<<27 /* crs1_er */; 3663215976Sjmallett info.flags = 0; 3664215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3665215976Sjmallett info.group_index = 1; 3666215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3667215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3668215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3669215976Sjmallett info.func = __cvmx_error_display; 3670215976Sjmallett info.user_info = (long) 3671215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n"; 3672215976Sjmallett fail |= cvmx_error_add(&info); 3673215976Sjmallett 3674215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3675215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3676215976Sjmallett info.status_mask = 1ull<<2 /* bar0_to */; 3677215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3678215976Sjmallett info.enable_mask = 1ull<<2 /* bar0_to */; 3679215976Sjmallett info.flags = 0; 3680215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3681215976Sjmallett info.group_index = 0; 3682215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3683215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3684215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3685215976Sjmallett info.func = __cvmx_error_display; 3686215976Sjmallett info.user_info = (long) 3687215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n" 3688215976Sjmallett " read-data/commit in 0xffff core clocks.\n"; 3689215976Sjmallett fail |= cvmx_error_add(&info); 3690215976Sjmallett 3691215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3692215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3693215976Sjmallett info.status_mask = 1ull<<4 /* dma0dbo */; 3694215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3695215976Sjmallett info.enable_mask = 1ull<<4 /* dma0dbo */; 3696215976Sjmallett info.flags = 0; 3697215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3698215976Sjmallett info.group_index = 0; 3699215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3700215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3701215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3702215976Sjmallett info.func = __cvmx_error_display; 3703215976Sjmallett info.user_info = (long) 3704215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n" 3705215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3706215976Sjmallett fail |= cvmx_error_add(&info); 3707215976Sjmallett 3708215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3709215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3710215976Sjmallett info.status_mask = 1ull<<5 /* dma1dbo */; 3711215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3712215976Sjmallett info.enable_mask = 1ull<<5 /* dma1dbo */; 3713215976Sjmallett info.flags = 0; 3714215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3715215976Sjmallett info.group_index = 0; 3716215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3717215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3718215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3719215976Sjmallett info.func = __cvmx_error_display; 3720215976Sjmallett info.user_info = (long) 3721215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n" 3722215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3723215976Sjmallett fail |= cvmx_error_add(&info); 3724215976Sjmallett 3725215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3726215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3727215976Sjmallett info.status_mask = 1ull<<6 /* dma2dbo */; 3728215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3729215976Sjmallett info.enable_mask = 1ull<<6 /* dma2dbo */; 3730215976Sjmallett info.flags = 0; 3731215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3732215976Sjmallett info.group_index = 0; 3733215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3734215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3735215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3736215976Sjmallett info.func = __cvmx_error_display; 3737215976Sjmallett info.user_info = (long) 3738215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n" 3739215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3740215976Sjmallett fail |= cvmx_error_add(&info); 3741215976Sjmallett 3742215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3743215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3744215976Sjmallett info.status_mask = 1ull<<7 /* dma3dbo */; 3745215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3746215976Sjmallett info.enable_mask = 1ull<<7 /* dma3dbo */; 3747215976Sjmallett info.flags = 0; 3748215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3749215976Sjmallett info.group_index = 0; 3750215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3751215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3752215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3753215976Sjmallett info.func = __cvmx_error_display; 3754215976Sjmallett info.user_info = (long) 3755215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n" 3756215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3757215976Sjmallett fail |= cvmx_error_add(&info); 3758215976Sjmallett 3759215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3760215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3761215976Sjmallett info.status_mask = 1ull<<3 /* iob2big */; 3762215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3763215976Sjmallett info.enable_mask = 1ull<<3 /* iob2big */; 3764215976Sjmallett info.flags = 0; 3765215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3766215976Sjmallett info.group_index = 0; 3767215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3768215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3769215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3770215976Sjmallett info.func = __cvmx_error_display; 3771215976Sjmallett info.user_info = (long) 3772215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n"; 3773215976Sjmallett fail |= cvmx_error_add(&info); 3774215976Sjmallett 3775215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3776215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3777215976Sjmallett info.status_mask = 1ull<<0 /* rml_rto */; 3778215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3779215976Sjmallett info.enable_mask = 1ull<<0 /* rml_rto */; 3780215976Sjmallett info.flags = 0; 3781215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3782215976Sjmallett info.group_index = 0; 3783215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3784215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3785215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3786215976Sjmallett info.func = __cvmx_error_display; 3787215976Sjmallett info.user_info = (long) 3788215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n"; 3789215976Sjmallett fail |= cvmx_error_add(&info); 3790215976Sjmallett 3791215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3792215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3793215976Sjmallett info.status_mask = 1ull<<1 /* rml_wto */; 3794215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3795215976Sjmallett info.enable_mask = 1ull<<1 /* rml_wto */; 3796215976Sjmallett info.flags = 0; 3797215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3798215976Sjmallett info.group_index = 0; 3799215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3800215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3801215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3802215976Sjmallett info.func = __cvmx_error_display; 3803215976Sjmallett info.user_info = (long) 3804215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n"; 3805215976Sjmallett fail |= cvmx_error_add(&info); 3806215976Sjmallett 3807215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3808215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3809215976Sjmallett info.status_mask = 1ull<<8 /* dma4dbo */; 3810215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3811215976Sjmallett info.enable_mask = 1ull<<8 /* dma4dbo */; 3812215976Sjmallett info.flags = 0; 3813215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3814215976Sjmallett info.group_index = 0; 3815215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3816215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3817215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3818215976Sjmallett info.func = __cvmx_error_display; 3819215976Sjmallett info.user_info = (long) 3820215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n" 3821215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3822215976Sjmallett fail |= cvmx_error_add(&info); 3823215976Sjmallett 3824215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3825215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3826215976Sjmallett info.status_mask = 0; 3827215976Sjmallett info.enable_addr = 0; 3828215976Sjmallett info.enable_mask = 0; 3829215976Sjmallett info.flags = 0; 3830215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3831215976Sjmallett info.group_index = 0; 3832215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3833215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3834215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3835215976Sjmallett info.func = __cvmx_error_decode; 3836215976Sjmallett info.user_info = 0; 3837215976Sjmallett fail |= cvmx_error_add(&info); 3838215976Sjmallett 3839215976Sjmallett /* CVMX_PESCX_DBG_INFO(0) */ 3840215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3841215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3842215976Sjmallett info.status_mask = 1ull<<0 /* spoison */; 3843215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3844215976Sjmallett info.enable_mask = 1ull<<0 /* spoison */; 3845215976Sjmallett info.flags = 0; 3846215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3847215976Sjmallett info.group_index = 0; 3848215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3849215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3850215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3851215976Sjmallett info.func = __cvmx_error_display; 3852215976Sjmallett info.user_info = (long) 3853215976Sjmallett "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n" 3854215976Sjmallett " peai__client0_tlp_ep & peai__client0_tlp_hv\n"; 3855215976Sjmallett fail |= cvmx_error_add(&info); 3856215976Sjmallett 3857215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3858215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3859215976Sjmallett info.status_mask = 1ull<<2 /* rtlplle */; 3860215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3861215976Sjmallett info.enable_mask = 1ull<<2 /* rtlplle */; 3862215976Sjmallett info.flags = 0; 3863215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3864215976Sjmallett info.group_index = 0; 3865215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3866215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3867215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3868215976Sjmallett info.func = __cvmx_error_display; 3869215976Sjmallett info.user_info = (long) 3870215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n" 3871215976Sjmallett " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n"; 3872215976Sjmallett fail |= cvmx_error_add(&info); 3873215976Sjmallett 3874215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3875215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3876215976Sjmallett info.status_mask = 1ull<<3 /* recrce */; 3877215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3878215976Sjmallett info.enable_mask = 1ull<<3 /* recrce */; 3879215976Sjmallett info.flags = 0; 3880215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3881215976Sjmallett info.group_index = 0; 3882215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3883215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3884215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3885215976Sjmallett info.func = __cvmx_error_display; 3886215976Sjmallett info.user_info = (long) 3887215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n" 3888215976Sjmallett " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n"; 3889215976Sjmallett fail |= cvmx_error_add(&info); 3890215976Sjmallett 3891215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3892215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3893215976Sjmallett info.status_mask = 1ull<<4 /* rpoison */; 3894215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3895215976Sjmallett info.enable_mask = 1ull<<4 /* rpoison */; 3896215976Sjmallett info.flags = 0; 3897215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3898215976Sjmallett info.group_index = 0; 3899215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3900215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3901215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3902215976Sjmallett info.func = __cvmx_error_display; 3903215976Sjmallett info.user_info = (long) 3904215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n" 3905215976Sjmallett " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n"; 3906215976Sjmallett fail |= cvmx_error_add(&info); 3907215976Sjmallett 3908215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3909215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3910215976Sjmallett info.status_mask = 1ull<<5 /* rcemrc */; 3911215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3912215976Sjmallett info.enable_mask = 1ull<<5 /* rcemrc */; 3913215976Sjmallett info.flags = 0; 3914215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3915215976Sjmallett info.group_index = 0; 3916215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3917215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3918215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3919215976Sjmallett info.func = __cvmx_error_display; 3920215976Sjmallett info.user_info = (long) 3921215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n" 3922215976Sjmallett " pedc_radm_correctable_err\n"; 3923215976Sjmallett fail |= cvmx_error_add(&info); 3924215976Sjmallett 3925215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3926215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3927215976Sjmallett info.status_mask = 1ull<<6 /* rnfemrc */; 3928215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3929215976Sjmallett info.enable_mask = 1ull<<6 /* rnfemrc */; 3930215976Sjmallett info.flags = 0; 3931215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3932215976Sjmallett info.group_index = 0; 3933215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3934215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3935215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3936215976Sjmallett info.func = __cvmx_error_display; 3937215976Sjmallett info.user_info = (long) 3938215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n" 3939215976Sjmallett " pedc_radm_nonfatal_err\n"; 3940215976Sjmallett fail |= cvmx_error_add(&info); 3941215976Sjmallett 3942215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3943215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3944215976Sjmallett info.status_mask = 1ull<<7 /* rfemrc */; 3945215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3946215976Sjmallett info.enable_mask = 1ull<<7 /* rfemrc */; 3947215976Sjmallett info.flags = 0; 3948215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3949215976Sjmallett info.group_index = 0; 3950215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3951215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3952215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3953215976Sjmallett info.func = __cvmx_error_display; 3954215976Sjmallett info.user_info = (long) 3955215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n" 3956215976Sjmallett " pedc_radm_fatal_err\n" 3957215976Sjmallett " Bit set when a message with ERR_FATAL is set.\n"; 3958215976Sjmallett fail |= cvmx_error_add(&info); 3959215976Sjmallett 3960215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3961215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3962215976Sjmallett info.status_mask = 1ull<<8 /* rpmerc */; 3963215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3964215976Sjmallett info.enable_mask = 1ull<<8 /* rpmerc */; 3965215976Sjmallett info.flags = 0; 3966215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3967215976Sjmallett info.group_index = 0; 3968215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3969215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3970215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3971215976Sjmallett info.func = __cvmx_error_display; 3972215976Sjmallett info.user_info = (long) 3973215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n" 3974215976Sjmallett " pedc_radm_pm_pme\n"; 3975215976Sjmallett fail |= cvmx_error_add(&info); 3976215976Sjmallett 3977215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3978215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3979215976Sjmallett info.status_mask = 1ull<<9 /* rptamrc */; 3980215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3981215976Sjmallett info.enable_mask = 1ull<<9 /* rptamrc */; 3982215976Sjmallett info.flags = 0; 3983215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3984215976Sjmallett info.group_index = 0; 3985215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3986215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3987215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3988215976Sjmallett info.func = __cvmx_error_display; 3989215976Sjmallett info.user_info = (long) 3990215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n" 3991215976Sjmallett " (RC Mode only)\n" 3992215976Sjmallett " pedc_radm_pm_to_ack\n"; 3993215976Sjmallett fail |= cvmx_error_add(&info); 3994215976Sjmallett 3995215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3996215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3997215976Sjmallett info.status_mask = 1ull<<10 /* rumep */; 3998215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3999215976Sjmallett info.enable_mask = 1ull<<10 /* rumep */; 4000215976Sjmallett info.flags = 0; 4001215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4002215976Sjmallett info.group_index = 0; 4003215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4004215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4005215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4006215976Sjmallett info.func = __cvmx_error_display; 4007215976Sjmallett info.user_info = (long) 4008215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n" 4009215976Sjmallett " pedc_radm_msg_unlock\n"; 4010215976Sjmallett fail |= cvmx_error_add(&info); 4011215976Sjmallett 4012215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4013215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4014215976Sjmallett info.status_mask = 1ull<<11 /* rvdm */; 4015215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4016215976Sjmallett info.enable_mask = 1ull<<11 /* rvdm */; 4017215976Sjmallett info.flags = 0; 4018215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4019215976Sjmallett info.group_index = 0; 4020215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4021215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4022215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4023215976Sjmallett info.func = __cvmx_error_display; 4024215976Sjmallett info.user_info = (long) 4025215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n" 4026215976Sjmallett " pedc_radm_vendor_msg\n"; 4027215976Sjmallett fail |= cvmx_error_add(&info); 4028215976Sjmallett 4029215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4030215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4031215976Sjmallett info.status_mask = 1ull<<12 /* acto */; 4032215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4033215976Sjmallett info.enable_mask = 1ull<<12 /* acto */; 4034215976Sjmallett info.flags = 0; 4035215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4036215976Sjmallett info.group_index = 0; 4037215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4038215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4039215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4040215976Sjmallett info.func = __cvmx_error_display; 4041215976Sjmallett info.user_info = (long) 4042215976Sjmallett "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n" 4043215976Sjmallett " pedc_radm_cpl_timeout\n"; 4044215976Sjmallett fail |= cvmx_error_add(&info); 4045215976Sjmallett 4046215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4047215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4048215976Sjmallett info.status_mask = 1ull<<13 /* rte */; 4049215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4050215976Sjmallett info.enable_mask = 1ull<<13 /* rte */; 4051215976Sjmallett info.flags = 0; 4052215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4053215976Sjmallett info.group_index = 0; 4054215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4055215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4056215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4057215976Sjmallett info.func = __cvmx_error_display; 4058215976Sjmallett info.user_info = (long) 4059215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n" 4060215976Sjmallett " xdlh_replay_timeout_err\n" 4061215976Sjmallett " This bit is set when the REPLAY_TIMER expires in\n" 4062215976Sjmallett " the PCIE core. The probability of this bit being\n" 4063215976Sjmallett " set will increase with the traffic load.\n"; 4064215976Sjmallett fail |= cvmx_error_add(&info); 4065215976Sjmallett 4066215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4067215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4068215976Sjmallett info.status_mask = 1ull<<14 /* mre */; 4069215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4070215976Sjmallett info.enable_mask = 1ull<<14 /* mre */; 4071215976Sjmallett info.flags = 0; 4072215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4073215976Sjmallett info.group_index = 0; 4074215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4075215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4076215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4077215976Sjmallett info.func = __cvmx_error_display; 4078215976Sjmallett info.user_info = (long) 4079215976Sjmallett "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n" 4080215976Sjmallett " xdlh_replay_num_rlover_err\n"; 4081215976Sjmallett fail |= cvmx_error_add(&info); 4082215976Sjmallett 4083215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4084215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4085215976Sjmallett info.status_mask = 1ull<<15 /* rdwdle */; 4086215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4087215976Sjmallett info.enable_mask = 1ull<<15 /* rdwdle */; 4088215976Sjmallett info.flags = 0; 4089215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4090215976Sjmallett info.group_index = 0; 4091215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4092215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4093215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4094215976Sjmallett info.func = __cvmx_error_display; 4095215976Sjmallett info.user_info = (long) 4096215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n" 4097215976Sjmallett " rdlh_bad_dllp_err\n"; 4098215976Sjmallett fail |= cvmx_error_add(&info); 4099215976Sjmallett 4100215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4101215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4102215976Sjmallett info.status_mask = 1ull<<16 /* rtwdle */; 4103215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4104215976Sjmallett info.enable_mask = 1ull<<16 /* rtwdle */; 4105215976Sjmallett info.flags = 0; 4106215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4107215976Sjmallett info.group_index = 0; 4108215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4109215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4110215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4111215976Sjmallett info.func = __cvmx_error_display; 4112215976Sjmallett info.user_info = (long) 4113215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n" 4114215976Sjmallett " rdlh_bad_tlp_err\n"; 4115215976Sjmallett fail |= cvmx_error_add(&info); 4116215976Sjmallett 4117215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4118215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4119215976Sjmallett info.status_mask = 1ull<<17 /* dpeoosd */; 4120215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4121215976Sjmallett info.enable_mask = 1ull<<17 /* dpeoosd */; 4122215976Sjmallett info.flags = 0; 4123215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4124215976Sjmallett info.group_index = 0; 4125215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4126215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4127215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4128215976Sjmallett info.func = __cvmx_error_display; 4129215976Sjmallett info.user_info = (long) 4130215976Sjmallett "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n" 4131215976Sjmallett " rdlh_prot_err\n"; 4132215976Sjmallett fail |= cvmx_error_add(&info); 4133215976Sjmallett 4134215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4135215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4136215976Sjmallett info.status_mask = 1ull<<18 /* fcpvwt */; 4137215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4138215976Sjmallett info.enable_mask = 1ull<<18 /* fcpvwt */; 4139215976Sjmallett info.flags = 0; 4140215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4141215976Sjmallett info.group_index = 0; 4142215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4143215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4144215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4145215976Sjmallett info.func = __cvmx_error_display; 4146215976Sjmallett info.user_info = (long) 4147215976Sjmallett "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n" 4148215976Sjmallett " rtlh_fc_prot_err\n"; 4149215976Sjmallett fail |= cvmx_error_add(&info); 4150215976Sjmallett 4151215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4152215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4153215976Sjmallett info.status_mask = 1ull<<19 /* rpe */; 4154215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4155215976Sjmallett info.enable_mask = 1ull<<19 /* rpe */; 4156215976Sjmallett info.flags = 0; 4157215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4158215976Sjmallett info.group_index = 0; 4159215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4160215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4161215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4162215976Sjmallett info.func = __cvmx_error_display; 4163215976Sjmallett info.user_info = (long) 4164215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n" 4165215976Sjmallett " (RxStatus = 3b100) or disparity error\n" 4166215976Sjmallett " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n" 4167215976Sjmallett " be asserted.\n" 4168215976Sjmallett " rmlh_rcvd_err\n"; 4169215976Sjmallett fail |= cvmx_error_add(&info); 4170215976Sjmallett 4171215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4172215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4173215976Sjmallett info.status_mask = 1ull<<20 /* fcuv */; 4174215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4175215976Sjmallett info.enable_mask = 1ull<<20 /* fcuv */; 4176215976Sjmallett info.flags = 0; 4177215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4178215976Sjmallett info.group_index = 0; 4179215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4180215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4181215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4182215976Sjmallett info.func = __cvmx_error_display; 4183215976Sjmallett info.user_info = (long) 4184215976Sjmallett "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n" 4185215976Sjmallett " int_xadm_fc_prot_err\n"; 4186215976Sjmallett fail |= cvmx_error_add(&info); 4187215976Sjmallett 4188215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4189215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4190215976Sjmallett info.status_mask = 1ull<<21 /* rqo */; 4191215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4192215976Sjmallett info.enable_mask = 1ull<<21 /* rqo */; 4193215976Sjmallett info.flags = 0; 4194215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4195215976Sjmallett info.group_index = 0; 4196215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4197215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4198215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4199215976Sjmallett info.func = __cvmx_error_display; 4200215976Sjmallett info.user_info = (long) 4201215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n" 4202215976Sjmallett " flow control advertisements are ignored\n" 4203215976Sjmallett " radm_qoverflow\n"; 4204215976Sjmallett fail |= cvmx_error_add(&info); 4205215976Sjmallett 4206215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4207215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4208215976Sjmallett info.status_mask = 1ull<<22 /* rauc */; 4209215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4210215976Sjmallett info.enable_mask = 1ull<<22 /* rauc */; 4211215976Sjmallett info.flags = 0; 4212215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4213215976Sjmallett info.group_index = 0; 4214215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4215215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4216215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4217215976Sjmallett info.func = __cvmx_error_display; 4218215976Sjmallett info.user_info = (long) 4219215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n" 4220215976Sjmallett " radm_unexp_cpl_err\n"; 4221215976Sjmallett fail |= cvmx_error_add(&info); 4222215976Sjmallett 4223215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4224215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4225215976Sjmallett info.status_mask = 1ull<<23 /* racur */; 4226215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4227215976Sjmallett info.enable_mask = 1ull<<23 /* racur */; 4228215976Sjmallett info.flags = 0; 4229215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4230215976Sjmallett info.group_index = 0; 4231215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4232215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4233215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4234215976Sjmallett info.func = __cvmx_error_display; 4235215976Sjmallett info.user_info = (long) 4236215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n" 4237215976Sjmallett " radm_rcvd_cpl_ur\n"; 4238215976Sjmallett fail |= cvmx_error_add(&info); 4239215976Sjmallett 4240215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4241215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4242215976Sjmallett info.status_mask = 1ull<<24 /* racca */; 4243215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4244215976Sjmallett info.enable_mask = 1ull<<24 /* racca */; 4245215976Sjmallett info.flags = 0; 4246215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4247215976Sjmallett info.group_index = 0; 4248215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4249215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4250215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4251215976Sjmallett info.func = __cvmx_error_display; 4252215976Sjmallett info.user_info = (long) 4253215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n" 4254215976Sjmallett " radm_rcvd_cpl_ca\n"; 4255215976Sjmallett fail |= cvmx_error_add(&info); 4256215976Sjmallett 4257215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4258215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4259215976Sjmallett info.status_mask = 1ull<<25 /* caar */; 4260215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4261215976Sjmallett info.enable_mask = 1ull<<25 /* caar */; 4262215976Sjmallett info.flags = 0; 4263215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4264215976Sjmallett info.group_index = 0; 4265215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4266215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4267215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4268215976Sjmallett info.func = __cvmx_error_display; 4269215976Sjmallett info.user_info = (long) 4270215976Sjmallett "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n" 4271215976Sjmallett " radm_rcvd_ca_req\n" 4272215976Sjmallett " This bit will never be set because Octeon does\n" 4273215976Sjmallett " not generate Completer Aborts.\n"; 4274215976Sjmallett fail |= cvmx_error_add(&info); 4275215976Sjmallett 4276215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4277215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4278215976Sjmallett info.status_mask = 1ull<<26 /* rarwdns */; 4279215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4280215976Sjmallett info.enable_mask = 1ull<<26 /* rarwdns */; 4281215976Sjmallett info.flags = 0; 4282215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4283215976Sjmallett info.group_index = 0; 4284215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4285215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4286215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4287215976Sjmallett info.func = __cvmx_error_display; 4288215976Sjmallett info.user_info = (long) 4289215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n" 4290215976Sjmallett " radm_rcvd_ur_req\n"; 4291215976Sjmallett fail |= cvmx_error_add(&info); 4292215976Sjmallett 4293215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4294215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4295215976Sjmallett info.status_mask = 1ull<<27 /* ramtlp */; 4296215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4297215976Sjmallett info.enable_mask = 1ull<<27 /* ramtlp */; 4298215976Sjmallett info.flags = 0; 4299215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4300215976Sjmallett info.group_index = 0; 4301215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4302215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4303215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4304215976Sjmallett info.func = __cvmx_error_display; 4305215976Sjmallett info.user_info = (long) 4306215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n" 4307215976Sjmallett " radm_mlf_tlp_err\n"; 4308215976Sjmallett fail |= cvmx_error_add(&info); 4309215976Sjmallett 4310215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4311215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4312215976Sjmallett info.status_mask = 1ull<<28 /* racpp */; 4313215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4314215976Sjmallett info.enable_mask = 1ull<<28 /* racpp */; 4315215976Sjmallett info.flags = 0; 4316215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4317215976Sjmallett info.group_index = 0; 4318215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4319215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4320215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4321215976Sjmallett info.func = __cvmx_error_display; 4322215976Sjmallett info.user_info = (long) 4323215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n" 4324215976Sjmallett " radm_rcvd_cpl_poisoned\n"; 4325215976Sjmallett fail |= cvmx_error_add(&info); 4326215976Sjmallett 4327215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4328215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4329215976Sjmallett info.status_mask = 1ull<<29 /* rawwpp */; 4330215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4331215976Sjmallett info.enable_mask = 1ull<<29 /* rawwpp */; 4332215976Sjmallett info.flags = 0; 4333215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4334215976Sjmallett info.group_index = 0; 4335215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4336215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4337215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4338215976Sjmallett info.func = __cvmx_error_display; 4339215976Sjmallett info.user_info = (long) 4340215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n" 4341215976Sjmallett " radm_rcvd_wreq_poisoned\n"; 4342215976Sjmallett fail |= cvmx_error_add(&info); 4343215976Sjmallett 4344215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4345215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4346215976Sjmallett info.status_mask = 1ull<<30 /* ecrc_e */; 4347215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4348215976Sjmallett info.enable_mask = 1ull<<30 /* ecrc_e */; 4349215976Sjmallett info.flags = 0; 4350215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4351215976Sjmallett info.group_index = 0; 4352215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4353215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4354215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4355215976Sjmallett info.func = __cvmx_error_display; 4356215976Sjmallett info.user_info = (long) 4357215976Sjmallett "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n" 4358215976Sjmallett " radm_ecrc_err\n"; 4359215976Sjmallett fail |= cvmx_error_add(&info); 4360215976Sjmallett 4361215976Sjmallett /* CVMX_PESCX_DBG_INFO(1) */ 4362215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4363215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4364215976Sjmallett info.status_mask = 1ull<<0 /* spoison */; 4365215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4366215976Sjmallett info.enable_mask = 1ull<<0 /* spoison */; 4367215976Sjmallett info.flags = 0; 4368215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4369215976Sjmallett info.group_index = 1; 4370215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4371215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4372215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4373215976Sjmallett info.func = __cvmx_error_display; 4374215976Sjmallett info.user_info = (long) 4375215976Sjmallett "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n" 4376215976Sjmallett " peai__client0_tlp_ep & peai__client0_tlp_hv\n"; 4377215976Sjmallett fail |= cvmx_error_add(&info); 4378215976Sjmallett 4379215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4380215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4381215976Sjmallett info.status_mask = 1ull<<2 /* rtlplle */; 4382215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4383215976Sjmallett info.enable_mask = 1ull<<2 /* rtlplle */; 4384215976Sjmallett info.flags = 0; 4385215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4386215976Sjmallett info.group_index = 1; 4387215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4388215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4389215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4390215976Sjmallett info.func = __cvmx_error_display; 4391215976Sjmallett info.user_info = (long) 4392215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n" 4393215976Sjmallett " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n"; 4394215976Sjmallett fail |= cvmx_error_add(&info); 4395215976Sjmallett 4396215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4397215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4398215976Sjmallett info.status_mask = 1ull<<3 /* recrce */; 4399215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4400215976Sjmallett info.enable_mask = 1ull<<3 /* recrce */; 4401215976Sjmallett info.flags = 0; 4402215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4403215976Sjmallett info.group_index = 1; 4404215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4405215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4406215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4407215976Sjmallett info.func = __cvmx_error_display; 4408215976Sjmallett info.user_info = (long) 4409215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n" 4410215976Sjmallett " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n"; 4411215976Sjmallett fail |= cvmx_error_add(&info); 4412215976Sjmallett 4413215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4414215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4415215976Sjmallett info.status_mask = 1ull<<4 /* rpoison */; 4416215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4417215976Sjmallett info.enable_mask = 1ull<<4 /* rpoison */; 4418215976Sjmallett info.flags = 0; 4419215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4420215976Sjmallett info.group_index = 1; 4421215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4422215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4423215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4424215976Sjmallett info.func = __cvmx_error_display; 4425215976Sjmallett info.user_info = (long) 4426215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n" 4427215976Sjmallett " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n"; 4428215976Sjmallett fail |= cvmx_error_add(&info); 4429215976Sjmallett 4430215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4431215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4432215976Sjmallett info.status_mask = 1ull<<5 /* rcemrc */; 4433215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4434215976Sjmallett info.enable_mask = 1ull<<5 /* rcemrc */; 4435215976Sjmallett info.flags = 0; 4436215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4437215976Sjmallett info.group_index = 1; 4438215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4439215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4440215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4441215976Sjmallett info.func = __cvmx_error_display; 4442215976Sjmallett info.user_info = (long) 4443215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n" 4444215976Sjmallett " pedc_radm_correctable_err\n"; 4445215976Sjmallett fail |= cvmx_error_add(&info); 4446215976Sjmallett 4447215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4448215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4449215976Sjmallett info.status_mask = 1ull<<6 /* rnfemrc */; 4450215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4451215976Sjmallett info.enable_mask = 1ull<<6 /* rnfemrc */; 4452215976Sjmallett info.flags = 0; 4453215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4454215976Sjmallett info.group_index = 1; 4455215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4456215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4457215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4458215976Sjmallett info.func = __cvmx_error_display; 4459215976Sjmallett info.user_info = (long) 4460215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n" 4461215976Sjmallett " pedc_radm_nonfatal_err\n"; 4462215976Sjmallett fail |= cvmx_error_add(&info); 4463215976Sjmallett 4464215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4465215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4466215976Sjmallett info.status_mask = 1ull<<7 /* rfemrc */; 4467215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4468215976Sjmallett info.enable_mask = 1ull<<7 /* rfemrc */; 4469215976Sjmallett info.flags = 0; 4470215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4471215976Sjmallett info.group_index = 1; 4472215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4473215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4474215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4475215976Sjmallett info.func = __cvmx_error_display; 4476215976Sjmallett info.user_info = (long) 4477215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n" 4478215976Sjmallett " pedc_radm_fatal_err\n" 4479215976Sjmallett " Bit set when a message with ERR_FATAL is set.\n"; 4480215976Sjmallett fail |= cvmx_error_add(&info); 4481215976Sjmallett 4482215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4483215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4484215976Sjmallett info.status_mask = 1ull<<8 /* rpmerc */; 4485215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4486215976Sjmallett info.enable_mask = 1ull<<8 /* rpmerc */; 4487215976Sjmallett info.flags = 0; 4488215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4489215976Sjmallett info.group_index = 1; 4490215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4491215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4492215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4493215976Sjmallett info.func = __cvmx_error_display; 4494215976Sjmallett info.user_info = (long) 4495215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n" 4496215976Sjmallett " pedc_radm_pm_pme\n"; 4497215976Sjmallett fail |= cvmx_error_add(&info); 4498215976Sjmallett 4499215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4500215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4501215976Sjmallett info.status_mask = 1ull<<9 /* rptamrc */; 4502215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4503215976Sjmallett info.enable_mask = 1ull<<9 /* rptamrc */; 4504215976Sjmallett info.flags = 0; 4505215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4506215976Sjmallett info.group_index = 1; 4507215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4508215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4509215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4510215976Sjmallett info.func = __cvmx_error_display; 4511215976Sjmallett info.user_info = (long) 4512215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n" 4513215976Sjmallett " (RC Mode only)\n" 4514215976Sjmallett " pedc_radm_pm_to_ack\n"; 4515215976Sjmallett fail |= cvmx_error_add(&info); 4516215976Sjmallett 4517215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4518215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4519215976Sjmallett info.status_mask = 1ull<<10 /* rumep */; 4520215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4521215976Sjmallett info.enable_mask = 1ull<<10 /* rumep */; 4522215976Sjmallett info.flags = 0; 4523215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4524215976Sjmallett info.group_index = 1; 4525215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4526215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4527215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4528215976Sjmallett info.func = __cvmx_error_display; 4529215976Sjmallett info.user_info = (long) 4530215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n" 4531215976Sjmallett " pedc_radm_msg_unlock\n"; 4532215976Sjmallett fail |= cvmx_error_add(&info); 4533215976Sjmallett 4534215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4535215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4536215976Sjmallett info.status_mask = 1ull<<11 /* rvdm */; 4537215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4538215976Sjmallett info.enable_mask = 1ull<<11 /* rvdm */; 4539215976Sjmallett info.flags = 0; 4540215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4541215976Sjmallett info.group_index = 1; 4542215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4543215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4544215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4545215976Sjmallett info.func = __cvmx_error_display; 4546215976Sjmallett info.user_info = (long) 4547215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n" 4548215976Sjmallett " pedc_radm_vendor_msg\n"; 4549215976Sjmallett fail |= cvmx_error_add(&info); 4550215976Sjmallett 4551215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4552215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4553215976Sjmallett info.status_mask = 1ull<<12 /* acto */; 4554215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4555215976Sjmallett info.enable_mask = 1ull<<12 /* acto */; 4556215976Sjmallett info.flags = 0; 4557215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4558215976Sjmallett info.group_index = 1; 4559215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4560215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4561215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4562215976Sjmallett info.func = __cvmx_error_display; 4563215976Sjmallett info.user_info = (long) 4564215976Sjmallett "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n" 4565215976Sjmallett " pedc_radm_cpl_timeout\n"; 4566215976Sjmallett fail |= cvmx_error_add(&info); 4567215976Sjmallett 4568215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4569215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4570215976Sjmallett info.status_mask = 1ull<<13 /* rte */; 4571215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4572215976Sjmallett info.enable_mask = 1ull<<13 /* rte */; 4573215976Sjmallett info.flags = 0; 4574215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4575215976Sjmallett info.group_index = 1; 4576215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4577215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4578215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4579215976Sjmallett info.func = __cvmx_error_display; 4580215976Sjmallett info.user_info = (long) 4581215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n" 4582215976Sjmallett " xdlh_replay_timeout_err\n" 4583215976Sjmallett " This bit is set when the REPLAY_TIMER expires in\n" 4584215976Sjmallett " the PCIE core. The probability of this bit being\n" 4585215976Sjmallett " set will increase with the traffic load.\n"; 4586215976Sjmallett fail |= cvmx_error_add(&info); 4587215976Sjmallett 4588215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4589215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4590215976Sjmallett info.status_mask = 1ull<<14 /* mre */; 4591215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4592215976Sjmallett info.enable_mask = 1ull<<14 /* mre */; 4593215976Sjmallett info.flags = 0; 4594215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4595215976Sjmallett info.group_index = 1; 4596215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4597215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4598215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4599215976Sjmallett info.func = __cvmx_error_display; 4600215976Sjmallett info.user_info = (long) 4601215976Sjmallett "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n" 4602215976Sjmallett " xdlh_replay_num_rlover_err\n"; 4603215976Sjmallett fail |= cvmx_error_add(&info); 4604215976Sjmallett 4605215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4606215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4607215976Sjmallett info.status_mask = 1ull<<15 /* rdwdle */; 4608215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4609215976Sjmallett info.enable_mask = 1ull<<15 /* rdwdle */; 4610215976Sjmallett info.flags = 0; 4611215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4612215976Sjmallett info.group_index = 1; 4613215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4614215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4615215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4616215976Sjmallett info.func = __cvmx_error_display; 4617215976Sjmallett info.user_info = (long) 4618215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n" 4619215976Sjmallett " rdlh_bad_dllp_err\n"; 4620215976Sjmallett fail |= cvmx_error_add(&info); 4621215976Sjmallett 4622215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4623215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4624215976Sjmallett info.status_mask = 1ull<<16 /* rtwdle */; 4625215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4626215976Sjmallett info.enable_mask = 1ull<<16 /* rtwdle */; 4627215976Sjmallett info.flags = 0; 4628215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4629215976Sjmallett info.group_index = 1; 4630215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4631215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4632215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4633215976Sjmallett info.func = __cvmx_error_display; 4634215976Sjmallett info.user_info = (long) 4635215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n" 4636215976Sjmallett " rdlh_bad_tlp_err\n"; 4637215976Sjmallett fail |= cvmx_error_add(&info); 4638215976Sjmallett 4639215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4640215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4641215976Sjmallett info.status_mask = 1ull<<17 /* dpeoosd */; 4642215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4643215976Sjmallett info.enable_mask = 1ull<<17 /* dpeoosd */; 4644215976Sjmallett info.flags = 0; 4645215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4646215976Sjmallett info.group_index = 1; 4647215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4648215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4649215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4650215976Sjmallett info.func = __cvmx_error_display; 4651215976Sjmallett info.user_info = (long) 4652215976Sjmallett "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n" 4653215976Sjmallett " rdlh_prot_err\n"; 4654215976Sjmallett fail |= cvmx_error_add(&info); 4655215976Sjmallett 4656215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4657215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4658215976Sjmallett info.status_mask = 1ull<<18 /* fcpvwt */; 4659215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4660215976Sjmallett info.enable_mask = 1ull<<18 /* fcpvwt */; 4661215976Sjmallett info.flags = 0; 4662215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4663215976Sjmallett info.group_index = 1; 4664215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4665215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4666215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4667215976Sjmallett info.func = __cvmx_error_display; 4668215976Sjmallett info.user_info = (long) 4669215976Sjmallett "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n" 4670215976Sjmallett " rtlh_fc_prot_err\n"; 4671215976Sjmallett fail |= cvmx_error_add(&info); 4672215976Sjmallett 4673215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4674215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4675215976Sjmallett info.status_mask = 1ull<<19 /* rpe */; 4676215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4677215976Sjmallett info.enable_mask = 1ull<<19 /* rpe */; 4678215976Sjmallett info.flags = 0; 4679215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4680215976Sjmallett info.group_index = 1; 4681215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4682215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4683215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4684215976Sjmallett info.func = __cvmx_error_display; 4685215976Sjmallett info.user_info = (long) 4686215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n" 4687215976Sjmallett " (RxStatus = 3b100) or disparity error\n" 4688215976Sjmallett " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n" 4689215976Sjmallett " be asserted.\n" 4690215976Sjmallett " rmlh_rcvd_err\n"; 4691215976Sjmallett fail |= cvmx_error_add(&info); 4692215976Sjmallett 4693215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4694215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4695215976Sjmallett info.status_mask = 1ull<<20 /* fcuv */; 4696215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4697215976Sjmallett info.enable_mask = 1ull<<20 /* fcuv */; 4698215976Sjmallett info.flags = 0; 4699215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4700215976Sjmallett info.group_index = 1; 4701215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4702215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4703215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4704215976Sjmallett info.func = __cvmx_error_display; 4705215976Sjmallett info.user_info = (long) 4706215976Sjmallett "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n" 4707215976Sjmallett " int_xadm_fc_prot_err\n"; 4708215976Sjmallett fail |= cvmx_error_add(&info); 4709215976Sjmallett 4710215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4711215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4712215976Sjmallett info.status_mask = 1ull<<21 /* rqo */; 4713215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4714215976Sjmallett info.enable_mask = 1ull<<21 /* rqo */; 4715215976Sjmallett info.flags = 0; 4716215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4717215976Sjmallett info.group_index = 1; 4718215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4719215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4720215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4721215976Sjmallett info.func = __cvmx_error_display; 4722215976Sjmallett info.user_info = (long) 4723215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n" 4724215976Sjmallett " flow control advertisements are ignored\n" 4725215976Sjmallett " radm_qoverflow\n"; 4726215976Sjmallett fail |= cvmx_error_add(&info); 4727215976Sjmallett 4728215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4729215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4730215976Sjmallett info.status_mask = 1ull<<22 /* rauc */; 4731215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4732215976Sjmallett info.enable_mask = 1ull<<22 /* rauc */; 4733215976Sjmallett info.flags = 0; 4734215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4735215976Sjmallett info.group_index = 1; 4736215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4737215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4738215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4739215976Sjmallett info.func = __cvmx_error_display; 4740215976Sjmallett info.user_info = (long) 4741215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n" 4742215976Sjmallett " radm_unexp_cpl_err\n"; 4743215976Sjmallett fail |= cvmx_error_add(&info); 4744215976Sjmallett 4745215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4746215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4747215976Sjmallett info.status_mask = 1ull<<23 /* racur */; 4748215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4749215976Sjmallett info.enable_mask = 1ull<<23 /* racur */; 4750215976Sjmallett info.flags = 0; 4751215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4752215976Sjmallett info.group_index = 1; 4753215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4754215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4755215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4756215976Sjmallett info.func = __cvmx_error_display; 4757215976Sjmallett info.user_info = (long) 4758215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n" 4759215976Sjmallett " radm_rcvd_cpl_ur\n"; 4760215976Sjmallett fail |= cvmx_error_add(&info); 4761215976Sjmallett 4762215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4763215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4764215976Sjmallett info.status_mask = 1ull<<24 /* racca */; 4765215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4766215976Sjmallett info.enable_mask = 1ull<<24 /* racca */; 4767215976Sjmallett info.flags = 0; 4768215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4769215976Sjmallett info.group_index = 1; 4770215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4771215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4772215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4773215976Sjmallett info.func = __cvmx_error_display; 4774215976Sjmallett info.user_info = (long) 4775215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n" 4776215976Sjmallett " radm_rcvd_cpl_ca\n"; 4777215976Sjmallett fail |= cvmx_error_add(&info); 4778215976Sjmallett 4779215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4780215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4781215976Sjmallett info.status_mask = 1ull<<25 /* caar */; 4782215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4783215976Sjmallett info.enable_mask = 1ull<<25 /* caar */; 4784215976Sjmallett info.flags = 0; 4785215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4786215976Sjmallett info.group_index = 1; 4787215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4788215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4789215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4790215976Sjmallett info.func = __cvmx_error_display; 4791215976Sjmallett info.user_info = (long) 4792215976Sjmallett "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n" 4793215976Sjmallett " radm_rcvd_ca_req\n" 4794215976Sjmallett " This bit will never be set because Octeon does\n" 4795215976Sjmallett " not generate Completer Aborts.\n"; 4796215976Sjmallett fail |= cvmx_error_add(&info); 4797215976Sjmallett 4798215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4799215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4800215976Sjmallett info.status_mask = 1ull<<26 /* rarwdns */; 4801215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4802215976Sjmallett info.enable_mask = 1ull<<26 /* rarwdns */; 4803215976Sjmallett info.flags = 0; 4804215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4805215976Sjmallett info.group_index = 1; 4806215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4807215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4808215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4809215976Sjmallett info.func = __cvmx_error_display; 4810215976Sjmallett info.user_info = (long) 4811215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n" 4812215976Sjmallett " radm_rcvd_ur_req\n"; 4813215976Sjmallett fail |= cvmx_error_add(&info); 4814215976Sjmallett 4815215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4816215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4817215976Sjmallett info.status_mask = 1ull<<27 /* ramtlp */; 4818215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4819215976Sjmallett info.enable_mask = 1ull<<27 /* ramtlp */; 4820215976Sjmallett info.flags = 0; 4821215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4822215976Sjmallett info.group_index = 1; 4823215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4824215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4825215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4826215976Sjmallett info.func = __cvmx_error_display; 4827215976Sjmallett info.user_info = (long) 4828215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n" 4829215976Sjmallett " radm_mlf_tlp_err\n"; 4830215976Sjmallett fail |= cvmx_error_add(&info); 4831215976Sjmallett 4832215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4833215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4834215976Sjmallett info.status_mask = 1ull<<28 /* racpp */; 4835215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4836215976Sjmallett info.enable_mask = 1ull<<28 /* racpp */; 4837215976Sjmallett info.flags = 0; 4838215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4839215976Sjmallett info.group_index = 1; 4840215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4841215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4842215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4843215976Sjmallett info.func = __cvmx_error_display; 4844215976Sjmallett info.user_info = (long) 4845215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n" 4846215976Sjmallett " radm_rcvd_cpl_poisoned\n"; 4847215976Sjmallett fail |= cvmx_error_add(&info); 4848215976Sjmallett 4849215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4850215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4851215976Sjmallett info.status_mask = 1ull<<29 /* rawwpp */; 4852215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4853215976Sjmallett info.enable_mask = 1ull<<29 /* rawwpp */; 4854215976Sjmallett info.flags = 0; 4855215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4856215976Sjmallett info.group_index = 1; 4857215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4858215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4859215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4860215976Sjmallett info.func = __cvmx_error_display; 4861215976Sjmallett info.user_info = (long) 4862215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n" 4863215976Sjmallett " radm_rcvd_wreq_poisoned\n"; 4864215976Sjmallett fail |= cvmx_error_add(&info); 4865215976Sjmallett 4866215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4867215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4868215976Sjmallett info.status_mask = 1ull<<30 /* ecrc_e */; 4869215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4870215976Sjmallett info.enable_mask = 1ull<<30 /* ecrc_e */; 4871215976Sjmallett info.flags = 0; 4872215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4873215976Sjmallett info.group_index = 1; 4874215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4875215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4876215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4877215976Sjmallett info.func = __cvmx_error_display; 4878215976Sjmallett info.user_info = (long) 4879215976Sjmallett "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n" 4880215976Sjmallett " radm_ecrc_err\n"; 4881215976Sjmallett fail |= cvmx_error_add(&info); 4882215976Sjmallett 4883215976Sjmallett /* CVMX_RAD_REG_ERROR */ 4884215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4885215976Sjmallett info.status_addr = CVMX_RAD_REG_ERROR; 4886215976Sjmallett info.status_mask = 1ull<<0 /* doorbell */; 4887215976Sjmallett info.enable_addr = CVMX_RAD_REG_INT_MASK; 4888215976Sjmallett info.enable_mask = 1ull<<0 /* doorbell */; 4889215976Sjmallett info.flags = 0; 4890215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4891215976Sjmallett info.group_index = 0; 4892215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4893215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4894215976Sjmallett info.parent.status_mask = 1ull<<14 /* rad */; 4895215976Sjmallett info.func = __cvmx_error_display; 4896215976Sjmallett info.user_info = (long) 4897215976Sjmallett "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 4898215976Sjmallett fail |= cvmx_error_add(&info); 4899215976Sjmallett 4900215976Sjmallett /* CVMX_LMCX_MEM_CFG0(1) */ 4901215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4902215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(1); 4903215976Sjmallett info.status_mask = 0xfull<<21 /* sec_err */; 4904215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(1); 4905215976Sjmallett info.enable_mask = 1ull<<19 /* intr_sec_ena */; 4906215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 4907215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 4908215976Sjmallett info.group_index = 1; 4909215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4910215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4911215976Sjmallett info.parent.status_mask = 1ull<<29 /* lmc1 */; 4912215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err; 4913215976Sjmallett info.user_info = (long) 4914215976Sjmallett "ERROR LMCX_MEM_CFG0(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n" 4915215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 4916215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 4917215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 4918215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 4919215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 4920215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 4921215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 4922215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 4923215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 4924215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 4925215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 4926215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4927215976Sjmallett fail |= cvmx_error_add(&info); 4928215976Sjmallett 4929215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4930215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(1); 4931215976Sjmallett info.status_mask = 0xfull<<25 /* ded_err */; 4932215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(1); 4933215976Sjmallett info.enable_mask = 1ull<<20 /* intr_ded_ena */; 4934215976Sjmallett info.flags = 0; 4935215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 4936215976Sjmallett info.group_index = 1; 4937215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4938215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4939215976Sjmallett info.parent.status_mask = 1ull<<29 /* lmc1 */; 4940215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err; 4941215976Sjmallett info.user_info = (long) 4942215976Sjmallett "ERROR LMCX_MEM_CFG0(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n" 4943215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 4944215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 4945215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 4946215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 4947215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 4948215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 4949215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 4950215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 4951215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 4952215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 4953215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 4954215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4955215976Sjmallett fail |= cvmx_error_add(&info); 4956215976Sjmallett 4957215976Sjmallett /* CVMX_PCSX_INTX_REG(0,1) */ 4958215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4959215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4960215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 4961215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4962215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 4963215976Sjmallett info.flags = 0; 4964215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4965215976Sjmallett info.group_index = 16; 4966215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4967215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4968215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4969215976Sjmallett info.func = __cvmx_error_display; 4970215976Sjmallett info.user_info = (long) 4971215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n"; 4972215976Sjmallett fail |= cvmx_error_add(&info); 4973215976Sjmallett 4974215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4975215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4976215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 4977215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4978215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 4979215976Sjmallett info.flags = 0; 4980215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4981215976Sjmallett info.group_index = 16; 4982215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4983215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4984215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 4985215976Sjmallett info.func = __cvmx_error_display; 4986215976Sjmallett info.user_info = (long) 4987215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 4988215976Sjmallett " condition\n"; 4989215976Sjmallett fail |= cvmx_error_add(&info); 4990215976Sjmallett 4991215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4992215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 4993215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 4994215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 4995215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 4996215976Sjmallett info.flags = 0; 4997215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4998215976Sjmallett info.group_index = 16; 4999215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5000215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5001215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5002215976Sjmallett info.func = __cvmx_error_display; 5003215976Sjmallett info.user_info = (long) 5004215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5005215976Sjmallett " condition\n"; 5006215976Sjmallett fail |= cvmx_error_add(&info); 5007215976Sjmallett 5008215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5009215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 5010215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5011215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 5012215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5013215976Sjmallett info.flags = 0; 5014215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5015215976Sjmallett info.group_index = 16; 5016215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5017215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5018215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5019215976Sjmallett info.func = __cvmx_error_display; 5020215976Sjmallett info.user_info = (long) 5021215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5022215976Sjmallett " state. Should never be set during normal operation\n"; 5023215976Sjmallett fail |= cvmx_error_add(&info); 5024215976Sjmallett 5025215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5026215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 5027215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5028215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 5029215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5030215976Sjmallett info.flags = 0; 5031215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5032215976Sjmallett info.group_index = 16; 5033215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5034215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5035215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5036215976Sjmallett info.func = __cvmx_error_display; 5037215976Sjmallett info.user_info = (long) 5038215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5039215976Sjmallett " state. Should never be set during normal operation\n"; 5040215976Sjmallett fail |= cvmx_error_add(&info); 5041215976Sjmallett 5042215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5043215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 5044215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5045215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 5046215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5047215976Sjmallett info.flags = 0; 5048215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5049215976Sjmallett info.group_index = 16; 5050215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5051215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5052215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5053215976Sjmallett info.func = __cvmx_error_display; 5054215976Sjmallett info.user_info = (long) 5055215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5056215976Sjmallett " failure occurs\n" 5057215976Sjmallett " Cannot fire in loopback1 mode\n"; 5058215976Sjmallett fail |= cvmx_error_add(&info); 5059215976Sjmallett 5060215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5061215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 5062215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5063215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 5064215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5065215976Sjmallett info.flags = 0; 5066215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5067215976Sjmallett info.group_index = 16; 5068215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5069215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5070215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5071215976Sjmallett info.func = __cvmx_error_display; 5072215976Sjmallett info.user_info = (long) 5073215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5074215976Sjmallett " state. Should never be set during normal operation\n"; 5075215976Sjmallett fail |= cvmx_error_add(&info); 5076215976Sjmallett 5077215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5078215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,1); 5079215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5080215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1); 5081215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5082215976Sjmallett info.flags = 0; 5083215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5084215976Sjmallett info.group_index = 16; 5085215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5086215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5087215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5088215976Sjmallett info.func = __cvmx_error_display; 5089215976Sjmallett info.user_info = (long) 5090215976Sjmallett "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5091215976Sjmallett " state. Should never be set during normal operation\n"; 5092215976Sjmallett fail |= cvmx_error_add(&info); 5093215976Sjmallett 5094215976Sjmallett /* CVMX_PCSX_INTX_REG(1,1) */ 5095215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5096215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 5097215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5098215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 5099215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5100215976Sjmallett info.flags = 0; 5101215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5102215976Sjmallett info.group_index = 17; 5103215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5104215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5105215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5106215976Sjmallett info.func = __cvmx_error_display; 5107215976Sjmallett info.user_info = (long) 5108215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n"; 5109215976Sjmallett fail |= cvmx_error_add(&info); 5110215976Sjmallett 5111215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5112215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 5113215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5114215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 5115215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5116215976Sjmallett info.flags = 0; 5117215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5118215976Sjmallett info.group_index = 17; 5119215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5120215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5121215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5122215976Sjmallett info.func = __cvmx_error_display; 5123215976Sjmallett info.user_info = (long) 5124215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5125215976Sjmallett " condition\n"; 5126215976Sjmallett fail |= cvmx_error_add(&info); 5127215976Sjmallett 5128215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5129215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 5130215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5131215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 5132215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5133215976Sjmallett info.flags = 0; 5134215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5135215976Sjmallett info.group_index = 17; 5136215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5137215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5138215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5139215976Sjmallett info.func = __cvmx_error_display; 5140215976Sjmallett info.user_info = (long) 5141215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5142215976Sjmallett " condition\n"; 5143215976Sjmallett fail |= cvmx_error_add(&info); 5144215976Sjmallett 5145215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5146215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 5147215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5148215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 5149215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5150215976Sjmallett info.flags = 0; 5151215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5152215976Sjmallett info.group_index = 17; 5153215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5154215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5155215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5156215976Sjmallett info.func = __cvmx_error_display; 5157215976Sjmallett info.user_info = (long) 5158215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5159215976Sjmallett " state. Should never be set during normal operation\n"; 5160215976Sjmallett fail |= cvmx_error_add(&info); 5161215976Sjmallett 5162215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5163215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 5164215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5165215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 5166215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5167215976Sjmallett info.flags = 0; 5168215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5169215976Sjmallett info.group_index = 17; 5170215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5171215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5172215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5173215976Sjmallett info.func = __cvmx_error_display; 5174215976Sjmallett info.user_info = (long) 5175215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5176215976Sjmallett " state. Should never be set during normal operation\n"; 5177215976Sjmallett fail |= cvmx_error_add(&info); 5178215976Sjmallett 5179215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5180215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 5181215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5182215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 5183215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5184215976Sjmallett info.flags = 0; 5185215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5186215976Sjmallett info.group_index = 17; 5187215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5188215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5189215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5190215976Sjmallett info.func = __cvmx_error_display; 5191215976Sjmallett info.user_info = (long) 5192215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5193215976Sjmallett " failure occurs\n" 5194215976Sjmallett " Cannot fire in loopback1 mode\n"; 5195215976Sjmallett fail |= cvmx_error_add(&info); 5196215976Sjmallett 5197215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5198215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 5199215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5200215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 5201215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5202215976Sjmallett info.flags = 0; 5203215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5204215976Sjmallett info.group_index = 17; 5205215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5206215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5207215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5208215976Sjmallett info.func = __cvmx_error_display; 5209215976Sjmallett info.user_info = (long) 5210215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5211215976Sjmallett " state. Should never be set during normal operation\n"; 5212215976Sjmallett fail |= cvmx_error_add(&info); 5213215976Sjmallett 5214215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5215215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,1); 5216215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5217215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1); 5218215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5219215976Sjmallett info.flags = 0; 5220215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5221215976Sjmallett info.group_index = 17; 5222215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5223215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5224215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5225215976Sjmallett info.func = __cvmx_error_display; 5226215976Sjmallett info.user_info = (long) 5227215976Sjmallett "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5228215976Sjmallett " state. Should never be set during normal operation\n"; 5229215976Sjmallett fail |= cvmx_error_add(&info); 5230215976Sjmallett 5231215976Sjmallett /* CVMX_PCSX_INTX_REG(2,1) */ 5232215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5233215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 5234215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5235215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 5236215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5237215976Sjmallett info.flags = 0; 5238215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5239215976Sjmallett info.group_index = 18; 5240215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5241215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5242215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5243215976Sjmallett info.func = __cvmx_error_display; 5244215976Sjmallett info.user_info = (long) 5245215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n"; 5246215976Sjmallett fail |= cvmx_error_add(&info); 5247215976Sjmallett 5248215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5249215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 5250215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5251215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 5252215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5253215976Sjmallett info.flags = 0; 5254215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5255215976Sjmallett info.group_index = 18; 5256215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5257215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5258215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5259215976Sjmallett info.func = __cvmx_error_display; 5260215976Sjmallett info.user_info = (long) 5261215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5262215976Sjmallett " condition\n"; 5263215976Sjmallett fail |= cvmx_error_add(&info); 5264215976Sjmallett 5265215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5266215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 5267215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5268215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 5269215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5270215976Sjmallett info.flags = 0; 5271215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5272215976Sjmallett info.group_index = 18; 5273215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5274215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5275215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5276215976Sjmallett info.func = __cvmx_error_display; 5277215976Sjmallett info.user_info = (long) 5278215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5279215976Sjmallett " condition\n"; 5280215976Sjmallett fail |= cvmx_error_add(&info); 5281215976Sjmallett 5282215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5283215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 5284215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5285215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 5286215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5287215976Sjmallett info.flags = 0; 5288215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5289215976Sjmallett info.group_index = 18; 5290215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5291215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5292215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5293215976Sjmallett info.func = __cvmx_error_display; 5294215976Sjmallett info.user_info = (long) 5295215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5296215976Sjmallett " state. Should never be set during normal operation\n"; 5297215976Sjmallett fail |= cvmx_error_add(&info); 5298215976Sjmallett 5299215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5300215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 5301215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5302215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 5303215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5304215976Sjmallett info.flags = 0; 5305215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5306215976Sjmallett info.group_index = 18; 5307215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5308215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5309215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5310215976Sjmallett info.func = __cvmx_error_display; 5311215976Sjmallett info.user_info = (long) 5312215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5313215976Sjmallett " state. Should never be set during normal operation\n"; 5314215976Sjmallett fail |= cvmx_error_add(&info); 5315215976Sjmallett 5316215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5317215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 5318215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5319215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 5320215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5321215976Sjmallett info.flags = 0; 5322215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5323215976Sjmallett info.group_index = 18; 5324215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5325215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5326215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5327215976Sjmallett info.func = __cvmx_error_display; 5328215976Sjmallett info.user_info = (long) 5329215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5330215976Sjmallett " failure occurs\n" 5331215976Sjmallett " Cannot fire in loopback1 mode\n"; 5332215976Sjmallett fail |= cvmx_error_add(&info); 5333215976Sjmallett 5334215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5335215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 5336215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5337215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 5338215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5339215976Sjmallett info.flags = 0; 5340215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5341215976Sjmallett info.group_index = 18; 5342215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5343215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5344215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5345215976Sjmallett info.func = __cvmx_error_display; 5346215976Sjmallett info.user_info = (long) 5347215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5348215976Sjmallett " state. Should never be set during normal operation\n"; 5349215976Sjmallett fail |= cvmx_error_add(&info); 5350215976Sjmallett 5351215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5352215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,1); 5353215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5354215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1); 5355215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5356215976Sjmallett info.flags = 0; 5357215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5358215976Sjmallett info.group_index = 18; 5359215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5360215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5361215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5362215976Sjmallett info.func = __cvmx_error_display; 5363215976Sjmallett info.user_info = (long) 5364215976Sjmallett "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5365215976Sjmallett " state. Should never be set during normal operation\n"; 5366215976Sjmallett fail |= cvmx_error_add(&info); 5367215976Sjmallett 5368215976Sjmallett /* CVMX_PCSX_INTX_REG(3,1) */ 5369215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5370215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5371215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5372215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5373215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5374215976Sjmallett info.flags = 0; 5375215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5376215976Sjmallett info.group_index = 19; 5377215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5378215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5379215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5380215976Sjmallett info.func = __cvmx_error_display; 5381215976Sjmallett info.user_info = (long) 5382215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n"; 5383215976Sjmallett fail |= cvmx_error_add(&info); 5384215976Sjmallett 5385215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5386215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5387215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5388215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5389215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5390215976Sjmallett info.flags = 0; 5391215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5392215976Sjmallett info.group_index = 19; 5393215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5394215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5395215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5396215976Sjmallett info.func = __cvmx_error_display; 5397215976Sjmallett info.user_info = (long) 5398215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5399215976Sjmallett " condition\n"; 5400215976Sjmallett fail |= cvmx_error_add(&info); 5401215976Sjmallett 5402215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5403215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5404215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5405215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5406215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5407215976Sjmallett info.flags = 0; 5408215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5409215976Sjmallett info.group_index = 19; 5410215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5411215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5412215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5413215976Sjmallett info.func = __cvmx_error_display; 5414215976Sjmallett info.user_info = (long) 5415215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5416215976Sjmallett " condition\n"; 5417215976Sjmallett fail |= cvmx_error_add(&info); 5418215976Sjmallett 5419215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5420215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5421215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5422215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5423215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5424215976Sjmallett info.flags = 0; 5425215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5426215976Sjmallett info.group_index = 19; 5427215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5428215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5429215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5430215976Sjmallett info.func = __cvmx_error_display; 5431215976Sjmallett info.user_info = (long) 5432215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5433215976Sjmallett " state. Should never be set during normal operation\n"; 5434215976Sjmallett fail |= cvmx_error_add(&info); 5435215976Sjmallett 5436215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5437215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5438215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5439215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5440215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5441215976Sjmallett info.flags = 0; 5442215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5443215976Sjmallett info.group_index = 19; 5444215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5445215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5446215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5447215976Sjmallett info.func = __cvmx_error_display; 5448215976Sjmallett info.user_info = (long) 5449215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5450215976Sjmallett " state. Should never be set during normal operation\n"; 5451215976Sjmallett fail |= cvmx_error_add(&info); 5452215976Sjmallett 5453215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5454215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5455215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5456215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5457215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5458215976Sjmallett info.flags = 0; 5459215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5460215976Sjmallett info.group_index = 19; 5461215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5462215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5463215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5464215976Sjmallett info.func = __cvmx_error_display; 5465215976Sjmallett info.user_info = (long) 5466215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5467215976Sjmallett " failure occurs\n" 5468215976Sjmallett " Cannot fire in loopback1 mode\n"; 5469215976Sjmallett fail |= cvmx_error_add(&info); 5470215976Sjmallett 5471215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5472215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5473215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5474215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5475215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5476215976Sjmallett info.flags = 0; 5477215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5478215976Sjmallett info.group_index = 19; 5479215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5480215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5481215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5482215976Sjmallett info.func = __cvmx_error_display; 5483215976Sjmallett info.user_info = (long) 5484215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5485215976Sjmallett " state. Should never be set during normal operation\n"; 5486215976Sjmallett fail |= cvmx_error_add(&info); 5487215976Sjmallett 5488215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5489215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,1); 5490215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5491215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1); 5492215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5493215976Sjmallett info.flags = 0; 5494215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5495215976Sjmallett info.group_index = 19; 5496215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5497215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5498215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5499215976Sjmallett info.func = __cvmx_error_display; 5500215976Sjmallett info.user_info = (long) 5501215976Sjmallett "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5502215976Sjmallett " state. Should never be set during normal operation\n"; 5503215976Sjmallett fail |= cvmx_error_add(&info); 5504215976Sjmallett 5505215976Sjmallett /* CVMX_PCSXX_INT_REG(1) */ 5506215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5507215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5508215976Sjmallett info.status_mask = 1ull<<0 /* txflt */; 5509215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5510215976Sjmallett info.enable_mask = 1ull<<0 /* txflt_en */; 5511215976Sjmallett info.flags = 0; 5512215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5513215976Sjmallett info.group_index = 16; 5514215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5515215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5516215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5517215976Sjmallett info.func = __cvmx_error_display; 5518215976Sjmallett info.user_info = (long) 5519215976Sjmallett "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n"; 5520215976Sjmallett fail |= cvmx_error_add(&info); 5521215976Sjmallett 5522215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5523215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5524215976Sjmallett info.status_mask = 1ull<<1 /* rxbad */; 5525215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5526215976Sjmallett info.enable_mask = 1ull<<1 /* rxbad_en */; 5527215976Sjmallett info.flags = 0; 5528215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5529215976Sjmallett info.group_index = 16; 5530215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5531215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5532215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5533215976Sjmallett info.func = __cvmx_error_display; 5534215976Sjmallett info.user_info = (long) 5535215976Sjmallett "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n"; 5536215976Sjmallett fail |= cvmx_error_add(&info); 5537215976Sjmallett 5538215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5539215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5540215976Sjmallett info.status_mask = 1ull<<2 /* rxsynbad */; 5541215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5542215976Sjmallett info.enable_mask = 1ull<<2 /* rxsynbad_en */; 5543215976Sjmallett info.flags = 0; 5544215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5545215976Sjmallett info.group_index = 16; 5546215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5547215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5548215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5549215976Sjmallett info.func = __cvmx_error_display; 5550215976Sjmallett info.user_info = (long) 5551215976Sjmallett "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n" 5552215976Sjmallett " in one of the 4 xaui lanes\n"; 5553215976Sjmallett fail |= cvmx_error_add(&info); 5554215976Sjmallett 5555215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5556215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5557215976Sjmallett info.status_mask = 1ull<<4 /* synlos */; 5558215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5559215976Sjmallett info.enable_mask = 1ull<<4 /* synlos_en */; 5560215976Sjmallett info.flags = 0; 5561215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5562215976Sjmallett info.group_index = 16; 5563215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5564215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5565215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5566215976Sjmallett info.func = __cvmx_error_display; 5567215976Sjmallett info.user_info = (long) 5568215976Sjmallett "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n"; 5569215976Sjmallett fail |= cvmx_error_add(&info); 5570215976Sjmallett 5571215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5572215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(1); 5573215976Sjmallett info.status_mask = 1ull<<5 /* algnlos */; 5574215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(1); 5575215976Sjmallett info.enable_mask = 1ull<<5 /* algnlos_en */; 5576215976Sjmallett info.flags = 0; 5577215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5578215976Sjmallett info.group_index = 16; 5579215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5580215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5581215976Sjmallett info.parent.status_mask = 1ull<<23 /* asxpcs1 */; 5582215976Sjmallett info.func = __cvmx_error_display; 5583215976Sjmallett info.user_info = (long) 5584215976Sjmallett "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n"; 5585215976Sjmallett fail |= cvmx_error_add(&info); 5586215976Sjmallett 5587215976Sjmallett /* CVMX_PCSX_INTX_REG(0,0) */ 5588215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5589215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5590215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5591215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5592215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5593215976Sjmallett info.flags = 0; 5594215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5595215976Sjmallett info.group_index = 0; 5596215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5597215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5598215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5599215976Sjmallett info.func = __cvmx_error_display; 5600215976Sjmallett info.user_info = (long) 5601215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 5602215976Sjmallett fail |= cvmx_error_add(&info); 5603215976Sjmallett 5604215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5605215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5606215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5607215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5608215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5609215976Sjmallett info.flags = 0; 5610215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5611215976Sjmallett info.group_index = 0; 5612215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5613215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5614215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5615215976Sjmallett info.func = __cvmx_error_display; 5616215976Sjmallett info.user_info = (long) 5617215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5618215976Sjmallett " condition\n"; 5619215976Sjmallett fail |= cvmx_error_add(&info); 5620215976Sjmallett 5621215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5622215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5623215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5624215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5625215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5626215976Sjmallett info.flags = 0; 5627215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5628215976Sjmallett info.group_index = 0; 5629215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5630215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5631215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5632215976Sjmallett info.func = __cvmx_error_display; 5633215976Sjmallett info.user_info = (long) 5634215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5635215976Sjmallett " condition\n"; 5636215976Sjmallett fail |= cvmx_error_add(&info); 5637215976Sjmallett 5638215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5639215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5640215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5641215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5642215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5643215976Sjmallett info.flags = 0; 5644215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5645215976Sjmallett info.group_index = 0; 5646215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5647215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5648215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5649215976Sjmallett info.func = __cvmx_error_display; 5650215976Sjmallett info.user_info = (long) 5651215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5652215976Sjmallett " state. Should never be set during normal operation\n"; 5653215976Sjmallett fail |= cvmx_error_add(&info); 5654215976Sjmallett 5655215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5656215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5657215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5658215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5659215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5660215976Sjmallett info.flags = 0; 5661215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5662215976Sjmallett info.group_index = 0; 5663215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5664215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5665215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5666215976Sjmallett info.func = __cvmx_error_display; 5667215976Sjmallett info.user_info = (long) 5668215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5669215976Sjmallett " state. Should never be set during normal operation\n"; 5670215976Sjmallett fail |= cvmx_error_add(&info); 5671215976Sjmallett 5672215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5673215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5674215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5675215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5676215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5677215976Sjmallett info.flags = 0; 5678215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5679215976Sjmallett info.group_index = 0; 5680215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5681215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5682215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5683215976Sjmallett info.func = __cvmx_error_display; 5684215976Sjmallett info.user_info = (long) 5685215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5686215976Sjmallett " failure occurs\n" 5687215976Sjmallett " Cannot fire in loopback1 mode\n"; 5688215976Sjmallett fail |= cvmx_error_add(&info); 5689215976Sjmallett 5690215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5691215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5692215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5693215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5694215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5695215976Sjmallett info.flags = 0; 5696215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5697215976Sjmallett info.group_index = 0; 5698215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5699215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5700215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5701215976Sjmallett info.func = __cvmx_error_display; 5702215976Sjmallett info.user_info = (long) 5703215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5704215976Sjmallett " state. Should never be set during normal operation\n"; 5705215976Sjmallett fail |= cvmx_error_add(&info); 5706215976Sjmallett 5707215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5708215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 5709215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5710215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 5711215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5712215976Sjmallett info.flags = 0; 5713215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5714215976Sjmallett info.group_index = 0; 5715215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5716215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5717215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5718215976Sjmallett info.func = __cvmx_error_display; 5719215976Sjmallett info.user_info = (long) 5720215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5721215976Sjmallett " state. Should never be set during normal operation\n"; 5722215976Sjmallett fail |= cvmx_error_add(&info); 5723215976Sjmallett 5724215976Sjmallett /* CVMX_PCSX_INTX_REG(1,0) */ 5725215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5726215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5727215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5728215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5729215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5730215976Sjmallett info.flags = 0; 5731215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5732215976Sjmallett info.group_index = 1; 5733215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5734215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5735215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5736215976Sjmallett info.func = __cvmx_error_display; 5737215976Sjmallett info.user_info = (long) 5738215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 5739215976Sjmallett fail |= cvmx_error_add(&info); 5740215976Sjmallett 5741215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5742215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5743215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5744215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5745215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5746215976Sjmallett info.flags = 0; 5747215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5748215976Sjmallett info.group_index = 1; 5749215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5750215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5751215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5752215976Sjmallett info.func = __cvmx_error_display; 5753215976Sjmallett info.user_info = (long) 5754215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5755215976Sjmallett " condition\n"; 5756215976Sjmallett fail |= cvmx_error_add(&info); 5757215976Sjmallett 5758215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5759215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5760215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5761215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5762215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5763215976Sjmallett info.flags = 0; 5764215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5765215976Sjmallett info.group_index = 1; 5766215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5767215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5768215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5769215976Sjmallett info.func = __cvmx_error_display; 5770215976Sjmallett info.user_info = (long) 5771215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5772215976Sjmallett " condition\n"; 5773215976Sjmallett fail |= cvmx_error_add(&info); 5774215976Sjmallett 5775215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5776215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5777215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5778215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5779215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5780215976Sjmallett info.flags = 0; 5781215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5782215976Sjmallett info.group_index = 1; 5783215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5784215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5785215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5786215976Sjmallett info.func = __cvmx_error_display; 5787215976Sjmallett info.user_info = (long) 5788215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5789215976Sjmallett " state. Should never be set during normal operation\n"; 5790215976Sjmallett fail |= cvmx_error_add(&info); 5791215976Sjmallett 5792215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5793215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5794215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5795215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5796215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5797215976Sjmallett info.flags = 0; 5798215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5799215976Sjmallett info.group_index = 1; 5800215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5801215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5802215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5803215976Sjmallett info.func = __cvmx_error_display; 5804215976Sjmallett info.user_info = (long) 5805215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5806215976Sjmallett " state. Should never be set during normal operation\n"; 5807215976Sjmallett fail |= cvmx_error_add(&info); 5808215976Sjmallett 5809215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5810215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5811215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5812215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5813215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5814215976Sjmallett info.flags = 0; 5815215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5816215976Sjmallett info.group_index = 1; 5817215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5818215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5819215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5820215976Sjmallett info.func = __cvmx_error_display; 5821215976Sjmallett info.user_info = (long) 5822215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5823215976Sjmallett " failure occurs\n" 5824215976Sjmallett " Cannot fire in loopback1 mode\n"; 5825215976Sjmallett fail |= cvmx_error_add(&info); 5826215976Sjmallett 5827215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5828215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5829215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5830215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5831215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5832215976Sjmallett info.flags = 0; 5833215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5834215976Sjmallett info.group_index = 1; 5835215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5836215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5837215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5838215976Sjmallett info.func = __cvmx_error_display; 5839215976Sjmallett info.user_info = (long) 5840215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5841215976Sjmallett " state. Should never be set during normal operation\n"; 5842215976Sjmallett fail |= cvmx_error_add(&info); 5843215976Sjmallett 5844215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5845215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 5846215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5847215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 5848215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5849215976Sjmallett info.flags = 0; 5850215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5851215976Sjmallett info.group_index = 1; 5852215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5853215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5854215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5855215976Sjmallett info.func = __cvmx_error_display; 5856215976Sjmallett info.user_info = (long) 5857215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5858215976Sjmallett " state. Should never be set during normal operation\n"; 5859215976Sjmallett fail |= cvmx_error_add(&info); 5860215976Sjmallett 5861215976Sjmallett /* CVMX_PCSX_INTX_REG(2,0) */ 5862215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5863215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5864215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5865215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5866215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5867215976Sjmallett info.flags = 0; 5868215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5869215976Sjmallett info.group_index = 2; 5870215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5871215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5872215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5873215976Sjmallett info.func = __cvmx_error_display; 5874215976Sjmallett info.user_info = (long) 5875215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 5876215976Sjmallett fail |= cvmx_error_add(&info); 5877215976Sjmallett 5878215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5879215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5880215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5881215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5882215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5883215976Sjmallett info.flags = 0; 5884215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5885215976Sjmallett info.group_index = 2; 5886215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5887215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5888215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5889215976Sjmallett info.func = __cvmx_error_display; 5890215976Sjmallett info.user_info = (long) 5891215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5892215976Sjmallett " condition\n"; 5893215976Sjmallett fail |= cvmx_error_add(&info); 5894215976Sjmallett 5895215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5896215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5897215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5898215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5899215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5900215976Sjmallett info.flags = 0; 5901215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5902215976Sjmallett info.group_index = 2; 5903215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5904215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5905215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5906215976Sjmallett info.func = __cvmx_error_display; 5907215976Sjmallett info.user_info = (long) 5908215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5909215976Sjmallett " condition\n"; 5910215976Sjmallett fail |= cvmx_error_add(&info); 5911215976Sjmallett 5912215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5913215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5914215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5915215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5916215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5917215976Sjmallett info.flags = 0; 5918215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5919215976Sjmallett info.group_index = 2; 5920215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5921215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5922215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5923215976Sjmallett info.func = __cvmx_error_display; 5924215976Sjmallett info.user_info = (long) 5925215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5926215976Sjmallett " state. Should never be set during normal operation\n"; 5927215976Sjmallett fail |= cvmx_error_add(&info); 5928215976Sjmallett 5929215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5930215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5931215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5932215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5933215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5934215976Sjmallett info.flags = 0; 5935215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5936215976Sjmallett info.group_index = 2; 5937215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5938215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5939215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5940215976Sjmallett info.func = __cvmx_error_display; 5941215976Sjmallett info.user_info = (long) 5942215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5943215976Sjmallett " state. Should never be set during normal operation\n"; 5944215976Sjmallett fail |= cvmx_error_add(&info); 5945215976Sjmallett 5946215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5947215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5948215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5949215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5950215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5951215976Sjmallett info.flags = 0; 5952215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5953215976Sjmallett info.group_index = 2; 5954215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5955215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5956215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5957215976Sjmallett info.func = __cvmx_error_display; 5958215976Sjmallett info.user_info = (long) 5959215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5960215976Sjmallett " failure occurs\n" 5961215976Sjmallett " Cannot fire in loopback1 mode\n"; 5962215976Sjmallett fail |= cvmx_error_add(&info); 5963215976Sjmallett 5964215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5965215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5966215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5967215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5968215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5969215976Sjmallett info.flags = 0; 5970215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5971215976Sjmallett info.group_index = 2; 5972215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5973215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5974215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5975215976Sjmallett info.func = __cvmx_error_display; 5976215976Sjmallett info.user_info = (long) 5977215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5978215976Sjmallett " state. Should never be set during normal operation\n"; 5979215976Sjmallett fail |= cvmx_error_add(&info); 5980215976Sjmallett 5981215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5982215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5983215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5984215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5985215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5986215976Sjmallett info.flags = 0; 5987215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5988215976Sjmallett info.group_index = 2; 5989215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5990215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5991215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5992215976Sjmallett info.func = __cvmx_error_display; 5993215976Sjmallett info.user_info = (long) 5994215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5995215976Sjmallett " state. Should never be set during normal operation\n"; 5996215976Sjmallett fail |= cvmx_error_add(&info); 5997215976Sjmallett 5998215976Sjmallett /* CVMX_PCSX_INTX_REG(3,0) */ 5999215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6000215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 6001215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 6002215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 6003215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 6004215976Sjmallett info.flags = 0; 6005215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6006215976Sjmallett info.group_index = 3; 6007215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6008215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6009215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6010215976Sjmallett info.func = __cvmx_error_display; 6011215976Sjmallett info.user_info = (long) 6012215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 6013215976Sjmallett fail |= cvmx_error_add(&info); 6014215976Sjmallett 6015215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6016215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 6017215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 6018215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 6019215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 6020215976Sjmallett info.flags = 0; 6021215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6022215976Sjmallett info.group_index = 3; 6023215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6024215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6025215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6026215976Sjmallett info.func = __cvmx_error_display; 6027215976Sjmallett info.user_info = (long) 6028215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 6029215976Sjmallett " condition\n"; 6030215976Sjmallett fail |= cvmx_error_add(&info); 6031215976Sjmallett 6032215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6033215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 6034215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 6035215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 6036215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 6037215976Sjmallett info.flags = 0; 6038215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6039215976Sjmallett info.group_index = 3; 6040215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6041215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6042215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6043215976Sjmallett info.func = __cvmx_error_display; 6044215976Sjmallett info.user_info = (long) 6045215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 6046215976Sjmallett " condition\n"; 6047215976Sjmallett fail |= cvmx_error_add(&info); 6048215976Sjmallett 6049215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6050215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 6051215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 6052215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 6053215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 6054215976Sjmallett info.flags = 0; 6055215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6056215976Sjmallett info.group_index = 3; 6057215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6058215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6059215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6060215976Sjmallett info.func = __cvmx_error_display; 6061215976Sjmallett info.user_info = (long) 6062215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 6063215976Sjmallett " state. Should never be set during normal operation\n"; 6064215976Sjmallett fail |= cvmx_error_add(&info); 6065215976Sjmallett 6066215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6067215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 6068215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 6069215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 6070215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 6071215976Sjmallett info.flags = 0; 6072215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6073215976Sjmallett info.group_index = 3; 6074215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6075215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6076215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6077215976Sjmallett info.func = __cvmx_error_display; 6078215976Sjmallett info.user_info = (long) 6079215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 6080215976Sjmallett " state. Should never be set during normal operation\n"; 6081215976Sjmallett fail |= cvmx_error_add(&info); 6082215976Sjmallett 6083215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6084215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 6085215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 6086215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 6087215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 6088215976Sjmallett info.flags = 0; 6089215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6090215976Sjmallett info.group_index = 3; 6091215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6092215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6093215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6094215976Sjmallett info.func = __cvmx_error_display; 6095215976Sjmallett info.user_info = (long) 6096215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 6097215976Sjmallett " failure occurs\n" 6098215976Sjmallett " Cannot fire in loopback1 mode\n"; 6099215976Sjmallett fail |= cvmx_error_add(&info); 6100215976Sjmallett 6101215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6102215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 6103215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 6104215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 6105215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 6106215976Sjmallett info.flags = 0; 6107215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6108215976Sjmallett info.group_index = 3; 6109215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6110215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6111215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6112215976Sjmallett info.func = __cvmx_error_display; 6113215976Sjmallett info.user_info = (long) 6114215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 6115215976Sjmallett " state. Should never be set during normal operation\n"; 6116215976Sjmallett fail |= cvmx_error_add(&info); 6117215976Sjmallett 6118215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6119215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 6120215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 6121215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 6122215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 6123215976Sjmallett info.flags = 0; 6124215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6125215976Sjmallett info.group_index = 3; 6126215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6127215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6128215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6129215976Sjmallett info.func = __cvmx_error_display; 6130215976Sjmallett info.user_info = (long) 6131215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 6132215976Sjmallett " state. Should never be set during normal operation\n"; 6133215976Sjmallett fail |= cvmx_error_add(&info); 6134215976Sjmallett 6135215976Sjmallett /* CVMX_PCSXX_INT_REG(0) */ 6136215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6137215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 6138215976Sjmallett info.status_mask = 1ull<<0 /* txflt */; 6139215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 6140215976Sjmallett info.enable_mask = 1ull<<0 /* txflt_en */; 6141215976Sjmallett info.flags = 0; 6142215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6143215976Sjmallett info.group_index = 0; 6144215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6145215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6146215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6147215976Sjmallett info.func = __cvmx_error_display; 6148215976Sjmallett info.user_info = (long) 6149215976Sjmallett "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n"; 6150215976Sjmallett fail |= cvmx_error_add(&info); 6151215976Sjmallett 6152215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6153215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 6154215976Sjmallett info.status_mask = 1ull<<1 /* rxbad */; 6155215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 6156215976Sjmallett info.enable_mask = 1ull<<1 /* rxbad_en */; 6157215976Sjmallett info.flags = 0; 6158215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6159215976Sjmallett info.group_index = 0; 6160215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6161215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6162215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6163215976Sjmallett info.func = __cvmx_error_display; 6164215976Sjmallett info.user_info = (long) 6165215976Sjmallett "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n"; 6166215976Sjmallett fail |= cvmx_error_add(&info); 6167215976Sjmallett 6168215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6169215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 6170215976Sjmallett info.status_mask = 1ull<<2 /* rxsynbad */; 6171215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 6172215976Sjmallett info.enable_mask = 1ull<<2 /* rxsynbad_en */; 6173215976Sjmallett info.flags = 0; 6174215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6175215976Sjmallett info.group_index = 0; 6176215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6177215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6178215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6179215976Sjmallett info.func = __cvmx_error_display; 6180215976Sjmallett info.user_info = (long) 6181215976Sjmallett "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n" 6182215976Sjmallett " in one of the 4 xaui lanes\n"; 6183215976Sjmallett fail |= cvmx_error_add(&info); 6184215976Sjmallett 6185215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6186215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 6187215976Sjmallett info.status_mask = 1ull<<4 /* synlos */; 6188215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 6189215976Sjmallett info.enable_mask = 1ull<<4 /* synlos_en */; 6190215976Sjmallett info.flags = 0; 6191215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6192215976Sjmallett info.group_index = 0; 6193215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6194215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6195215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6196215976Sjmallett info.func = __cvmx_error_display; 6197215976Sjmallett info.user_info = (long) 6198215976Sjmallett "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n"; 6199215976Sjmallett fail |= cvmx_error_add(&info); 6200215976Sjmallett 6201215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6202215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 6203215976Sjmallett info.status_mask = 1ull<<5 /* algnlos */; 6204215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 6205215976Sjmallett info.enable_mask = 1ull<<5 /* algnlos_en */; 6206215976Sjmallett info.flags = 0; 6207215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 6208215976Sjmallett info.group_index = 0; 6209215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6210215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6211215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 6212215976Sjmallett info.func = __cvmx_error_display; 6213215976Sjmallett info.user_info = (long) 6214215976Sjmallett "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n"; 6215215976Sjmallett fail |= cvmx_error_add(&info); 6216215976Sjmallett 6217215976Sjmallett /* CVMX_KEY_INT_SUM */ 6218215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6219215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 6220215976Sjmallett info.status_mask = 1ull<<0 /* ked0_sbe */; 6221215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 6222215976Sjmallett info.enable_mask = 1ull<<0 /* ked0_sbe */; 6223215976Sjmallett info.flags = 0; 6224215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6225215976Sjmallett info.group_index = 0; 6226215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6227215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6228215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 6229215976Sjmallett info.func = __cvmx_error_display; 6230215976Sjmallett info.user_info = (long) 6231215976Sjmallett "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n" 6232215976Sjmallett; 6233215976Sjmallett fail |= cvmx_error_add(&info); 6234215976Sjmallett 6235215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6236215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 6237215976Sjmallett info.status_mask = 1ull<<1 /* ked0_dbe */; 6238215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 6239215976Sjmallett info.enable_mask = 1ull<<1 /* ked0_dbe */; 6240215976Sjmallett info.flags = 0; 6241215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6242215976Sjmallett info.group_index = 0; 6243215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6244215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6245215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 6246215976Sjmallett info.func = __cvmx_error_display; 6247215976Sjmallett info.user_info = (long) 6248215976Sjmallett "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n" 6249215976Sjmallett; 6250215976Sjmallett fail |= cvmx_error_add(&info); 6251215976Sjmallett 6252215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6253215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 6254215976Sjmallett info.status_mask = 1ull<<2 /* ked1_sbe */; 6255215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 6256215976Sjmallett info.enable_mask = 1ull<<2 /* ked1_sbe */; 6257215976Sjmallett info.flags = 0; 6258215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6259215976Sjmallett info.group_index = 0; 6260215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6261215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6262215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 6263215976Sjmallett info.func = __cvmx_error_display; 6264215976Sjmallett info.user_info = (long) 6265215976Sjmallett "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n" 6266215976Sjmallett; 6267215976Sjmallett fail |= cvmx_error_add(&info); 6268215976Sjmallett 6269215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6270215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 6271215976Sjmallett info.status_mask = 1ull<<3 /* ked1_dbe */; 6272215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 6273215976Sjmallett info.enable_mask = 1ull<<3 /* ked1_dbe */; 6274215976Sjmallett info.flags = 0; 6275215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6276215976Sjmallett info.group_index = 0; 6277215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6278215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6279215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 6280215976Sjmallett info.func = __cvmx_error_display; 6281215976Sjmallett info.user_info = (long) 6282215976Sjmallett "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n" 6283215976Sjmallett; 6284215976Sjmallett fail |= cvmx_error_add(&info); 6285215976Sjmallett 6286215976Sjmallett /* CVMX_MIO_BOOT_ERR */ 6287215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6288215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 6289215976Sjmallett info.status_mask = 1ull<<0 /* adr_err */; 6290215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 6291215976Sjmallett info.enable_mask = 1ull<<0 /* adr_int */; 6292215976Sjmallett info.flags = 0; 6293215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6294215976Sjmallett info.group_index = 0; 6295215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6296215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6297215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 6298215976Sjmallett info.func = __cvmx_error_display; 6299215976Sjmallett info.user_info = (long) 6300215976Sjmallett "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n"; 6301215976Sjmallett fail |= cvmx_error_add(&info); 6302215976Sjmallett 6303215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6304215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 6305215976Sjmallett info.status_mask = 1ull<<1 /* wait_err */; 6306215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 6307215976Sjmallett info.enable_mask = 1ull<<1 /* wait_int */; 6308215976Sjmallett info.flags = 0; 6309215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6310215976Sjmallett info.group_index = 0; 6311215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6312215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6313215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 6314215976Sjmallett info.func = __cvmx_error_display; 6315215976Sjmallett info.user_info = (long) 6316215976Sjmallett "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n"; 6317215976Sjmallett fail |= cvmx_error_add(&info); 6318215976Sjmallett 6319215976Sjmallett /* CVMX_PIP_INT_REG */ 6320215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6321215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 6322215976Sjmallett info.status_mask = 1ull<<3 /* prtnxa */; 6323215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 6324215976Sjmallett info.enable_mask = 1ull<<3 /* prtnxa */; 6325215976Sjmallett info.flags = 0; 6326215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6327215976Sjmallett info.group_index = 0; 6328215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6329215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6330215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 6331215976Sjmallett info.func = __cvmx_error_display; 6332215976Sjmallett info.user_info = (long) 6333215976Sjmallett "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n"; 6334215976Sjmallett fail |= cvmx_error_add(&info); 6335215976Sjmallett 6336215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6337215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 6338215976Sjmallett info.status_mask = 1ull<<4 /* badtag */; 6339215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 6340215976Sjmallett info.enable_mask = 1ull<<4 /* badtag */; 6341215976Sjmallett info.flags = 0; 6342215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6343215976Sjmallett info.group_index = 0; 6344215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6345215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6346215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 6347215976Sjmallett info.func = __cvmx_error_display; 6348215976Sjmallett info.user_info = (long) 6349215976Sjmallett "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n"; 6350215976Sjmallett fail |= cvmx_error_add(&info); 6351215976Sjmallett 6352215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6353215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 6354215976Sjmallett info.status_mask = 1ull<<5 /* skprunt */; 6355215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 6356215976Sjmallett info.enable_mask = 1ull<<5 /* skprunt */; 6357215976Sjmallett info.flags = 0; 6358215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6359215976Sjmallett info.group_index = 0; 6360215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6361215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6362215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 6363215976Sjmallett info.func = __cvmx_error_display; 6364215976Sjmallett info.user_info = (long) 6365215976Sjmallett "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n" 6366215976Sjmallett " This interrupt can occur with received PARTIAL\n" 6367215976Sjmallett " packets that are truncated to SKIP bytes or\n" 6368215976Sjmallett " smaller.\n"; 6369215976Sjmallett fail |= cvmx_error_add(&info); 6370215976Sjmallett 6371215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6372215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 6373215976Sjmallett info.status_mask = 1ull<<6 /* todoovr */; 6374215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 6375215976Sjmallett info.enable_mask = 1ull<<6 /* todoovr */; 6376215976Sjmallett info.flags = 0; 6377215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6378215976Sjmallett info.group_index = 0; 6379215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6380215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6381215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 6382215976Sjmallett info.func = __cvmx_error_display; 6383215976Sjmallett info.user_info = (long) 6384215976Sjmallett "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n"; 6385215976Sjmallett fail |= cvmx_error_add(&info); 6386215976Sjmallett 6387215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6388215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 6389215976Sjmallett info.status_mask = 1ull<<7 /* feperr */; 6390215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 6391215976Sjmallett info.enable_mask = 1ull<<7 /* feperr */; 6392215976Sjmallett info.flags = 0; 6393215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6394215976Sjmallett info.group_index = 0; 6395215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6396215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6397215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 6398215976Sjmallett info.func = __cvmx_error_display; 6399215976Sjmallett info.user_info = (long) 6400215976Sjmallett "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n"; 6401215976Sjmallett fail |= cvmx_error_add(&info); 6402215976Sjmallett 6403215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6404215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 6405215976Sjmallett info.status_mask = 1ull<<8 /* beperr */; 6406215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 6407215976Sjmallett info.enable_mask = 1ull<<8 /* beperr */; 6408215976Sjmallett info.flags = 0; 6409215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6410215976Sjmallett info.group_index = 0; 6411215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6412215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6413215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 6414215976Sjmallett info.func = __cvmx_error_display; 6415215976Sjmallett info.user_info = (long) 6416215976Sjmallett "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n"; 6417215976Sjmallett fail |= cvmx_error_add(&info); 6418215976Sjmallett 6419215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6420215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 6421215976Sjmallett info.status_mask = 1ull<<12 /* punyerr */; 6422215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 6423215976Sjmallett info.enable_mask = 1ull<<12 /* punyerr */; 6424215976Sjmallett info.flags = 0; 6425215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6426215976Sjmallett info.group_index = 0; 6427215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6428215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6429215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 6430215976Sjmallett info.func = __cvmx_error_display; 6431215976Sjmallett info.user_info = (long) 6432215976Sjmallett "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n" 6433215976Sjmallett " stripping in IPD is enable\n"; 6434215976Sjmallett fail |= cvmx_error_add(&info); 6435215976Sjmallett 6436215976Sjmallett /* CVMX_FPA_INT_SUM */ 6437215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6438215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6439215976Sjmallett info.status_mask = 1ull<<0 /* fed0_sbe */; 6440215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6441215976Sjmallett info.enable_mask = 1ull<<0 /* fed0_sbe */; 6442215976Sjmallett info.flags = 0; 6443215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6444215976Sjmallett info.group_index = 0; 6445215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6446215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6447215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6448215976Sjmallett info.func = __cvmx_error_display; 6449215976Sjmallett info.user_info = (long) 6450215976Sjmallett "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n"; 6451215976Sjmallett fail |= cvmx_error_add(&info); 6452215976Sjmallett 6453215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6454215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6455215976Sjmallett info.status_mask = 1ull<<1 /* fed0_dbe */; 6456215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6457215976Sjmallett info.enable_mask = 1ull<<1 /* fed0_dbe */; 6458215976Sjmallett info.flags = 0; 6459215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6460215976Sjmallett info.group_index = 0; 6461215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6462215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6463215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6464215976Sjmallett info.func = __cvmx_error_display; 6465215976Sjmallett info.user_info = (long) 6466215976Sjmallett "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n"; 6467215976Sjmallett fail |= cvmx_error_add(&info); 6468215976Sjmallett 6469215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6470215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6471215976Sjmallett info.status_mask = 1ull<<2 /* fed1_sbe */; 6472215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6473215976Sjmallett info.enable_mask = 1ull<<2 /* fed1_sbe */; 6474215976Sjmallett info.flags = 0; 6475215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6476215976Sjmallett info.group_index = 0; 6477215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6478215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6479215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6480215976Sjmallett info.func = __cvmx_error_display; 6481215976Sjmallett info.user_info = (long) 6482215976Sjmallett "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n"; 6483215976Sjmallett fail |= cvmx_error_add(&info); 6484215976Sjmallett 6485215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6486215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6487215976Sjmallett info.status_mask = 1ull<<3 /* fed1_dbe */; 6488215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6489215976Sjmallett info.enable_mask = 1ull<<3 /* fed1_dbe */; 6490215976Sjmallett info.flags = 0; 6491215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6492215976Sjmallett info.group_index = 0; 6493215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6494215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6495215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6496215976Sjmallett info.func = __cvmx_error_display; 6497215976Sjmallett info.user_info = (long) 6498215976Sjmallett "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n"; 6499215976Sjmallett fail |= cvmx_error_add(&info); 6500215976Sjmallett 6501215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6502215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6503215976Sjmallett info.status_mask = 1ull<<4 /* q0_und */; 6504215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6505215976Sjmallett info.enable_mask = 1ull<<4 /* q0_und */; 6506215976Sjmallett info.flags = 0; 6507215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6508215976Sjmallett info.group_index = 0; 6509215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6510215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6511215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6512215976Sjmallett info.func = __cvmx_error_display; 6513215976Sjmallett info.user_info = (long) 6514215976Sjmallett "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n" 6515215976Sjmallett " negative.\n"; 6516215976Sjmallett fail |= cvmx_error_add(&info); 6517215976Sjmallett 6518215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6519215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6520215976Sjmallett info.status_mask = 1ull<<5 /* q0_coff */; 6521215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6522215976Sjmallett info.enable_mask = 1ull<<5 /* q0_coff */; 6523215976Sjmallett info.flags = 0; 6524215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6525215976Sjmallett info.group_index = 0; 6526215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6527215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6528215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6529215976Sjmallett info.func = __cvmx_error_display; 6530215976Sjmallett info.user_info = (long) 6531215976Sjmallett "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n" 6532215976Sjmallett " the count available is greater than pointers\n" 6533215976Sjmallett " present in the FPA.\n"; 6534215976Sjmallett fail |= cvmx_error_add(&info); 6535215976Sjmallett 6536215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6537215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6538215976Sjmallett info.status_mask = 1ull<<6 /* q0_perr */; 6539215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6540215976Sjmallett info.enable_mask = 1ull<<6 /* q0_perr */; 6541215976Sjmallett info.flags = 0; 6542215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6543215976Sjmallett info.group_index = 0; 6544215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6545215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6546215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6547215976Sjmallett info.func = __cvmx_error_display; 6548215976Sjmallett info.user_info = (long) 6549215976Sjmallett "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n" 6550215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6551215976Sjmallett fail |= cvmx_error_add(&info); 6552215976Sjmallett 6553215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6554215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6555215976Sjmallett info.status_mask = 1ull<<7 /* q1_und */; 6556215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6557215976Sjmallett info.enable_mask = 1ull<<7 /* q1_und */; 6558215976Sjmallett info.flags = 0; 6559215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6560215976Sjmallett info.group_index = 0; 6561215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6562215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6563215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6564215976Sjmallett info.func = __cvmx_error_display; 6565215976Sjmallett info.user_info = (long) 6566215976Sjmallett "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n" 6567215976Sjmallett " negative.\n"; 6568215976Sjmallett fail |= cvmx_error_add(&info); 6569215976Sjmallett 6570215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6571215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6572215976Sjmallett info.status_mask = 1ull<<8 /* q1_coff */; 6573215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6574215976Sjmallett info.enable_mask = 1ull<<8 /* q1_coff */; 6575215976Sjmallett info.flags = 0; 6576215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6577215976Sjmallett info.group_index = 0; 6578215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6579215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6580215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6581215976Sjmallett info.func = __cvmx_error_display; 6582215976Sjmallett info.user_info = (long) 6583215976Sjmallett "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n" 6584215976Sjmallett " the count available is greater than pointers\n" 6585215976Sjmallett " present in the FPA.\n"; 6586215976Sjmallett fail |= cvmx_error_add(&info); 6587215976Sjmallett 6588215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6589215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6590215976Sjmallett info.status_mask = 1ull<<9 /* q1_perr */; 6591215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6592215976Sjmallett info.enable_mask = 1ull<<9 /* q1_perr */; 6593215976Sjmallett info.flags = 0; 6594215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6595215976Sjmallett info.group_index = 0; 6596215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6597215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6598215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6599215976Sjmallett info.func = __cvmx_error_display; 6600215976Sjmallett info.user_info = (long) 6601215976Sjmallett "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n" 6602215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6603215976Sjmallett fail |= cvmx_error_add(&info); 6604215976Sjmallett 6605215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6606215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6607215976Sjmallett info.status_mask = 1ull<<10 /* q2_und */; 6608215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6609215976Sjmallett info.enable_mask = 1ull<<10 /* q2_und */; 6610215976Sjmallett info.flags = 0; 6611215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6612215976Sjmallett info.group_index = 0; 6613215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6614215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6615215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6616215976Sjmallett info.func = __cvmx_error_display; 6617215976Sjmallett info.user_info = (long) 6618215976Sjmallett "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n" 6619215976Sjmallett " negative.\n"; 6620215976Sjmallett fail |= cvmx_error_add(&info); 6621215976Sjmallett 6622215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6623215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6624215976Sjmallett info.status_mask = 1ull<<11 /* q2_coff */; 6625215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6626215976Sjmallett info.enable_mask = 1ull<<11 /* q2_coff */; 6627215976Sjmallett info.flags = 0; 6628215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6629215976Sjmallett info.group_index = 0; 6630215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6631215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6632215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6633215976Sjmallett info.func = __cvmx_error_display; 6634215976Sjmallett info.user_info = (long) 6635215976Sjmallett "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n" 6636215976Sjmallett " the count available is greater than than pointers\n" 6637215976Sjmallett " present in the FPA.\n"; 6638215976Sjmallett fail |= cvmx_error_add(&info); 6639215976Sjmallett 6640215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6641215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6642215976Sjmallett info.status_mask = 1ull<<12 /* q2_perr */; 6643215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6644215976Sjmallett info.enable_mask = 1ull<<12 /* q2_perr */; 6645215976Sjmallett info.flags = 0; 6646215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6647215976Sjmallett info.group_index = 0; 6648215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6649215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6650215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6651215976Sjmallett info.func = __cvmx_error_display; 6652215976Sjmallett info.user_info = (long) 6653215976Sjmallett "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n" 6654215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6655215976Sjmallett fail |= cvmx_error_add(&info); 6656215976Sjmallett 6657215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6658215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6659215976Sjmallett info.status_mask = 1ull<<13 /* q3_und */; 6660215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6661215976Sjmallett info.enable_mask = 1ull<<13 /* q3_und */; 6662215976Sjmallett info.flags = 0; 6663215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6664215976Sjmallett info.group_index = 0; 6665215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6666215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6667215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6668215976Sjmallett info.func = __cvmx_error_display; 6669215976Sjmallett info.user_info = (long) 6670215976Sjmallett "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n" 6671215976Sjmallett " negative.\n"; 6672215976Sjmallett fail |= cvmx_error_add(&info); 6673215976Sjmallett 6674215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6675215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6676215976Sjmallett info.status_mask = 1ull<<14 /* q3_coff */; 6677215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6678215976Sjmallett info.enable_mask = 1ull<<14 /* q3_coff */; 6679215976Sjmallett info.flags = 0; 6680215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6681215976Sjmallett info.group_index = 0; 6682215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6683215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6684215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6685215976Sjmallett info.func = __cvmx_error_display; 6686215976Sjmallett info.user_info = (long) 6687215976Sjmallett "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n" 6688215976Sjmallett " the count available is greater than than pointers\n" 6689215976Sjmallett " present in the FPA.\n"; 6690215976Sjmallett fail |= cvmx_error_add(&info); 6691215976Sjmallett 6692215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6693215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6694215976Sjmallett info.status_mask = 1ull<<15 /* q3_perr */; 6695215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6696215976Sjmallett info.enable_mask = 1ull<<15 /* q3_perr */; 6697215976Sjmallett info.flags = 0; 6698215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6699215976Sjmallett info.group_index = 0; 6700215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6701215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6702215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6703215976Sjmallett info.func = __cvmx_error_display; 6704215976Sjmallett info.user_info = (long) 6705215976Sjmallett "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n" 6706215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6707215976Sjmallett fail |= cvmx_error_add(&info); 6708215976Sjmallett 6709215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6710215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6711215976Sjmallett info.status_mask = 1ull<<16 /* q4_und */; 6712215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6713215976Sjmallett info.enable_mask = 1ull<<16 /* q4_und */; 6714215976Sjmallett info.flags = 0; 6715215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6716215976Sjmallett info.group_index = 0; 6717215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6718215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6719215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6720215976Sjmallett info.func = __cvmx_error_display; 6721215976Sjmallett info.user_info = (long) 6722215976Sjmallett "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n" 6723215976Sjmallett " negative.\n"; 6724215976Sjmallett fail |= cvmx_error_add(&info); 6725215976Sjmallett 6726215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6727215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6728215976Sjmallett info.status_mask = 1ull<<17 /* q4_coff */; 6729215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6730215976Sjmallett info.enable_mask = 1ull<<17 /* q4_coff */; 6731215976Sjmallett info.flags = 0; 6732215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6733215976Sjmallett info.group_index = 0; 6734215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6735215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6736215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6737215976Sjmallett info.func = __cvmx_error_display; 6738215976Sjmallett info.user_info = (long) 6739215976Sjmallett "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n" 6740215976Sjmallett " the count available is greater than than pointers\n" 6741215976Sjmallett " present in the FPA.\n"; 6742215976Sjmallett fail |= cvmx_error_add(&info); 6743215976Sjmallett 6744215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6745215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6746215976Sjmallett info.status_mask = 1ull<<18 /* q4_perr */; 6747215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6748215976Sjmallett info.enable_mask = 1ull<<18 /* q4_perr */; 6749215976Sjmallett info.flags = 0; 6750215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6751215976Sjmallett info.group_index = 0; 6752215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6753215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6754215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6755215976Sjmallett info.func = __cvmx_error_display; 6756215976Sjmallett info.user_info = (long) 6757215976Sjmallett "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n" 6758215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6759215976Sjmallett fail |= cvmx_error_add(&info); 6760215976Sjmallett 6761215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6762215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6763215976Sjmallett info.status_mask = 1ull<<19 /* q5_und */; 6764215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6765215976Sjmallett info.enable_mask = 1ull<<19 /* q5_und */; 6766215976Sjmallett info.flags = 0; 6767215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6768215976Sjmallett info.group_index = 0; 6769215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6770215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6771215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6772215976Sjmallett info.func = __cvmx_error_display; 6773215976Sjmallett info.user_info = (long) 6774215976Sjmallett "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n" 6775215976Sjmallett " negative.\n"; 6776215976Sjmallett fail |= cvmx_error_add(&info); 6777215976Sjmallett 6778215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6779215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6780215976Sjmallett info.status_mask = 1ull<<20 /* q5_coff */; 6781215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6782215976Sjmallett info.enable_mask = 1ull<<20 /* q5_coff */; 6783215976Sjmallett info.flags = 0; 6784215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6785215976Sjmallett info.group_index = 0; 6786215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6787215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6788215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6789215976Sjmallett info.func = __cvmx_error_display; 6790215976Sjmallett info.user_info = (long) 6791215976Sjmallett "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n" 6792215976Sjmallett " the count available is greater than than pointers\n" 6793215976Sjmallett " present in the FPA.\n"; 6794215976Sjmallett fail |= cvmx_error_add(&info); 6795215976Sjmallett 6796215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6797215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6798215976Sjmallett info.status_mask = 1ull<<21 /* q5_perr */; 6799215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6800215976Sjmallett info.enable_mask = 1ull<<21 /* q5_perr */; 6801215976Sjmallett info.flags = 0; 6802215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6803215976Sjmallett info.group_index = 0; 6804215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6805215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6806215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6807215976Sjmallett info.func = __cvmx_error_display; 6808215976Sjmallett info.user_info = (long) 6809215976Sjmallett "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n" 6810215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6811215976Sjmallett fail |= cvmx_error_add(&info); 6812215976Sjmallett 6813215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6814215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6815215976Sjmallett info.status_mask = 1ull<<22 /* q6_und */; 6816215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6817215976Sjmallett info.enable_mask = 1ull<<22 /* q6_und */; 6818215976Sjmallett info.flags = 0; 6819215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6820215976Sjmallett info.group_index = 0; 6821215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6822215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6823215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6824215976Sjmallett info.func = __cvmx_error_display; 6825215976Sjmallett info.user_info = (long) 6826215976Sjmallett "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n" 6827215976Sjmallett " negative.\n"; 6828215976Sjmallett fail |= cvmx_error_add(&info); 6829215976Sjmallett 6830215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6831215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6832215976Sjmallett info.status_mask = 1ull<<23 /* q6_coff */; 6833215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6834215976Sjmallett info.enable_mask = 1ull<<23 /* q6_coff */; 6835215976Sjmallett info.flags = 0; 6836215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6837215976Sjmallett info.group_index = 0; 6838215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6839215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6840215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6841215976Sjmallett info.func = __cvmx_error_display; 6842215976Sjmallett info.user_info = (long) 6843215976Sjmallett "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n" 6844215976Sjmallett " the count available is greater than than pointers\n" 6845215976Sjmallett " present in the FPA.\n"; 6846215976Sjmallett fail |= cvmx_error_add(&info); 6847215976Sjmallett 6848215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6849215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6850215976Sjmallett info.status_mask = 1ull<<24 /* q6_perr */; 6851215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6852215976Sjmallett info.enable_mask = 1ull<<24 /* q6_perr */; 6853215976Sjmallett info.flags = 0; 6854215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6855215976Sjmallett info.group_index = 0; 6856215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6857215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6858215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6859215976Sjmallett info.func = __cvmx_error_display; 6860215976Sjmallett info.user_info = (long) 6861215976Sjmallett "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n" 6862215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6863215976Sjmallett fail |= cvmx_error_add(&info); 6864215976Sjmallett 6865215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6866215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6867215976Sjmallett info.status_mask = 1ull<<25 /* q7_und */; 6868215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6869215976Sjmallett info.enable_mask = 1ull<<25 /* q7_und */; 6870215976Sjmallett info.flags = 0; 6871215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6872215976Sjmallett info.group_index = 0; 6873215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6874215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6875215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6876215976Sjmallett info.func = __cvmx_error_display; 6877215976Sjmallett info.user_info = (long) 6878215976Sjmallett "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n" 6879215976Sjmallett " negative.\n"; 6880215976Sjmallett fail |= cvmx_error_add(&info); 6881215976Sjmallett 6882215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6883215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6884215976Sjmallett info.status_mask = 1ull<<26 /* q7_coff */; 6885215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6886215976Sjmallett info.enable_mask = 1ull<<26 /* q7_coff */; 6887215976Sjmallett info.flags = 0; 6888215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6889215976Sjmallett info.group_index = 0; 6890215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6891215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6892215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6893215976Sjmallett info.func = __cvmx_error_display; 6894215976Sjmallett info.user_info = (long) 6895215976Sjmallett "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n" 6896215976Sjmallett " the count available is greater than than pointers\n" 6897215976Sjmallett " present in the FPA.\n"; 6898215976Sjmallett fail |= cvmx_error_add(&info); 6899215976Sjmallett 6900215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6901215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 6902215976Sjmallett info.status_mask = 1ull<<27 /* q7_perr */; 6903215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 6904215976Sjmallett info.enable_mask = 1ull<<27 /* q7_perr */; 6905215976Sjmallett info.flags = 0; 6906215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6907215976Sjmallett info.group_index = 0; 6908215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6909215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6910215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 6911215976Sjmallett info.func = __cvmx_error_display; 6912215976Sjmallett info.user_info = (long) 6913215976Sjmallett "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n" 6914215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 6915215976Sjmallett fail |= cvmx_error_add(&info); 6916215976Sjmallett 6917215976Sjmallett /* CVMX_LMCX_MEM_CFG0(0) */ 6918215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6919215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 6920215976Sjmallett info.status_mask = 0xfull<<21 /* sec_err */; 6921215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 6922215976Sjmallett info.enable_mask = 1ull<<19 /* intr_sec_ena */; 6923215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 6924215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 6925215976Sjmallett info.group_index = 0; 6926215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6927215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6928215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc0 */; 6929215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err; 6930215976Sjmallett info.user_info = (long) 6931215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n" 6932215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 6933215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 6934215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 6935215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 6936215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 6937215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 6938215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 6939215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 6940215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 6941215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 6942215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 6943215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 6944215976Sjmallett fail |= cvmx_error_add(&info); 6945215976Sjmallett 6946215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6947215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 6948215976Sjmallett info.status_mask = 0xfull<<25 /* ded_err */; 6949215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 6950215976Sjmallett info.enable_mask = 1ull<<20 /* intr_ded_ena */; 6951215976Sjmallett info.flags = 0; 6952215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 6953215976Sjmallett info.group_index = 0; 6954215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6955215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6956215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc0 */; 6957215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err; 6958215976Sjmallett info.user_info = (long) 6959215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n" 6960215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 6961215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 6962215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 6963215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 6964215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 6965215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 6966215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 6967215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 6968215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 6969215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 6970215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 6971215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 6972215976Sjmallett fail |= cvmx_error_add(&info); 6973215976Sjmallett 6974215976Sjmallett /* CVMX_IOB_INT_SUM */ 6975215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6976215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6977215976Sjmallett info.status_mask = 1ull<<0 /* np_sop */; 6978215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6979215976Sjmallett info.enable_mask = 1ull<<0 /* np_sop */; 6980215976Sjmallett info.flags = 0; 6981215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6982215976Sjmallett info.group_index = 0; 6983215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6984215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6985215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6986215976Sjmallett info.func = __cvmx_error_display; 6987215976Sjmallett info.user_info = (long) 6988215976Sjmallett "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n" 6989215976Sjmallett " port for a non-passthrough packet.\n" 6990215976Sjmallett " The first detected error associated with bits [5:0]\n" 6991215976Sjmallett " of this register will only be set here. A new bit\n" 6992215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6993215976Sjmallett fail |= cvmx_error_add(&info); 6994215976Sjmallett 6995215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6996215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6997215976Sjmallett info.status_mask = 1ull<<1 /* np_eop */; 6998215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6999215976Sjmallett info.enable_mask = 1ull<<1 /* np_eop */; 7000215976Sjmallett info.flags = 0; 7001215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 7002215976Sjmallett info.group_index = 0; 7003215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7004215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7005215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 7006215976Sjmallett info.func = __cvmx_error_display; 7007215976Sjmallett info.user_info = (long) 7008215976Sjmallett "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n" 7009215976Sjmallett " port for a non-passthrough packet.\n" 7010215976Sjmallett " The first detected error associated with bits [5:0]\n" 7011215976Sjmallett " of this register will only be set here. A new bit\n" 7012215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 7013215976Sjmallett fail |= cvmx_error_add(&info); 7014215976Sjmallett 7015215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7016215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 7017215976Sjmallett info.status_mask = 1ull<<2 /* p_sop */; 7018215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 7019215976Sjmallett info.enable_mask = 1ull<<2 /* p_sop */; 7020215976Sjmallett info.flags = 0; 7021215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 7022215976Sjmallett info.group_index = 0; 7023215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7024215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7025215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 7026215976Sjmallett info.func = __cvmx_error_display; 7027215976Sjmallett info.user_info = (long) 7028215976Sjmallett "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n" 7029215976Sjmallett " port for a passthrough packet.\n" 7030215976Sjmallett " The first detected error associated with bits [5:0]\n" 7031215976Sjmallett " of this register will only be set here. A new bit\n" 7032215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 7033215976Sjmallett fail |= cvmx_error_add(&info); 7034215976Sjmallett 7035215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7036215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 7037215976Sjmallett info.status_mask = 1ull<<3 /* p_eop */; 7038215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 7039215976Sjmallett info.enable_mask = 1ull<<3 /* p_eop */; 7040215976Sjmallett info.flags = 0; 7041215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 7042215976Sjmallett info.group_index = 0; 7043215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7044215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7045215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 7046215976Sjmallett info.func = __cvmx_error_display; 7047215976Sjmallett info.user_info = (long) 7048215976Sjmallett "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n" 7049215976Sjmallett " port for a passthrough packet.\n" 7050215976Sjmallett " The first detected error associated with bits [5:0]\n" 7051215976Sjmallett " of this register will only be set here. A new bit\n" 7052215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 7053215976Sjmallett fail |= cvmx_error_add(&info); 7054215976Sjmallett 7055215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7056215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 7057215976Sjmallett info.status_mask = 1ull<<4 /* np_dat */; 7058215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 7059215976Sjmallett info.enable_mask = 1ull<<4 /* np_dat */; 7060215976Sjmallett info.flags = 0; 7061215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 7062215976Sjmallett info.group_index = 0; 7063215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7064215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7065215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 7066215976Sjmallett info.func = __cvmx_error_display; 7067215976Sjmallett info.user_info = (long) 7068215976Sjmallett "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n" 7069215976Sjmallett " port for a non-passthrough packet.\n" 7070215976Sjmallett " The first detected error associated with bits [5:0]\n" 7071215976Sjmallett " of this register will only be set here. A new bit\n" 7072215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 7073215976Sjmallett fail |= cvmx_error_add(&info); 7074215976Sjmallett 7075215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7076215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 7077215976Sjmallett info.status_mask = 1ull<<5 /* p_dat */; 7078215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 7079215976Sjmallett info.enable_mask = 1ull<<5 /* p_dat */; 7080215976Sjmallett info.flags = 0; 7081215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 7082215976Sjmallett info.group_index = 0; 7083215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7084215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7085215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 7086215976Sjmallett info.func = __cvmx_error_display; 7087215976Sjmallett info.user_info = (long) 7088215976Sjmallett "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n" 7089215976Sjmallett " port for a passthrough packet.\n" 7090215976Sjmallett " The first detected error associated with bits [5:0]\n" 7091215976Sjmallett " of this register will only be set here. A new bit\n" 7092215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 7093215976Sjmallett fail |= cvmx_error_add(&info); 7094215976Sjmallett 7095215976Sjmallett /* CVMX_ZIP_ERROR */ 7096215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7097215976Sjmallett info.status_addr = CVMX_ZIP_ERROR; 7098215976Sjmallett info.status_mask = 1ull<<0 /* doorbell */; 7099215976Sjmallett info.enable_addr = CVMX_ZIP_INT_MASK; 7100215976Sjmallett info.enable_mask = 1ull<<0 /* doorbell */; 7101215976Sjmallett info.flags = 0; 7102215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 7103215976Sjmallett info.group_index = 0; 7104215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7105215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7106215976Sjmallett info.parent.status_mask = 1ull<<7 /* zip */; 7107215976Sjmallett info.func = __cvmx_error_display; 7108215976Sjmallett info.user_info = (long) 7109215976Sjmallett "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 7110215976Sjmallett fail |= cvmx_error_add(&info); 7111215976Sjmallett 7112215976Sjmallett /* CVMX_USBNX_INT_SUM(0) */ 7113215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7114215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7115215976Sjmallett info.status_mask = 1ull<<0 /* pr_po_e */; 7116215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7117215976Sjmallett info.enable_mask = 1ull<<0 /* pr_po_e */; 7118215976Sjmallett info.flags = 0; 7119215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7120215976Sjmallett info.group_index = 0; 7121215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7122215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7123215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7124215976Sjmallett info.func = __cvmx_error_display; 7125215976Sjmallett info.user_info = (long) 7126215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n"; 7127215976Sjmallett fail |= cvmx_error_add(&info); 7128215976Sjmallett 7129215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7130215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7131215976Sjmallett info.status_mask = 1ull<<1 /* pr_pu_f */; 7132215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7133215976Sjmallett info.enable_mask = 1ull<<1 /* pr_pu_f */; 7134215976Sjmallett info.flags = 0; 7135215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7136215976Sjmallett info.group_index = 0; 7137215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7138215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7139215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7140215976Sjmallett info.func = __cvmx_error_display; 7141215976Sjmallett info.user_info = (long) 7142215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n"; 7143215976Sjmallett fail |= cvmx_error_add(&info); 7144215976Sjmallett 7145215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7146215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7147215976Sjmallett info.status_mask = 1ull<<2 /* nr_po_e */; 7148215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7149215976Sjmallett info.enable_mask = 1ull<<2 /* nr_po_e */; 7150215976Sjmallett info.flags = 0; 7151215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7152215976Sjmallett info.group_index = 0; 7153215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7154215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7155215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7156215976Sjmallett info.func = __cvmx_error_display; 7157215976Sjmallett info.user_info = (long) 7158215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n"; 7159215976Sjmallett fail |= cvmx_error_add(&info); 7160215976Sjmallett 7161215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7162215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7163215976Sjmallett info.status_mask = 1ull<<3 /* nr_pu_f */; 7164215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7165215976Sjmallett info.enable_mask = 1ull<<3 /* nr_pu_f */; 7166215976Sjmallett info.flags = 0; 7167215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7168215976Sjmallett info.group_index = 0; 7169215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7170215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7171215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7172215976Sjmallett info.func = __cvmx_error_display; 7173215976Sjmallett info.user_info = (long) 7174215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n"; 7175215976Sjmallett fail |= cvmx_error_add(&info); 7176215976Sjmallett 7177215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7178215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7179215976Sjmallett info.status_mask = 1ull<<4 /* lr_po_e */; 7180215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7181215976Sjmallett info.enable_mask = 1ull<<4 /* lr_po_e */; 7182215976Sjmallett info.flags = 0; 7183215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7184215976Sjmallett info.group_index = 0; 7185215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7186215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7187215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7188215976Sjmallett info.func = __cvmx_error_display; 7189215976Sjmallett info.user_info = (long) 7190215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n"; 7191215976Sjmallett fail |= cvmx_error_add(&info); 7192215976Sjmallett 7193215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7194215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7195215976Sjmallett info.status_mask = 1ull<<5 /* lr_pu_f */; 7196215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7197215976Sjmallett info.enable_mask = 1ull<<5 /* lr_pu_f */; 7198215976Sjmallett info.flags = 0; 7199215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7200215976Sjmallett info.group_index = 0; 7201215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7202215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7203215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7204215976Sjmallett info.func = __cvmx_error_display; 7205215976Sjmallett info.user_info = (long) 7206215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n"; 7207215976Sjmallett fail |= cvmx_error_add(&info); 7208215976Sjmallett 7209215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7210215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7211215976Sjmallett info.status_mask = 1ull<<6 /* pt_po_e */; 7212215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7213215976Sjmallett info.enable_mask = 1ull<<6 /* pt_po_e */; 7214215976Sjmallett info.flags = 0; 7215215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7216215976Sjmallett info.group_index = 0; 7217215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7218215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7219215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7220215976Sjmallett info.func = __cvmx_error_display; 7221215976Sjmallett info.user_info = (long) 7222215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n"; 7223215976Sjmallett fail |= cvmx_error_add(&info); 7224215976Sjmallett 7225215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7226215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7227215976Sjmallett info.status_mask = 1ull<<7 /* pt_pu_f */; 7228215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7229215976Sjmallett info.enable_mask = 1ull<<7 /* pt_pu_f */; 7230215976Sjmallett info.flags = 0; 7231215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7232215976Sjmallett info.group_index = 0; 7233215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7234215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7235215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7236215976Sjmallett info.func = __cvmx_error_display; 7237215976Sjmallett info.user_info = (long) 7238215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n"; 7239215976Sjmallett fail |= cvmx_error_add(&info); 7240215976Sjmallett 7241215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7242215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7243215976Sjmallett info.status_mask = 1ull<<8 /* nt_po_e */; 7244215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7245215976Sjmallett info.enable_mask = 1ull<<8 /* nt_po_e */; 7246215976Sjmallett info.flags = 0; 7247215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7248215976Sjmallett info.group_index = 0; 7249215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7250215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7251215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7252215976Sjmallett info.func = __cvmx_error_display; 7253215976Sjmallett info.user_info = (long) 7254215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n"; 7255215976Sjmallett fail |= cvmx_error_add(&info); 7256215976Sjmallett 7257215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7258215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7259215976Sjmallett info.status_mask = 1ull<<9 /* nt_pu_f */; 7260215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7261215976Sjmallett info.enable_mask = 1ull<<9 /* nt_pu_f */; 7262215976Sjmallett info.flags = 0; 7263215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7264215976Sjmallett info.group_index = 0; 7265215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7266215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7267215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7268215976Sjmallett info.func = __cvmx_error_display; 7269215976Sjmallett info.user_info = (long) 7270215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n"; 7271215976Sjmallett fail |= cvmx_error_add(&info); 7272215976Sjmallett 7273215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7274215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7275215976Sjmallett info.status_mask = 1ull<<10 /* lt_po_e */; 7276215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7277215976Sjmallett info.enable_mask = 1ull<<10 /* lt_po_e */; 7278215976Sjmallett info.flags = 0; 7279215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7280215976Sjmallett info.group_index = 0; 7281215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7282215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7283215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7284215976Sjmallett info.func = __cvmx_error_display; 7285215976Sjmallett info.user_info = (long) 7286215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n"; 7287215976Sjmallett fail |= cvmx_error_add(&info); 7288215976Sjmallett 7289215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7290215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7291215976Sjmallett info.status_mask = 1ull<<11 /* lt_pu_f */; 7292215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7293215976Sjmallett info.enable_mask = 1ull<<11 /* lt_pu_f */; 7294215976Sjmallett info.flags = 0; 7295215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7296215976Sjmallett info.group_index = 0; 7297215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7298215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7299215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7300215976Sjmallett info.func = __cvmx_error_display; 7301215976Sjmallett info.user_info = (long) 7302215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n"; 7303215976Sjmallett fail |= cvmx_error_add(&info); 7304215976Sjmallett 7305215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7306215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7307215976Sjmallett info.status_mask = 1ull<<12 /* dcred_e */; 7308215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7309215976Sjmallett info.enable_mask = 1ull<<12 /* dcred_e */; 7310215976Sjmallett info.flags = 0; 7311215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7312215976Sjmallett info.group_index = 0; 7313215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7314215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7315215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7316215976Sjmallett info.func = __cvmx_error_display; 7317215976Sjmallett info.user_info = (long) 7318215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n"; 7319215976Sjmallett fail |= cvmx_error_add(&info); 7320215976Sjmallett 7321215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7322215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7323215976Sjmallett info.status_mask = 1ull<<13 /* dcred_f */; 7324215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7325215976Sjmallett info.enable_mask = 1ull<<13 /* dcred_f */; 7326215976Sjmallett info.flags = 0; 7327215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7328215976Sjmallett info.group_index = 0; 7329215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7330215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7331215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7332215976Sjmallett info.func = __cvmx_error_display; 7333215976Sjmallett info.user_info = (long) 7334215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n"; 7335215976Sjmallett fail |= cvmx_error_add(&info); 7336215976Sjmallett 7337215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7338215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7339215976Sjmallett info.status_mask = 1ull<<14 /* l2c_s_e */; 7340215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7341215976Sjmallett info.enable_mask = 1ull<<14 /* l2c_s_e */; 7342215976Sjmallett info.flags = 0; 7343215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7344215976Sjmallett info.group_index = 0; 7345215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7346215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7347215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7348215976Sjmallett info.func = __cvmx_error_display; 7349215976Sjmallett info.user_info = (long) 7350215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n"; 7351215976Sjmallett fail |= cvmx_error_add(&info); 7352215976Sjmallett 7353215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7354215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7355215976Sjmallett info.status_mask = 1ull<<15 /* l2c_a_f */; 7356215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7357215976Sjmallett info.enable_mask = 1ull<<15 /* l2c_a_f */; 7358215976Sjmallett info.flags = 0; 7359215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7360215976Sjmallett info.group_index = 0; 7361215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7362215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7363215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7364215976Sjmallett info.func = __cvmx_error_display; 7365215976Sjmallett info.user_info = (long) 7366215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n"; 7367215976Sjmallett fail |= cvmx_error_add(&info); 7368215976Sjmallett 7369215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7370215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7371215976Sjmallett info.status_mask = 1ull<<16 /* lt_fi_e */; 7372215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7373215976Sjmallett info.enable_mask = 1ull<<16 /* l2_fi_e */; 7374215976Sjmallett info.flags = 0; 7375215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7376215976Sjmallett info.group_index = 0; 7377215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7378215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7379215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7380215976Sjmallett info.func = __cvmx_error_display; 7381215976Sjmallett info.user_info = (long) 7382215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n"; 7383215976Sjmallett fail |= cvmx_error_add(&info); 7384215976Sjmallett 7385215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7386215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7387215976Sjmallett info.status_mask = 1ull<<17 /* lt_fi_f */; 7388215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7389215976Sjmallett info.enable_mask = 1ull<<17 /* l2_fi_f */; 7390215976Sjmallett info.flags = 0; 7391215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7392215976Sjmallett info.group_index = 0; 7393215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7394215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7395215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7396215976Sjmallett info.func = __cvmx_error_display; 7397215976Sjmallett info.user_info = (long) 7398215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n"; 7399215976Sjmallett fail |= cvmx_error_add(&info); 7400215976Sjmallett 7401215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7402215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7403215976Sjmallett info.status_mask = 1ull<<18 /* rg_fi_e */; 7404215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7405215976Sjmallett info.enable_mask = 1ull<<18 /* rg_fi_e */; 7406215976Sjmallett info.flags = 0; 7407215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7408215976Sjmallett info.group_index = 0; 7409215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7410215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7411215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7412215976Sjmallett info.func = __cvmx_error_display; 7413215976Sjmallett info.user_info = (long) 7414215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n"; 7415215976Sjmallett fail |= cvmx_error_add(&info); 7416215976Sjmallett 7417215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7418215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7419215976Sjmallett info.status_mask = 1ull<<19 /* rg_fi_f */; 7420215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7421215976Sjmallett info.enable_mask = 1ull<<19 /* rg_fi_f */; 7422215976Sjmallett info.flags = 0; 7423215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7424215976Sjmallett info.group_index = 0; 7425215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7426215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7427215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7428215976Sjmallett info.func = __cvmx_error_display; 7429215976Sjmallett info.user_info = (long) 7430215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n"; 7431215976Sjmallett fail |= cvmx_error_add(&info); 7432215976Sjmallett 7433215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7434215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7435215976Sjmallett info.status_mask = 1ull<<20 /* rq_q2_f */; 7436215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7437215976Sjmallett info.enable_mask = 1ull<<20 /* rq_q2_f */; 7438215976Sjmallett info.flags = 0; 7439215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7440215976Sjmallett info.group_index = 0; 7441215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7442215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7443215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7444215976Sjmallett info.func = __cvmx_error_display; 7445215976Sjmallett info.user_info = (long) 7446215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n"; 7447215976Sjmallett fail |= cvmx_error_add(&info); 7448215976Sjmallett 7449215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7450215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7451215976Sjmallett info.status_mask = 1ull<<21 /* rq_q2_e */; 7452215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7453215976Sjmallett info.enable_mask = 1ull<<21 /* rq_q2_e */; 7454215976Sjmallett info.flags = 0; 7455215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7456215976Sjmallett info.group_index = 0; 7457215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7458215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7459215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7460215976Sjmallett info.func = __cvmx_error_display; 7461215976Sjmallett info.user_info = (long) 7462215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n"; 7463215976Sjmallett fail |= cvmx_error_add(&info); 7464215976Sjmallett 7465215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7466215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7467215976Sjmallett info.status_mask = 1ull<<22 /* rq_q3_f */; 7468215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7469215976Sjmallett info.enable_mask = 1ull<<22 /* rq_q3_f */; 7470215976Sjmallett info.flags = 0; 7471215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7472215976Sjmallett info.group_index = 0; 7473215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7474215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7475215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7476215976Sjmallett info.func = __cvmx_error_display; 7477215976Sjmallett info.user_info = (long) 7478215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n"; 7479215976Sjmallett fail |= cvmx_error_add(&info); 7480215976Sjmallett 7481215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7482215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7483215976Sjmallett info.status_mask = 1ull<<23 /* rq_q3_e */; 7484215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7485215976Sjmallett info.enable_mask = 1ull<<23 /* rq_q3_e */; 7486215976Sjmallett info.flags = 0; 7487215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7488215976Sjmallett info.group_index = 0; 7489215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7490215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7491215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7492215976Sjmallett info.func = __cvmx_error_display; 7493215976Sjmallett info.user_info = (long) 7494215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n"; 7495215976Sjmallett fail |= cvmx_error_add(&info); 7496215976Sjmallett 7497215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7498215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7499215976Sjmallett info.status_mask = 1ull<<24 /* uod_pe */; 7500215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7501215976Sjmallett info.enable_mask = 1ull<<24 /* uod_pe */; 7502215976Sjmallett info.flags = 0; 7503215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7504215976Sjmallett info.group_index = 0; 7505215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7506215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7507215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7508215976Sjmallett info.func = __cvmx_error_display; 7509215976Sjmallett info.user_info = (long) 7510215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n"; 7511215976Sjmallett fail |= cvmx_error_add(&info); 7512215976Sjmallett 7513215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7514215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7515215976Sjmallett info.status_mask = 1ull<<25 /* uod_pf */; 7516215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7517215976Sjmallett info.enable_mask = 1ull<<25 /* uod_pf */; 7518215976Sjmallett info.flags = 0; 7519215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7520215976Sjmallett info.group_index = 0; 7521215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7522215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7523215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7524215976Sjmallett info.func = __cvmx_error_display; 7525215976Sjmallett info.user_info = (long) 7526215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n"; 7527215976Sjmallett fail |= cvmx_error_add(&info); 7528215976Sjmallett 7529215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7530215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7531215976Sjmallett info.status_mask = 1ull<<32 /* ltl_f_pe */; 7532215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7533215976Sjmallett info.enable_mask = 1ull<<32 /* ltl_f_pe */; 7534215976Sjmallett info.flags = 0; 7535215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7536215976Sjmallett info.group_index = 0; 7537215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7538215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7539215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7540215976Sjmallett info.func = __cvmx_error_display; 7541215976Sjmallett info.user_info = (long) 7542215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n"; 7543215976Sjmallett fail |= cvmx_error_add(&info); 7544215976Sjmallett 7545215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7546215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7547215976Sjmallett info.status_mask = 1ull<<33 /* ltl_f_pf */; 7548215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7549215976Sjmallett info.enable_mask = 1ull<<33 /* ltl_f_pf */; 7550215976Sjmallett info.flags = 0; 7551215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7552215976Sjmallett info.group_index = 0; 7553215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7554215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7555215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7556215976Sjmallett info.func = __cvmx_error_display; 7557215976Sjmallett info.user_info = (long) 7558215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n"; 7559215976Sjmallett fail |= cvmx_error_add(&info); 7560215976Sjmallett 7561215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7562215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7563215976Sjmallett info.status_mask = 1ull<<34 /* nd4o_rpe */; 7564215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7565215976Sjmallett info.enable_mask = 1ull<<34 /* nd4o_rpe */; 7566215976Sjmallett info.flags = 0; 7567215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7568215976Sjmallett info.group_index = 0; 7569215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7570215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7571215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7572215976Sjmallett info.func = __cvmx_error_display; 7573215976Sjmallett info.user_info = (long) 7574215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n"; 7575215976Sjmallett fail |= cvmx_error_add(&info); 7576215976Sjmallett 7577215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7578215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7579215976Sjmallett info.status_mask = 1ull<<35 /* nd4o_rpf */; 7580215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7581215976Sjmallett info.enable_mask = 1ull<<35 /* nd4o_rpf */; 7582215976Sjmallett info.flags = 0; 7583215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7584215976Sjmallett info.group_index = 0; 7585215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7586215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7587215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7588215976Sjmallett info.func = __cvmx_error_display; 7589215976Sjmallett info.user_info = (long) 7590215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n"; 7591215976Sjmallett fail |= cvmx_error_add(&info); 7592215976Sjmallett 7593215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7594215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7595215976Sjmallett info.status_mask = 1ull<<36 /* nd4o_dpe */; 7596215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7597215976Sjmallett info.enable_mask = 1ull<<36 /* nd4o_dpe */; 7598215976Sjmallett info.flags = 0; 7599215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7600215976Sjmallett info.group_index = 0; 7601215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7602215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7603215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7604215976Sjmallett info.func = __cvmx_error_display; 7605215976Sjmallett info.user_info = (long) 7606215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n"; 7607215976Sjmallett fail |= cvmx_error_add(&info); 7608215976Sjmallett 7609215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 7610215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 7611215976Sjmallett info.status_mask = 1ull<<37 /* nd4o_dpf */; 7612215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 7613215976Sjmallett info.enable_mask = 1ull<<37 /* nd4o_dpf */; 7614215976Sjmallett info.flags = 0; 7615215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 7616215976Sjmallett info.group_index = 0; 7617215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 7618215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 7619215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 7620215976Sjmallett info.func = __cvmx_error_display; 7621215976Sjmallett info.user_info = (long) 7622215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n"; 7623215976Sjmallett fail |= cvmx_error_add(&info); 7624215976Sjmallett 7625215976Sjmallett return fail; 7626215976Sjmallett} 7627215976Sjmallett 7628