1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * @file 43215976Sjmallett * 44215976Sjmallett * Automatically generated error messages for cn52xxp1. 45215976Sjmallett * 46215976Sjmallett * This file is auto generated. Do not edit. 47215976Sjmallett * 48215976Sjmallett * <hr>$Revision$<hr> 49215976Sjmallett * 50215976Sjmallett * <hr><h2>Error tree for CN52XXP1</h2> 51215976Sjmallett * @dot 52215976Sjmallett * digraph cn52xxp1 53215976Sjmallett * { 54215976Sjmallett * rankdir=LR; 55215976Sjmallett * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica]; 56215976Sjmallett * edge [fontsize=7, font=helvitica]; 57215976Sjmallett * cvmx_root [label="ROOT|<root>root"]; 58215976Sjmallett * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"]; 59215976Sjmallett * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"]; 60215976Sjmallett * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"]; 61215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"]; 62215976Sjmallett * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1"]; 63215976Sjmallett * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"]; 64215976Sjmallett * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"]; 65215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"]; 66215976Sjmallett * cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<mio>mio|<ipd>ipd|<tim>tim|<pow>pow|<usb1>usb1|<npei>npei|<rad>rad|<pko>pko|<asxpcs0>asxpcs0|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<usb>usb"]; 67215976Sjmallett * cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"]; 68215976Sjmallett * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"]; 69215976Sjmallett * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"]; 70215976Sjmallett * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"]; 71215976Sjmallett * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"]; 72215976Sjmallett * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"]; 73215976Sjmallett * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"]; 74215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"]; 75215976Sjmallett * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"]; 76215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"]; 77215976Sjmallett * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"]; 78215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"]; 79215976Sjmallett * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"]; 80215976Sjmallett * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"]; 81215976Sjmallett * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 82215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"]; 83215976Sjmallett * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 84215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"]; 85215976Sjmallett * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 86215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"]; 87215976Sjmallett * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 88215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"]; 89215976Sjmallett * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 90215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"]; 91215976Sjmallett * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"]; 92215976Sjmallett * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"]; 93215976Sjmallett * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"]; 94215976Sjmallett * cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"]; 95215976Sjmallett * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"]; 96215976Sjmallett * cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"]; 97215976Sjmallett * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"]; 98215976Sjmallett * cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"]; 99215976Sjmallett * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"]; 100215976Sjmallett * cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"]; 101215976Sjmallett * cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"]; 102215976Sjmallett * cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"]; 103215976Sjmallett * cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<c0_exc>c0_exc|<c1_exc>c1_exc"]; 104215976Sjmallett * cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"]; 105215976Sjmallett * cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"]; 106215976Sjmallett * cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"]; 107215976Sjmallett * cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"]; 108215976Sjmallett * cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"]; 109215976Sjmallett * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"]; 110215976Sjmallett * cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"]; 111215976Sjmallett * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"]; 112215976Sjmallett * cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"]; 113215976Sjmallett * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 114215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"]; 115215976Sjmallett * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 116215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"]; 117215976Sjmallett * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 118215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"]; 119215976Sjmallett * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"]; 120215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"]; 121215976Sjmallett * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"]; 122215976Sjmallett * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"]; 123215976Sjmallett * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"]; 124215976Sjmallett * cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"]; 125215976Sjmallett * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"]; 126215976Sjmallett * cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"]; 127215976Sjmallett * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"]; 128215976Sjmallett * cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"]; 129215976Sjmallett * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"]; 130215976Sjmallett * cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"]; 131215976Sjmallett * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"]; 132215976Sjmallett * cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"]; 133215976Sjmallett * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis]; 134215976Sjmallett * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis]; 135215976Sjmallett * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis]; 136215976Sjmallett * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis]; 137215976Sjmallett * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis]; 138215976Sjmallett * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis]; 139215976Sjmallett * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis]; 140215976Sjmallett * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis]; 141215976Sjmallett * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis]; 142215976Sjmallett * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis]; 143215976Sjmallett * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis]; 144215976Sjmallett * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis]; 145215976Sjmallett * cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"]; 146215976Sjmallett * } 147215976Sjmallett * @enddot 148215976Sjmallett */ 149215976Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 150215976Sjmallett#include <asm/octeon/cvmx.h> 151215976Sjmallett#include <asm/octeon/cvmx-error.h> 152215976Sjmallett#include <asm/octeon/cvmx-error-custom.h> 153215976Sjmallett#include <asm/octeon/cvmx-csr-typedefs.h> 154215976Sjmallett#else 155215976Sjmallett#include "cvmx.h" 156215976Sjmallett#include "cvmx-error.h" 157215976Sjmallett#include "cvmx-error-custom.h" 158215976Sjmallett#endif 159215976Sjmallett 160215990Sjmallettint cvmx_error_initialize_cn52xxp1(void); 161215990Sjmallett 162215976Sjmallettint cvmx_error_initialize_cn52xxp1(void) 163215976Sjmallett{ 164215976Sjmallett cvmx_error_info_t info; 165215976Sjmallett int fail = 0; 166215976Sjmallett 167215976Sjmallett /* CVMX_CIU_INTX_SUM0(0) */ 168215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 169215976Sjmallett info.status_addr = CVMX_CIU_INTX_SUM0(0); 170215976Sjmallett info.status_mask = 0; 171215976Sjmallett info.enable_addr = 0; 172215976Sjmallett info.enable_mask = 0; 173215976Sjmallett info.flags = 0; 174215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 175215976Sjmallett info.group_index = 0; 176215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 177215976Sjmallett info.parent.status_addr = 0; 178215976Sjmallett info.parent.status_mask = 0; 179215976Sjmallett info.func = __cvmx_error_decode; 180215976Sjmallett info.user_info = 0; 181215976Sjmallett fail |= cvmx_error_add(&info); 182215976Sjmallett 183215976Sjmallett /* CVMX_MIXX_ISR(0) */ 184215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 185215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 186215976Sjmallett info.status_mask = 1ull<<0 /* odblovf */; 187215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 188215976Sjmallett info.enable_mask = 1ull<<0 /* ovfena */; 189215976Sjmallett info.flags = 0; 190215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 191215976Sjmallett info.group_index = 0; 192215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 193215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 194215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 195215976Sjmallett info.func = __cvmx_error_display; 196215976Sjmallett info.user_info = (long) 197215976Sjmallett "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n" 198215976Sjmallett " If SW attempts to write to the MIX_ORING2[ODBELL]\n" 199215976Sjmallett " with a value greater than the remaining #of\n" 200215976Sjmallett " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n" 201215976Sjmallett " the following occurs:\n" 202215976Sjmallett " 1) The MIX_ORING2[ODBELL] write is IGNORED\n" 203215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 204215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 205215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 206215976Sjmallett " and the local interrupt mask bit(OVFENA) is set, than an\n" 207215976Sjmallett " interrupt is reported for this event.\n" 208215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 209215976Sjmallett " (ie: cumulative # of ODBELL writes), and ensure that\n" 210215976Sjmallett " future ODBELL writes don't exceed the size of the\n" 211215976Sjmallett " O-Ring Buffer (MIX_ORING2[OSIZE]).\n" 212215976Sjmallett " SW must reclaim O-Ring Entries by writing to the\n" 213215976Sjmallett " MIX_ORCNT[ORCNT]. .\n" 214215976Sjmallett " NOTE: There is no recovery from an ODBLOVF Interrupt.\n" 215215976Sjmallett " If it occurs, it's an indication that SW has\n" 216215976Sjmallett " overwritten the O-Ring buffer, and the only recourse\n" 217215976Sjmallett " is a HW reset.\n"; 218215976Sjmallett fail |= cvmx_error_add(&info); 219215976Sjmallett 220215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 221215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 222215976Sjmallett info.status_mask = 1ull<<1 /* idblovf */; 223215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 224215976Sjmallett info.enable_mask = 1ull<<1 /* ivfena */; 225215976Sjmallett info.flags = 0; 226215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 227215976Sjmallett info.group_index = 0; 228215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 229215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 230215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 231215976Sjmallett info.func = __cvmx_error_display; 232215976Sjmallett info.user_info = (long) 233215976Sjmallett "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n" 234215976Sjmallett " If SW attempts to write to the MIX_IRING2[IDBELL]\n" 235215976Sjmallett " with a value greater than the remaining #of\n" 236215976Sjmallett " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n" 237215976Sjmallett " the following occurs:\n" 238215976Sjmallett " 1) The MIX_IRING2[IDBELL] write is IGNORED\n" 239215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 240215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 241215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 242215976Sjmallett " and the local interrupt mask bit(IVFENA) is set, than an\n" 243215976Sjmallett " interrupt is reported for this event.\n" 244215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 245215976Sjmallett " (ie: cumulative # of IDBELL writes), and ensure that\n" 246215976Sjmallett " future IDBELL writes don't exceed the size of the\n" 247215976Sjmallett " I-Ring Buffer (MIX_IRING2[ISIZE]).\n" 248215976Sjmallett " SW must reclaim I-Ring Entries by keeping track of the\n" 249215976Sjmallett " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n" 250215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] register represents the\n" 251215976Sjmallett " total #packets(not IRing Entries) and SW must further\n" 252215976Sjmallett " keep track of the # of I-Ring Entries associated with\n" 253215976Sjmallett " each packet as they are processed.\n" 254215976Sjmallett " NOTE: There is no recovery from an IDBLOVF Interrupt.\n" 255215976Sjmallett " If it occurs, it's an indication that SW has\n" 256215976Sjmallett " overwritten the I-Ring buffer, and the only recourse\n" 257215976Sjmallett " is a HW reset.\n"; 258215976Sjmallett fail |= cvmx_error_add(&info); 259215976Sjmallett 260215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 261215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 262215976Sjmallett info.status_mask = 1ull<<4 /* data_drp */; 263215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 264215976Sjmallett info.enable_mask = 1ull<<4 /* data_drpena */; 265215976Sjmallett info.flags = 0; 266215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 267215976Sjmallett info.group_index = 0; 268215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 269215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 270215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 271215976Sjmallett info.func = __cvmx_error_display; 272215976Sjmallett info.user_info = (long) 273215976Sjmallett "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n" 274215976Sjmallett " If this does occur, the DATA_DRP is set and the\n" 275215976Sjmallett " CIU_INTx_SUM0,4[MII] bits are set.\n" 276215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 277215976Sjmallett " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n" 278215976Sjmallett " interrupt is reported for this event.\n"; 279215976Sjmallett fail |= cvmx_error_add(&info); 280215976Sjmallett 281215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 282215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 283215976Sjmallett info.status_mask = 1ull<<5 /* irun */; 284215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 285215976Sjmallett info.enable_mask = 1ull<<5 /* irunena */; 286215976Sjmallett info.flags = 0; 287215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 288215976Sjmallett info.group_index = 0; 289215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 290215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 291215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 292215976Sjmallett info.func = __cvmx_error_display; 293215976Sjmallett info.user_info = (long) 294215976Sjmallett "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n" 295215976Sjmallett " If SW writes a larger value than what is currently\n" 296215976Sjmallett " in the MIX_IRCNT[IRCNT], then HW will report the\n" 297215976Sjmallett " underflow condition.\n" 298215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n" 299215976Sjmallett " NOTE: If an IRUN underflow condition is detected,\n" 300215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 301215976Sjmallett " been compromised. To recover, SW must issue a\n" 302215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 303215976Sjmallett fail |= cvmx_error_add(&info); 304215976Sjmallett 305215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 306215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 307215976Sjmallett info.status_mask = 1ull<<6 /* orun */; 308215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 309215976Sjmallett info.enable_mask = 1ull<<6 /* orunena */; 310215976Sjmallett info.flags = 0; 311215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 312215976Sjmallett info.group_index = 0; 313215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 314215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 315215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 316215976Sjmallett info.func = __cvmx_error_display; 317215976Sjmallett info.user_info = (long) 318215976Sjmallett "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n" 319215976Sjmallett " If SW writes a larger value than what is currently\n" 320215976Sjmallett " in the MIX_ORCNT[ORCNT], then HW will report the\n" 321215976Sjmallett " underflow condition.\n" 322215976Sjmallett " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n" 323215976Sjmallett " NOTE: If an ORUN underflow condition is detected,\n" 324215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 325215976Sjmallett " been compromised. To recover, SW must issue a\n" 326215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 327215976Sjmallett fail |= cvmx_error_add(&info); 328215976Sjmallett 329215976Sjmallett /* CVMX_CIU_INT_SUM1 */ 330215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 331215976Sjmallett info.status_addr = CVMX_CIU_INT_SUM1; 332215976Sjmallett info.status_mask = 0; 333215976Sjmallett info.enable_addr = 0; 334215976Sjmallett info.enable_mask = 0; 335215976Sjmallett info.flags = 0; 336215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 337215976Sjmallett info.group_index = 0; 338215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 339215976Sjmallett info.parent.status_addr = 0; 340215976Sjmallett info.parent.status_mask = 0; 341215976Sjmallett info.func = __cvmx_error_decode; 342215976Sjmallett info.user_info = 0; 343215976Sjmallett fail |= cvmx_error_add(&info); 344215976Sjmallett 345215976Sjmallett /* CVMX_MIXX_ISR(1) */ 346215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 347215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 348215976Sjmallett info.status_mask = 1ull<<0 /* odblovf */; 349215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 350215976Sjmallett info.enable_mask = 1ull<<0 /* ovfena */; 351215976Sjmallett info.flags = 0; 352215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 353215976Sjmallett info.group_index = 1; 354215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 355215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 356215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 357215976Sjmallett info.func = __cvmx_error_display; 358215976Sjmallett info.user_info = (long) 359215976Sjmallett "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n" 360215976Sjmallett " If SW attempts to write to the MIX_ORING2[ODBELL]\n" 361215976Sjmallett " with a value greater than the remaining #of\n" 362215976Sjmallett " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n" 363215976Sjmallett " the following occurs:\n" 364215976Sjmallett " 1) The MIX_ORING2[ODBELL] write is IGNORED\n" 365215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 366215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 367215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 368215976Sjmallett " and the local interrupt mask bit(OVFENA) is set, than an\n" 369215976Sjmallett " interrupt is reported for this event.\n" 370215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 371215976Sjmallett " (ie: cumulative # of ODBELL writes), and ensure that\n" 372215976Sjmallett " future ODBELL writes don't exceed the size of the\n" 373215976Sjmallett " O-Ring Buffer (MIX_ORING2[OSIZE]).\n" 374215976Sjmallett " SW must reclaim O-Ring Entries by writing to the\n" 375215976Sjmallett " MIX_ORCNT[ORCNT]. .\n" 376215976Sjmallett " NOTE: There is no recovery from an ODBLOVF Interrupt.\n" 377215976Sjmallett " If it occurs, it's an indication that SW has\n" 378215976Sjmallett " overwritten the O-Ring buffer, and the only recourse\n" 379215976Sjmallett " is a HW reset.\n"; 380215976Sjmallett fail |= cvmx_error_add(&info); 381215976Sjmallett 382215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 383215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 384215976Sjmallett info.status_mask = 1ull<<1 /* idblovf */; 385215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 386215976Sjmallett info.enable_mask = 1ull<<1 /* ivfena */; 387215976Sjmallett info.flags = 0; 388215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 389215976Sjmallett info.group_index = 1; 390215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 391215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 392215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 393215976Sjmallett info.func = __cvmx_error_display; 394215976Sjmallett info.user_info = (long) 395215976Sjmallett "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n" 396215976Sjmallett " If SW attempts to write to the MIX_IRING2[IDBELL]\n" 397215976Sjmallett " with a value greater than the remaining #of\n" 398215976Sjmallett " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n" 399215976Sjmallett " the following occurs:\n" 400215976Sjmallett " 1) The MIX_IRING2[IDBELL] write is IGNORED\n" 401215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 402215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 403215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 404215976Sjmallett " and the local interrupt mask bit(IVFENA) is set, than an\n" 405215976Sjmallett " interrupt is reported for this event.\n" 406215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 407215976Sjmallett " (ie: cumulative # of IDBELL writes), and ensure that\n" 408215976Sjmallett " future IDBELL writes don't exceed the size of the\n" 409215976Sjmallett " I-Ring Buffer (MIX_IRING2[ISIZE]).\n" 410215976Sjmallett " SW must reclaim I-Ring Entries by keeping track of the\n" 411215976Sjmallett " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n" 412215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] register represents the\n" 413215976Sjmallett " total #packets(not IRing Entries) and SW must further\n" 414215976Sjmallett " keep track of the # of I-Ring Entries associated with\n" 415215976Sjmallett " each packet as they are processed.\n" 416215976Sjmallett " NOTE: There is no recovery from an IDBLOVF Interrupt.\n" 417215976Sjmallett " If it occurs, it's an indication that SW has\n" 418215976Sjmallett " overwritten the I-Ring buffer, and the only recourse\n" 419215976Sjmallett " is a HW reset.\n"; 420215976Sjmallett fail |= cvmx_error_add(&info); 421215976Sjmallett 422215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 423215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 424215976Sjmallett info.status_mask = 1ull<<4 /* data_drp */; 425215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 426215976Sjmallett info.enable_mask = 1ull<<4 /* data_drpena */; 427215976Sjmallett info.flags = 0; 428215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 429215976Sjmallett info.group_index = 1; 430215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 431215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 432215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 433215976Sjmallett info.func = __cvmx_error_display; 434215976Sjmallett info.user_info = (long) 435215976Sjmallett "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n" 436215976Sjmallett " If this does occur, the DATA_DRP is set and the\n" 437215976Sjmallett " CIU_INTx_SUM0,4[MII] bits are set.\n" 438215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 439215976Sjmallett " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n" 440215976Sjmallett " interrupt is reported for this event.\n"; 441215976Sjmallett fail |= cvmx_error_add(&info); 442215976Sjmallett 443215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 444215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 445215976Sjmallett info.status_mask = 1ull<<5 /* irun */; 446215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 447215976Sjmallett info.enable_mask = 1ull<<5 /* irunena */; 448215976Sjmallett info.flags = 0; 449215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 450215976Sjmallett info.group_index = 1; 451215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 452215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 453215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 454215976Sjmallett info.func = __cvmx_error_display; 455215976Sjmallett info.user_info = (long) 456215976Sjmallett "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n" 457215976Sjmallett " If SW writes a larger value than what is currently\n" 458215976Sjmallett " in the MIX_IRCNT[IRCNT], then HW will report the\n" 459215976Sjmallett " underflow condition.\n" 460215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n" 461215976Sjmallett " NOTE: If an IRUN underflow condition is detected,\n" 462215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 463215976Sjmallett " been compromised. To recover, SW must issue a\n" 464215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 465215976Sjmallett fail |= cvmx_error_add(&info); 466215976Sjmallett 467215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 468215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 469215976Sjmallett info.status_mask = 1ull<<6 /* orun */; 470215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 471215976Sjmallett info.enable_mask = 1ull<<6 /* orunena */; 472215976Sjmallett info.flags = 0; 473215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 474215976Sjmallett info.group_index = 1; 475215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 476215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 477215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 478215976Sjmallett info.func = __cvmx_error_display; 479215976Sjmallett info.user_info = (long) 480215976Sjmallett "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n" 481215976Sjmallett " If SW writes a larger value than what is currently\n" 482215976Sjmallett " in the MIX_ORCNT[ORCNT], then HW will report the\n" 483215976Sjmallett " underflow condition.\n" 484215976Sjmallett " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n" 485215976Sjmallett " NOTE: If an ORUN underflow condition is detected,\n" 486215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 487215976Sjmallett " been compromised. To recover, SW must issue a\n" 488215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 489215976Sjmallett fail |= cvmx_error_add(&info); 490215976Sjmallett 491215976Sjmallett /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */ 492215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 493215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 494215976Sjmallett info.status_mask = 0; 495215976Sjmallett info.enable_addr = 0; 496215976Sjmallett info.enable_mask = 0; 497215976Sjmallett info.flags = 0; 498215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 499215976Sjmallett info.group_index = 0; 500215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 501215976Sjmallett info.parent.status_addr = 0; 502215976Sjmallett info.parent.status_mask = 0; 503215976Sjmallett info.func = __cvmx_error_decode; 504215976Sjmallett info.user_info = 0; 505215976Sjmallett fail |= cvmx_error_add(&info); 506215976Sjmallett 507215976Sjmallett /* CVMX_L2C_INT_STAT */ 508215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 509215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 510215976Sjmallett info.status_mask = 1ull<<3 /* l2tsec */; 511215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 512215976Sjmallett info.enable_mask = 1ull<<3 /* l2tsecen */; 513215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 514215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 515215976Sjmallett info.group_index = 0; 516215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 517215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 518215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 519215976Sjmallett info.func = __cvmx_error_display; 520215976Sjmallett info.user_info = (long) 521215976Sjmallett "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n" 522215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 523215976Sjmallett " given index) are checked for single bit errors(SBEs).\n" 524215976Sjmallett " This bit is set if ANY of the 8 sets contains an SBE.\n" 525215976Sjmallett " SBEs are auto corrected in HW and generate an\n" 526215976Sjmallett " interrupt(if enabled).\n" 527215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n"; 528215976Sjmallett fail |= cvmx_error_add(&info); 529215976Sjmallett 530215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 531215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 532215976Sjmallett info.status_mask = 1ull<<5 /* l2dsec */; 533215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 534215976Sjmallett info.enable_mask = 1ull<<5 /* l2dsecen */; 535215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 536215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 537215976Sjmallett info.group_index = 0; 538215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 539215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 540215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 541215976Sjmallett info.func = __cvmx_error_display; 542215976Sjmallett info.user_info = (long) 543215976Sjmallett "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n" 544215976Sjmallett " NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n"; 545215976Sjmallett fail |= cvmx_error_add(&info); 546215976Sjmallett 547215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 548215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 549215976Sjmallett info.status_mask = 1ull<<0 /* oob1 */; 550215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 551215976Sjmallett info.enable_mask = 1ull<<0 /* oob1en */; 552215976Sjmallett info.flags = 0; 553215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 554215976Sjmallett info.group_index = 0; 555215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 556215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 557215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 558215976Sjmallett info.func = __cvmx_error_display; 559215976Sjmallett info.user_info = (long) 560215976Sjmallett "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n"; 561215976Sjmallett fail |= cvmx_error_add(&info); 562215976Sjmallett 563215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 564215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 565215976Sjmallett info.status_mask = 1ull<<1 /* oob2 */; 566215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 567215976Sjmallett info.enable_mask = 1ull<<1 /* oob2en */; 568215976Sjmallett info.flags = 0; 569215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 570215976Sjmallett info.group_index = 0; 571215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 572215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 573215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 574215976Sjmallett info.func = __cvmx_error_display; 575215976Sjmallett info.user_info = (long) 576215976Sjmallett "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n"; 577215976Sjmallett fail |= cvmx_error_add(&info); 578215976Sjmallett 579215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 580215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 581215976Sjmallett info.status_mask = 1ull<<2 /* oob3 */; 582215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 583215976Sjmallett info.enable_mask = 1ull<<2 /* oob3en */; 584215976Sjmallett info.flags = 0; 585215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 586215976Sjmallett info.group_index = 0; 587215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 588215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 589215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 590215976Sjmallett info.func = __cvmx_error_display; 591215976Sjmallett info.user_info = (long) 592215976Sjmallett "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n"; 593215976Sjmallett fail |= cvmx_error_add(&info); 594215976Sjmallett 595215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 596215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 597215976Sjmallett info.status_mask = 1ull<<4 /* l2tded */; 598215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 599215976Sjmallett info.enable_mask = 1ull<<4 /* l2tdeden */; 600215976Sjmallett info.flags = 0; 601215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 602215976Sjmallett info.group_index = 0; 603215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 604215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 605215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 606215976Sjmallett info.func = __cvmx_error_display; 607215976Sjmallett info.user_info = (long) 608215976Sjmallett "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n" 609215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 610215976Sjmallett " given index) are checked for double bit errors(DBEs).\n" 611215976Sjmallett " This bit is set if ANY of the 8 sets contains a DBE.\n" 612215976Sjmallett " DBEs also generated an interrupt(if enabled).\n" 613215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n"; 614215976Sjmallett fail |= cvmx_error_add(&info); 615215976Sjmallett 616215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 617215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 618215976Sjmallett info.status_mask = 1ull<<6 /* l2dded */; 619215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 620215976Sjmallett info.enable_mask = 1ull<<6 /* l2ddeden */; 621215976Sjmallett info.flags = 0; 622215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 623215976Sjmallett info.group_index = 0; 624215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 625215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 626215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 627215976Sjmallett info.func = __cvmx_error_display; 628215976Sjmallett info.user_info = (long) 629215976Sjmallett "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n" 630215976Sjmallett " NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n"; 631215976Sjmallett fail |= cvmx_error_add(&info); 632215976Sjmallett 633215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 634215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 635215976Sjmallett info.status_mask = 1ull<<7 /* lck */; 636215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 637215976Sjmallett info.enable_mask = 1ull<<7 /* lckena */; 638215976Sjmallett info.flags = 0; 639215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 640215976Sjmallett info.group_index = 0; 641215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 642215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 643215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 644215976Sjmallett info.func = __cvmx_error_display; 645215976Sjmallett info.user_info = (long) 646215976Sjmallett "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n" 647215976Sjmallett " the INDEX (which is ignored by HW - but reported to SW).\n" 648215976Sjmallett " The LDD(L1 load-miss) for the LOCK operation is completed\n" 649215976Sjmallett " successfully, however the address is NOT locked.\n" 650215976Sjmallett " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n" 651215976Sjmallett " into account. For example, if diagnostic PPx has\n" 652215976Sjmallett " UMSKx defined to only use SETs [1:0], and SET1 had\n" 653215976Sjmallett " been previously LOCKED, then an attempt to LOCK the\n" 654215976Sjmallett " last available SET0 would result in a LCKERR. (This\n" 655215976Sjmallett " is to ensure that at least 1 SET at each INDEX is\n" 656215976Sjmallett " not LOCKED for general use by other PPs).\n" 657215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n"; 658215976Sjmallett fail |= cvmx_error_add(&info); 659215976Sjmallett 660215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 661215976Sjmallett info.status_addr = CVMX_L2C_INT_STAT; 662215976Sjmallett info.status_mask = 1ull<<8 /* lck2 */; 663215976Sjmallett info.enable_addr = CVMX_L2C_INT_EN; 664215976Sjmallett info.enable_mask = 1ull<<8 /* lck2ena */; 665215976Sjmallett info.flags = 0; 666215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 667215976Sjmallett info.group_index = 0; 668215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 669215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 670215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 671215976Sjmallett info.func = __cvmx_error_display; 672215976Sjmallett info.user_info = (long) 673215976Sjmallett "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n" 674215976Sjmallett " could not find an available/unlocked set (for\n" 675215976Sjmallett " replacement).\n" 676215976Sjmallett " Most likely, this is a result of SW mixing SET\n" 677215976Sjmallett " PARTITIONING with ADDRESS LOCKING. If SW allows\n" 678215976Sjmallett " another PP to LOCKDOWN all SETs available to PP#n,\n" 679215976Sjmallett " then a Rd/Wr Miss from PP#n will be unable\n" 680215976Sjmallett " to determine a 'valid' replacement set (since LOCKED\n" 681215976Sjmallett " addresses should NEVER be replaced).\n" 682215976Sjmallett " If such an event occurs, the HW will select the smallest\n" 683215976Sjmallett " available SET(specified by UMSK'x)' as the replacement\n" 684215976Sjmallett " set, and the address is unlocked.\n" 685215976Sjmallett " NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n"; 686215976Sjmallett fail |= cvmx_error_add(&info); 687215976Sjmallett 688215976Sjmallett /* CVMX_L2D_ERR */ 689215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 690215976Sjmallett info.status_addr = CVMX_L2D_ERR; 691215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 692215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 693215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 694215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 695215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 696215976Sjmallett info.group_index = 0; 697215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 698215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 699215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 700215976Sjmallett info.func = __cvmx_error_handle_l2d_err_sec_err; 701215976Sjmallett info.user_info = (long) 702215976Sjmallett "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n"; 703215976Sjmallett fail |= cvmx_error_add(&info); 704215976Sjmallett 705215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 706215976Sjmallett info.status_addr = CVMX_L2D_ERR; 707215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 708215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 709215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 710215976Sjmallett info.flags = 0; 711215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 712215976Sjmallett info.group_index = 0; 713215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 714215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 715215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 716215976Sjmallett info.func = __cvmx_error_handle_l2d_err_ded_err; 717215976Sjmallett info.user_info = (long) 718215976Sjmallett "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n"; 719215976Sjmallett fail |= cvmx_error_add(&info); 720215976Sjmallett 721215976Sjmallett /* CVMX_L2T_ERR */ 722215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 723215976Sjmallett info.status_addr = CVMX_L2T_ERR; 724215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 725215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 726215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 727215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 728215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 729215976Sjmallett info.group_index = 0; 730215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 731215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 732215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 733215976Sjmallett info.func = __cvmx_error_handle_l2t_err_sec_err; 734215976Sjmallett info.user_info = (long) 735215976Sjmallett "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n" 736215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 737215976Sjmallett " given index) are checked for single bit errors(SBEs).\n" 738215976Sjmallett " This bit is set if ANY of the 8 sets contains an SBE.\n" 739215976Sjmallett " SBEs are auto corrected in HW and generate an\n" 740215976Sjmallett " interrupt(if enabled).\n"; 741215976Sjmallett fail |= cvmx_error_add(&info); 742215976Sjmallett 743215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 744215976Sjmallett info.status_addr = CVMX_L2T_ERR; 745215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 746215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 747215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 748215976Sjmallett info.flags = 0; 749215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 750215976Sjmallett info.group_index = 0; 751215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 752215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 753215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 754215976Sjmallett info.func = __cvmx_error_handle_l2t_err_ded_err; 755215976Sjmallett info.user_info = (long) 756215976Sjmallett "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n" 757215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 758215976Sjmallett " given index) are checked for double bit errors(DBEs).\n" 759215976Sjmallett " This bit is set if ANY of the 8 sets contains a DBE.\n" 760215976Sjmallett " DBEs also generated an interrupt(if enabled).\n"; 761215976Sjmallett fail |= cvmx_error_add(&info); 762215976Sjmallett 763215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 764215976Sjmallett info.status_addr = CVMX_L2T_ERR; 765215976Sjmallett info.status_mask = 1ull<<24 /* lckerr */; 766215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 767215976Sjmallett info.enable_mask = 1ull<<25 /* lck_intena */; 768215976Sjmallett info.flags = 0; 769215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 770215976Sjmallett info.group_index = 0; 771215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 772215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 773215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 774215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr; 775215976Sjmallett info.user_info = (long) 776215976Sjmallett "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n" 777215976Sjmallett " the INDEX (which is ignored by HW - but reported to SW).\n" 778215976Sjmallett " The LDD(L1 load-miss) for the LOCK operation is completed\n" 779215976Sjmallett " successfully, however the address is NOT locked.\n" 780215976Sjmallett " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n" 781215976Sjmallett " into account. For example, if diagnostic PPx has\n" 782215976Sjmallett " UMSKx defined to only use SETs [1:0], and SET1 had\n" 783215976Sjmallett " been previously LOCKED, then an attempt to LOCK the\n" 784215976Sjmallett " last available SET0 would result in a LCKERR. (This\n" 785215976Sjmallett " is to ensure that at least 1 SET at each INDEX is\n" 786215976Sjmallett " not LOCKED for general use by other PPs).\n"; 787215976Sjmallett fail |= cvmx_error_add(&info); 788215976Sjmallett 789215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 790215976Sjmallett info.status_addr = CVMX_L2T_ERR; 791215976Sjmallett info.status_mask = 1ull<<26 /* lckerr2 */; 792215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 793215976Sjmallett info.enable_mask = 1ull<<27 /* lck_intena2 */; 794215976Sjmallett info.flags = 0; 795215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 796215976Sjmallett info.group_index = 0; 797215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 798215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 799215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 800215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr2; 801215976Sjmallett info.user_info = (long) 802215976Sjmallett "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n" 803215976Sjmallett " could not find an available/unlocked set (for\n" 804215976Sjmallett " replacement).\n" 805215976Sjmallett " Most likely, this is a result of SW mixing SET\n" 806215976Sjmallett " PARTITIONING with ADDRESS LOCKING. If SW allows\n" 807215976Sjmallett " another PP to LOCKDOWN all SETs available to PP#n,\n" 808215976Sjmallett " then a Rd/Wr Miss from PP#n will be unable\n" 809215976Sjmallett " to determine a 'valid' replacement set (since LOCKED\n" 810215976Sjmallett " addresses should NEVER be replaced).\n" 811215976Sjmallett " If such an event occurs, the HW will select the smallest\n" 812215976Sjmallett " available SET(specified by UMSK'x)' as the replacement\n" 813215976Sjmallett " set, and the address is unlocked.\n"; 814215976Sjmallett fail |= cvmx_error_add(&info); 815215976Sjmallett 816215976Sjmallett /* CVMX_AGL_GMX_BAD_REG */ 817215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 818215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 819215976Sjmallett info.status_mask = 1ull<<32 /* ovrflw */; 820215976Sjmallett info.enable_addr = 0; 821215976Sjmallett info.enable_mask = 0; 822215976Sjmallett info.flags = 0; 823215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 824215976Sjmallett info.group_index = 0; 825215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 826215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 827215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 828215976Sjmallett info.func = __cvmx_error_display; 829215976Sjmallett info.user_info = (long) 830215976Sjmallett "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n"; 831215976Sjmallett fail |= cvmx_error_add(&info); 832215976Sjmallett 833215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 834215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 835215976Sjmallett info.status_mask = 1ull<<33 /* txpop */; 836215976Sjmallett info.enable_addr = 0; 837215976Sjmallett info.enable_mask = 0; 838215976Sjmallett info.flags = 0; 839215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 840215976Sjmallett info.group_index = 0; 841215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 842215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 843215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 844215976Sjmallett info.func = __cvmx_error_display; 845215976Sjmallett info.user_info = (long) 846215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n"; 847215976Sjmallett fail |= cvmx_error_add(&info); 848215976Sjmallett 849215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 850215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 851215976Sjmallett info.status_mask = 1ull<<34 /* txpsh */; 852215976Sjmallett info.enable_addr = 0; 853215976Sjmallett info.enable_mask = 0; 854215976Sjmallett info.flags = 0; 855215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 856215976Sjmallett info.group_index = 0; 857215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 858215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 859215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 860215976Sjmallett info.func = __cvmx_error_display; 861215976Sjmallett info.user_info = (long) 862215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n"; 863215976Sjmallett fail |= cvmx_error_add(&info); 864215976Sjmallett 865215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 866215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 867215976Sjmallett info.status_mask = 1ull<<35 /* ovrflw1 */; 868215976Sjmallett info.enable_addr = 0; 869215976Sjmallett info.enable_mask = 0; 870215976Sjmallett info.flags = 0; 871215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 872215976Sjmallett info.group_index = 0; 873215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 874215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 875215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 876215976Sjmallett info.func = __cvmx_error_display; 877215976Sjmallett info.user_info = (long) 878215976Sjmallett "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n"; 879215976Sjmallett fail |= cvmx_error_add(&info); 880215976Sjmallett 881215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 882215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 883215976Sjmallett info.status_mask = 1ull<<36 /* txpop1 */; 884215976Sjmallett info.enable_addr = 0; 885215976Sjmallett info.enable_mask = 0; 886215976Sjmallett info.flags = 0; 887215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 888215976Sjmallett info.group_index = 0; 889215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 890215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 891215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 892215976Sjmallett info.func = __cvmx_error_display; 893215976Sjmallett info.user_info = (long) 894215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n"; 895215976Sjmallett fail |= cvmx_error_add(&info); 896215976Sjmallett 897215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 898215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 899215976Sjmallett info.status_mask = 1ull<<37 /* txpsh1 */; 900215976Sjmallett info.enable_addr = 0; 901215976Sjmallett info.enable_mask = 0; 902215976Sjmallett info.flags = 0; 903215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 904215976Sjmallett info.group_index = 0; 905215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 906215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 907215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 908215976Sjmallett info.func = __cvmx_error_display; 909215976Sjmallett info.user_info = (long) 910215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n"; 911215976Sjmallett fail |= cvmx_error_add(&info); 912215976Sjmallett 913215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 914215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 915215976Sjmallett info.status_mask = 0x3ull<<2 /* out_ovr */; 916215976Sjmallett info.enable_addr = 0; 917215976Sjmallett info.enable_mask = 0; 918215976Sjmallett info.flags = 0; 919215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 920215976Sjmallett info.group_index = 0; 921215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 922215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 923215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 924215976Sjmallett info.func = __cvmx_error_display; 925215976Sjmallett info.user_info = (long) 926215976Sjmallett "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n"; 927215976Sjmallett fail |= cvmx_error_add(&info); 928215976Sjmallett 929215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 930215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 931215976Sjmallett info.status_mask = 1ull<<22 /* loststat */; 932215976Sjmallett info.enable_addr = 0; 933215976Sjmallett info.enable_mask = 0; 934215976Sjmallett info.flags = 0; 935215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 936215976Sjmallett info.group_index = 0; 937215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 938215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 939215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 940215976Sjmallett info.func = __cvmx_error_display; 941215976Sjmallett info.user_info = (long) 942215976Sjmallett "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n" 943215976Sjmallett " TX Stats are corrupted\n"; 944215976Sjmallett fail |= cvmx_error_add(&info); 945215976Sjmallett 946215976Sjmallett /* CVMX_AGL_GMX_RXX_INT_REG(0) */ 947215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 948215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0); 949215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 950215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0); 951215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 952215976Sjmallett info.flags = 0; 953215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 954215976Sjmallett info.group_index = 0; 955215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 956215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 957215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 958215976Sjmallett info.func = __cvmx_error_display; 959215976Sjmallett info.user_info = (long) 960215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n"; 961215976Sjmallett fail |= cvmx_error_add(&info); 962215976Sjmallett 963215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 964215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0); 965215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 966215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0); 967215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 968215976Sjmallett info.flags = 0; 969215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 970215976Sjmallett info.group_index = 0; 971215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 972215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 973215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 974215976Sjmallett info.func = __cvmx_error_display; 975215976Sjmallett info.user_info = (long) 976215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n" 977215976Sjmallett " This interrupt should never assert\n"; 978215976Sjmallett fail |= cvmx_error_add(&info); 979215976Sjmallett 980215976Sjmallett /* CVMX_AGL_GMX_RXX_INT_REG(1) */ 981215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 982215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1); 983215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 984215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1); 985215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 986215976Sjmallett info.flags = 0; 987215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 988215976Sjmallett info.group_index = 1; 989215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 990215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 991215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 992215976Sjmallett info.func = __cvmx_error_display; 993215976Sjmallett info.user_info = (long) 994215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n"; 995215976Sjmallett fail |= cvmx_error_add(&info); 996215976Sjmallett 997215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 998215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1); 999215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1000215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1); 1001215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1002215976Sjmallett info.flags = 0; 1003215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 1004215976Sjmallett info.group_index = 1; 1005215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1006215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1007215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 1008215976Sjmallett info.func = __cvmx_error_display; 1009215976Sjmallett info.user_info = (long) 1010215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n" 1011215976Sjmallett " This interrupt should never assert\n"; 1012215976Sjmallett fail |= cvmx_error_add(&info); 1013215976Sjmallett 1014215976Sjmallett /* CVMX_AGL_GMX_TX_INT_REG */ 1015215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1016215976Sjmallett info.status_addr = CVMX_AGL_GMX_TX_INT_REG; 1017215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 1018215976Sjmallett info.enable_addr = CVMX_AGL_GMX_TX_INT_EN; 1019215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 1020215976Sjmallett info.flags = 0; 1021215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 1022215976Sjmallett info.group_index = 0; 1023215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1024215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1025215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 1026215976Sjmallett info.func = __cvmx_error_display; 1027215976Sjmallett info.user_info = (long) 1028215976Sjmallett "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 1029215976Sjmallett fail |= cvmx_error_add(&info); 1030215976Sjmallett 1031215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1032215976Sjmallett info.status_addr = CVMX_AGL_GMX_TX_INT_REG; 1033215976Sjmallett info.status_mask = 0x3ull<<2 /* undflw */; 1034215976Sjmallett info.enable_addr = CVMX_AGL_GMX_TX_INT_EN; 1035215976Sjmallett info.enable_mask = 0x3ull<<2 /* undflw */; 1036215976Sjmallett info.flags = 0; 1037215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 1038215976Sjmallett info.group_index = 0; 1039215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1040215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1041215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 1042215976Sjmallett info.func = __cvmx_error_display; 1043215976Sjmallett info.user_info = (long) 1044215976Sjmallett "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n"; 1045215976Sjmallett fail |= cvmx_error_add(&info); 1046215976Sjmallett 1047215976Sjmallett /* CVMX_GMXX_BAD_REG(0) */ 1048215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1049215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1050215976Sjmallett info.status_mask = 0xfull<<2 /* out_ovr */; 1051215976Sjmallett info.enable_addr = 0; 1052215976Sjmallett info.enable_mask = 0; 1053215976Sjmallett info.flags = 0; 1054215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1055215976Sjmallett info.group_index = 0; 1056215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1057215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1058215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1059215976Sjmallett info.func = __cvmx_error_display; 1060215976Sjmallett info.user_info = (long) 1061215976Sjmallett "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 1062215976Sjmallett fail |= cvmx_error_add(&info); 1063215976Sjmallett 1064215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1065215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1066215976Sjmallett info.status_mask = 0xfull<<22 /* loststat */; 1067215976Sjmallett info.enable_addr = 0; 1068215976Sjmallett info.enable_mask = 0; 1069215976Sjmallett info.flags = 0; 1070215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1071215976Sjmallett info.group_index = 0; 1072215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1073215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1074215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1075215976Sjmallett info.func = __cvmx_error_display; 1076215976Sjmallett info.user_info = (long) 1077215976Sjmallett "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n" 1078215976Sjmallett " In SGMII, one bit per port\n" 1079215976Sjmallett " In XAUI, only port0 is used\n" 1080215976Sjmallett " TX Stats are corrupted\n"; 1081215976Sjmallett fail |= cvmx_error_add(&info); 1082215976Sjmallett 1083215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1084215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1085215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 1086215976Sjmallett info.enable_addr = 0; 1087215976Sjmallett info.enable_mask = 0; 1088215976Sjmallett info.flags = 0; 1089215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1090215976Sjmallett info.group_index = 0; 1091215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1092215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1093215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1094215976Sjmallett info.func = __cvmx_error_display; 1095215976Sjmallett info.user_info = (long) 1096215976Sjmallett "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n" 1097215976Sjmallett " The common FIFO to SGMII and XAUI had an overflow\n" 1098215976Sjmallett " TX Stats are corrupted\n"; 1099215976Sjmallett fail |= cvmx_error_add(&info); 1100215976Sjmallett 1101215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1102215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1103215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 1104215976Sjmallett info.enable_addr = 0; 1105215976Sjmallett info.enable_mask = 0; 1106215976Sjmallett info.flags = 0; 1107215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1108215976Sjmallett info.group_index = 0; 1109215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1110215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1111215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1112215976Sjmallett info.func = __cvmx_error_display; 1113215976Sjmallett info.user_info = (long) 1114215976Sjmallett "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 1115215976Sjmallett fail |= cvmx_error_add(&info); 1116215976Sjmallett 1117215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,0) */ 1118215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1119215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1120215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1121215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1122215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1123215976Sjmallett info.flags = 0; 1124215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1125215976Sjmallett info.group_index = 0; 1126215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1127215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1128215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1129215976Sjmallett info.func = __cvmx_error_display; 1130215976Sjmallett info.user_info = (long) 1131215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n" 1132215976Sjmallett " (SGMII/1000Base-X only)\n"; 1133215976Sjmallett fail |= cvmx_error_add(&info); 1134215976Sjmallett 1135215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1136215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1137215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1138215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1139215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1140215976Sjmallett info.flags = 0; 1141215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1142215976Sjmallett info.group_index = 0; 1143215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1144215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1145215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1146215976Sjmallett info.func = __cvmx_error_display; 1147215976Sjmallett info.user_info = (long) 1148215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n"; 1149215976Sjmallett fail |= cvmx_error_add(&info); 1150215976Sjmallett 1151215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1152215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1153215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1154215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1155215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1156215976Sjmallett info.flags = 0; 1157215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1158215976Sjmallett info.group_index = 0; 1159215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1160215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1161215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1162215976Sjmallett info.func = __cvmx_error_display; 1163215976Sjmallett info.user_info = (long) 1164215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1165215976Sjmallett " This interrupt should never assert\n" 1166215976Sjmallett " (SGMII/1000Base-X only)\n"; 1167215976Sjmallett fail |= cvmx_error_add(&info); 1168215976Sjmallett 1169215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1170215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1171215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1172215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1173215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1174215976Sjmallett info.flags = 0; 1175215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1176215976Sjmallett info.group_index = 0; 1177215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1178215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1179215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1180215976Sjmallett info.func = __cvmx_error_display; 1181215976Sjmallett info.user_info = (long) 1182215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1183215976Sjmallett " (XAUI Mode only)\n"; 1184215976Sjmallett fail |= cvmx_error_add(&info); 1185215976Sjmallett 1186215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1187215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1188215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1189215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1190215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1191215976Sjmallett info.flags = 0; 1192215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1193215976Sjmallett info.group_index = 0; 1194215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1195215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1196215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1197215976Sjmallett info.func = __cvmx_error_display; 1198215976Sjmallett info.user_info = (long) 1199215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1200215976Sjmallett " (XAUI Mode only)\n"; 1201215976Sjmallett fail |= cvmx_error_add(&info); 1202215976Sjmallett 1203215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1204215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1205215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1206215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1207215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1208215976Sjmallett info.flags = 0; 1209215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1210215976Sjmallett info.group_index = 0; 1211215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1212215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1213215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1214215976Sjmallett info.func = __cvmx_error_display; 1215215976Sjmallett info.user_info = (long) 1216215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1217215976Sjmallett " (XAUI Mode only)\n"; 1218215976Sjmallett fail |= cvmx_error_add(&info); 1219215976Sjmallett 1220215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1221215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1222215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1223215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1224215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1225215976Sjmallett info.flags = 0; 1226215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1227215976Sjmallett info.group_index = 0; 1228215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1229215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1230215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1231215976Sjmallett info.func = __cvmx_error_display; 1232215976Sjmallett info.user_info = (long) 1233215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n" 1234215976Sjmallett " than /T/. The error propagation control\n" 1235215976Sjmallett " character /E/ will be included as part of the\n" 1236215976Sjmallett " frame and does not cause a frame termination.\n" 1237215976Sjmallett " (XAUI Mode only)\n"; 1238215976Sjmallett fail |= cvmx_error_add(&info); 1239215976Sjmallett 1240215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1241215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1242215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1243215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1244215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1245215976Sjmallett info.flags = 0; 1246215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1247215976Sjmallett info.group_index = 0; 1248215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1249215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1250215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1251215976Sjmallett info.func = __cvmx_error_display; 1252215976Sjmallett info.user_info = (long) 1253215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n" 1254215976Sjmallett " (XAUI Mode only)\n"; 1255215976Sjmallett fail |= cvmx_error_add(&info); 1256215976Sjmallett 1257215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1258215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1259215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1260215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1261215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1262215976Sjmallett info.flags = 0; 1263215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1264215976Sjmallett info.group_index = 0; 1265215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1266215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1267215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1268215976Sjmallett info.func = __cvmx_error_display; 1269215976Sjmallett info.user_info = (long) 1270215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n" 1271215976Sjmallett " (XAUI Mode only)\n"; 1272215976Sjmallett fail |= cvmx_error_add(&info); 1273215976Sjmallett 1274215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1275215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1276215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1277215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1278215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1279215976Sjmallett info.flags = 0; 1280215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1281215976Sjmallett info.group_index = 0; 1282215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1283215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1284215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1285215976Sjmallett info.func = __cvmx_error_display; 1286215976Sjmallett info.user_info = (long) 1287215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n" 1288215976Sjmallett " (XAUI Mode only)\n"; 1289215976Sjmallett fail |= cvmx_error_add(&info); 1290215976Sjmallett 1291215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1292215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1293215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 1294215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1295215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 1296215976Sjmallett info.flags = 0; 1297215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1298215976Sjmallett info.group_index = 0; 1299215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1300215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1301215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1302215976Sjmallett info.func = __cvmx_error_display; 1303215976Sjmallett info.user_info = (long) 1304215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n" 1305215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 1306215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 1307215976Sjmallett " is the only defined type for HiGig2\n" 1308215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 1309215976Sjmallett " which is the only defined type for HiGig2\n" 1310215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 1311215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 1312215976Sjmallett " Those are the only two defined types in HiGig2\n"; 1313215976Sjmallett fail |= cvmx_error_add(&info); 1314215976Sjmallett 1315215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1316215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1317215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 1318215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1319215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 1320215976Sjmallett info.flags = 0; 1321215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1322215976Sjmallett info.group_index = 0; 1323215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1324215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1325215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1326215976Sjmallett info.func = __cvmx_error_display; 1327215976Sjmallett info.user_info = (long) 1328215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 1329215976Sjmallett " Set when either CRC8 error detected or when\n" 1330215976Sjmallett " a Control Character is found in the message\n" 1331215976Sjmallett " bytes after the K.SOM\n" 1332215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 1333215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 1334215976Sjmallett " getting set, will never set HG2FLD.\n"; 1335215976Sjmallett fail |= cvmx_error_add(&info); 1336215976Sjmallett 1337215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,0) */ 1338215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1339215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1340215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1341215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1342215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1343215976Sjmallett info.flags = 0; 1344215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1345215976Sjmallett info.group_index = 1; 1346215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1347215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1348215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1349215976Sjmallett info.func = __cvmx_error_display; 1350215976Sjmallett info.user_info = (long) 1351215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n" 1352215976Sjmallett " (SGMII/1000Base-X only)\n"; 1353215976Sjmallett fail |= cvmx_error_add(&info); 1354215976Sjmallett 1355215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1356215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1357215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1358215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1359215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1360215976Sjmallett info.flags = 0; 1361215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1362215976Sjmallett info.group_index = 1; 1363215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1364215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1365215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1366215976Sjmallett info.func = __cvmx_error_display; 1367215976Sjmallett info.user_info = (long) 1368215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n"; 1369215976Sjmallett fail |= cvmx_error_add(&info); 1370215976Sjmallett 1371215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1372215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1373215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1374215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1375215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1376215976Sjmallett info.flags = 0; 1377215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1378215976Sjmallett info.group_index = 1; 1379215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1380215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1381215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1382215976Sjmallett info.func = __cvmx_error_display; 1383215976Sjmallett info.user_info = (long) 1384215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1385215976Sjmallett " This interrupt should never assert\n" 1386215976Sjmallett " (SGMII/1000Base-X only)\n"; 1387215976Sjmallett fail |= cvmx_error_add(&info); 1388215976Sjmallett 1389215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1390215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1391215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1392215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1393215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1394215976Sjmallett info.flags = 0; 1395215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1396215976Sjmallett info.group_index = 1; 1397215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1398215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1399215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1400215976Sjmallett info.func = __cvmx_error_display; 1401215976Sjmallett info.user_info = (long) 1402215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1403215976Sjmallett " (XAUI Mode only)\n"; 1404215976Sjmallett fail |= cvmx_error_add(&info); 1405215976Sjmallett 1406215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1407215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1408215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1409215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1410215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1411215976Sjmallett info.flags = 0; 1412215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1413215976Sjmallett info.group_index = 1; 1414215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1415215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1416215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1417215976Sjmallett info.func = __cvmx_error_display; 1418215976Sjmallett info.user_info = (long) 1419215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1420215976Sjmallett " (XAUI Mode only)\n"; 1421215976Sjmallett fail |= cvmx_error_add(&info); 1422215976Sjmallett 1423215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1424215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1425215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1426215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1427215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1428215976Sjmallett info.flags = 0; 1429215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1430215976Sjmallett info.group_index = 1; 1431215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1432215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1433215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1434215976Sjmallett info.func = __cvmx_error_display; 1435215976Sjmallett info.user_info = (long) 1436215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1437215976Sjmallett " (XAUI Mode only)\n"; 1438215976Sjmallett fail |= cvmx_error_add(&info); 1439215976Sjmallett 1440215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1441215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1442215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1443215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1444215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1445215976Sjmallett info.flags = 0; 1446215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1447215976Sjmallett info.group_index = 1; 1448215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1449215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1450215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1451215976Sjmallett info.func = __cvmx_error_display; 1452215976Sjmallett info.user_info = (long) 1453215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n" 1454215976Sjmallett " than /T/. The error propagation control\n" 1455215976Sjmallett " character /E/ will be included as part of the\n" 1456215976Sjmallett " frame and does not cause a frame termination.\n" 1457215976Sjmallett " (XAUI Mode only)\n"; 1458215976Sjmallett fail |= cvmx_error_add(&info); 1459215976Sjmallett 1460215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1461215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1462215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1463215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1464215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1465215976Sjmallett info.flags = 0; 1466215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1467215976Sjmallett info.group_index = 1; 1468215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1469215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1470215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1471215976Sjmallett info.func = __cvmx_error_display; 1472215976Sjmallett info.user_info = (long) 1473215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n" 1474215976Sjmallett " (XAUI Mode only)\n"; 1475215976Sjmallett fail |= cvmx_error_add(&info); 1476215976Sjmallett 1477215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1478215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1479215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1480215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1481215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1482215976Sjmallett info.flags = 0; 1483215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1484215976Sjmallett info.group_index = 1; 1485215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1486215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1487215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1488215976Sjmallett info.func = __cvmx_error_display; 1489215976Sjmallett info.user_info = (long) 1490215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n" 1491215976Sjmallett " (XAUI Mode only)\n"; 1492215976Sjmallett fail |= cvmx_error_add(&info); 1493215976Sjmallett 1494215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1495215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1496215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1497215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1498215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1499215976Sjmallett info.flags = 0; 1500215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1501215976Sjmallett info.group_index = 1; 1502215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1503215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1504215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1505215976Sjmallett info.func = __cvmx_error_display; 1506215976Sjmallett info.user_info = (long) 1507215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n" 1508215976Sjmallett " (XAUI Mode only)\n"; 1509215976Sjmallett fail |= cvmx_error_add(&info); 1510215976Sjmallett 1511215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1512215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1513215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 1514215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1515215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 1516215976Sjmallett info.flags = 0; 1517215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1518215976Sjmallett info.group_index = 1; 1519215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1520215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1521215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1522215976Sjmallett info.func = __cvmx_error_display; 1523215976Sjmallett info.user_info = (long) 1524215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n" 1525215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 1526215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 1527215976Sjmallett " is the only defined type for HiGig2\n" 1528215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 1529215976Sjmallett " which is the only defined type for HiGig2\n" 1530215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 1531215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 1532215976Sjmallett " Those are the only two defined types in HiGig2\n"; 1533215976Sjmallett fail |= cvmx_error_add(&info); 1534215976Sjmallett 1535215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1536215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1537215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 1538215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1539215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 1540215976Sjmallett info.flags = 0; 1541215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1542215976Sjmallett info.group_index = 1; 1543215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1544215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1545215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1546215976Sjmallett info.func = __cvmx_error_display; 1547215976Sjmallett info.user_info = (long) 1548215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 1549215976Sjmallett " Set when either CRC8 error detected or when\n" 1550215976Sjmallett " a Control Character is found in the message\n" 1551215976Sjmallett " bytes after the K.SOM\n" 1552215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 1553215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 1554215976Sjmallett " getting set, will never set HG2FLD.\n"; 1555215976Sjmallett fail |= cvmx_error_add(&info); 1556215976Sjmallett 1557215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,0) */ 1558215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1559215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1560215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1561215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1562215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1563215976Sjmallett info.flags = 0; 1564215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1565215976Sjmallett info.group_index = 2; 1566215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1567215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1568215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1569215976Sjmallett info.func = __cvmx_error_display; 1570215976Sjmallett info.user_info = (long) 1571215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n" 1572215976Sjmallett " (SGMII/1000Base-X only)\n"; 1573215976Sjmallett fail |= cvmx_error_add(&info); 1574215976Sjmallett 1575215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1576215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1577215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1578215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1579215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1580215976Sjmallett info.flags = 0; 1581215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1582215976Sjmallett info.group_index = 2; 1583215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1584215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1585215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1586215976Sjmallett info.func = __cvmx_error_display; 1587215976Sjmallett info.user_info = (long) 1588215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n"; 1589215976Sjmallett fail |= cvmx_error_add(&info); 1590215976Sjmallett 1591215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1592215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1593215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1594215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1595215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1596215976Sjmallett info.flags = 0; 1597215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1598215976Sjmallett info.group_index = 2; 1599215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1600215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1601215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1602215976Sjmallett info.func = __cvmx_error_display; 1603215976Sjmallett info.user_info = (long) 1604215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1605215976Sjmallett " This interrupt should never assert\n" 1606215976Sjmallett " (SGMII/1000Base-X only)\n"; 1607215976Sjmallett fail |= cvmx_error_add(&info); 1608215976Sjmallett 1609215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1610215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1611215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1612215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1613215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1614215976Sjmallett info.flags = 0; 1615215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1616215976Sjmallett info.group_index = 2; 1617215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1618215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1619215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1620215976Sjmallett info.func = __cvmx_error_display; 1621215976Sjmallett info.user_info = (long) 1622215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1623215976Sjmallett " (XAUI Mode only)\n"; 1624215976Sjmallett fail |= cvmx_error_add(&info); 1625215976Sjmallett 1626215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1627215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1628215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1629215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1630215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1631215976Sjmallett info.flags = 0; 1632215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1633215976Sjmallett info.group_index = 2; 1634215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1635215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1636215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1637215976Sjmallett info.func = __cvmx_error_display; 1638215976Sjmallett info.user_info = (long) 1639215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1640215976Sjmallett " (XAUI Mode only)\n"; 1641215976Sjmallett fail |= cvmx_error_add(&info); 1642215976Sjmallett 1643215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1644215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1645215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1646215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1647215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1648215976Sjmallett info.flags = 0; 1649215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1650215976Sjmallett info.group_index = 2; 1651215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1652215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1653215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1654215976Sjmallett info.func = __cvmx_error_display; 1655215976Sjmallett info.user_info = (long) 1656215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1657215976Sjmallett " (XAUI Mode only)\n"; 1658215976Sjmallett fail |= cvmx_error_add(&info); 1659215976Sjmallett 1660215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1661215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1662215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1663215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1664215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1665215976Sjmallett info.flags = 0; 1666215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1667215976Sjmallett info.group_index = 2; 1668215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1669215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1670215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1671215976Sjmallett info.func = __cvmx_error_display; 1672215976Sjmallett info.user_info = (long) 1673215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n" 1674215976Sjmallett " than /T/. The error propagation control\n" 1675215976Sjmallett " character /E/ will be included as part of the\n" 1676215976Sjmallett " frame and does not cause a frame termination.\n" 1677215976Sjmallett " (XAUI Mode only)\n"; 1678215976Sjmallett fail |= cvmx_error_add(&info); 1679215976Sjmallett 1680215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1681215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1682215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1683215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1684215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1685215976Sjmallett info.flags = 0; 1686215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1687215976Sjmallett info.group_index = 2; 1688215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1689215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1690215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1691215976Sjmallett info.func = __cvmx_error_display; 1692215976Sjmallett info.user_info = (long) 1693215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n" 1694215976Sjmallett " (XAUI Mode only)\n"; 1695215976Sjmallett fail |= cvmx_error_add(&info); 1696215976Sjmallett 1697215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1698215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1699215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1700215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1701215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1702215976Sjmallett info.flags = 0; 1703215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1704215976Sjmallett info.group_index = 2; 1705215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1706215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1707215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1708215976Sjmallett info.func = __cvmx_error_display; 1709215976Sjmallett info.user_info = (long) 1710215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n" 1711215976Sjmallett " (XAUI Mode only)\n"; 1712215976Sjmallett fail |= cvmx_error_add(&info); 1713215976Sjmallett 1714215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1715215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1716215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1717215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1718215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1719215976Sjmallett info.flags = 0; 1720215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1721215976Sjmallett info.group_index = 2; 1722215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1723215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1724215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1725215976Sjmallett info.func = __cvmx_error_display; 1726215976Sjmallett info.user_info = (long) 1727215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n" 1728215976Sjmallett " (XAUI Mode only)\n"; 1729215976Sjmallett fail |= cvmx_error_add(&info); 1730215976Sjmallett 1731215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1732215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1733215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 1734215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1735215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 1736215976Sjmallett info.flags = 0; 1737215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1738215976Sjmallett info.group_index = 2; 1739215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1740215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1741215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1742215976Sjmallett info.func = __cvmx_error_display; 1743215976Sjmallett info.user_info = (long) 1744215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n" 1745215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 1746215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 1747215976Sjmallett " is the only defined type for HiGig2\n" 1748215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 1749215976Sjmallett " which is the only defined type for HiGig2\n" 1750215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 1751215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 1752215976Sjmallett " Those are the only two defined types in HiGig2\n"; 1753215976Sjmallett fail |= cvmx_error_add(&info); 1754215976Sjmallett 1755215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1756215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1757215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 1758215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1759215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 1760215976Sjmallett info.flags = 0; 1761215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1762215976Sjmallett info.group_index = 2; 1763215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1764215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1765215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1766215976Sjmallett info.func = __cvmx_error_display; 1767215976Sjmallett info.user_info = (long) 1768215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 1769215976Sjmallett " Set when either CRC8 error detected or when\n" 1770215976Sjmallett " a Control Character is found in the message\n" 1771215976Sjmallett " bytes after the K.SOM\n" 1772215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 1773215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 1774215976Sjmallett " getting set, will never set HG2FLD.\n"; 1775215976Sjmallett fail |= cvmx_error_add(&info); 1776215976Sjmallett 1777215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(3,0) */ 1778215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1779215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1780215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1781215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1782215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1783215976Sjmallett info.flags = 0; 1784215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1785215976Sjmallett info.group_index = 3; 1786215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1787215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1788215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1789215976Sjmallett info.func = __cvmx_error_display; 1790215976Sjmallett info.user_info = (long) 1791215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n" 1792215976Sjmallett " (SGMII/1000Base-X only)\n"; 1793215976Sjmallett fail |= cvmx_error_add(&info); 1794215976Sjmallett 1795215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1796215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1797215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1798215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1799215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1800215976Sjmallett info.flags = 0; 1801215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1802215976Sjmallett info.group_index = 3; 1803215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1804215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1805215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1806215976Sjmallett info.func = __cvmx_error_display; 1807215976Sjmallett info.user_info = (long) 1808215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n"; 1809215976Sjmallett fail |= cvmx_error_add(&info); 1810215976Sjmallett 1811215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1812215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1813215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1814215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1815215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1816215976Sjmallett info.flags = 0; 1817215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1818215976Sjmallett info.group_index = 3; 1819215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1820215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1821215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1822215976Sjmallett info.func = __cvmx_error_display; 1823215976Sjmallett info.user_info = (long) 1824215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1825215976Sjmallett " This interrupt should never assert\n" 1826215976Sjmallett " (SGMII/1000Base-X only)\n"; 1827215976Sjmallett fail |= cvmx_error_add(&info); 1828215976Sjmallett 1829215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1830215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1831215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 1832215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1833215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 1834215976Sjmallett info.flags = 0; 1835215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1836215976Sjmallett info.group_index = 3; 1837215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1838215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1839215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1840215976Sjmallett info.func = __cvmx_error_display; 1841215976Sjmallett info.user_info = (long) 1842215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 1843215976Sjmallett " (XAUI Mode only)\n"; 1844215976Sjmallett fail |= cvmx_error_add(&info); 1845215976Sjmallett 1846215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1847215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1848215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 1849215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1850215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 1851215976Sjmallett info.flags = 0; 1852215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1853215976Sjmallett info.group_index = 3; 1854215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1855215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1856215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1857215976Sjmallett info.func = __cvmx_error_display; 1858215976Sjmallett info.user_info = (long) 1859215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 1860215976Sjmallett " (XAUI Mode only)\n"; 1861215976Sjmallett fail |= cvmx_error_add(&info); 1862215976Sjmallett 1863215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1864215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1865215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 1866215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1867215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 1868215976Sjmallett info.flags = 0; 1869215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1870215976Sjmallett info.group_index = 3; 1871215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1872215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1873215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1874215976Sjmallett info.func = __cvmx_error_display; 1875215976Sjmallett info.user_info = (long) 1876215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 1877215976Sjmallett " (XAUI Mode only)\n"; 1878215976Sjmallett fail |= cvmx_error_add(&info); 1879215976Sjmallett 1880215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1881215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1882215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 1883215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1884215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 1885215976Sjmallett info.flags = 0; 1886215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1887215976Sjmallett info.group_index = 3; 1888215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1889215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1890215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1891215976Sjmallett info.func = __cvmx_error_display; 1892215976Sjmallett info.user_info = (long) 1893215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n" 1894215976Sjmallett " than /T/. The error propagation control\n" 1895215976Sjmallett " character /E/ will be included as part of the\n" 1896215976Sjmallett " frame and does not cause a frame termination.\n" 1897215976Sjmallett " (XAUI Mode only)\n"; 1898215976Sjmallett fail |= cvmx_error_add(&info); 1899215976Sjmallett 1900215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1901215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1902215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 1903215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1904215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 1905215976Sjmallett info.flags = 0; 1906215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1907215976Sjmallett info.group_index = 3; 1908215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1909215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1910215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1911215976Sjmallett info.func = __cvmx_error_display; 1912215976Sjmallett info.user_info = (long) 1913215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n" 1914215976Sjmallett " (XAUI Mode only)\n"; 1915215976Sjmallett fail |= cvmx_error_add(&info); 1916215976Sjmallett 1917215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1918215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1919215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 1920215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1921215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 1922215976Sjmallett info.flags = 0; 1923215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1924215976Sjmallett info.group_index = 3; 1925215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1926215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1927215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1928215976Sjmallett info.func = __cvmx_error_display; 1929215976Sjmallett info.user_info = (long) 1930215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n" 1931215976Sjmallett " (XAUI Mode only)\n"; 1932215976Sjmallett fail |= cvmx_error_add(&info); 1933215976Sjmallett 1934215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1935215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1936215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 1937215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1938215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 1939215976Sjmallett info.flags = 0; 1940215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1941215976Sjmallett info.group_index = 3; 1942215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1943215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1944215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1945215976Sjmallett info.func = __cvmx_error_display; 1946215976Sjmallett info.user_info = (long) 1947215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n" 1948215976Sjmallett " (XAUI Mode only)\n"; 1949215976Sjmallett fail |= cvmx_error_add(&info); 1950215976Sjmallett 1951215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1952215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1953215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 1954215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1955215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 1956215976Sjmallett info.flags = 0; 1957215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1958215976Sjmallett info.group_index = 3; 1959215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1960215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1961215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1962215976Sjmallett info.func = __cvmx_error_display; 1963215976Sjmallett info.user_info = (long) 1964215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n" 1965215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 1966215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 1967215976Sjmallett " is the only defined type for HiGig2\n" 1968215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 1969215976Sjmallett " which is the only defined type for HiGig2\n" 1970215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 1971215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 1972215976Sjmallett " Those are the only two defined types in HiGig2\n"; 1973215976Sjmallett fail |= cvmx_error_add(&info); 1974215976Sjmallett 1975215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1976215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 1977215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 1978215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 1979215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 1980215976Sjmallett info.flags = 0; 1981215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1982215976Sjmallett info.group_index = 3; 1983215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1984215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 1985215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1986215976Sjmallett info.func = __cvmx_error_display; 1987215976Sjmallett info.user_info = (long) 1988215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 1989215976Sjmallett " Set when either CRC8 error detected or when\n" 1990215976Sjmallett " a Control Character is found in the message\n" 1991215976Sjmallett " bytes after the K.SOM\n" 1992215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 1993215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 1994215976Sjmallett " getting set, will never set HG2FLD.\n"; 1995215976Sjmallett fail |= cvmx_error_add(&info); 1996215976Sjmallett 1997215976Sjmallett /* CVMX_GMXX_TX_INT_REG(0) */ 1998215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1999215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 2000215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 2001215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 2002215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 2003215976Sjmallett info.flags = 0; 2004215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2005215976Sjmallett info.group_index = 0; 2006215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2007215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2008215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2009215976Sjmallett info.func = __cvmx_error_display; 2010215976Sjmallett info.user_info = (long) 2011215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 2012215976Sjmallett fail |= cvmx_error_add(&info); 2013215976Sjmallett 2014215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2015215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 2016215976Sjmallett info.status_mask = 0xfull<<2 /* undflw */; 2017215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 2018215976Sjmallett info.enable_mask = 0xfull<<2 /* undflw */; 2019215976Sjmallett info.flags = 0; 2020215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2021215976Sjmallett info.group_index = 0; 2022215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2023215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2024215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2025215976Sjmallett info.func = __cvmx_error_display; 2026215976Sjmallett info.user_info = (long) 2027215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n"; 2028215976Sjmallett fail |= cvmx_error_add(&info); 2029215976Sjmallett 2030215976Sjmallett /* CVMX_MIO_BOOT_ERR */ 2031215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2032215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 2033215976Sjmallett info.status_mask = 1ull<<0 /* adr_err */; 2034215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 2035215976Sjmallett info.enable_mask = 1ull<<0 /* adr_int */; 2036215976Sjmallett info.flags = 0; 2037215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2038215976Sjmallett info.group_index = 0; 2039215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2040215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2041215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 2042215976Sjmallett info.func = __cvmx_error_display; 2043215976Sjmallett info.user_info = (long) 2044215976Sjmallett "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n"; 2045215976Sjmallett fail |= cvmx_error_add(&info); 2046215976Sjmallett 2047215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2048215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 2049215976Sjmallett info.status_mask = 1ull<<1 /* wait_err */; 2050215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 2051215976Sjmallett info.enable_mask = 1ull<<1 /* wait_int */; 2052215976Sjmallett info.flags = 0; 2053215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2054215976Sjmallett info.group_index = 0; 2055215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2056215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2057215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 2058215976Sjmallett info.func = __cvmx_error_display; 2059215976Sjmallett info.user_info = (long) 2060215976Sjmallett "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n"; 2061215976Sjmallett fail |= cvmx_error_add(&info); 2062215976Sjmallett 2063215976Sjmallett /* CVMX_IPD_INT_SUM */ 2064215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2065215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2066215976Sjmallett info.status_mask = 1ull<<0 /* prc_par0 */; 2067215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2068215976Sjmallett info.enable_mask = 1ull<<0 /* prc_par0 */; 2069215976Sjmallett info.flags = 0; 2070215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2071215976Sjmallett info.group_index = 0; 2072215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2073215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2074215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2075215976Sjmallett info.func = __cvmx_error_display; 2076215976Sjmallett info.user_info = (long) 2077215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n" 2078215976Sjmallett " [31:0] of the PBM memory.\n"; 2079215976Sjmallett fail |= cvmx_error_add(&info); 2080215976Sjmallett 2081215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2082215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2083215976Sjmallett info.status_mask = 1ull<<1 /* prc_par1 */; 2084215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2085215976Sjmallett info.enable_mask = 1ull<<1 /* prc_par1 */; 2086215976Sjmallett info.flags = 0; 2087215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2088215976Sjmallett info.group_index = 0; 2089215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2090215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2091215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2092215976Sjmallett info.func = __cvmx_error_display; 2093215976Sjmallett info.user_info = (long) 2094215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n" 2095215976Sjmallett " [63:32] of the PBM memory.\n"; 2096215976Sjmallett fail |= cvmx_error_add(&info); 2097215976Sjmallett 2098215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2099215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2100215976Sjmallett info.status_mask = 1ull<<2 /* prc_par2 */; 2101215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2102215976Sjmallett info.enable_mask = 1ull<<2 /* prc_par2 */; 2103215976Sjmallett info.flags = 0; 2104215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2105215976Sjmallett info.group_index = 0; 2106215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2107215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2108215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2109215976Sjmallett info.func = __cvmx_error_display; 2110215976Sjmallett info.user_info = (long) 2111215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n" 2112215976Sjmallett " [95:64] of the PBM memory.\n"; 2113215976Sjmallett fail |= cvmx_error_add(&info); 2114215976Sjmallett 2115215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2116215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2117215976Sjmallett info.status_mask = 1ull<<3 /* prc_par3 */; 2118215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2119215976Sjmallett info.enable_mask = 1ull<<3 /* prc_par3 */; 2120215976Sjmallett info.flags = 0; 2121215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2122215976Sjmallett info.group_index = 0; 2123215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2124215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2125215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2126215976Sjmallett info.func = __cvmx_error_display; 2127215976Sjmallett info.user_info = (long) 2128215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n" 2129215976Sjmallett " [127:96] of the PBM memory.\n"; 2130215976Sjmallett fail |= cvmx_error_add(&info); 2131215976Sjmallett 2132215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2133215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2134215976Sjmallett info.status_mask = 1ull<<4 /* bp_sub */; 2135215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2136215976Sjmallett info.enable_mask = 1ull<<4 /* bp_sub */; 2137215976Sjmallett info.flags = 0; 2138215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2139215976Sjmallett info.group_index = 0; 2140215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2141215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2142215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2143215976Sjmallett info.func = __cvmx_error_display; 2144215976Sjmallett info.user_info = (long) 2145215976Sjmallett "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n" 2146215976Sjmallett " supplied illegal value.\n"; 2147215976Sjmallett fail |= cvmx_error_add(&info); 2148215976Sjmallett 2149215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2150215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2151215976Sjmallett info.status_mask = 1ull<<5 /* dc_ovr */; 2152215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2153215976Sjmallett info.enable_mask = 1ull<<5 /* dc_ovr */; 2154215976Sjmallett info.flags = 0; 2155215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2156215976Sjmallett info.group_index = 0; 2157215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2158215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2159215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2160215976Sjmallett info.func = __cvmx_error_display; 2161215976Sjmallett info.user_info = (long) 2162215976Sjmallett "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"; 2163215976Sjmallett fail |= cvmx_error_add(&info); 2164215976Sjmallett 2165215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2166215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2167215976Sjmallett info.status_mask = 1ull<<6 /* cc_ovr */; 2168215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2169215976Sjmallett info.enable_mask = 1ull<<6 /* cc_ovr */; 2170215976Sjmallett info.flags = 0; 2171215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2172215976Sjmallett info.group_index = 0; 2173215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2174215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2175215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2176215976Sjmallett info.func = __cvmx_error_display; 2177215976Sjmallett info.user_info = (long) 2178215976Sjmallett "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"; 2179215976Sjmallett fail |= cvmx_error_add(&info); 2180215976Sjmallett 2181215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2182215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2183215976Sjmallett info.status_mask = 1ull<<7 /* c_coll */; 2184215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2185215976Sjmallett info.enable_mask = 1ull<<7 /* c_coll */; 2186215976Sjmallett info.flags = 0; 2187215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2188215976Sjmallett info.group_index = 0; 2189215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2190215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2191215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2192215976Sjmallett info.func = __cvmx_error_display; 2193215976Sjmallett info.user_info = (long) 2194215976Sjmallett "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n" 2195215976Sjmallett " collides.\n"; 2196215976Sjmallett fail |= cvmx_error_add(&info); 2197215976Sjmallett 2198215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2199215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2200215976Sjmallett info.status_mask = 1ull<<8 /* d_coll */; 2201215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2202215976Sjmallett info.enable_mask = 1ull<<8 /* d_coll */; 2203215976Sjmallett info.flags = 0; 2204215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2205215976Sjmallett info.group_index = 0; 2206215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2207215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2208215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2209215976Sjmallett info.func = __cvmx_error_display; 2210215976Sjmallett info.user_info = (long) 2211215976Sjmallett "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n" 2212215976Sjmallett " collides.\n"; 2213215976Sjmallett fail |= cvmx_error_add(&info); 2214215976Sjmallett 2215215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2216215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2217215976Sjmallett info.status_mask = 1ull<<9 /* bc_ovr */; 2218215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2219215976Sjmallett info.enable_mask = 1ull<<9 /* bc_ovr */; 2220215976Sjmallett info.flags = 0; 2221215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2222215976Sjmallett info.group_index = 0; 2223215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2224215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2225215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2226215976Sjmallett info.func = __cvmx_error_display; 2227215976Sjmallett info.user_info = (long) 2228215976Sjmallett "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"; 2229215976Sjmallett fail |= cvmx_error_add(&info); 2230215976Sjmallett 2231215976Sjmallett /* CVMX_TIM_REG_ERROR */ 2232215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2233215976Sjmallett info.status_addr = CVMX_TIM_REG_ERROR; 2234215976Sjmallett info.status_mask = 0xffffull<<0 /* mask */; 2235215976Sjmallett info.enable_addr = CVMX_TIM_REG_INT_MASK; 2236215976Sjmallett info.enable_mask = 0xffffull<<0 /* mask */; 2237215976Sjmallett info.flags = 0; 2238215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2239215976Sjmallett info.group_index = 0; 2240215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2241215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2242215976Sjmallett info.parent.status_mask = 1ull<<11 /* tim */; 2243215976Sjmallett info.func = __cvmx_error_display; 2244215976Sjmallett info.user_info = (long) 2245215976Sjmallett "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n"; 2246215976Sjmallett fail |= cvmx_error_add(&info); 2247215976Sjmallett 2248215976Sjmallett /* CVMX_POW_ECC_ERR */ 2249215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2250215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2251215976Sjmallett info.status_mask = 1ull<<0 /* sbe */; 2252215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2253215976Sjmallett info.enable_mask = 1ull<<2 /* sbe_ie */; 2254215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 2255215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2256215976Sjmallett info.group_index = 0; 2257215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2258215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2259215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2260215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_sbe; 2261215976Sjmallett info.user_info = (long) 2262215976Sjmallett "ERROR POW_ECC_ERR[SBE]: Single bit error\n"; 2263215976Sjmallett fail |= cvmx_error_add(&info); 2264215976Sjmallett 2265215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2266215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2267215976Sjmallett info.status_mask = 1ull<<1 /* dbe */; 2268215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2269215976Sjmallett info.enable_mask = 1ull<<3 /* dbe_ie */; 2270215976Sjmallett info.flags = 0; 2271215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2272215976Sjmallett info.group_index = 0; 2273215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2274215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2275215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2276215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_dbe; 2277215976Sjmallett info.user_info = (long) 2278215976Sjmallett "ERROR POW_ECC_ERR[DBE]: Double bit error\n"; 2279215976Sjmallett fail |= cvmx_error_add(&info); 2280215976Sjmallett 2281215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2282215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2283215976Sjmallett info.status_mask = 1ull<<12 /* rpe */; 2284215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2285215976Sjmallett info.enable_mask = 1ull<<13 /* rpe_ie */; 2286215976Sjmallett info.flags = 0; 2287215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2288215976Sjmallett info.group_index = 0; 2289215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2290215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2291215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2292215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_rpe; 2293215976Sjmallett info.user_info = (long) 2294215976Sjmallett "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n"; 2295215976Sjmallett fail |= cvmx_error_add(&info); 2296215976Sjmallett 2297215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2298215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2299215976Sjmallett info.status_mask = 0x1fffull<<16 /* iop */; 2300215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2301215976Sjmallett info.enable_mask = 0x1fffull<<32 /* iop_ie */; 2302215976Sjmallett info.flags = 0; 2303215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2304215976Sjmallett info.group_index = 0; 2305215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2306215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2307215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2308215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_iop; 2309215976Sjmallett info.user_info = (long) 2310215976Sjmallett "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n"; 2311215976Sjmallett fail |= cvmx_error_add(&info); 2312215976Sjmallett 2313215976Sjmallett /* CVMX_USBNX_INT_SUM(1) */ 2314215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2315215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2316215976Sjmallett info.status_mask = 1ull<<0 /* pr_po_e */; 2317215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2318215976Sjmallett info.enable_mask = 1ull<<0 /* pr_po_e */; 2319215976Sjmallett info.flags = 0; 2320215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2321215976Sjmallett info.group_index = 1; 2322215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2323215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2324215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2325215976Sjmallett info.func = __cvmx_error_display; 2326215976Sjmallett info.user_info = (long) 2327215976Sjmallett "ERROR USBNX_INT_SUM(1)[PR_PO_E]: PP Request Fifo Popped When Empty.\n"; 2328215976Sjmallett fail |= cvmx_error_add(&info); 2329215976Sjmallett 2330215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2331215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2332215976Sjmallett info.status_mask = 1ull<<1 /* pr_pu_f */; 2333215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2334215976Sjmallett info.enable_mask = 1ull<<1 /* pr_pu_f */; 2335215976Sjmallett info.flags = 0; 2336215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2337215976Sjmallett info.group_index = 1; 2338215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2339215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2340215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2341215976Sjmallett info.func = __cvmx_error_display; 2342215976Sjmallett info.user_info = (long) 2343215976Sjmallett "ERROR USBNX_INT_SUM(1)[PR_PU_F]: PP Request Fifo Pushed When Full.\n"; 2344215976Sjmallett fail |= cvmx_error_add(&info); 2345215976Sjmallett 2346215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2347215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2348215976Sjmallett info.status_mask = 1ull<<2 /* nr_po_e */; 2349215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2350215976Sjmallett info.enable_mask = 1ull<<2 /* nr_po_e */; 2351215976Sjmallett info.flags = 0; 2352215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2353215976Sjmallett info.group_index = 1; 2354215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2355215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2356215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2357215976Sjmallett info.func = __cvmx_error_display; 2358215976Sjmallett info.user_info = (long) 2359215976Sjmallett "ERROR USBNX_INT_SUM(1)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n"; 2360215976Sjmallett fail |= cvmx_error_add(&info); 2361215976Sjmallett 2362215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2363215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2364215976Sjmallett info.status_mask = 1ull<<3 /* nr_pu_f */; 2365215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2366215976Sjmallett info.enable_mask = 1ull<<3 /* nr_pu_f */; 2367215976Sjmallett info.flags = 0; 2368215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2369215976Sjmallett info.group_index = 1; 2370215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2371215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2372215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2373215976Sjmallett info.func = __cvmx_error_display; 2374215976Sjmallett info.user_info = (long) 2375215976Sjmallett "ERROR USBNX_INT_SUM(1)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n"; 2376215976Sjmallett fail |= cvmx_error_add(&info); 2377215976Sjmallett 2378215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2379215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2380215976Sjmallett info.status_mask = 1ull<<4 /* lr_po_e */; 2381215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2382215976Sjmallett info.enable_mask = 1ull<<4 /* lr_po_e */; 2383215976Sjmallett info.flags = 0; 2384215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2385215976Sjmallett info.group_index = 1; 2386215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2387215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2388215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2389215976Sjmallett info.func = __cvmx_error_display; 2390215976Sjmallett info.user_info = (long) 2391215976Sjmallett "ERROR USBNX_INT_SUM(1)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n"; 2392215976Sjmallett fail |= cvmx_error_add(&info); 2393215976Sjmallett 2394215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2395215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2396215976Sjmallett info.status_mask = 1ull<<5 /* lr_pu_f */; 2397215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2398215976Sjmallett info.enable_mask = 1ull<<5 /* lr_pu_f */; 2399215976Sjmallett info.flags = 0; 2400215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2401215976Sjmallett info.group_index = 1; 2402215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2403215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2404215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2405215976Sjmallett info.func = __cvmx_error_display; 2406215976Sjmallett info.user_info = (long) 2407215976Sjmallett "ERROR USBNX_INT_SUM(1)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n"; 2408215976Sjmallett fail |= cvmx_error_add(&info); 2409215976Sjmallett 2410215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2411215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2412215976Sjmallett info.status_mask = 1ull<<6 /* pt_po_e */; 2413215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2414215976Sjmallett info.enable_mask = 1ull<<6 /* pt_po_e */; 2415215976Sjmallett info.flags = 0; 2416215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2417215976Sjmallett info.group_index = 1; 2418215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2419215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2420215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2421215976Sjmallett info.func = __cvmx_error_display; 2422215976Sjmallett info.user_info = (long) 2423215976Sjmallett "ERROR USBNX_INT_SUM(1)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n"; 2424215976Sjmallett fail |= cvmx_error_add(&info); 2425215976Sjmallett 2426215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2427215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2428215976Sjmallett info.status_mask = 1ull<<7 /* pt_pu_f */; 2429215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2430215976Sjmallett info.enable_mask = 1ull<<7 /* pt_pu_f */; 2431215976Sjmallett info.flags = 0; 2432215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2433215976Sjmallett info.group_index = 1; 2434215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2435215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2436215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2437215976Sjmallett info.func = __cvmx_error_display; 2438215976Sjmallett info.user_info = (long) 2439215976Sjmallett "ERROR USBNX_INT_SUM(1)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n"; 2440215976Sjmallett fail |= cvmx_error_add(&info); 2441215976Sjmallett 2442215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2443215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2444215976Sjmallett info.status_mask = 1ull<<8 /* nt_po_e */; 2445215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2446215976Sjmallett info.enable_mask = 1ull<<8 /* nt_po_e */; 2447215976Sjmallett info.flags = 0; 2448215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2449215976Sjmallett info.group_index = 1; 2450215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2451215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2452215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2453215976Sjmallett info.func = __cvmx_error_display; 2454215976Sjmallett info.user_info = (long) 2455215976Sjmallett "ERROR USBNX_INT_SUM(1)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n"; 2456215976Sjmallett fail |= cvmx_error_add(&info); 2457215976Sjmallett 2458215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2459215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2460215976Sjmallett info.status_mask = 1ull<<9 /* nt_pu_f */; 2461215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2462215976Sjmallett info.enable_mask = 1ull<<9 /* nt_pu_f */; 2463215976Sjmallett info.flags = 0; 2464215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2465215976Sjmallett info.group_index = 1; 2466215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2467215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2468215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2469215976Sjmallett info.func = __cvmx_error_display; 2470215976Sjmallett info.user_info = (long) 2471215976Sjmallett "ERROR USBNX_INT_SUM(1)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n"; 2472215976Sjmallett fail |= cvmx_error_add(&info); 2473215976Sjmallett 2474215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2475215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2476215976Sjmallett info.status_mask = 1ull<<10 /* lt_po_e */; 2477215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2478215976Sjmallett info.enable_mask = 1ull<<10 /* lt_po_e */; 2479215976Sjmallett info.flags = 0; 2480215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2481215976Sjmallett info.group_index = 1; 2482215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2483215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2484215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2485215976Sjmallett info.func = __cvmx_error_display; 2486215976Sjmallett info.user_info = (long) 2487215976Sjmallett "ERROR USBNX_INT_SUM(1)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n"; 2488215976Sjmallett fail |= cvmx_error_add(&info); 2489215976Sjmallett 2490215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2491215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2492215976Sjmallett info.status_mask = 1ull<<11 /* lt_pu_f */; 2493215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2494215976Sjmallett info.enable_mask = 1ull<<11 /* lt_pu_f */; 2495215976Sjmallett info.flags = 0; 2496215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2497215976Sjmallett info.group_index = 1; 2498215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2499215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2500215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2501215976Sjmallett info.func = __cvmx_error_display; 2502215976Sjmallett info.user_info = (long) 2503215976Sjmallett "ERROR USBNX_INT_SUM(1)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n"; 2504215976Sjmallett fail |= cvmx_error_add(&info); 2505215976Sjmallett 2506215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2507215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2508215976Sjmallett info.status_mask = 1ull<<12 /* dcred_e */; 2509215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2510215976Sjmallett info.enable_mask = 1ull<<12 /* dcred_e */; 2511215976Sjmallett info.flags = 0; 2512215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2513215976Sjmallett info.group_index = 1; 2514215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2515215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2516215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2517215976Sjmallett info.func = __cvmx_error_display; 2518215976Sjmallett info.user_info = (long) 2519215976Sjmallett "ERROR USBNX_INT_SUM(1)[DCRED_E]: Data Credit Fifo Pushed When Full.\n"; 2520215976Sjmallett fail |= cvmx_error_add(&info); 2521215976Sjmallett 2522215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2523215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2524215976Sjmallett info.status_mask = 1ull<<13 /* dcred_f */; 2525215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2526215976Sjmallett info.enable_mask = 1ull<<13 /* dcred_f */; 2527215976Sjmallett info.flags = 0; 2528215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2529215976Sjmallett info.group_index = 1; 2530215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2531215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2532215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2533215976Sjmallett info.func = __cvmx_error_display; 2534215976Sjmallett info.user_info = (long) 2535215976Sjmallett "ERROR USBNX_INT_SUM(1)[DCRED_F]: Data CreditFifo Pushed When Full.\n"; 2536215976Sjmallett fail |= cvmx_error_add(&info); 2537215976Sjmallett 2538215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2539215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2540215976Sjmallett info.status_mask = 1ull<<14 /* l2c_s_e */; 2541215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2542215976Sjmallett info.enable_mask = 1ull<<14 /* l2c_s_e */; 2543215976Sjmallett info.flags = 0; 2544215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2545215976Sjmallett info.group_index = 1; 2546215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2547215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2548215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2549215976Sjmallett info.func = __cvmx_error_display; 2550215976Sjmallett info.user_info = (long) 2551215976Sjmallett "ERROR USBNX_INT_SUM(1)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n"; 2552215976Sjmallett fail |= cvmx_error_add(&info); 2553215976Sjmallett 2554215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2555215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2556215976Sjmallett info.status_mask = 1ull<<15 /* l2c_a_f */; 2557215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2558215976Sjmallett info.enable_mask = 1ull<<15 /* l2c_a_f */; 2559215976Sjmallett info.flags = 0; 2560215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2561215976Sjmallett info.group_index = 1; 2562215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2563215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2564215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2565215976Sjmallett info.func = __cvmx_error_display; 2566215976Sjmallett info.user_info = (long) 2567215976Sjmallett "ERROR USBNX_INT_SUM(1)[L2C_A_F]: L2C Credit Count Added When Full.\n"; 2568215976Sjmallett fail |= cvmx_error_add(&info); 2569215976Sjmallett 2570215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2571215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2572215976Sjmallett info.status_mask = 1ull<<16 /* lt_fi_e */; 2573215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2574215976Sjmallett info.enable_mask = 1ull<<16 /* l2_fi_e */; 2575215976Sjmallett info.flags = 0; 2576215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2577215976Sjmallett info.group_index = 1; 2578215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2579215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2580215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2581215976Sjmallett info.func = __cvmx_error_display; 2582215976Sjmallett info.user_info = (long) 2583215976Sjmallett "ERROR USBNX_INT_SUM(1)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n"; 2584215976Sjmallett fail |= cvmx_error_add(&info); 2585215976Sjmallett 2586215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2587215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2588215976Sjmallett info.status_mask = 1ull<<17 /* lt_fi_f */; 2589215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2590215976Sjmallett info.enable_mask = 1ull<<17 /* l2_fi_f */; 2591215976Sjmallett info.flags = 0; 2592215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2593215976Sjmallett info.group_index = 1; 2594215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2595215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2596215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2597215976Sjmallett info.func = __cvmx_error_display; 2598215976Sjmallett info.user_info = (long) 2599215976Sjmallett "ERROR USBNX_INT_SUM(1)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n"; 2600215976Sjmallett fail |= cvmx_error_add(&info); 2601215976Sjmallett 2602215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2603215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2604215976Sjmallett info.status_mask = 1ull<<18 /* rg_fi_e */; 2605215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2606215976Sjmallett info.enable_mask = 1ull<<18 /* rg_fi_e */; 2607215976Sjmallett info.flags = 0; 2608215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2609215976Sjmallett info.group_index = 1; 2610215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2611215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2612215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2613215976Sjmallett info.func = __cvmx_error_display; 2614215976Sjmallett info.user_info = (long) 2615215976Sjmallett "ERROR USBNX_INT_SUM(1)[RG_FI_E]: Register Request Fifo Pushed When Full.\n"; 2616215976Sjmallett fail |= cvmx_error_add(&info); 2617215976Sjmallett 2618215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2619215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2620215976Sjmallett info.status_mask = 1ull<<19 /* rg_fi_f */; 2621215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2622215976Sjmallett info.enable_mask = 1ull<<19 /* rg_fi_f */; 2623215976Sjmallett info.flags = 0; 2624215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2625215976Sjmallett info.group_index = 1; 2626215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2627215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2628215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2629215976Sjmallett info.func = __cvmx_error_display; 2630215976Sjmallett info.user_info = (long) 2631215976Sjmallett "ERROR USBNX_INT_SUM(1)[RG_FI_F]: Register Request Fifo Pushed When Full.\n"; 2632215976Sjmallett fail |= cvmx_error_add(&info); 2633215976Sjmallett 2634215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2635215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2636215976Sjmallett info.status_mask = 1ull<<20 /* rq_q2_f */; 2637215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2638215976Sjmallett info.enable_mask = 1ull<<20 /* rq_q2_f */; 2639215976Sjmallett info.flags = 0; 2640215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2641215976Sjmallett info.group_index = 1; 2642215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2643215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2644215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2645215976Sjmallett info.func = __cvmx_error_display; 2646215976Sjmallett info.user_info = (long) 2647215976Sjmallett "ERROR USBNX_INT_SUM(1)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n"; 2648215976Sjmallett fail |= cvmx_error_add(&info); 2649215976Sjmallett 2650215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2651215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2652215976Sjmallett info.status_mask = 1ull<<21 /* rq_q2_e */; 2653215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2654215976Sjmallett info.enable_mask = 1ull<<21 /* rq_q2_e */; 2655215976Sjmallett info.flags = 0; 2656215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2657215976Sjmallett info.group_index = 1; 2658215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2659215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2660215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2661215976Sjmallett info.func = __cvmx_error_display; 2662215976Sjmallett info.user_info = (long) 2663215976Sjmallett "ERROR USBNX_INT_SUM(1)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n"; 2664215976Sjmallett fail |= cvmx_error_add(&info); 2665215976Sjmallett 2666215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2667215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2668215976Sjmallett info.status_mask = 1ull<<22 /* rq_q3_f */; 2669215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2670215976Sjmallett info.enable_mask = 1ull<<22 /* rq_q3_f */; 2671215976Sjmallett info.flags = 0; 2672215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2673215976Sjmallett info.group_index = 1; 2674215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2675215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2676215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2677215976Sjmallett info.func = __cvmx_error_display; 2678215976Sjmallett info.user_info = (long) 2679215976Sjmallett "ERROR USBNX_INT_SUM(1)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n"; 2680215976Sjmallett fail |= cvmx_error_add(&info); 2681215976Sjmallett 2682215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2683215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2684215976Sjmallett info.status_mask = 1ull<<23 /* rq_q3_e */; 2685215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2686215976Sjmallett info.enable_mask = 1ull<<23 /* rq_q3_e */; 2687215976Sjmallett info.flags = 0; 2688215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2689215976Sjmallett info.group_index = 1; 2690215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2691215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2692215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2693215976Sjmallett info.func = __cvmx_error_display; 2694215976Sjmallett info.user_info = (long) 2695215976Sjmallett "ERROR USBNX_INT_SUM(1)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n"; 2696215976Sjmallett fail |= cvmx_error_add(&info); 2697215976Sjmallett 2698215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2699215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2700215976Sjmallett info.status_mask = 1ull<<24 /* uod_pe */; 2701215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2702215976Sjmallett info.enable_mask = 1ull<<24 /* uod_pe */; 2703215976Sjmallett info.flags = 0; 2704215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2705215976Sjmallett info.group_index = 1; 2706215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2707215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2708215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2709215976Sjmallett info.func = __cvmx_error_display; 2710215976Sjmallett info.user_info = (long) 2711215976Sjmallett "ERROR USBNX_INT_SUM(1)[UOD_PE]: UOD Fifo Pop Empty.\n"; 2712215976Sjmallett fail |= cvmx_error_add(&info); 2713215976Sjmallett 2714215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2715215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2716215976Sjmallett info.status_mask = 1ull<<25 /* uod_pf */; 2717215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2718215976Sjmallett info.enable_mask = 1ull<<25 /* uod_pf */; 2719215976Sjmallett info.flags = 0; 2720215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2721215976Sjmallett info.group_index = 1; 2722215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2723215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2724215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2725215976Sjmallett info.func = __cvmx_error_display; 2726215976Sjmallett info.user_info = (long) 2727215976Sjmallett "ERROR USBNX_INT_SUM(1)[UOD_PF]: UOD Fifo Push Full.\n"; 2728215976Sjmallett fail |= cvmx_error_add(&info); 2729215976Sjmallett 2730215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2731215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2732215976Sjmallett info.status_mask = 1ull<<32 /* ltl_f_pe */; 2733215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2734215976Sjmallett info.enable_mask = 1ull<<32 /* ltl_f_pe */; 2735215976Sjmallett info.flags = 0; 2736215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2737215976Sjmallett info.group_index = 1; 2738215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2739215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2740215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2741215976Sjmallett info.func = __cvmx_error_display; 2742215976Sjmallett info.user_info = (long) 2743215976Sjmallett "ERROR USBNX_INT_SUM(1)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n"; 2744215976Sjmallett fail |= cvmx_error_add(&info); 2745215976Sjmallett 2746215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2747215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2748215976Sjmallett info.status_mask = 1ull<<33 /* ltl_f_pf */; 2749215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2750215976Sjmallett info.enable_mask = 1ull<<33 /* ltl_f_pf */; 2751215976Sjmallett info.flags = 0; 2752215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2753215976Sjmallett info.group_index = 1; 2754215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2755215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2756215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2757215976Sjmallett info.func = __cvmx_error_display; 2758215976Sjmallett info.user_info = (long) 2759215976Sjmallett "ERROR USBNX_INT_SUM(1)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n"; 2760215976Sjmallett fail |= cvmx_error_add(&info); 2761215976Sjmallett 2762215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2763215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2764215976Sjmallett info.status_mask = 1ull<<34 /* nd4o_rpe */; 2765215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2766215976Sjmallett info.enable_mask = 1ull<<34 /* nd4o_rpe */; 2767215976Sjmallett info.flags = 0; 2768215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2769215976Sjmallett info.group_index = 1; 2770215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2771215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2772215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2773215976Sjmallett info.func = __cvmx_error_display; 2774215976Sjmallett info.user_info = (long) 2775215976Sjmallett "ERROR USBNX_INT_SUM(1)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n"; 2776215976Sjmallett fail |= cvmx_error_add(&info); 2777215976Sjmallett 2778215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2779215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2780215976Sjmallett info.status_mask = 1ull<<35 /* nd4o_rpf */; 2781215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2782215976Sjmallett info.enable_mask = 1ull<<35 /* nd4o_rpf */; 2783215976Sjmallett info.flags = 0; 2784215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2785215976Sjmallett info.group_index = 1; 2786215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2787215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2788215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2789215976Sjmallett info.func = __cvmx_error_display; 2790215976Sjmallett info.user_info = (long) 2791215976Sjmallett "ERROR USBNX_INT_SUM(1)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n"; 2792215976Sjmallett fail |= cvmx_error_add(&info); 2793215976Sjmallett 2794215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2795215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2796215976Sjmallett info.status_mask = 1ull<<36 /* nd4o_dpe */; 2797215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2798215976Sjmallett info.enable_mask = 1ull<<36 /* nd4o_dpe */; 2799215976Sjmallett info.flags = 0; 2800215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2801215976Sjmallett info.group_index = 1; 2802215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2803215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2804215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2805215976Sjmallett info.func = __cvmx_error_display; 2806215976Sjmallett info.user_info = (long) 2807215976Sjmallett "ERROR USBNX_INT_SUM(1)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n"; 2808215976Sjmallett fail |= cvmx_error_add(&info); 2809215976Sjmallett 2810215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2811215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(1); 2812215976Sjmallett info.status_mask = 1ull<<37 /* nd4o_dpf */; 2813215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(1); 2814215976Sjmallett info.enable_mask = 1ull<<37 /* nd4o_dpf */; 2815215976Sjmallett info.flags = 0; 2816215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 2817215976Sjmallett info.group_index = 1; 2818215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2819215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2820215976Sjmallett info.parent.status_mask = 1ull<<15 /* usb1 */; 2821215976Sjmallett info.func = __cvmx_error_display; 2822215976Sjmallett info.user_info = (long) 2823215976Sjmallett "ERROR USBNX_INT_SUM(1)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n"; 2824215976Sjmallett fail |= cvmx_error_add(&info); 2825215976Sjmallett 2826215976Sjmallett /* CVMX_PEXP_NPEI_INT_SUM */ 2827215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2828215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2829215976Sjmallett info.status_mask = 1ull<<59 /* c0_ldwn */; 2830215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2831215976Sjmallett info.enable_mask = 1ull<<59 /* c0_ldwn */; 2832215976Sjmallett info.flags = 0; 2833215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2834215976Sjmallett info.group_index = 0; 2835215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2836215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2837215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2838215976Sjmallett info.func = __cvmx_error_display; 2839215976Sjmallett info.user_info = (long) 2840215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n"; 2841215976Sjmallett fail |= cvmx_error_add(&info); 2842215976Sjmallett 2843215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2844215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2845215976Sjmallett info.status_mask = 1ull<<21 /* c0_se */; 2846215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2847215976Sjmallett info.enable_mask = 1ull<<21 /* c0_se */; 2848215976Sjmallett info.flags = 0; 2849215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2850215976Sjmallett info.group_index = 0; 2851215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2852215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2853215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2854215976Sjmallett info.func = __cvmx_error_display; 2855215976Sjmallett info.user_info = (long) 2856215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n" 2857215976Sjmallett " Pcie Core 0. (cfg_sys_err_rc)\n"; 2858215976Sjmallett fail |= cvmx_error_add(&info); 2859215976Sjmallett 2860215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2861215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2862215976Sjmallett info.status_mask = 1ull<<38 /* c0_un_b0 */; 2863215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2864215976Sjmallett info.enable_mask = 1ull<<38 /* c0_un_b0 */; 2865215976Sjmallett info.flags = 0; 2866215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2867215976Sjmallett info.group_index = 0; 2868215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2869215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2870215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2871215976Sjmallett info.func = __cvmx_error_display; 2872215976Sjmallett info.user_info = (long) 2873215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n" 2874215976Sjmallett " Core 0.\n"; 2875215976Sjmallett fail |= cvmx_error_add(&info); 2876215976Sjmallett 2877215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2878215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2879215976Sjmallett info.status_mask = 1ull<<39 /* c0_un_b1 */; 2880215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2881215976Sjmallett info.enable_mask = 1ull<<39 /* c0_un_b1 */; 2882215976Sjmallett info.flags = 0; 2883215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2884215976Sjmallett info.group_index = 0; 2885215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2886215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2887215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2888215976Sjmallett info.func = __cvmx_error_display; 2889215976Sjmallett info.user_info = (long) 2890215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n" 2891215976Sjmallett " Core 0.\n"; 2892215976Sjmallett fail |= cvmx_error_add(&info); 2893215976Sjmallett 2894215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2895215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2896215976Sjmallett info.status_mask = 1ull<<40 /* c0_un_b2 */; 2897215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2898215976Sjmallett info.enable_mask = 1ull<<40 /* c0_un_b2 */; 2899215976Sjmallett info.flags = 0; 2900215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2901215976Sjmallett info.group_index = 0; 2902215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2903215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2904215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2905215976Sjmallett info.func = __cvmx_error_display; 2906215976Sjmallett info.user_info = (long) 2907215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n" 2908215976Sjmallett " Core 0.\n"; 2909215976Sjmallett fail |= cvmx_error_add(&info); 2910215976Sjmallett 2911215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2912215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2913215976Sjmallett info.status_mask = 1ull<<42 /* c0_un_bx */; 2914215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2915215976Sjmallett info.enable_mask = 1ull<<42 /* c0_un_bx */; 2916215976Sjmallett info.flags = 0; 2917215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2918215976Sjmallett info.group_index = 0; 2919215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2920215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2921215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2922215976Sjmallett info.func = __cvmx_error_display; 2923215976Sjmallett info.user_info = (long) 2924215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n" 2925215976Sjmallett " Core 0.\n"; 2926215976Sjmallett fail |= cvmx_error_add(&info); 2927215976Sjmallett 2928215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2929215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2930215976Sjmallett info.status_mask = 1ull<<53 /* c0_un_wf */; 2931215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2932215976Sjmallett info.enable_mask = 1ull<<53 /* c0_un_wf */; 2933215976Sjmallett info.flags = 0; 2934215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2935215976Sjmallett info.group_index = 0; 2936215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2937215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2938215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2939215976Sjmallett info.func = __cvmx_error_display; 2940215976Sjmallett info.user_info = (long) 2941215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n" 2942215976Sjmallett " register. Core0.\n"; 2943215976Sjmallett fail |= cvmx_error_add(&info); 2944215976Sjmallett 2945215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2946215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2947215976Sjmallett info.status_mask = 1ull<<41 /* c0_un_wi */; 2948215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2949215976Sjmallett info.enable_mask = 1ull<<41 /* c0_un_wi */; 2950215976Sjmallett info.flags = 0; 2951215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2952215976Sjmallett info.group_index = 0; 2953215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2954215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2955215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2956215976Sjmallett info.func = __cvmx_error_display; 2957215976Sjmallett info.user_info = (long) 2958215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n" 2959215976Sjmallett " Core 0.\n"; 2960215976Sjmallett fail |= cvmx_error_add(&info); 2961215976Sjmallett 2962215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2963215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2964215976Sjmallett info.status_mask = 1ull<<33 /* c0_up_b0 */; 2965215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2966215976Sjmallett info.enable_mask = 1ull<<33 /* c0_up_b0 */; 2967215976Sjmallett info.flags = 0; 2968215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2969215976Sjmallett info.group_index = 0; 2970215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2971215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2972215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2973215976Sjmallett info.func = __cvmx_error_display; 2974215976Sjmallett info.user_info = (long) 2975215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n" 2976215976Sjmallett " Core 0.\n"; 2977215976Sjmallett fail |= cvmx_error_add(&info); 2978215976Sjmallett 2979215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2980215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2981215976Sjmallett info.status_mask = 1ull<<34 /* c0_up_b1 */; 2982215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 2983215976Sjmallett info.enable_mask = 1ull<<34 /* c0_up_b1 */; 2984215976Sjmallett info.flags = 0; 2985215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2986215976Sjmallett info.group_index = 0; 2987215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2988215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 2989215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 2990215976Sjmallett info.func = __cvmx_error_display; 2991215976Sjmallett info.user_info = (long) 2992215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n" 2993215976Sjmallett " Core 0.\n"; 2994215976Sjmallett fail |= cvmx_error_add(&info); 2995215976Sjmallett 2996215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2997215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 2998215976Sjmallett info.status_mask = 1ull<<35 /* c0_up_b2 */; 2999215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3000215976Sjmallett info.enable_mask = 1ull<<35 /* c0_up_b2 */; 3001215976Sjmallett info.flags = 0; 3002215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3003215976Sjmallett info.group_index = 0; 3004215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3005215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3006215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3007215976Sjmallett info.func = __cvmx_error_display; 3008215976Sjmallett info.user_info = (long) 3009215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n" 3010215976Sjmallett " Core 0.\n"; 3011215976Sjmallett fail |= cvmx_error_add(&info); 3012215976Sjmallett 3013215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3014215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3015215976Sjmallett info.status_mask = 1ull<<37 /* c0_up_bx */; 3016215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3017215976Sjmallett info.enable_mask = 1ull<<37 /* c0_up_bx */; 3018215976Sjmallett info.flags = 0; 3019215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3020215976Sjmallett info.group_index = 0; 3021215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3022215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3023215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3024215976Sjmallett info.func = __cvmx_error_display; 3025215976Sjmallett info.user_info = (long) 3026215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n" 3027215976Sjmallett " Core 0.\n"; 3028215976Sjmallett fail |= cvmx_error_add(&info); 3029215976Sjmallett 3030215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3031215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3032215976Sjmallett info.status_mask = 1ull<<55 /* c0_up_wf */; 3033215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3034215976Sjmallett info.enable_mask = 1ull<<55 /* c0_up_wf */; 3035215976Sjmallett info.flags = 0; 3036215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3037215976Sjmallett info.group_index = 0; 3038215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3039215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3040215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3041215976Sjmallett info.func = __cvmx_error_display; 3042215976Sjmallett info.user_info = (long) 3043215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n" 3044215976Sjmallett " register. Core0.\n"; 3045215976Sjmallett fail |= cvmx_error_add(&info); 3046215976Sjmallett 3047215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3048215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3049215976Sjmallett info.status_mask = 1ull<<36 /* c0_up_wi */; 3050215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3051215976Sjmallett info.enable_mask = 1ull<<36 /* c0_up_wi */; 3052215976Sjmallett info.flags = 0; 3053215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3054215976Sjmallett info.group_index = 0; 3055215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3056215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3057215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3058215976Sjmallett info.func = __cvmx_error_display; 3059215976Sjmallett info.user_info = (long) 3060215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n" 3061215976Sjmallett " Core 0.\n"; 3062215976Sjmallett fail |= cvmx_error_add(&info); 3063215976Sjmallett 3064215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3065215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3066215976Sjmallett info.status_mask = 1ull<<23 /* c0_wake */; 3067215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3068215976Sjmallett info.enable_mask = 1ull<<23 /* c0_wake */; 3069215976Sjmallett info.flags = 0; 3070215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3071215976Sjmallett info.group_index = 0; 3072215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3073215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3074215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3075215976Sjmallett info.func = __cvmx_error_display; 3076215976Sjmallett info.user_info = (long) 3077215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n" 3078215976Sjmallett " Pcie Core 0. (wake_n)\n" 3079215976Sjmallett " Octeon will never generate this interrupt.\n"; 3080215976Sjmallett fail |= cvmx_error_add(&info); 3081215976Sjmallett 3082215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3083215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3084215976Sjmallett info.status_mask = 1ull<<22 /* crs0_dr */; 3085215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3086215976Sjmallett info.enable_mask = 1ull<<22 /* crs0_dr */; 3087215976Sjmallett info.flags = 0; 3088215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3089215976Sjmallett info.group_index = 0; 3090215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3091215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3092215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3093215976Sjmallett info.func = __cvmx_error_display; 3094215976Sjmallett info.user_info = (long) 3095215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n"; 3096215976Sjmallett fail |= cvmx_error_add(&info); 3097215976Sjmallett 3098215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3099215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3100215976Sjmallett info.status_mask = 1ull<<20 /* crs0_er */; 3101215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3102215976Sjmallett info.enable_mask = 1ull<<20 /* crs0_er */; 3103215976Sjmallett info.flags = 0; 3104215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3105215976Sjmallett info.group_index = 0; 3106215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3107215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3108215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3109215976Sjmallett info.func = __cvmx_error_display; 3110215976Sjmallett info.user_info = (long) 3111215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n"; 3112215976Sjmallett fail |= cvmx_error_add(&info); 3113215976Sjmallett 3114215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3115215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3116215976Sjmallett info.status_mask = 1ull<<60 /* c1_ldwn */; 3117215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3118215976Sjmallett info.enable_mask = 1ull<<60 /* c1_ldwn */; 3119215976Sjmallett info.flags = 0; 3120215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3121215976Sjmallett info.group_index = 1; 3122215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3123215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3124215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3125215976Sjmallett info.func = __cvmx_error_display; 3126215976Sjmallett info.user_info = (long) 3127215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n"; 3128215976Sjmallett fail |= cvmx_error_add(&info); 3129215976Sjmallett 3130215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3131215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3132215976Sjmallett info.status_mask = 1ull<<28 /* c1_se */; 3133215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3134215976Sjmallett info.enable_mask = 1ull<<28 /* c1_se */; 3135215976Sjmallett info.flags = 0; 3136215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3137215976Sjmallett info.group_index = 1; 3138215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3139215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3140215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3141215976Sjmallett info.func = __cvmx_error_display; 3142215976Sjmallett info.user_info = (long) 3143215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n" 3144215976Sjmallett " Pcie Core 1. (cfg_sys_err_rc)\n"; 3145215976Sjmallett fail |= cvmx_error_add(&info); 3146215976Sjmallett 3147215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3148215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3149215976Sjmallett info.status_mask = 1ull<<48 /* c1_un_b0 */; 3150215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3151215976Sjmallett info.enable_mask = 1ull<<48 /* c1_un_b0 */; 3152215976Sjmallett info.flags = 0; 3153215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3154215976Sjmallett info.group_index = 1; 3155215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3156215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3157215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3158215976Sjmallett info.func = __cvmx_error_display; 3159215976Sjmallett info.user_info = (long) 3160215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n" 3161215976Sjmallett " Core 1.\n"; 3162215976Sjmallett fail |= cvmx_error_add(&info); 3163215976Sjmallett 3164215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3165215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3166215976Sjmallett info.status_mask = 1ull<<49 /* c1_un_b1 */; 3167215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3168215976Sjmallett info.enable_mask = 1ull<<49 /* c1_un_b1 */; 3169215976Sjmallett info.flags = 0; 3170215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3171215976Sjmallett info.group_index = 1; 3172215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3173215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3174215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3175215976Sjmallett info.func = __cvmx_error_display; 3176215976Sjmallett info.user_info = (long) 3177215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n" 3178215976Sjmallett " Core 1.\n"; 3179215976Sjmallett fail |= cvmx_error_add(&info); 3180215976Sjmallett 3181215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3182215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3183215976Sjmallett info.status_mask = 1ull<<50 /* c1_un_b2 */; 3184215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3185215976Sjmallett info.enable_mask = 1ull<<50 /* c1_un_b2 */; 3186215976Sjmallett info.flags = 0; 3187215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3188215976Sjmallett info.group_index = 1; 3189215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3190215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3191215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3192215976Sjmallett info.func = __cvmx_error_display; 3193215976Sjmallett info.user_info = (long) 3194215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n" 3195215976Sjmallett " Core 1.\n"; 3196215976Sjmallett fail |= cvmx_error_add(&info); 3197215976Sjmallett 3198215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3199215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3200215976Sjmallett info.status_mask = 1ull<<52 /* c1_un_bx */; 3201215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3202215976Sjmallett info.enable_mask = 1ull<<52 /* c1_un_bx */; 3203215976Sjmallett info.flags = 0; 3204215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3205215976Sjmallett info.group_index = 1; 3206215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3207215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3208215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3209215976Sjmallett info.func = __cvmx_error_display; 3210215976Sjmallett info.user_info = (long) 3211215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n" 3212215976Sjmallett " Core 1.\n"; 3213215976Sjmallett fail |= cvmx_error_add(&info); 3214215976Sjmallett 3215215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3216215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3217215976Sjmallett info.status_mask = 1ull<<54 /* c1_un_wf */; 3218215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3219215976Sjmallett info.enable_mask = 1ull<<54 /* c1_un_wf */; 3220215976Sjmallett info.flags = 0; 3221215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3222215976Sjmallett info.group_index = 1; 3223215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3224215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3225215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3226215976Sjmallett info.func = __cvmx_error_display; 3227215976Sjmallett info.user_info = (long) 3228215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n" 3229215976Sjmallett " register. Core1.\n"; 3230215976Sjmallett fail |= cvmx_error_add(&info); 3231215976Sjmallett 3232215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3233215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3234215976Sjmallett info.status_mask = 1ull<<51 /* c1_un_wi */; 3235215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3236215976Sjmallett info.enable_mask = 1ull<<51 /* c1_un_wi */; 3237215976Sjmallett info.flags = 0; 3238215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3239215976Sjmallett info.group_index = 1; 3240215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3241215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3242215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3243215976Sjmallett info.func = __cvmx_error_display; 3244215976Sjmallett info.user_info = (long) 3245215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n" 3246215976Sjmallett " Core 1.\n"; 3247215976Sjmallett fail |= cvmx_error_add(&info); 3248215976Sjmallett 3249215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3250215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3251215976Sjmallett info.status_mask = 1ull<<43 /* c1_up_b0 */; 3252215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3253215976Sjmallett info.enable_mask = 1ull<<43 /* c1_up_b0 */; 3254215976Sjmallett info.flags = 0; 3255215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3256215976Sjmallett info.group_index = 1; 3257215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3258215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3259215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3260215976Sjmallett info.func = __cvmx_error_display; 3261215976Sjmallett info.user_info = (long) 3262215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n" 3263215976Sjmallett " Core 1.\n"; 3264215976Sjmallett fail |= cvmx_error_add(&info); 3265215976Sjmallett 3266215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3267215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3268215976Sjmallett info.status_mask = 1ull<<44 /* c1_up_b1 */; 3269215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3270215976Sjmallett info.enable_mask = 1ull<<44 /* c1_up_b1 */; 3271215976Sjmallett info.flags = 0; 3272215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3273215976Sjmallett info.group_index = 1; 3274215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3275215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3276215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3277215976Sjmallett info.func = __cvmx_error_display; 3278215976Sjmallett info.user_info = (long) 3279215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n" 3280215976Sjmallett " Core 1.\n"; 3281215976Sjmallett fail |= cvmx_error_add(&info); 3282215976Sjmallett 3283215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3284215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3285215976Sjmallett info.status_mask = 1ull<<45 /* c1_up_b2 */; 3286215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3287215976Sjmallett info.enable_mask = 1ull<<45 /* c1_up_b2 */; 3288215976Sjmallett info.flags = 0; 3289215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3290215976Sjmallett info.group_index = 1; 3291215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3292215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3293215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3294215976Sjmallett info.func = __cvmx_error_display; 3295215976Sjmallett info.user_info = (long) 3296215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n" 3297215976Sjmallett " Core 1.\n"; 3298215976Sjmallett fail |= cvmx_error_add(&info); 3299215976Sjmallett 3300215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3301215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3302215976Sjmallett info.status_mask = 1ull<<47 /* c1_up_bx */; 3303215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3304215976Sjmallett info.enable_mask = 1ull<<47 /* c1_up_bx */; 3305215976Sjmallett info.flags = 0; 3306215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3307215976Sjmallett info.group_index = 1; 3308215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3309215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3310215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3311215976Sjmallett info.func = __cvmx_error_display; 3312215976Sjmallett info.user_info = (long) 3313215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n" 3314215976Sjmallett " Core 1.\n"; 3315215976Sjmallett fail |= cvmx_error_add(&info); 3316215976Sjmallett 3317215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3318215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3319215976Sjmallett info.status_mask = 1ull<<56 /* c1_up_wf */; 3320215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3321215976Sjmallett info.enable_mask = 1ull<<56 /* c1_up_wf */; 3322215976Sjmallett info.flags = 0; 3323215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3324215976Sjmallett info.group_index = 1; 3325215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3326215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3327215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3328215976Sjmallett info.func = __cvmx_error_display; 3329215976Sjmallett info.user_info = (long) 3330215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n" 3331215976Sjmallett " register. Core1.\n"; 3332215976Sjmallett fail |= cvmx_error_add(&info); 3333215976Sjmallett 3334215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3335215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3336215976Sjmallett info.status_mask = 1ull<<46 /* c1_up_wi */; 3337215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3338215976Sjmallett info.enable_mask = 1ull<<46 /* c1_up_wi */; 3339215976Sjmallett info.flags = 0; 3340215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3341215976Sjmallett info.group_index = 1; 3342215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3343215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3344215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3345215976Sjmallett info.func = __cvmx_error_display; 3346215976Sjmallett info.user_info = (long) 3347215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n" 3348215976Sjmallett " Core 1.\n"; 3349215976Sjmallett fail |= cvmx_error_add(&info); 3350215976Sjmallett 3351215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3352215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3353215976Sjmallett info.status_mask = 1ull<<30 /* c1_wake */; 3354215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3355215976Sjmallett info.enable_mask = 1ull<<30 /* c1_wake */; 3356215976Sjmallett info.flags = 0; 3357215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3358215976Sjmallett info.group_index = 1; 3359215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3360215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3361215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3362215976Sjmallett info.func = __cvmx_error_display; 3363215976Sjmallett info.user_info = (long) 3364215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n" 3365215976Sjmallett " Pcie Core 1. (wake_n)\n" 3366215976Sjmallett " Octeon will never generate this interrupt.\n"; 3367215976Sjmallett fail |= cvmx_error_add(&info); 3368215976Sjmallett 3369215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3370215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3371215976Sjmallett info.status_mask = 1ull<<29 /* crs1_dr */; 3372215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3373215976Sjmallett info.enable_mask = 1ull<<29 /* crs1_dr */; 3374215976Sjmallett info.flags = 0; 3375215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3376215976Sjmallett info.group_index = 1; 3377215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3378215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3379215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3380215976Sjmallett info.func = __cvmx_error_display; 3381215976Sjmallett info.user_info = (long) 3382215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n"; 3383215976Sjmallett fail |= cvmx_error_add(&info); 3384215976Sjmallett 3385215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3386215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3387215976Sjmallett info.status_mask = 1ull<<27 /* crs1_er */; 3388215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3389215976Sjmallett info.enable_mask = 1ull<<27 /* crs1_er */; 3390215976Sjmallett info.flags = 0; 3391215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3392215976Sjmallett info.group_index = 1; 3393215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3394215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3395215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3396215976Sjmallett info.func = __cvmx_error_display; 3397215976Sjmallett info.user_info = (long) 3398215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n"; 3399215976Sjmallett fail |= cvmx_error_add(&info); 3400215976Sjmallett 3401215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3402215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3403215976Sjmallett info.status_mask = 1ull<<2 /* bar0_to */; 3404215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3405215976Sjmallett info.enable_mask = 1ull<<2 /* bar0_to */; 3406215976Sjmallett info.flags = 0; 3407215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3408215976Sjmallett info.group_index = 0; 3409215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3410215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3411215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3412215976Sjmallett info.func = __cvmx_error_display; 3413215976Sjmallett info.user_info = (long) 3414215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n" 3415215976Sjmallett " read-data/commit in 0xffff core clocks.\n"; 3416215976Sjmallett fail |= cvmx_error_add(&info); 3417215976Sjmallett 3418215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3419215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3420215976Sjmallett info.status_mask = 1ull<<4 /* dma0dbo */; 3421215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3422215976Sjmallett info.enable_mask = 1ull<<4 /* dma0dbo */; 3423215976Sjmallett info.flags = 0; 3424215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3425215976Sjmallett info.group_index = 0; 3426215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3427215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3428215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3429215976Sjmallett info.func = __cvmx_error_display; 3430215976Sjmallett info.user_info = (long) 3431215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell count overflow.\n" 3432215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3433215976Sjmallett fail |= cvmx_error_add(&info); 3434215976Sjmallett 3435215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3436215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3437215976Sjmallett info.status_mask = 1ull<<5 /* dma1dbo */; 3438215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3439215976Sjmallett info.enable_mask = 1ull<<5 /* dma1dbo */; 3440215976Sjmallett info.flags = 0; 3441215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3442215976Sjmallett info.group_index = 0; 3443215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3444215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3445215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3446215976Sjmallett info.func = __cvmx_error_display; 3447215976Sjmallett info.user_info = (long) 3448215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell count overflow.\n" 3449215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3450215976Sjmallett fail |= cvmx_error_add(&info); 3451215976Sjmallett 3452215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3453215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3454215976Sjmallett info.status_mask = 1ull<<6 /* dma2dbo */; 3455215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3456215976Sjmallett info.enable_mask = 1ull<<6 /* dma2dbo */; 3457215976Sjmallett info.flags = 0; 3458215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3459215976Sjmallett info.group_index = 0; 3460215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3461215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3462215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3463215976Sjmallett info.func = __cvmx_error_display; 3464215976Sjmallett info.user_info = (long) 3465215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell count overflow.\n" 3466215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3467215976Sjmallett fail |= cvmx_error_add(&info); 3468215976Sjmallett 3469215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3470215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3471215976Sjmallett info.status_mask = 1ull<<7 /* dma3dbo */; 3472215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3473215976Sjmallett info.enable_mask = 1ull<<7 /* dma3dbo */; 3474215976Sjmallett info.flags = 0; 3475215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3476215976Sjmallett info.group_index = 0; 3477215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3478215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3479215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3480215976Sjmallett info.func = __cvmx_error_display; 3481215976Sjmallett info.user_info = (long) 3482215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell count overflow.\n" 3483215976Sjmallett " Bit[32] of the doorbell count was set.\n"; 3484215976Sjmallett fail |= cvmx_error_add(&info); 3485215976Sjmallett 3486215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3487215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3488215976Sjmallett info.status_mask = 1ull<<3 /* iob2big */; 3489215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3490215976Sjmallett info.enable_mask = 1ull<<3 /* iob2big */; 3491215976Sjmallett info.flags = 0; 3492215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3493215976Sjmallett info.group_index = 0; 3494215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3495215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3496215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3497215976Sjmallett info.func = __cvmx_error_display; 3498215976Sjmallett info.user_info = (long) 3499215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n"; 3500215976Sjmallett fail |= cvmx_error_add(&info); 3501215976Sjmallett 3502215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3503215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3504215976Sjmallett info.status_mask = 1ull<<0 /* rml_rto */; 3505215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3506215976Sjmallett info.enable_mask = 1ull<<0 /* rml_rto */; 3507215976Sjmallett info.flags = 0; 3508215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3509215976Sjmallett info.group_index = 0; 3510215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3511215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3512215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3513215976Sjmallett info.func = __cvmx_error_display; 3514215976Sjmallett info.user_info = (long) 3515215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n"; 3516215976Sjmallett fail |= cvmx_error_add(&info); 3517215976Sjmallett 3518215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3519215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3520215976Sjmallett info.status_mask = 1ull<<1 /* rml_wto */; 3521215976Sjmallett info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2; 3522215976Sjmallett info.enable_mask = 1ull<<1 /* rml_wto */; 3523215976Sjmallett info.flags = 0; 3524215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3525215976Sjmallett info.group_index = 0; 3526215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3527215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3528215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3529215976Sjmallett info.func = __cvmx_error_display; 3530215976Sjmallett info.user_info = (long) 3531215976Sjmallett "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n"; 3532215976Sjmallett fail |= cvmx_error_add(&info); 3533215976Sjmallett 3534215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3535215976Sjmallett info.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3536215976Sjmallett info.status_mask = 0; 3537215976Sjmallett info.enable_addr = 0; 3538215976Sjmallett info.enable_mask = 0; 3539215976Sjmallett info.flags = 0; 3540215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3541215976Sjmallett info.group_index = 0; 3542215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3543215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 3544215976Sjmallett info.parent.status_mask = 1ull<<3 /* npei */; 3545215976Sjmallett info.func = __cvmx_error_decode; 3546215976Sjmallett info.user_info = 0; 3547215976Sjmallett fail |= cvmx_error_add(&info); 3548215976Sjmallett 3549215976Sjmallett /* CVMX_PESCX_DBG_INFO(0) */ 3550215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3551215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3552215976Sjmallett info.status_mask = 1ull<<0 /* spoison */; 3553215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3554215976Sjmallett info.enable_mask = 1ull<<0 /* spoison */; 3555215976Sjmallett info.flags = 0; 3556215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3557215976Sjmallett info.group_index = 0; 3558215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3559215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3560215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3561215976Sjmallett info.func = __cvmx_error_display; 3562215976Sjmallett info.user_info = (long) 3563215976Sjmallett "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n" 3564215976Sjmallett " peai__client0_tlp_ep & peai__client0_tlp_hv\n"; 3565215976Sjmallett fail |= cvmx_error_add(&info); 3566215976Sjmallett 3567215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3568215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3569215976Sjmallett info.status_mask = 1ull<<2 /* rtlplle */; 3570215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3571215976Sjmallett info.enable_mask = 1ull<<2 /* rtlplle */; 3572215976Sjmallett info.flags = 0; 3573215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3574215976Sjmallett info.group_index = 0; 3575215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3576215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3577215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3578215976Sjmallett info.func = __cvmx_error_display; 3579215976Sjmallett info.user_info = (long) 3580215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n" 3581215976Sjmallett " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n"; 3582215976Sjmallett fail |= cvmx_error_add(&info); 3583215976Sjmallett 3584215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3585215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3586215976Sjmallett info.status_mask = 1ull<<3 /* recrce */; 3587215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3588215976Sjmallett info.enable_mask = 1ull<<3 /* recrce */; 3589215976Sjmallett info.flags = 0; 3590215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3591215976Sjmallett info.group_index = 0; 3592215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3593215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3594215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3595215976Sjmallett info.func = __cvmx_error_display; 3596215976Sjmallett info.user_info = (long) 3597215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n" 3598215976Sjmallett " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n"; 3599215976Sjmallett fail |= cvmx_error_add(&info); 3600215976Sjmallett 3601215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3602215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3603215976Sjmallett info.status_mask = 1ull<<4 /* rpoison */; 3604215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3605215976Sjmallett info.enable_mask = 1ull<<4 /* rpoison */; 3606215976Sjmallett info.flags = 0; 3607215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3608215976Sjmallett info.group_index = 0; 3609215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3610215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3611215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3612215976Sjmallett info.func = __cvmx_error_display; 3613215976Sjmallett info.user_info = (long) 3614215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n" 3615215976Sjmallett " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n"; 3616215976Sjmallett fail |= cvmx_error_add(&info); 3617215976Sjmallett 3618215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3619215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3620215976Sjmallett info.status_mask = 1ull<<5 /* rcemrc */; 3621215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3622215976Sjmallett info.enable_mask = 1ull<<5 /* rcemrc */; 3623215976Sjmallett info.flags = 0; 3624215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3625215976Sjmallett info.group_index = 0; 3626215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3627215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3628215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3629215976Sjmallett info.func = __cvmx_error_display; 3630215976Sjmallett info.user_info = (long) 3631215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n" 3632215976Sjmallett " pedc_radm_correctable_err\n"; 3633215976Sjmallett fail |= cvmx_error_add(&info); 3634215976Sjmallett 3635215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3636215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3637215976Sjmallett info.status_mask = 1ull<<6 /* rnfemrc */; 3638215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3639215976Sjmallett info.enable_mask = 1ull<<6 /* rnfemrc */; 3640215976Sjmallett info.flags = 0; 3641215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3642215976Sjmallett info.group_index = 0; 3643215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3644215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3645215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3646215976Sjmallett info.func = __cvmx_error_display; 3647215976Sjmallett info.user_info = (long) 3648215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n" 3649215976Sjmallett " pedc_radm_nonfatal_err\n"; 3650215976Sjmallett fail |= cvmx_error_add(&info); 3651215976Sjmallett 3652215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3653215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3654215976Sjmallett info.status_mask = 1ull<<7 /* rfemrc */; 3655215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3656215976Sjmallett info.enable_mask = 1ull<<7 /* rfemrc */; 3657215976Sjmallett info.flags = 0; 3658215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3659215976Sjmallett info.group_index = 0; 3660215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3661215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3662215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3663215976Sjmallett info.func = __cvmx_error_display; 3664215976Sjmallett info.user_info = (long) 3665215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n" 3666215976Sjmallett " pedc_radm_fatal_err\n" 3667215976Sjmallett " Bit set when a message with ERR_FATAL is set.\n"; 3668215976Sjmallett fail |= cvmx_error_add(&info); 3669215976Sjmallett 3670215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3671215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3672215976Sjmallett info.status_mask = 1ull<<8 /* rpmerc */; 3673215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3674215976Sjmallett info.enable_mask = 1ull<<8 /* rpmerc */; 3675215976Sjmallett info.flags = 0; 3676215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3677215976Sjmallett info.group_index = 0; 3678215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3679215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3680215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3681215976Sjmallett info.func = __cvmx_error_display; 3682215976Sjmallett info.user_info = (long) 3683215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n" 3684215976Sjmallett " pedc_radm_pm_pme\n"; 3685215976Sjmallett fail |= cvmx_error_add(&info); 3686215976Sjmallett 3687215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3688215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3689215976Sjmallett info.status_mask = 1ull<<9 /* rptamrc */; 3690215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3691215976Sjmallett info.enable_mask = 1ull<<9 /* rptamrc */; 3692215976Sjmallett info.flags = 0; 3693215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3694215976Sjmallett info.group_index = 0; 3695215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3696215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3697215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3698215976Sjmallett info.func = __cvmx_error_display; 3699215976Sjmallett info.user_info = (long) 3700215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n" 3701215976Sjmallett " (RC Mode only)\n" 3702215976Sjmallett " pedc_radm_pm_to_ack\n"; 3703215976Sjmallett fail |= cvmx_error_add(&info); 3704215976Sjmallett 3705215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3706215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3707215976Sjmallett info.status_mask = 1ull<<10 /* rumep */; 3708215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3709215976Sjmallett info.enable_mask = 1ull<<10 /* rumep */; 3710215976Sjmallett info.flags = 0; 3711215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3712215976Sjmallett info.group_index = 0; 3713215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3714215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3715215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3716215976Sjmallett info.func = __cvmx_error_display; 3717215976Sjmallett info.user_info = (long) 3718215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n" 3719215976Sjmallett " pedc_radm_msg_unlock\n"; 3720215976Sjmallett fail |= cvmx_error_add(&info); 3721215976Sjmallett 3722215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3723215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3724215976Sjmallett info.status_mask = 1ull<<11 /* rvdm */; 3725215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3726215976Sjmallett info.enable_mask = 1ull<<11 /* rvdm */; 3727215976Sjmallett info.flags = 0; 3728215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3729215976Sjmallett info.group_index = 0; 3730215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3731215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3732215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3733215976Sjmallett info.func = __cvmx_error_display; 3734215976Sjmallett info.user_info = (long) 3735215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n" 3736215976Sjmallett " pedc_radm_vendor_msg\n"; 3737215976Sjmallett fail |= cvmx_error_add(&info); 3738215976Sjmallett 3739215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3740215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3741215976Sjmallett info.status_mask = 1ull<<12 /* acto */; 3742215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3743215976Sjmallett info.enable_mask = 1ull<<12 /* acto */; 3744215976Sjmallett info.flags = 0; 3745215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3746215976Sjmallett info.group_index = 0; 3747215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3748215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3749215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3750215976Sjmallett info.func = __cvmx_error_display; 3751215976Sjmallett info.user_info = (long) 3752215976Sjmallett "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n" 3753215976Sjmallett " pedc_radm_cpl_timeout\n"; 3754215976Sjmallett fail |= cvmx_error_add(&info); 3755215976Sjmallett 3756215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3757215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3758215976Sjmallett info.status_mask = 1ull<<13 /* rte */; 3759215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3760215976Sjmallett info.enable_mask = 1ull<<13 /* rte */; 3761215976Sjmallett info.flags = 0; 3762215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3763215976Sjmallett info.group_index = 0; 3764215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3765215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3766215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3767215976Sjmallett info.func = __cvmx_error_display; 3768215976Sjmallett info.user_info = (long) 3769215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n" 3770215976Sjmallett " xdlh_replay_timeout_err\n" 3771215976Sjmallett " This bit is set when the REPLAY_TIMER expires in\n" 3772215976Sjmallett " the PCIE core. The probability of this bit being\n" 3773215976Sjmallett " set will increase with the traffic load.\n"; 3774215976Sjmallett fail |= cvmx_error_add(&info); 3775215976Sjmallett 3776215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3777215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3778215976Sjmallett info.status_mask = 1ull<<14 /* mre */; 3779215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3780215976Sjmallett info.enable_mask = 1ull<<14 /* mre */; 3781215976Sjmallett info.flags = 0; 3782215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3783215976Sjmallett info.group_index = 0; 3784215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3785215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3786215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3787215976Sjmallett info.func = __cvmx_error_display; 3788215976Sjmallett info.user_info = (long) 3789215976Sjmallett "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n" 3790215976Sjmallett " xdlh_replay_num_rlover_err\n"; 3791215976Sjmallett fail |= cvmx_error_add(&info); 3792215976Sjmallett 3793215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3794215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3795215976Sjmallett info.status_mask = 1ull<<15 /* rdwdle */; 3796215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3797215976Sjmallett info.enable_mask = 1ull<<15 /* rdwdle */; 3798215976Sjmallett info.flags = 0; 3799215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3800215976Sjmallett info.group_index = 0; 3801215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3802215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3803215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3804215976Sjmallett info.func = __cvmx_error_display; 3805215976Sjmallett info.user_info = (long) 3806215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n" 3807215976Sjmallett " rdlh_bad_dllp_err\n"; 3808215976Sjmallett fail |= cvmx_error_add(&info); 3809215976Sjmallett 3810215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3811215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3812215976Sjmallett info.status_mask = 1ull<<16 /* rtwdle */; 3813215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3814215976Sjmallett info.enable_mask = 1ull<<16 /* rtwdle */; 3815215976Sjmallett info.flags = 0; 3816215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3817215976Sjmallett info.group_index = 0; 3818215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3819215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3820215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3821215976Sjmallett info.func = __cvmx_error_display; 3822215976Sjmallett info.user_info = (long) 3823215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n" 3824215976Sjmallett " rdlh_bad_tlp_err\n"; 3825215976Sjmallett fail |= cvmx_error_add(&info); 3826215976Sjmallett 3827215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3828215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3829215976Sjmallett info.status_mask = 1ull<<17 /* dpeoosd */; 3830215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3831215976Sjmallett info.enable_mask = 1ull<<17 /* dpeoosd */; 3832215976Sjmallett info.flags = 0; 3833215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3834215976Sjmallett info.group_index = 0; 3835215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3836215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3837215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3838215976Sjmallett info.func = __cvmx_error_display; 3839215976Sjmallett info.user_info = (long) 3840215976Sjmallett "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n" 3841215976Sjmallett " rdlh_prot_err\n"; 3842215976Sjmallett fail |= cvmx_error_add(&info); 3843215976Sjmallett 3844215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3845215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3846215976Sjmallett info.status_mask = 1ull<<18 /* fcpvwt */; 3847215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3848215976Sjmallett info.enable_mask = 1ull<<18 /* fcpvwt */; 3849215976Sjmallett info.flags = 0; 3850215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3851215976Sjmallett info.group_index = 0; 3852215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3853215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3854215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3855215976Sjmallett info.func = __cvmx_error_display; 3856215976Sjmallett info.user_info = (long) 3857215976Sjmallett "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n" 3858215976Sjmallett " rtlh_fc_prot_err\n"; 3859215976Sjmallett fail |= cvmx_error_add(&info); 3860215976Sjmallett 3861215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3862215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3863215976Sjmallett info.status_mask = 1ull<<19 /* rpe */; 3864215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3865215976Sjmallett info.enable_mask = 1ull<<19 /* rpe */; 3866215976Sjmallett info.flags = 0; 3867215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3868215976Sjmallett info.group_index = 0; 3869215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3870215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3871215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3872215976Sjmallett info.func = __cvmx_error_display; 3873215976Sjmallett info.user_info = (long) 3874215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n" 3875215976Sjmallett " (RxStatus = 3b100) or disparity error\n" 3876215976Sjmallett " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n" 3877215976Sjmallett " be asserted.\n" 3878215976Sjmallett " rmlh_rcvd_err\n"; 3879215976Sjmallett fail |= cvmx_error_add(&info); 3880215976Sjmallett 3881215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3882215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3883215976Sjmallett info.status_mask = 1ull<<20 /* fcuv */; 3884215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3885215976Sjmallett info.enable_mask = 1ull<<20 /* fcuv */; 3886215976Sjmallett info.flags = 0; 3887215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3888215976Sjmallett info.group_index = 0; 3889215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3890215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3891215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3892215976Sjmallett info.func = __cvmx_error_display; 3893215976Sjmallett info.user_info = (long) 3894215976Sjmallett "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n" 3895215976Sjmallett " int_xadm_fc_prot_err\n"; 3896215976Sjmallett fail |= cvmx_error_add(&info); 3897215976Sjmallett 3898215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3899215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3900215976Sjmallett info.status_mask = 1ull<<21 /* rqo */; 3901215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3902215976Sjmallett info.enable_mask = 1ull<<21 /* rqo */; 3903215976Sjmallett info.flags = 0; 3904215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3905215976Sjmallett info.group_index = 0; 3906215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3907215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3908215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3909215976Sjmallett info.func = __cvmx_error_display; 3910215976Sjmallett info.user_info = (long) 3911215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n" 3912215976Sjmallett " flow control advertisements are ignored\n" 3913215976Sjmallett " radm_qoverflow\n"; 3914215976Sjmallett fail |= cvmx_error_add(&info); 3915215976Sjmallett 3916215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3917215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3918215976Sjmallett info.status_mask = 1ull<<22 /* rauc */; 3919215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3920215976Sjmallett info.enable_mask = 1ull<<22 /* rauc */; 3921215976Sjmallett info.flags = 0; 3922215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3923215976Sjmallett info.group_index = 0; 3924215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3925215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3926215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3927215976Sjmallett info.func = __cvmx_error_display; 3928215976Sjmallett info.user_info = (long) 3929215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n" 3930215976Sjmallett " radm_unexp_cpl_err\n"; 3931215976Sjmallett fail |= cvmx_error_add(&info); 3932215976Sjmallett 3933215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3934215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3935215976Sjmallett info.status_mask = 1ull<<23 /* racur */; 3936215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3937215976Sjmallett info.enable_mask = 1ull<<23 /* racur */; 3938215976Sjmallett info.flags = 0; 3939215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3940215976Sjmallett info.group_index = 0; 3941215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3942215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3943215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3944215976Sjmallett info.func = __cvmx_error_display; 3945215976Sjmallett info.user_info = (long) 3946215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n" 3947215976Sjmallett " radm_rcvd_cpl_ur\n"; 3948215976Sjmallett fail |= cvmx_error_add(&info); 3949215976Sjmallett 3950215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3951215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3952215976Sjmallett info.status_mask = 1ull<<24 /* racca */; 3953215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3954215976Sjmallett info.enable_mask = 1ull<<24 /* racca */; 3955215976Sjmallett info.flags = 0; 3956215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3957215976Sjmallett info.group_index = 0; 3958215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3959215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3960215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3961215976Sjmallett info.func = __cvmx_error_display; 3962215976Sjmallett info.user_info = (long) 3963215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n" 3964215976Sjmallett " radm_rcvd_cpl_ca\n"; 3965215976Sjmallett fail |= cvmx_error_add(&info); 3966215976Sjmallett 3967215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3968215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3969215976Sjmallett info.status_mask = 1ull<<25 /* caar */; 3970215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3971215976Sjmallett info.enable_mask = 1ull<<25 /* caar */; 3972215976Sjmallett info.flags = 0; 3973215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3974215976Sjmallett info.group_index = 0; 3975215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3976215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3977215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3978215976Sjmallett info.func = __cvmx_error_display; 3979215976Sjmallett info.user_info = (long) 3980215976Sjmallett "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n" 3981215976Sjmallett " radm_rcvd_ca_req\n" 3982215976Sjmallett " This bit will never be set because Octeon does\n" 3983215976Sjmallett " not generate Completer Aborts.\n"; 3984215976Sjmallett fail |= cvmx_error_add(&info); 3985215976Sjmallett 3986215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3987215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 3988215976Sjmallett info.status_mask = 1ull<<26 /* rarwdns */; 3989215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 3990215976Sjmallett info.enable_mask = 1ull<<26 /* rarwdns */; 3991215976Sjmallett info.flags = 0; 3992215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3993215976Sjmallett info.group_index = 0; 3994215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3995215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 3996215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 3997215976Sjmallett info.func = __cvmx_error_display; 3998215976Sjmallett info.user_info = (long) 3999215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n" 4000215976Sjmallett " radm_rcvd_ur_req\n"; 4001215976Sjmallett fail |= cvmx_error_add(&info); 4002215976Sjmallett 4003215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4004215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4005215976Sjmallett info.status_mask = 1ull<<27 /* ramtlp */; 4006215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4007215976Sjmallett info.enable_mask = 1ull<<27 /* ramtlp */; 4008215976Sjmallett info.flags = 0; 4009215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4010215976Sjmallett info.group_index = 0; 4011215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4012215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4013215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4014215976Sjmallett info.func = __cvmx_error_display; 4015215976Sjmallett info.user_info = (long) 4016215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n" 4017215976Sjmallett " radm_mlf_tlp_err\n"; 4018215976Sjmallett fail |= cvmx_error_add(&info); 4019215976Sjmallett 4020215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4021215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4022215976Sjmallett info.status_mask = 1ull<<28 /* racpp */; 4023215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4024215976Sjmallett info.enable_mask = 1ull<<28 /* racpp */; 4025215976Sjmallett info.flags = 0; 4026215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4027215976Sjmallett info.group_index = 0; 4028215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4029215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4030215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4031215976Sjmallett info.func = __cvmx_error_display; 4032215976Sjmallett info.user_info = (long) 4033215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n" 4034215976Sjmallett " radm_rcvd_cpl_poisoned\n"; 4035215976Sjmallett fail |= cvmx_error_add(&info); 4036215976Sjmallett 4037215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4038215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4039215976Sjmallett info.status_mask = 1ull<<29 /* rawwpp */; 4040215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4041215976Sjmallett info.enable_mask = 1ull<<29 /* rawwpp */; 4042215976Sjmallett info.flags = 0; 4043215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4044215976Sjmallett info.group_index = 0; 4045215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4046215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4047215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4048215976Sjmallett info.func = __cvmx_error_display; 4049215976Sjmallett info.user_info = (long) 4050215976Sjmallett "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n" 4051215976Sjmallett " radm_rcvd_wreq_poisoned\n"; 4052215976Sjmallett fail |= cvmx_error_add(&info); 4053215976Sjmallett 4054215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4055215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(0); 4056215976Sjmallett info.status_mask = 1ull<<30 /* ecrc_e */; 4057215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0); 4058215976Sjmallett info.enable_mask = 1ull<<30 /* ecrc_e */; 4059215976Sjmallett info.flags = 0; 4060215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4061215976Sjmallett info.group_index = 0; 4062215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4063215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4064215976Sjmallett info.parent.status_mask = 1ull<<57 /* c0_exc */; 4065215976Sjmallett info.func = __cvmx_error_display; 4066215976Sjmallett info.user_info = (long) 4067215976Sjmallett "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n" 4068215976Sjmallett " radm_ecrc_err\n"; 4069215976Sjmallett fail |= cvmx_error_add(&info); 4070215976Sjmallett 4071215976Sjmallett /* CVMX_PESCX_DBG_INFO(1) */ 4072215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4073215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4074215976Sjmallett info.status_mask = 1ull<<0 /* spoison */; 4075215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4076215976Sjmallett info.enable_mask = 1ull<<0 /* spoison */; 4077215976Sjmallett info.flags = 0; 4078215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4079215976Sjmallett info.group_index = 1; 4080215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4081215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4082215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4083215976Sjmallett info.func = __cvmx_error_display; 4084215976Sjmallett info.user_info = (long) 4085215976Sjmallett "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n" 4086215976Sjmallett " peai__client0_tlp_ep & peai__client0_tlp_hv\n"; 4087215976Sjmallett fail |= cvmx_error_add(&info); 4088215976Sjmallett 4089215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4090215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4091215976Sjmallett info.status_mask = 1ull<<2 /* rtlplle */; 4092215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4093215976Sjmallett info.enable_mask = 1ull<<2 /* rtlplle */; 4094215976Sjmallett info.flags = 0; 4095215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4096215976Sjmallett info.group_index = 1; 4097215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4098215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4099215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4100215976Sjmallett info.func = __cvmx_error_display; 4101215976Sjmallett info.user_info = (long) 4102215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n" 4103215976Sjmallett " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n"; 4104215976Sjmallett fail |= cvmx_error_add(&info); 4105215976Sjmallett 4106215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4107215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4108215976Sjmallett info.status_mask = 1ull<<3 /* recrce */; 4109215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4110215976Sjmallett info.enable_mask = 1ull<<3 /* recrce */; 4111215976Sjmallett info.flags = 0; 4112215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4113215976Sjmallett info.group_index = 1; 4114215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4115215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4116215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4117215976Sjmallett info.func = __cvmx_error_display; 4118215976Sjmallett info.user_info = (long) 4119215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n" 4120215976Sjmallett " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n"; 4121215976Sjmallett fail |= cvmx_error_add(&info); 4122215976Sjmallett 4123215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4124215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4125215976Sjmallett info.status_mask = 1ull<<4 /* rpoison */; 4126215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4127215976Sjmallett info.enable_mask = 1ull<<4 /* rpoison */; 4128215976Sjmallett info.flags = 0; 4129215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4130215976Sjmallett info.group_index = 1; 4131215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4132215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4133215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4134215976Sjmallett info.func = __cvmx_error_display; 4135215976Sjmallett info.user_info = (long) 4136215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n" 4137215976Sjmallett " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n"; 4138215976Sjmallett fail |= cvmx_error_add(&info); 4139215976Sjmallett 4140215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4141215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4142215976Sjmallett info.status_mask = 1ull<<5 /* rcemrc */; 4143215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4144215976Sjmallett info.enable_mask = 1ull<<5 /* rcemrc */; 4145215976Sjmallett info.flags = 0; 4146215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4147215976Sjmallett info.group_index = 1; 4148215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4149215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4150215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4151215976Sjmallett info.func = __cvmx_error_display; 4152215976Sjmallett info.user_info = (long) 4153215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n" 4154215976Sjmallett " pedc_radm_correctable_err\n"; 4155215976Sjmallett fail |= cvmx_error_add(&info); 4156215976Sjmallett 4157215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4158215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4159215976Sjmallett info.status_mask = 1ull<<6 /* rnfemrc */; 4160215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4161215976Sjmallett info.enable_mask = 1ull<<6 /* rnfemrc */; 4162215976Sjmallett info.flags = 0; 4163215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4164215976Sjmallett info.group_index = 1; 4165215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4166215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4167215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4168215976Sjmallett info.func = __cvmx_error_display; 4169215976Sjmallett info.user_info = (long) 4170215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n" 4171215976Sjmallett " pedc_radm_nonfatal_err\n"; 4172215976Sjmallett fail |= cvmx_error_add(&info); 4173215976Sjmallett 4174215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4175215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4176215976Sjmallett info.status_mask = 1ull<<7 /* rfemrc */; 4177215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4178215976Sjmallett info.enable_mask = 1ull<<7 /* rfemrc */; 4179215976Sjmallett info.flags = 0; 4180215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4181215976Sjmallett info.group_index = 1; 4182215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4183215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4184215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4185215976Sjmallett info.func = __cvmx_error_display; 4186215976Sjmallett info.user_info = (long) 4187215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n" 4188215976Sjmallett " pedc_radm_fatal_err\n" 4189215976Sjmallett " Bit set when a message with ERR_FATAL is set.\n"; 4190215976Sjmallett fail |= cvmx_error_add(&info); 4191215976Sjmallett 4192215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4193215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4194215976Sjmallett info.status_mask = 1ull<<8 /* rpmerc */; 4195215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4196215976Sjmallett info.enable_mask = 1ull<<8 /* rpmerc */; 4197215976Sjmallett info.flags = 0; 4198215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4199215976Sjmallett info.group_index = 1; 4200215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4201215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4202215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4203215976Sjmallett info.func = __cvmx_error_display; 4204215976Sjmallett info.user_info = (long) 4205215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n" 4206215976Sjmallett " pedc_radm_pm_pme\n"; 4207215976Sjmallett fail |= cvmx_error_add(&info); 4208215976Sjmallett 4209215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4210215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4211215976Sjmallett info.status_mask = 1ull<<9 /* rptamrc */; 4212215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4213215976Sjmallett info.enable_mask = 1ull<<9 /* rptamrc */; 4214215976Sjmallett info.flags = 0; 4215215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4216215976Sjmallett info.group_index = 1; 4217215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4218215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4219215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4220215976Sjmallett info.func = __cvmx_error_display; 4221215976Sjmallett info.user_info = (long) 4222215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n" 4223215976Sjmallett " (RC Mode only)\n" 4224215976Sjmallett " pedc_radm_pm_to_ack\n"; 4225215976Sjmallett fail |= cvmx_error_add(&info); 4226215976Sjmallett 4227215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4228215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4229215976Sjmallett info.status_mask = 1ull<<10 /* rumep */; 4230215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4231215976Sjmallett info.enable_mask = 1ull<<10 /* rumep */; 4232215976Sjmallett info.flags = 0; 4233215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4234215976Sjmallett info.group_index = 1; 4235215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4236215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4237215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4238215976Sjmallett info.func = __cvmx_error_display; 4239215976Sjmallett info.user_info = (long) 4240215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n" 4241215976Sjmallett " pedc_radm_msg_unlock\n"; 4242215976Sjmallett fail |= cvmx_error_add(&info); 4243215976Sjmallett 4244215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4245215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4246215976Sjmallett info.status_mask = 1ull<<11 /* rvdm */; 4247215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4248215976Sjmallett info.enable_mask = 1ull<<11 /* rvdm */; 4249215976Sjmallett info.flags = 0; 4250215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4251215976Sjmallett info.group_index = 1; 4252215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4253215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4254215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4255215976Sjmallett info.func = __cvmx_error_display; 4256215976Sjmallett info.user_info = (long) 4257215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n" 4258215976Sjmallett " pedc_radm_vendor_msg\n"; 4259215976Sjmallett fail |= cvmx_error_add(&info); 4260215976Sjmallett 4261215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4262215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4263215976Sjmallett info.status_mask = 1ull<<12 /* acto */; 4264215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4265215976Sjmallett info.enable_mask = 1ull<<12 /* acto */; 4266215976Sjmallett info.flags = 0; 4267215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4268215976Sjmallett info.group_index = 1; 4269215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4270215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4271215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4272215976Sjmallett info.func = __cvmx_error_display; 4273215976Sjmallett info.user_info = (long) 4274215976Sjmallett "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n" 4275215976Sjmallett " pedc_radm_cpl_timeout\n"; 4276215976Sjmallett fail |= cvmx_error_add(&info); 4277215976Sjmallett 4278215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4279215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4280215976Sjmallett info.status_mask = 1ull<<13 /* rte */; 4281215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4282215976Sjmallett info.enable_mask = 1ull<<13 /* rte */; 4283215976Sjmallett info.flags = 0; 4284215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4285215976Sjmallett info.group_index = 1; 4286215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4287215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4288215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4289215976Sjmallett info.func = __cvmx_error_display; 4290215976Sjmallett info.user_info = (long) 4291215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n" 4292215976Sjmallett " xdlh_replay_timeout_err\n" 4293215976Sjmallett " This bit is set when the REPLAY_TIMER expires in\n" 4294215976Sjmallett " the PCIE core. The probability of this bit being\n" 4295215976Sjmallett " set will increase with the traffic load.\n"; 4296215976Sjmallett fail |= cvmx_error_add(&info); 4297215976Sjmallett 4298215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4299215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4300215976Sjmallett info.status_mask = 1ull<<14 /* mre */; 4301215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4302215976Sjmallett info.enable_mask = 1ull<<14 /* mre */; 4303215976Sjmallett info.flags = 0; 4304215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4305215976Sjmallett info.group_index = 1; 4306215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4307215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4308215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4309215976Sjmallett info.func = __cvmx_error_display; 4310215976Sjmallett info.user_info = (long) 4311215976Sjmallett "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n" 4312215976Sjmallett " xdlh_replay_num_rlover_err\n"; 4313215976Sjmallett fail |= cvmx_error_add(&info); 4314215976Sjmallett 4315215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4316215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4317215976Sjmallett info.status_mask = 1ull<<15 /* rdwdle */; 4318215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4319215976Sjmallett info.enable_mask = 1ull<<15 /* rdwdle */; 4320215976Sjmallett info.flags = 0; 4321215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4322215976Sjmallett info.group_index = 1; 4323215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4324215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4325215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4326215976Sjmallett info.func = __cvmx_error_display; 4327215976Sjmallett info.user_info = (long) 4328215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n" 4329215976Sjmallett " rdlh_bad_dllp_err\n"; 4330215976Sjmallett fail |= cvmx_error_add(&info); 4331215976Sjmallett 4332215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4333215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4334215976Sjmallett info.status_mask = 1ull<<16 /* rtwdle */; 4335215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4336215976Sjmallett info.enable_mask = 1ull<<16 /* rtwdle */; 4337215976Sjmallett info.flags = 0; 4338215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4339215976Sjmallett info.group_index = 1; 4340215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4341215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4342215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4343215976Sjmallett info.func = __cvmx_error_display; 4344215976Sjmallett info.user_info = (long) 4345215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n" 4346215976Sjmallett " rdlh_bad_tlp_err\n"; 4347215976Sjmallett fail |= cvmx_error_add(&info); 4348215976Sjmallett 4349215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4350215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4351215976Sjmallett info.status_mask = 1ull<<17 /* dpeoosd */; 4352215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4353215976Sjmallett info.enable_mask = 1ull<<17 /* dpeoosd */; 4354215976Sjmallett info.flags = 0; 4355215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4356215976Sjmallett info.group_index = 1; 4357215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4358215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4359215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4360215976Sjmallett info.func = __cvmx_error_display; 4361215976Sjmallett info.user_info = (long) 4362215976Sjmallett "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n" 4363215976Sjmallett " rdlh_prot_err\n"; 4364215976Sjmallett fail |= cvmx_error_add(&info); 4365215976Sjmallett 4366215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4367215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4368215976Sjmallett info.status_mask = 1ull<<18 /* fcpvwt */; 4369215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4370215976Sjmallett info.enable_mask = 1ull<<18 /* fcpvwt */; 4371215976Sjmallett info.flags = 0; 4372215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4373215976Sjmallett info.group_index = 1; 4374215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4375215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4376215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4377215976Sjmallett info.func = __cvmx_error_display; 4378215976Sjmallett info.user_info = (long) 4379215976Sjmallett "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n" 4380215976Sjmallett " rtlh_fc_prot_err\n"; 4381215976Sjmallett fail |= cvmx_error_add(&info); 4382215976Sjmallett 4383215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4384215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4385215976Sjmallett info.status_mask = 1ull<<19 /* rpe */; 4386215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4387215976Sjmallett info.enable_mask = 1ull<<19 /* rpe */; 4388215976Sjmallett info.flags = 0; 4389215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4390215976Sjmallett info.group_index = 1; 4391215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4392215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4393215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4394215976Sjmallett info.func = __cvmx_error_display; 4395215976Sjmallett info.user_info = (long) 4396215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n" 4397215976Sjmallett " (RxStatus = 3b100) or disparity error\n" 4398215976Sjmallett " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n" 4399215976Sjmallett " be asserted.\n" 4400215976Sjmallett " rmlh_rcvd_err\n"; 4401215976Sjmallett fail |= cvmx_error_add(&info); 4402215976Sjmallett 4403215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4404215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4405215976Sjmallett info.status_mask = 1ull<<20 /* fcuv */; 4406215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4407215976Sjmallett info.enable_mask = 1ull<<20 /* fcuv */; 4408215976Sjmallett info.flags = 0; 4409215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4410215976Sjmallett info.group_index = 1; 4411215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4412215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4413215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4414215976Sjmallett info.func = __cvmx_error_display; 4415215976Sjmallett info.user_info = (long) 4416215976Sjmallett "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n" 4417215976Sjmallett " int_xadm_fc_prot_err\n"; 4418215976Sjmallett fail |= cvmx_error_add(&info); 4419215976Sjmallett 4420215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4421215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4422215976Sjmallett info.status_mask = 1ull<<21 /* rqo */; 4423215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4424215976Sjmallett info.enable_mask = 1ull<<21 /* rqo */; 4425215976Sjmallett info.flags = 0; 4426215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4427215976Sjmallett info.group_index = 1; 4428215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4429215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4430215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4431215976Sjmallett info.func = __cvmx_error_display; 4432215976Sjmallett info.user_info = (long) 4433215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n" 4434215976Sjmallett " flow control advertisements are ignored\n" 4435215976Sjmallett " radm_qoverflow\n"; 4436215976Sjmallett fail |= cvmx_error_add(&info); 4437215976Sjmallett 4438215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4439215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4440215976Sjmallett info.status_mask = 1ull<<22 /* rauc */; 4441215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4442215976Sjmallett info.enable_mask = 1ull<<22 /* rauc */; 4443215976Sjmallett info.flags = 0; 4444215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4445215976Sjmallett info.group_index = 1; 4446215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4447215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4448215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4449215976Sjmallett info.func = __cvmx_error_display; 4450215976Sjmallett info.user_info = (long) 4451215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n" 4452215976Sjmallett " radm_unexp_cpl_err\n"; 4453215976Sjmallett fail |= cvmx_error_add(&info); 4454215976Sjmallett 4455215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4456215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4457215976Sjmallett info.status_mask = 1ull<<23 /* racur */; 4458215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4459215976Sjmallett info.enable_mask = 1ull<<23 /* racur */; 4460215976Sjmallett info.flags = 0; 4461215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4462215976Sjmallett info.group_index = 1; 4463215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4464215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4465215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4466215976Sjmallett info.func = __cvmx_error_display; 4467215976Sjmallett info.user_info = (long) 4468215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n" 4469215976Sjmallett " radm_rcvd_cpl_ur\n"; 4470215976Sjmallett fail |= cvmx_error_add(&info); 4471215976Sjmallett 4472215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4473215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4474215976Sjmallett info.status_mask = 1ull<<24 /* racca */; 4475215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4476215976Sjmallett info.enable_mask = 1ull<<24 /* racca */; 4477215976Sjmallett info.flags = 0; 4478215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4479215976Sjmallett info.group_index = 1; 4480215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4481215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4482215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4483215976Sjmallett info.func = __cvmx_error_display; 4484215976Sjmallett info.user_info = (long) 4485215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n" 4486215976Sjmallett " radm_rcvd_cpl_ca\n"; 4487215976Sjmallett fail |= cvmx_error_add(&info); 4488215976Sjmallett 4489215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4490215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4491215976Sjmallett info.status_mask = 1ull<<25 /* caar */; 4492215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4493215976Sjmallett info.enable_mask = 1ull<<25 /* caar */; 4494215976Sjmallett info.flags = 0; 4495215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4496215976Sjmallett info.group_index = 1; 4497215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4498215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4499215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4500215976Sjmallett info.func = __cvmx_error_display; 4501215976Sjmallett info.user_info = (long) 4502215976Sjmallett "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n" 4503215976Sjmallett " radm_rcvd_ca_req\n" 4504215976Sjmallett " This bit will never be set because Octeon does\n" 4505215976Sjmallett " not generate Completer Aborts.\n"; 4506215976Sjmallett fail |= cvmx_error_add(&info); 4507215976Sjmallett 4508215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4509215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4510215976Sjmallett info.status_mask = 1ull<<26 /* rarwdns */; 4511215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4512215976Sjmallett info.enable_mask = 1ull<<26 /* rarwdns */; 4513215976Sjmallett info.flags = 0; 4514215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4515215976Sjmallett info.group_index = 1; 4516215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4517215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4518215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4519215976Sjmallett info.func = __cvmx_error_display; 4520215976Sjmallett info.user_info = (long) 4521215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n" 4522215976Sjmallett " radm_rcvd_ur_req\n"; 4523215976Sjmallett fail |= cvmx_error_add(&info); 4524215976Sjmallett 4525215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4526215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4527215976Sjmallett info.status_mask = 1ull<<27 /* ramtlp */; 4528215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4529215976Sjmallett info.enable_mask = 1ull<<27 /* ramtlp */; 4530215976Sjmallett info.flags = 0; 4531215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4532215976Sjmallett info.group_index = 1; 4533215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4534215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4535215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4536215976Sjmallett info.func = __cvmx_error_display; 4537215976Sjmallett info.user_info = (long) 4538215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n" 4539215976Sjmallett " radm_mlf_tlp_err\n"; 4540215976Sjmallett fail |= cvmx_error_add(&info); 4541215976Sjmallett 4542215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4543215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4544215976Sjmallett info.status_mask = 1ull<<28 /* racpp */; 4545215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4546215976Sjmallett info.enable_mask = 1ull<<28 /* racpp */; 4547215976Sjmallett info.flags = 0; 4548215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4549215976Sjmallett info.group_index = 1; 4550215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4551215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4552215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4553215976Sjmallett info.func = __cvmx_error_display; 4554215976Sjmallett info.user_info = (long) 4555215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n" 4556215976Sjmallett " radm_rcvd_cpl_poisoned\n"; 4557215976Sjmallett fail |= cvmx_error_add(&info); 4558215976Sjmallett 4559215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4560215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4561215976Sjmallett info.status_mask = 1ull<<29 /* rawwpp */; 4562215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4563215976Sjmallett info.enable_mask = 1ull<<29 /* rawwpp */; 4564215976Sjmallett info.flags = 0; 4565215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4566215976Sjmallett info.group_index = 1; 4567215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4568215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4569215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4570215976Sjmallett info.func = __cvmx_error_display; 4571215976Sjmallett info.user_info = (long) 4572215976Sjmallett "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n" 4573215976Sjmallett " radm_rcvd_wreq_poisoned\n"; 4574215976Sjmallett fail |= cvmx_error_add(&info); 4575215976Sjmallett 4576215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4577215976Sjmallett info.status_addr = CVMX_PESCX_DBG_INFO(1); 4578215976Sjmallett info.status_mask = 1ull<<30 /* ecrc_e */; 4579215976Sjmallett info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1); 4580215976Sjmallett info.enable_mask = 1ull<<30 /* ecrc_e */; 4581215976Sjmallett info.flags = 0; 4582215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 4583215976Sjmallett info.group_index = 1; 4584215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4585215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM; 4586215976Sjmallett info.parent.status_mask = 1ull<<58 /* c1_exc */; 4587215976Sjmallett info.func = __cvmx_error_display; 4588215976Sjmallett info.user_info = (long) 4589215976Sjmallett "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n" 4590215976Sjmallett " radm_ecrc_err\n"; 4591215976Sjmallett fail |= cvmx_error_add(&info); 4592215976Sjmallett 4593215976Sjmallett /* CVMX_RAD_REG_ERROR */ 4594215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4595215976Sjmallett info.status_addr = CVMX_RAD_REG_ERROR; 4596215976Sjmallett info.status_mask = 1ull<<0 /* doorbell */; 4597215976Sjmallett info.enable_addr = CVMX_RAD_REG_INT_MASK; 4598215976Sjmallett info.enable_mask = 1ull<<0 /* doorbell */; 4599215976Sjmallett info.flags = 0; 4600215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4601215976Sjmallett info.group_index = 0; 4602215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4603215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4604215976Sjmallett info.parent.status_mask = 1ull<<14 /* rad */; 4605215976Sjmallett info.func = __cvmx_error_display; 4606215976Sjmallett info.user_info = (long) 4607215976Sjmallett "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 4608215976Sjmallett fail |= cvmx_error_add(&info); 4609215976Sjmallett 4610215976Sjmallett /* CVMX_PKO_REG_ERROR */ 4611215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4612215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 4613215976Sjmallett info.status_mask = 1ull<<0 /* parity */; 4614215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 4615215976Sjmallett info.enable_mask = 1ull<<0 /* parity */; 4616215976Sjmallett info.flags = 0; 4617215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4618215976Sjmallett info.group_index = 0; 4619215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4620215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4621215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 4622215976Sjmallett info.func = __cvmx_error_display; 4623215976Sjmallett info.user_info = (long) 4624215976Sjmallett "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n"; 4625215976Sjmallett fail |= cvmx_error_add(&info); 4626215976Sjmallett 4627215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4628215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 4629215976Sjmallett info.status_mask = 1ull<<1 /* doorbell */; 4630215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 4631215976Sjmallett info.enable_mask = 1ull<<1 /* doorbell */; 4632215976Sjmallett info.flags = 0; 4633215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4634215976Sjmallett info.group_index = 0; 4635215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4636215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4637215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 4638215976Sjmallett info.func = __cvmx_error_display; 4639215976Sjmallett info.user_info = (long) 4640215976Sjmallett "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 4641215976Sjmallett fail |= cvmx_error_add(&info); 4642215976Sjmallett 4643215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4644215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 4645215976Sjmallett info.status_mask = 1ull<<2 /* currzero */; 4646215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 4647215976Sjmallett info.enable_mask = 1ull<<2 /* currzero */; 4648215976Sjmallett info.flags = 0; 4649215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4650215976Sjmallett info.group_index = 0; 4651215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4652215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4653215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 4654215976Sjmallett info.func = __cvmx_error_display; 4655215976Sjmallett info.user_info = (long) 4656215976Sjmallett "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n"; 4657215976Sjmallett fail |= cvmx_error_add(&info); 4658215976Sjmallett 4659215976Sjmallett /* CVMX_PCSX_INTX_REG(0,0) */ 4660215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4661215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 4662215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 4663215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 4664215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 4665215976Sjmallett info.flags = 0; 4666215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4667215976Sjmallett info.group_index = 0; 4668215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4669215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4670215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4671215976Sjmallett info.func = __cvmx_error_display; 4672215976Sjmallett info.user_info = (long) 4673215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 4674215976Sjmallett fail |= cvmx_error_add(&info); 4675215976Sjmallett 4676215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4677215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 4678215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 4679215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 4680215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 4681215976Sjmallett info.flags = 0; 4682215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4683215976Sjmallett info.group_index = 0; 4684215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4685215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4686215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4687215976Sjmallett info.func = __cvmx_error_display; 4688215976Sjmallett info.user_info = (long) 4689215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 4690215976Sjmallett " condition\n"; 4691215976Sjmallett fail |= cvmx_error_add(&info); 4692215976Sjmallett 4693215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4694215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 4695215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 4696215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 4697215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 4698215976Sjmallett info.flags = 0; 4699215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4700215976Sjmallett info.group_index = 0; 4701215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4702215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4703215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4704215976Sjmallett info.func = __cvmx_error_display; 4705215976Sjmallett info.user_info = (long) 4706215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 4707215976Sjmallett " condition\n"; 4708215976Sjmallett fail |= cvmx_error_add(&info); 4709215976Sjmallett 4710215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4711215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 4712215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 4713215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 4714215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 4715215976Sjmallett info.flags = 0; 4716215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4717215976Sjmallett info.group_index = 0; 4718215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4719215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4720215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4721215976Sjmallett info.func = __cvmx_error_display; 4722215976Sjmallett info.user_info = (long) 4723215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 4724215976Sjmallett " state. Should never be set during normal operation\n"; 4725215976Sjmallett fail |= cvmx_error_add(&info); 4726215976Sjmallett 4727215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4728215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 4729215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 4730215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 4731215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 4732215976Sjmallett info.flags = 0; 4733215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4734215976Sjmallett info.group_index = 0; 4735215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4736215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4737215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4738215976Sjmallett info.func = __cvmx_error_display; 4739215976Sjmallett info.user_info = (long) 4740215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 4741215976Sjmallett " state. Should never be set during normal operation\n"; 4742215976Sjmallett fail |= cvmx_error_add(&info); 4743215976Sjmallett 4744215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4745215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 4746215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 4747215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 4748215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 4749215976Sjmallett info.flags = 0; 4750215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4751215976Sjmallett info.group_index = 0; 4752215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4753215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4754215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4755215976Sjmallett info.func = __cvmx_error_display; 4756215976Sjmallett info.user_info = (long) 4757215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 4758215976Sjmallett " failure occurs\n" 4759215976Sjmallett " Cannot fire in loopback1 mode\n"; 4760215976Sjmallett fail |= cvmx_error_add(&info); 4761215976Sjmallett 4762215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4763215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 4764215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 4765215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 4766215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 4767215976Sjmallett info.flags = 0; 4768215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4769215976Sjmallett info.group_index = 0; 4770215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4771215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4772215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4773215976Sjmallett info.func = __cvmx_error_display; 4774215976Sjmallett info.user_info = (long) 4775215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 4776215976Sjmallett " state. Should never be set during normal operation\n"; 4777215976Sjmallett fail |= cvmx_error_add(&info); 4778215976Sjmallett 4779215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4780215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 4781215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 4782215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 4783215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 4784215976Sjmallett info.flags = 0; 4785215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4786215976Sjmallett info.group_index = 0; 4787215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4788215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4789215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4790215976Sjmallett info.func = __cvmx_error_display; 4791215976Sjmallett info.user_info = (long) 4792215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 4793215976Sjmallett " state. Should never be set during normal operation\n"; 4794215976Sjmallett fail |= cvmx_error_add(&info); 4795215976Sjmallett 4796215976Sjmallett /* CVMX_PCSX_INTX_REG(1,0) */ 4797215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4798215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 4799215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 4800215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 4801215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 4802215976Sjmallett info.flags = 0; 4803215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4804215976Sjmallett info.group_index = 1; 4805215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4806215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4807215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4808215976Sjmallett info.func = __cvmx_error_display; 4809215976Sjmallett info.user_info = (long) 4810215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 4811215976Sjmallett fail |= cvmx_error_add(&info); 4812215976Sjmallett 4813215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4814215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 4815215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 4816215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 4817215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 4818215976Sjmallett info.flags = 0; 4819215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4820215976Sjmallett info.group_index = 1; 4821215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4822215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4823215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4824215976Sjmallett info.func = __cvmx_error_display; 4825215976Sjmallett info.user_info = (long) 4826215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 4827215976Sjmallett " condition\n"; 4828215976Sjmallett fail |= cvmx_error_add(&info); 4829215976Sjmallett 4830215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4831215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 4832215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 4833215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 4834215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 4835215976Sjmallett info.flags = 0; 4836215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4837215976Sjmallett info.group_index = 1; 4838215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4839215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4840215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4841215976Sjmallett info.func = __cvmx_error_display; 4842215976Sjmallett info.user_info = (long) 4843215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 4844215976Sjmallett " condition\n"; 4845215976Sjmallett fail |= cvmx_error_add(&info); 4846215976Sjmallett 4847215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4848215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 4849215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 4850215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 4851215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 4852215976Sjmallett info.flags = 0; 4853215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4854215976Sjmallett info.group_index = 1; 4855215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4856215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4857215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4858215976Sjmallett info.func = __cvmx_error_display; 4859215976Sjmallett info.user_info = (long) 4860215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 4861215976Sjmallett " state. Should never be set during normal operation\n"; 4862215976Sjmallett fail |= cvmx_error_add(&info); 4863215976Sjmallett 4864215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4865215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 4866215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 4867215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 4868215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 4869215976Sjmallett info.flags = 0; 4870215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4871215976Sjmallett info.group_index = 1; 4872215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4873215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4874215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4875215976Sjmallett info.func = __cvmx_error_display; 4876215976Sjmallett info.user_info = (long) 4877215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 4878215976Sjmallett " state. Should never be set during normal operation\n"; 4879215976Sjmallett fail |= cvmx_error_add(&info); 4880215976Sjmallett 4881215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4882215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 4883215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 4884215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 4885215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 4886215976Sjmallett info.flags = 0; 4887215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4888215976Sjmallett info.group_index = 1; 4889215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4890215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4891215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4892215976Sjmallett info.func = __cvmx_error_display; 4893215976Sjmallett info.user_info = (long) 4894215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 4895215976Sjmallett " failure occurs\n" 4896215976Sjmallett " Cannot fire in loopback1 mode\n"; 4897215976Sjmallett fail |= cvmx_error_add(&info); 4898215976Sjmallett 4899215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4900215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 4901215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 4902215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 4903215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 4904215976Sjmallett info.flags = 0; 4905215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4906215976Sjmallett info.group_index = 1; 4907215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4908215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4909215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4910215976Sjmallett info.func = __cvmx_error_display; 4911215976Sjmallett info.user_info = (long) 4912215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 4913215976Sjmallett " state. Should never be set during normal operation\n"; 4914215976Sjmallett fail |= cvmx_error_add(&info); 4915215976Sjmallett 4916215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4917215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 4918215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 4919215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 4920215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 4921215976Sjmallett info.flags = 0; 4922215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4923215976Sjmallett info.group_index = 1; 4924215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4925215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4926215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4927215976Sjmallett info.func = __cvmx_error_display; 4928215976Sjmallett info.user_info = (long) 4929215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 4930215976Sjmallett " state. Should never be set during normal operation\n"; 4931215976Sjmallett fail |= cvmx_error_add(&info); 4932215976Sjmallett 4933215976Sjmallett /* CVMX_PCSX_INTX_REG(2,0) */ 4934215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4935215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 4936215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 4937215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 4938215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 4939215976Sjmallett info.flags = 0; 4940215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4941215976Sjmallett info.group_index = 2; 4942215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4943215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4944215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4945215976Sjmallett info.func = __cvmx_error_display; 4946215976Sjmallett info.user_info = (long) 4947215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 4948215976Sjmallett fail |= cvmx_error_add(&info); 4949215976Sjmallett 4950215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4951215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 4952215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 4953215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 4954215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 4955215976Sjmallett info.flags = 0; 4956215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4957215976Sjmallett info.group_index = 2; 4958215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4959215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4960215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4961215976Sjmallett info.func = __cvmx_error_display; 4962215976Sjmallett info.user_info = (long) 4963215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 4964215976Sjmallett " condition\n"; 4965215976Sjmallett fail |= cvmx_error_add(&info); 4966215976Sjmallett 4967215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4968215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 4969215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 4970215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 4971215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 4972215976Sjmallett info.flags = 0; 4973215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4974215976Sjmallett info.group_index = 2; 4975215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4976215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4977215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4978215976Sjmallett info.func = __cvmx_error_display; 4979215976Sjmallett info.user_info = (long) 4980215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 4981215976Sjmallett " condition\n"; 4982215976Sjmallett fail |= cvmx_error_add(&info); 4983215976Sjmallett 4984215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4985215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 4986215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 4987215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 4988215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 4989215976Sjmallett info.flags = 0; 4990215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4991215976Sjmallett info.group_index = 2; 4992215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4993215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 4994215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 4995215976Sjmallett info.func = __cvmx_error_display; 4996215976Sjmallett info.user_info = (long) 4997215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 4998215976Sjmallett " state. Should never be set during normal operation\n"; 4999215976Sjmallett fail |= cvmx_error_add(&info); 5000215976Sjmallett 5001215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5002215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5003215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5004215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5005215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5006215976Sjmallett info.flags = 0; 5007215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5008215976Sjmallett info.group_index = 2; 5009215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5010215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5011215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5012215976Sjmallett info.func = __cvmx_error_display; 5013215976Sjmallett info.user_info = (long) 5014215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5015215976Sjmallett " state. Should never be set during normal operation\n"; 5016215976Sjmallett fail |= cvmx_error_add(&info); 5017215976Sjmallett 5018215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5019215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5020215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5021215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5022215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5023215976Sjmallett info.flags = 0; 5024215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5025215976Sjmallett info.group_index = 2; 5026215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5027215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5028215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5029215976Sjmallett info.func = __cvmx_error_display; 5030215976Sjmallett info.user_info = (long) 5031215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5032215976Sjmallett " failure occurs\n" 5033215976Sjmallett " Cannot fire in loopback1 mode\n"; 5034215976Sjmallett fail |= cvmx_error_add(&info); 5035215976Sjmallett 5036215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5037215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5038215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5039215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5040215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5041215976Sjmallett info.flags = 0; 5042215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5043215976Sjmallett info.group_index = 2; 5044215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5045215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5046215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5047215976Sjmallett info.func = __cvmx_error_display; 5048215976Sjmallett info.user_info = (long) 5049215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5050215976Sjmallett " state. Should never be set during normal operation\n"; 5051215976Sjmallett fail |= cvmx_error_add(&info); 5052215976Sjmallett 5053215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5054215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 5055215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5056215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 5057215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5058215976Sjmallett info.flags = 0; 5059215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5060215976Sjmallett info.group_index = 2; 5061215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5062215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5063215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5064215976Sjmallett info.func = __cvmx_error_display; 5065215976Sjmallett info.user_info = (long) 5066215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5067215976Sjmallett " state. Should never be set during normal operation\n"; 5068215976Sjmallett fail |= cvmx_error_add(&info); 5069215976Sjmallett 5070215976Sjmallett /* CVMX_PCSX_INTX_REG(3,0) */ 5071215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5072215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5073215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 5074215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5075215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 5076215976Sjmallett info.flags = 0; 5077215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5078215976Sjmallett info.group_index = 3; 5079215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5080215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5081215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5082215976Sjmallett info.func = __cvmx_error_display; 5083215976Sjmallett info.user_info = (long) 5084215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 5085215976Sjmallett fail |= cvmx_error_add(&info); 5086215976Sjmallett 5087215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5088215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5089215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 5090215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5091215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 5092215976Sjmallett info.flags = 0; 5093215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5094215976Sjmallett info.group_index = 3; 5095215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5096215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5097215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5098215976Sjmallett info.func = __cvmx_error_display; 5099215976Sjmallett info.user_info = (long) 5100215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 5101215976Sjmallett " condition\n"; 5102215976Sjmallett fail |= cvmx_error_add(&info); 5103215976Sjmallett 5104215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5105215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5106215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 5107215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5108215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 5109215976Sjmallett info.flags = 0; 5110215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5111215976Sjmallett info.group_index = 3; 5112215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5113215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5114215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5115215976Sjmallett info.func = __cvmx_error_display; 5116215976Sjmallett info.user_info = (long) 5117215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 5118215976Sjmallett " condition\n"; 5119215976Sjmallett fail |= cvmx_error_add(&info); 5120215976Sjmallett 5121215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5122215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5123215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 5124215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5125215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 5126215976Sjmallett info.flags = 0; 5127215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5128215976Sjmallett info.group_index = 3; 5129215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5130215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5131215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5132215976Sjmallett info.func = __cvmx_error_display; 5133215976Sjmallett info.user_info = (long) 5134215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 5135215976Sjmallett " state. Should never be set during normal operation\n"; 5136215976Sjmallett fail |= cvmx_error_add(&info); 5137215976Sjmallett 5138215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5139215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5140215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 5141215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5142215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 5143215976Sjmallett info.flags = 0; 5144215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5145215976Sjmallett info.group_index = 3; 5146215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5147215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5148215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5149215976Sjmallett info.func = __cvmx_error_display; 5150215976Sjmallett info.user_info = (long) 5151215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 5152215976Sjmallett " state. Should never be set during normal operation\n"; 5153215976Sjmallett fail |= cvmx_error_add(&info); 5154215976Sjmallett 5155215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5156215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5157215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 5158215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5159215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 5160215976Sjmallett info.flags = 0; 5161215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5162215976Sjmallett info.group_index = 3; 5163215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5164215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5165215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5166215976Sjmallett info.func = __cvmx_error_display; 5167215976Sjmallett info.user_info = (long) 5168215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 5169215976Sjmallett " failure occurs\n" 5170215976Sjmallett " Cannot fire in loopback1 mode\n"; 5171215976Sjmallett fail |= cvmx_error_add(&info); 5172215976Sjmallett 5173215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5174215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5175215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 5176215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5177215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 5178215976Sjmallett info.flags = 0; 5179215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5180215976Sjmallett info.group_index = 3; 5181215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5182215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5183215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5184215976Sjmallett info.func = __cvmx_error_display; 5185215976Sjmallett info.user_info = (long) 5186215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 5187215976Sjmallett " state. Should never be set during normal operation\n"; 5188215976Sjmallett fail |= cvmx_error_add(&info); 5189215976Sjmallett 5190215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5191215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 5192215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 5193215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 5194215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 5195215976Sjmallett info.flags = 0; 5196215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5197215976Sjmallett info.group_index = 3; 5198215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5199215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5200215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5201215976Sjmallett info.func = __cvmx_error_display; 5202215976Sjmallett info.user_info = (long) 5203215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 5204215976Sjmallett " state. Should never be set during normal operation\n"; 5205215976Sjmallett fail |= cvmx_error_add(&info); 5206215976Sjmallett 5207215976Sjmallett /* CVMX_PCSXX_INT_REG(0) */ 5208215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5209215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5210215976Sjmallett info.status_mask = 1ull<<0 /* txflt */; 5211215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5212215976Sjmallett info.enable_mask = 1ull<<0 /* txflt_en */; 5213215976Sjmallett info.flags = 0; 5214215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5215215976Sjmallett info.group_index = 0; 5216215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5217215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5218215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5219215976Sjmallett info.func = __cvmx_error_display; 5220215976Sjmallett info.user_info = (long) 5221215976Sjmallett "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n"; 5222215976Sjmallett fail |= cvmx_error_add(&info); 5223215976Sjmallett 5224215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5225215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5226215976Sjmallett info.status_mask = 1ull<<1 /* rxbad */; 5227215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5228215976Sjmallett info.enable_mask = 1ull<<1 /* rxbad_en */; 5229215976Sjmallett info.flags = 0; 5230215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5231215976Sjmallett info.group_index = 0; 5232215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5233215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5234215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5235215976Sjmallett info.func = __cvmx_error_display; 5236215976Sjmallett info.user_info = (long) 5237215976Sjmallett "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n"; 5238215976Sjmallett fail |= cvmx_error_add(&info); 5239215976Sjmallett 5240215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5241215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5242215976Sjmallett info.status_mask = 1ull<<2 /* rxsynbad */; 5243215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5244215976Sjmallett info.enable_mask = 1ull<<2 /* rxsynbad_en */; 5245215976Sjmallett info.flags = 0; 5246215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5247215976Sjmallett info.group_index = 0; 5248215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5249215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5250215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5251215976Sjmallett info.func = __cvmx_error_display; 5252215976Sjmallett info.user_info = (long) 5253215976Sjmallett "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n" 5254215976Sjmallett " in one of the 4 xaui lanes\n"; 5255215976Sjmallett fail |= cvmx_error_add(&info); 5256215976Sjmallett 5257215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5258215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5259215976Sjmallett info.status_mask = 1ull<<4 /* synlos */; 5260215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5261215976Sjmallett info.enable_mask = 1ull<<4 /* synlos_en */; 5262215976Sjmallett info.flags = 0; 5263215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5264215976Sjmallett info.group_index = 0; 5265215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5266215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5267215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5268215976Sjmallett info.func = __cvmx_error_display; 5269215976Sjmallett info.user_info = (long) 5270215976Sjmallett "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n"; 5271215976Sjmallett fail |= cvmx_error_add(&info); 5272215976Sjmallett 5273215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5274215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 5275215976Sjmallett info.status_mask = 1ull<<5 /* algnlos */; 5276215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 5277215976Sjmallett info.enable_mask = 1ull<<5 /* algnlos_en */; 5278215976Sjmallett info.flags = 0; 5279215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5280215976Sjmallett info.group_index = 0; 5281215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5282215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5283215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 5284215976Sjmallett info.func = __cvmx_error_display; 5285215976Sjmallett info.user_info = (long) 5286215976Sjmallett "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n"; 5287215976Sjmallett fail |= cvmx_error_add(&info); 5288215976Sjmallett 5289215976Sjmallett /* CVMX_PIP_INT_REG */ 5290215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5291215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5292215976Sjmallett info.status_mask = 1ull<<3 /* prtnxa */; 5293215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5294215976Sjmallett info.enable_mask = 1ull<<3 /* prtnxa */; 5295215976Sjmallett info.flags = 0; 5296215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5297215976Sjmallett info.group_index = 0; 5298215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5299215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5300215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5301215976Sjmallett info.func = __cvmx_error_display; 5302215976Sjmallett info.user_info = (long) 5303215976Sjmallett "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n"; 5304215976Sjmallett fail |= cvmx_error_add(&info); 5305215976Sjmallett 5306215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5307215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5308215976Sjmallett info.status_mask = 1ull<<4 /* badtag */; 5309215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5310215976Sjmallett info.enable_mask = 1ull<<4 /* badtag */; 5311215976Sjmallett info.flags = 0; 5312215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5313215976Sjmallett info.group_index = 0; 5314215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5315215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5316215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5317215976Sjmallett info.func = __cvmx_error_display; 5318215976Sjmallett info.user_info = (long) 5319215976Sjmallett "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n"; 5320215976Sjmallett fail |= cvmx_error_add(&info); 5321215976Sjmallett 5322215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5323215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5324215976Sjmallett info.status_mask = 1ull<<5 /* skprunt */; 5325215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5326215976Sjmallett info.enable_mask = 1ull<<5 /* skprunt */; 5327215976Sjmallett info.flags = 0; 5328215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5329215976Sjmallett info.group_index = 0; 5330215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5331215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5332215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5333215976Sjmallett info.func = __cvmx_error_display; 5334215976Sjmallett info.user_info = (long) 5335215976Sjmallett "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n" 5336215976Sjmallett " This interrupt can occur with received PARTIAL\n" 5337215976Sjmallett " packets that are truncated to SKIP bytes or\n" 5338215976Sjmallett " smaller.\n"; 5339215976Sjmallett fail |= cvmx_error_add(&info); 5340215976Sjmallett 5341215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5342215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5343215976Sjmallett info.status_mask = 1ull<<6 /* todoovr */; 5344215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5345215976Sjmallett info.enable_mask = 1ull<<6 /* todoovr */; 5346215976Sjmallett info.flags = 0; 5347215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5348215976Sjmallett info.group_index = 0; 5349215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5350215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5351215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5352215976Sjmallett info.func = __cvmx_error_display; 5353215976Sjmallett info.user_info = (long) 5354215976Sjmallett "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n"; 5355215976Sjmallett fail |= cvmx_error_add(&info); 5356215976Sjmallett 5357215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5358215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5359215976Sjmallett info.status_mask = 1ull<<7 /* feperr */; 5360215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5361215976Sjmallett info.enable_mask = 1ull<<7 /* feperr */; 5362215976Sjmallett info.flags = 0; 5363215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5364215976Sjmallett info.group_index = 0; 5365215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5366215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5367215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5368215976Sjmallett info.func = __cvmx_error_display; 5369215976Sjmallett info.user_info = (long) 5370215976Sjmallett "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n"; 5371215976Sjmallett fail |= cvmx_error_add(&info); 5372215976Sjmallett 5373215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5374215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5375215976Sjmallett info.status_mask = 1ull<<8 /* beperr */; 5376215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5377215976Sjmallett info.enable_mask = 1ull<<8 /* beperr */; 5378215976Sjmallett info.flags = 0; 5379215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5380215976Sjmallett info.group_index = 0; 5381215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5382215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5383215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5384215976Sjmallett info.func = __cvmx_error_display; 5385215976Sjmallett info.user_info = (long) 5386215976Sjmallett "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n"; 5387215976Sjmallett fail |= cvmx_error_add(&info); 5388215976Sjmallett 5389215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5390215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 5391215976Sjmallett info.status_mask = 1ull<<12 /* punyerr */; 5392215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 5393215976Sjmallett info.enable_mask = 1ull<<12 /* punyerr */; 5394215976Sjmallett info.flags = 0; 5395215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5396215976Sjmallett info.group_index = 0; 5397215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5398215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5399215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 5400215976Sjmallett info.func = __cvmx_error_display; 5401215976Sjmallett info.user_info = (long) 5402215976Sjmallett "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n" 5403215976Sjmallett " stripping in IPD is enable\n"; 5404215976Sjmallett fail |= cvmx_error_add(&info); 5405215976Sjmallett 5406215976Sjmallett /* CVMX_FPA_INT_SUM */ 5407215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5408215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5409215976Sjmallett info.status_mask = 1ull<<0 /* fed0_sbe */; 5410215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5411215976Sjmallett info.enable_mask = 1ull<<0 /* fed0_sbe */; 5412215976Sjmallett info.flags = 0; 5413215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5414215976Sjmallett info.group_index = 0; 5415215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5416215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5417215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5418215976Sjmallett info.func = __cvmx_error_display; 5419215976Sjmallett info.user_info = (long) 5420215976Sjmallett "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n"; 5421215976Sjmallett fail |= cvmx_error_add(&info); 5422215976Sjmallett 5423215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5424215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5425215976Sjmallett info.status_mask = 1ull<<1 /* fed0_dbe */; 5426215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5427215976Sjmallett info.enable_mask = 1ull<<1 /* fed0_dbe */; 5428215976Sjmallett info.flags = 0; 5429215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5430215976Sjmallett info.group_index = 0; 5431215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5432215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5433215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5434215976Sjmallett info.func = __cvmx_error_display; 5435215976Sjmallett info.user_info = (long) 5436215976Sjmallett "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n"; 5437215976Sjmallett fail |= cvmx_error_add(&info); 5438215976Sjmallett 5439215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5440215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5441215976Sjmallett info.status_mask = 1ull<<2 /* fed1_sbe */; 5442215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5443215976Sjmallett info.enable_mask = 1ull<<2 /* fed1_sbe */; 5444215976Sjmallett info.flags = 0; 5445215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5446215976Sjmallett info.group_index = 0; 5447215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5448215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5449215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5450215976Sjmallett info.func = __cvmx_error_display; 5451215976Sjmallett info.user_info = (long) 5452215976Sjmallett "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n"; 5453215976Sjmallett fail |= cvmx_error_add(&info); 5454215976Sjmallett 5455215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5456215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5457215976Sjmallett info.status_mask = 1ull<<3 /* fed1_dbe */; 5458215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5459215976Sjmallett info.enable_mask = 1ull<<3 /* fed1_dbe */; 5460215976Sjmallett info.flags = 0; 5461215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5462215976Sjmallett info.group_index = 0; 5463215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5464215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5465215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5466215976Sjmallett info.func = __cvmx_error_display; 5467215976Sjmallett info.user_info = (long) 5468215976Sjmallett "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n"; 5469215976Sjmallett fail |= cvmx_error_add(&info); 5470215976Sjmallett 5471215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5472215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5473215976Sjmallett info.status_mask = 1ull<<4 /* q0_und */; 5474215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5475215976Sjmallett info.enable_mask = 1ull<<4 /* q0_und */; 5476215976Sjmallett info.flags = 0; 5477215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5478215976Sjmallett info.group_index = 0; 5479215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5480215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5481215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5482215976Sjmallett info.func = __cvmx_error_display; 5483215976Sjmallett info.user_info = (long) 5484215976Sjmallett "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n" 5485215976Sjmallett " negative.\n"; 5486215976Sjmallett fail |= cvmx_error_add(&info); 5487215976Sjmallett 5488215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5489215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5490215976Sjmallett info.status_mask = 1ull<<5 /* q0_coff */; 5491215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5492215976Sjmallett info.enable_mask = 1ull<<5 /* q0_coff */; 5493215976Sjmallett info.flags = 0; 5494215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5495215976Sjmallett info.group_index = 0; 5496215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5497215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5498215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5499215976Sjmallett info.func = __cvmx_error_display; 5500215976Sjmallett info.user_info = (long) 5501215976Sjmallett "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n" 5502215976Sjmallett " the count available is greater than pointers\n" 5503215976Sjmallett " present in the FPA.\n"; 5504215976Sjmallett fail |= cvmx_error_add(&info); 5505215976Sjmallett 5506215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5507215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5508215976Sjmallett info.status_mask = 1ull<<6 /* q0_perr */; 5509215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5510215976Sjmallett info.enable_mask = 1ull<<6 /* q0_perr */; 5511215976Sjmallett info.flags = 0; 5512215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5513215976Sjmallett info.group_index = 0; 5514215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5515215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5516215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5517215976Sjmallett info.func = __cvmx_error_display; 5518215976Sjmallett info.user_info = (long) 5519215976Sjmallett "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n" 5520215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 5521215976Sjmallett fail |= cvmx_error_add(&info); 5522215976Sjmallett 5523215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5524215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5525215976Sjmallett info.status_mask = 1ull<<7 /* q1_und */; 5526215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5527215976Sjmallett info.enable_mask = 1ull<<7 /* q1_und */; 5528215976Sjmallett info.flags = 0; 5529215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5530215976Sjmallett info.group_index = 0; 5531215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5532215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5533215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5534215976Sjmallett info.func = __cvmx_error_display; 5535215976Sjmallett info.user_info = (long) 5536215976Sjmallett "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n" 5537215976Sjmallett " negative.\n"; 5538215976Sjmallett fail |= cvmx_error_add(&info); 5539215976Sjmallett 5540215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5541215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5542215976Sjmallett info.status_mask = 1ull<<8 /* q1_coff */; 5543215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5544215976Sjmallett info.enable_mask = 1ull<<8 /* q1_coff */; 5545215976Sjmallett info.flags = 0; 5546215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5547215976Sjmallett info.group_index = 0; 5548215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5549215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5550215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5551215976Sjmallett info.func = __cvmx_error_display; 5552215976Sjmallett info.user_info = (long) 5553215976Sjmallett "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n" 5554215976Sjmallett " the count available is greater than pointers\n" 5555215976Sjmallett " present in the FPA.\n"; 5556215976Sjmallett fail |= cvmx_error_add(&info); 5557215976Sjmallett 5558215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5559215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5560215976Sjmallett info.status_mask = 1ull<<9 /* q1_perr */; 5561215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5562215976Sjmallett info.enable_mask = 1ull<<9 /* q1_perr */; 5563215976Sjmallett info.flags = 0; 5564215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5565215976Sjmallett info.group_index = 0; 5566215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5567215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5568215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5569215976Sjmallett info.func = __cvmx_error_display; 5570215976Sjmallett info.user_info = (long) 5571215976Sjmallett "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n" 5572215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 5573215976Sjmallett fail |= cvmx_error_add(&info); 5574215976Sjmallett 5575215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5576215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5577215976Sjmallett info.status_mask = 1ull<<10 /* q2_und */; 5578215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5579215976Sjmallett info.enable_mask = 1ull<<10 /* q2_und */; 5580215976Sjmallett info.flags = 0; 5581215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5582215976Sjmallett info.group_index = 0; 5583215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5584215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5585215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5586215976Sjmallett info.func = __cvmx_error_display; 5587215976Sjmallett info.user_info = (long) 5588215976Sjmallett "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n" 5589215976Sjmallett " negative.\n"; 5590215976Sjmallett fail |= cvmx_error_add(&info); 5591215976Sjmallett 5592215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5593215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5594215976Sjmallett info.status_mask = 1ull<<11 /* q2_coff */; 5595215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5596215976Sjmallett info.enable_mask = 1ull<<11 /* q2_coff */; 5597215976Sjmallett info.flags = 0; 5598215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5599215976Sjmallett info.group_index = 0; 5600215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5601215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5602215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5603215976Sjmallett info.func = __cvmx_error_display; 5604215976Sjmallett info.user_info = (long) 5605215976Sjmallett "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n" 5606215976Sjmallett " the count available is greater than than pointers\n" 5607215976Sjmallett " present in the FPA.\n"; 5608215976Sjmallett fail |= cvmx_error_add(&info); 5609215976Sjmallett 5610215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5611215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5612215976Sjmallett info.status_mask = 1ull<<12 /* q2_perr */; 5613215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5614215976Sjmallett info.enable_mask = 1ull<<12 /* q2_perr */; 5615215976Sjmallett info.flags = 0; 5616215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5617215976Sjmallett info.group_index = 0; 5618215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5619215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5620215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5621215976Sjmallett info.func = __cvmx_error_display; 5622215976Sjmallett info.user_info = (long) 5623215976Sjmallett "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n" 5624215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 5625215976Sjmallett fail |= cvmx_error_add(&info); 5626215976Sjmallett 5627215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5628215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5629215976Sjmallett info.status_mask = 1ull<<13 /* q3_und */; 5630215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5631215976Sjmallett info.enable_mask = 1ull<<13 /* q3_und */; 5632215976Sjmallett info.flags = 0; 5633215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5634215976Sjmallett info.group_index = 0; 5635215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5636215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5637215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5638215976Sjmallett info.func = __cvmx_error_display; 5639215976Sjmallett info.user_info = (long) 5640215976Sjmallett "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n" 5641215976Sjmallett " negative.\n"; 5642215976Sjmallett fail |= cvmx_error_add(&info); 5643215976Sjmallett 5644215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5645215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5646215976Sjmallett info.status_mask = 1ull<<14 /* q3_coff */; 5647215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5648215976Sjmallett info.enable_mask = 1ull<<14 /* q3_coff */; 5649215976Sjmallett info.flags = 0; 5650215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5651215976Sjmallett info.group_index = 0; 5652215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5653215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5654215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5655215976Sjmallett info.func = __cvmx_error_display; 5656215976Sjmallett info.user_info = (long) 5657215976Sjmallett "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n" 5658215976Sjmallett " the count available is greater than than pointers\n" 5659215976Sjmallett " present in the FPA.\n"; 5660215976Sjmallett fail |= cvmx_error_add(&info); 5661215976Sjmallett 5662215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5663215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5664215976Sjmallett info.status_mask = 1ull<<15 /* q3_perr */; 5665215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5666215976Sjmallett info.enable_mask = 1ull<<15 /* q3_perr */; 5667215976Sjmallett info.flags = 0; 5668215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5669215976Sjmallett info.group_index = 0; 5670215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5671215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5672215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5673215976Sjmallett info.func = __cvmx_error_display; 5674215976Sjmallett info.user_info = (long) 5675215976Sjmallett "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n" 5676215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 5677215976Sjmallett fail |= cvmx_error_add(&info); 5678215976Sjmallett 5679215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5680215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5681215976Sjmallett info.status_mask = 1ull<<16 /* q4_und */; 5682215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5683215976Sjmallett info.enable_mask = 1ull<<16 /* q4_und */; 5684215976Sjmallett info.flags = 0; 5685215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5686215976Sjmallett info.group_index = 0; 5687215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5688215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5689215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5690215976Sjmallett info.func = __cvmx_error_display; 5691215976Sjmallett info.user_info = (long) 5692215976Sjmallett "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n" 5693215976Sjmallett " negative.\n"; 5694215976Sjmallett fail |= cvmx_error_add(&info); 5695215976Sjmallett 5696215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5697215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5698215976Sjmallett info.status_mask = 1ull<<17 /* q4_coff */; 5699215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5700215976Sjmallett info.enable_mask = 1ull<<17 /* q4_coff */; 5701215976Sjmallett info.flags = 0; 5702215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5703215976Sjmallett info.group_index = 0; 5704215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5705215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5706215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5707215976Sjmallett info.func = __cvmx_error_display; 5708215976Sjmallett info.user_info = (long) 5709215976Sjmallett "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n" 5710215976Sjmallett " the count available is greater than than pointers\n" 5711215976Sjmallett " present in the FPA.\n"; 5712215976Sjmallett fail |= cvmx_error_add(&info); 5713215976Sjmallett 5714215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5715215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5716215976Sjmallett info.status_mask = 1ull<<18 /* q4_perr */; 5717215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5718215976Sjmallett info.enable_mask = 1ull<<18 /* q4_perr */; 5719215976Sjmallett info.flags = 0; 5720215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5721215976Sjmallett info.group_index = 0; 5722215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5723215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5724215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5725215976Sjmallett info.func = __cvmx_error_display; 5726215976Sjmallett info.user_info = (long) 5727215976Sjmallett "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n" 5728215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 5729215976Sjmallett fail |= cvmx_error_add(&info); 5730215976Sjmallett 5731215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5732215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5733215976Sjmallett info.status_mask = 1ull<<19 /* q5_und */; 5734215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5735215976Sjmallett info.enable_mask = 1ull<<19 /* q5_und */; 5736215976Sjmallett info.flags = 0; 5737215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5738215976Sjmallett info.group_index = 0; 5739215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5740215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5741215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5742215976Sjmallett info.func = __cvmx_error_display; 5743215976Sjmallett info.user_info = (long) 5744215976Sjmallett "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n" 5745215976Sjmallett " negative.\n"; 5746215976Sjmallett fail |= cvmx_error_add(&info); 5747215976Sjmallett 5748215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5749215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5750215976Sjmallett info.status_mask = 1ull<<20 /* q5_coff */; 5751215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5752215976Sjmallett info.enable_mask = 1ull<<20 /* q5_coff */; 5753215976Sjmallett info.flags = 0; 5754215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5755215976Sjmallett info.group_index = 0; 5756215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5757215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5758215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5759215976Sjmallett info.func = __cvmx_error_display; 5760215976Sjmallett info.user_info = (long) 5761215976Sjmallett "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n" 5762215976Sjmallett " the count available is greater than than pointers\n" 5763215976Sjmallett " present in the FPA.\n"; 5764215976Sjmallett fail |= cvmx_error_add(&info); 5765215976Sjmallett 5766215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5767215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5768215976Sjmallett info.status_mask = 1ull<<21 /* q5_perr */; 5769215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5770215976Sjmallett info.enable_mask = 1ull<<21 /* q5_perr */; 5771215976Sjmallett info.flags = 0; 5772215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5773215976Sjmallett info.group_index = 0; 5774215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5775215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5776215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5777215976Sjmallett info.func = __cvmx_error_display; 5778215976Sjmallett info.user_info = (long) 5779215976Sjmallett "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n" 5780215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 5781215976Sjmallett fail |= cvmx_error_add(&info); 5782215976Sjmallett 5783215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5784215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5785215976Sjmallett info.status_mask = 1ull<<22 /* q6_und */; 5786215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5787215976Sjmallett info.enable_mask = 1ull<<22 /* q6_und */; 5788215976Sjmallett info.flags = 0; 5789215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5790215976Sjmallett info.group_index = 0; 5791215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5792215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5793215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5794215976Sjmallett info.func = __cvmx_error_display; 5795215976Sjmallett info.user_info = (long) 5796215976Sjmallett "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n" 5797215976Sjmallett " negative.\n"; 5798215976Sjmallett fail |= cvmx_error_add(&info); 5799215976Sjmallett 5800215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5801215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5802215976Sjmallett info.status_mask = 1ull<<23 /* q6_coff */; 5803215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5804215976Sjmallett info.enable_mask = 1ull<<23 /* q6_coff */; 5805215976Sjmallett info.flags = 0; 5806215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5807215976Sjmallett info.group_index = 0; 5808215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5809215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5810215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5811215976Sjmallett info.func = __cvmx_error_display; 5812215976Sjmallett info.user_info = (long) 5813215976Sjmallett "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n" 5814215976Sjmallett " the count available is greater than than pointers\n" 5815215976Sjmallett " present in the FPA.\n"; 5816215976Sjmallett fail |= cvmx_error_add(&info); 5817215976Sjmallett 5818215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5819215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5820215976Sjmallett info.status_mask = 1ull<<24 /* q6_perr */; 5821215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5822215976Sjmallett info.enable_mask = 1ull<<24 /* q6_perr */; 5823215976Sjmallett info.flags = 0; 5824215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5825215976Sjmallett info.group_index = 0; 5826215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5827215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5828215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5829215976Sjmallett info.func = __cvmx_error_display; 5830215976Sjmallett info.user_info = (long) 5831215976Sjmallett "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n" 5832215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 5833215976Sjmallett fail |= cvmx_error_add(&info); 5834215976Sjmallett 5835215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5836215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5837215976Sjmallett info.status_mask = 1ull<<25 /* q7_und */; 5838215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5839215976Sjmallett info.enable_mask = 1ull<<25 /* q7_und */; 5840215976Sjmallett info.flags = 0; 5841215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5842215976Sjmallett info.group_index = 0; 5843215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5844215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5845215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5846215976Sjmallett info.func = __cvmx_error_display; 5847215976Sjmallett info.user_info = (long) 5848215976Sjmallett "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n" 5849215976Sjmallett " negative.\n"; 5850215976Sjmallett fail |= cvmx_error_add(&info); 5851215976Sjmallett 5852215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5853215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5854215976Sjmallett info.status_mask = 1ull<<26 /* q7_coff */; 5855215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5856215976Sjmallett info.enable_mask = 1ull<<26 /* q7_coff */; 5857215976Sjmallett info.flags = 0; 5858215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5859215976Sjmallett info.group_index = 0; 5860215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5861215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5862215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5863215976Sjmallett info.func = __cvmx_error_display; 5864215976Sjmallett info.user_info = (long) 5865215976Sjmallett "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n" 5866215976Sjmallett " the count available is greater than than pointers\n" 5867215976Sjmallett " present in the FPA.\n"; 5868215976Sjmallett fail |= cvmx_error_add(&info); 5869215976Sjmallett 5870215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5871215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 5872215976Sjmallett info.status_mask = 1ull<<27 /* q7_perr */; 5873215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 5874215976Sjmallett info.enable_mask = 1ull<<27 /* q7_perr */; 5875215976Sjmallett info.flags = 0; 5876215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5877215976Sjmallett info.group_index = 0; 5878215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5879215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5880215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 5881215976Sjmallett info.func = __cvmx_error_display; 5882215976Sjmallett info.user_info = (long) 5883215976Sjmallett "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n" 5884215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 5885215976Sjmallett fail |= cvmx_error_add(&info); 5886215976Sjmallett 5887215976Sjmallett /* CVMX_LMCX_MEM_CFG0(0) */ 5888215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5889215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 5890215976Sjmallett info.status_mask = 0xfull<<21 /* sec_err */; 5891215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 5892215976Sjmallett info.enable_mask = 1ull<<19 /* intr_sec_ena */; 5893215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 5894215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 5895215976Sjmallett info.group_index = 0; 5896215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5897215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5898215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc0 */; 5899215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err; 5900215976Sjmallett info.user_info = (long) 5901215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n" 5902215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 5903215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 5904215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 5905215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 5906215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 5907215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 5908215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 5909215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 5910215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 5911215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 5912215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 5913215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 5914215976Sjmallett fail |= cvmx_error_add(&info); 5915215976Sjmallett 5916215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5917215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 5918215976Sjmallett info.status_mask = 0xfull<<25 /* ded_err */; 5919215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 5920215976Sjmallett info.enable_mask = 1ull<<20 /* intr_ded_ena */; 5921215976Sjmallett info.flags = 0; 5922215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 5923215976Sjmallett info.group_index = 0; 5924215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5925215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5926215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc0 */; 5927215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err; 5928215976Sjmallett info.user_info = (long) 5929215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n" 5930215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 5931215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 5932215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 5933215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 5934215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 5935215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 5936215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 5937215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 5938215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 5939215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 5940215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 5941215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 5942215976Sjmallett fail |= cvmx_error_add(&info); 5943215976Sjmallett 5944215976Sjmallett /* CVMX_IOB_INT_SUM */ 5945215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5946215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 5947215976Sjmallett info.status_mask = 1ull<<0 /* np_sop */; 5948215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 5949215976Sjmallett info.enable_mask = 1ull<<0 /* np_sop */; 5950215976Sjmallett info.flags = 0; 5951215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5952215976Sjmallett info.group_index = 0; 5953215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5954215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5955215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 5956215976Sjmallett info.func = __cvmx_error_display; 5957215976Sjmallett info.user_info = (long) 5958215976Sjmallett "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n" 5959215976Sjmallett " port for a non-passthrough packet.\n" 5960215976Sjmallett " The first detected error associated with bits [5:0]\n" 5961215976Sjmallett " of this register will only be set here. A new bit\n" 5962215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 5963215976Sjmallett fail |= cvmx_error_add(&info); 5964215976Sjmallett 5965215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5966215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 5967215976Sjmallett info.status_mask = 1ull<<1 /* np_eop */; 5968215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 5969215976Sjmallett info.enable_mask = 1ull<<1 /* np_eop */; 5970215976Sjmallett info.flags = 0; 5971215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5972215976Sjmallett info.group_index = 0; 5973215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5974215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5975215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 5976215976Sjmallett info.func = __cvmx_error_display; 5977215976Sjmallett info.user_info = (long) 5978215976Sjmallett "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n" 5979215976Sjmallett " port for a non-passthrough packet.\n" 5980215976Sjmallett " The first detected error associated with bits [5:0]\n" 5981215976Sjmallett " of this register will only be set here. A new bit\n" 5982215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 5983215976Sjmallett fail |= cvmx_error_add(&info); 5984215976Sjmallett 5985215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5986215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 5987215976Sjmallett info.status_mask = 1ull<<2 /* p_sop */; 5988215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 5989215976Sjmallett info.enable_mask = 1ull<<2 /* p_sop */; 5990215976Sjmallett info.flags = 0; 5991215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5992215976Sjmallett info.group_index = 0; 5993215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5994215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 5995215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 5996215976Sjmallett info.func = __cvmx_error_display; 5997215976Sjmallett info.user_info = (long) 5998215976Sjmallett "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n" 5999215976Sjmallett " port for a passthrough packet.\n" 6000215976Sjmallett " The first detected error associated with bits [5:0]\n" 6001215976Sjmallett " of this register will only be set here. A new bit\n" 6002215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6003215976Sjmallett fail |= cvmx_error_add(&info); 6004215976Sjmallett 6005215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6006215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6007215976Sjmallett info.status_mask = 1ull<<3 /* p_eop */; 6008215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6009215976Sjmallett info.enable_mask = 1ull<<3 /* p_eop */; 6010215976Sjmallett info.flags = 0; 6011215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6012215976Sjmallett info.group_index = 0; 6013215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6014215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6015215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6016215976Sjmallett info.func = __cvmx_error_display; 6017215976Sjmallett info.user_info = (long) 6018215976Sjmallett "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n" 6019215976Sjmallett " port for a passthrough packet.\n" 6020215976Sjmallett " The first detected error associated with bits [5:0]\n" 6021215976Sjmallett " of this register will only be set here. A new bit\n" 6022215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6023215976Sjmallett fail |= cvmx_error_add(&info); 6024215976Sjmallett 6025215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6026215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6027215976Sjmallett info.status_mask = 1ull<<4 /* np_dat */; 6028215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6029215976Sjmallett info.enable_mask = 1ull<<4 /* np_dat */; 6030215976Sjmallett info.flags = 0; 6031215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6032215976Sjmallett info.group_index = 0; 6033215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6034215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6035215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6036215976Sjmallett info.func = __cvmx_error_display; 6037215976Sjmallett info.user_info = (long) 6038215976Sjmallett "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n" 6039215976Sjmallett " port for a non-passthrough packet.\n" 6040215976Sjmallett " The first detected error associated with bits [5:0]\n" 6041215976Sjmallett " of this register will only be set here. A new bit\n" 6042215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6043215976Sjmallett fail |= cvmx_error_add(&info); 6044215976Sjmallett 6045215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6046215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 6047215976Sjmallett info.status_mask = 1ull<<5 /* p_dat */; 6048215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 6049215976Sjmallett info.enable_mask = 1ull<<5 /* p_dat */; 6050215976Sjmallett info.flags = 0; 6051215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6052215976Sjmallett info.group_index = 0; 6053215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6054215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6055215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 6056215976Sjmallett info.func = __cvmx_error_display; 6057215976Sjmallett info.user_info = (long) 6058215976Sjmallett "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n" 6059215976Sjmallett " port for a passthrough packet.\n" 6060215976Sjmallett " The first detected error associated with bits [5:0]\n" 6061215976Sjmallett " of this register will only be set here. A new bit\n" 6062215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 6063215976Sjmallett fail |= cvmx_error_add(&info); 6064215976Sjmallett 6065215976Sjmallett /* CVMX_USBNX_INT_SUM(0) */ 6066215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6067215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6068215976Sjmallett info.status_mask = 1ull<<0 /* pr_po_e */; 6069215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6070215976Sjmallett info.enable_mask = 1ull<<0 /* pr_po_e */; 6071215976Sjmallett info.flags = 0; 6072215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6073215976Sjmallett info.group_index = 0; 6074215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6075215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6076215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6077215976Sjmallett info.func = __cvmx_error_display; 6078215976Sjmallett info.user_info = (long) 6079215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n"; 6080215976Sjmallett fail |= cvmx_error_add(&info); 6081215976Sjmallett 6082215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6083215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6084215976Sjmallett info.status_mask = 1ull<<1 /* pr_pu_f */; 6085215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6086215976Sjmallett info.enable_mask = 1ull<<1 /* pr_pu_f */; 6087215976Sjmallett info.flags = 0; 6088215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6089215976Sjmallett info.group_index = 0; 6090215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6091215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6092215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6093215976Sjmallett info.func = __cvmx_error_display; 6094215976Sjmallett info.user_info = (long) 6095215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n"; 6096215976Sjmallett fail |= cvmx_error_add(&info); 6097215976Sjmallett 6098215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6099215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6100215976Sjmallett info.status_mask = 1ull<<2 /* nr_po_e */; 6101215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6102215976Sjmallett info.enable_mask = 1ull<<2 /* nr_po_e */; 6103215976Sjmallett info.flags = 0; 6104215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6105215976Sjmallett info.group_index = 0; 6106215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6107215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6108215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6109215976Sjmallett info.func = __cvmx_error_display; 6110215976Sjmallett info.user_info = (long) 6111215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n"; 6112215976Sjmallett fail |= cvmx_error_add(&info); 6113215976Sjmallett 6114215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6115215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6116215976Sjmallett info.status_mask = 1ull<<3 /* nr_pu_f */; 6117215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6118215976Sjmallett info.enable_mask = 1ull<<3 /* nr_pu_f */; 6119215976Sjmallett info.flags = 0; 6120215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6121215976Sjmallett info.group_index = 0; 6122215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6123215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6124215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6125215976Sjmallett info.func = __cvmx_error_display; 6126215976Sjmallett info.user_info = (long) 6127215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n"; 6128215976Sjmallett fail |= cvmx_error_add(&info); 6129215976Sjmallett 6130215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6131215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6132215976Sjmallett info.status_mask = 1ull<<4 /* lr_po_e */; 6133215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6134215976Sjmallett info.enable_mask = 1ull<<4 /* lr_po_e */; 6135215976Sjmallett info.flags = 0; 6136215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6137215976Sjmallett info.group_index = 0; 6138215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6139215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6140215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6141215976Sjmallett info.func = __cvmx_error_display; 6142215976Sjmallett info.user_info = (long) 6143215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n"; 6144215976Sjmallett fail |= cvmx_error_add(&info); 6145215976Sjmallett 6146215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6147215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6148215976Sjmallett info.status_mask = 1ull<<5 /* lr_pu_f */; 6149215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6150215976Sjmallett info.enable_mask = 1ull<<5 /* lr_pu_f */; 6151215976Sjmallett info.flags = 0; 6152215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6153215976Sjmallett info.group_index = 0; 6154215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6155215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6156215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6157215976Sjmallett info.func = __cvmx_error_display; 6158215976Sjmallett info.user_info = (long) 6159215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n"; 6160215976Sjmallett fail |= cvmx_error_add(&info); 6161215976Sjmallett 6162215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6163215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6164215976Sjmallett info.status_mask = 1ull<<6 /* pt_po_e */; 6165215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6166215976Sjmallett info.enable_mask = 1ull<<6 /* pt_po_e */; 6167215976Sjmallett info.flags = 0; 6168215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6169215976Sjmallett info.group_index = 0; 6170215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6171215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6172215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6173215976Sjmallett info.func = __cvmx_error_display; 6174215976Sjmallett info.user_info = (long) 6175215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n"; 6176215976Sjmallett fail |= cvmx_error_add(&info); 6177215976Sjmallett 6178215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6179215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6180215976Sjmallett info.status_mask = 1ull<<7 /* pt_pu_f */; 6181215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6182215976Sjmallett info.enable_mask = 1ull<<7 /* pt_pu_f */; 6183215976Sjmallett info.flags = 0; 6184215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6185215976Sjmallett info.group_index = 0; 6186215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6187215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6188215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6189215976Sjmallett info.func = __cvmx_error_display; 6190215976Sjmallett info.user_info = (long) 6191215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n"; 6192215976Sjmallett fail |= cvmx_error_add(&info); 6193215976Sjmallett 6194215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6195215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6196215976Sjmallett info.status_mask = 1ull<<8 /* nt_po_e */; 6197215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6198215976Sjmallett info.enable_mask = 1ull<<8 /* nt_po_e */; 6199215976Sjmallett info.flags = 0; 6200215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6201215976Sjmallett info.group_index = 0; 6202215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6203215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6204215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6205215976Sjmallett info.func = __cvmx_error_display; 6206215976Sjmallett info.user_info = (long) 6207215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n"; 6208215976Sjmallett fail |= cvmx_error_add(&info); 6209215976Sjmallett 6210215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6211215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6212215976Sjmallett info.status_mask = 1ull<<9 /* nt_pu_f */; 6213215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6214215976Sjmallett info.enable_mask = 1ull<<9 /* nt_pu_f */; 6215215976Sjmallett info.flags = 0; 6216215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6217215976Sjmallett info.group_index = 0; 6218215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6219215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6220215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6221215976Sjmallett info.func = __cvmx_error_display; 6222215976Sjmallett info.user_info = (long) 6223215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n"; 6224215976Sjmallett fail |= cvmx_error_add(&info); 6225215976Sjmallett 6226215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6227215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6228215976Sjmallett info.status_mask = 1ull<<10 /* lt_po_e */; 6229215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6230215976Sjmallett info.enable_mask = 1ull<<10 /* lt_po_e */; 6231215976Sjmallett info.flags = 0; 6232215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6233215976Sjmallett info.group_index = 0; 6234215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6235215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6236215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6237215976Sjmallett info.func = __cvmx_error_display; 6238215976Sjmallett info.user_info = (long) 6239215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n"; 6240215976Sjmallett fail |= cvmx_error_add(&info); 6241215976Sjmallett 6242215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6243215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6244215976Sjmallett info.status_mask = 1ull<<11 /* lt_pu_f */; 6245215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6246215976Sjmallett info.enable_mask = 1ull<<11 /* lt_pu_f */; 6247215976Sjmallett info.flags = 0; 6248215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6249215976Sjmallett info.group_index = 0; 6250215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6251215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6252215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6253215976Sjmallett info.func = __cvmx_error_display; 6254215976Sjmallett info.user_info = (long) 6255215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n"; 6256215976Sjmallett fail |= cvmx_error_add(&info); 6257215976Sjmallett 6258215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6259215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6260215976Sjmallett info.status_mask = 1ull<<12 /* dcred_e */; 6261215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6262215976Sjmallett info.enable_mask = 1ull<<12 /* dcred_e */; 6263215976Sjmallett info.flags = 0; 6264215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6265215976Sjmallett info.group_index = 0; 6266215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6267215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6268215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6269215976Sjmallett info.func = __cvmx_error_display; 6270215976Sjmallett info.user_info = (long) 6271215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n"; 6272215976Sjmallett fail |= cvmx_error_add(&info); 6273215976Sjmallett 6274215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6275215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6276215976Sjmallett info.status_mask = 1ull<<13 /* dcred_f */; 6277215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6278215976Sjmallett info.enable_mask = 1ull<<13 /* dcred_f */; 6279215976Sjmallett info.flags = 0; 6280215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6281215976Sjmallett info.group_index = 0; 6282215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6283215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6284215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6285215976Sjmallett info.func = __cvmx_error_display; 6286215976Sjmallett info.user_info = (long) 6287215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n"; 6288215976Sjmallett fail |= cvmx_error_add(&info); 6289215976Sjmallett 6290215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6291215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6292215976Sjmallett info.status_mask = 1ull<<14 /* l2c_s_e */; 6293215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6294215976Sjmallett info.enable_mask = 1ull<<14 /* l2c_s_e */; 6295215976Sjmallett info.flags = 0; 6296215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6297215976Sjmallett info.group_index = 0; 6298215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6299215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6300215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6301215976Sjmallett info.func = __cvmx_error_display; 6302215976Sjmallett info.user_info = (long) 6303215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n"; 6304215976Sjmallett fail |= cvmx_error_add(&info); 6305215976Sjmallett 6306215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6307215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6308215976Sjmallett info.status_mask = 1ull<<15 /* l2c_a_f */; 6309215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6310215976Sjmallett info.enable_mask = 1ull<<15 /* l2c_a_f */; 6311215976Sjmallett info.flags = 0; 6312215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6313215976Sjmallett info.group_index = 0; 6314215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6315215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6316215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6317215976Sjmallett info.func = __cvmx_error_display; 6318215976Sjmallett info.user_info = (long) 6319215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n"; 6320215976Sjmallett fail |= cvmx_error_add(&info); 6321215976Sjmallett 6322215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6323215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6324215976Sjmallett info.status_mask = 1ull<<16 /* lt_fi_e */; 6325215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6326215976Sjmallett info.enable_mask = 1ull<<16 /* l2_fi_e */; 6327215976Sjmallett info.flags = 0; 6328215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6329215976Sjmallett info.group_index = 0; 6330215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6331215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6332215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6333215976Sjmallett info.func = __cvmx_error_display; 6334215976Sjmallett info.user_info = (long) 6335215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n"; 6336215976Sjmallett fail |= cvmx_error_add(&info); 6337215976Sjmallett 6338215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6339215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6340215976Sjmallett info.status_mask = 1ull<<17 /* lt_fi_f */; 6341215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6342215976Sjmallett info.enable_mask = 1ull<<17 /* l2_fi_f */; 6343215976Sjmallett info.flags = 0; 6344215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6345215976Sjmallett info.group_index = 0; 6346215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6347215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6348215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6349215976Sjmallett info.func = __cvmx_error_display; 6350215976Sjmallett info.user_info = (long) 6351215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n"; 6352215976Sjmallett fail |= cvmx_error_add(&info); 6353215976Sjmallett 6354215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6355215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6356215976Sjmallett info.status_mask = 1ull<<18 /* rg_fi_e */; 6357215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6358215976Sjmallett info.enable_mask = 1ull<<18 /* rg_fi_e */; 6359215976Sjmallett info.flags = 0; 6360215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6361215976Sjmallett info.group_index = 0; 6362215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6363215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6364215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6365215976Sjmallett info.func = __cvmx_error_display; 6366215976Sjmallett info.user_info = (long) 6367215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n"; 6368215976Sjmallett fail |= cvmx_error_add(&info); 6369215976Sjmallett 6370215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6371215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6372215976Sjmallett info.status_mask = 1ull<<19 /* rg_fi_f */; 6373215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6374215976Sjmallett info.enable_mask = 1ull<<19 /* rg_fi_f */; 6375215976Sjmallett info.flags = 0; 6376215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6377215976Sjmallett info.group_index = 0; 6378215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6379215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6380215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6381215976Sjmallett info.func = __cvmx_error_display; 6382215976Sjmallett info.user_info = (long) 6383215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n"; 6384215976Sjmallett fail |= cvmx_error_add(&info); 6385215976Sjmallett 6386215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6387215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6388215976Sjmallett info.status_mask = 1ull<<20 /* rq_q2_f */; 6389215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6390215976Sjmallett info.enable_mask = 1ull<<20 /* rq_q2_f */; 6391215976Sjmallett info.flags = 0; 6392215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6393215976Sjmallett info.group_index = 0; 6394215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6395215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6396215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6397215976Sjmallett info.func = __cvmx_error_display; 6398215976Sjmallett info.user_info = (long) 6399215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n"; 6400215976Sjmallett fail |= cvmx_error_add(&info); 6401215976Sjmallett 6402215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6403215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6404215976Sjmallett info.status_mask = 1ull<<21 /* rq_q2_e */; 6405215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6406215976Sjmallett info.enable_mask = 1ull<<21 /* rq_q2_e */; 6407215976Sjmallett info.flags = 0; 6408215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6409215976Sjmallett info.group_index = 0; 6410215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6411215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6412215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6413215976Sjmallett info.func = __cvmx_error_display; 6414215976Sjmallett info.user_info = (long) 6415215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n"; 6416215976Sjmallett fail |= cvmx_error_add(&info); 6417215976Sjmallett 6418215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6419215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6420215976Sjmallett info.status_mask = 1ull<<22 /* rq_q3_f */; 6421215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6422215976Sjmallett info.enable_mask = 1ull<<22 /* rq_q3_f */; 6423215976Sjmallett info.flags = 0; 6424215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6425215976Sjmallett info.group_index = 0; 6426215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6427215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6428215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6429215976Sjmallett info.func = __cvmx_error_display; 6430215976Sjmallett info.user_info = (long) 6431215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n"; 6432215976Sjmallett fail |= cvmx_error_add(&info); 6433215976Sjmallett 6434215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6435215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6436215976Sjmallett info.status_mask = 1ull<<23 /* rq_q3_e */; 6437215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6438215976Sjmallett info.enable_mask = 1ull<<23 /* rq_q3_e */; 6439215976Sjmallett info.flags = 0; 6440215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6441215976Sjmallett info.group_index = 0; 6442215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6443215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6444215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6445215976Sjmallett info.func = __cvmx_error_display; 6446215976Sjmallett info.user_info = (long) 6447215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n"; 6448215976Sjmallett fail |= cvmx_error_add(&info); 6449215976Sjmallett 6450215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6451215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6452215976Sjmallett info.status_mask = 1ull<<24 /* uod_pe */; 6453215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6454215976Sjmallett info.enable_mask = 1ull<<24 /* uod_pe */; 6455215976Sjmallett info.flags = 0; 6456215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6457215976Sjmallett info.group_index = 0; 6458215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6459215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6460215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6461215976Sjmallett info.func = __cvmx_error_display; 6462215976Sjmallett info.user_info = (long) 6463215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n"; 6464215976Sjmallett fail |= cvmx_error_add(&info); 6465215976Sjmallett 6466215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6467215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6468215976Sjmallett info.status_mask = 1ull<<25 /* uod_pf */; 6469215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6470215976Sjmallett info.enable_mask = 1ull<<25 /* uod_pf */; 6471215976Sjmallett info.flags = 0; 6472215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6473215976Sjmallett info.group_index = 0; 6474215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6475215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6476215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6477215976Sjmallett info.func = __cvmx_error_display; 6478215976Sjmallett info.user_info = (long) 6479215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n"; 6480215976Sjmallett fail |= cvmx_error_add(&info); 6481215976Sjmallett 6482215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6483215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6484215976Sjmallett info.status_mask = 1ull<<32 /* ltl_f_pe */; 6485215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6486215976Sjmallett info.enable_mask = 1ull<<32 /* ltl_f_pe */; 6487215976Sjmallett info.flags = 0; 6488215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6489215976Sjmallett info.group_index = 0; 6490215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6491215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6492215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6493215976Sjmallett info.func = __cvmx_error_display; 6494215976Sjmallett info.user_info = (long) 6495215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n"; 6496215976Sjmallett fail |= cvmx_error_add(&info); 6497215976Sjmallett 6498215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6499215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6500215976Sjmallett info.status_mask = 1ull<<33 /* ltl_f_pf */; 6501215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6502215976Sjmallett info.enable_mask = 1ull<<33 /* ltl_f_pf */; 6503215976Sjmallett info.flags = 0; 6504215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6505215976Sjmallett info.group_index = 0; 6506215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6507215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6508215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6509215976Sjmallett info.func = __cvmx_error_display; 6510215976Sjmallett info.user_info = (long) 6511215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n"; 6512215976Sjmallett fail |= cvmx_error_add(&info); 6513215976Sjmallett 6514215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6515215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6516215976Sjmallett info.status_mask = 1ull<<34 /* nd4o_rpe */; 6517215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6518215976Sjmallett info.enable_mask = 1ull<<34 /* nd4o_rpe */; 6519215976Sjmallett info.flags = 0; 6520215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6521215976Sjmallett info.group_index = 0; 6522215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6523215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6524215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6525215976Sjmallett info.func = __cvmx_error_display; 6526215976Sjmallett info.user_info = (long) 6527215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n"; 6528215976Sjmallett fail |= cvmx_error_add(&info); 6529215976Sjmallett 6530215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6531215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6532215976Sjmallett info.status_mask = 1ull<<35 /* nd4o_rpf */; 6533215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6534215976Sjmallett info.enable_mask = 1ull<<35 /* nd4o_rpf */; 6535215976Sjmallett info.flags = 0; 6536215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6537215976Sjmallett info.group_index = 0; 6538215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6539215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6540215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6541215976Sjmallett info.func = __cvmx_error_display; 6542215976Sjmallett info.user_info = (long) 6543215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n"; 6544215976Sjmallett fail |= cvmx_error_add(&info); 6545215976Sjmallett 6546215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6547215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6548215976Sjmallett info.status_mask = 1ull<<36 /* nd4o_dpe */; 6549215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6550215976Sjmallett info.enable_mask = 1ull<<36 /* nd4o_dpe */; 6551215976Sjmallett info.flags = 0; 6552215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6553215976Sjmallett info.group_index = 0; 6554215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6555215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6556215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6557215976Sjmallett info.func = __cvmx_error_display; 6558215976Sjmallett info.user_info = (long) 6559215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n"; 6560215976Sjmallett fail |= cvmx_error_add(&info); 6561215976Sjmallett 6562215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6563215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 6564215976Sjmallett info.status_mask = 1ull<<37 /* nd4o_dpf */; 6565215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 6566215976Sjmallett info.enable_mask = 1ull<<37 /* nd4o_dpf */; 6567215976Sjmallett info.flags = 0; 6568215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 6569215976Sjmallett info.group_index = 0; 6570215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6571215976Sjmallett info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS; 6572215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 6573215976Sjmallett info.func = __cvmx_error_display; 6574215976Sjmallett info.user_info = (long) 6575215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n"; 6576215976Sjmallett fail |= cvmx_error_add(&info); 6577215976Sjmallett 6578215976Sjmallett return fail; 6579215976Sjmallett} 6580215976Sjmallett 6581