1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * @file 43215976Sjmallett * 44215976Sjmallett * Automatically generated error messages for cn50xx. 45215976Sjmallett * 46215976Sjmallett * This file is auto generated. Do not edit. 47215976Sjmallett * 48215976Sjmallett * <hr>$Revision$<hr> 49215976Sjmallett * 50215976Sjmallett * <hr><h2>Error tree for CN50XX</h2> 51215976Sjmallett * @dot 52215976Sjmallett * digraph cn50xx 53215976Sjmallett * { 54215976Sjmallett * rankdir=LR; 55215976Sjmallett * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica]; 56215976Sjmallett * edge [fontsize=7, font=helvitica]; 57215976Sjmallett * cvmx_root [label="ROOT|<root>root"]; 58215976Sjmallett * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"]; 59215976Sjmallett * cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"]; 60215976Sjmallett * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"]; 61215976Sjmallett * cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"]; 62215976Sjmallett * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"]; 63215976Sjmallett * cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"]; 64215976Sjmallett * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"]; 65215976Sjmallett * cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"]; 66215976Sjmallett * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"]; 67215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"]; 68215976Sjmallett * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"]; 69215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"]; 70215976Sjmallett * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<fpa>fpa|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<pip>pip|<gmx0>gmx0|<lmc>lmc|<iob>iob|<usb>usb"]; 71215976Sjmallett * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"]; 72215976Sjmallett * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"]; 73215976Sjmallett * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"]; 74215976Sjmallett * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"]; 75215976Sjmallett * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"]; 76215976Sjmallett * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"]; 77215976Sjmallett * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"]; 78215976Sjmallett * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"]; 79215976Sjmallett * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"]; 80215976Sjmallett * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"]; 81215976Sjmallett * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"]; 82215976Sjmallett * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"]; 83215976Sjmallett * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"]; 84215976Sjmallett * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"]; 85215976Sjmallett * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"]; 86215976Sjmallett * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"]; 87215976Sjmallett * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"]; 88215976Sjmallett * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"]; 89215976Sjmallett * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"]; 90215976Sjmallett * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"]; 91215976Sjmallett * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"]; 92215976Sjmallett * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"]; 93215976Sjmallett * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"]; 94215976Sjmallett * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"]; 95215976Sjmallett * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 96215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"]; 97215976Sjmallett * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 98215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"]; 99215976Sjmallett * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 100215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"]; 101215976Sjmallett * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 102215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"]; 103215976Sjmallett * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"]; 104215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"]; 105215976Sjmallett * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"]; 106215976Sjmallett * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"]; 107215976Sjmallett * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"]; 108215976Sjmallett * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"]; 109215976Sjmallett * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"]; 110215976Sjmallett * cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"]; 111215976Sjmallett * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis]; 112215976Sjmallett * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis]; 113215976Sjmallett * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis]; 114215976Sjmallett * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis]; 115215976Sjmallett * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"]; 116215976Sjmallett * } 117215976Sjmallett * @enddot 118215976Sjmallett */ 119215976Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 120215976Sjmallett#include <asm/octeon/cvmx.h> 121215976Sjmallett#include <asm/octeon/cvmx-error.h> 122215976Sjmallett#include <asm/octeon/cvmx-error-custom.h> 123215976Sjmallett#include <asm/octeon/cvmx-csr-typedefs.h> 124215976Sjmallett#else 125215976Sjmallett#include "cvmx.h" 126215976Sjmallett#include "cvmx-error.h" 127215976Sjmallett#include "cvmx-error-custom.h" 128215976Sjmallett#endif 129215976Sjmallett 130215990Sjmallettint cvmx_error_initialize_cn50xx(void); 131215990Sjmallett 132215976Sjmallettint cvmx_error_initialize_cn50xx(void) 133215976Sjmallett{ 134215976Sjmallett cvmx_error_info_t info; 135215976Sjmallett int fail = 0; 136215976Sjmallett 137215976Sjmallett /* CVMX_CIU_INTX_SUM0(0) */ 138215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 139215976Sjmallett info.status_addr = CVMX_CIU_INTX_SUM0(0); 140215976Sjmallett info.status_mask = 0; 141215976Sjmallett info.enable_addr = 0; 142215976Sjmallett info.enable_mask = 0; 143215976Sjmallett info.flags = 0; 144215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 145215976Sjmallett info.group_index = 0; 146215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 147215976Sjmallett info.parent.status_addr = 0; 148215976Sjmallett info.parent.status_mask = 0; 149215976Sjmallett info.func = __cvmx_error_decode; 150215976Sjmallett info.user_info = 0; 151215976Sjmallett fail |= cvmx_error_add(&info); 152215976Sjmallett 153215976Sjmallett /* CVMX_PCMX_INT_SUM(0) */ 154215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 155215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(0); 156215976Sjmallett info.status_mask = 1ull<<0 /* fsyncmissed */; 157215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(0); 158215976Sjmallett info.enable_mask = 1ull<<0 /* fsyncmissed */; 159215976Sjmallett info.flags = 0; 160215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 161215976Sjmallett info.group_index = 0; 162215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 163215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 164215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 165215976Sjmallett info.func = __cvmx_error_display; 166215976Sjmallett info.user_info = (long) 167215976Sjmallett "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n"; 168215976Sjmallett fail |= cvmx_error_add(&info); 169215976Sjmallett 170215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 171215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(0); 172215976Sjmallett info.status_mask = 1ull<<1 /* fsyncextra */; 173215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(0); 174215976Sjmallett info.enable_mask = 1ull<<1 /* fsyncextra */; 175215976Sjmallett info.flags = 0; 176215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 177215976Sjmallett info.group_index = 0; 178215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 179215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 180215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 181215976Sjmallett info.func = __cvmx_error_display; 182215976Sjmallett info.user_info = (long) 183215976Sjmallett "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n"; 184215976Sjmallett fail |= cvmx_error_add(&info); 185215976Sjmallett 186215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 187215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(0); 188215976Sjmallett info.status_mask = 1ull<<6 /* txempty */; 189215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(0); 190215976Sjmallett info.enable_mask = 1ull<<6 /* txempty */; 191215976Sjmallett info.flags = 0; 192215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 193215976Sjmallett info.group_index = 0; 194215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 195215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 196215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 197215976Sjmallett info.func = __cvmx_error_display; 198215976Sjmallett info.user_info = (long) 199215976Sjmallett "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n"; 200215976Sjmallett fail |= cvmx_error_add(&info); 201215976Sjmallett 202215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 203215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(0); 204215976Sjmallett info.status_mask = 1ull<<7 /* rxovf */; 205215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(0); 206215976Sjmallett info.enable_mask = 1ull<<7 /* rxovf */; 207215976Sjmallett info.flags = 0; 208215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 209215976Sjmallett info.group_index = 0; 210215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 211215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 212215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 213215976Sjmallett info.func = __cvmx_error_display; 214215976Sjmallett info.user_info = (long) 215215976Sjmallett "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n"; 216215976Sjmallett fail |= cvmx_error_add(&info); 217215976Sjmallett 218215976Sjmallett /* CVMX_PCMX_INT_SUM(1) */ 219215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 220215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(1); 221215976Sjmallett info.status_mask = 1ull<<0 /* fsyncmissed */; 222215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(1); 223215976Sjmallett info.enable_mask = 1ull<<0 /* fsyncmissed */; 224215976Sjmallett info.flags = 0; 225215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 226215976Sjmallett info.group_index = 0; 227215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 228215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 229215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 230215976Sjmallett info.func = __cvmx_error_display; 231215976Sjmallett info.user_info = (long) 232215976Sjmallett "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n"; 233215976Sjmallett fail |= cvmx_error_add(&info); 234215976Sjmallett 235215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 236215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(1); 237215976Sjmallett info.status_mask = 1ull<<1 /* fsyncextra */; 238215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(1); 239215976Sjmallett info.enable_mask = 1ull<<1 /* fsyncextra */; 240215976Sjmallett info.flags = 0; 241215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 242215976Sjmallett info.group_index = 0; 243215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 244215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 245215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 246215976Sjmallett info.func = __cvmx_error_display; 247215976Sjmallett info.user_info = (long) 248215976Sjmallett "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n"; 249215976Sjmallett fail |= cvmx_error_add(&info); 250215976Sjmallett 251215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 252215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(1); 253215976Sjmallett info.status_mask = 1ull<<6 /* txempty */; 254215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(1); 255215976Sjmallett info.enable_mask = 1ull<<6 /* txempty */; 256215976Sjmallett info.flags = 0; 257215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 258215976Sjmallett info.group_index = 0; 259215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 260215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 261215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 262215976Sjmallett info.func = __cvmx_error_display; 263215976Sjmallett info.user_info = (long) 264215976Sjmallett "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n"; 265215976Sjmallett fail |= cvmx_error_add(&info); 266215976Sjmallett 267215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 268215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(1); 269215976Sjmallett info.status_mask = 1ull<<7 /* rxovf */; 270215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(1); 271215976Sjmallett info.enable_mask = 1ull<<7 /* rxovf */; 272215976Sjmallett info.flags = 0; 273215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 274215976Sjmallett info.group_index = 0; 275215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 276215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 277215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 278215976Sjmallett info.func = __cvmx_error_display; 279215976Sjmallett info.user_info = (long) 280215976Sjmallett "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n"; 281215976Sjmallett fail |= cvmx_error_add(&info); 282215976Sjmallett 283215976Sjmallett /* CVMX_PCMX_INT_SUM(2) */ 284215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 285215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(2); 286215976Sjmallett info.status_mask = 1ull<<0 /* fsyncmissed */; 287215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(2); 288215976Sjmallett info.enable_mask = 1ull<<0 /* fsyncmissed */; 289215976Sjmallett info.flags = 0; 290215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 291215976Sjmallett info.group_index = 0; 292215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 293215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 294215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 295215976Sjmallett info.func = __cvmx_error_display; 296215976Sjmallett info.user_info = (long) 297215976Sjmallett "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n"; 298215976Sjmallett fail |= cvmx_error_add(&info); 299215976Sjmallett 300215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 301215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(2); 302215976Sjmallett info.status_mask = 1ull<<1 /* fsyncextra */; 303215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(2); 304215976Sjmallett info.enable_mask = 1ull<<1 /* fsyncextra */; 305215976Sjmallett info.flags = 0; 306215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 307215976Sjmallett info.group_index = 0; 308215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 309215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 310215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 311215976Sjmallett info.func = __cvmx_error_display; 312215976Sjmallett info.user_info = (long) 313215976Sjmallett "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n"; 314215976Sjmallett fail |= cvmx_error_add(&info); 315215976Sjmallett 316215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 317215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(2); 318215976Sjmallett info.status_mask = 1ull<<6 /* txempty */; 319215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(2); 320215976Sjmallett info.enable_mask = 1ull<<6 /* txempty */; 321215976Sjmallett info.flags = 0; 322215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 323215976Sjmallett info.group_index = 0; 324215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 325215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 326215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 327215976Sjmallett info.func = __cvmx_error_display; 328215976Sjmallett info.user_info = (long) 329215976Sjmallett "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n"; 330215976Sjmallett fail |= cvmx_error_add(&info); 331215976Sjmallett 332215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 333215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(2); 334215976Sjmallett info.status_mask = 1ull<<7 /* rxovf */; 335215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(2); 336215976Sjmallett info.enable_mask = 1ull<<7 /* rxovf */; 337215976Sjmallett info.flags = 0; 338215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 339215976Sjmallett info.group_index = 0; 340215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 341215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 342215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 343215976Sjmallett info.func = __cvmx_error_display; 344215976Sjmallett info.user_info = (long) 345215976Sjmallett "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n"; 346215976Sjmallett fail |= cvmx_error_add(&info); 347215976Sjmallett 348215976Sjmallett /* CVMX_PCMX_INT_SUM(3) */ 349215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 350215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(3); 351215976Sjmallett info.status_mask = 1ull<<0 /* fsyncmissed */; 352215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(3); 353215976Sjmallett info.enable_mask = 1ull<<0 /* fsyncmissed */; 354215976Sjmallett info.flags = 0; 355215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 356215976Sjmallett info.group_index = 0; 357215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 358215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 359215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 360215976Sjmallett info.func = __cvmx_error_display; 361215976Sjmallett info.user_info = (long) 362215976Sjmallett "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n"; 363215976Sjmallett fail |= cvmx_error_add(&info); 364215976Sjmallett 365215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 366215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(3); 367215976Sjmallett info.status_mask = 1ull<<1 /* fsyncextra */; 368215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(3); 369215976Sjmallett info.enable_mask = 1ull<<1 /* fsyncextra */; 370215976Sjmallett info.flags = 0; 371215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 372215976Sjmallett info.group_index = 0; 373215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 374215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 375215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 376215976Sjmallett info.func = __cvmx_error_display; 377215976Sjmallett info.user_info = (long) 378215976Sjmallett "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n"; 379215976Sjmallett fail |= cvmx_error_add(&info); 380215976Sjmallett 381215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 382215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(3); 383215976Sjmallett info.status_mask = 1ull<<6 /* txempty */; 384215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(3); 385215976Sjmallett info.enable_mask = 1ull<<6 /* txempty */; 386215976Sjmallett info.flags = 0; 387215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 388215976Sjmallett info.group_index = 0; 389215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 390215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 391215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 392215976Sjmallett info.func = __cvmx_error_display; 393215976Sjmallett info.user_info = (long) 394215976Sjmallett "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n"; 395215976Sjmallett fail |= cvmx_error_add(&info); 396215976Sjmallett 397215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 398215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(3); 399215976Sjmallett info.status_mask = 1ull<<7 /* rxovf */; 400215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(3); 401215976Sjmallett info.enable_mask = 1ull<<7 /* rxovf */; 402215976Sjmallett info.flags = 0; 403215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 404215976Sjmallett info.group_index = 0; 405215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 406215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 407215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 408215976Sjmallett info.func = __cvmx_error_display; 409215976Sjmallett info.user_info = (long) 410215976Sjmallett "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n"; 411215976Sjmallett fail |= cvmx_error_add(&info); 412215976Sjmallett 413215976Sjmallett /* CVMX_CIU_INT_SUM1 */ 414215976Sjmallett /* CVMX_NPI_RSL_INT_BLOCKS */ 415215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 416215976Sjmallett info.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 417215976Sjmallett info.status_mask = 0; 418215976Sjmallett info.enable_addr = 0; 419215976Sjmallett info.enable_mask = 0; 420215976Sjmallett info.flags = 0; 421215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 422215976Sjmallett info.group_index = 0; 423215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 424215976Sjmallett info.parent.status_addr = 0; 425215976Sjmallett info.parent.status_mask = 0; 426215976Sjmallett info.func = __cvmx_error_decode; 427215976Sjmallett info.user_info = 0; 428215976Sjmallett fail |= cvmx_error_add(&info); 429215976Sjmallett 430215976Sjmallett /* CVMX_L2D_ERR */ 431215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 432215976Sjmallett info.status_addr = CVMX_L2D_ERR; 433215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 434215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 435215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 436215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 437215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 438215976Sjmallett info.group_index = 0; 439215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 440215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 441215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 442215976Sjmallett info.func = __cvmx_error_handle_l2d_err_sec_err; 443215976Sjmallett info.user_info = (long) 444215976Sjmallett "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n"; 445215976Sjmallett fail |= cvmx_error_add(&info); 446215976Sjmallett 447215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 448215976Sjmallett info.status_addr = CVMX_L2D_ERR; 449215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 450215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 451215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 452215976Sjmallett info.flags = 0; 453215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 454215976Sjmallett info.group_index = 0; 455215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 456215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 457215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 458215976Sjmallett info.func = __cvmx_error_handle_l2d_err_ded_err; 459215976Sjmallett info.user_info = (long) 460215976Sjmallett "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n"; 461215976Sjmallett fail |= cvmx_error_add(&info); 462215976Sjmallett 463215976Sjmallett /* CVMX_L2T_ERR */ 464215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 465215976Sjmallett info.status_addr = CVMX_L2T_ERR; 466215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 467215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 468215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 469215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 470215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 471215976Sjmallett info.group_index = 0; 472215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 473215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 474215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 475215976Sjmallett info.func = __cvmx_error_handle_l2t_err_sec_err; 476215976Sjmallett info.user_info = (long) 477215976Sjmallett "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n" 478215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 479215976Sjmallett " given index) are checked for single bit errors(SBEs).\n" 480215976Sjmallett " This bit is set if ANY of the 8 sets contains an SBE.\n" 481215976Sjmallett " SBEs are auto corrected in HW and generate an\n" 482215976Sjmallett " interrupt(if enabled).\n"; 483215976Sjmallett fail |= cvmx_error_add(&info); 484215976Sjmallett 485215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 486215976Sjmallett info.status_addr = CVMX_L2T_ERR; 487215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 488215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 489215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 490215976Sjmallett info.flags = 0; 491215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 492215976Sjmallett info.group_index = 0; 493215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 494215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 495215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 496215976Sjmallett info.func = __cvmx_error_handle_l2t_err_ded_err; 497215976Sjmallett info.user_info = (long) 498215976Sjmallett "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n" 499215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 500215976Sjmallett " given index) are checked for double bit errors(DBEs).\n" 501215976Sjmallett " This bit is set if ANY of the 8 sets contains a DBE.\n" 502215976Sjmallett " DBEs also generated an interrupt(if enabled).\n"; 503215976Sjmallett fail |= cvmx_error_add(&info); 504215976Sjmallett 505215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 506215976Sjmallett info.status_addr = CVMX_L2T_ERR; 507215976Sjmallett info.status_mask = 1ull<<24 /* lckerr */; 508215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 509215976Sjmallett info.enable_mask = 1ull<<25 /* lck_intena */; 510215976Sjmallett info.flags = 0; 511215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 512215976Sjmallett info.group_index = 0; 513215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 514215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 515215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 516215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr; 517215976Sjmallett info.user_info = (long) 518215976Sjmallett "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n" 519215976Sjmallett " the INDEX (which is ignored by HW - but reported to SW).\n" 520215976Sjmallett " The LDD(L1 load-miss) for the LOCK operation is completed\n" 521215976Sjmallett " successfully, however the address is NOT locked.\n" 522215976Sjmallett " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n" 523215976Sjmallett " into account. For example, if diagnostic PPx has\n" 524215976Sjmallett " UMSKx defined to only use SETs [1:0], and SET1 had\n" 525215976Sjmallett " been previously LOCKED, then an attempt to LOCK the\n" 526215976Sjmallett " last available SET0 would result in a LCKERR. (This\n" 527215976Sjmallett " is to ensure that at least 1 SET at each INDEX is\n" 528215976Sjmallett " not LOCKED for general use by other PPs).\n"; 529215976Sjmallett fail |= cvmx_error_add(&info); 530215976Sjmallett 531215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 532215976Sjmallett info.status_addr = CVMX_L2T_ERR; 533215976Sjmallett info.status_mask = 1ull<<26 /* lckerr2 */; 534215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 535215976Sjmallett info.enable_mask = 1ull<<27 /* lck_intena2 */; 536215976Sjmallett info.flags = 0; 537215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 538215976Sjmallett info.group_index = 0; 539215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 540215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 541215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 542215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr2; 543215976Sjmallett info.user_info = (long) 544215976Sjmallett "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n" 545215976Sjmallett " could not find an available/unlocked set (for\n" 546215976Sjmallett " replacement).\n" 547215976Sjmallett " Most likely, this is a result of SW mixing SET\n" 548215976Sjmallett " PARTITIONING with ADDRESS LOCKING. If SW allows\n" 549215976Sjmallett " another PP to LOCKDOWN all SETs available to PP#n,\n" 550215976Sjmallett " then a Rd/Wr Miss from PP#n will be unable\n" 551215976Sjmallett " to determine a 'valid' replacement set (since LOCKED\n" 552215976Sjmallett " addresses should NEVER be replaced).\n" 553215976Sjmallett " If such an event occurs, the HW will select the smallest\n" 554215976Sjmallett " available SET(specified by UMSK'x)' as the replacement\n" 555215976Sjmallett " set, and the address is unlocked.\n"; 556215976Sjmallett fail |= cvmx_error_add(&info); 557215976Sjmallett 558215976Sjmallett /* CVMX_NPI_INT_SUM */ 559215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 560215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 561215976Sjmallett info.status_mask = 1ull<<0 /* rml_rto */; 562215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 563215976Sjmallett info.enable_mask = 1ull<<0 /* rml_rto */; 564215976Sjmallett info.flags = 0; 565215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 566215976Sjmallett info.group_index = 0; 567215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 568215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 569215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 570215976Sjmallett info.func = __cvmx_error_display; 571215976Sjmallett info.user_info = (long) 572215976Sjmallett "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n" 573215976Sjmallett " back from a RSL after sending a read command to\n" 574215976Sjmallett " a RSL.\n"; 575215976Sjmallett fail |= cvmx_error_add(&info); 576215976Sjmallett 577215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 578215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 579215976Sjmallett info.status_mask = 1ull<<1 /* rml_wto */; 580215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 581215976Sjmallett info.enable_mask = 1ull<<1 /* rml_wto */; 582215976Sjmallett info.flags = 0; 583215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 584215976Sjmallett info.group_index = 0; 585215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 586215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 587215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 588215976Sjmallett info.func = __cvmx_error_display; 589215976Sjmallett info.user_info = (long) 590215976Sjmallett "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n" 591215976Sjmallett " back from a RSL after sending a write command to\n" 592215976Sjmallett " a RSL.\n"; 593215976Sjmallett fail |= cvmx_error_add(&info); 594215976Sjmallett 595215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 596215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 597215976Sjmallett info.status_mask = 1ull<<3 /* po0_2sml */; 598215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 599215976Sjmallett info.enable_mask = 1ull<<3 /* po0_2sml */; 600215976Sjmallett info.flags = 0; 601215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 602215976Sjmallett info.group_index = 0; 603215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 604215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 605215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 606215976Sjmallett info.func = __cvmx_error_display; 607215976Sjmallett info.user_info = (long) 608215976Sjmallett "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n" 609215976Sjmallett " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n"; 610215976Sjmallett fail |= cvmx_error_add(&info); 611215976Sjmallett 612215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 613215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 614215976Sjmallett info.status_mask = 1ull<<4 /* po1_2sml */; 615215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 616215976Sjmallett info.enable_mask = 1ull<<4 /* po1_2sml */; 617215976Sjmallett info.flags = 0; 618215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 619215976Sjmallett info.group_index = 0; 620215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 621215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 622215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 623215976Sjmallett info.func = __cvmx_error_display; 624215976Sjmallett info.user_info = (long) 625215976Sjmallett "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n" 626215976Sjmallett " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n"; 627215976Sjmallett fail |= cvmx_error_add(&info); 628215976Sjmallett 629215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 630215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 631215976Sjmallett info.status_mask = 1ull<<7 /* i0_rtout */; 632215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 633215976Sjmallett info.enable_mask = 1ull<<7 /* i0_rtout */; 634215976Sjmallett info.flags = 0; 635215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 636215976Sjmallett info.group_index = 0; 637215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 638215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 639215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 640215976Sjmallett info.func = __cvmx_error_display; 641215976Sjmallett info.user_info = (long) 642215976Sjmallett "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n" 643215976Sjmallett " read instructions.\n"; 644215976Sjmallett fail |= cvmx_error_add(&info); 645215976Sjmallett 646215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 647215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 648215976Sjmallett info.status_mask = 1ull<<8 /* i1_rtout */; 649215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 650215976Sjmallett info.enable_mask = 1ull<<8 /* i1_rtout */; 651215976Sjmallett info.flags = 0; 652215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 653215976Sjmallett info.group_index = 0; 654215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 655215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 656215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 657215976Sjmallett info.func = __cvmx_error_display; 658215976Sjmallett info.user_info = (long) 659215976Sjmallett "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n" 660215976Sjmallett " read instructions.\n"; 661215976Sjmallett fail |= cvmx_error_add(&info); 662215976Sjmallett 663215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 664215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 665215976Sjmallett info.status_mask = 1ull<<11 /* i0_overf */; 666215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 667215976Sjmallett info.enable_mask = 1ull<<11 /* i0_overf */; 668215976Sjmallett info.flags = 0; 669215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 670215976Sjmallett info.group_index = 0; 671215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 672215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 673215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 674215976Sjmallett info.func = __cvmx_error_display; 675215976Sjmallett info.user_info = (long) 676215976Sjmallett "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n" 677215976Sjmallett " doorbell count was set.\n"; 678215976Sjmallett fail |= cvmx_error_add(&info); 679215976Sjmallett 680215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 681215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 682215976Sjmallett info.status_mask = 1ull<<12 /* i1_overf */; 683215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 684215976Sjmallett info.enable_mask = 1ull<<12 /* i1_overf */; 685215976Sjmallett info.flags = 0; 686215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 687215976Sjmallett info.group_index = 0; 688215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 689215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 690215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 691215976Sjmallett info.func = __cvmx_error_display; 692215976Sjmallett info.user_info = (long) 693215976Sjmallett "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n" 694215976Sjmallett " doorbell count was set.\n"; 695215976Sjmallett fail |= cvmx_error_add(&info); 696215976Sjmallett 697215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 698215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 699215976Sjmallett info.status_mask = 1ull<<15 /* p0_rtout */; 700215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 701215976Sjmallett info.enable_mask = 1ull<<15 /* p0_rtout */; 702215976Sjmallett info.flags = 0; 703215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 704215976Sjmallett info.group_index = 0; 705215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 706215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 707215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 708215976Sjmallett info.func = __cvmx_error_display; 709215976Sjmallett info.user_info = (long) 710215976Sjmallett "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n" 711215976Sjmallett " read packet data.\n"; 712215976Sjmallett fail |= cvmx_error_add(&info); 713215976Sjmallett 714215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 715215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 716215976Sjmallett info.status_mask = 1ull<<16 /* p1_rtout */; 717215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 718215976Sjmallett info.enable_mask = 1ull<<16 /* p1_rtout */; 719215976Sjmallett info.flags = 0; 720215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 721215976Sjmallett info.group_index = 0; 722215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 723215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 724215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 725215976Sjmallett info.func = __cvmx_error_display; 726215976Sjmallett info.user_info = (long) 727215976Sjmallett "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n" 728215976Sjmallett " read packet data.\n"; 729215976Sjmallett fail |= cvmx_error_add(&info); 730215976Sjmallett 731215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 732215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 733215976Sjmallett info.status_mask = 1ull<<19 /* p0_perr */; 734215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 735215976Sjmallett info.enable_mask = 1ull<<19 /* p0_perr */; 736215976Sjmallett info.flags = 0; 737215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 738215976Sjmallett info.group_index = 0; 739215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 740215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 741215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 742215976Sjmallett info.func = __cvmx_error_display; 743215976Sjmallett info.user_info = (long) 744215976Sjmallett "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n" 745215976Sjmallett " data this bit may be set.\n"; 746215976Sjmallett fail |= cvmx_error_add(&info); 747215976Sjmallett 748215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 749215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 750215976Sjmallett info.status_mask = 1ull<<20 /* p1_perr */; 751215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 752215976Sjmallett info.enable_mask = 1ull<<20 /* p1_perr */; 753215976Sjmallett info.flags = 0; 754215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 755215976Sjmallett info.group_index = 0; 756215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 757215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 758215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 759215976Sjmallett info.func = __cvmx_error_display; 760215976Sjmallett info.user_info = (long) 761215976Sjmallett "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n" 762215976Sjmallett " data this bit may be set.\n"; 763215976Sjmallett fail |= cvmx_error_add(&info); 764215976Sjmallett 765215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 766215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 767215976Sjmallett info.status_mask = 1ull<<23 /* g0_rtout */; 768215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 769215976Sjmallett info.enable_mask = 1ull<<23 /* g0_rtout */; 770215976Sjmallett info.flags = 0; 771215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 772215976Sjmallett info.group_index = 0; 773215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 774215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 775215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 776215976Sjmallett info.func = __cvmx_error_display; 777215976Sjmallett info.user_info = (long) 778215976Sjmallett "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n" 779215976Sjmallett " read a gather list.\n"; 780215976Sjmallett fail |= cvmx_error_add(&info); 781215976Sjmallett 782215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 783215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 784215976Sjmallett info.status_mask = 1ull<<24 /* g1_rtout */; 785215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 786215976Sjmallett info.enable_mask = 1ull<<24 /* g1_rtout */; 787215976Sjmallett info.flags = 0; 788215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 789215976Sjmallett info.group_index = 0; 790215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 791215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 792215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 793215976Sjmallett info.func = __cvmx_error_display; 794215976Sjmallett info.user_info = (long) 795215976Sjmallett "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n" 796215976Sjmallett " read a gather list.\n"; 797215976Sjmallett fail |= cvmx_error_add(&info); 798215976Sjmallett 799215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 800215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 801215976Sjmallett info.status_mask = 1ull<<27 /* p0_pperr */; 802215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 803215976Sjmallett info.enable_mask = 1ull<<27 /* p0_pperr */; 804215976Sjmallett info.flags = 0; 805215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 806215976Sjmallett info.group_index = 0; 807215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 808215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 809215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 810215976Sjmallett info.func = __cvmx_error_display; 811215976Sjmallett info.user_info = (long) 812215976Sjmallett "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n" 813215976Sjmallett " pointer-pair, this bit may be set.\n"; 814215976Sjmallett fail |= cvmx_error_add(&info); 815215976Sjmallett 816215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 817215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 818215976Sjmallett info.status_mask = 1ull<<28 /* p1_pperr */; 819215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 820215976Sjmallett info.enable_mask = 1ull<<28 /* p1_pperr */; 821215976Sjmallett info.flags = 0; 822215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 823215976Sjmallett info.group_index = 0; 824215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 825215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 826215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 827215976Sjmallett info.func = __cvmx_error_display; 828215976Sjmallett info.user_info = (long) 829215976Sjmallett "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n" 830215976Sjmallett " pointer-pair, this bit may be set.\n"; 831215976Sjmallett fail |= cvmx_error_add(&info); 832215976Sjmallett 833215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 834215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 835215976Sjmallett info.status_mask = 1ull<<31 /* p0_ptout */; 836215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 837215976Sjmallett info.enable_mask = 1ull<<31 /* p0_ptout */; 838215976Sjmallett info.flags = 0; 839215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 840215976Sjmallett info.group_index = 0; 841215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 842215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 843215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 844215976Sjmallett info.func = __cvmx_error_display; 845215976Sjmallett info.user_info = (long) 846215976Sjmallett "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n" 847215976Sjmallett " pair.\n"; 848215976Sjmallett fail |= cvmx_error_add(&info); 849215976Sjmallett 850215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 851215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 852215976Sjmallett info.status_mask = 1ull<<32 /* p1_ptout */; 853215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 854215976Sjmallett info.enable_mask = 1ull<<32 /* p1_ptout */; 855215976Sjmallett info.flags = 0; 856215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 857215976Sjmallett info.group_index = 0; 858215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 859215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 860215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 861215976Sjmallett info.func = __cvmx_error_display; 862215976Sjmallett info.user_info = (long) 863215976Sjmallett "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n" 864215976Sjmallett " pair.\n"; 865215976Sjmallett fail |= cvmx_error_add(&info); 866215976Sjmallett 867215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 868215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 869215976Sjmallett info.status_mask = 1ull<<35 /* i0_pperr */; 870215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 871215976Sjmallett info.enable_mask = 1ull<<35 /* i0_pperr */; 872215976Sjmallett info.flags = 0; 873215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 874215976Sjmallett info.group_index = 0; 875215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 876215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 877215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 878215976Sjmallett info.func = __cvmx_error_display; 879215976Sjmallett info.user_info = (long) 880215976Sjmallett "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n" 881215976Sjmallett " this bit may be set.\n"; 882215976Sjmallett fail |= cvmx_error_add(&info); 883215976Sjmallett 884215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 885215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 886215976Sjmallett info.status_mask = 1ull<<36 /* i1_pperr */; 887215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 888215976Sjmallett info.enable_mask = 1ull<<36 /* i1_pperr */; 889215976Sjmallett info.flags = 0; 890215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 891215976Sjmallett info.group_index = 0; 892215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 893215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 894215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 895215976Sjmallett info.func = __cvmx_error_display; 896215976Sjmallett info.user_info = (long) 897215976Sjmallett "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n" 898215976Sjmallett " this bit may be set.\n"; 899215976Sjmallett fail |= cvmx_error_add(&info); 900215976Sjmallett 901215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 902215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 903215976Sjmallett info.status_mask = 1ull<<39 /* win_rto */; 904215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 905215976Sjmallett info.enable_mask = 1ull<<39 /* win_rto */; 906215976Sjmallett info.flags = 0; 907215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 908215976Sjmallett info.group_index = 0; 909215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 910215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 911215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 912215976Sjmallett info.func = __cvmx_error_display; 913215976Sjmallett info.user_info = (long) 914215976Sjmallett "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n"; 915215976Sjmallett fail |= cvmx_error_add(&info); 916215976Sjmallett 917215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 918215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 919215976Sjmallett info.status_mask = 1ull<<40 /* p_dperr */; 920215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 921215976Sjmallett info.enable_mask = 1ull<<40 /* p_dperr */; 922215976Sjmallett info.flags = 0; 923215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 924215976Sjmallett info.group_index = 0; 925215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 926215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 927215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 928215976Sjmallett info.func = __cvmx_error_display; 929215976Sjmallett info.user_info = (long) 930215976Sjmallett "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n" 931215976Sjmallett " from the PCI this bit may be set.\n"; 932215976Sjmallett fail |= cvmx_error_add(&info); 933215976Sjmallett 934215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 935215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 936215976Sjmallett info.status_mask = 1ull<<41 /* iobdma */; 937215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 938215976Sjmallett info.enable_mask = 1ull<<41 /* iobdma */; 939215976Sjmallett info.flags = 0; 940215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 941215976Sjmallett info.group_index = 0; 942215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 943215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 944215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 945215976Sjmallett info.func = __cvmx_error_display; 946215976Sjmallett info.user_info = (long) 947215976Sjmallett "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n"; 948215976Sjmallett fail |= cvmx_error_add(&info); 949215976Sjmallett 950215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 951215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 952215976Sjmallett info.status_mask = 1ull<<42 /* fcr_s_e */; 953215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 954215976Sjmallett info.enable_mask = 1ull<<42 /* fcr_s_e */; 955215976Sjmallett info.flags = 0; 956215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 957215976Sjmallett info.group_index = 0; 958215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 959215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 960215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 961215976Sjmallett info.func = __cvmx_error_display; 962215976Sjmallett info.user_info = (long) 963215976Sjmallett "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"; 964215976Sjmallett fail |= cvmx_error_add(&info); 965215976Sjmallett 966215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 967215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 968215976Sjmallett info.status_mask = 1ull<<43 /* fcr_a_f */; 969215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 970215976Sjmallett info.enable_mask = 1ull<<43 /* fcr_a_f */; 971215976Sjmallett info.flags = 0; 972215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 973215976Sjmallett info.group_index = 0; 974215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 975215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 976215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 977215976Sjmallett info.func = __cvmx_error_display; 978215976Sjmallett info.user_info = (long) 979215976Sjmallett "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"; 980215976Sjmallett fail |= cvmx_error_add(&info); 981215976Sjmallett 982215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 983215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 984215976Sjmallett info.status_mask = 1ull<<44 /* pcr_s_e */; 985215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 986215976Sjmallett info.enable_mask = 1ull<<44 /* pcr_s_e */; 987215976Sjmallett info.flags = 0; 988215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 989215976Sjmallett info.group_index = 0; 990215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 991215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 992215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 993215976Sjmallett info.func = __cvmx_error_display; 994215976Sjmallett info.user_info = (long) 995215976Sjmallett "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"; 996215976Sjmallett fail |= cvmx_error_add(&info); 997215976Sjmallett 998215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 999215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1000215976Sjmallett info.status_mask = 1ull<<45 /* pcr_a_f */; 1001215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1002215976Sjmallett info.enable_mask = 1ull<<45 /* pcr_a_f */; 1003215976Sjmallett info.flags = 0; 1004215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1005215976Sjmallett info.group_index = 0; 1006215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1007215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1008215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1009215976Sjmallett info.func = __cvmx_error_display; 1010215976Sjmallett info.user_info = (long) 1011215976Sjmallett "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"; 1012215976Sjmallett fail |= cvmx_error_add(&info); 1013215976Sjmallett 1014215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1015215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1016215976Sjmallett info.status_mask = 1ull<<46 /* q2_s_e */; 1017215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1018215976Sjmallett info.enable_mask = 1ull<<46 /* q2_s_e */; 1019215976Sjmallett info.flags = 0; 1020215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1021215976Sjmallett info.group_index = 0; 1022215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1023215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1024215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1025215976Sjmallett info.func = __cvmx_error_display; 1026215976Sjmallett info.user_info = (long) 1027215976Sjmallett "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"; 1028215976Sjmallett fail |= cvmx_error_add(&info); 1029215976Sjmallett 1030215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1031215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1032215976Sjmallett info.status_mask = 1ull<<47 /* q2_a_f */; 1033215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1034215976Sjmallett info.enable_mask = 1ull<<47 /* q2_a_f */; 1035215976Sjmallett info.flags = 0; 1036215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1037215976Sjmallett info.group_index = 0; 1038215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1039215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1040215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1041215976Sjmallett info.func = __cvmx_error_display; 1042215976Sjmallett info.user_info = (long) 1043215976Sjmallett "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"; 1044215976Sjmallett fail |= cvmx_error_add(&info); 1045215976Sjmallett 1046215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1047215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1048215976Sjmallett info.status_mask = 1ull<<48 /* q3_s_e */; 1049215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1050215976Sjmallett info.enable_mask = 1ull<<48 /* q3_s_e */; 1051215976Sjmallett info.flags = 0; 1052215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1053215976Sjmallett info.group_index = 0; 1054215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1055215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1056215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1057215976Sjmallett info.func = __cvmx_error_display; 1058215976Sjmallett info.user_info = (long) 1059215976Sjmallett "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"; 1060215976Sjmallett fail |= cvmx_error_add(&info); 1061215976Sjmallett 1062215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1063215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1064215976Sjmallett info.status_mask = 1ull<<49 /* q3_a_f */; 1065215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1066215976Sjmallett info.enable_mask = 1ull<<49 /* q3_a_f */; 1067215976Sjmallett info.flags = 0; 1068215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1069215976Sjmallett info.group_index = 0; 1070215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1071215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1072215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1073215976Sjmallett info.func = __cvmx_error_display; 1074215976Sjmallett info.user_info = (long) 1075215976Sjmallett "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"; 1076215976Sjmallett fail |= cvmx_error_add(&info); 1077215976Sjmallett 1078215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1079215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1080215976Sjmallett info.status_mask = 1ull<<50 /* com_s_e */; 1081215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1082215976Sjmallett info.enable_mask = 1ull<<50 /* com_s_e */; 1083215976Sjmallett info.flags = 0; 1084215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1085215976Sjmallett info.group_index = 0; 1086215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1087215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1088215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1089215976Sjmallett info.func = __cvmx_error_display; 1090215976Sjmallett info.user_info = (long) 1091215976Sjmallett "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"; 1092215976Sjmallett fail |= cvmx_error_add(&info); 1093215976Sjmallett 1094215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1095215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1096215976Sjmallett info.status_mask = 1ull<<51 /* com_a_f */; 1097215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1098215976Sjmallett info.enable_mask = 1ull<<51 /* com_a_f */; 1099215976Sjmallett info.flags = 0; 1100215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1101215976Sjmallett info.group_index = 0; 1102215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1103215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1104215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1105215976Sjmallett info.func = __cvmx_error_display; 1106215976Sjmallett info.user_info = (long) 1107215976Sjmallett "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"; 1108215976Sjmallett fail |= cvmx_error_add(&info); 1109215976Sjmallett 1110215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1111215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1112215976Sjmallett info.status_mask = 1ull<<52 /* pnc_s_e */; 1113215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1114215976Sjmallett info.enable_mask = 1ull<<52 /* pnc_s_e */; 1115215976Sjmallett info.flags = 0; 1116215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1117215976Sjmallett info.group_index = 0; 1118215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1119215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1120215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1121215976Sjmallett info.func = __cvmx_error_display; 1122215976Sjmallett info.user_info = (long) 1123215976Sjmallett "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"; 1124215976Sjmallett fail |= cvmx_error_add(&info); 1125215976Sjmallett 1126215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1127215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1128215976Sjmallett info.status_mask = 1ull<<53 /* pnc_a_f */; 1129215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1130215976Sjmallett info.enable_mask = 1ull<<53 /* pnc_a_f */; 1131215976Sjmallett info.flags = 0; 1132215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1133215976Sjmallett info.group_index = 0; 1134215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1135215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1136215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1137215976Sjmallett info.func = __cvmx_error_display; 1138215976Sjmallett info.user_info = (long) 1139215976Sjmallett "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"; 1140215976Sjmallett fail |= cvmx_error_add(&info); 1141215976Sjmallett 1142215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1143215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1144215976Sjmallett info.status_mask = 1ull<<54 /* rwx_s_e */; 1145215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1146215976Sjmallett info.enable_mask = 1ull<<54 /* rwx_s_e */; 1147215976Sjmallett info.flags = 0; 1148215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1149215976Sjmallett info.group_index = 0; 1150215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1151215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1152215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1153215976Sjmallett info.func = __cvmx_error_display; 1154215976Sjmallett info.user_info = (long) 1155215976Sjmallett "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"; 1156215976Sjmallett fail |= cvmx_error_add(&info); 1157215976Sjmallett 1158215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1159215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1160215976Sjmallett info.status_mask = 1ull<<55 /* rdx_s_e */; 1161215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1162215976Sjmallett info.enable_mask = 1ull<<55 /* rdx_s_e */; 1163215976Sjmallett info.flags = 0; 1164215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1165215976Sjmallett info.group_index = 0; 1166215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1167215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1168215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1169215976Sjmallett info.func = __cvmx_error_display; 1170215976Sjmallett info.user_info = (long) 1171215976Sjmallett "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"; 1172215976Sjmallett fail |= cvmx_error_add(&info); 1173215976Sjmallett 1174215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1175215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1176215976Sjmallett info.status_mask = 1ull<<56 /* pcf_p_e */; 1177215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1178215976Sjmallett info.enable_mask = 1ull<<56 /* pcf_p_e */; 1179215976Sjmallett info.flags = 0; 1180215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1181215976Sjmallett info.group_index = 0; 1182215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1183215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1184215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1185215976Sjmallett info.func = __cvmx_error_display; 1186215976Sjmallett info.user_info = (long) 1187215976Sjmallett "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"; 1188215976Sjmallett fail |= cvmx_error_add(&info); 1189215976Sjmallett 1190215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1191215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1192215976Sjmallett info.status_mask = 1ull<<57 /* pcf_p_f */; 1193215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1194215976Sjmallett info.enable_mask = 1ull<<57 /* pcf_p_f */; 1195215976Sjmallett info.flags = 0; 1196215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1197215976Sjmallett info.group_index = 0; 1198215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1199215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1200215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1201215976Sjmallett info.func = __cvmx_error_display; 1202215976Sjmallett info.user_info = (long) 1203215976Sjmallett "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"; 1204215976Sjmallett fail |= cvmx_error_add(&info); 1205215976Sjmallett 1206215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1207215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1208215976Sjmallett info.status_mask = 1ull<<58 /* pdf_p_e */; 1209215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1210215976Sjmallett info.enable_mask = 1ull<<58 /* pdf_p_e */; 1211215976Sjmallett info.flags = 0; 1212215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1213215976Sjmallett info.group_index = 0; 1214215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1215215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1216215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1217215976Sjmallett info.func = __cvmx_error_display; 1218215976Sjmallett info.user_info = (long) 1219215976Sjmallett "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"; 1220215976Sjmallett fail |= cvmx_error_add(&info); 1221215976Sjmallett 1222215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1223215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1224215976Sjmallett info.status_mask = 1ull<<59 /* pdf_p_f */; 1225215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1226215976Sjmallett info.enable_mask = 1ull<<59 /* pdf_p_f */; 1227215976Sjmallett info.flags = 0; 1228215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1229215976Sjmallett info.group_index = 0; 1230215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1231215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1232215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1233215976Sjmallett info.func = __cvmx_error_display; 1234215976Sjmallett info.user_info = (long) 1235215976Sjmallett "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"; 1236215976Sjmallett fail |= cvmx_error_add(&info); 1237215976Sjmallett 1238215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1239215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1240215976Sjmallett info.status_mask = 1ull<<60 /* q1_s_e */; 1241215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1242215976Sjmallett info.enable_mask = 1ull<<60 /* q1_s_e */; 1243215976Sjmallett info.flags = 0; 1244215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1245215976Sjmallett info.group_index = 0; 1246215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1247215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1248215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1249215976Sjmallett info.func = __cvmx_error_display; 1250215976Sjmallett info.user_info = (long) 1251215976Sjmallett "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"; 1252215976Sjmallett fail |= cvmx_error_add(&info); 1253215976Sjmallett 1254215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1255215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1256215976Sjmallett info.status_mask = 1ull<<61 /* q1_a_f */; 1257215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1258215976Sjmallett info.enable_mask = 1ull<<61 /* q1_a_f */; 1259215976Sjmallett info.flags = 0; 1260215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1261215976Sjmallett info.group_index = 0; 1262215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1263215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1264215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1265215976Sjmallett info.func = __cvmx_error_display; 1266215976Sjmallett info.user_info = (long) 1267215976Sjmallett "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"; 1268215976Sjmallett fail |= cvmx_error_add(&info); 1269215976Sjmallett 1270215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1271215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1272215976Sjmallett info.status_mask = 0; 1273215976Sjmallett info.enable_addr = 0; 1274215976Sjmallett info.enable_mask = 0; 1275215976Sjmallett info.flags = 0; 1276215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1277215976Sjmallett info.group_index = 0; 1278215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1279215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1280215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1281215976Sjmallett info.func = __cvmx_error_decode; 1282215976Sjmallett info.user_info = 0; 1283215976Sjmallett fail |= cvmx_error_add(&info); 1284215976Sjmallett 1285215976Sjmallett /* CVMX_NPI_PCI_INT_SUM2 */ 1286215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1287215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1288215976Sjmallett info.status_mask = 1ull<<0 /* tr_wabt */; 1289215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1290215976Sjmallett info.enable_mask = 1ull<<0 /* rtr_wabt */; 1291215976Sjmallett info.flags = 0; 1292215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1293215976Sjmallett info.group_index = 0; 1294215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1295215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1296215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1297215976Sjmallett info.func = __cvmx_error_display; 1298215976Sjmallett info.user_info = (long) 1299215976Sjmallett "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n"; 1300215976Sjmallett fail |= cvmx_error_add(&info); 1301215976Sjmallett 1302215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1303215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1304215976Sjmallett info.status_mask = 1ull<<1 /* mr_wabt */; 1305215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1306215976Sjmallett info.enable_mask = 1ull<<1 /* rmr_wabt */; 1307215976Sjmallett info.flags = 0; 1308215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1309215976Sjmallett info.group_index = 0; 1310215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1311215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1312215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1313215976Sjmallett info.func = __cvmx_error_display; 1314215976Sjmallett info.user_info = (long) 1315215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n"; 1316215976Sjmallett fail |= cvmx_error_add(&info); 1317215976Sjmallett 1318215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1319215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1320215976Sjmallett info.status_mask = 1ull<<2 /* mr_wtto */; 1321215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1322215976Sjmallett info.enable_mask = 1ull<<2 /* rmr_wtto */; 1323215976Sjmallett info.flags = 0; 1324215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1325215976Sjmallett info.group_index = 0; 1326215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1327215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1328215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1329215976Sjmallett info.func = __cvmx_error_display; 1330215976Sjmallett info.user_info = (long) 1331215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n"; 1332215976Sjmallett fail |= cvmx_error_add(&info); 1333215976Sjmallett 1334215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1335215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1336215976Sjmallett info.status_mask = 1ull<<3 /* tr_abt */; 1337215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1338215976Sjmallett info.enable_mask = 1ull<<3 /* rtr_abt */; 1339215976Sjmallett info.flags = 0; 1340215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1341215976Sjmallett info.group_index = 0; 1342215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1343215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1344215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1345215976Sjmallett info.func = __cvmx_error_display; 1346215976Sjmallett info.user_info = (long) 1347215976Sjmallett "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n"; 1348215976Sjmallett fail |= cvmx_error_add(&info); 1349215976Sjmallett 1350215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1351215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1352215976Sjmallett info.status_mask = 1ull<<4 /* mr_abt */; 1353215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1354215976Sjmallett info.enable_mask = 1ull<<4 /* rmr_abt */; 1355215976Sjmallett info.flags = 0; 1356215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1357215976Sjmallett info.group_index = 0; 1358215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1359215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1360215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1361215976Sjmallett info.func = __cvmx_error_display; 1362215976Sjmallett info.user_info = (long) 1363215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n"; 1364215976Sjmallett fail |= cvmx_error_add(&info); 1365215976Sjmallett 1366215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1367215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1368215976Sjmallett info.status_mask = 1ull<<5 /* mr_tto */; 1369215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1370215976Sjmallett info.enable_mask = 1ull<<5 /* rmr_tto */; 1371215976Sjmallett info.flags = 0; 1372215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1373215976Sjmallett info.group_index = 0; 1374215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1375215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1376215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1377215976Sjmallett info.func = __cvmx_error_display; 1378215976Sjmallett info.user_info = (long) 1379215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n"; 1380215976Sjmallett fail |= cvmx_error_add(&info); 1381215976Sjmallett 1382215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1383215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1384215976Sjmallett info.status_mask = 1ull<<6 /* msi_per */; 1385215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1386215976Sjmallett info.enable_mask = 1ull<<6 /* rmsi_per */; 1387215976Sjmallett info.flags = 0; 1388215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1389215976Sjmallett info.group_index = 0; 1390215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1391215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1392215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1393215976Sjmallett info.func = __cvmx_error_display; 1394215976Sjmallett info.user_info = (long) 1395215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n"; 1396215976Sjmallett fail |= cvmx_error_add(&info); 1397215976Sjmallett 1398215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1399215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1400215976Sjmallett info.status_mask = 1ull<<7 /* msi_tabt */; 1401215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1402215976Sjmallett info.enable_mask = 1ull<<7 /* rmsi_tabt */; 1403215976Sjmallett info.flags = 0; 1404215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1405215976Sjmallett info.group_index = 0; 1406215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1407215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1408215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1409215976Sjmallett info.func = __cvmx_error_display; 1410215976Sjmallett info.user_info = (long) 1411215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n"; 1412215976Sjmallett fail |= cvmx_error_add(&info); 1413215976Sjmallett 1414215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1415215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1416215976Sjmallett info.status_mask = 1ull<<8 /* msi_mabt */; 1417215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1418215976Sjmallett info.enable_mask = 1ull<<8 /* rmsi_mabt */; 1419215976Sjmallett info.flags = 0; 1420215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1421215976Sjmallett info.group_index = 0; 1422215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1423215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1424215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1425215976Sjmallett info.func = __cvmx_error_display; 1426215976Sjmallett info.user_info = (long) 1427215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n"; 1428215976Sjmallett fail |= cvmx_error_add(&info); 1429215976Sjmallett 1430215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1431215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1432215976Sjmallett info.status_mask = 1ull<<9 /* msc_msg */; 1433215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1434215976Sjmallett info.enable_mask = 1ull<<9 /* rmsc_msg */; 1435215976Sjmallett info.flags = 0; 1436215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1437215976Sjmallett info.group_index = 0; 1438215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1439215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1440215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1441215976Sjmallett info.func = __cvmx_error_display; 1442215976Sjmallett info.user_info = (long) 1443215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n"; 1444215976Sjmallett fail |= cvmx_error_add(&info); 1445215976Sjmallett 1446215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1447215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1448215976Sjmallett info.status_mask = 1ull<<10 /* tsr_abt */; 1449215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1450215976Sjmallett info.enable_mask = 1ull<<10 /* rtsr_abt */; 1451215976Sjmallett info.flags = 0; 1452215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1453215976Sjmallett info.group_index = 0; 1454215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1455215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1456215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1457215976Sjmallett info.func = __cvmx_error_display; 1458215976Sjmallett info.user_info = (long) 1459215976Sjmallett "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n"; 1460215976Sjmallett fail |= cvmx_error_add(&info); 1461215976Sjmallett 1462215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1463215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1464215976Sjmallett info.status_mask = 1ull<<11 /* serr */; 1465215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1466215976Sjmallett info.enable_mask = 1ull<<11 /* rserr */; 1467215976Sjmallett info.flags = 0; 1468215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1469215976Sjmallett info.group_index = 0; 1470215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1471215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1472215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1473215976Sjmallett info.func = __cvmx_error_display; 1474215976Sjmallett info.user_info = (long) 1475215976Sjmallett "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n"; 1476215976Sjmallett fail |= cvmx_error_add(&info); 1477215976Sjmallett 1478215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1479215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1480215976Sjmallett info.status_mask = 1ull<<12 /* aperr */; 1481215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1482215976Sjmallett info.enable_mask = 1ull<<12 /* raperr */; 1483215976Sjmallett info.flags = 0; 1484215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1485215976Sjmallett info.group_index = 0; 1486215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1487215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1488215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1489215976Sjmallett info.func = __cvmx_error_display; 1490215976Sjmallett info.user_info = (long) 1491215976Sjmallett "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n"; 1492215976Sjmallett fail |= cvmx_error_add(&info); 1493215976Sjmallett 1494215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1495215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1496215976Sjmallett info.status_mask = 1ull<<13 /* dperr */; 1497215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1498215976Sjmallett info.enable_mask = 1ull<<13 /* rdperr */; 1499215976Sjmallett info.flags = 0; 1500215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1501215976Sjmallett info.group_index = 0; 1502215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1503215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1504215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1505215976Sjmallett info.func = __cvmx_error_display; 1506215976Sjmallett info.user_info = (long) 1507215976Sjmallett "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n"; 1508215976Sjmallett fail |= cvmx_error_add(&info); 1509215976Sjmallett 1510215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1511215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1512215976Sjmallett info.status_mask = 1ull<<14 /* ill_rwr */; 1513215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1514215976Sjmallett info.enable_mask = 1ull<<14 /* ill_rwr */; 1515215976Sjmallett info.flags = 0; 1516215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1517215976Sjmallett info.group_index = 0; 1518215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1519215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1520215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1521215976Sjmallett info.func = __cvmx_error_display; 1522215976Sjmallett info.user_info = (long) 1523215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n"; 1524215976Sjmallett fail |= cvmx_error_add(&info); 1525215976Sjmallett 1526215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1527215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1528215976Sjmallett info.status_mask = 1ull<<15 /* ill_rrd */; 1529215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1530215976Sjmallett info.enable_mask = 1ull<<15 /* ill_rrd */; 1531215976Sjmallett info.flags = 0; 1532215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1533215976Sjmallett info.group_index = 0; 1534215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1535215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1536215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1537215976Sjmallett info.func = __cvmx_error_display; 1538215976Sjmallett info.user_info = (long) 1539215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n"; 1540215976Sjmallett fail |= cvmx_error_add(&info); 1541215976Sjmallett 1542215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1543215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1544215976Sjmallett info.status_mask = 1ull<<31 /* win_wr */; 1545215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1546215976Sjmallett info.enable_mask = 1ull<<31 /* win_wr */; 1547215976Sjmallett info.flags = 0; 1548215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1549215976Sjmallett info.group_index = 0; 1550215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1551215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1552215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1553215976Sjmallett info.func = __cvmx_error_display; 1554215976Sjmallett info.user_info = (long) 1555215976Sjmallett "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n" 1556215976Sjmallett " Read-Address Register took place.\n"; 1557215976Sjmallett fail |= cvmx_error_add(&info); 1558215976Sjmallett 1559215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1560215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1561215976Sjmallett info.status_mask = 1ull<<32 /* ill_wr */; 1562215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1563215976Sjmallett info.enable_mask = 1ull<<32 /* ill_wr */; 1564215976Sjmallett info.flags = 0; 1565215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1566215976Sjmallett info.group_index = 0; 1567215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1568215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1569215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1570215976Sjmallett info.func = __cvmx_error_display; 1571215976Sjmallett info.user_info = (long) 1572215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n" 1573215976Sjmallett " when the mem area is disabled.\n"; 1574215976Sjmallett fail |= cvmx_error_add(&info); 1575215976Sjmallett 1576215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1577215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1578215976Sjmallett info.status_mask = 1ull<<33 /* ill_rd */; 1579215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1580215976Sjmallett info.enable_mask = 1ull<<33 /* ill_rd */; 1581215976Sjmallett info.flags = 0; 1582215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1583215976Sjmallett info.group_index = 0; 1584215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1585215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1586215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1587215976Sjmallett info.func = __cvmx_error_display; 1588215976Sjmallett info.user_info = (long) 1589215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n" 1590215976Sjmallett " when the mem area is disabled.\n"; 1591215976Sjmallett fail |= cvmx_error_add(&info); 1592215976Sjmallett 1593215976Sjmallett /* CVMX_FPA_INT_SUM */ 1594215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1595215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1596215976Sjmallett info.status_mask = 1ull<<0 /* fed0_sbe */; 1597215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1598215976Sjmallett info.enable_mask = 1ull<<0 /* fed0_sbe */; 1599215976Sjmallett info.flags = 0; 1600215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1601215976Sjmallett info.group_index = 0; 1602215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1603215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1604215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1605215976Sjmallett info.func = __cvmx_error_display; 1606215976Sjmallett info.user_info = (long) 1607215976Sjmallett "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n"; 1608215976Sjmallett fail |= cvmx_error_add(&info); 1609215976Sjmallett 1610215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1611215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1612215976Sjmallett info.status_mask = 1ull<<1 /* fed0_dbe */; 1613215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1614215976Sjmallett info.enable_mask = 1ull<<1 /* fed0_dbe */; 1615215976Sjmallett info.flags = 0; 1616215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1617215976Sjmallett info.group_index = 0; 1618215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1619215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1620215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1621215976Sjmallett info.func = __cvmx_error_display; 1622215976Sjmallett info.user_info = (long) 1623215976Sjmallett "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n"; 1624215976Sjmallett fail |= cvmx_error_add(&info); 1625215976Sjmallett 1626215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1627215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1628215976Sjmallett info.status_mask = 1ull<<2 /* fed1_sbe */; 1629215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1630215976Sjmallett info.enable_mask = 1ull<<2 /* fed1_sbe */; 1631215976Sjmallett info.flags = 0; 1632215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1633215976Sjmallett info.group_index = 0; 1634215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1635215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1636215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1637215976Sjmallett info.func = __cvmx_error_display; 1638215976Sjmallett info.user_info = (long) 1639215976Sjmallett "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n"; 1640215976Sjmallett fail |= cvmx_error_add(&info); 1641215976Sjmallett 1642215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1643215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1644215976Sjmallett info.status_mask = 1ull<<3 /* fed1_dbe */; 1645215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1646215976Sjmallett info.enable_mask = 1ull<<3 /* fed1_dbe */; 1647215976Sjmallett info.flags = 0; 1648215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1649215976Sjmallett info.group_index = 0; 1650215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1651215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1652215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1653215976Sjmallett info.func = __cvmx_error_display; 1654215976Sjmallett info.user_info = (long) 1655215976Sjmallett "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n"; 1656215976Sjmallett fail |= cvmx_error_add(&info); 1657215976Sjmallett 1658215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1659215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1660215976Sjmallett info.status_mask = 1ull<<4 /* q0_und */; 1661215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1662215976Sjmallett info.enable_mask = 1ull<<4 /* q0_und */; 1663215976Sjmallett info.flags = 0; 1664215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1665215976Sjmallett info.group_index = 0; 1666215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1667215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1668215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1669215976Sjmallett info.func = __cvmx_error_display; 1670215976Sjmallett info.user_info = (long) 1671215976Sjmallett "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n" 1672215976Sjmallett " negative.\n"; 1673215976Sjmallett fail |= cvmx_error_add(&info); 1674215976Sjmallett 1675215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1676215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1677215976Sjmallett info.status_mask = 1ull<<5 /* q0_coff */; 1678215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1679215976Sjmallett info.enable_mask = 1ull<<5 /* q0_coff */; 1680215976Sjmallett info.flags = 0; 1681215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1682215976Sjmallett info.group_index = 0; 1683215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1684215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1685215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1686215976Sjmallett info.func = __cvmx_error_display; 1687215976Sjmallett info.user_info = (long) 1688215976Sjmallett "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n" 1689215976Sjmallett " the count available is greater than pointers\n" 1690215976Sjmallett " present in the FPA.\n"; 1691215976Sjmallett fail |= cvmx_error_add(&info); 1692215976Sjmallett 1693215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1694215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1695215976Sjmallett info.status_mask = 1ull<<6 /* q0_perr */; 1696215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1697215976Sjmallett info.enable_mask = 1ull<<6 /* q0_perr */; 1698215976Sjmallett info.flags = 0; 1699215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1700215976Sjmallett info.group_index = 0; 1701215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1702215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1703215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1704215976Sjmallett info.func = __cvmx_error_display; 1705215976Sjmallett info.user_info = (long) 1706215976Sjmallett "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n" 1707215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 1708215976Sjmallett fail |= cvmx_error_add(&info); 1709215976Sjmallett 1710215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1711215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1712215976Sjmallett info.status_mask = 1ull<<7 /* q1_und */; 1713215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1714215976Sjmallett info.enable_mask = 1ull<<7 /* q1_und */; 1715215976Sjmallett info.flags = 0; 1716215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1717215976Sjmallett info.group_index = 0; 1718215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1719215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1720215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1721215976Sjmallett info.func = __cvmx_error_display; 1722215976Sjmallett info.user_info = (long) 1723215976Sjmallett "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n" 1724215976Sjmallett " negative.\n"; 1725215976Sjmallett fail |= cvmx_error_add(&info); 1726215976Sjmallett 1727215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1728215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1729215976Sjmallett info.status_mask = 1ull<<8 /* q1_coff */; 1730215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1731215976Sjmallett info.enable_mask = 1ull<<8 /* q1_coff */; 1732215976Sjmallett info.flags = 0; 1733215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1734215976Sjmallett info.group_index = 0; 1735215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1736215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1737215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1738215976Sjmallett info.func = __cvmx_error_display; 1739215976Sjmallett info.user_info = (long) 1740215976Sjmallett "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n" 1741215976Sjmallett " the count available is greater than pointers\n" 1742215976Sjmallett " present in the FPA.\n"; 1743215976Sjmallett fail |= cvmx_error_add(&info); 1744215976Sjmallett 1745215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1746215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1747215976Sjmallett info.status_mask = 1ull<<9 /* q1_perr */; 1748215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1749215976Sjmallett info.enable_mask = 1ull<<9 /* q1_perr */; 1750215976Sjmallett info.flags = 0; 1751215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1752215976Sjmallett info.group_index = 0; 1753215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1754215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1755215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1756215976Sjmallett info.func = __cvmx_error_display; 1757215976Sjmallett info.user_info = (long) 1758215976Sjmallett "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n" 1759215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 1760215976Sjmallett fail |= cvmx_error_add(&info); 1761215976Sjmallett 1762215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1763215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1764215976Sjmallett info.status_mask = 1ull<<10 /* q2_und */; 1765215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1766215976Sjmallett info.enable_mask = 1ull<<10 /* q2_und */; 1767215976Sjmallett info.flags = 0; 1768215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1769215976Sjmallett info.group_index = 0; 1770215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1771215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1772215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1773215976Sjmallett info.func = __cvmx_error_display; 1774215976Sjmallett info.user_info = (long) 1775215976Sjmallett "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n" 1776215976Sjmallett " negative.\n"; 1777215976Sjmallett fail |= cvmx_error_add(&info); 1778215976Sjmallett 1779215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1780215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1781215976Sjmallett info.status_mask = 1ull<<11 /* q2_coff */; 1782215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1783215976Sjmallett info.enable_mask = 1ull<<11 /* q2_coff */; 1784215976Sjmallett info.flags = 0; 1785215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1786215976Sjmallett info.group_index = 0; 1787215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1788215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1789215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1790215976Sjmallett info.func = __cvmx_error_display; 1791215976Sjmallett info.user_info = (long) 1792215976Sjmallett "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n" 1793215976Sjmallett " the count available is greater than than pointers\n" 1794215976Sjmallett " present in the FPA.\n"; 1795215976Sjmallett fail |= cvmx_error_add(&info); 1796215976Sjmallett 1797215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1798215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1799215976Sjmallett info.status_mask = 1ull<<12 /* q2_perr */; 1800215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1801215976Sjmallett info.enable_mask = 1ull<<12 /* q2_perr */; 1802215976Sjmallett info.flags = 0; 1803215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1804215976Sjmallett info.group_index = 0; 1805215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1806215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1807215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1808215976Sjmallett info.func = __cvmx_error_display; 1809215976Sjmallett info.user_info = (long) 1810215976Sjmallett "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n" 1811215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 1812215976Sjmallett fail |= cvmx_error_add(&info); 1813215976Sjmallett 1814215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1815215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1816215976Sjmallett info.status_mask = 1ull<<13 /* q3_und */; 1817215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1818215976Sjmallett info.enable_mask = 1ull<<13 /* q3_und */; 1819215976Sjmallett info.flags = 0; 1820215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1821215976Sjmallett info.group_index = 0; 1822215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1823215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1824215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1825215976Sjmallett info.func = __cvmx_error_display; 1826215976Sjmallett info.user_info = (long) 1827215976Sjmallett "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n" 1828215976Sjmallett " negative.\n"; 1829215976Sjmallett fail |= cvmx_error_add(&info); 1830215976Sjmallett 1831215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1832215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1833215976Sjmallett info.status_mask = 1ull<<14 /* q3_coff */; 1834215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1835215976Sjmallett info.enable_mask = 1ull<<14 /* q3_coff */; 1836215976Sjmallett info.flags = 0; 1837215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1838215976Sjmallett info.group_index = 0; 1839215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1840215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1841215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1842215976Sjmallett info.func = __cvmx_error_display; 1843215976Sjmallett info.user_info = (long) 1844215976Sjmallett "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n" 1845215976Sjmallett " the count available is greater than than pointers\n" 1846215976Sjmallett " present in the FPA.\n"; 1847215976Sjmallett fail |= cvmx_error_add(&info); 1848215976Sjmallett 1849215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1850215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1851215976Sjmallett info.status_mask = 1ull<<15 /* q3_perr */; 1852215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1853215976Sjmallett info.enable_mask = 1ull<<15 /* q3_perr */; 1854215976Sjmallett info.flags = 0; 1855215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1856215976Sjmallett info.group_index = 0; 1857215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1858215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1859215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1860215976Sjmallett info.func = __cvmx_error_display; 1861215976Sjmallett info.user_info = (long) 1862215976Sjmallett "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n" 1863215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 1864215976Sjmallett fail |= cvmx_error_add(&info); 1865215976Sjmallett 1866215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1867215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1868215976Sjmallett info.status_mask = 1ull<<16 /* q4_und */; 1869215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1870215976Sjmallett info.enable_mask = 1ull<<16 /* q4_und */; 1871215976Sjmallett info.flags = 0; 1872215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1873215976Sjmallett info.group_index = 0; 1874215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1875215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1876215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1877215976Sjmallett info.func = __cvmx_error_display; 1878215976Sjmallett info.user_info = (long) 1879215976Sjmallett "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n" 1880215976Sjmallett " negative.\n"; 1881215976Sjmallett fail |= cvmx_error_add(&info); 1882215976Sjmallett 1883215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1884215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1885215976Sjmallett info.status_mask = 1ull<<17 /* q4_coff */; 1886215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1887215976Sjmallett info.enable_mask = 1ull<<17 /* q4_coff */; 1888215976Sjmallett info.flags = 0; 1889215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1890215976Sjmallett info.group_index = 0; 1891215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1892215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1893215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1894215976Sjmallett info.func = __cvmx_error_display; 1895215976Sjmallett info.user_info = (long) 1896215976Sjmallett "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n" 1897215976Sjmallett " the count available is greater than than pointers\n" 1898215976Sjmallett " present in the FPA.\n"; 1899215976Sjmallett fail |= cvmx_error_add(&info); 1900215976Sjmallett 1901215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1902215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1903215976Sjmallett info.status_mask = 1ull<<18 /* q4_perr */; 1904215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1905215976Sjmallett info.enable_mask = 1ull<<18 /* q4_perr */; 1906215976Sjmallett info.flags = 0; 1907215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1908215976Sjmallett info.group_index = 0; 1909215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1910215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1911215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1912215976Sjmallett info.func = __cvmx_error_display; 1913215976Sjmallett info.user_info = (long) 1914215976Sjmallett "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n" 1915215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 1916215976Sjmallett fail |= cvmx_error_add(&info); 1917215976Sjmallett 1918215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1919215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1920215976Sjmallett info.status_mask = 1ull<<19 /* q5_und */; 1921215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1922215976Sjmallett info.enable_mask = 1ull<<19 /* q5_und */; 1923215976Sjmallett info.flags = 0; 1924215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1925215976Sjmallett info.group_index = 0; 1926215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1927215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1928215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1929215976Sjmallett info.func = __cvmx_error_display; 1930215976Sjmallett info.user_info = (long) 1931215976Sjmallett "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n" 1932215976Sjmallett " negative.\n"; 1933215976Sjmallett fail |= cvmx_error_add(&info); 1934215976Sjmallett 1935215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1936215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1937215976Sjmallett info.status_mask = 1ull<<20 /* q5_coff */; 1938215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1939215976Sjmallett info.enable_mask = 1ull<<20 /* q5_coff */; 1940215976Sjmallett info.flags = 0; 1941215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1942215976Sjmallett info.group_index = 0; 1943215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1944215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1945215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1946215976Sjmallett info.func = __cvmx_error_display; 1947215976Sjmallett info.user_info = (long) 1948215976Sjmallett "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n" 1949215976Sjmallett " the count available is greater than than pointers\n" 1950215976Sjmallett " present in the FPA.\n"; 1951215976Sjmallett fail |= cvmx_error_add(&info); 1952215976Sjmallett 1953215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1954215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1955215976Sjmallett info.status_mask = 1ull<<21 /* q5_perr */; 1956215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1957215976Sjmallett info.enable_mask = 1ull<<21 /* q5_perr */; 1958215976Sjmallett info.flags = 0; 1959215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1960215976Sjmallett info.group_index = 0; 1961215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1962215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1963215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1964215976Sjmallett info.func = __cvmx_error_display; 1965215976Sjmallett info.user_info = (long) 1966215976Sjmallett "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n" 1967215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 1968215976Sjmallett fail |= cvmx_error_add(&info); 1969215976Sjmallett 1970215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1971215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1972215976Sjmallett info.status_mask = 1ull<<22 /* q6_und */; 1973215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1974215976Sjmallett info.enable_mask = 1ull<<22 /* q6_und */; 1975215976Sjmallett info.flags = 0; 1976215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1977215976Sjmallett info.group_index = 0; 1978215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1979215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1980215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1981215976Sjmallett info.func = __cvmx_error_display; 1982215976Sjmallett info.user_info = (long) 1983215976Sjmallett "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n" 1984215976Sjmallett " negative.\n"; 1985215976Sjmallett fail |= cvmx_error_add(&info); 1986215976Sjmallett 1987215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1988215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 1989215976Sjmallett info.status_mask = 1ull<<23 /* q6_coff */; 1990215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 1991215976Sjmallett info.enable_mask = 1ull<<23 /* q6_coff */; 1992215976Sjmallett info.flags = 0; 1993215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1994215976Sjmallett info.group_index = 0; 1995215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1996215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1997215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 1998215976Sjmallett info.func = __cvmx_error_display; 1999215976Sjmallett info.user_info = (long) 2000215976Sjmallett "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n" 2001215976Sjmallett " the count available is greater than than pointers\n" 2002215976Sjmallett " present in the FPA.\n"; 2003215976Sjmallett fail |= cvmx_error_add(&info); 2004215976Sjmallett 2005215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2006215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2007215976Sjmallett info.status_mask = 1ull<<24 /* q6_perr */; 2008215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2009215976Sjmallett info.enable_mask = 1ull<<24 /* q6_perr */; 2010215976Sjmallett info.flags = 0; 2011215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2012215976Sjmallett info.group_index = 0; 2013215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2014215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2015215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2016215976Sjmallett info.func = __cvmx_error_display; 2017215976Sjmallett info.user_info = (long) 2018215976Sjmallett "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n" 2019215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2020215976Sjmallett fail |= cvmx_error_add(&info); 2021215976Sjmallett 2022215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2023215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2024215976Sjmallett info.status_mask = 1ull<<25 /* q7_und */; 2025215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2026215976Sjmallett info.enable_mask = 1ull<<25 /* q7_und */; 2027215976Sjmallett info.flags = 0; 2028215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2029215976Sjmallett info.group_index = 0; 2030215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2031215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2032215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2033215976Sjmallett info.func = __cvmx_error_display; 2034215976Sjmallett info.user_info = (long) 2035215976Sjmallett "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n" 2036215976Sjmallett " negative.\n"; 2037215976Sjmallett fail |= cvmx_error_add(&info); 2038215976Sjmallett 2039215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2040215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2041215976Sjmallett info.status_mask = 1ull<<26 /* q7_coff */; 2042215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2043215976Sjmallett info.enable_mask = 1ull<<26 /* q7_coff */; 2044215976Sjmallett info.flags = 0; 2045215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2046215976Sjmallett info.group_index = 0; 2047215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2048215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2049215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2050215976Sjmallett info.func = __cvmx_error_display; 2051215976Sjmallett info.user_info = (long) 2052215976Sjmallett "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n" 2053215976Sjmallett " the count available is greater than than pointers\n" 2054215976Sjmallett " present in the FPA.\n"; 2055215976Sjmallett fail |= cvmx_error_add(&info); 2056215976Sjmallett 2057215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2058215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2059215976Sjmallett info.status_mask = 1ull<<27 /* q7_perr */; 2060215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2061215976Sjmallett info.enable_mask = 1ull<<27 /* q7_perr */; 2062215976Sjmallett info.flags = 0; 2063215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2064215976Sjmallett info.group_index = 0; 2065215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2066215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2067215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2068215976Sjmallett info.func = __cvmx_error_display; 2069215976Sjmallett info.user_info = (long) 2070215976Sjmallett "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n" 2071215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2072215976Sjmallett fail |= cvmx_error_add(&info); 2073215976Sjmallett 2074215976Sjmallett /* CVMX_MIO_BOOT_ERR */ 2075215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2076215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 2077215976Sjmallett info.status_mask = 1ull<<0 /* adr_err */; 2078215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 2079215976Sjmallett info.enable_mask = 1ull<<0 /* adr_int */; 2080215976Sjmallett info.flags = 0; 2081215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2082215976Sjmallett info.group_index = 0; 2083215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2084215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2085215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 2086215976Sjmallett info.func = __cvmx_error_display; 2087215976Sjmallett info.user_info = (long) 2088215976Sjmallett "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n"; 2089215976Sjmallett fail |= cvmx_error_add(&info); 2090215976Sjmallett 2091215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2092215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 2093215976Sjmallett info.status_mask = 1ull<<1 /* wait_err */; 2094215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 2095215976Sjmallett info.enable_mask = 1ull<<1 /* wait_int */; 2096215976Sjmallett info.flags = 0; 2097215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2098215976Sjmallett info.group_index = 0; 2099215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2100215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2101215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 2102215976Sjmallett info.func = __cvmx_error_display; 2103215976Sjmallett info.user_info = (long) 2104215976Sjmallett "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n"; 2105215976Sjmallett fail |= cvmx_error_add(&info); 2106215976Sjmallett 2107215976Sjmallett /* CVMX_IPD_INT_SUM */ 2108215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2109215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2110215976Sjmallett info.status_mask = 1ull<<0 /* prc_par0 */; 2111215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2112215976Sjmallett info.enable_mask = 1ull<<0 /* prc_par0 */; 2113215976Sjmallett info.flags = 0; 2114215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2115215976Sjmallett info.group_index = 0; 2116215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2117215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2118215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2119215976Sjmallett info.func = __cvmx_error_display; 2120215976Sjmallett info.user_info = (long) 2121215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n" 2122215976Sjmallett " [31:0] of the PBM memory.\n"; 2123215976Sjmallett fail |= cvmx_error_add(&info); 2124215976Sjmallett 2125215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2126215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2127215976Sjmallett info.status_mask = 1ull<<1 /* prc_par1 */; 2128215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2129215976Sjmallett info.enable_mask = 1ull<<1 /* prc_par1 */; 2130215976Sjmallett info.flags = 0; 2131215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2132215976Sjmallett info.group_index = 0; 2133215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2134215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2135215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2136215976Sjmallett info.func = __cvmx_error_display; 2137215976Sjmallett info.user_info = (long) 2138215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n" 2139215976Sjmallett " [63:32] of the PBM memory.\n"; 2140215976Sjmallett fail |= cvmx_error_add(&info); 2141215976Sjmallett 2142215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2143215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2144215976Sjmallett info.status_mask = 1ull<<2 /* prc_par2 */; 2145215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2146215976Sjmallett info.enable_mask = 1ull<<2 /* prc_par2 */; 2147215976Sjmallett info.flags = 0; 2148215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2149215976Sjmallett info.group_index = 0; 2150215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2151215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2152215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2153215976Sjmallett info.func = __cvmx_error_display; 2154215976Sjmallett info.user_info = (long) 2155215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n" 2156215976Sjmallett " [95:64] of the PBM memory.\n"; 2157215976Sjmallett fail |= cvmx_error_add(&info); 2158215976Sjmallett 2159215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2160215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2161215976Sjmallett info.status_mask = 1ull<<3 /* prc_par3 */; 2162215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2163215976Sjmallett info.enable_mask = 1ull<<3 /* prc_par3 */; 2164215976Sjmallett info.flags = 0; 2165215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2166215976Sjmallett info.group_index = 0; 2167215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2168215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2169215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2170215976Sjmallett info.func = __cvmx_error_display; 2171215976Sjmallett info.user_info = (long) 2172215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n" 2173215976Sjmallett " [127:96] of the PBM memory.\n"; 2174215976Sjmallett fail |= cvmx_error_add(&info); 2175215976Sjmallett 2176215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2177215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2178215976Sjmallett info.status_mask = 1ull<<4 /* bp_sub */; 2179215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2180215976Sjmallett info.enable_mask = 1ull<<4 /* bp_sub */; 2181215976Sjmallett info.flags = 0; 2182215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2183215976Sjmallett info.group_index = 0; 2184215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2185215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2186215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2187215976Sjmallett info.func = __cvmx_error_display; 2188215976Sjmallett info.user_info = (long) 2189215976Sjmallett "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n" 2190215976Sjmallett " supplied illegal value.\n"; 2191215976Sjmallett fail |= cvmx_error_add(&info); 2192215976Sjmallett 2193215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2194215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2195215976Sjmallett info.status_mask = 1ull<<5 /* dc_ovr */; 2196215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2197215976Sjmallett info.enable_mask = 1ull<<5 /* dc_ovr */; 2198215976Sjmallett info.flags = 0; 2199215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2200215976Sjmallett info.group_index = 0; 2201215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2202215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2203215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2204215976Sjmallett info.func = __cvmx_error_display; 2205215976Sjmallett info.user_info = (long) 2206215976Sjmallett "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n" 2207215976Sjmallett " This is a PASS-3 Field.\n"; 2208215976Sjmallett fail |= cvmx_error_add(&info); 2209215976Sjmallett 2210215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2211215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2212215976Sjmallett info.status_mask = 1ull<<6 /* cc_ovr */; 2213215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2214215976Sjmallett info.enable_mask = 1ull<<6 /* cc_ovr */; 2215215976Sjmallett info.flags = 0; 2216215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2217215976Sjmallett info.group_index = 0; 2218215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2219215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2220215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2221215976Sjmallett info.func = __cvmx_error_display; 2222215976Sjmallett info.user_info = (long) 2223215976Sjmallett "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n" 2224215976Sjmallett " This is a PASS-3 Field.\n"; 2225215976Sjmallett fail |= cvmx_error_add(&info); 2226215976Sjmallett 2227215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2228215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2229215976Sjmallett info.status_mask = 1ull<<7 /* c_coll */; 2230215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2231215976Sjmallett info.enable_mask = 1ull<<7 /* c_coll */; 2232215976Sjmallett info.flags = 0; 2233215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2234215976Sjmallett info.group_index = 0; 2235215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2236215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2237215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2238215976Sjmallett info.func = __cvmx_error_display; 2239215976Sjmallett info.user_info = (long) 2240215976Sjmallett "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n" 2241215976Sjmallett " collides.\n" 2242215976Sjmallett " This is a PASS-3 Field.\n"; 2243215976Sjmallett fail |= cvmx_error_add(&info); 2244215976Sjmallett 2245215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2246215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2247215976Sjmallett info.status_mask = 1ull<<8 /* d_coll */; 2248215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2249215976Sjmallett info.enable_mask = 1ull<<8 /* d_coll */; 2250215976Sjmallett info.flags = 0; 2251215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2252215976Sjmallett info.group_index = 0; 2253215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2254215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2255215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2256215976Sjmallett info.func = __cvmx_error_display; 2257215976Sjmallett info.user_info = (long) 2258215976Sjmallett "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n" 2259215976Sjmallett " collides.\n" 2260215976Sjmallett " This is a PASS-3 Field.\n"; 2261215976Sjmallett fail |= cvmx_error_add(&info); 2262215976Sjmallett 2263215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2264215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2265215976Sjmallett info.status_mask = 1ull<<9 /* bc_ovr */; 2266215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2267215976Sjmallett info.enable_mask = 1ull<<9 /* bc_ovr */; 2268215976Sjmallett info.flags = 0; 2269215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2270215976Sjmallett info.group_index = 0; 2271215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2272215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2273215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2274215976Sjmallett info.func = __cvmx_error_display; 2275215976Sjmallett info.user_info = (long) 2276215976Sjmallett "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n" 2277215976Sjmallett " This is a PASS-3 Field.\n"; 2278215976Sjmallett fail |= cvmx_error_add(&info); 2279215976Sjmallett 2280215976Sjmallett /* CVMX_POW_ECC_ERR */ 2281215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2282215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2283215976Sjmallett info.status_mask = 1ull<<0 /* sbe */; 2284215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2285215976Sjmallett info.enable_mask = 1ull<<2 /* sbe_ie */; 2286215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 2287215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2288215976Sjmallett info.group_index = 0; 2289215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2290215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2291215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2292215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_sbe; 2293215976Sjmallett info.user_info = (long) 2294215976Sjmallett "ERROR POW_ECC_ERR[SBE]: Single bit error\n"; 2295215976Sjmallett fail |= cvmx_error_add(&info); 2296215976Sjmallett 2297215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2298215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2299215976Sjmallett info.status_mask = 1ull<<1 /* dbe */; 2300215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2301215976Sjmallett info.enable_mask = 1ull<<3 /* dbe_ie */; 2302215976Sjmallett info.flags = 0; 2303215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2304215976Sjmallett info.group_index = 0; 2305215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2306215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2307215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2308215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_dbe; 2309215976Sjmallett info.user_info = (long) 2310215976Sjmallett "ERROR POW_ECC_ERR[DBE]: Double bit error\n"; 2311215976Sjmallett fail |= cvmx_error_add(&info); 2312215976Sjmallett 2313215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2314215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2315215976Sjmallett info.status_mask = 1ull<<12 /* rpe */; 2316215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2317215976Sjmallett info.enable_mask = 1ull<<13 /* rpe_ie */; 2318215976Sjmallett info.flags = 0; 2319215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2320215976Sjmallett info.group_index = 0; 2321215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2322215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2323215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2324215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_rpe; 2325215976Sjmallett info.user_info = (long) 2326215976Sjmallett "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n"; 2327215976Sjmallett fail |= cvmx_error_add(&info); 2328215976Sjmallett 2329215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2330215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2331215976Sjmallett info.status_mask = 0x1fffull<<16 /* iop */; 2332215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2333215976Sjmallett info.enable_mask = 0x1fffull<<32 /* iop_ie */; 2334215976Sjmallett info.flags = 0; 2335215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2336215976Sjmallett info.group_index = 0; 2337215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2338215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2339215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2340215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_iop; 2341215976Sjmallett info.user_info = (long) 2342215976Sjmallett "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n"; 2343215976Sjmallett fail |= cvmx_error_add(&info); 2344215976Sjmallett 2345215976Sjmallett /* CVMX_ASXX_INT_REG(0) */ 2346215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2347215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(0); 2348215976Sjmallett info.status_mask = 0x7ull<<0 /* ovrflw */; 2349215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(0); 2350215976Sjmallett info.enable_mask = 0x7ull<<0 /* ovrflw */; 2351215976Sjmallett info.flags = 0; 2352215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2353215976Sjmallett info.group_index = 0; 2354215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2355215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2356215976Sjmallett info.parent.status_mask = 1ull<<22 /* asx0 */; 2357215976Sjmallett info.func = __cvmx_error_display; 2358215976Sjmallett info.user_info = (long) 2359215976Sjmallett "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n"; 2360215976Sjmallett fail |= cvmx_error_add(&info); 2361215976Sjmallett 2362215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2363215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(0); 2364215976Sjmallett info.status_mask = 0x7ull<<4 /* txpop */; 2365215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(0); 2366215976Sjmallett info.enable_mask = 0x7ull<<4 /* txpop */; 2367215976Sjmallett info.flags = 0; 2368215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2369215976Sjmallett info.group_index = 0; 2370215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2371215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2372215976Sjmallett info.parent.status_mask = 1ull<<22 /* asx0 */; 2373215976Sjmallett info.func = __cvmx_error_display; 2374215976Sjmallett info.user_info = (long) 2375215976Sjmallett "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n"; 2376215976Sjmallett fail |= cvmx_error_add(&info); 2377215976Sjmallett 2378215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2379215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(0); 2380215976Sjmallett info.status_mask = 0x7ull<<8 /* txpsh */; 2381215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(0); 2382215976Sjmallett info.enable_mask = 0x7ull<<8 /* txpsh */; 2383215976Sjmallett info.flags = 0; 2384215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2385215976Sjmallett info.group_index = 0; 2386215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2387215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2388215976Sjmallett info.parent.status_mask = 1ull<<22 /* asx0 */; 2389215976Sjmallett info.func = __cvmx_error_display; 2390215976Sjmallett info.user_info = (long) 2391215976Sjmallett "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n"; 2392215976Sjmallett fail |= cvmx_error_add(&info); 2393215976Sjmallett 2394215976Sjmallett /* CVMX_PKO_REG_ERROR */ 2395215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2396215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 2397215976Sjmallett info.status_mask = 1ull<<0 /* parity */; 2398215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 2399215976Sjmallett info.enable_mask = 1ull<<0 /* parity */; 2400215976Sjmallett info.flags = 0; 2401215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2402215976Sjmallett info.group_index = 0; 2403215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2404215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2405215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 2406215976Sjmallett info.func = __cvmx_error_display; 2407215976Sjmallett info.user_info = (long) 2408215976Sjmallett "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n"; 2409215976Sjmallett fail |= cvmx_error_add(&info); 2410215976Sjmallett 2411215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2412215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 2413215976Sjmallett info.status_mask = 1ull<<1 /* doorbell */; 2414215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 2415215976Sjmallett info.enable_mask = 1ull<<1 /* doorbell */; 2416215976Sjmallett info.flags = 0; 2417215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2418215976Sjmallett info.group_index = 0; 2419215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2420215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2421215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 2422215976Sjmallett info.func = __cvmx_error_display; 2423215976Sjmallett info.user_info = (long) 2424215976Sjmallett "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 2425215976Sjmallett fail |= cvmx_error_add(&info); 2426215976Sjmallett 2427215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2428215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 2429215976Sjmallett info.status_mask = 1ull<<2 /* currzero */; 2430215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 2431215976Sjmallett info.enable_mask = 1ull<<2 /* currzero */; 2432215976Sjmallett info.flags = 0; 2433215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2434215976Sjmallett info.group_index = 0; 2435215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2436215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2437215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 2438215976Sjmallett info.func = __cvmx_error_display; 2439215976Sjmallett info.user_info = (long) 2440215976Sjmallett "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n"; 2441215976Sjmallett fail |= cvmx_error_add(&info); 2442215976Sjmallett 2443215976Sjmallett /* CVMX_TIM_REG_ERROR */ 2444215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2445215976Sjmallett info.status_addr = CVMX_TIM_REG_ERROR; 2446215976Sjmallett info.status_mask = 0xffffull<<0 /* mask */; 2447215976Sjmallett info.enable_addr = CVMX_TIM_REG_INT_MASK; 2448215976Sjmallett info.enable_mask = 0xffffull<<0 /* mask */; 2449215976Sjmallett info.flags = 0; 2450215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2451215976Sjmallett info.group_index = 0; 2452215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2453215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2454215976Sjmallett info.parent.status_mask = 1ull<<11 /* tim */; 2455215976Sjmallett info.func = __cvmx_error_display; 2456215976Sjmallett info.user_info = (long) 2457215976Sjmallett "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n"; 2458215976Sjmallett fail |= cvmx_error_add(&info); 2459215976Sjmallett 2460215976Sjmallett /* CVMX_PIP_INT_REG */ 2461215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2462215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2463215976Sjmallett info.status_mask = 1ull<<3 /* prtnxa */; 2464215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2465215976Sjmallett info.enable_mask = 1ull<<3 /* prtnxa */; 2466215976Sjmallett info.flags = 0; 2467215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2468215976Sjmallett info.group_index = 0; 2469215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2470215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2471215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2472215976Sjmallett info.func = __cvmx_error_display; 2473215976Sjmallett info.user_info = (long) 2474215976Sjmallett "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n"; 2475215976Sjmallett fail |= cvmx_error_add(&info); 2476215976Sjmallett 2477215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2478215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2479215976Sjmallett info.status_mask = 1ull<<4 /* badtag */; 2480215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2481215976Sjmallett info.enable_mask = 1ull<<4 /* badtag */; 2482215976Sjmallett info.flags = 0; 2483215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2484215976Sjmallett info.group_index = 0; 2485215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2486215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2487215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2488215976Sjmallett info.func = __cvmx_error_display; 2489215976Sjmallett info.user_info = (long) 2490215976Sjmallett "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n"; 2491215976Sjmallett fail |= cvmx_error_add(&info); 2492215976Sjmallett 2493215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2494215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2495215976Sjmallett info.status_mask = 1ull<<5 /* skprunt */; 2496215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2497215976Sjmallett info.enable_mask = 1ull<<5 /* skprunt */; 2498215976Sjmallett info.flags = 0; 2499215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2500215976Sjmallett info.group_index = 0; 2501215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2502215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2503215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2504215976Sjmallett info.func = __cvmx_error_display; 2505215976Sjmallett info.user_info = (long) 2506215976Sjmallett "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n" 2507215976Sjmallett " This interrupt can occur with received PARTIAL\n" 2508215976Sjmallett " packets that are truncated to SKIP bytes or\n" 2509215976Sjmallett " smaller.\n"; 2510215976Sjmallett fail |= cvmx_error_add(&info); 2511215976Sjmallett 2512215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2513215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2514215976Sjmallett info.status_mask = 1ull<<6 /* todoovr */; 2515215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2516215976Sjmallett info.enable_mask = 1ull<<6 /* todoovr */; 2517215976Sjmallett info.flags = 0; 2518215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2519215976Sjmallett info.group_index = 0; 2520215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2521215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2522215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2523215976Sjmallett info.func = __cvmx_error_display; 2524215976Sjmallett info.user_info = (long) 2525215976Sjmallett "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n"; 2526215976Sjmallett fail |= cvmx_error_add(&info); 2527215976Sjmallett 2528215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2529215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2530215976Sjmallett info.status_mask = 1ull<<7 /* feperr */; 2531215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2532215976Sjmallett info.enable_mask = 1ull<<7 /* feperr */; 2533215976Sjmallett info.flags = 0; 2534215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2535215976Sjmallett info.group_index = 0; 2536215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2537215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2538215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2539215976Sjmallett info.func = __cvmx_error_display; 2540215976Sjmallett info.user_info = (long) 2541215976Sjmallett "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n"; 2542215976Sjmallett fail |= cvmx_error_add(&info); 2543215976Sjmallett 2544215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2545215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2546215976Sjmallett info.status_mask = 1ull<<8 /* beperr */; 2547215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2548215976Sjmallett info.enable_mask = 1ull<<8 /* beperr */; 2549215976Sjmallett info.flags = 0; 2550215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2551215976Sjmallett info.group_index = 0; 2552215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2553215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2554215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2555215976Sjmallett info.func = __cvmx_error_display; 2556215976Sjmallett info.user_info = (long) 2557215976Sjmallett "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n"; 2558215976Sjmallett fail |= cvmx_error_add(&info); 2559215976Sjmallett 2560215976Sjmallett /* CVMX_GMXX_BAD_REG(0) */ 2561215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2562215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 2563215976Sjmallett info.status_mask = 0x7ull<<2 /* out_ovr */; 2564215976Sjmallett info.enable_addr = 0; 2565215976Sjmallett info.enable_mask = 0; 2566215976Sjmallett info.flags = 0; 2567215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2568215976Sjmallett info.group_index = 0; 2569215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2570215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2571215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2572215976Sjmallett info.func = __cvmx_error_display; 2573215976Sjmallett info.user_info = (long) 2574215976Sjmallett "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 2575215976Sjmallett fail |= cvmx_error_add(&info); 2576215976Sjmallett 2577215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2578215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 2579215976Sjmallett info.status_mask = 0x7ull<<22 /* loststat */; 2580215976Sjmallett info.enable_addr = 0; 2581215976Sjmallett info.enable_mask = 0; 2582215976Sjmallett info.flags = 0; 2583215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2584215976Sjmallett info.group_index = 0; 2585215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2586215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2587215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2588215976Sjmallett info.func = __cvmx_error_display; 2589215976Sjmallett info.user_info = (long) 2590215976Sjmallett "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n" 2591215976Sjmallett " TX Stats are corrupted\n"; 2592215976Sjmallett fail |= cvmx_error_add(&info); 2593215976Sjmallett 2594215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2595215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 2596215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 2597215976Sjmallett info.enable_addr = 0; 2598215976Sjmallett info.enable_mask = 0; 2599215976Sjmallett info.flags = 0; 2600215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2601215976Sjmallett info.group_index = 0; 2602215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2603215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2604215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2605215976Sjmallett info.func = __cvmx_error_display; 2606215976Sjmallett info.user_info = (long) 2607215976Sjmallett "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"; 2608215976Sjmallett fail |= cvmx_error_add(&info); 2609215976Sjmallett 2610215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2611215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 2612215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 2613215976Sjmallett info.enable_addr = 0; 2614215976Sjmallett info.enable_mask = 0; 2615215976Sjmallett info.flags = 0; 2616215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2617215976Sjmallett info.group_index = 0; 2618215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2619215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2620215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2621215976Sjmallett info.func = __cvmx_error_display; 2622215976Sjmallett info.user_info = (long) 2623215976Sjmallett "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 2624215976Sjmallett fail |= cvmx_error_add(&info); 2625215976Sjmallett 2626215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,0) */ 2627215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2628215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 2629215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2630215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 2631215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2632215976Sjmallett info.flags = 0; 2633215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2634215976Sjmallett info.group_index = 0; 2635215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2636215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2637215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2638215976Sjmallett info.func = __cvmx_error_display; 2639215976Sjmallett info.user_info = (long) 2640215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n"; 2641215976Sjmallett fail |= cvmx_error_add(&info); 2642215976Sjmallett 2643215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2644215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 2645215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 2646215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 2647215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 2648215976Sjmallett info.flags = 0; 2649215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2650215976Sjmallett info.group_index = 0; 2651215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2652215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2653215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2654215976Sjmallett info.func = __cvmx_error_display; 2655215976Sjmallett info.user_info = (long) 2656215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n"; 2657215976Sjmallett fail |= cvmx_error_add(&info); 2658215976Sjmallett 2659215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2660215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 2661215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2662215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 2663215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2664215976Sjmallett info.flags = 0; 2665215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2666215976Sjmallett info.group_index = 0; 2667215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2668215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2669215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2670215976Sjmallett info.func = __cvmx_error_display; 2671215976Sjmallett info.user_info = (long) 2672215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n"; 2673215976Sjmallett fail |= cvmx_error_add(&info); 2674215976Sjmallett 2675215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2676215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 2677215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 2678215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 2679215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 2680215976Sjmallett info.flags = 0; 2681215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2682215976Sjmallett info.group_index = 0; 2683215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2684215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2685215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2686215976Sjmallett info.func = __cvmx_error_display; 2687215976Sjmallett info.user_info = (long) 2688215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 2689215976Sjmallett fail |= cvmx_error_add(&info); 2690215976Sjmallett 2691215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2692215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 2693215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2694215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 2695215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2696215976Sjmallett info.flags = 0; 2697215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2698215976Sjmallett info.group_index = 0; 2699215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2700215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2701215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2702215976Sjmallett info.func = __cvmx_error_display; 2703215976Sjmallett info.user_info = (long) 2704215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n" 2705215976Sjmallett " This interrupt should never assert\n"; 2706215976Sjmallett fail |= cvmx_error_add(&info); 2707215976Sjmallett 2708215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,0) */ 2709215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2710215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 2711215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2712215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 2713215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2714215976Sjmallett info.flags = 0; 2715215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2716215976Sjmallett info.group_index = 1; 2717215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2718215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2719215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2720215976Sjmallett info.func = __cvmx_error_display; 2721215976Sjmallett info.user_info = (long) 2722215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n"; 2723215976Sjmallett fail |= cvmx_error_add(&info); 2724215976Sjmallett 2725215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2726215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 2727215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 2728215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 2729215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 2730215976Sjmallett info.flags = 0; 2731215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2732215976Sjmallett info.group_index = 1; 2733215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2734215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2735215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2736215976Sjmallett info.func = __cvmx_error_display; 2737215976Sjmallett info.user_info = (long) 2738215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n"; 2739215976Sjmallett fail |= cvmx_error_add(&info); 2740215976Sjmallett 2741215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2742215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 2743215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2744215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 2745215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2746215976Sjmallett info.flags = 0; 2747215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2748215976Sjmallett info.group_index = 1; 2749215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2750215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2751215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2752215976Sjmallett info.func = __cvmx_error_display; 2753215976Sjmallett info.user_info = (long) 2754215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n"; 2755215976Sjmallett fail |= cvmx_error_add(&info); 2756215976Sjmallett 2757215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2758215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 2759215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 2760215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 2761215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 2762215976Sjmallett info.flags = 0; 2763215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2764215976Sjmallett info.group_index = 1; 2765215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2766215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2767215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2768215976Sjmallett info.func = __cvmx_error_display; 2769215976Sjmallett info.user_info = (long) 2770215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 2771215976Sjmallett fail |= cvmx_error_add(&info); 2772215976Sjmallett 2773215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2774215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 2775215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2776215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 2777215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2778215976Sjmallett info.flags = 0; 2779215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2780215976Sjmallett info.group_index = 1; 2781215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2782215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2783215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2784215976Sjmallett info.func = __cvmx_error_display; 2785215976Sjmallett info.user_info = (long) 2786215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n" 2787215976Sjmallett " This interrupt should never assert\n"; 2788215976Sjmallett fail |= cvmx_error_add(&info); 2789215976Sjmallett 2790215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,0) */ 2791215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2792215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2793215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 2794215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2795215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 2796215976Sjmallett info.flags = 0; 2797215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2798215976Sjmallett info.group_index = 2; 2799215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2800215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2801215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2802215976Sjmallett info.func = __cvmx_error_display; 2803215976Sjmallett info.user_info = (long) 2804215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n"; 2805215976Sjmallett fail |= cvmx_error_add(&info); 2806215976Sjmallett 2807215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2808215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2809215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 2810215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2811215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 2812215976Sjmallett info.flags = 0; 2813215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2814215976Sjmallett info.group_index = 2; 2815215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2816215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2817215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2818215976Sjmallett info.func = __cvmx_error_display; 2819215976Sjmallett info.user_info = (long) 2820215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n"; 2821215976Sjmallett fail |= cvmx_error_add(&info); 2822215976Sjmallett 2823215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2824215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2825215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 2826215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2827215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 2828215976Sjmallett info.flags = 0; 2829215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2830215976Sjmallett info.group_index = 2; 2831215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2832215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2833215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2834215976Sjmallett info.func = __cvmx_error_display; 2835215976Sjmallett info.user_info = (long) 2836215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n"; 2837215976Sjmallett fail |= cvmx_error_add(&info); 2838215976Sjmallett 2839215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2840215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2841215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 2842215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2843215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 2844215976Sjmallett info.flags = 0; 2845215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2846215976Sjmallett info.group_index = 2; 2847215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2848215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2849215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2850215976Sjmallett info.func = __cvmx_error_display; 2851215976Sjmallett info.user_info = (long) 2852215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 2853215976Sjmallett fail |= cvmx_error_add(&info); 2854215976Sjmallett 2855215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2856215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 2857215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 2858215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 2859215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 2860215976Sjmallett info.flags = 0; 2861215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2862215976Sjmallett info.group_index = 2; 2863215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2864215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2865215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2866215976Sjmallett info.func = __cvmx_error_display; 2867215976Sjmallett info.user_info = (long) 2868215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n" 2869215976Sjmallett " This interrupt should never assert\n"; 2870215976Sjmallett fail |= cvmx_error_add(&info); 2871215976Sjmallett 2872215976Sjmallett /* CVMX_GMXX_TX_INT_REG(0) */ 2873215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2874215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 2875215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 2876215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 2877215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 2878215976Sjmallett info.flags = 0; 2879215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2880215976Sjmallett info.group_index = 0; 2881215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2882215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2883215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2884215976Sjmallett info.func = __cvmx_error_display; 2885215976Sjmallett info.user_info = (long) 2886215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 2887215976Sjmallett fail |= cvmx_error_add(&info); 2888215976Sjmallett 2889215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2890215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 2891215976Sjmallett info.status_mask = 0x7ull<<2 /* undflw */; 2892215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 2893215976Sjmallett info.enable_mask = 0x7ull<<2 /* undflw */; 2894215976Sjmallett info.flags = 0; 2895215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2896215976Sjmallett info.group_index = 0; 2897215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2898215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2899215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2900215976Sjmallett info.func = __cvmx_error_display; 2901215976Sjmallett info.user_info = (long) 2902215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n"; 2903215976Sjmallett fail |= cvmx_error_add(&info); 2904215976Sjmallett 2905215976Sjmallett /* CVMX_LMCX_MEM_CFG0(0) */ 2906215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2907215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 2908215976Sjmallett info.status_mask = 0xfull<<21 /* sec_err */; 2909215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 2910215976Sjmallett info.enable_mask = 1ull<<19 /* intr_sec_ena */; 2911215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 2912215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 2913215976Sjmallett info.group_index = 0; 2914215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2915215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2916215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc */; 2917215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err; 2918215976Sjmallett info.user_info = (long) 2919215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n" 2920215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 2921215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 2922215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 2923215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 2924215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 2925215976Sjmallett " In 16b mode, ecc is calculated on 8 cycle worth of data\n" 2926215976Sjmallett " [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n" 2927215976Sjmallett " DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n" 2928215976Sjmallett " [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n" 2929215976Sjmallett " DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n" 2930215976Sjmallett " [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n" 2931215976Sjmallett " DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n" 2932215976Sjmallett " [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n" 2933215976Sjmallett " DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n" 2934215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 2935215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 2936215976Sjmallett fail |= cvmx_error_add(&info); 2937215976Sjmallett 2938215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2939215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 2940215976Sjmallett info.status_mask = 0xfull<<25 /* ded_err */; 2941215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 2942215976Sjmallett info.enable_mask = 1ull<<20 /* intr_ded_ena */; 2943215976Sjmallett info.flags = 0; 2944215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 2945215976Sjmallett info.group_index = 0; 2946215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2947215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2948215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc */; 2949215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err; 2950215976Sjmallett info.user_info = (long) 2951215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n" 2952215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 2953215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 2954215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 2955215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 2956215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 2957215976Sjmallett " In 16b mode, ecc is calculated on 8 cycle worth of data\n" 2958215976Sjmallett " [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n" 2959215976Sjmallett " DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n" 2960215976Sjmallett " [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n" 2961215976Sjmallett " DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n" 2962215976Sjmallett " [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n" 2963215976Sjmallett " DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n" 2964215976Sjmallett " [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n" 2965215976Sjmallett " DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n" 2966215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 2967215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 2968215976Sjmallett fail |= cvmx_error_add(&info); 2969215976Sjmallett 2970215976Sjmallett /* CVMX_IOB_INT_SUM */ 2971215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2972215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 2973215976Sjmallett info.status_mask = 1ull<<0 /* np_sop */; 2974215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 2975215976Sjmallett info.enable_mask = 1ull<<0 /* np_sop */; 2976215976Sjmallett info.flags = 0; 2977215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2978215976Sjmallett info.group_index = 0; 2979215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2980215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2981215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 2982215976Sjmallett info.func = __cvmx_error_display; 2983215976Sjmallett info.user_info = (long) 2984215976Sjmallett "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n" 2985215976Sjmallett " port for a non-passthrough packet.\n" 2986215976Sjmallett " The first detected error associated with bits [3:0]\n" 2987215976Sjmallett " of this register will only be set here. A new bit\n" 2988215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 2989215976Sjmallett fail |= cvmx_error_add(&info); 2990215976Sjmallett 2991215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2992215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 2993215976Sjmallett info.status_mask = 1ull<<1 /* np_eop */; 2994215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 2995215976Sjmallett info.enable_mask = 1ull<<1 /* np_eop */; 2996215976Sjmallett info.flags = 0; 2997215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2998215976Sjmallett info.group_index = 0; 2999215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3000215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3001215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 3002215976Sjmallett info.func = __cvmx_error_display; 3003215976Sjmallett info.user_info = (long) 3004215976Sjmallett "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n" 3005215976Sjmallett " port for a non-passthrough packet.\n" 3006215976Sjmallett " The first detected error associated with bits [3:0]\n" 3007215976Sjmallett " of this register will only be set here. A new bit\n" 3008215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 3009215976Sjmallett fail |= cvmx_error_add(&info); 3010215976Sjmallett 3011215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3012215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 3013215976Sjmallett info.status_mask = 1ull<<2 /* p_sop */; 3014215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 3015215976Sjmallett info.enable_mask = 1ull<<2 /* p_sop */; 3016215976Sjmallett info.flags = 0; 3017215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3018215976Sjmallett info.group_index = 0; 3019215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3020215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3021215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 3022215976Sjmallett info.func = __cvmx_error_display; 3023215976Sjmallett info.user_info = (long) 3024215976Sjmallett "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n" 3025215976Sjmallett " port for a passthrough packet.\n" 3026215976Sjmallett " The first detected error associated with bits [3:0]\n" 3027215976Sjmallett " of this register will only be set here. A new bit\n" 3028215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 3029215976Sjmallett fail |= cvmx_error_add(&info); 3030215976Sjmallett 3031215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3032215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 3033215976Sjmallett info.status_mask = 1ull<<3 /* p_eop */; 3034215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 3035215976Sjmallett info.enable_mask = 1ull<<3 /* p_eop */; 3036215976Sjmallett info.flags = 0; 3037215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3038215976Sjmallett info.group_index = 0; 3039215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3040215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3041215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 3042215976Sjmallett info.func = __cvmx_error_display; 3043215976Sjmallett info.user_info = (long) 3044215976Sjmallett "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n" 3045215976Sjmallett " port for a passthrough packet.\n" 3046215976Sjmallett " The first detected error associated with bits [3:0]\n" 3047215976Sjmallett " of this register will only be set here. A new bit\n" 3048215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 3049215976Sjmallett fail |= cvmx_error_add(&info); 3050215976Sjmallett 3051215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3052215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 3053215976Sjmallett info.status_mask = 1ull<<4 /* np_dat */; 3054215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 3055215976Sjmallett info.enable_mask = 1ull<<4 /* np_dat */; 3056215976Sjmallett info.flags = 0; 3057215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3058215976Sjmallett info.group_index = 0; 3059215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3060215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3061215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 3062215976Sjmallett info.func = __cvmx_error_display; 3063215976Sjmallett info.user_info = (long) 3064215976Sjmallett "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n" 3065215976Sjmallett " port for a non-passthrough packet.\n" 3066215976Sjmallett " The first detected error associated with bits [5:0]\n" 3067215976Sjmallett " of this register will only be set here. A new bit\n" 3068215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 3069215976Sjmallett fail |= cvmx_error_add(&info); 3070215976Sjmallett 3071215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3072215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 3073215976Sjmallett info.status_mask = 1ull<<5 /* p_dat */; 3074215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 3075215976Sjmallett info.enable_mask = 1ull<<5 /* p_dat */; 3076215976Sjmallett info.flags = 0; 3077215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3078215976Sjmallett info.group_index = 0; 3079215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3080215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3081215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 3082215976Sjmallett info.func = __cvmx_error_display; 3083215976Sjmallett info.user_info = (long) 3084215976Sjmallett "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n" 3085215976Sjmallett " port for a passthrough packet.\n" 3086215976Sjmallett " The first detected error associated with bits [5:0]\n" 3087215976Sjmallett " of this register will only be set here. A new bit\n" 3088215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 3089215976Sjmallett fail |= cvmx_error_add(&info); 3090215976Sjmallett 3091215976Sjmallett /* CVMX_USBNX_INT_SUM(0) */ 3092215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3093215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3094215976Sjmallett info.status_mask = 1ull<<0 /* pr_po_e */; 3095215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3096215976Sjmallett info.enable_mask = 1ull<<0 /* pr_po_e */; 3097215976Sjmallett info.flags = 0; 3098215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3099215976Sjmallett info.group_index = 0; 3100215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3101215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3102215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3103215976Sjmallett info.func = __cvmx_error_display; 3104215976Sjmallett info.user_info = (long) 3105215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n"; 3106215976Sjmallett fail |= cvmx_error_add(&info); 3107215976Sjmallett 3108215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3109215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3110215976Sjmallett info.status_mask = 1ull<<1 /* pr_pu_f */; 3111215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3112215976Sjmallett info.enable_mask = 1ull<<1 /* pr_pu_f */; 3113215976Sjmallett info.flags = 0; 3114215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3115215976Sjmallett info.group_index = 0; 3116215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3117215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3118215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3119215976Sjmallett info.func = __cvmx_error_display; 3120215976Sjmallett info.user_info = (long) 3121215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n"; 3122215976Sjmallett fail |= cvmx_error_add(&info); 3123215976Sjmallett 3124215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3125215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3126215976Sjmallett info.status_mask = 1ull<<2 /* nr_po_e */; 3127215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3128215976Sjmallett info.enable_mask = 1ull<<2 /* nr_po_e */; 3129215976Sjmallett info.flags = 0; 3130215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3131215976Sjmallett info.group_index = 0; 3132215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3133215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3134215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3135215976Sjmallett info.func = __cvmx_error_display; 3136215976Sjmallett info.user_info = (long) 3137215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n"; 3138215976Sjmallett fail |= cvmx_error_add(&info); 3139215976Sjmallett 3140215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3141215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3142215976Sjmallett info.status_mask = 1ull<<3 /* nr_pu_f */; 3143215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3144215976Sjmallett info.enable_mask = 1ull<<3 /* nr_pu_f */; 3145215976Sjmallett info.flags = 0; 3146215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3147215976Sjmallett info.group_index = 0; 3148215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3149215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3150215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3151215976Sjmallett info.func = __cvmx_error_display; 3152215976Sjmallett info.user_info = (long) 3153215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n"; 3154215976Sjmallett fail |= cvmx_error_add(&info); 3155215976Sjmallett 3156215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3157215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3158215976Sjmallett info.status_mask = 1ull<<4 /* lr_po_e */; 3159215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3160215976Sjmallett info.enable_mask = 1ull<<4 /* lr_po_e */; 3161215976Sjmallett info.flags = 0; 3162215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3163215976Sjmallett info.group_index = 0; 3164215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3165215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3166215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3167215976Sjmallett info.func = __cvmx_error_display; 3168215976Sjmallett info.user_info = (long) 3169215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n"; 3170215976Sjmallett fail |= cvmx_error_add(&info); 3171215976Sjmallett 3172215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3173215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3174215976Sjmallett info.status_mask = 1ull<<5 /* lr_pu_f */; 3175215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3176215976Sjmallett info.enable_mask = 1ull<<5 /* lr_pu_f */; 3177215976Sjmallett info.flags = 0; 3178215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3179215976Sjmallett info.group_index = 0; 3180215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3181215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3182215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3183215976Sjmallett info.func = __cvmx_error_display; 3184215976Sjmallett info.user_info = (long) 3185215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n"; 3186215976Sjmallett fail |= cvmx_error_add(&info); 3187215976Sjmallett 3188215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3189215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3190215976Sjmallett info.status_mask = 1ull<<6 /* pt_po_e */; 3191215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3192215976Sjmallett info.enable_mask = 1ull<<6 /* pt_po_e */; 3193215976Sjmallett info.flags = 0; 3194215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3195215976Sjmallett info.group_index = 0; 3196215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3197215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3198215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3199215976Sjmallett info.func = __cvmx_error_display; 3200215976Sjmallett info.user_info = (long) 3201215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n"; 3202215976Sjmallett fail |= cvmx_error_add(&info); 3203215976Sjmallett 3204215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3205215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3206215976Sjmallett info.status_mask = 1ull<<7 /* pt_pu_f */; 3207215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3208215976Sjmallett info.enable_mask = 1ull<<7 /* pt_pu_f */; 3209215976Sjmallett info.flags = 0; 3210215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3211215976Sjmallett info.group_index = 0; 3212215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3213215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3214215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3215215976Sjmallett info.func = __cvmx_error_display; 3216215976Sjmallett info.user_info = (long) 3217215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n"; 3218215976Sjmallett fail |= cvmx_error_add(&info); 3219215976Sjmallett 3220215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3221215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3222215976Sjmallett info.status_mask = 1ull<<8 /* nt_po_e */; 3223215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3224215976Sjmallett info.enable_mask = 1ull<<8 /* nt_po_e */; 3225215976Sjmallett info.flags = 0; 3226215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3227215976Sjmallett info.group_index = 0; 3228215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3229215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3230215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3231215976Sjmallett info.func = __cvmx_error_display; 3232215976Sjmallett info.user_info = (long) 3233215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n"; 3234215976Sjmallett fail |= cvmx_error_add(&info); 3235215976Sjmallett 3236215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3237215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3238215976Sjmallett info.status_mask = 1ull<<9 /* nt_pu_f */; 3239215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3240215976Sjmallett info.enable_mask = 1ull<<9 /* nt_pu_f */; 3241215976Sjmallett info.flags = 0; 3242215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3243215976Sjmallett info.group_index = 0; 3244215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3245215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3246215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3247215976Sjmallett info.func = __cvmx_error_display; 3248215976Sjmallett info.user_info = (long) 3249215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n"; 3250215976Sjmallett fail |= cvmx_error_add(&info); 3251215976Sjmallett 3252215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3253215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3254215976Sjmallett info.status_mask = 1ull<<10 /* lt_po_e */; 3255215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3256215976Sjmallett info.enable_mask = 1ull<<10 /* lt_po_e */; 3257215976Sjmallett info.flags = 0; 3258215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3259215976Sjmallett info.group_index = 0; 3260215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3261215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3262215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3263215976Sjmallett info.func = __cvmx_error_display; 3264215976Sjmallett info.user_info = (long) 3265215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n"; 3266215976Sjmallett fail |= cvmx_error_add(&info); 3267215976Sjmallett 3268215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3269215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3270215976Sjmallett info.status_mask = 1ull<<11 /* lt_pu_f */; 3271215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3272215976Sjmallett info.enable_mask = 1ull<<11 /* lt_pu_f */; 3273215976Sjmallett info.flags = 0; 3274215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3275215976Sjmallett info.group_index = 0; 3276215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3277215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3278215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3279215976Sjmallett info.func = __cvmx_error_display; 3280215976Sjmallett info.user_info = (long) 3281215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n"; 3282215976Sjmallett fail |= cvmx_error_add(&info); 3283215976Sjmallett 3284215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3285215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3286215976Sjmallett info.status_mask = 1ull<<12 /* dcred_e */; 3287215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3288215976Sjmallett info.enable_mask = 1ull<<12 /* dcred_e */; 3289215976Sjmallett info.flags = 0; 3290215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3291215976Sjmallett info.group_index = 0; 3292215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3293215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3294215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3295215976Sjmallett info.func = __cvmx_error_display; 3296215976Sjmallett info.user_info = (long) 3297215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n"; 3298215976Sjmallett fail |= cvmx_error_add(&info); 3299215976Sjmallett 3300215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3301215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3302215976Sjmallett info.status_mask = 1ull<<13 /* dcred_f */; 3303215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3304215976Sjmallett info.enable_mask = 1ull<<13 /* dcred_f */; 3305215976Sjmallett info.flags = 0; 3306215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3307215976Sjmallett info.group_index = 0; 3308215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3309215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3310215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3311215976Sjmallett info.func = __cvmx_error_display; 3312215976Sjmallett info.user_info = (long) 3313215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n"; 3314215976Sjmallett fail |= cvmx_error_add(&info); 3315215976Sjmallett 3316215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3317215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3318215976Sjmallett info.status_mask = 1ull<<14 /* l2c_s_e */; 3319215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3320215976Sjmallett info.enable_mask = 1ull<<14 /* l2c_s_e */; 3321215976Sjmallett info.flags = 0; 3322215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3323215976Sjmallett info.group_index = 0; 3324215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3325215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3326215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3327215976Sjmallett info.func = __cvmx_error_display; 3328215976Sjmallett info.user_info = (long) 3329215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n"; 3330215976Sjmallett fail |= cvmx_error_add(&info); 3331215976Sjmallett 3332215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3333215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3334215976Sjmallett info.status_mask = 1ull<<15 /* l2c_a_f */; 3335215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3336215976Sjmallett info.enable_mask = 1ull<<15 /* l2c_a_f */; 3337215976Sjmallett info.flags = 0; 3338215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3339215976Sjmallett info.group_index = 0; 3340215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3341215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3342215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3343215976Sjmallett info.func = __cvmx_error_display; 3344215976Sjmallett info.user_info = (long) 3345215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n"; 3346215976Sjmallett fail |= cvmx_error_add(&info); 3347215976Sjmallett 3348215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3349215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3350215976Sjmallett info.status_mask = 1ull<<16 /* lt_fi_e */; 3351215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3352215976Sjmallett info.enable_mask = 1ull<<16 /* l2_fi_e */; 3353215976Sjmallett info.flags = 0; 3354215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3355215976Sjmallett info.group_index = 0; 3356215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3357215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3358215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3359215976Sjmallett info.func = __cvmx_error_display; 3360215976Sjmallett info.user_info = (long) 3361215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n"; 3362215976Sjmallett fail |= cvmx_error_add(&info); 3363215976Sjmallett 3364215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3365215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3366215976Sjmallett info.status_mask = 1ull<<17 /* lt_fi_f */; 3367215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3368215976Sjmallett info.enable_mask = 1ull<<17 /* l2_fi_f */; 3369215976Sjmallett info.flags = 0; 3370215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3371215976Sjmallett info.group_index = 0; 3372215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3373215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3374215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3375215976Sjmallett info.func = __cvmx_error_display; 3376215976Sjmallett info.user_info = (long) 3377215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n"; 3378215976Sjmallett fail |= cvmx_error_add(&info); 3379215976Sjmallett 3380215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3381215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3382215976Sjmallett info.status_mask = 1ull<<18 /* rg_fi_e */; 3383215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3384215976Sjmallett info.enable_mask = 1ull<<18 /* rg_fi_e */; 3385215976Sjmallett info.flags = 0; 3386215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3387215976Sjmallett info.group_index = 0; 3388215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3389215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3390215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3391215976Sjmallett info.func = __cvmx_error_display; 3392215976Sjmallett info.user_info = (long) 3393215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n"; 3394215976Sjmallett fail |= cvmx_error_add(&info); 3395215976Sjmallett 3396215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3397215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3398215976Sjmallett info.status_mask = 1ull<<19 /* rg_fi_f */; 3399215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3400215976Sjmallett info.enable_mask = 1ull<<19 /* rg_fi_f */; 3401215976Sjmallett info.flags = 0; 3402215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3403215976Sjmallett info.group_index = 0; 3404215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3405215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3406215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3407215976Sjmallett info.func = __cvmx_error_display; 3408215976Sjmallett info.user_info = (long) 3409215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n"; 3410215976Sjmallett fail |= cvmx_error_add(&info); 3411215976Sjmallett 3412215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3413215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3414215976Sjmallett info.status_mask = 1ull<<20 /* rq_q2_f */; 3415215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3416215976Sjmallett info.enable_mask = 1ull<<20 /* rq_q2_f */; 3417215976Sjmallett info.flags = 0; 3418215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3419215976Sjmallett info.group_index = 0; 3420215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3421215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3422215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3423215976Sjmallett info.func = __cvmx_error_display; 3424215976Sjmallett info.user_info = (long) 3425215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n"; 3426215976Sjmallett fail |= cvmx_error_add(&info); 3427215976Sjmallett 3428215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3429215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3430215976Sjmallett info.status_mask = 1ull<<21 /* rq_q2_e */; 3431215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3432215976Sjmallett info.enable_mask = 1ull<<21 /* rq_q2_e */; 3433215976Sjmallett info.flags = 0; 3434215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3435215976Sjmallett info.group_index = 0; 3436215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3437215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3438215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3439215976Sjmallett info.func = __cvmx_error_display; 3440215976Sjmallett info.user_info = (long) 3441215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n"; 3442215976Sjmallett fail |= cvmx_error_add(&info); 3443215976Sjmallett 3444215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3445215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3446215976Sjmallett info.status_mask = 1ull<<22 /* rq_q3_f */; 3447215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3448215976Sjmallett info.enable_mask = 1ull<<22 /* rq_q3_f */; 3449215976Sjmallett info.flags = 0; 3450215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3451215976Sjmallett info.group_index = 0; 3452215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3453215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3454215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3455215976Sjmallett info.func = __cvmx_error_display; 3456215976Sjmallett info.user_info = (long) 3457215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n"; 3458215976Sjmallett fail |= cvmx_error_add(&info); 3459215976Sjmallett 3460215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3461215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3462215976Sjmallett info.status_mask = 1ull<<23 /* rq_q3_e */; 3463215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3464215976Sjmallett info.enable_mask = 1ull<<23 /* rq_q3_e */; 3465215976Sjmallett info.flags = 0; 3466215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3467215976Sjmallett info.group_index = 0; 3468215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3469215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3470215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3471215976Sjmallett info.func = __cvmx_error_display; 3472215976Sjmallett info.user_info = (long) 3473215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n"; 3474215976Sjmallett fail |= cvmx_error_add(&info); 3475215976Sjmallett 3476215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3477215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3478215976Sjmallett info.status_mask = 1ull<<24 /* uod_pe */; 3479215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3480215976Sjmallett info.enable_mask = 1ull<<24 /* uod_pe */; 3481215976Sjmallett info.flags = 0; 3482215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3483215976Sjmallett info.group_index = 0; 3484215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3485215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3486215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3487215976Sjmallett info.func = __cvmx_error_display; 3488215976Sjmallett info.user_info = (long) 3489215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n"; 3490215976Sjmallett fail |= cvmx_error_add(&info); 3491215976Sjmallett 3492215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3493215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3494215976Sjmallett info.status_mask = 1ull<<25 /* uod_pf */; 3495215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3496215976Sjmallett info.enable_mask = 1ull<<25 /* uod_pf */; 3497215976Sjmallett info.flags = 0; 3498215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3499215976Sjmallett info.group_index = 0; 3500215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3501215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3502215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3503215976Sjmallett info.func = __cvmx_error_display; 3504215976Sjmallett info.user_info = (long) 3505215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n"; 3506215976Sjmallett fail |= cvmx_error_add(&info); 3507215976Sjmallett 3508215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3509215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3510215976Sjmallett info.status_mask = 1ull<<32 /* ltl_f_pe */; 3511215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3512215976Sjmallett info.enable_mask = 1ull<<32 /* ltl_f_pe */; 3513215976Sjmallett info.flags = 0; 3514215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3515215976Sjmallett info.group_index = 0; 3516215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3517215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3518215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3519215976Sjmallett info.func = __cvmx_error_display; 3520215976Sjmallett info.user_info = (long) 3521215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n"; 3522215976Sjmallett fail |= cvmx_error_add(&info); 3523215976Sjmallett 3524215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3525215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3526215976Sjmallett info.status_mask = 1ull<<33 /* ltl_f_pf */; 3527215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3528215976Sjmallett info.enable_mask = 1ull<<33 /* ltl_f_pf */; 3529215976Sjmallett info.flags = 0; 3530215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3531215976Sjmallett info.group_index = 0; 3532215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3533215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3534215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3535215976Sjmallett info.func = __cvmx_error_display; 3536215976Sjmallett info.user_info = (long) 3537215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n"; 3538215976Sjmallett fail |= cvmx_error_add(&info); 3539215976Sjmallett 3540215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3541215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3542215976Sjmallett info.status_mask = 1ull<<34 /* nd4o_rpe */; 3543215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3544215976Sjmallett info.enable_mask = 1ull<<34 /* nd4o_rpe */; 3545215976Sjmallett info.flags = 0; 3546215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3547215976Sjmallett info.group_index = 0; 3548215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3549215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3550215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3551215976Sjmallett info.func = __cvmx_error_display; 3552215976Sjmallett info.user_info = (long) 3553215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n"; 3554215976Sjmallett fail |= cvmx_error_add(&info); 3555215976Sjmallett 3556215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3557215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3558215976Sjmallett info.status_mask = 1ull<<35 /* nd4o_rpf */; 3559215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3560215976Sjmallett info.enable_mask = 1ull<<35 /* nd4o_rpf */; 3561215976Sjmallett info.flags = 0; 3562215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3563215976Sjmallett info.group_index = 0; 3564215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3565215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3566215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3567215976Sjmallett info.func = __cvmx_error_display; 3568215976Sjmallett info.user_info = (long) 3569215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n"; 3570215976Sjmallett fail |= cvmx_error_add(&info); 3571215976Sjmallett 3572215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3573215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3574215976Sjmallett info.status_mask = 1ull<<36 /* nd4o_dpe */; 3575215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3576215976Sjmallett info.enable_mask = 1ull<<36 /* nd4o_dpe */; 3577215976Sjmallett info.flags = 0; 3578215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3579215976Sjmallett info.group_index = 0; 3580215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3581215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3582215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3583215976Sjmallett info.func = __cvmx_error_display; 3584215976Sjmallett info.user_info = (long) 3585215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n"; 3586215976Sjmallett fail |= cvmx_error_add(&info); 3587215976Sjmallett 3588215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3589215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3590215976Sjmallett info.status_mask = 1ull<<37 /* nd4o_dpf */; 3591215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3592215976Sjmallett info.enable_mask = 1ull<<37 /* nd4o_dpf */; 3593215976Sjmallett info.flags = 0; 3594215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3595215976Sjmallett info.group_index = 0; 3596215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3597215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3598215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3599215976Sjmallett info.func = __cvmx_error_display; 3600215976Sjmallett info.user_info = (long) 3601215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n"; 3602215976Sjmallett fail |= cvmx_error_add(&info); 3603215976Sjmallett 3604215976Sjmallett return fail; 3605215976Sjmallett} 3606215976Sjmallett 3607