1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * @file 43215976Sjmallett * 44215976Sjmallett * Automatically generated error messages for cn31xx. 45215976Sjmallett * 46215976Sjmallett * This file is auto generated. Do not edit. 47215976Sjmallett * 48215976Sjmallett * <hr>$Revision$<hr> 49215976Sjmallett * 50215976Sjmallett * <hr><h2>Error tree for CN31XX</h2> 51215976Sjmallett * @dot 52215976Sjmallett * digraph cn31xx 53215976Sjmallett * { 54215976Sjmallett * rankdir=LR; 55215976Sjmallett * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica]; 56215976Sjmallett * edge [fontsize=7, font=helvitica]; 57215976Sjmallett * cvmx_root [label="ROOT|<root>root"]; 58215976Sjmallett * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"]; 59215976Sjmallett * cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"]; 60215976Sjmallett * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"]; 61215976Sjmallett * cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"]; 62215976Sjmallett * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"]; 63215976Sjmallett * cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"]; 64215976Sjmallett * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"]; 65215976Sjmallett * cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"]; 66215976Sjmallett * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"]; 67215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"]; 68215976Sjmallett * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"]; 69215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"]; 70215976Sjmallett * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<zip>zip|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<usb>usb"]; 71215976Sjmallett * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"]; 72215976Sjmallett * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"]; 73215976Sjmallett * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"]; 74215976Sjmallett * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"]; 75215976Sjmallett * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"]; 76215976Sjmallett * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"]; 77215976Sjmallett * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"]; 78215976Sjmallett * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"]; 79215976Sjmallett * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 80215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"]; 81215976Sjmallett * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 82215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"]; 83215976Sjmallett * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 84215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"]; 85215976Sjmallett * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"]; 86215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"]; 87215976Sjmallett * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"]; 88215976Sjmallett * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"]; 89215976Sjmallett * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"]; 90215976Sjmallett * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"]; 91215976Sjmallett * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"]; 92215976Sjmallett * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"]; 93215976Sjmallett * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe"]; 94215976Sjmallett * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"]; 95215976Sjmallett * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"]; 96215976Sjmallett * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"]; 97215976Sjmallett * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"]; 98215976Sjmallett * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"]; 99215976Sjmallett * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"]; 100215976Sjmallett * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"]; 101215976Sjmallett * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"]; 102215976Sjmallett * cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"]; 103215976Sjmallett * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"]; 104215976Sjmallett * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"]; 105215976Sjmallett * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"]; 106215976Sjmallett * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"]; 107215976Sjmallett * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"]; 108215976Sjmallett * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"]; 109215976Sjmallett * cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"]; 110215976Sjmallett * cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"]; 111215976Sjmallett * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"]; 112215976Sjmallett * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"]; 113215976Sjmallett * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<n2u_pf>n2u_pf|<n2u_pe>n2u_pe|<u2n_d_pe>u2n_d_pe|<u2n_d_pf>u2n_d_pf|<u2n_c_pf>u2n_c_pf|<u2n_c_pe>u2n_c_pe|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"]; 114215976Sjmallett * cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"]; 115215976Sjmallett * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis]; 116215976Sjmallett * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis]; 117215976Sjmallett * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis]; 118215976Sjmallett * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis]; 119215976Sjmallett * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"]; 120215976Sjmallett * } 121215976Sjmallett * @enddot 122215976Sjmallett */ 123215976Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 124215976Sjmallett#include <asm/octeon/cvmx.h> 125215976Sjmallett#include <asm/octeon/cvmx-error.h> 126215976Sjmallett#include <asm/octeon/cvmx-error-custom.h> 127215976Sjmallett#include <asm/octeon/cvmx-csr-typedefs.h> 128215976Sjmallett#else 129215976Sjmallett#include "cvmx.h" 130215976Sjmallett#include "cvmx-error.h" 131215976Sjmallett#include "cvmx-error-custom.h" 132215976Sjmallett#endif 133215976Sjmallett 134215990Sjmallettint cvmx_error_initialize_cn31xx(void); 135215990Sjmallett 136215976Sjmallettint cvmx_error_initialize_cn31xx(void) 137215976Sjmallett{ 138215976Sjmallett cvmx_error_info_t info; 139215976Sjmallett int fail = 0; 140215976Sjmallett 141215976Sjmallett /* CVMX_CIU_INTX_SUM0(0) */ 142215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 143215976Sjmallett info.status_addr = CVMX_CIU_INTX_SUM0(0); 144215976Sjmallett info.status_mask = 0; 145215976Sjmallett info.enable_addr = 0; 146215976Sjmallett info.enable_mask = 0; 147215976Sjmallett info.flags = 0; 148215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 149215976Sjmallett info.group_index = 0; 150215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 151215976Sjmallett info.parent.status_addr = 0; 152215976Sjmallett info.parent.status_mask = 0; 153215976Sjmallett info.func = __cvmx_error_decode; 154215976Sjmallett info.user_info = 0; 155215976Sjmallett fail |= cvmx_error_add(&info); 156215976Sjmallett 157215976Sjmallett /* CVMX_PCMX_INT_SUM(0) */ 158215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 159215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(0); 160215976Sjmallett info.status_mask = 1ull<<0 /* fsyncmissed */; 161215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(0); 162215976Sjmallett info.enable_mask = 1ull<<0 /* fsyncmissed */; 163215976Sjmallett info.flags = 0; 164215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 165215976Sjmallett info.group_index = 0; 166215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 167215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 168215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 169215976Sjmallett info.func = __cvmx_error_display; 170215976Sjmallett info.user_info = (long) 171215976Sjmallett "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n"; 172215976Sjmallett fail |= cvmx_error_add(&info); 173215976Sjmallett 174215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 175215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(0); 176215976Sjmallett info.status_mask = 1ull<<1 /* fsyncextra */; 177215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(0); 178215976Sjmallett info.enable_mask = 1ull<<1 /* fsyncextra */; 179215976Sjmallett info.flags = 0; 180215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 181215976Sjmallett info.group_index = 0; 182215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 183215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 184215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 185215976Sjmallett info.func = __cvmx_error_display; 186215976Sjmallett info.user_info = (long) 187215976Sjmallett "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n"; 188215976Sjmallett fail |= cvmx_error_add(&info); 189215976Sjmallett 190215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 191215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(0); 192215976Sjmallett info.status_mask = 1ull<<6 /* txempty */; 193215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(0); 194215976Sjmallett info.enable_mask = 1ull<<6 /* txempty */; 195215976Sjmallett info.flags = 0; 196215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 197215976Sjmallett info.group_index = 0; 198215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 199215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 200215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 201215976Sjmallett info.func = __cvmx_error_display; 202215976Sjmallett info.user_info = (long) 203215976Sjmallett "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n"; 204215976Sjmallett fail |= cvmx_error_add(&info); 205215976Sjmallett 206215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 207215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(0); 208215976Sjmallett info.status_mask = 1ull<<7 /* rxovf */; 209215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(0); 210215976Sjmallett info.enable_mask = 1ull<<7 /* rxovf */; 211215976Sjmallett info.flags = 0; 212215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 213215976Sjmallett info.group_index = 0; 214215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 215215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 216215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 217215976Sjmallett info.func = __cvmx_error_display; 218215976Sjmallett info.user_info = (long) 219215976Sjmallett "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n"; 220215976Sjmallett fail |= cvmx_error_add(&info); 221215976Sjmallett 222215976Sjmallett /* CVMX_PCMX_INT_SUM(1) */ 223215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 224215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(1); 225215976Sjmallett info.status_mask = 1ull<<0 /* fsyncmissed */; 226215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(1); 227215976Sjmallett info.enable_mask = 1ull<<0 /* fsyncmissed */; 228215976Sjmallett info.flags = 0; 229215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 230215976Sjmallett info.group_index = 0; 231215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 232215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 233215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 234215976Sjmallett info.func = __cvmx_error_display; 235215976Sjmallett info.user_info = (long) 236215976Sjmallett "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n"; 237215976Sjmallett fail |= cvmx_error_add(&info); 238215976Sjmallett 239215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 240215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(1); 241215976Sjmallett info.status_mask = 1ull<<1 /* fsyncextra */; 242215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(1); 243215976Sjmallett info.enable_mask = 1ull<<1 /* fsyncextra */; 244215976Sjmallett info.flags = 0; 245215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 246215976Sjmallett info.group_index = 0; 247215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 248215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 249215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 250215976Sjmallett info.func = __cvmx_error_display; 251215976Sjmallett info.user_info = (long) 252215976Sjmallett "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n"; 253215976Sjmallett fail |= cvmx_error_add(&info); 254215976Sjmallett 255215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 256215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(1); 257215976Sjmallett info.status_mask = 1ull<<6 /* txempty */; 258215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(1); 259215976Sjmallett info.enable_mask = 1ull<<6 /* txempty */; 260215976Sjmallett info.flags = 0; 261215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 262215976Sjmallett info.group_index = 0; 263215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 264215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 265215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 266215976Sjmallett info.func = __cvmx_error_display; 267215976Sjmallett info.user_info = (long) 268215976Sjmallett "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n"; 269215976Sjmallett fail |= cvmx_error_add(&info); 270215976Sjmallett 271215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 272215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(1); 273215976Sjmallett info.status_mask = 1ull<<7 /* rxovf */; 274215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(1); 275215976Sjmallett info.enable_mask = 1ull<<7 /* rxovf */; 276215976Sjmallett info.flags = 0; 277215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 278215976Sjmallett info.group_index = 0; 279215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 280215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 281215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 282215976Sjmallett info.func = __cvmx_error_display; 283215976Sjmallett info.user_info = (long) 284215976Sjmallett "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n"; 285215976Sjmallett fail |= cvmx_error_add(&info); 286215976Sjmallett 287215976Sjmallett /* CVMX_PCMX_INT_SUM(2) */ 288215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 289215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(2); 290215976Sjmallett info.status_mask = 1ull<<0 /* fsyncmissed */; 291215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(2); 292215976Sjmallett info.enable_mask = 1ull<<0 /* fsyncmissed */; 293215976Sjmallett info.flags = 0; 294215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 295215976Sjmallett info.group_index = 0; 296215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 297215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 298215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 299215976Sjmallett info.func = __cvmx_error_display; 300215976Sjmallett info.user_info = (long) 301215976Sjmallett "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n"; 302215976Sjmallett fail |= cvmx_error_add(&info); 303215976Sjmallett 304215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 305215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(2); 306215976Sjmallett info.status_mask = 1ull<<1 /* fsyncextra */; 307215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(2); 308215976Sjmallett info.enable_mask = 1ull<<1 /* fsyncextra */; 309215976Sjmallett info.flags = 0; 310215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 311215976Sjmallett info.group_index = 0; 312215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 313215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 314215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 315215976Sjmallett info.func = __cvmx_error_display; 316215976Sjmallett info.user_info = (long) 317215976Sjmallett "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n"; 318215976Sjmallett fail |= cvmx_error_add(&info); 319215976Sjmallett 320215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 321215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(2); 322215976Sjmallett info.status_mask = 1ull<<6 /* txempty */; 323215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(2); 324215976Sjmallett info.enable_mask = 1ull<<6 /* txempty */; 325215976Sjmallett info.flags = 0; 326215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 327215976Sjmallett info.group_index = 0; 328215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 329215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 330215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 331215976Sjmallett info.func = __cvmx_error_display; 332215976Sjmallett info.user_info = (long) 333215976Sjmallett "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n"; 334215976Sjmallett fail |= cvmx_error_add(&info); 335215976Sjmallett 336215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 337215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(2); 338215976Sjmallett info.status_mask = 1ull<<7 /* rxovf */; 339215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(2); 340215976Sjmallett info.enable_mask = 1ull<<7 /* rxovf */; 341215976Sjmallett info.flags = 0; 342215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 343215976Sjmallett info.group_index = 0; 344215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 345215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 346215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 347215976Sjmallett info.func = __cvmx_error_display; 348215976Sjmallett info.user_info = (long) 349215976Sjmallett "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n"; 350215976Sjmallett fail |= cvmx_error_add(&info); 351215976Sjmallett 352215976Sjmallett /* CVMX_PCMX_INT_SUM(3) */ 353215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 354215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(3); 355215976Sjmallett info.status_mask = 1ull<<0 /* fsyncmissed */; 356215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(3); 357215976Sjmallett info.enable_mask = 1ull<<0 /* fsyncmissed */; 358215976Sjmallett info.flags = 0; 359215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 360215976Sjmallett info.group_index = 0; 361215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 362215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 363215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 364215976Sjmallett info.func = __cvmx_error_display; 365215976Sjmallett info.user_info = (long) 366215976Sjmallett "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n"; 367215976Sjmallett fail |= cvmx_error_add(&info); 368215976Sjmallett 369215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 370215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(3); 371215976Sjmallett info.status_mask = 1ull<<1 /* fsyncextra */; 372215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(3); 373215976Sjmallett info.enable_mask = 1ull<<1 /* fsyncextra */; 374215976Sjmallett info.flags = 0; 375215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 376215976Sjmallett info.group_index = 0; 377215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 378215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 379215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 380215976Sjmallett info.func = __cvmx_error_display; 381215976Sjmallett info.user_info = (long) 382215976Sjmallett "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n"; 383215976Sjmallett fail |= cvmx_error_add(&info); 384215976Sjmallett 385215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 386215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(3); 387215976Sjmallett info.status_mask = 1ull<<6 /* txempty */; 388215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(3); 389215976Sjmallett info.enable_mask = 1ull<<6 /* txempty */; 390215976Sjmallett info.flags = 0; 391215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 392215976Sjmallett info.group_index = 0; 393215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 394215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 395215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 396215976Sjmallett info.func = __cvmx_error_display; 397215976Sjmallett info.user_info = (long) 398215976Sjmallett "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n"; 399215976Sjmallett fail |= cvmx_error_add(&info); 400215976Sjmallett 401215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 402215976Sjmallett info.status_addr = CVMX_PCMX_INT_SUM(3); 403215976Sjmallett info.status_mask = 1ull<<7 /* rxovf */; 404215976Sjmallett info.enable_addr = CVMX_PCMX_INT_ENA(3); 405215976Sjmallett info.enable_mask = 1ull<<7 /* rxovf */; 406215976Sjmallett info.flags = 0; 407215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 408215976Sjmallett info.group_index = 0; 409215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 410215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 411215976Sjmallett info.parent.status_mask = 1ull<<57 /* pcm */; 412215976Sjmallett info.func = __cvmx_error_display; 413215976Sjmallett info.user_info = (long) 414215976Sjmallett "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n"; 415215976Sjmallett fail |= cvmx_error_add(&info); 416215976Sjmallett 417215976Sjmallett /* CVMX_CIU_INT_SUM1 */ 418215976Sjmallett /* CVMX_NPI_RSL_INT_BLOCKS */ 419215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 420215976Sjmallett info.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 421215976Sjmallett info.status_mask = 0; 422215976Sjmallett info.enable_addr = 0; 423215976Sjmallett info.enable_mask = 0; 424215976Sjmallett info.flags = 0; 425215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 426215976Sjmallett info.group_index = 0; 427215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 428215976Sjmallett info.parent.status_addr = 0; 429215976Sjmallett info.parent.status_mask = 0; 430215976Sjmallett info.func = __cvmx_error_decode; 431215976Sjmallett info.user_info = 0; 432215976Sjmallett fail |= cvmx_error_add(&info); 433215976Sjmallett 434215976Sjmallett /* CVMX_L2D_ERR */ 435215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 436215976Sjmallett info.status_addr = CVMX_L2D_ERR; 437215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 438215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 439215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 440215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 441215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 442215976Sjmallett info.group_index = 0; 443215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 444215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 445215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 446215976Sjmallett info.func = __cvmx_error_handle_l2d_err_sec_err; 447215976Sjmallett info.user_info = (long) 448215976Sjmallett "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n"; 449215976Sjmallett fail |= cvmx_error_add(&info); 450215976Sjmallett 451215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 452215976Sjmallett info.status_addr = CVMX_L2D_ERR; 453215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 454215976Sjmallett info.enable_addr = CVMX_L2D_ERR; 455215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 456215976Sjmallett info.flags = 0; 457215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 458215976Sjmallett info.group_index = 0; 459215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 460215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 461215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 462215976Sjmallett info.func = __cvmx_error_handle_l2d_err_ded_err; 463215976Sjmallett info.user_info = (long) 464215976Sjmallett "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n"; 465215976Sjmallett fail |= cvmx_error_add(&info); 466215976Sjmallett 467215976Sjmallett /* CVMX_L2T_ERR */ 468215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 469215976Sjmallett info.status_addr = CVMX_L2T_ERR; 470215976Sjmallett info.status_mask = 1ull<<3 /* sec_err */; 471215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 472215976Sjmallett info.enable_mask = 1ull<<1 /* sec_intena */; 473215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 474215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 475215976Sjmallett info.group_index = 0; 476215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 477215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 478215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 479215976Sjmallett info.func = __cvmx_error_handle_l2t_err_sec_err; 480215976Sjmallett info.user_info = (long) 481215976Sjmallett "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n" 482215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 483215976Sjmallett " given index) are checked for single bit errors(SBEs).\n" 484215976Sjmallett " This bit is set if ANY of the 8 sets contains an SBE.\n" 485215976Sjmallett " SBEs are auto corrected in HW and generate an\n" 486215976Sjmallett " interrupt(if enabled).\n"; 487215976Sjmallett fail |= cvmx_error_add(&info); 488215976Sjmallett 489215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 490215976Sjmallett info.status_addr = CVMX_L2T_ERR; 491215976Sjmallett info.status_mask = 1ull<<4 /* ded_err */; 492215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 493215976Sjmallett info.enable_mask = 1ull<<2 /* ded_intena */; 494215976Sjmallett info.flags = 0; 495215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 496215976Sjmallett info.group_index = 0; 497215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 498215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 499215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 500215976Sjmallett info.func = __cvmx_error_handle_l2t_err_ded_err; 501215976Sjmallett info.user_info = (long) 502215976Sjmallett "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n" 503215976Sjmallett " During every L2 Tag Probe, all 8 sets Tag's (at a\n" 504215976Sjmallett " given index) are checked for double bit errors(DBEs).\n" 505215976Sjmallett " This bit is set if ANY of the 8 sets contains a DBE.\n" 506215976Sjmallett " DBEs also generated an interrupt(if enabled).\n"; 507215976Sjmallett fail |= cvmx_error_add(&info); 508215976Sjmallett 509215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 510215976Sjmallett info.status_addr = CVMX_L2T_ERR; 511215976Sjmallett info.status_mask = 1ull<<24 /* lckerr */; 512215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 513215976Sjmallett info.enable_mask = 1ull<<25 /* lck_intena */; 514215976Sjmallett info.flags = 0; 515215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 516215976Sjmallett info.group_index = 0; 517215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 518215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 519215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 520215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr; 521215976Sjmallett info.user_info = (long) 522215976Sjmallett "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n" 523215976Sjmallett " the INDEX (which is ignored by HW - but reported to SW).\n" 524215976Sjmallett " The LDD(L1 load-miss) for the LOCK operation is completed\n" 525215976Sjmallett " successfully, however the address is NOT locked.\n" 526215976Sjmallett " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n" 527215976Sjmallett " into account. For example, if diagnostic PPx has\n" 528215976Sjmallett " UMSKx defined to only use SETs [1:0], and SET1 had\n" 529215976Sjmallett " been previously LOCKED, then an attempt to LOCK the\n" 530215976Sjmallett " last available SET0 would result in a LCKERR. (This\n" 531215976Sjmallett " is to ensure that at least 1 SET at each INDEX is\n" 532215976Sjmallett " not LOCKED for general use by other PPs).\n"; 533215976Sjmallett fail |= cvmx_error_add(&info); 534215976Sjmallett 535215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 536215976Sjmallett info.status_addr = CVMX_L2T_ERR; 537215976Sjmallett info.status_mask = 1ull<<26 /* lckerr2 */; 538215976Sjmallett info.enable_addr = CVMX_L2T_ERR; 539215976Sjmallett info.enable_mask = 1ull<<27 /* lck_intena2 */; 540215976Sjmallett info.flags = 0; 541215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 542215976Sjmallett info.group_index = 0; 543215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 544215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 545215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 546215976Sjmallett info.func = __cvmx_error_handle_l2t_err_lckerr2; 547215976Sjmallett info.user_info = (long) 548215976Sjmallett "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n" 549215976Sjmallett " could not find an available/unlocked set (for\n" 550215976Sjmallett " replacement).\n" 551215976Sjmallett " Most likely, this is a result of SW mixing SET\n" 552215976Sjmallett " PARTITIONING with ADDRESS LOCKING. If SW allows\n" 553215976Sjmallett " another PP to LOCKDOWN all SETs available to PP#n,\n" 554215976Sjmallett " then a Rd/Wr Miss from PP#n will be unable\n" 555215976Sjmallett " to determine a 'valid' replacement set (since LOCKED\n" 556215976Sjmallett " addresses should NEVER be replaced).\n" 557215976Sjmallett " If such an event occurs, the HW will select the smallest\n" 558215976Sjmallett " available SET(specified by UMSK'x)' as the replacement\n" 559215976Sjmallett " set, and the address is unlocked.\n"; 560215976Sjmallett fail |= cvmx_error_add(&info); 561215976Sjmallett 562215976Sjmallett /* CVMX_NPI_INT_SUM */ 563215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 564215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 565215976Sjmallett info.status_mask = 1ull<<0 /* rml_rto */; 566215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 567215976Sjmallett info.enable_mask = 1ull<<0 /* rml_rto */; 568215976Sjmallett info.flags = 0; 569215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 570215976Sjmallett info.group_index = 0; 571215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 572215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 573215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 574215976Sjmallett info.func = __cvmx_error_display; 575215976Sjmallett info.user_info = (long) 576215976Sjmallett "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n" 577215976Sjmallett " back from a RSL after sending a read command to\n" 578215976Sjmallett " a RSL.\n"; 579215976Sjmallett fail |= cvmx_error_add(&info); 580215976Sjmallett 581215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 582215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 583215976Sjmallett info.status_mask = 1ull<<1 /* rml_wto */; 584215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 585215976Sjmallett info.enable_mask = 1ull<<1 /* rml_wto */; 586215976Sjmallett info.flags = 0; 587215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 588215976Sjmallett info.group_index = 0; 589215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 590215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 591215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 592215976Sjmallett info.func = __cvmx_error_display; 593215976Sjmallett info.user_info = (long) 594215976Sjmallett "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n" 595215976Sjmallett " back from a RSL after sending a write command to\n" 596215976Sjmallett " a RSL.\n"; 597215976Sjmallett fail |= cvmx_error_add(&info); 598215976Sjmallett 599215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 600215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 601215976Sjmallett info.status_mask = 1ull<<3 /* po0_2sml */; 602215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 603215976Sjmallett info.enable_mask = 1ull<<3 /* po0_2sml */; 604215976Sjmallett info.flags = 0; 605215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 606215976Sjmallett info.group_index = 0; 607215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 608215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 609215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 610215976Sjmallett info.func = __cvmx_error_display; 611215976Sjmallett info.user_info = (long) 612215976Sjmallett "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n" 613215976Sjmallett " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n"; 614215976Sjmallett fail |= cvmx_error_add(&info); 615215976Sjmallett 616215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 617215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 618215976Sjmallett info.status_mask = 1ull<<4 /* po1_2sml */; 619215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 620215976Sjmallett info.enable_mask = 1ull<<4 /* po1_2sml */; 621215976Sjmallett info.flags = 0; 622215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 623215976Sjmallett info.group_index = 0; 624215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 625215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 626215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 627215976Sjmallett info.func = __cvmx_error_display; 628215976Sjmallett info.user_info = (long) 629215976Sjmallett "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n" 630215976Sjmallett " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n"; 631215976Sjmallett fail |= cvmx_error_add(&info); 632215976Sjmallett 633215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 634215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 635215976Sjmallett info.status_mask = 1ull<<7 /* i0_rtout */; 636215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 637215976Sjmallett info.enable_mask = 1ull<<7 /* i0_rtout */; 638215976Sjmallett info.flags = 0; 639215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 640215976Sjmallett info.group_index = 0; 641215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 642215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 643215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 644215976Sjmallett info.func = __cvmx_error_display; 645215976Sjmallett info.user_info = (long) 646215976Sjmallett "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n" 647215976Sjmallett " read instructions.\n"; 648215976Sjmallett fail |= cvmx_error_add(&info); 649215976Sjmallett 650215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 651215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 652215976Sjmallett info.status_mask = 1ull<<8 /* i1_rtout */; 653215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 654215976Sjmallett info.enable_mask = 1ull<<8 /* i1_rtout */; 655215976Sjmallett info.flags = 0; 656215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 657215976Sjmallett info.group_index = 0; 658215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 659215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 660215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 661215976Sjmallett info.func = __cvmx_error_display; 662215976Sjmallett info.user_info = (long) 663215976Sjmallett "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n" 664215976Sjmallett " read instructions.\n"; 665215976Sjmallett fail |= cvmx_error_add(&info); 666215976Sjmallett 667215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 668215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 669215976Sjmallett info.status_mask = 1ull<<11 /* i0_overf */; 670215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 671215976Sjmallett info.enable_mask = 1ull<<11 /* i0_overf */; 672215976Sjmallett info.flags = 0; 673215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 674215976Sjmallett info.group_index = 0; 675215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 676215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 677215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 678215976Sjmallett info.func = __cvmx_error_display; 679215976Sjmallett info.user_info = (long) 680215976Sjmallett "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n" 681215976Sjmallett " doorbell count was set.\n"; 682215976Sjmallett fail |= cvmx_error_add(&info); 683215976Sjmallett 684215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 685215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 686215976Sjmallett info.status_mask = 1ull<<12 /* i1_overf */; 687215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 688215976Sjmallett info.enable_mask = 1ull<<12 /* i1_overf */; 689215976Sjmallett info.flags = 0; 690215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 691215976Sjmallett info.group_index = 0; 692215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 693215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 694215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 695215976Sjmallett info.func = __cvmx_error_display; 696215976Sjmallett info.user_info = (long) 697215976Sjmallett "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n" 698215976Sjmallett " doorbell count was set.\n"; 699215976Sjmallett fail |= cvmx_error_add(&info); 700215976Sjmallett 701215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 702215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 703215976Sjmallett info.status_mask = 1ull<<15 /* p0_rtout */; 704215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 705215976Sjmallett info.enable_mask = 1ull<<15 /* p0_rtout */; 706215976Sjmallett info.flags = 0; 707215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 708215976Sjmallett info.group_index = 0; 709215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 710215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 711215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 712215976Sjmallett info.func = __cvmx_error_display; 713215976Sjmallett info.user_info = (long) 714215976Sjmallett "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n" 715215976Sjmallett " read packet data.\n"; 716215976Sjmallett fail |= cvmx_error_add(&info); 717215976Sjmallett 718215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 719215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 720215976Sjmallett info.status_mask = 1ull<<16 /* p1_rtout */; 721215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 722215976Sjmallett info.enable_mask = 1ull<<16 /* p1_rtout */; 723215976Sjmallett info.flags = 0; 724215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 725215976Sjmallett info.group_index = 0; 726215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 727215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 728215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 729215976Sjmallett info.func = __cvmx_error_display; 730215976Sjmallett info.user_info = (long) 731215976Sjmallett "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n" 732215976Sjmallett " read packet data.\n"; 733215976Sjmallett fail |= cvmx_error_add(&info); 734215976Sjmallett 735215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 736215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 737215976Sjmallett info.status_mask = 1ull<<19 /* p0_perr */; 738215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 739215976Sjmallett info.enable_mask = 1ull<<19 /* p0_perr */; 740215976Sjmallett info.flags = 0; 741215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 742215976Sjmallett info.group_index = 0; 743215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 744215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 745215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 746215976Sjmallett info.func = __cvmx_error_display; 747215976Sjmallett info.user_info = (long) 748215976Sjmallett "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n" 749215976Sjmallett " data this bit may be set.\n"; 750215976Sjmallett fail |= cvmx_error_add(&info); 751215976Sjmallett 752215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 753215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 754215976Sjmallett info.status_mask = 1ull<<20 /* p1_perr */; 755215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 756215976Sjmallett info.enable_mask = 1ull<<20 /* p1_perr */; 757215976Sjmallett info.flags = 0; 758215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 759215976Sjmallett info.group_index = 0; 760215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 761215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 762215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 763215976Sjmallett info.func = __cvmx_error_display; 764215976Sjmallett info.user_info = (long) 765215976Sjmallett "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n" 766215976Sjmallett " data this bit may be set.\n"; 767215976Sjmallett fail |= cvmx_error_add(&info); 768215976Sjmallett 769215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 770215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 771215976Sjmallett info.status_mask = 1ull<<23 /* g0_rtout */; 772215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 773215976Sjmallett info.enable_mask = 1ull<<23 /* g0_rtout */; 774215976Sjmallett info.flags = 0; 775215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 776215976Sjmallett info.group_index = 0; 777215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 778215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 779215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 780215976Sjmallett info.func = __cvmx_error_display; 781215976Sjmallett info.user_info = (long) 782215976Sjmallett "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n" 783215976Sjmallett " read a gather list.\n"; 784215976Sjmallett fail |= cvmx_error_add(&info); 785215976Sjmallett 786215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 787215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 788215976Sjmallett info.status_mask = 1ull<<24 /* g1_rtout */; 789215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 790215976Sjmallett info.enable_mask = 1ull<<24 /* g1_rtout */; 791215976Sjmallett info.flags = 0; 792215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 793215976Sjmallett info.group_index = 0; 794215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 795215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 796215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 797215976Sjmallett info.func = __cvmx_error_display; 798215976Sjmallett info.user_info = (long) 799215976Sjmallett "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n" 800215976Sjmallett " read a gather list.\n"; 801215976Sjmallett fail |= cvmx_error_add(&info); 802215976Sjmallett 803215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 804215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 805215976Sjmallett info.status_mask = 1ull<<27 /* p0_pperr */; 806215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 807215976Sjmallett info.enable_mask = 1ull<<27 /* p0_pperr */; 808215976Sjmallett info.flags = 0; 809215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 810215976Sjmallett info.group_index = 0; 811215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 812215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 813215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 814215976Sjmallett info.func = __cvmx_error_display; 815215976Sjmallett info.user_info = (long) 816215976Sjmallett "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n" 817215976Sjmallett " pointer-pair, this bit may be set.\n"; 818215976Sjmallett fail |= cvmx_error_add(&info); 819215976Sjmallett 820215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 821215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 822215976Sjmallett info.status_mask = 1ull<<28 /* p1_pperr */; 823215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 824215976Sjmallett info.enable_mask = 1ull<<28 /* p1_pperr */; 825215976Sjmallett info.flags = 0; 826215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 827215976Sjmallett info.group_index = 0; 828215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 829215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 830215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 831215976Sjmallett info.func = __cvmx_error_display; 832215976Sjmallett info.user_info = (long) 833215976Sjmallett "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n" 834215976Sjmallett " pointer-pair, this bit may be set.\n"; 835215976Sjmallett fail |= cvmx_error_add(&info); 836215976Sjmallett 837215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 838215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 839215976Sjmallett info.status_mask = 1ull<<31 /* p0_ptout */; 840215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 841215976Sjmallett info.enable_mask = 1ull<<31 /* p0_ptout */; 842215976Sjmallett info.flags = 0; 843215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 844215976Sjmallett info.group_index = 0; 845215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 846215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 847215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 848215976Sjmallett info.func = __cvmx_error_display; 849215976Sjmallett info.user_info = (long) 850215976Sjmallett "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n" 851215976Sjmallett " pair.\n"; 852215976Sjmallett fail |= cvmx_error_add(&info); 853215976Sjmallett 854215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 855215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 856215976Sjmallett info.status_mask = 1ull<<32 /* p1_ptout */; 857215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 858215976Sjmallett info.enable_mask = 1ull<<32 /* p1_ptout */; 859215976Sjmallett info.flags = 0; 860215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 861215976Sjmallett info.group_index = 0; 862215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 863215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 864215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 865215976Sjmallett info.func = __cvmx_error_display; 866215976Sjmallett info.user_info = (long) 867215976Sjmallett "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n" 868215976Sjmallett " pair.\n"; 869215976Sjmallett fail |= cvmx_error_add(&info); 870215976Sjmallett 871215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 872215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 873215976Sjmallett info.status_mask = 1ull<<35 /* i0_pperr */; 874215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 875215976Sjmallett info.enable_mask = 1ull<<35 /* i0_pperr */; 876215976Sjmallett info.flags = 0; 877215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 878215976Sjmallett info.group_index = 0; 879215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 880215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 881215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 882215976Sjmallett info.func = __cvmx_error_display; 883215976Sjmallett info.user_info = (long) 884215976Sjmallett "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n" 885215976Sjmallett " this bit may be set.\n"; 886215976Sjmallett fail |= cvmx_error_add(&info); 887215976Sjmallett 888215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 889215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 890215976Sjmallett info.status_mask = 1ull<<36 /* i1_pperr */; 891215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 892215976Sjmallett info.enable_mask = 1ull<<36 /* i1_pperr */; 893215976Sjmallett info.flags = 0; 894215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 895215976Sjmallett info.group_index = 0; 896215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 897215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 898215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 899215976Sjmallett info.func = __cvmx_error_display; 900215976Sjmallett info.user_info = (long) 901215976Sjmallett "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n" 902215976Sjmallett " this bit may be set.\n"; 903215976Sjmallett fail |= cvmx_error_add(&info); 904215976Sjmallett 905215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 906215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 907215976Sjmallett info.status_mask = 1ull<<39 /* win_rto */; 908215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 909215976Sjmallett info.enable_mask = 1ull<<39 /* win_rto */; 910215976Sjmallett info.flags = 0; 911215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 912215976Sjmallett info.group_index = 0; 913215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 914215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 915215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 916215976Sjmallett info.func = __cvmx_error_display; 917215976Sjmallett info.user_info = (long) 918215976Sjmallett "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n"; 919215976Sjmallett fail |= cvmx_error_add(&info); 920215976Sjmallett 921215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 922215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 923215976Sjmallett info.status_mask = 1ull<<40 /* p_dperr */; 924215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 925215976Sjmallett info.enable_mask = 1ull<<40 /* p_dperr */; 926215976Sjmallett info.flags = 0; 927215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 928215976Sjmallett info.group_index = 0; 929215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 930215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 931215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 932215976Sjmallett info.func = __cvmx_error_display; 933215976Sjmallett info.user_info = (long) 934215976Sjmallett "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n" 935215976Sjmallett " from the PCI this bit may be set.\n"; 936215976Sjmallett fail |= cvmx_error_add(&info); 937215976Sjmallett 938215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 939215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 940215976Sjmallett info.status_mask = 1ull<<41 /* iobdma */; 941215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 942215976Sjmallett info.enable_mask = 1ull<<41 /* iobdma */; 943215976Sjmallett info.flags = 0; 944215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 945215976Sjmallett info.group_index = 0; 946215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 947215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 948215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 949215976Sjmallett info.func = __cvmx_error_display; 950215976Sjmallett info.user_info = (long) 951215976Sjmallett "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n"; 952215976Sjmallett fail |= cvmx_error_add(&info); 953215976Sjmallett 954215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 955215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 956215976Sjmallett info.status_mask = 1ull<<42 /* fcr_s_e */; 957215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 958215976Sjmallett info.enable_mask = 1ull<<42 /* fcr_s_e */; 959215976Sjmallett info.flags = 0; 960215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 961215976Sjmallett info.group_index = 0; 962215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 963215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 964215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 965215976Sjmallett info.func = __cvmx_error_display; 966215976Sjmallett info.user_info = (long) 967215976Sjmallett "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"; 968215976Sjmallett fail |= cvmx_error_add(&info); 969215976Sjmallett 970215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 971215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 972215976Sjmallett info.status_mask = 1ull<<43 /* fcr_a_f */; 973215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 974215976Sjmallett info.enable_mask = 1ull<<43 /* fcr_a_f */; 975215976Sjmallett info.flags = 0; 976215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 977215976Sjmallett info.group_index = 0; 978215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 979215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 980215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 981215976Sjmallett info.func = __cvmx_error_display; 982215976Sjmallett info.user_info = (long) 983215976Sjmallett "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"; 984215976Sjmallett fail |= cvmx_error_add(&info); 985215976Sjmallett 986215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 987215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 988215976Sjmallett info.status_mask = 1ull<<44 /* pcr_s_e */; 989215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 990215976Sjmallett info.enable_mask = 1ull<<44 /* pcr_s_e */; 991215976Sjmallett info.flags = 0; 992215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 993215976Sjmallett info.group_index = 0; 994215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 995215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 996215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 997215976Sjmallett info.func = __cvmx_error_display; 998215976Sjmallett info.user_info = (long) 999215976Sjmallett "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"; 1000215976Sjmallett fail |= cvmx_error_add(&info); 1001215976Sjmallett 1002215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1003215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1004215976Sjmallett info.status_mask = 1ull<<45 /* pcr_a_f */; 1005215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1006215976Sjmallett info.enable_mask = 1ull<<45 /* pcr_a_f */; 1007215976Sjmallett info.flags = 0; 1008215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1009215976Sjmallett info.group_index = 0; 1010215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1011215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1012215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1013215976Sjmallett info.func = __cvmx_error_display; 1014215976Sjmallett info.user_info = (long) 1015215976Sjmallett "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"; 1016215976Sjmallett fail |= cvmx_error_add(&info); 1017215976Sjmallett 1018215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1019215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1020215976Sjmallett info.status_mask = 1ull<<46 /* q2_s_e */; 1021215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1022215976Sjmallett info.enable_mask = 1ull<<46 /* q2_s_e */; 1023215976Sjmallett info.flags = 0; 1024215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1025215976Sjmallett info.group_index = 0; 1026215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1027215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1028215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1029215976Sjmallett info.func = __cvmx_error_display; 1030215976Sjmallett info.user_info = (long) 1031215976Sjmallett "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"; 1032215976Sjmallett fail |= cvmx_error_add(&info); 1033215976Sjmallett 1034215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1035215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1036215976Sjmallett info.status_mask = 1ull<<47 /* q2_a_f */; 1037215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1038215976Sjmallett info.enable_mask = 1ull<<47 /* q2_a_f */; 1039215976Sjmallett info.flags = 0; 1040215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1041215976Sjmallett info.group_index = 0; 1042215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1043215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1044215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1045215976Sjmallett info.func = __cvmx_error_display; 1046215976Sjmallett info.user_info = (long) 1047215976Sjmallett "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"; 1048215976Sjmallett fail |= cvmx_error_add(&info); 1049215976Sjmallett 1050215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1051215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1052215976Sjmallett info.status_mask = 1ull<<48 /* q3_s_e */; 1053215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1054215976Sjmallett info.enable_mask = 1ull<<48 /* q3_s_e */; 1055215976Sjmallett info.flags = 0; 1056215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1057215976Sjmallett info.group_index = 0; 1058215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1059215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1060215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1061215976Sjmallett info.func = __cvmx_error_display; 1062215976Sjmallett info.user_info = (long) 1063215976Sjmallett "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"; 1064215976Sjmallett fail |= cvmx_error_add(&info); 1065215976Sjmallett 1066215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1067215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1068215976Sjmallett info.status_mask = 1ull<<49 /* q3_a_f */; 1069215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1070215976Sjmallett info.enable_mask = 1ull<<49 /* q3_a_f */; 1071215976Sjmallett info.flags = 0; 1072215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1073215976Sjmallett info.group_index = 0; 1074215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1075215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1076215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1077215976Sjmallett info.func = __cvmx_error_display; 1078215976Sjmallett info.user_info = (long) 1079215976Sjmallett "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"; 1080215976Sjmallett fail |= cvmx_error_add(&info); 1081215976Sjmallett 1082215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1083215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1084215976Sjmallett info.status_mask = 1ull<<50 /* com_s_e */; 1085215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1086215976Sjmallett info.enable_mask = 1ull<<50 /* com_s_e */; 1087215976Sjmallett info.flags = 0; 1088215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1089215976Sjmallett info.group_index = 0; 1090215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1091215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1092215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1093215976Sjmallett info.func = __cvmx_error_display; 1094215976Sjmallett info.user_info = (long) 1095215976Sjmallett "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"; 1096215976Sjmallett fail |= cvmx_error_add(&info); 1097215976Sjmallett 1098215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1099215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1100215976Sjmallett info.status_mask = 1ull<<51 /* com_a_f */; 1101215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1102215976Sjmallett info.enable_mask = 1ull<<51 /* com_a_f */; 1103215976Sjmallett info.flags = 0; 1104215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1105215976Sjmallett info.group_index = 0; 1106215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1107215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1108215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1109215976Sjmallett info.func = __cvmx_error_display; 1110215976Sjmallett info.user_info = (long) 1111215976Sjmallett "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"; 1112215976Sjmallett fail |= cvmx_error_add(&info); 1113215976Sjmallett 1114215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1115215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1116215976Sjmallett info.status_mask = 1ull<<52 /* pnc_s_e */; 1117215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1118215976Sjmallett info.enable_mask = 1ull<<52 /* pnc_s_e */; 1119215976Sjmallett info.flags = 0; 1120215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1121215976Sjmallett info.group_index = 0; 1122215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1123215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1124215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1125215976Sjmallett info.func = __cvmx_error_display; 1126215976Sjmallett info.user_info = (long) 1127215976Sjmallett "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"; 1128215976Sjmallett fail |= cvmx_error_add(&info); 1129215976Sjmallett 1130215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1131215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1132215976Sjmallett info.status_mask = 1ull<<53 /* pnc_a_f */; 1133215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1134215976Sjmallett info.enable_mask = 1ull<<53 /* pnc_a_f */; 1135215976Sjmallett info.flags = 0; 1136215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1137215976Sjmallett info.group_index = 0; 1138215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1139215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1140215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1141215976Sjmallett info.func = __cvmx_error_display; 1142215976Sjmallett info.user_info = (long) 1143215976Sjmallett "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"; 1144215976Sjmallett fail |= cvmx_error_add(&info); 1145215976Sjmallett 1146215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1147215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1148215976Sjmallett info.status_mask = 1ull<<54 /* rwx_s_e */; 1149215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1150215976Sjmallett info.enable_mask = 1ull<<54 /* rwx_s_e */; 1151215976Sjmallett info.flags = 0; 1152215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1153215976Sjmallett info.group_index = 0; 1154215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1155215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1156215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1157215976Sjmallett info.func = __cvmx_error_display; 1158215976Sjmallett info.user_info = (long) 1159215976Sjmallett "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"; 1160215976Sjmallett fail |= cvmx_error_add(&info); 1161215976Sjmallett 1162215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1163215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1164215976Sjmallett info.status_mask = 1ull<<55 /* rdx_s_e */; 1165215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1166215976Sjmallett info.enable_mask = 1ull<<55 /* rdx_s_e */; 1167215976Sjmallett info.flags = 0; 1168215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1169215976Sjmallett info.group_index = 0; 1170215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1171215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1172215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1173215976Sjmallett info.func = __cvmx_error_display; 1174215976Sjmallett info.user_info = (long) 1175215976Sjmallett "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"; 1176215976Sjmallett fail |= cvmx_error_add(&info); 1177215976Sjmallett 1178215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1179215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1180215976Sjmallett info.status_mask = 1ull<<56 /* pcf_p_e */; 1181215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1182215976Sjmallett info.enable_mask = 1ull<<56 /* pcf_p_e */; 1183215976Sjmallett info.flags = 0; 1184215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1185215976Sjmallett info.group_index = 0; 1186215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1187215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1188215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1189215976Sjmallett info.func = __cvmx_error_display; 1190215976Sjmallett info.user_info = (long) 1191215976Sjmallett "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"; 1192215976Sjmallett fail |= cvmx_error_add(&info); 1193215976Sjmallett 1194215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1195215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1196215976Sjmallett info.status_mask = 1ull<<57 /* pcf_p_f */; 1197215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1198215976Sjmallett info.enable_mask = 1ull<<57 /* pcf_p_f */; 1199215976Sjmallett info.flags = 0; 1200215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1201215976Sjmallett info.group_index = 0; 1202215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1203215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1204215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1205215976Sjmallett info.func = __cvmx_error_display; 1206215976Sjmallett info.user_info = (long) 1207215976Sjmallett "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"; 1208215976Sjmallett fail |= cvmx_error_add(&info); 1209215976Sjmallett 1210215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1211215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1212215976Sjmallett info.status_mask = 1ull<<58 /* pdf_p_e */; 1213215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1214215976Sjmallett info.enable_mask = 1ull<<58 /* pdf_p_e */; 1215215976Sjmallett info.flags = 0; 1216215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1217215976Sjmallett info.group_index = 0; 1218215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1219215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1220215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1221215976Sjmallett info.func = __cvmx_error_display; 1222215976Sjmallett info.user_info = (long) 1223215976Sjmallett "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"; 1224215976Sjmallett fail |= cvmx_error_add(&info); 1225215976Sjmallett 1226215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1227215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1228215976Sjmallett info.status_mask = 1ull<<59 /* pdf_p_f */; 1229215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1230215976Sjmallett info.enable_mask = 1ull<<59 /* pdf_p_f */; 1231215976Sjmallett info.flags = 0; 1232215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1233215976Sjmallett info.group_index = 0; 1234215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1235215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1236215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1237215976Sjmallett info.func = __cvmx_error_display; 1238215976Sjmallett info.user_info = (long) 1239215976Sjmallett "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"; 1240215976Sjmallett fail |= cvmx_error_add(&info); 1241215976Sjmallett 1242215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1243215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1244215976Sjmallett info.status_mask = 1ull<<60 /* q1_s_e */; 1245215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1246215976Sjmallett info.enable_mask = 1ull<<60 /* q1_s_e */; 1247215976Sjmallett info.flags = 0; 1248215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1249215976Sjmallett info.group_index = 0; 1250215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1251215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1252215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1253215976Sjmallett info.func = __cvmx_error_display; 1254215976Sjmallett info.user_info = (long) 1255215976Sjmallett "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"; 1256215976Sjmallett fail |= cvmx_error_add(&info); 1257215976Sjmallett 1258215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1259215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1260215976Sjmallett info.status_mask = 1ull<<61 /* q1_a_f */; 1261215976Sjmallett info.enable_addr = CVMX_NPI_INT_ENB; 1262215976Sjmallett info.enable_mask = 1ull<<61 /* q1_a_f */; 1263215976Sjmallett info.flags = 0; 1264215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1265215976Sjmallett info.group_index = 0; 1266215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1267215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1268215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1269215976Sjmallett info.func = __cvmx_error_display; 1270215976Sjmallett info.user_info = (long) 1271215976Sjmallett "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"; 1272215976Sjmallett fail |= cvmx_error_add(&info); 1273215976Sjmallett 1274215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1275215976Sjmallett info.status_addr = CVMX_NPI_INT_SUM; 1276215976Sjmallett info.status_mask = 0; 1277215976Sjmallett info.enable_addr = 0; 1278215976Sjmallett info.enable_mask = 0; 1279215976Sjmallett info.flags = 0; 1280215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1281215976Sjmallett info.group_index = 0; 1282215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1283215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1284215976Sjmallett info.parent.status_mask = 1ull<<3 /* npi */; 1285215976Sjmallett info.func = __cvmx_error_decode; 1286215976Sjmallett info.user_info = 0; 1287215976Sjmallett fail |= cvmx_error_add(&info); 1288215976Sjmallett 1289215976Sjmallett /* CVMX_NPI_PCI_INT_SUM2 */ 1290215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1291215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1292215976Sjmallett info.status_mask = 1ull<<0 /* tr_wabt */; 1293215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1294215976Sjmallett info.enable_mask = 1ull<<0 /* rtr_wabt */; 1295215976Sjmallett info.flags = 0; 1296215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1297215976Sjmallett info.group_index = 0; 1298215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1299215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1300215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1301215976Sjmallett info.func = __cvmx_error_display; 1302215976Sjmallett info.user_info = (long) 1303215976Sjmallett "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n"; 1304215976Sjmallett fail |= cvmx_error_add(&info); 1305215976Sjmallett 1306215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1307215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1308215976Sjmallett info.status_mask = 1ull<<1 /* mr_wabt */; 1309215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1310215976Sjmallett info.enable_mask = 1ull<<1 /* rmr_wabt */; 1311215976Sjmallett info.flags = 0; 1312215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1313215976Sjmallett info.group_index = 0; 1314215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1315215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1316215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1317215976Sjmallett info.func = __cvmx_error_display; 1318215976Sjmallett info.user_info = (long) 1319215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n"; 1320215976Sjmallett fail |= cvmx_error_add(&info); 1321215976Sjmallett 1322215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1323215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1324215976Sjmallett info.status_mask = 1ull<<2 /* mr_wtto */; 1325215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1326215976Sjmallett info.enable_mask = 1ull<<2 /* rmr_wtto */; 1327215976Sjmallett info.flags = 0; 1328215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1329215976Sjmallett info.group_index = 0; 1330215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1331215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1332215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1333215976Sjmallett info.func = __cvmx_error_display; 1334215976Sjmallett info.user_info = (long) 1335215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n"; 1336215976Sjmallett fail |= cvmx_error_add(&info); 1337215976Sjmallett 1338215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1339215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1340215976Sjmallett info.status_mask = 1ull<<3 /* tr_abt */; 1341215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1342215976Sjmallett info.enable_mask = 1ull<<3 /* rtr_abt */; 1343215976Sjmallett info.flags = 0; 1344215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1345215976Sjmallett info.group_index = 0; 1346215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1347215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1348215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1349215976Sjmallett info.func = __cvmx_error_display; 1350215976Sjmallett info.user_info = (long) 1351215976Sjmallett "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n"; 1352215976Sjmallett fail |= cvmx_error_add(&info); 1353215976Sjmallett 1354215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1355215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1356215976Sjmallett info.status_mask = 1ull<<4 /* mr_abt */; 1357215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1358215976Sjmallett info.enable_mask = 1ull<<4 /* rmr_abt */; 1359215976Sjmallett info.flags = 0; 1360215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1361215976Sjmallett info.group_index = 0; 1362215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1363215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1364215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1365215976Sjmallett info.func = __cvmx_error_display; 1366215976Sjmallett info.user_info = (long) 1367215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n"; 1368215976Sjmallett fail |= cvmx_error_add(&info); 1369215976Sjmallett 1370215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1371215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1372215976Sjmallett info.status_mask = 1ull<<5 /* mr_tto */; 1373215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1374215976Sjmallett info.enable_mask = 1ull<<5 /* rmr_tto */; 1375215976Sjmallett info.flags = 0; 1376215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1377215976Sjmallett info.group_index = 0; 1378215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1379215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1380215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1381215976Sjmallett info.func = __cvmx_error_display; 1382215976Sjmallett info.user_info = (long) 1383215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n"; 1384215976Sjmallett fail |= cvmx_error_add(&info); 1385215976Sjmallett 1386215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1387215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1388215976Sjmallett info.status_mask = 1ull<<6 /* msi_per */; 1389215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1390215976Sjmallett info.enable_mask = 1ull<<6 /* rmsi_per */; 1391215976Sjmallett info.flags = 0; 1392215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1393215976Sjmallett info.group_index = 0; 1394215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1395215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1396215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1397215976Sjmallett info.func = __cvmx_error_display; 1398215976Sjmallett info.user_info = (long) 1399215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n"; 1400215976Sjmallett fail |= cvmx_error_add(&info); 1401215976Sjmallett 1402215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1403215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1404215976Sjmallett info.status_mask = 1ull<<7 /* msi_tabt */; 1405215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1406215976Sjmallett info.enable_mask = 1ull<<7 /* rmsi_tabt */; 1407215976Sjmallett info.flags = 0; 1408215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1409215976Sjmallett info.group_index = 0; 1410215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1411215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1412215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1413215976Sjmallett info.func = __cvmx_error_display; 1414215976Sjmallett info.user_info = (long) 1415215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n"; 1416215976Sjmallett fail |= cvmx_error_add(&info); 1417215976Sjmallett 1418215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1419215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1420215976Sjmallett info.status_mask = 1ull<<8 /* msi_mabt */; 1421215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1422215976Sjmallett info.enable_mask = 1ull<<8 /* rmsi_mabt */; 1423215976Sjmallett info.flags = 0; 1424215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1425215976Sjmallett info.group_index = 0; 1426215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1427215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1428215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1429215976Sjmallett info.func = __cvmx_error_display; 1430215976Sjmallett info.user_info = (long) 1431215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n"; 1432215976Sjmallett fail |= cvmx_error_add(&info); 1433215976Sjmallett 1434215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1435215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1436215976Sjmallett info.status_mask = 1ull<<9 /* msc_msg */; 1437215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1438215976Sjmallett info.enable_mask = 1ull<<9 /* rmsc_msg */; 1439215976Sjmallett info.flags = 0; 1440215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1441215976Sjmallett info.group_index = 0; 1442215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1443215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1444215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1445215976Sjmallett info.func = __cvmx_error_display; 1446215976Sjmallett info.user_info = (long) 1447215976Sjmallett "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n"; 1448215976Sjmallett fail |= cvmx_error_add(&info); 1449215976Sjmallett 1450215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1451215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1452215976Sjmallett info.status_mask = 1ull<<10 /* tsr_abt */; 1453215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1454215976Sjmallett info.enable_mask = 1ull<<10 /* rtsr_abt */; 1455215976Sjmallett info.flags = 0; 1456215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1457215976Sjmallett info.group_index = 0; 1458215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1459215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1460215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1461215976Sjmallett info.func = __cvmx_error_display; 1462215976Sjmallett info.user_info = (long) 1463215976Sjmallett "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n"; 1464215976Sjmallett fail |= cvmx_error_add(&info); 1465215976Sjmallett 1466215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1467215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1468215976Sjmallett info.status_mask = 1ull<<11 /* serr */; 1469215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1470215976Sjmallett info.enable_mask = 1ull<<11 /* rserr */; 1471215976Sjmallett info.flags = 0; 1472215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1473215976Sjmallett info.group_index = 0; 1474215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1475215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1476215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1477215976Sjmallett info.func = __cvmx_error_display; 1478215976Sjmallett info.user_info = (long) 1479215976Sjmallett "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n"; 1480215976Sjmallett fail |= cvmx_error_add(&info); 1481215976Sjmallett 1482215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1483215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1484215976Sjmallett info.status_mask = 1ull<<12 /* aperr */; 1485215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1486215976Sjmallett info.enable_mask = 1ull<<12 /* raperr */; 1487215976Sjmallett info.flags = 0; 1488215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1489215976Sjmallett info.group_index = 0; 1490215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1491215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1492215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1493215976Sjmallett info.func = __cvmx_error_display; 1494215976Sjmallett info.user_info = (long) 1495215976Sjmallett "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n"; 1496215976Sjmallett fail |= cvmx_error_add(&info); 1497215976Sjmallett 1498215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1499215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1500215976Sjmallett info.status_mask = 1ull<<13 /* dperr */; 1501215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1502215976Sjmallett info.enable_mask = 1ull<<13 /* rdperr */; 1503215976Sjmallett info.flags = 0; 1504215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1505215976Sjmallett info.group_index = 0; 1506215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1507215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1508215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1509215976Sjmallett info.func = __cvmx_error_display; 1510215976Sjmallett info.user_info = (long) 1511215976Sjmallett "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n"; 1512215976Sjmallett fail |= cvmx_error_add(&info); 1513215976Sjmallett 1514215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1515215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1516215976Sjmallett info.status_mask = 1ull<<14 /* ill_rwr */; 1517215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1518215976Sjmallett info.enable_mask = 1ull<<14 /* ill_rwr */; 1519215976Sjmallett info.flags = 0; 1520215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1521215976Sjmallett info.group_index = 0; 1522215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1523215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1524215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1525215976Sjmallett info.func = __cvmx_error_display; 1526215976Sjmallett info.user_info = (long) 1527215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n"; 1528215976Sjmallett fail |= cvmx_error_add(&info); 1529215976Sjmallett 1530215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1531215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1532215976Sjmallett info.status_mask = 1ull<<15 /* ill_rrd */; 1533215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1534215976Sjmallett info.enable_mask = 1ull<<15 /* ill_rrd */; 1535215976Sjmallett info.flags = 0; 1536215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1537215976Sjmallett info.group_index = 0; 1538215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1539215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1540215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1541215976Sjmallett info.func = __cvmx_error_display; 1542215976Sjmallett info.user_info = (long) 1543215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n"; 1544215976Sjmallett fail |= cvmx_error_add(&info); 1545215976Sjmallett 1546215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1547215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1548215976Sjmallett info.status_mask = 1ull<<31 /* win_wr */; 1549215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1550215976Sjmallett info.enable_mask = 1ull<<31 /* win_wr */; 1551215976Sjmallett info.flags = 0; 1552215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1553215976Sjmallett info.group_index = 0; 1554215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1555215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1556215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1557215976Sjmallett info.func = __cvmx_error_display; 1558215976Sjmallett info.user_info = (long) 1559215976Sjmallett "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n" 1560215976Sjmallett " Read-Address Register took place.\n"; 1561215976Sjmallett fail |= cvmx_error_add(&info); 1562215976Sjmallett 1563215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1564215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1565215976Sjmallett info.status_mask = 1ull<<32 /* ill_wr */; 1566215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1567215976Sjmallett info.enable_mask = 1ull<<32 /* ill_wr */; 1568215976Sjmallett info.flags = 0; 1569215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1570215976Sjmallett info.group_index = 0; 1571215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1572215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1573215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1574215976Sjmallett info.func = __cvmx_error_display; 1575215976Sjmallett info.user_info = (long) 1576215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n" 1577215976Sjmallett " when the mem area is disabled.\n"; 1578215976Sjmallett fail |= cvmx_error_add(&info); 1579215976Sjmallett 1580215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1581215976Sjmallett info.status_addr = CVMX_NPI_PCI_INT_SUM2; 1582215976Sjmallett info.status_mask = 1ull<<33 /* ill_rd */; 1583215976Sjmallett info.enable_addr = CVMX_NPI_PCI_INT_ENB2; 1584215976Sjmallett info.enable_mask = 1ull<<33 /* ill_rd */; 1585215976Sjmallett info.flags = 0; 1586215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 1587215976Sjmallett info.group_index = 0; 1588215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1589215976Sjmallett info.parent.status_addr = CVMX_NPI_INT_SUM; 1590215976Sjmallett info.parent.status_mask = 1ull<<2 /* pci_rsl */; 1591215976Sjmallett info.func = __cvmx_error_display; 1592215976Sjmallett info.user_info = (long) 1593215976Sjmallett "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n" 1594215976Sjmallett " when the mem area is disabled.\n"; 1595215976Sjmallett fail |= cvmx_error_add(&info); 1596215976Sjmallett 1597215976Sjmallett /* CVMX_GMXX_BAD_REG(0) */ 1598215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1599215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1600215976Sjmallett info.status_mask = 0x7ull<<2 /* out_ovr */; 1601215976Sjmallett info.enable_addr = 0; 1602215976Sjmallett info.enable_mask = 0; 1603215976Sjmallett info.flags = 0; 1604215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1605215976Sjmallett info.group_index = 0; 1606215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1607215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1608215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1609215976Sjmallett info.func = __cvmx_error_display; 1610215976Sjmallett info.user_info = (long) 1611215976Sjmallett "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 1612215976Sjmallett fail |= cvmx_error_add(&info); 1613215976Sjmallett 1614215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1615215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1616215976Sjmallett info.status_mask = 0x7ull<<22 /* loststat */; 1617215976Sjmallett info.enable_addr = 0; 1618215976Sjmallett info.enable_mask = 0; 1619215976Sjmallett info.flags = 0; 1620215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1621215976Sjmallett info.group_index = 0; 1622215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1623215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1624215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1625215976Sjmallett info.func = __cvmx_error_display; 1626215976Sjmallett info.user_info = (long) 1627215976Sjmallett "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n" 1628215976Sjmallett " TX Stats are corrupted\n"; 1629215976Sjmallett fail |= cvmx_error_add(&info); 1630215976Sjmallett 1631215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1632215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1633215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 1634215976Sjmallett info.enable_addr = 0; 1635215976Sjmallett info.enable_mask = 0; 1636215976Sjmallett info.flags = 0; 1637215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1638215976Sjmallett info.group_index = 0; 1639215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1640215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1641215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1642215976Sjmallett info.func = __cvmx_error_display; 1643215976Sjmallett info.user_info = (long) 1644215976Sjmallett "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"; 1645215976Sjmallett fail |= cvmx_error_add(&info); 1646215976Sjmallett 1647215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1648215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 1649215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 1650215976Sjmallett info.enable_addr = 0; 1651215976Sjmallett info.enable_mask = 0; 1652215976Sjmallett info.flags = 0; 1653215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1654215976Sjmallett info.group_index = 0; 1655215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1656215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1657215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1658215976Sjmallett info.func = __cvmx_error_display; 1659215976Sjmallett info.user_info = (long) 1660215976Sjmallett "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 1661215976Sjmallett fail |= cvmx_error_add(&info); 1662215976Sjmallett 1663215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,0) */ 1664215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1665215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1666215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1667215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1668215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1669215976Sjmallett info.flags = 0; 1670215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1671215976Sjmallett info.group_index = 0; 1672215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1673215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1674215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1675215976Sjmallett info.func = __cvmx_error_display; 1676215976Sjmallett info.user_info = (long) 1677215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n"; 1678215976Sjmallett fail |= cvmx_error_add(&info); 1679215976Sjmallett 1680215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1681215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1682215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 1683215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1684215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 1685215976Sjmallett info.flags = 0; 1686215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1687215976Sjmallett info.group_index = 0; 1688215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1689215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1690215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1691215976Sjmallett info.func = __cvmx_error_display; 1692215976Sjmallett info.user_info = (long) 1693215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n"; 1694215976Sjmallett fail |= cvmx_error_add(&info); 1695215976Sjmallett 1696215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1697215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1698215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 1699215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1700215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 1701215976Sjmallett info.flags = 0; 1702215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1703215976Sjmallett info.group_index = 0; 1704215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1705215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1706215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1707215976Sjmallett info.func = __cvmx_error_display; 1708215976Sjmallett info.user_info = (long) 1709215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n"; 1710215976Sjmallett fail |= cvmx_error_add(&info); 1711215976Sjmallett 1712215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1713215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1714215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 1715215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1716215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 1717215976Sjmallett info.flags = 0; 1718215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1719215976Sjmallett info.group_index = 0; 1720215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1721215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1722215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1723215976Sjmallett info.func = __cvmx_error_display; 1724215976Sjmallett info.user_info = (long) 1725215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n"; 1726215976Sjmallett fail |= cvmx_error_add(&info); 1727215976Sjmallett 1728215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1729215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1730215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1731215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1732215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1733215976Sjmallett info.flags = 0; 1734215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1735215976Sjmallett info.group_index = 0; 1736215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1737215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1738215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1739215976Sjmallett info.func = __cvmx_error_display; 1740215976Sjmallett info.user_info = (long) 1741215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n"; 1742215976Sjmallett fail |= cvmx_error_add(&info); 1743215976Sjmallett 1744215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1745215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1746215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 1747215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1748215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 1749215976Sjmallett info.flags = 0; 1750215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1751215976Sjmallett info.group_index = 0; 1752215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1753215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1754215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1755215976Sjmallett info.func = __cvmx_error_display; 1756215976Sjmallett info.user_info = (long) 1757215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 1758215976Sjmallett fail |= cvmx_error_add(&info); 1759215976Sjmallett 1760215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1761215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 1762215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1763215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 1764215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1765215976Sjmallett info.flags = 0; 1766215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1767215976Sjmallett info.group_index = 0; 1768215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1769215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1770215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1771215976Sjmallett info.func = __cvmx_error_display; 1772215976Sjmallett info.user_info = (long) 1773215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1774215976Sjmallett " This interrupt should never assert\n"; 1775215976Sjmallett fail |= cvmx_error_add(&info); 1776215976Sjmallett 1777215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,0) */ 1778215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1779215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1780215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1781215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1782215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1783215976Sjmallett info.flags = 0; 1784215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1785215976Sjmallett info.group_index = 1; 1786215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1787215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1788215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1789215976Sjmallett info.func = __cvmx_error_display; 1790215976Sjmallett info.user_info = (long) 1791215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n"; 1792215976Sjmallett fail |= cvmx_error_add(&info); 1793215976Sjmallett 1794215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1795215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1796215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 1797215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1798215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 1799215976Sjmallett info.flags = 0; 1800215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1801215976Sjmallett info.group_index = 1; 1802215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1803215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1804215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1805215976Sjmallett info.func = __cvmx_error_display; 1806215976Sjmallett info.user_info = (long) 1807215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n"; 1808215976Sjmallett fail |= cvmx_error_add(&info); 1809215976Sjmallett 1810215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1811215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1812215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 1813215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1814215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 1815215976Sjmallett info.flags = 0; 1816215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1817215976Sjmallett info.group_index = 1; 1818215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1819215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1820215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1821215976Sjmallett info.func = __cvmx_error_display; 1822215976Sjmallett info.user_info = (long) 1823215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n"; 1824215976Sjmallett fail |= cvmx_error_add(&info); 1825215976Sjmallett 1826215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1827215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1828215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 1829215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1830215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 1831215976Sjmallett info.flags = 0; 1832215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1833215976Sjmallett info.group_index = 1; 1834215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1835215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1836215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1837215976Sjmallett info.func = __cvmx_error_display; 1838215976Sjmallett info.user_info = (long) 1839215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n"; 1840215976Sjmallett fail |= cvmx_error_add(&info); 1841215976Sjmallett 1842215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1843215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1844215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1845215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1846215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1847215976Sjmallett info.flags = 0; 1848215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1849215976Sjmallett info.group_index = 1; 1850215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1851215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1852215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1853215976Sjmallett info.func = __cvmx_error_display; 1854215976Sjmallett info.user_info = (long) 1855215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n"; 1856215976Sjmallett fail |= cvmx_error_add(&info); 1857215976Sjmallett 1858215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1859215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1860215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 1861215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1862215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 1863215976Sjmallett info.flags = 0; 1864215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1865215976Sjmallett info.group_index = 1; 1866215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1867215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1868215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1869215976Sjmallett info.func = __cvmx_error_display; 1870215976Sjmallett info.user_info = (long) 1871215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 1872215976Sjmallett fail |= cvmx_error_add(&info); 1873215976Sjmallett 1874215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1875215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 1876215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1877215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 1878215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1879215976Sjmallett info.flags = 0; 1880215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1881215976Sjmallett info.group_index = 1; 1882215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1883215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1884215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1885215976Sjmallett info.func = __cvmx_error_display; 1886215976Sjmallett info.user_info = (long) 1887215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n" 1888215976Sjmallett " This interrupt should never assert\n"; 1889215976Sjmallett fail |= cvmx_error_add(&info); 1890215976Sjmallett 1891215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,0) */ 1892215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1893215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1894215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 1895215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1896215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 1897215976Sjmallett info.flags = 0; 1898215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1899215976Sjmallett info.group_index = 2; 1900215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1901215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1902215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1903215976Sjmallett info.func = __cvmx_error_display; 1904215976Sjmallett info.user_info = (long) 1905215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n"; 1906215976Sjmallett fail |= cvmx_error_add(&info); 1907215976Sjmallett 1908215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1909215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1910215976Sjmallett info.status_mask = 1ull<<2 /* maxerr */; 1911215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1912215976Sjmallett info.enable_mask = 1ull<<2 /* maxerr */; 1913215976Sjmallett info.flags = 0; 1914215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1915215976Sjmallett info.group_index = 2; 1916215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1917215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1918215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1919215976Sjmallett info.func = __cvmx_error_display; 1920215976Sjmallett info.user_info = (long) 1921215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n"; 1922215976Sjmallett fail |= cvmx_error_add(&info); 1923215976Sjmallett 1924215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1925215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1926215976Sjmallett info.status_mask = 1ull<<5 /* alnerr */; 1927215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1928215976Sjmallett info.enable_mask = 1ull<<5 /* alnerr */; 1929215976Sjmallett info.flags = 0; 1930215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1931215976Sjmallett info.group_index = 2; 1932215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1933215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1934215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1935215976Sjmallett info.func = __cvmx_error_display; 1936215976Sjmallett info.user_info = (long) 1937215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n"; 1938215976Sjmallett fail |= cvmx_error_add(&info); 1939215976Sjmallett 1940215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1941215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1942215976Sjmallett info.status_mask = 1ull<<6 /* lenerr */; 1943215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1944215976Sjmallett info.enable_mask = 1ull<<6 /* lenerr */; 1945215976Sjmallett info.flags = 0; 1946215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1947215976Sjmallett info.group_index = 2; 1948215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1949215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1950215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1951215976Sjmallett info.func = __cvmx_error_display; 1952215976Sjmallett info.user_info = (long) 1953215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n"; 1954215976Sjmallett fail |= cvmx_error_add(&info); 1955215976Sjmallett 1956215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1957215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1958215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 1959215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1960215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 1961215976Sjmallett info.flags = 0; 1962215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1963215976Sjmallett info.group_index = 2; 1964215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1965215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1966215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1967215976Sjmallett info.func = __cvmx_error_display; 1968215976Sjmallett info.user_info = (long) 1969215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n"; 1970215976Sjmallett fail |= cvmx_error_add(&info); 1971215976Sjmallett 1972215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1973215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1974215976Sjmallett info.status_mask = 1ull<<9 /* niberr */; 1975215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1976215976Sjmallett info.enable_mask = 1ull<<9 /* niberr */; 1977215976Sjmallett info.flags = 0; 1978215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1979215976Sjmallett info.group_index = 2; 1980215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1981215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1982215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1983215976Sjmallett info.func = __cvmx_error_display; 1984215976Sjmallett info.user_info = (long) 1985215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n"; 1986215976Sjmallett fail |= cvmx_error_add(&info); 1987215976Sjmallett 1988215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1989215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 1990215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 1991215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 1992215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 1993215976Sjmallett info.flags = 0; 1994215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1995215976Sjmallett info.group_index = 2; 1996215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1997215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 1998215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 1999215976Sjmallett info.func = __cvmx_error_display; 2000215976Sjmallett info.user_info = (long) 2001215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n" 2002215976Sjmallett " This interrupt should never assert\n"; 2003215976Sjmallett fail |= cvmx_error_add(&info); 2004215976Sjmallett 2005215976Sjmallett /* CVMX_GMXX_TX_INT_REG(0) */ 2006215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2007215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 2008215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 2009215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 2010215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 2011215976Sjmallett info.flags = 0; 2012215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2013215976Sjmallett info.group_index = 0; 2014215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2015215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2016215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2017215976Sjmallett info.func = __cvmx_error_display; 2018215976Sjmallett info.user_info = (long) 2019215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 2020215976Sjmallett fail |= cvmx_error_add(&info); 2021215976Sjmallett 2022215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2023215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 2024215976Sjmallett info.status_mask = 0x7ull<<2 /* undflw */; 2025215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 2026215976Sjmallett info.enable_mask = 0x7ull<<2 /* undflw */; 2027215976Sjmallett info.flags = 0; 2028215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2029215976Sjmallett info.group_index = 0; 2030215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2031215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2032215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 2033215976Sjmallett info.func = __cvmx_error_display; 2034215976Sjmallett info.user_info = (long) 2035215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n"; 2036215976Sjmallett fail |= cvmx_error_add(&info); 2037215976Sjmallett 2038215976Sjmallett /* CVMX_MIO_BOOT_ERR */ 2039215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2040215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 2041215976Sjmallett info.status_mask = 1ull<<0 /* adr_err */; 2042215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 2043215976Sjmallett info.enable_mask = 1ull<<0 /* adr_int */; 2044215976Sjmallett info.flags = 0; 2045215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2046215976Sjmallett info.group_index = 0; 2047215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2048215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2049215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 2050215976Sjmallett info.func = __cvmx_error_display; 2051215976Sjmallett info.user_info = (long) 2052215976Sjmallett "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n"; 2053215976Sjmallett fail |= cvmx_error_add(&info); 2054215976Sjmallett 2055215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2056215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 2057215976Sjmallett info.status_mask = 1ull<<1 /* wait_err */; 2058215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 2059215976Sjmallett info.enable_mask = 1ull<<1 /* wait_int */; 2060215976Sjmallett info.flags = 0; 2061215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2062215976Sjmallett info.group_index = 0; 2063215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2064215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2065215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 2066215976Sjmallett info.func = __cvmx_error_display; 2067215976Sjmallett info.user_info = (long) 2068215976Sjmallett "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n"; 2069215976Sjmallett fail |= cvmx_error_add(&info); 2070215976Sjmallett 2071215976Sjmallett /* CVMX_IPD_INT_SUM */ 2072215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2073215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2074215976Sjmallett info.status_mask = 1ull<<0 /* prc_par0 */; 2075215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2076215976Sjmallett info.enable_mask = 1ull<<0 /* prc_par0 */; 2077215976Sjmallett info.flags = 0; 2078215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2079215976Sjmallett info.group_index = 0; 2080215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2081215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2082215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2083215976Sjmallett info.func = __cvmx_error_display; 2084215976Sjmallett info.user_info = (long) 2085215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n" 2086215976Sjmallett " [31:0] of the PBM memory.\n"; 2087215976Sjmallett fail |= cvmx_error_add(&info); 2088215976Sjmallett 2089215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2090215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2091215976Sjmallett info.status_mask = 1ull<<1 /* prc_par1 */; 2092215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2093215976Sjmallett info.enable_mask = 1ull<<1 /* prc_par1 */; 2094215976Sjmallett info.flags = 0; 2095215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2096215976Sjmallett info.group_index = 0; 2097215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2098215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2099215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2100215976Sjmallett info.func = __cvmx_error_display; 2101215976Sjmallett info.user_info = (long) 2102215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n" 2103215976Sjmallett " [63:32] of the PBM memory.\n"; 2104215976Sjmallett fail |= cvmx_error_add(&info); 2105215976Sjmallett 2106215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2107215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2108215976Sjmallett info.status_mask = 1ull<<2 /* prc_par2 */; 2109215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2110215976Sjmallett info.enable_mask = 1ull<<2 /* prc_par2 */; 2111215976Sjmallett info.flags = 0; 2112215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2113215976Sjmallett info.group_index = 0; 2114215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2115215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2116215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2117215976Sjmallett info.func = __cvmx_error_display; 2118215976Sjmallett info.user_info = (long) 2119215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n" 2120215976Sjmallett " [95:64] of the PBM memory.\n"; 2121215976Sjmallett fail |= cvmx_error_add(&info); 2122215976Sjmallett 2123215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2124215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2125215976Sjmallett info.status_mask = 1ull<<3 /* prc_par3 */; 2126215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2127215976Sjmallett info.enable_mask = 1ull<<3 /* prc_par3 */; 2128215976Sjmallett info.flags = 0; 2129215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2130215976Sjmallett info.group_index = 0; 2131215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2132215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2133215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2134215976Sjmallett info.func = __cvmx_error_display; 2135215976Sjmallett info.user_info = (long) 2136215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n" 2137215976Sjmallett " [127:96] of the PBM memory.\n"; 2138215976Sjmallett fail |= cvmx_error_add(&info); 2139215976Sjmallett 2140215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2141215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 2142215976Sjmallett info.status_mask = 1ull<<4 /* bp_sub */; 2143215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 2144215976Sjmallett info.enable_mask = 1ull<<4 /* bp_sub */; 2145215976Sjmallett info.flags = 0; 2146215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2147215976Sjmallett info.group_index = 0; 2148215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2149215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2150215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 2151215976Sjmallett info.func = __cvmx_error_display; 2152215976Sjmallett info.user_info = (long) 2153215976Sjmallett "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n" 2154215976Sjmallett " supplied illegal value.\n"; 2155215976Sjmallett fail |= cvmx_error_add(&info); 2156215976Sjmallett 2157215976Sjmallett /* CVMX_POW_ECC_ERR */ 2158215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2159215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2160215976Sjmallett info.status_mask = 1ull<<0 /* sbe */; 2161215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2162215976Sjmallett info.enable_mask = 1ull<<2 /* sbe_ie */; 2163215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 2164215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2165215976Sjmallett info.group_index = 0; 2166215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2167215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2168215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2169215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_sbe; 2170215976Sjmallett info.user_info = (long) 2171215976Sjmallett "ERROR POW_ECC_ERR[SBE]: Single bit error\n"; 2172215976Sjmallett fail |= cvmx_error_add(&info); 2173215976Sjmallett 2174215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2175215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2176215976Sjmallett info.status_mask = 1ull<<1 /* dbe */; 2177215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2178215976Sjmallett info.enable_mask = 1ull<<3 /* dbe_ie */; 2179215976Sjmallett info.flags = 0; 2180215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2181215976Sjmallett info.group_index = 0; 2182215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2183215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2184215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2185215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_dbe; 2186215976Sjmallett info.user_info = (long) 2187215976Sjmallett "ERROR POW_ECC_ERR[DBE]: Double bit error\n"; 2188215976Sjmallett fail |= cvmx_error_add(&info); 2189215976Sjmallett 2190215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2191215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 2192215976Sjmallett info.status_mask = 1ull<<12 /* rpe */; 2193215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 2194215976Sjmallett info.enable_mask = 1ull<<13 /* rpe_ie */; 2195215976Sjmallett info.flags = 0; 2196215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2197215976Sjmallett info.group_index = 0; 2198215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2199215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2200215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 2201215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_rpe; 2202215976Sjmallett info.user_info = (long) 2203215976Sjmallett "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n"; 2204215976Sjmallett fail |= cvmx_error_add(&info); 2205215976Sjmallett 2206215976Sjmallett /* CVMX_ASXX_INT_REG(0) */ 2207215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2208215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(0); 2209215976Sjmallett info.status_mask = 0x7ull<<0 /* ovrflw */; 2210215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(0); 2211215976Sjmallett info.enable_mask = 0x7ull<<0 /* ovrflw */; 2212215976Sjmallett info.flags = 0; 2213215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2214215976Sjmallett info.group_index = 0; 2215215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2216215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2217215976Sjmallett info.parent.status_mask = 1ull<<22 /* asx0 */; 2218215976Sjmallett info.func = __cvmx_error_display; 2219215976Sjmallett info.user_info = (long) 2220215976Sjmallett "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n"; 2221215976Sjmallett fail |= cvmx_error_add(&info); 2222215976Sjmallett 2223215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2224215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(0); 2225215976Sjmallett info.status_mask = 0x7ull<<4 /* txpop */; 2226215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(0); 2227215976Sjmallett info.enable_mask = 0x7ull<<4 /* txpop */; 2228215976Sjmallett info.flags = 0; 2229215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2230215976Sjmallett info.group_index = 0; 2231215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2232215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2233215976Sjmallett info.parent.status_mask = 1ull<<22 /* asx0 */; 2234215976Sjmallett info.func = __cvmx_error_display; 2235215976Sjmallett info.user_info = (long) 2236215976Sjmallett "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n"; 2237215976Sjmallett fail |= cvmx_error_add(&info); 2238215976Sjmallett 2239215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2240215976Sjmallett info.status_addr = CVMX_ASXX_INT_REG(0); 2241215976Sjmallett info.status_mask = 0x7ull<<8 /* txpsh */; 2242215976Sjmallett info.enable_addr = CVMX_ASXX_INT_EN(0); 2243215976Sjmallett info.enable_mask = 0x7ull<<8 /* txpsh */; 2244215976Sjmallett info.flags = 0; 2245215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 2246215976Sjmallett info.group_index = 0; 2247215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2248215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2249215976Sjmallett info.parent.status_mask = 1ull<<22 /* asx0 */; 2250215976Sjmallett info.func = __cvmx_error_display; 2251215976Sjmallett info.user_info = (long) 2252215976Sjmallett "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n"; 2253215976Sjmallett fail |= cvmx_error_add(&info); 2254215976Sjmallett 2255215976Sjmallett /* CVMX_PKO_REG_ERROR */ 2256215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2257215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 2258215976Sjmallett info.status_mask = 1ull<<0 /* parity */; 2259215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 2260215976Sjmallett info.enable_mask = 1ull<<0 /* parity */; 2261215976Sjmallett info.flags = 0; 2262215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2263215976Sjmallett info.group_index = 0; 2264215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2265215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2266215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 2267215976Sjmallett info.func = __cvmx_error_display; 2268215976Sjmallett info.user_info = (long) 2269215976Sjmallett "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n"; 2270215976Sjmallett fail |= cvmx_error_add(&info); 2271215976Sjmallett 2272215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2273215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 2274215976Sjmallett info.status_mask = 1ull<<1 /* doorbell */; 2275215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 2276215976Sjmallett info.enable_mask = 1ull<<1 /* doorbell */; 2277215976Sjmallett info.flags = 0; 2278215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2279215976Sjmallett info.group_index = 0; 2280215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2281215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2282215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 2283215976Sjmallett info.func = __cvmx_error_display; 2284215976Sjmallett info.user_info = (long) 2285215976Sjmallett "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 2286215976Sjmallett fail |= cvmx_error_add(&info); 2287215976Sjmallett 2288215976Sjmallett /* CVMX_TIM_REG_ERROR */ 2289215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2290215976Sjmallett info.status_addr = CVMX_TIM_REG_ERROR; 2291215976Sjmallett info.status_mask = 0xffffull<<0 /* mask */; 2292215976Sjmallett info.enable_addr = CVMX_TIM_REG_INT_MASK; 2293215976Sjmallett info.enable_mask = 0xffffull<<0 /* mask */; 2294215976Sjmallett info.flags = 0; 2295215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2296215976Sjmallett info.group_index = 0; 2297215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2298215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2299215976Sjmallett info.parent.status_mask = 1ull<<11 /* tim */; 2300215976Sjmallett info.func = __cvmx_error_display; 2301215976Sjmallett info.user_info = (long) 2302215976Sjmallett "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n"; 2303215976Sjmallett fail |= cvmx_error_add(&info); 2304215976Sjmallett 2305215976Sjmallett /* CVMX_ZIP_ERROR */ 2306215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2307215976Sjmallett info.status_addr = CVMX_ZIP_ERROR; 2308215976Sjmallett info.status_mask = 1ull<<0 /* doorbell */; 2309215976Sjmallett info.enable_addr = CVMX_ZIP_INT_MASK; 2310215976Sjmallett info.enable_mask = 1ull<<0 /* doorbell */; 2311215976Sjmallett info.flags = 0; 2312215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2313215976Sjmallett info.group_index = 0; 2314215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2315215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2316215976Sjmallett info.parent.status_mask = 1ull<<7 /* zip */; 2317215976Sjmallett info.func = __cvmx_error_display; 2318215976Sjmallett info.user_info = (long) 2319215976Sjmallett "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 2320215976Sjmallett fail |= cvmx_error_add(&info); 2321215976Sjmallett 2322215976Sjmallett /* CVMX_PIP_INT_REG */ 2323215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2324215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2325215976Sjmallett info.status_mask = 1ull<<3 /* prtnxa */; 2326215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2327215976Sjmallett info.enable_mask = 1ull<<3 /* prtnxa */; 2328215976Sjmallett info.flags = 0; 2329215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2330215976Sjmallett info.group_index = 0; 2331215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2332215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2333215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2334215976Sjmallett info.func = __cvmx_error_display; 2335215976Sjmallett info.user_info = (long) 2336215976Sjmallett "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n"; 2337215976Sjmallett fail |= cvmx_error_add(&info); 2338215976Sjmallett 2339215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2340215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2341215976Sjmallett info.status_mask = 1ull<<4 /* badtag */; 2342215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2343215976Sjmallett info.enable_mask = 1ull<<4 /* badtag */; 2344215976Sjmallett info.flags = 0; 2345215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2346215976Sjmallett info.group_index = 0; 2347215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2348215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2349215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2350215976Sjmallett info.func = __cvmx_error_display; 2351215976Sjmallett info.user_info = (long) 2352215976Sjmallett "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n"; 2353215976Sjmallett fail |= cvmx_error_add(&info); 2354215976Sjmallett 2355215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2356215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2357215976Sjmallett info.status_mask = 1ull<<5 /* skprunt */; 2358215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2359215976Sjmallett info.enable_mask = 1ull<<5 /* skprunt */; 2360215976Sjmallett info.flags = 0; 2361215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2362215976Sjmallett info.group_index = 0; 2363215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2364215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2365215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2366215976Sjmallett info.func = __cvmx_error_display; 2367215976Sjmallett info.user_info = (long) 2368215976Sjmallett "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n" 2369215976Sjmallett " This interrupt can occur with received PARTIAL\n" 2370215976Sjmallett " packets that are truncated to SKIP bytes or\n" 2371215976Sjmallett " smaller.\n"; 2372215976Sjmallett fail |= cvmx_error_add(&info); 2373215976Sjmallett 2374215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2375215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2376215976Sjmallett info.status_mask = 1ull<<6 /* todoovr */; 2377215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2378215976Sjmallett info.enable_mask = 1ull<<6 /* todoovr */; 2379215976Sjmallett info.flags = 0; 2380215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2381215976Sjmallett info.group_index = 0; 2382215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2383215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2384215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2385215976Sjmallett info.func = __cvmx_error_display; 2386215976Sjmallett info.user_info = (long) 2387215976Sjmallett "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n" 2388215976Sjmallett " (not used in O2P)\n"; 2389215976Sjmallett fail |= cvmx_error_add(&info); 2390215976Sjmallett 2391215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2392215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2393215976Sjmallett info.status_mask = 1ull<<7 /* feperr */; 2394215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2395215976Sjmallett info.enable_mask = 1ull<<7 /* feperr */; 2396215976Sjmallett info.flags = 0; 2397215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2398215976Sjmallett info.group_index = 0; 2399215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2400215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2401215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2402215976Sjmallett info.func = __cvmx_error_display; 2403215976Sjmallett info.user_info = (long) 2404215976Sjmallett "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n"; 2405215976Sjmallett fail |= cvmx_error_add(&info); 2406215976Sjmallett 2407215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2408215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 2409215976Sjmallett info.status_mask = 1ull<<8 /* beperr */; 2410215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 2411215976Sjmallett info.enable_mask = 1ull<<8 /* beperr */; 2412215976Sjmallett info.flags = 0; 2413215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2414215976Sjmallett info.group_index = 0; 2415215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2416215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2417215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 2418215976Sjmallett info.func = __cvmx_error_display; 2419215976Sjmallett info.user_info = (long) 2420215976Sjmallett "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n"; 2421215976Sjmallett fail |= cvmx_error_add(&info); 2422215976Sjmallett 2423215976Sjmallett /* CVMX_FPA_INT_SUM */ 2424215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2425215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2426215976Sjmallett info.status_mask = 1ull<<0 /* fed0_sbe */; 2427215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2428215976Sjmallett info.enable_mask = 1ull<<0 /* fed0_sbe */; 2429215976Sjmallett info.flags = 0; 2430215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2431215976Sjmallett info.group_index = 0; 2432215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2433215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2434215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2435215976Sjmallett info.func = __cvmx_error_display; 2436215976Sjmallett info.user_info = (long) 2437215976Sjmallett "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n"; 2438215976Sjmallett fail |= cvmx_error_add(&info); 2439215976Sjmallett 2440215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2441215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2442215976Sjmallett info.status_mask = 1ull<<1 /* fed0_dbe */; 2443215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2444215976Sjmallett info.enable_mask = 1ull<<1 /* fed0_dbe */; 2445215976Sjmallett info.flags = 0; 2446215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2447215976Sjmallett info.group_index = 0; 2448215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2449215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2450215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2451215976Sjmallett info.func = __cvmx_error_display; 2452215976Sjmallett info.user_info = (long) 2453215976Sjmallett "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n"; 2454215976Sjmallett fail |= cvmx_error_add(&info); 2455215976Sjmallett 2456215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2457215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2458215976Sjmallett info.status_mask = 1ull<<2 /* fed1_sbe */; 2459215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2460215976Sjmallett info.enable_mask = 1ull<<2 /* fed1_sbe */; 2461215976Sjmallett info.flags = 0; 2462215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2463215976Sjmallett info.group_index = 0; 2464215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2465215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2466215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2467215976Sjmallett info.func = __cvmx_error_display; 2468215976Sjmallett info.user_info = (long) 2469215976Sjmallett "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n"; 2470215976Sjmallett fail |= cvmx_error_add(&info); 2471215976Sjmallett 2472215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2473215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2474215976Sjmallett info.status_mask = 1ull<<3 /* fed1_dbe */; 2475215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2476215976Sjmallett info.enable_mask = 1ull<<3 /* fed1_dbe */; 2477215976Sjmallett info.flags = 0; 2478215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2479215976Sjmallett info.group_index = 0; 2480215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2481215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2482215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2483215976Sjmallett info.func = __cvmx_error_display; 2484215976Sjmallett info.user_info = (long) 2485215976Sjmallett "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n"; 2486215976Sjmallett fail |= cvmx_error_add(&info); 2487215976Sjmallett 2488215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2489215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2490215976Sjmallett info.status_mask = 1ull<<4 /* q0_und */; 2491215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2492215976Sjmallett info.enable_mask = 1ull<<4 /* q0_und */; 2493215976Sjmallett info.flags = 0; 2494215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2495215976Sjmallett info.group_index = 0; 2496215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2497215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2498215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2499215976Sjmallett info.func = __cvmx_error_display; 2500215976Sjmallett info.user_info = (long) 2501215976Sjmallett "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n" 2502215976Sjmallett " negative.\n"; 2503215976Sjmallett fail |= cvmx_error_add(&info); 2504215976Sjmallett 2505215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2506215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2507215976Sjmallett info.status_mask = 1ull<<5 /* q0_coff */; 2508215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2509215976Sjmallett info.enable_mask = 1ull<<5 /* q0_coff */; 2510215976Sjmallett info.flags = 0; 2511215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2512215976Sjmallett info.group_index = 0; 2513215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2514215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2515215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2516215976Sjmallett info.func = __cvmx_error_display; 2517215976Sjmallett info.user_info = (long) 2518215976Sjmallett "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n" 2519215976Sjmallett " the count available is greater than pointers\n" 2520215976Sjmallett " present in the FPA.\n"; 2521215976Sjmallett fail |= cvmx_error_add(&info); 2522215976Sjmallett 2523215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2524215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2525215976Sjmallett info.status_mask = 1ull<<6 /* q0_perr */; 2526215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2527215976Sjmallett info.enable_mask = 1ull<<6 /* q0_perr */; 2528215976Sjmallett info.flags = 0; 2529215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2530215976Sjmallett info.group_index = 0; 2531215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2532215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2533215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2534215976Sjmallett info.func = __cvmx_error_display; 2535215976Sjmallett info.user_info = (long) 2536215976Sjmallett "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n" 2537215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2538215976Sjmallett fail |= cvmx_error_add(&info); 2539215976Sjmallett 2540215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2541215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2542215976Sjmallett info.status_mask = 1ull<<7 /* q1_und */; 2543215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2544215976Sjmallett info.enable_mask = 1ull<<7 /* q1_und */; 2545215976Sjmallett info.flags = 0; 2546215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2547215976Sjmallett info.group_index = 0; 2548215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2549215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2550215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2551215976Sjmallett info.func = __cvmx_error_display; 2552215976Sjmallett info.user_info = (long) 2553215976Sjmallett "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n" 2554215976Sjmallett " negative.\n"; 2555215976Sjmallett fail |= cvmx_error_add(&info); 2556215976Sjmallett 2557215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2558215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2559215976Sjmallett info.status_mask = 1ull<<8 /* q1_coff */; 2560215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2561215976Sjmallett info.enable_mask = 1ull<<8 /* q1_coff */; 2562215976Sjmallett info.flags = 0; 2563215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2564215976Sjmallett info.group_index = 0; 2565215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2566215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2567215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2568215976Sjmallett info.func = __cvmx_error_display; 2569215976Sjmallett info.user_info = (long) 2570215976Sjmallett "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n" 2571215976Sjmallett " the count available is greater than pointers\n" 2572215976Sjmallett " present in the FPA.\n"; 2573215976Sjmallett fail |= cvmx_error_add(&info); 2574215976Sjmallett 2575215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2576215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2577215976Sjmallett info.status_mask = 1ull<<9 /* q1_perr */; 2578215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2579215976Sjmallett info.enable_mask = 1ull<<9 /* q1_perr */; 2580215976Sjmallett info.flags = 0; 2581215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2582215976Sjmallett info.group_index = 0; 2583215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2584215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2585215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2586215976Sjmallett info.func = __cvmx_error_display; 2587215976Sjmallett info.user_info = (long) 2588215976Sjmallett "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n" 2589215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2590215976Sjmallett fail |= cvmx_error_add(&info); 2591215976Sjmallett 2592215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2593215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2594215976Sjmallett info.status_mask = 1ull<<10 /* q2_und */; 2595215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2596215976Sjmallett info.enable_mask = 1ull<<10 /* q2_und */; 2597215976Sjmallett info.flags = 0; 2598215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2599215976Sjmallett info.group_index = 0; 2600215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2601215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2602215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2603215976Sjmallett info.func = __cvmx_error_display; 2604215976Sjmallett info.user_info = (long) 2605215976Sjmallett "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n" 2606215976Sjmallett " negative.\n"; 2607215976Sjmallett fail |= cvmx_error_add(&info); 2608215976Sjmallett 2609215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2610215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2611215976Sjmallett info.status_mask = 1ull<<11 /* q2_coff */; 2612215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2613215976Sjmallett info.enable_mask = 1ull<<11 /* q2_coff */; 2614215976Sjmallett info.flags = 0; 2615215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2616215976Sjmallett info.group_index = 0; 2617215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2618215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2619215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2620215976Sjmallett info.func = __cvmx_error_display; 2621215976Sjmallett info.user_info = (long) 2622215976Sjmallett "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n" 2623215976Sjmallett " the count available is greater than than pointers\n" 2624215976Sjmallett " present in the FPA.\n"; 2625215976Sjmallett fail |= cvmx_error_add(&info); 2626215976Sjmallett 2627215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2628215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2629215976Sjmallett info.status_mask = 1ull<<12 /* q2_perr */; 2630215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2631215976Sjmallett info.enable_mask = 1ull<<12 /* q2_perr */; 2632215976Sjmallett info.flags = 0; 2633215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2634215976Sjmallett info.group_index = 0; 2635215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2636215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2637215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2638215976Sjmallett info.func = __cvmx_error_display; 2639215976Sjmallett info.user_info = (long) 2640215976Sjmallett "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n" 2641215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2642215976Sjmallett fail |= cvmx_error_add(&info); 2643215976Sjmallett 2644215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2645215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2646215976Sjmallett info.status_mask = 1ull<<13 /* q3_und */; 2647215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2648215976Sjmallett info.enable_mask = 1ull<<13 /* q3_und */; 2649215976Sjmallett info.flags = 0; 2650215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2651215976Sjmallett info.group_index = 0; 2652215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2653215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2654215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2655215976Sjmallett info.func = __cvmx_error_display; 2656215976Sjmallett info.user_info = (long) 2657215976Sjmallett "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n" 2658215976Sjmallett " negative.\n"; 2659215976Sjmallett fail |= cvmx_error_add(&info); 2660215976Sjmallett 2661215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2662215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2663215976Sjmallett info.status_mask = 1ull<<14 /* q3_coff */; 2664215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2665215976Sjmallett info.enable_mask = 1ull<<14 /* q3_coff */; 2666215976Sjmallett info.flags = 0; 2667215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2668215976Sjmallett info.group_index = 0; 2669215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2670215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2671215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2672215976Sjmallett info.func = __cvmx_error_display; 2673215976Sjmallett info.user_info = (long) 2674215976Sjmallett "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n" 2675215976Sjmallett " the count available is greater than than pointers\n" 2676215976Sjmallett " present in the FPA.\n"; 2677215976Sjmallett fail |= cvmx_error_add(&info); 2678215976Sjmallett 2679215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2680215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2681215976Sjmallett info.status_mask = 1ull<<15 /* q3_perr */; 2682215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2683215976Sjmallett info.enable_mask = 1ull<<15 /* q3_perr */; 2684215976Sjmallett info.flags = 0; 2685215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2686215976Sjmallett info.group_index = 0; 2687215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2688215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2689215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2690215976Sjmallett info.func = __cvmx_error_display; 2691215976Sjmallett info.user_info = (long) 2692215976Sjmallett "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n" 2693215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2694215976Sjmallett fail |= cvmx_error_add(&info); 2695215976Sjmallett 2696215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2697215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2698215976Sjmallett info.status_mask = 1ull<<16 /* q4_und */; 2699215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2700215976Sjmallett info.enable_mask = 1ull<<16 /* q4_und */; 2701215976Sjmallett info.flags = 0; 2702215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2703215976Sjmallett info.group_index = 0; 2704215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2705215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2706215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2707215976Sjmallett info.func = __cvmx_error_display; 2708215976Sjmallett info.user_info = (long) 2709215976Sjmallett "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n" 2710215976Sjmallett " negative.\n"; 2711215976Sjmallett fail |= cvmx_error_add(&info); 2712215976Sjmallett 2713215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2714215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2715215976Sjmallett info.status_mask = 1ull<<17 /* q4_coff */; 2716215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2717215976Sjmallett info.enable_mask = 1ull<<17 /* q4_coff */; 2718215976Sjmallett info.flags = 0; 2719215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2720215976Sjmallett info.group_index = 0; 2721215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2722215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2723215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2724215976Sjmallett info.func = __cvmx_error_display; 2725215976Sjmallett info.user_info = (long) 2726215976Sjmallett "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n" 2727215976Sjmallett " the count available is greater than than pointers\n" 2728215976Sjmallett " present in the FPA.\n"; 2729215976Sjmallett fail |= cvmx_error_add(&info); 2730215976Sjmallett 2731215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2732215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2733215976Sjmallett info.status_mask = 1ull<<18 /* q4_perr */; 2734215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2735215976Sjmallett info.enable_mask = 1ull<<18 /* q4_perr */; 2736215976Sjmallett info.flags = 0; 2737215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2738215976Sjmallett info.group_index = 0; 2739215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2740215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2741215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2742215976Sjmallett info.func = __cvmx_error_display; 2743215976Sjmallett info.user_info = (long) 2744215976Sjmallett "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n" 2745215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2746215976Sjmallett fail |= cvmx_error_add(&info); 2747215976Sjmallett 2748215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2749215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2750215976Sjmallett info.status_mask = 1ull<<19 /* q5_und */; 2751215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2752215976Sjmallett info.enable_mask = 1ull<<19 /* q5_und */; 2753215976Sjmallett info.flags = 0; 2754215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2755215976Sjmallett info.group_index = 0; 2756215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2757215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2758215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2759215976Sjmallett info.func = __cvmx_error_display; 2760215976Sjmallett info.user_info = (long) 2761215976Sjmallett "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n" 2762215976Sjmallett " negative.\n"; 2763215976Sjmallett fail |= cvmx_error_add(&info); 2764215976Sjmallett 2765215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2766215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2767215976Sjmallett info.status_mask = 1ull<<20 /* q5_coff */; 2768215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2769215976Sjmallett info.enable_mask = 1ull<<20 /* q5_coff */; 2770215976Sjmallett info.flags = 0; 2771215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2772215976Sjmallett info.group_index = 0; 2773215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2774215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2775215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2776215976Sjmallett info.func = __cvmx_error_display; 2777215976Sjmallett info.user_info = (long) 2778215976Sjmallett "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n" 2779215976Sjmallett " the count available is greater than than pointers\n" 2780215976Sjmallett " present in the FPA.\n"; 2781215976Sjmallett fail |= cvmx_error_add(&info); 2782215976Sjmallett 2783215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2784215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2785215976Sjmallett info.status_mask = 1ull<<21 /* q5_perr */; 2786215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2787215976Sjmallett info.enable_mask = 1ull<<21 /* q5_perr */; 2788215976Sjmallett info.flags = 0; 2789215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2790215976Sjmallett info.group_index = 0; 2791215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2792215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2793215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2794215976Sjmallett info.func = __cvmx_error_display; 2795215976Sjmallett info.user_info = (long) 2796215976Sjmallett "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n" 2797215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2798215976Sjmallett fail |= cvmx_error_add(&info); 2799215976Sjmallett 2800215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2801215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2802215976Sjmallett info.status_mask = 1ull<<22 /* q6_und */; 2803215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2804215976Sjmallett info.enable_mask = 1ull<<22 /* q6_und */; 2805215976Sjmallett info.flags = 0; 2806215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2807215976Sjmallett info.group_index = 0; 2808215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2809215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2810215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2811215976Sjmallett info.func = __cvmx_error_display; 2812215976Sjmallett info.user_info = (long) 2813215976Sjmallett "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n" 2814215976Sjmallett " negative.\n"; 2815215976Sjmallett fail |= cvmx_error_add(&info); 2816215976Sjmallett 2817215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2818215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2819215976Sjmallett info.status_mask = 1ull<<23 /* q6_coff */; 2820215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2821215976Sjmallett info.enable_mask = 1ull<<23 /* q6_coff */; 2822215976Sjmallett info.flags = 0; 2823215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2824215976Sjmallett info.group_index = 0; 2825215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2826215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2827215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2828215976Sjmallett info.func = __cvmx_error_display; 2829215976Sjmallett info.user_info = (long) 2830215976Sjmallett "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n" 2831215976Sjmallett " the count available is greater than than pointers\n" 2832215976Sjmallett " present in the FPA.\n"; 2833215976Sjmallett fail |= cvmx_error_add(&info); 2834215976Sjmallett 2835215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2836215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2837215976Sjmallett info.status_mask = 1ull<<24 /* q6_perr */; 2838215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2839215976Sjmallett info.enable_mask = 1ull<<24 /* q6_perr */; 2840215976Sjmallett info.flags = 0; 2841215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2842215976Sjmallett info.group_index = 0; 2843215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2844215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2845215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2846215976Sjmallett info.func = __cvmx_error_display; 2847215976Sjmallett info.user_info = (long) 2848215976Sjmallett "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n" 2849215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2850215976Sjmallett fail |= cvmx_error_add(&info); 2851215976Sjmallett 2852215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2853215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2854215976Sjmallett info.status_mask = 1ull<<25 /* q7_und */; 2855215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2856215976Sjmallett info.enable_mask = 1ull<<25 /* q7_und */; 2857215976Sjmallett info.flags = 0; 2858215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2859215976Sjmallett info.group_index = 0; 2860215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2861215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2862215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2863215976Sjmallett info.func = __cvmx_error_display; 2864215976Sjmallett info.user_info = (long) 2865215976Sjmallett "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n" 2866215976Sjmallett " negative.\n"; 2867215976Sjmallett fail |= cvmx_error_add(&info); 2868215976Sjmallett 2869215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2870215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2871215976Sjmallett info.status_mask = 1ull<<26 /* q7_coff */; 2872215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2873215976Sjmallett info.enable_mask = 1ull<<26 /* q7_coff */; 2874215976Sjmallett info.flags = 0; 2875215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2876215976Sjmallett info.group_index = 0; 2877215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2878215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2879215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2880215976Sjmallett info.func = __cvmx_error_display; 2881215976Sjmallett info.user_info = (long) 2882215976Sjmallett "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n" 2883215976Sjmallett " the count available is greater than than pointers\n" 2884215976Sjmallett " present in the FPA.\n"; 2885215976Sjmallett fail |= cvmx_error_add(&info); 2886215976Sjmallett 2887215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2888215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 2889215976Sjmallett info.status_mask = 1ull<<27 /* q7_perr */; 2890215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 2891215976Sjmallett info.enable_mask = 1ull<<27 /* q7_perr */; 2892215976Sjmallett info.flags = 0; 2893215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2894215976Sjmallett info.group_index = 0; 2895215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2896215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2897215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 2898215976Sjmallett info.func = __cvmx_error_display; 2899215976Sjmallett info.user_info = (long) 2900215976Sjmallett "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n" 2901215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 2902215976Sjmallett fail |= cvmx_error_add(&info); 2903215976Sjmallett 2904215976Sjmallett /* CVMX_LMCX_MEM_CFG0(0) */ 2905215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2906215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 2907215976Sjmallett info.status_mask = 0xfull<<21 /* sec_err */; 2908215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 2909215976Sjmallett info.enable_mask = 1ull<<19 /* intr_sec_ena */; 2910215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 2911215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 2912215976Sjmallett info.group_index = 0; 2913215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2914215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2915215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc */; 2916215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err; 2917215976Sjmallett info.user_info = (long) 2918215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n" 2919215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 2920215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 2921215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 2922215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 2923215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 2924215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 2925215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 2926215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 2927215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 2928215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 2929215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 2930215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 2931215976Sjmallett fail |= cvmx_error_add(&info); 2932215976Sjmallett 2933215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2934215976Sjmallett info.status_addr = CVMX_LMCX_MEM_CFG0(0); 2935215976Sjmallett info.status_mask = 0xfull<<25 /* ded_err */; 2936215976Sjmallett info.enable_addr = CVMX_LMCX_MEM_CFG0(0); 2937215976Sjmallett info.enable_mask = 1ull<<20 /* intr_ded_ena */; 2938215976Sjmallett info.flags = 0; 2939215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 2940215976Sjmallett info.group_index = 0; 2941215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2942215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2943215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc */; 2944215976Sjmallett info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err; 2945215976Sjmallett info.user_info = (long) 2946215976Sjmallett "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n" 2947215976Sjmallett " In 64b mode, ecc is calculated on 2 cycle worth of data\n" 2948215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 2949215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 2950215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 2951215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 2952215976Sjmallett " In 32b mode, ecc is calculated on 4 cycle worth of data\n" 2953215976Sjmallett " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n" 2954215976Sjmallett " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n" 2955215976Sjmallett " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n" 2956215976Sjmallett " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n" 2957215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 2958215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 2959215976Sjmallett fail |= cvmx_error_add(&info); 2960215976Sjmallett 2961215976Sjmallett /* CVMX_DFA_ERR */ 2962215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2963215976Sjmallett info.status_addr = CVMX_DFA_ERR; 2964215976Sjmallett info.status_mask = 1ull<<1 /* cp2sbe */; 2965215976Sjmallett info.enable_addr = 0; 2966215976Sjmallett info.enable_mask = 0; 2967215976Sjmallett info.flags = 0; 2968215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2969215976Sjmallett info.group_index = 0; 2970215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2971215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 2972215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 2973215976Sjmallett info.func = __cvmx_error_handle_dfa_err_cp2sbe; 2974215976Sjmallett info.user_info = (long) 2975215976Sjmallett "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n" 2976215976Sjmallett " When set, a single bit error had been detected and\n" 2977215976Sjmallett " corrected for a PP-generated QW Mode read\n" 2978215976Sjmallett " transaction.\n" 2979215976Sjmallett " If the CP2DBE=0, then the CP2SYN contains the\n" 2980215976Sjmallett " failing syndrome (used during correction).\n" 2981215976Sjmallett " Refer to CP2ECCENA.\n" 2982215976Sjmallett " If the CP2SBINA had previously been enabled(set),\n" 2983215976Sjmallett " an interrupt will be posted. Software can clear\n" 2984215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 2985215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 2986215976Sjmallett " about the memory address/control to help isolate\n" 2987215976Sjmallett " the failure.\n" 2988215976Sjmallett " NOTE: PP-generated LW Mode Read transactions\n" 2989215976Sjmallett " do not participate in ECC check/correct).\n"; 2990215976Sjmallett fail |= cvmx_error_add(&info); 2991215976Sjmallett 2992215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2993215976Sjmallett info.status_addr = CVMX_DFA_ERR; 2994215976Sjmallett info.status_mask = 1ull<<2 /* cp2dbe */; 2995215976Sjmallett info.enable_addr = 0; 2996215976Sjmallett info.enable_mask = 0; 2997215976Sjmallett info.flags = 0; 2998215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2999215976Sjmallett info.group_index = 0; 3000215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3001215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3002215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 3003215976Sjmallett info.func = __cvmx_error_handle_dfa_err_cp2dbe; 3004215976Sjmallett info.user_info = (long) 3005215976Sjmallett "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n" 3006215976Sjmallett " When set, a double bit error had been detected\n" 3007215976Sjmallett " for a PP-generated QW Mode read transaction.\n" 3008215976Sjmallett " The CP2SYN contains the failing syndrome.\n" 3009215976Sjmallett " NOTE: PP-generated LW Mode Read transactions\n" 3010215976Sjmallett " do not participate in ECC check/correct).\n" 3011215976Sjmallett " Refer to CP2ECCENA.\n" 3012215976Sjmallett " If the CP2DBINA had previously been enabled(set),\n" 3013215976Sjmallett " an interrupt will be posted. Software can clear\n" 3014215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 3015215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 3016215976Sjmallett " about the memory address/control to help isolate\n" 3017215976Sjmallett " the failure.\n"; 3018215976Sjmallett fail |= cvmx_error_add(&info); 3019215976Sjmallett 3020215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3021215976Sjmallett info.status_addr = CVMX_DFA_ERR; 3022215976Sjmallett info.status_mask = 1ull<<14 /* dtesbe */; 3023215976Sjmallett info.enable_addr = 0; 3024215976Sjmallett info.enable_mask = 0; 3025215976Sjmallett info.flags = 0; 3026215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3027215976Sjmallett info.group_index = 0; 3028215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3029215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3030215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 3031215976Sjmallett info.func = __cvmx_error_handle_dfa_err_dtesbe; 3032215976Sjmallett info.user_info = (long) 3033215976Sjmallett "ERROR DFA_ERR[DTESBE]: DTE 25b Single Bit Error Corrected - Status bit\n" 3034215976Sjmallett " When set, a single bit error had been detected and\n" 3035215976Sjmallett " corrected for a DTE-generated 32b SIMPLE Mode read\n" 3036215976Sjmallett " transaction.\n" 3037215976Sjmallett " If the DTEDBE=0, then the DTESYN contains the\n" 3038215976Sjmallett " failing syndrome (used during correction).\n" 3039215976Sjmallett " NOTE: DTE-generated 16b SIMPLE Mode Read\n" 3040215976Sjmallett " transactions do not participate in ECC check/correct).\n" 3041215976Sjmallett " If the DTESBINA had previously been enabled(set),\n" 3042215976Sjmallett " an interrupt will be posted. Software can clear\n" 3043215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 3044215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 3045215976Sjmallett " about the memory address/control to help isolate\n" 3046215976Sjmallett " the failure.\n"; 3047215976Sjmallett fail |= cvmx_error_add(&info); 3048215976Sjmallett 3049215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3050215976Sjmallett info.status_addr = CVMX_DFA_ERR; 3051215976Sjmallett info.status_mask = 1ull<<15 /* dtedbe */; 3052215976Sjmallett info.enable_addr = 0; 3053215976Sjmallett info.enable_mask = 0; 3054215976Sjmallett info.flags = 0; 3055215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3056215976Sjmallett info.group_index = 0; 3057215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3058215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3059215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 3060215976Sjmallett info.func = __cvmx_error_handle_dfa_err_dtedbe; 3061215976Sjmallett info.user_info = (long) 3062215976Sjmallett "ERROR DFA_ERR[DTEDBE]: DTE 25b Double Bit Error Detected - Status bit\n" 3063215976Sjmallett " When set, a double bit error had been detected\n" 3064215976Sjmallett " for a DTE-generated 32b SIMPLE Mode read transaction.\n" 3065215976Sjmallett " The DTESYN contains the failing syndrome.\n" 3066215976Sjmallett " If the DTEDBINA had previously been enabled(set),\n" 3067215976Sjmallett " an interrupt will be posted. Software can clear\n" 3068215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 3069215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 3070215976Sjmallett " about the memory address/control to help isolate\n" 3071215976Sjmallett " the failure.\n" 3072215976Sjmallett " NOTE: DTE-generated 16b SIMPLE Mode Read transactions\n" 3073215976Sjmallett " do not participate in ECC check/correct).\n"; 3074215976Sjmallett fail |= cvmx_error_add(&info); 3075215976Sjmallett 3076215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3077215976Sjmallett info.status_addr = CVMX_DFA_ERR; 3078215976Sjmallett info.status_mask = 1ull<<26 /* dteperr */; 3079215976Sjmallett info.enable_addr = 0; 3080215976Sjmallett info.enable_mask = 0; 3081215976Sjmallett info.flags = 0; 3082215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3083215976Sjmallett info.group_index = 0; 3084215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3085215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3086215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 3087215976Sjmallett info.func = __cvmx_error_handle_dfa_err_dteperr; 3088215976Sjmallett info.user_info = (long) 3089215976Sjmallett "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 16b SIMPLE mode ONLY)\n" 3090215976Sjmallett " When set, all DTE-generated 16b SIMPLE Mode read\n" 3091215976Sjmallett " transactions which encounter a parity error (across\n" 3092215976Sjmallett " the 17b of data) are reported.\n"; 3093215976Sjmallett fail |= cvmx_error_add(&info); 3094215976Sjmallett 3095215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3096215976Sjmallett info.status_addr = CVMX_DFA_ERR; 3097215976Sjmallett info.status_mask = 1ull<<29 /* cp2perr */; 3098215976Sjmallett info.enable_addr = 0; 3099215976Sjmallett info.enable_mask = 0; 3100215976Sjmallett info.flags = 0; 3101215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3102215976Sjmallett info.group_index = 0; 3103215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3104215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3105215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 3106215976Sjmallett info.func = __cvmx_error_handle_dfa_err_cp2perr; 3107215976Sjmallett info.user_info = (long) 3108215976Sjmallett "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n" 3109215976Sjmallett " When set, a parity error had been detected for a\n" 3110215976Sjmallett " PP-generated LW Mode read transaction.\n" 3111215976Sjmallett " If the CP2PINA had previously been enabled(set),\n" 3112215976Sjmallett " an interrupt will be posted. Software can clear\n" 3113215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 3114215976Sjmallett " See also: DFA_MEMFADR CSR which contains more data\n" 3115215976Sjmallett " about the memory address/control to help isolate\n" 3116215976Sjmallett " the failure.\n"; 3117215976Sjmallett fail |= cvmx_error_add(&info); 3118215976Sjmallett 3119215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3120215976Sjmallett info.status_addr = CVMX_DFA_ERR; 3121215976Sjmallett info.status_mask = 1ull<<31 /* dblovf */; 3122215976Sjmallett info.enable_addr = 0; 3123215976Sjmallett info.enable_mask = 0; 3124215976Sjmallett info.flags = 0; 3125215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3126215976Sjmallett info.group_index = 0; 3127215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3128215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3129215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 3130215976Sjmallett info.func = __cvmx_error_handle_dfa_err_dblovf; 3131215976Sjmallett info.user_info = (long) 3132215976Sjmallett "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n" 3133215976Sjmallett " When set, the 20b accumulated doorbell register\n" 3134215976Sjmallett " had overflowed (SW wrote too many doorbell requests).\n" 3135215976Sjmallett " If the DBLINA had previously been enabled(set),\n" 3136215976Sjmallett " an interrupt will be posted. Software can clear\n" 3137215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 3138215976Sjmallett " NOTE: Detection of a Doorbell Register overflow\n" 3139215976Sjmallett " is a catastrophic error which may leave the DFA\n" 3140215976Sjmallett " HW in an unrecoverable state.\n"; 3141215976Sjmallett fail |= cvmx_error_add(&info); 3142215976Sjmallett 3143215976Sjmallett /* CVMX_IOB_INT_SUM */ 3144215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3145215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 3146215976Sjmallett info.status_mask = 1ull<<0 /* np_sop */; 3147215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 3148215976Sjmallett info.enable_mask = 1ull<<0 /* np_sop */; 3149215976Sjmallett info.flags = 0; 3150215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3151215976Sjmallett info.group_index = 0; 3152215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3153215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3154215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 3155215976Sjmallett info.func = __cvmx_error_display; 3156215976Sjmallett info.user_info = (long) 3157215976Sjmallett "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n" 3158215976Sjmallett " port for a non-passthrough packet.\n" 3159215976Sjmallett " The first detected error associated with bits [3:0]\n" 3160215976Sjmallett " of this register will only be set here. A new bit\n" 3161215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 3162215976Sjmallett fail |= cvmx_error_add(&info); 3163215976Sjmallett 3164215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3165215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 3166215976Sjmallett info.status_mask = 1ull<<1 /* np_eop */; 3167215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 3168215976Sjmallett info.enable_mask = 1ull<<1 /* np_eop */; 3169215976Sjmallett info.flags = 0; 3170215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3171215976Sjmallett info.group_index = 0; 3172215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3173215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3174215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 3175215976Sjmallett info.func = __cvmx_error_display; 3176215976Sjmallett info.user_info = (long) 3177215976Sjmallett "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n" 3178215976Sjmallett " port for a non-passthrough packet.\n" 3179215976Sjmallett " The first detected error associated with bits [3:0]\n" 3180215976Sjmallett " of this register will only be set here. A new bit\n" 3181215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 3182215976Sjmallett fail |= cvmx_error_add(&info); 3183215976Sjmallett 3184215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3185215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 3186215976Sjmallett info.status_mask = 1ull<<2 /* p_sop */; 3187215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 3188215976Sjmallett info.enable_mask = 1ull<<2 /* p_sop */; 3189215976Sjmallett info.flags = 0; 3190215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3191215976Sjmallett info.group_index = 0; 3192215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3193215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3194215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 3195215976Sjmallett info.func = __cvmx_error_display; 3196215976Sjmallett info.user_info = (long) 3197215976Sjmallett "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n" 3198215976Sjmallett " port for a passthrough packet.\n" 3199215976Sjmallett " The first detected error associated with bits [3:0]\n" 3200215976Sjmallett " of this register will only be set here. A new bit\n" 3201215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 3202215976Sjmallett fail |= cvmx_error_add(&info); 3203215976Sjmallett 3204215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3205215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 3206215976Sjmallett info.status_mask = 1ull<<3 /* p_eop */; 3207215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 3208215976Sjmallett info.enable_mask = 1ull<<3 /* p_eop */; 3209215976Sjmallett info.flags = 0; 3210215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3211215976Sjmallett info.group_index = 0; 3212215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3213215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3214215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 3215215976Sjmallett info.func = __cvmx_error_display; 3216215976Sjmallett info.user_info = (long) 3217215976Sjmallett "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n" 3218215976Sjmallett " port for a passthrough packet.\n" 3219215976Sjmallett " The first detected error associated with bits [3:0]\n" 3220215976Sjmallett " of this register will only be set here. A new bit\n" 3221215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 3222215976Sjmallett fail |= cvmx_error_add(&info); 3223215976Sjmallett 3224215976Sjmallett /* CVMX_USBNX_INT_SUM(0) */ 3225215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3226215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3227215976Sjmallett info.status_mask = 1ull<<0 /* pr_po_e */; 3228215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3229215976Sjmallett info.enable_mask = 1ull<<0 /* pr_po_e */; 3230215976Sjmallett info.flags = 0; 3231215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3232215976Sjmallett info.group_index = 0; 3233215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3234215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3235215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3236215976Sjmallett info.func = __cvmx_error_display; 3237215976Sjmallett info.user_info = (long) 3238215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n"; 3239215976Sjmallett fail |= cvmx_error_add(&info); 3240215976Sjmallett 3241215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3242215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3243215976Sjmallett info.status_mask = 1ull<<1 /* pr_pu_f */; 3244215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3245215976Sjmallett info.enable_mask = 1ull<<1 /* pr_pu_f */; 3246215976Sjmallett info.flags = 0; 3247215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3248215976Sjmallett info.group_index = 0; 3249215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3250215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3251215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3252215976Sjmallett info.func = __cvmx_error_display; 3253215976Sjmallett info.user_info = (long) 3254215976Sjmallett "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n"; 3255215976Sjmallett fail |= cvmx_error_add(&info); 3256215976Sjmallett 3257215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3258215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3259215976Sjmallett info.status_mask = 1ull<<2 /* nr_po_e */; 3260215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3261215976Sjmallett info.enable_mask = 1ull<<2 /* nr_po_e */; 3262215976Sjmallett info.flags = 0; 3263215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3264215976Sjmallett info.group_index = 0; 3265215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3266215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3267215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3268215976Sjmallett info.func = __cvmx_error_display; 3269215976Sjmallett info.user_info = (long) 3270215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n"; 3271215976Sjmallett fail |= cvmx_error_add(&info); 3272215976Sjmallett 3273215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3274215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3275215976Sjmallett info.status_mask = 1ull<<3 /* nr_pu_f */; 3276215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3277215976Sjmallett info.enable_mask = 1ull<<3 /* nr_pu_f */; 3278215976Sjmallett info.flags = 0; 3279215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3280215976Sjmallett info.group_index = 0; 3281215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3282215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3283215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3284215976Sjmallett info.func = __cvmx_error_display; 3285215976Sjmallett info.user_info = (long) 3286215976Sjmallett "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n"; 3287215976Sjmallett fail |= cvmx_error_add(&info); 3288215976Sjmallett 3289215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3290215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3291215976Sjmallett info.status_mask = 1ull<<4 /* lr_po_e */; 3292215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3293215976Sjmallett info.enable_mask = 1ull<<4 /* lr_po_e */; 3294215976Sjmallett info.flags = 0; 3295215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3296215976Sjmallett info.group_index = 0; 3297215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3298215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3299215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3300215976Sjmallett info.func = __cvmx_error_display; 3301215976Sjmallett info.user_info = (long) 3302215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n"; 3303215976Sjmallett fail |= cvmx_error_add(&info); 3304215976Sjmallett 3305215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3306215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3307215976Sjmallett info.status_mask = 1ull<<5 /* lr_pu_f */; 3308215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3309215976Sjmallett info.enable_mask = 1ull<<5 /* lr_pu_f */; 3310215976Sjmallett info.flags = 0; 3311215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3312215976Sjmallett info.group_index = 0; 3313215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3314215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3315215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3316215976Sjmallett info.func = __cvmx_error_display; 3317215976Sjmallett info.user_info = (long) 3318215976Sjmallett "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n"; 3319215976Sjmallett fail |= cvmx_error_add(&info); 3320215976Sjmallett 3321215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3322215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3323215976Sjmallett info.status_mask = 1ull<<6 /* pt_po_e */; 3324215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3325215976Sjmallett info.enable_mask = 1ull<<6 /* pt_po_e */; 3326215976Sjmallett info.flags = 0; 3327215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3328215976Sjmallett info.group_index = 0; 3329215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3330215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3331215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3332215976Sjmallett info.func = __cvmx_error_display; 3333215976Sjmallett info.user_info = (long) 3334215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n"; 3335215976Sjmallett fail |= cvmx_error_add(&info); 3336215976Sjmallett 3337215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3338215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3339215976Sjmallett info.status_mask = 1ull<<7 /* pt_pu_f */; 3340215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3341215976Sjmallett info.enable_mask = 1ull<<7 /* pt_pu_f */; 3342215976Sjmallett info.flags = 0; 3343215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3344215976Sjmallett info.group_index = 0; 3345215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3346215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3347215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3348215976Sjmallett info.func = __cvmx_error_display; 3349215976Sjmallett info.user_info = (long) 3350215976Sjmallett "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n"; 3351215976Sjmallett fail |= cvmx_error_add(&info); 3352215976Sjmallett 3353215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3354215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3355215976Sjmallett info.status_mask = 1ull<<8 /* nt_po_e */; 3356215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3357215976Sjmallett info.enable_mask = 1ull<<8 /* nt_po_e */; 3358215976Sjmallett info.flags = 0; 3359215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3360215976Sjmallett info.group_index = 0; 3361215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3362215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3363215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3364215976Sjmallett info.func = __cvmx_error_display; 3365215976Sjmallett info.user_info = (long) 3366215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n"; 3367215976Sjmallett fail |= cvmx_error_add(&info); 3368215976Sjmallett 3369215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3370215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3371215976Sjmallett info.status_mask = 1ull<<9 /* nt_pu_f */; 3372215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3373215976Sjmallett info.enable_mask = 1ull<<9 /* nt_pu_f */; 3374215976Sjmallett info.flags = 0; 3375215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3376215976Sjmallett info.group_index = 0; 3377215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3378215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3379215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3380215976Sjmallett info.func = __cvmx_error_display; 3381215976Sjmallett info.user_info = (long) 3382215976Sjmallett "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n"; 3383215976Sjmallett fail |= cvmx_error_add(&info); 3384215976Sjmallett 3385215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3386215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3387215976Sjmallett info.status_mask = 1ull<<10 /* lt_po_e */; 3388215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3389215976Sjmallett info.enable_mask = 1ull<<10 /* lt_po_e */; 3390215976Sjmallett info.flags = 0; 3391215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3392215976Sjmallett info.group_index = 0; 3393215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3394215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3395215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3396215976Sjmallett info.func = __cvmx_error_display; 3397215976Sjmallett info.user_info = (long) 3398215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n"; 3399215976Sjmallett fail |= cvmx_error_add(&info); 3400215976Sjmallett 3401215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3402215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3403215976Sjmallett info.status_mask = 1ull<<11 /* lt_pu_f */; 3404215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3405215976Sjmallett info.enable_mask = 1ull<<11 /* lt_pu_f */; 3406215976Sjmallett info.flags = 0; 3407215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3408215976Sjmallett info.group_index = 0; 3409215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3410215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3411215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3412215976Sjmallett info.func = __cvmx_error_display; 3413215976Sjmallett info.user_info = (long) 3414215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n"; 3415215976Sjmallett fail |= cvmx_error_add(&info); 3416215976Sjmallett 3417215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3418215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3419215976Sjmallett info.status_mask = 1ull<<12 /* dcred_e */; 3420215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3421215976Sjmallett info.enable_mask = 1ull<<12 /* dcred_e */; 3422215976Sjmallett info.flags = 0; 3423215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3424215976Sjmallett info.group_index = 0; 3425215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3426215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3427215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3428215976Sjmallett info.func = __cvmx_error_display; 3429215976Sjmallett info.user_info = (long) 3430215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n"; 3431215976Sjmallett fail |= cvmx_error_add(&info); 3432215976Sjmallett 3433215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3434215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3435215976Sjmallett info.status_mask = 1ull<<13 /* dcred_f */; 3436215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3437215976Sjmallett info.enable_mask = 1ull<<13 /* dcred_f */; 3438215976Sjmallett info.flags = 0; 3439215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3440215976Sjmallett info.group_index = 0; 3441215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3442215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3443215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3444215976Sjmallett info.func = __cvmx_error_display; 3445215976Sjmallett info.user_info = (long) 3446215976Sjmallett "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n"; 3447215976Sjmallett fail |= cvmx_error_add(&info); 3448215976Sjmallett 3449215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3450215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3451215976Sjmallett info.status_mask = 1ull<<14 /* l2c_s_e */; 3452215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3453215976Sjmallett info.enable_mask = 1ull<<14 /* l2c_s_e */; 3454215976Sjmallett info.flags = 0; 3455215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3456215976Sjmallett info.group_index = 0; 3457215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3458215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3459215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3460215976Sjmallett info.func = __cvmx_error_display; 3461215976Sjmallett info.user_info = (long) 3462215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n"; 3463215976Sjmallett fail |= cvmx_error_add(&info); 3464215976Sjmallett 3465215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3466215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3467215976Sjmallett info.status_mask = 1ull<<15 /* l2c_a_f */; 3468215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3469215976Sjmallett info.enable_mask = 1ull<<15 /* l2c_a_f */; 3470215976Sjmallett info.flags = 0; 3471215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3472215976Sjmallett info.group_index = 0; 3473215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3474215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3475215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3476215976Sjmallett info.func = __cvmx_error_display; 3477215976Sjmallett info.user_info = (long) 3478215976Sjmallett "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n"; 3479215976Sjmallett fail |= cvmx_error_add(&info); 3480215976Sjmallett 3481215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3482215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3483215976Sjmallett info.status_mask = 1ull<<16 /* lt_fi_e */; 3484215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3485215976Sjmallett info.enable_mask = 1ull<<16 /* l2_fi_e */; 3486215976Sjmallett info.flags = 0; 3487215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3488215976Sjmallett info.group_index = 0; 3489215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3490215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3491215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3492215976Sjmallett info.func = __cvmx_error_display; 3493215976Sjmallett info.user_info = (long) 3494215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n"; 3495215976Sjmallett fail |= cvmx_error_add(&info); 3496215976Sjmallett 3497215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3498215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3499215976Sjmallett info.status_mask = 1ull<<17 /* lt_fi_f */; 3500215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3501215976Sjmallett info.enable_mask = 1ull<<17 /* l2_fi_f */; 3502215976Sjmallett info.flags = 0; 3503215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3504215976Sjmallett info.group_index = 0; 3505215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3506215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3507215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3508215976Sjmallett info.func = __cvmx_error_display; 3509215976Sjmallett info.user_info = (long) 3510215976Sjmallett "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n"; 3511215976Sjmallett fail |= cvmx_error_add(&info); 3512215976Sjmallett 3513215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3514215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3515215976Sjmallett info.status_mask = 1ull<<18 /* rg_fi_e */; 3516215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3517215976Sjmallett info.enable_mask = 1ull<<18 /* rg_fi_e */; 3518215976Sjmallett info.flags = 0; 3519215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3520215976Sjmallett info.group_index = 0; 3521215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3522215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3523215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3524215976Sjmallett info.func = __cvmx_error_display; 3525215976Sjmallett info.user_info = (long) 3526215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n"; 3527215976Sjmallett fail |= cvmx_error_add(&info); 3528215976Sjmallett 3529215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3530215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3531215976Sjmallett info.status_mask = 1ull<<19 /* rg_fi_f */; 3532215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3533215976Sjmallett info.enable_mask = 1ull<<19 /* rg_fi_f */; 3534215976Sjmallett info.flags = 0; 3535215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3536215976Sjmallett info.group_index = 0; 3537215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3538215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3539215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3540215976Sjmallett info.func = __cvmx_error_display; 3541215976Sjmallett info.user_info = (long) 3542215976Sjmallett "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n"; 3543215976Sjmallett fail |= cvmx_error_add(&info); 3544215976Sjmallett 3545215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3546215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3547215976Sjmallett info.status_mask = 1ull<<20 /* rq_q2_f */; 3548215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3549215976Sjmallett info.enable_mask = 1ull<<20 /* rq_q2_f */; 3550215976Sjmallett info.flags = 0; 3551215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3552215976Sjmallett info.group_index = 0; 3553215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3554215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3555215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3556215976Sjmallett info.func = __cvmx_error_display; 3557215976Sjmallett info.user_info = (long) 3558215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n"; 3559215976Sjmallett fail |= cvmx_error_add(&info); 3560215976Sjmallett 3561215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3562215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3563215976Sjmallett info.status_mask = 1ull<<21 /* rq_q2_e */; 3564215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3565215976Sjmallett info.enable_mask = 1ull<<21 /* rq_q2_e */; 3566215976Sjmallett info.flags = 0; 3567215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3568215976Sjmallett info.group_index = 0; 3569215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3570215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3571215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3572215976Sjmallett info.func = __cvmx_error_display; 3573215976Sjmallett info.user_info = (long) 3574215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n"; 3575215976Sjmallett fail |= cvmx_error_add(&info); 3576215976Sjmallett 3577215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3578215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3579215976Sjmallett info.status_mask = 1ull<<22 /* rq_q3_f */; 3580215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3581215976Sjmallett info.enable_mask = 1ull<<22 /* rq_q3_f */; 3582215976Sjmallett info.flags = 0; 3583215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3584215976Sjmallett info.group_index = 0; 3585215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3586215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3587215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3588215976Sjmallett info.func = __cvmx_error_display; 3589215976Sjmallett info.user_info = (long) 3590215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n"; 3591215976Sjmallett fail |= cvmx_error_add(&info); 3592215976Sjmallett 3593215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3594215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3595215976Sjmallett info.status_mask = 1ull<<23 /* rq_q3_e */; 3596215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3597215976Sjmallett info.enable_mask = 1ull<<23 /* rq_q3_e */; 3598215976Sjmallett info.flags = 0; 3599215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3600215976Sjmallett info.group_index = 0; 3601215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3602215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3603215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3604215976Sjmallett info.func = __cvmx_error_display; 3605215976Sjmallett info.user_info = (long) 3606215976Sjmallett "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n"; 3607215976Sjmallett fail |= cvmx_error_add(&info); 3608215976Sjmallett 3609215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3610215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3611215976Sjmallett info.status_mask = 1ull<<24 /* uod_pe */; 3612215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3613215976Sjmallett info.enable_mask = 1ull<<24 /* uod_pe */; 3614215976Sjmallett info.flags = 0; 3615215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3616215976Sjmallett info.group_index = 0; 3617215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3618215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3619215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3620215976Sjmallett info.func = __cvmx_error_display; 3621215976Sjmallett info.user_info = (long) 3622215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n"; 3623215976Sjmallett fail |= cvmx_error_add(&info); 3624215976Sjmallett 3625215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3626215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3627215976Sjmallett info.status_mask = 1ull<<25 /* uod_pf */; 3628215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3629215976Sjmallett info.enable_mask = 1ull<<25 /* uod_pf */; 3630215976Sjmallett info.flags = 0; 3631215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3632215976Sjmallett info.group_index = 0; 3633215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3634215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3635215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3636215976Sjmallett info.func = __cvmx_error_display; 3637215976Sjmallett info.user_info = (long) 3638215976Sjmallett "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n"; 3639215976Sjmallett fail |= cvmx_error_add(&info); 3640215976Sjmallett 3641215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3642215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3643215976Sjmallett info.status_mask = 1ull<<26 /* n2u_pf */; 3644215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3645215976Sjmallett info.enable_mask = 1ull<<26 /* n2u_pf */; 3646215976Sjmallett info.flags = 0; 3647215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3648215976Sjmallett info.group_index = 0; 3649215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3650215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3651215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3652215976Sjmallett info.func = __cvmx_error_display; 3653215976Sjmallett info.user_info = (long) 3654215976Sjmallett "ERROR USBNX_INT_SUM(0)[N2U_PF]: N2U Fifo Push Full.\n"; 3655215976Sjmallett fail |= cvmx_error_add(&info); 3656215976Sjmallett 3657215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3658215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3659215976Sjmallett info.status_mask = 1ull<<27 /* n2u_pe */; 3660215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3661215976Sjmallett info.enable_mask = 1ull<<27 /* n2u_pe */; 3662215976Sjmallett info.flags = 0; 3663215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3664215976Sjmallett info.group_index = 0; 3665215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3666215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3667215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3668215976Sjmallett info.func = __cvmx_error_display; 3669215976Sjmallett info.user_info = (long) 3670215976Sjmallett "ERROR USBNX_INT_SUM(0)[N2U_PE]: N2U Fifo Pop Empty.\n"; 3671215976Sjmallett fail |= cvmx_error_add(&info); 3672215976Sjmallett 3673215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3674215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3675215976Sjmallett info.status_mask = 1ull<<28 /* u2n_d_pe */; 3676215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3677215976Sjmallett info.enable_mask = 1ull<<28 /* u2n_d_pe */; 3678215976Sjmallett info.flags = 0; 3679215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3680215976Sjmallett info.group_index = 0; 3681215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3682215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3683215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3684215976Sjmallett info.func = __cvmx_error_display; 3685215976Sjmallett info.user_info = (long) 3686215976Sjmallett "ERROR USBNX_INT_SUM(0)[U2N_D_PE]: U2N Data Fifo Pop Empty.\n"; 3687215976Sjmallett fail |= cvmx_error_add(&info); 3688215976Sjmallett 3689215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3690215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3691215976Sjmallett info.status_mask = 1ull<<29 /* u2n_d_pf */; 3692215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3693215976Sjmallett info.enable_mask = 1ull<<29 /* u2n_d_pf */; 3694215976Sjmallett info.flags = 0; 3695215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3696215976Sjmallett info.group_index = 0; 3697215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3698215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3699215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3700215976Sjmallett info.func = __cvmx_error_display; 3701215976Sjmallett info.user_info = (long) 3702215976Sjmallett "ERROR USBNX_INT_SUM(0)[U2N_D_PF]: U2N Data Fifo Push Full.\n"; 3703215976Sjmallett fail |= cvmx_error_add(&info); 3704215976Sjmallett 3705215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3706215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3707215976Sjmallett info.status_mask = 1ull<<30 /* u2n_c_pf */; 3708215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3709215976Sjmallett info.enable_mask = 1ull<<30 /* u2n_c_pf */; 3710215976Sjmallett info.flags = 0; 3711215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3712215976Sjmallett info.group_index = 0; 3713215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3714215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3715215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3716215976Sjmallett info.func = __cvmx_error_display; 3717215976Sjmallett info.user_info = (long) 3718215976Sjmallett "ERROR USBNX_INT_SUM(0)[U2N_C_PF]: U2N Control Fifo Push Full.\n"; 3719215976Sjmallett fail |= cvmx_error_add(&info); 3720215976Sjmallett 3721215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3722215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3723215976Sjmallett info.status_mask = 1ull<<31 /* u2n_c_pe */; 3724215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3725215976Sjmallett info.enable_mask = 1ull<<31 /* u2n_c_pe */; 3726215976Sjmallett info.flags = 0; 3727215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3728215976Sjmallett info.group_index = 0; 3729215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3730215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3731215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3732215976Sjmallett info.func = __cvmx_error_display; 3733215976Sjmallett info.user_info = (long) 3734215976Sjmallett "ERROR USBNX_INT_SUM(0)[U2N_C_PE]: U2N Control Fifo Pop Empty.\n"; 3735215976Sjmallett fail |= cvmx_error_add(&info); 3736215976Sjmallett 3737215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3738215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3739215976Sjmallett info.status_mask = 1ull<<32 /* ltl_f_pe */; 3740215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3741215976Sjmallett info.enable_mask = 1ull<<32 /* ltl_f_pe */; 3742215976Sjmallett info.flags = 0; 3743215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3744215976Sjmallett info.group_index = 0; 3745215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3746215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3747215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3748215976Sjmallett info.func = __cvmx_error_display; 3749215976Sjmallett info.user_info = (long) 3750215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n"; 3751215976Sjmallett fail |= cvmx_error_add(&info); 3752215976Sjmallett 3753215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3754215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3755215976Sjmallett info.status_mask = 1ull<<33 /* ltl_f_pf */; 3756215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3757215976Sjmallett info.enable_mask = 1ull<<33 /* ltl_f_pf */; 3758215976Sjmallett info.flags = 0; 3759215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3760215976Sjmallett info.group_index = 0; 3761215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3762215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3763215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3764215976Sjmallett info.func = __cvmx_error_display; 3765215976Sjmallett info.user_info = (long) 3766215976Sjmallett "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n"; 3767215976Sjmallett fail |= cvmx_error_add(&info); 3768215976Sjmallett 3769215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3770215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3771215976Sjmallett info.status_mask = 1ull<<34 /* nd4o_rpe */; 3772215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3773215976Sjmallett info.enable_mask = 1ull<<34 /* nd4o_rpe */; 3774215976Sjmallett info.flags = 0; 3775215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3776215976Sjmallett info.group_index = 0; 3777215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3778215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3779215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3780215976Sjmallett info.func = __cvmx_error_display; 3781215976Sjmallett info.user_info = (long) 3782215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n"; 3783215976Sjmallett fail |= cvmx_error_add(&info); 3784215976Sjmallett 3785215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3786215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3787215976Sjmallett info.status_mask = 1ull<<35 /* nd4o_rpf */; 3788215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3789215976Sjmallett info.enable_mask = 1ull<<35 /* nd4o_rpf */; 3790215976Sjmallett info.flags = 0; 3791215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3792215976Sjmallett info.group_index = 0; 3793215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3794215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3795215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3796215976Sjmallett info.func = __cvmx_error_display; 3797215976Sjmallett info.user_info = (long) 3798215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n"; 3799215976Sjmallett fail |= cvmx_error_add(&info); 3800215976Sjmallett 3801215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3802215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3803215976Sjmallett info.status_mask = 1ull<<36 /* nd4o_dpe */; 3804215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3805215976Sjmallett info.enable_mask = 1ull<<36 /* nd4o_dpe */; 3806215976Sjmallett info.flags = 0; 3807215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3808215976Sjmallett info.group_index = 0; 3809215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3810215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3811215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3812215976Sjmallett info.func = __cvmx_error_display; 3813215976Sjmallett info.user_info = (long) 3814215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n"; 3815215976Sjmallett fail |= cvmx_error_add(&info); 3816215976Sjmallett 3817215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3818215976Sjmallett info.status_addr = CVMX_USBNX_INT_SUM(0); 3819215976Sjmallett info.status_mask = 1ull<<37 /* nd4o_dpf */; 3820215976Sjmallett info.enable_addr = CVMX_USBNX_INT_ENB(0); 3821215976Sjmallett info.enable_mask = 1ull<<37 /* nd4o_dpf */; 3822215976Sjmallett info.flags = 0; 3823215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3824215976Sjmallett info.group_index = 0; 3825215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3826215976Sjmallett info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS; 3827215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3828215976Sjmallett info.func = __cvmx_error_display; 3829215976Sjmallett info.user_info = (long) 3830215976Sjmallett "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n"; 3831215976Sjmallett fail |= cvmx_error_add(&info); 3832215976Sjmallett 3833215976Sjmallett return fail; 3834215976Sjmallett} 3835215976Sjmallett 3836