1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-dfa-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon dfa. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_DFA_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_DFA_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_DFA_BIST0 CVMX_DFA_BIST0_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_DFA_BIST0_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 60215976Sjmallett cvmx_warn("CVMX_DFA_BIST0 not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370007F0ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_DFA_BIST0 (CVMX_ADD_IO_SEG(0x00011800370007F0ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_DFA_BIST1 CVMX_DFA_BIST1_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_DFA_BIST1_FUNC(void) 69215976Sjmallett{ 70215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 71215976Sjmallett cvmx_warn("CVMX_DFA_BIST1 not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370007F8ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_DFA_BIST1 (CVMX_ADD_IO_SEG(0x00011800370007F8ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_DFA_BST0 CVMX_DFA_BST0_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_DFA_BST0_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 82215976Sjmallett cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800300007F0ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_DFA_BST0 (CVMX_ADD_IO_SEG(0x00011800300007F0ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_DFA_BST1 CVMX_DFA_BST1_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_DFA_BST1_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 93215976Sjmallett cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800300007F8ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_DFA_BST1 (CVMX_ADD_IO_SEG(0x00011800300007F8ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_DFA_CFG CVMX_DFA_CFG_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_DFA_CFG_FUNC(void) 102215976Sjmallett{ 103215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 104215976Sjmallett cvmx_warn("CVMX_DFA_CFG not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000000ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_DFA_CFG (CVMX_ADD_IO_SEG(0x0001180030000000ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_DFA_CONFIG CVMX_DFA_CONFIG_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_DFA_CONFIG_FUNC(void) 113215976Sjmallett{ 114215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 115215976Sjmallett cvmx_warn("CVMX_DFA_CONFIG not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000000ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_DFA_CONFIG (CVMX_ADD_IO_SEG(0x0001180037000000ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_DFA_CONTROL CVMX_DFA_CONTROL_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_DFA_CONTROL_FUNC(void) 124215976Sjmallett{ 125215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 126215976Sjmallett cvmx_warn("CVMX_DFA_CONTROL not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000020ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_DFA_CONTROL (CVMX_ADD_IO_SEG(0x0001180037000020ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_DFA_DBELL_FUNC(void) 135215976Sjmallett{ 136215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 137215976Sjmallett cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x0001370000000000ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_DFA_DBELL (CVMX_ADD_IO_SEG(0x0001370000000000ull)) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallett#define CVMX_DFA_DDR2_ADDR CVMX_DFA_DDR2_ADDR_FUNC() 145215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_ADDR_FUNC(void) 146215976Sjmallett{ 147215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 148215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n"); 149215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000210ull); 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_DFA_DDR2_ADDR (CVMX_ADD_IO_SEG(0x0001180030000210ull)) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallett#define CVMX_DFA_DDR2_BUS CVMX_DFA_DDR2_BUS_FUNC() 156215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_BUS_FUNC(void) 157215976Sjmallett{ 158215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 159215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n"); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000080ull); 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_DFA_DDR2_BUS (CVMX_ADD_IO_SEG(0x0001180030000080ull)) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallett#define CVMX_DFA_DDR2_CFG CVMX_DFA_DDR2_CFG_FUNC() 167215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_CFG_FUNC(void) 168215976Sjmallett{ 169215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 170215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_CFG not supported on this chip\n"); 171215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000208ull); 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_DFA_DDR2_CFG (CVMX_ADD_IO_SEG(0x0001180030000208ull)) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallett#define CVMX_DFA_DDR2_COMP CVMX_DFA_DDR2_COMP_FUNC() 178215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_COMP_FUNC(void) 179215976Sjmallett{ 180215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 181215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_COMP not supported on this chip\n"); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000090ull); 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_DFA_DDR2_COMP (CVMX_ADD_IO_SEG(0x0001180030000090ull)) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallett#define CVMX_DFA_DDR2_EMRS CVMX_DFA_DDR2_EMRS_FUNC() 189215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_EMRS_FUNC(void) 190215976Sjmallett{ 191215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 192215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_EMRS not supported on this chip\n"); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000268ull); 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_DFA_DDR2_EMRS (CVMX_ADD_IO_SEG(0x0001180030000268ull)) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallett#define CVMX_DFA_DDR2_FCNT CVMX_DFA_DDR2_FCNT_FUNC() 200215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_FCNT_FUNC(void) 201215976Sjmallett{ 202215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 203215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_FCNT not supported on this chip\n"); 204215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000078ull); 205215976Sjmallett} 206215976Sjmallett#else 207215976Sjmallett#define CVMX_DFA_DDR2_FCNT (CVMX_ADD_IO_SEG(0x0001180030000078ull)) 208215976Sjmallett#endif 209215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210215976Sjmallett#define CVMX_DFA_DDR2_MRS CVMX_DFA_DDR2_MRS_FUNC() 211215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_MRS_FUNC(void) 212215976Sjmallett{ 213215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 214215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_MRS not supported on this chip\n"); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000260ull); 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_DFA_DDR2_MRS (CVMX_ADD_IO_SEG(0x0001180030000260ull)) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallett#define CVMX_DFA_DDR2_OPT CVMX_DFA_DDR2_OPT_FUNC() 222215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_OPT_FUNC(void) 223215976Sjmallett{ 224215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 225215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_OPT not supported on this chip\n"); 226215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000070ull); 227215976Sjmallett} 228215976Sjmallett#else 229215976Sjmallett#define CVMX_DFA_DDR2_OPT (CVMX_ADD_IO_SEG(0x0001180030000070ull)) 230215976Sjmallett#endif 231215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232215976Sjmallett#define CVMX_DFA_DDR2_PLL CVMX_DFA_DDR2_PLL_FUNC() 233215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_PLL_FUNC(void) 234215976Sjmallett{ 235215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 236215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_PLL not supported on this chip\n"); 237215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000088ull); 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_DFA_DDR2_PLL (CVMX_ADD_IO_SEG(0x0001180030000088ull)) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallett#define CVMX_DFA_DDR2_TMG CVMX_DFA_DDR2_TMG_FUNC() 244215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void) 245215976Sjmallett{ 246215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 247215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_TMG not supported on this chip\n"); 248215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000218ull); 249215976Sjmallett} 250215976Sjmallett#else 251215976Sjmallett#define CVMX_DFA_DDR2_TMG (CVMX_ADD_IO_SEG(0x0001180030000218ull)) 252215976Sjmallett#endif 253215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254215976Sjmallett#define CVMX_DFA_DEBUG0 CVMX_DFA_DEBUG0_FUNC() 255215976Sjmallettstatic inline uint64_t CVMX_DFA_DEBUG0_FUNC(void) 256215976Sjmallett{ 257215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 258215976Sjmallett cvmx_warn("CVMX_DFA_DEBUG0 not supported on this chip\n"); 259215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000040ull); 260215976Sjmallett} 261215976Sjmallett#else 262215976Sjmallett#define CVMX_DFA_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180037000040ull)) 263215976Sjmallett#endif 264215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265215976Sjmallett#define CVMX_DFA_DEBUG1 CVMX_DFA_DEBUG1_FUNC() 266215976Sjmallettstatic inline uint64_t CVMX_DFA_DEBUG1_FUNC(void) 267215976Sjmallett{ 268215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 269215976Sjmallett cvmx_warn("CVMX_DFA_DEBUG1 not supported on this chip\n"); 270215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000048ull); 271215976Sjmallett} 272215976Sjmallett#else 273215976Sjmallett#define CVMX_DFA_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180037000048ull)) 274215976Sjmallett#endif 275215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276215976Sjmallett#define CVMX_DFA_DEBUG2 CVMX_DFA_DEBUG2_FUNC() 277215976Sjmallettstatic inline uint64_t CVMX_DFA_DEBUG2_FUNC(void) 278215976Sjmallett{ 279215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 280215976Sjmallett cvmx_warn("CVMX_DFA_DEBUG2 not supported on this chip\n"); 281215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000050ull); 282215976Sjmallett} 283215976Sjmallett#else 284215976Sjmallett#define CVMX_DFA_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180037000050ull)) 285215976Sjmallett#endif 286215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287215976Sjmallett#define CVMX_DFA_DEBUG3 CVMX_DFA_DEBUG3_FUNC() 288215976Sjmallettstatic inline uint64_t CVMX_DFA_DEBUG3_FUNC(void) 289215976Sjmallett{ 290215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 291215976Sjmallett cvmx_warn("CVMX_DFA_DEBUG3 not supported on this chip\n"); 292215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000058ull); 293215976Sjmallett} 294215976Sjmallett#else 295215976Sjmallett#define CVMX_DFA_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180037000058ull)) 296215976Sjmallett#endif 297215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298215976Sjmallett#define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC() 299215976Sjmallettstatic inline uint64_t CVMX_DFA_DIFCTL_FUNC(void) 300215976Sjmallett{ 301215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 302215976Sjmallett cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n"); 303215976Sjmallett return CVMX_ADD_IO_SEG(0x0001370600000000ull); 304215976Sjmallett} 305215976Sjmallett#else 306215976Sjmallett#define CVMX_DFA_DIFCTL (CVMX_ADD_IO_SEG(0x0001370600000000ull)) 307215976Sjmallett#endif 308215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309215976Sjmallett#define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC() 310215976Sjmallettstatic inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void) 311215976Sjmallett{ 312215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 313215976Sjmallett cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n"); 314215976Sjmallett return CVMX_ADD_IO_SEG(0x0001370200000000ull); 315215976Sjmallett} 316215976Sjmallett#else 317215976Sjmallett#define CVMX_DFA_DIFRDPTR (CVMX_ADD_IO_SEG(0x0001370200000000ull)) 318215976Sjmallett#endif 319215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320215976Sjmallett#define CVMX_DFA_DTCFADR CVMX_DFA_DTCFADR_FUNC() 321215976Sjmallettstatic inline uint64_t CVMX_DFA_DTCFADR_FUNC(void) 322215976Sjmallett{ 323215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 324215976Sjmallett cvmx_warn("CVMX_DFA_DTCFADR not supported on this chip\n"); 325215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000060ull); 326215976Sjmallett} 327215976Sjmallett#else 328215976Sjmallett#define CVMX_DFA_DTCFADR (CVMX_ADD_IO_SEG(0x0001180037000060ull)) 329215976Sjmallett#endif 330215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331215976Sjmallett#define CVMX_DFA_ECLKCFG CVMX_DFA_ECLKCFG_FUNC() 332215976Sjmallettstatic inline uint64_t CVMX_DFA_ECLKCFG_FUNC(void) 333215976Sjmallett{ 334215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 335215976Sjmallett cvmx_warn("CVMX_DFA_ECLKCFG not supported on this chip\n"); 336215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000200ull); 337215976Sjmallett} 338215976Sjmallett#else 339215976Sjmallett#define CVMX_DFA_ECLKCFG (CVMX_ADD_IO_SEG(0x0001180030000200ull)) 340215976Sjmallett#endif 341215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342215976Sjmallett#define CVMX_DFA_ERR CVMX_DFA_ERR_FUNC() 343215976Sjmallettstatic inline uint64_t CVMX_DFA_ERR_FUNC(void) 344215976Sjmallett{ 345215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 346215976Sjmallett cvmx_warn("CVMX_DFA_ERR not supported on this chip\n"); 347215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000028ull); 348215976Sjmallett} 349215976Sjmallett#else 350215976Sjmallett#define CVMX_DFA_ERR (CVMX_ADD_IO_SEG(0x0001180030000028ull)) 351215976Sjmallett#endif 352215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353215976Sjmallett#define CVMX_DFA_ERROR CVMX_DFA_ERROR_FUNC() 354215976Sjmallettstatic inline uint64_t CVMX_DFA_ERROR_FUNC(void) 355215976Sjmallett{ 356215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 357215976Sjmallett cvmx_warn("CVMX_DFA_ERROR not supported on this chip\n"); 358215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000028ull); 359215976Sjmallett} 360215976Sjmallett#else 361215976Sjmallett#define CVMX_DFA_ERROR (CVMX_ADD_IO_SEG(0x0001180037000028ull)) 362215976Sjmallett#endif 363215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364215976Sjmallett#define CVMX_DFA_INTMSK CVMX_DFA_INTMSK_FUNC() 365215976Sjmallettstatic inline uint64_t CVMX_DFA_INTMSK_FUNC(void) 366215976Sjmallett{ 367215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 368215976Sjmallett cvmx_warn("CVMX_DFA_INTMSK not supported on this chip\n"); 369215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000030ull); 370215976Sjmallett} 371215976Sjmallett#else 372215976Sjmallett#define CVMX_DFA_INTMSK (CVMX_ADD_IO_SEG(0x0001180037000030ull)) 373215976Sjmallett#endif 374215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375215976Sjmallett#define CVMX_DFA_MEMCFG0 CVMX_DFA_MEMCFG0_FUNC() 376215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMCFG0_FUNC(void) 377215976Sjmallett{ 378215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 379215976Sjmallett cvmx_warn("CVMX_DFA_MEMCFG0 not supported on this chip\n"); 380215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000008ull); 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_DFA_MEMCFG0 (CVMX_ADD_IO_SEG(0x0001180030000008ull)) 384215976Sjmallett#endif 385215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386215976Sjmallett#define CVMX_DFA_MEMCFG1 CVMX_DFA_MEMCFG1_FUNC() 387215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMCFG1_FUNC(void) 388215976Sjmallett{ 389215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 390215976Sjmallett cvmx_warn("CVMX_DFA_MEMCFG1 not supported on this chip\n"); 391215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000010ull); 392215976Sjmallett} 393215976Sjmallett#else 394215976Sjmallett#define CVMX_DFA_MEMCFG1 (CVMX_ADD_IO_SEG(0x0001180030000010ull)) 395215976Sjmallett#endif 396215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397215976Sjmallett#define CVMX_DFA_MEMCFG2 CVMX_DFA_MEMCFG2_FUNC() 398215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMCFG2_FUNC(void) 399215976Sjmallett{ 400215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 401215976Sjmallett cvmx_warn("CVMX_DFA_MEMCFG2 not supported on this chip\n"); 402215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000060ull); 403215976Sjmallett} 404215976Sjmallett#else 405215976Sjmallett#define CVMX_DFA_MEMCFG2 (CVMX_ADD_IO_SEG(0x0001180030000060ull)) 406215976Sjmallett#endif 407215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408215976Sjmallett#define CVMX_DFA_MEMFADR CVMX_DFA_MEMFADR_FUNC() 409215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMFADR_FUNC(void) 410215976Sjmallett{ 411215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 412215976Sjmallett cvmx_warn("CVMX_DFA_MEMFADR not supported on this chip\n"); 413215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000030ull); 414215976Sjmallett} 415215976Sjmallett#else 416215976Sjmallett#define CVMX_DFA_MEMFADR (CVMX_ADD_IO_SEG(0x0001180030000030ull)) 417215976Sjmallett#endif 418215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419215976Sjmallett#define CVMX_DFA_MEMFCR CVMX_DFA_MEMFCR_FUNC() 420215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMFCR_FUNC(void) 421215976Sjmallett{ 422215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 423215976Sjmallett cvmx_warn("CVMX_DFA_MEMFCR not supported on this chip\n"); 424215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000038ull); 425215976Sjmallett} 426215976Sjmallett#else 427215976Sjmallett#define CVMX_DFA_MEMFCR (CVMX_ADD_IO_SEG(0x0001180030000038ull)) 428215976Sjmallett#endif 429215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430215976Sjmallett#define CVMX_DFA_MEMHIDAT CVMX_DFA_MEMHIDAT_FUNC() 431215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMHIDAT_FUNC(void) 432215976Sjmallett{ 433215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 434215976Sjmallett cvmx_warn("CVMX_DFA_MEMHIDAT not supported on this chip\n"); 435215976Sjmallett return CVMX_ADD_IO_SEG(0x0001370700000000ull); 436215976Sjmallett} 437215976Sjmallett#else 438215976Sjmallett#define CVMX_DFA_MEMHIDAT (CVMX_ADD_IO_SEG(0x0001370700000000ull)) 439215976Sjmallett#endif 440215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441215976Sjmallett#define CVMX_DFA_MEMRLD CVMX_DFA_MEMRLD_FUNC() 442215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMRLD_FUNC(void) 443215976Sjmallett{ 444215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 445215976Sjmallett cvmx_warn("CVMX_DFA_MEMRLD not supported on this chip\n"); 446215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000018ull); 447215976Sjmallett} 448215976Sjmallett#else 449215976Sjmallett#define CVMX_DFA_MEMRLD (CVMX_ADD_IO_SEG(0x0001180030000018ull)) 450215976Sjmallett#endif 451215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452215976Sjmallett#define CVMX_DFA_NCBCTL CVMX_DFA_NCBCTL_FUNC() 453215976Sjmallettstatic inline uint64_t CVMX_DFA_NCBCTL_FUNC(void) 454215976Sjmallett{ 455215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 456215976Sjmallett cvmx_warn("CVMX_DFA_NCBCTL not supported on this chip\n"); 457215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000020ull); 458215976Sjmallett} 459215976Sjmallett#else 460215976Sjmallett#define CVMX_DFA_NCBCTL (CVMX_ADD_IO_SEG(0x0001180030000020ull)) 461215976Sjmallett#endif 462215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463215976Sjmallett#define CVMX_DFA_PFC0_CNT CVMX_DFA_PFC0_CNT_FUNC() 464215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC0_CNT_FUNC(void) 465215976Sjmallett{ 466215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 467215976Sjmallett cvmx_warn("CVMX_DFA_PFC0_CNT not supported on this chip\n"); 468215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000090ull); 469215976Sjmallett} 470215976Sjmallett#else 471215976Sjmallett#define CVMX_DFA_PFC0_CNT (CVMX_ADD_IO_SEG(0x0001180037000090ull)) 472215976Sjmallett#endif 473215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474215976Sjmallett#define CVMX_DFA_PFC0_CTL CVMX_DFA_PFC0_CTL_FUNC() 475215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC0_CTL_FUNC(void) 476215976Sjmallett{ 477215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 478215976Sjmallett cvmx_warn("CVMX_DFA_PFC0_CTL not supported on this chip\n"); 479215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000088ull); 480215976Sjmallett} 481215976Sjmallett#else 482215976Sjmallett#define CVMX_DFA_PFC0_CTL (CVMX_ADD_IO_SEG(0x0001180037000088ull)) 483215976Sjmallett#endif 484215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485215976Sjmallett#define CVMX_DFA_PFC1_CNT CVMX_DFA_PFC1_CNT_FUNC() 486215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC1_CNT_FUNC(void) 487215976Sjmallett{ 488215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 489215976Sjmallett cvmx_warn("CVMX_DFA_PFC1_CNT not supported on this chip\n"); 490215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000A0ull); 491215976Sjmallett} 492215976Sjmallett#else 493215976Sjmallett#define CVMX_DFA_PFC1_CNT (CVMX_ADD_IO_SEG(0x00011800370000A0ull)) 494215976Sjmallett#endif 495215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496215976Sjmallett#define CVMX_DFA_PFC1_CTL CVMX_DFA_PFC1_CTL_FUNC() 497215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC1_CTL_FUNC(void) 498215976Sjmallett{ 499215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 500215976Sjmallett cvmx_warn("CVMX_DFA_PFC1_CTL not supported on this chip\n"); 501215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000098ull); 502215976Sjmallett} 503215976Sjmallett#else 504215976Sjmallett#define CVMX_DFA_PFC1_CTL (CVMX_ADD_IO_SEG(0x0001180037000098ull)) 505215976Sjmallett#endif 506215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507215976Sjmallett#define CVMX_DFA_PFC2_CNT CVMX_DFA_PFC2_CNT_FUNC() 508215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC2_CNT_FUNC(void) 509215976Sjmallett{ 510215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 511215976Sjmallett cvmx_warn("CVMX_DFA_PFC2_CNT not supported on this chip\n"); 512215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000B0ull); 513215976Sjmallett} 514215976Sjmallett#else 515215976Sjmallett#define CVMX_DFA_PFC2_CNT (CVMX_ADD_IO_SEG(0x00011800370000B0ull)) 516215976Sjmallett#endif 517215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518215976Sjmallett#define CVMX_DFA_PFC2_CTL CVMX_DFA_PFC2_CTL_FUNC() 519215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC2_CTL_FUNC(void) 520215976Sjmallett{ 521215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 522215976Sjmallett cvmx_warn("CVMX_DFA_PFC2_CTL not supported on this chip\n"); 523215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000A8ull); 524215976Sjmallett} 525215976Sjmallett#else 526215976Sjmallett#define CVMX_DFA_PFC2_CTL (CVMX_ADD_IO_SEG(0x00011800370000A8ull)) 527215976Sjmallett#endif 528215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529215976Sjmallett#define CVMX_DFA_PFC3_CNT CVMX_DFA_PFC3_CNT_FUNC() 530215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC3_CNT_FUNC(void) 531215976Sjmallett{ 532215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 533215976Sjmallett cvmx_warn("CVMX_DFA_PFC3_CNT not supported on this chip\n"); 534215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000C0ull); 535215976Sjmallett} 536215976Sjmallett#else 537215976Sjmallett#define CVMX_DFA_PFC3_CNT (CVMX_ADD_IO_SEG(0x00011800370000C0ull)) 538215976Sjmallett#endif 539215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540215976Sjmallett#define CVMX_DFA_PFC3_CTL CVMX_DFA_PFC3_CTL_FUNC() 541215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC3_CTL_FUNC(void) 542215976Sjmallett{ 543215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 544215976Sjmallett cvmx_warn("CVMX_DFA_PFC3_CTL not supported on this chip\n"); 545215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000B8ull); 546215976Sjmallett} 547215976Sjmallett#else 548215976Sjmallett#define CVMX_DFA_PFC3_CTL (CVMX_ADD_IO_SEG(0x00011800370000B8ull)) 549215976Sjmallett#endif 550215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551215976Sjmallett#define CVMX_DFA_PFC_GCTL CVMX_DFA_PFC_GCTL_FUNC() 552215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC_GCTL_FUNC(void) 553215976Sjmallett{ 554215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 555215976Sjmallett cvmx_warn("CVMX_DFA_PFC_GCTL not supported on this chip\n"); 556215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000080ull); 557215976Sjmallett} 558215976Sjmallett#else 559215976Sjmallett#define CVMX_DFA_PFC_GCTL (CVMX_ADD_IO_SEG(0x0001180037000080ull)) 560215976Sjmallett#endif 561215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562215976Sjmallett#define CVMX_DFA_RODT_COMP_CTL CVMX_DFA_RODT_COMP_CTL_FUNC() 563215976Sjmallettstatic inline uint64_t CVMX_DFA_RODT_COMP_CTL_FUNC(void) 564215976Sjmallett{ 565215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN58XX))) 566215976Sjmallett cvmx_warn("CVMX_DFA_RODT_COMP_CTL not supported on this chip\n"); 567215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000068ull); 568215976Sjmallett} 569215976Sjmallett#else 570215976Sjmallett#define CVMX_DFA_RODT_COMP_CTL (CVMX_ADD_IO_SEG(0x0001180030000068ull)) 571215976Sjmallett#endif 572215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573215976Sjmallett#define CVMX_DFA_SBD_DBG0 CVMX_DFA_SBD_DBG0_FUNC() 574215976Sjmallettstatic inline uint64_t CVMX_DFA_SBD_DBG0_FUNC(void) 575215976Sjmallett{ 576215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 577215976Sjmallett cvmx_warn("CVMX_DFA_SBD_DBG0 not supported on this chip\n"); 578215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000040ull); 579215976Sjmallett} 580215976Sjmallett#else 581215976Sjmallett#define CVMX_DFA_SBD_DBG0 (CVMX_ADD_IO_SEG(0x0001180030000040ull)) 582215976Sjmallett#endif 583215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584215976Sjmallett#define CVMX_DFA_SBD_DBG1 CVMX_DFA_SBD_DBG1_FUNC() 585215976Sjmallettstatic inline uint64_t CVMX_DFA_SBD_DBG1_FUNC(void) 586215976Sjmallett{ 587215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 588215976Sjmallett cvmx_warn("CVMX_DFA_SBD_DBG1 not supported on this chip\n"); 589215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000048ull); 590215976Sjmallett} 591215976Sjmallett#else 592215976Sjmallett#define CVMX_DFA_SBD_DBG1 (CVMX_ADD_IO_SEG(0x0001180030000048ull)) 593215976Sjmallett#endif 594215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595215976Sjmallett#define CVMX_DFA_SBD_DBG2 CVMX_DFA_SBD_DBG2_FUNC() 596215976Sjmallettstatic inline uint64_t CVMX_DFA_SBD_DBG2_FUNC(void) 597215976Sjmallett{ 598215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 599215976Sjmallett cvmx_warn("CVMX_DFA_SBD_DBG2 not supported on this chip\n"); 600215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000050ull); 601215976Sjmallett} 602215976Sjmallett#else 603215976Sjmallett#define CVMX_DFA_SBD_DBG2 (CVMX_ADD_IO_SEG(0x0001180030000050ull)) 604215976Sjmallett#endif 605215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606215976Sjmallett#define CVMX_DFA_SBD_DBG3 CVMX_DFA_SBD_DBG3_FUNC() 607215976Sjmallettstatic inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void) 608215976Sjmallett{ 609215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 610215976Sjmallett cvmx_warn("CVMX_DFA_SBD_DBG3 not supported on this chip\n"); 611215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000058ull); 612215976Sjmallett} 613215976Sjmallett#else 614215976Sjmallett#define CVMX_DFA_SBD_DBG3 (CVMX_ADD_IO_SEG(0x0001180030000058ull)) 615215976Sjmallett#endif 616215976Sjmallett 617215976Sjmallett/** 618215976Sjmallett * cvmx_dfa_bist0 619215976Sjmallett * 620215976Sjmallett * DFA_BIST0 = DFA Bist Status (per-DTC) 621215976Sjmallett * 622215976Sjmallett * Description: 623215976Sjmallett */ 624215976Sjmallettunion cvmx_dfa_bist0 625215976Sjmallett{ 626215976Sjmallett uint64_t u64; 627215976Sjmallett struct cvmx_dfa_bist0_s 628215976Sjmallett { 629215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 630215976Sjmallett uint64_t reserved_29_63 : 35; 631215976Sjmallett uint64_t mwb : 1; /**< Bist Results for MWB RAM(s) 632215976Sjmallett - 0: GOOD (or bist in progress/never run) 633215976Sjmallett - 1: BAD */ 634215976Sjmallett uint64_t reserved_25_27 : 3; 635215976Sjmallett uint64_t gfb : 1; /**< Bist Results for GFB RAM(s) 636215976Sjmallett - 0: GOOD (or bist in progress/never run) 637215976Sjmallett - 1: BAD */ 638215976Sjmallett uint64_t reserved_18_23 : 6; 639215976Sjmallett uint64_t stx : 2; /**< Bist Results for STX RAM(s) 640215976Sjmallett - 0: GOOD (or bist in progress/never run) 641215976Sjmallett - 1: BAD */ 642215976Sjmallett uint64_t reserved_10_15 : 6; 643215976Sjmallett uint64_t dtx : 2; /**< Bist Results for DTX RAM(s) 644215976Sjmallett - 0: GOOD (or bist in progress/never run) 645215976Sjmallett - 1: BAD */ 646215976Sjmallett uint64_t reserved_5_7 : 3; 647215976Sjmallett uint64_t rdf : 1; /**< Bist Results for RWB[3:0] RAM(s) 648215976Sjmallett - 0: GOOD (or bist in progress/never run) 649215976Sjmallett - 1: BAD */ 650215976Sjmallett uint64_t reserved_1_3 : 3; 651215976Sjmallett uint64_t pdb : 1; /**< Bist Results for PDB RAM(s) 652215976Sjmallett - 0: GOOD (or bist in progress/never run) 653215976Sjmallett - 1: BAD */ 654215976Sjmallett#else 655215976Sjmallett uint64_t pdb : 1; 656215976Sjmallett uint64_t reserved_1_3 : 3; 657215976Sjmallett uint64_t rdf : 1; 658215976Sjmallett uint64_t reserved_5_7 : 3; 659215976Sjmallett uint64_t dtx : 2; 660215976Sjmallett uint64_t reserved_10_15 : 6; 661215976Sjmallett uint64_t stx : 2; 662215976Sjmallett uint64_t reserved_18_23 : 6; 663215976Sjmallett uint64_t gfb : 1; 664215976Sjmallett uint64_t reserved_25_27 : 3; 665215976Sjmallett uint64_t mwb : 1; 666215976Sjmallett uint64_t reserved_29_63 : 35; 667215976Sjmallett#endif 668215976Sjmallett } s; 669215976Sjmallett struct cvmx_dfa_bist0_s cn63xx; 670215976Sjmallett struct cvmx_dfa_bist0_s cn63xxp1; 671215976Sjmallett}; 672215976Sjmalletttypedef union cvmx_dfa_bist0 cvmx_dfa_bist0_t; 673215976Sjmallett 674215976Sjmallett/** 675215976Sjmallett * cvmx_dfa_bist1 676215976Sjmallett * 677215976Sjmallett * DFA_BIST1 = DFA Bist Status (Globals) 678215976Sjmallett * 679215976Sjmallett * Description: 680215976Sjmallett */ 681215976Sjmallettunion cvmx_dfa_bist1 682215976Sjmallett{ 683215976Sjmallett uint64_t u64; 684215976Sjmallett struct cvmx_dfa_bist1_s 685215976Sjmallett { 686215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 687215976Sjmallett uint64_t reserved_13_63 : 51; 688215976Sjmallett uint64_t ram3 : 1; /**< Bist Results for RAM3 RAM 689215976Sjmallett - 0: GOOD (or bist in progress/never run) 690215976Sjmallett - 1: BAD */ 691215976Sjmallett uint64_t ram2 : 1; /**< Bist Results for RAM2 RAM 692215976Sjmallett - 0: GOOD (or bist in progress/never run) 693215976Sjmallett - 1: BAD */ 694215976Sjmallett uint64_t ram1 : 1; /**< Bist Results for RAM1 RAM 695215976Sjmallett - 0: GOOD (or bist in progress/never run) 696215976Sjmallett - 1: BAD */ 697215976Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 698215976Sjmallett - 0: GOOD (or bist in progress/never run) 699215976Sjmallett - 1: BAD */ 700215976Sjmallett uint64_t gutv : 1; /**< Bist Results for GUTV RAM 701215976Sjmallett - 0: GOOD (or bist in progress/never run) 702215976Sjmallett - 1: BAD */ 703215976Sjmallett uint64_t reserved_5_7 : 3; 704215976Sjmallett uint64_t gutp : 1; /**< Bist Results for NCD RAM 705215976Sjmallett - 0: GOOD (or bist in progress/never run) 706215976Sjmallett - 1: BAD */ 707215976Sjmallett uint64_t ncd : 1; /**< Bist Results for NCD RAM 708215976Sjmallett - 0: GOOD (or bist in progress/never run) 709215976Sjmallett - 1: BAD */ 710215976Sjmallett uint64_t gif : 1; /**< Bist Results for GIF RAM 711215976Sjmallett - 0: GOOD (or bist in progress/never run) 712215976Sjmallett - 1: BAD */ 713215976Sjmallett uint64_t gib : 1; /**< Bist Results for GIB RAM 714215976Sjmallett - 0: GOOD (or bist in progress/never run) 715215976Sjmallett - 1: BAD */ 716215976Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 717215976Sjmallett - 0: GOOD (or bist in progress/never run) 718215976Sjmallett - 1: BAD */ 719215976Sjmallett#else 720215976Sjmallett uint64_t gfu : 1; 721215976Sjmallett uint64_t gib : 1; 722215976Sjmallett uint64_t gif : 1; 723215976Sjmallett uint64_t ncd : 1; 724215976Sjmallett uint64_t gutp : 1; 725215976Sjmallett uint64_t reserved_5_7 : 3; 726215976Sjmallett uint64_t gutv : 1; 727215976Sjmallett uint64_t crq : 1; 728215976Sjmallett uint64_t ram1 : 1; 729215976Sjmallett uint64_t ram2 : 1; 730215976Sjmallett uint64_t ram3 : 1; 731215976Sjmallett uint64_t reserved_13_63 : 51; 732215976Sjmallett#endif 733215976Sjmallett } s; 734215976Sjmallett struct cvmx_dfa_bist1_s cn63xx; 735215976Sjmallett struct cvmx_dfa_bist1_s cn63xxp1; 736215976Sjmallett}; 737215976Sjmalletttypedef union cvmx_dfa_bist1 cvmx_dfa_bist1_t; 738215976Sjmallett 739215976Sjmallett/** 740215976Sjmallett * cvmx_dfa_bst0 741215976Sjmallett * 742215976Sjmallett * DFA_BST0 = DFA Bist Status 743215976Sjmallett * 744215976Sjmallett * Description: 745215976Sjmallett */ 746215976Sjmallettunion cvmx_dfa_bst0 747215976Sjmallett{ 748215976Sjmallett uint64_t u64; 749215976Sjmallett struct cvmx_dfa_bst0_s 750215976Sjmallett { 751215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 752215976Sjmallett uint64_t reserved_32_63 : 32; 753215976Sjmallett uint64_t rdf : 16; /**< Bist Results for RDF[3:0] RAM(s) 754215976Sjmallett - 0: GOOD (or bist in progress/never run) 755215976Sjmallett - 1: BAD */ 756215976Sjmallett uint64_t pdf : 16; /**< Bist Results for PDF[3:0] RAM(s) 757215976Sjmallett - 0: GOOD (or bist in progress/never run) 758215976Sjmallett - 1: BAD */ 759215976Sjmallett#else 760215976Sjmallett uint64_t pdf : 16; 761215976Sjmallett uint64_t rdf : 16; 762215976Sjmallett uint64_t reserved_32_63 : 32; 763215976Sjmallett#endif 764215976Sjmallett } s; 765215976Sjmallett struct cvmx_dfa_bst0_s cn31xx; 766215976Sjmallett struct cvmx_dfa_bst0_s cn38xx; 767215976Sjmallett struct cvmx_dfa_bst0_s cn38xxp2; 768215976Sjmallett struct cvmx_dfa_bst0_cn58xx 769215976Sjmallett { 770215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 771215976Sjmallett uint64_t reserved_20_63 : 44; 772215976Sjmallett uint64_t rdf : 4; /**< Bist Results for RDF[3:0] RAM(s) 773215976Sjmallett - 0: GOOD (or bist in progress/never run) 774215976Sjmallett - 1: BAD */ 775215976Sjmallett uint64_t reserved_4_15 : 12; 776215976Sjmallett uint64_t pdf : 4; /**< Bist Results for PDF[3:0] RAM(s) 777215976Sjmallett - 0: GOOD (or bist in progress/never run) 778215976Sjmallett - 1: BAD */ 779215976Sjmallett#else 780215976Sjmallett uint64_t pdf : 4; 781215976Sjmallett uint64_t reserved_4_15 : 12; 782215976Sjmallett uint64_t rdf : 4; 783215976Sjmallett uint64_t reserved_20_63 : 44; 784215976Sjmallett#endif 785215976Sjmallett } cn58xx; 786215976Sjmallett struct cvmx_dfa_bst0_cn58xx cn58xxp1; 787215976Sjmallett}; 788215976Sjmalletttypedef union cvmx_dfa_bst0 cvmx_dfa_bst0_t; 789215976Sjmallett 790215976Sjmallett/** 791215976Sjmallett * cvmx_dfa_bst1 792215976Sjmallett * 793215976Sjmallett * DFA_BST1 = DFA Bist Status 794215976Sjmallett * 795215976Sjmallett * Description: 796215976Sjmallett */ 797215976Sjmallettunion cvmx_dfa_bst1 798215976Sjmallett{ 799215976Sjmallett uint64_t u64; 800215976Sjmallett struct cvmx_dfa_bst1_s 801215976Sjmallett { 802215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 803215976Sjmallett uint64_t reserved_23_63 : 41; 804215976Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 805215976Sjmallett - 0: GOOD (or bist in progress/never run) 806215976Sjmallett - 1: BAD */ 807215976Sjmallett uint64_t ifu : 1; /**< Bist Results for IFU RAM 808215976Sjmallett - 0: GOOD (or bist in progress/never run) 809215976Sjmallett - 1: BAD */ 810215976Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 811215976Sjmallett - 0: GOOD (or bist in progress/never run) 812215976Sjmallett - 1: BAD */ 813215976Sjmallett uint64_t drf : 1; /**< Bist Results for DRF RAM 814215976Sjmallett - 0: GOOD (or bist in progress/never run) 815215976Sjmallett - 1: BAD */ 816215976Sjmallett uint64_t crf : 1; /**< Bist Results for CRF RAM 817215976Sjmallett - 0: GOOD (or bist in progress/never run) 818215976Sjmallett - 1: BAD */ 819215976Sjmallett uint64_t p0_bwb : 1; /**< Bist Results for P0_BWB RAM 820215976Sjmallett - 0: GOOD (or bist in progress/never run) 821215976Sjmallett - 1: BAD */ 822215976Sjmallett uint64_t p1_bwb : 1; /**< Bist Results for P1_BWB RAM 823215976Sjmallett - 0: GOOD (or bist in progress/never run) 824215976Sjmallett - 1: BAD */ 825215976Sjmallett uint64_t p0_brf : 8; /**< Bist Results for P0_BRF RAM 826215976Sjmallett - 0: GOOD (or bist in progress/never run) 827215976Sjmallett - 1: BAD */ 828215976Sjmallett uint64_t p1_brf : 8; /**< Bist Results for P1_BRF RAM 829215976Sjmallett - 0: GOOD (or bist in progress/never run) 830215976Sjmallett - 1: BAD */ 831215976Sjmallett#else 832215976Sjmallett uint64_t p1_brf : 8; 833215976Sjmallett uint64_t p0_brf : 8; 834215976Sjmallett uint64_t p1_bwb : 1; 835215976Sjmallett uint64_t p0_bwb : 1; 836215976Sjmallett uint64_t crf : 1; 837215976Sjmallett uint64_t drf : 1; 838215976Sjmallett uint64_t gfu : 1; 839215976Sjmallett uint64_t ifu : 1; 840215976Sjmallett uint64_t crq : 1; 841215976Sjmallett uint64_t reserved_23_63 : 41; 842215976Sjmallett#endif 843215976Sjmallett } s; 844215976Sjmallett struct cvmx_dfa_bst1_cn31xx 845215976Sjmallett { 846215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 847215976Sjmallett uint64_t reserved_23_63 : 41; 848215976Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 849215976Sjmallett - 0: GOOD (or bist in progress/never run) 850215976Sjmallett - 1: BAD */ 851215976Sjmallett uint64_t ifu : 1; /**< Bist Results for IFU RAM 852215976Sjmallett - 0: GOOD (or bist in progress/never run) 853215976Sjmallett - 1: BAD */ 854215976Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 855215976Sjmallett - 0: GOOD (or bist in progress/never run) 856215976Sjmallett - 1: BAD */ 857215976Sjmallett uint64_t drf : 1; /**< Bist Results for DRF RAM 858215976Sjmallett - 0: GOOD (or bist in progress/never run) 859215976Sjmallett - 1: BAD */ 860215976Sjmallett uint64_t crf : 1; /**< Bist Results for CRF RAM 861215976Sjmallett - 0: GOOD (or bist in progress/never run) 862215976Sjmallett - 1: BAD */ 863215976Sjmallett uint64_t reserved_0_17 : 18; 864215976Sjmallett#else 865215976Sjmallett uint64_t reserved_0_17 : 18; 866215976Sjmallett uint64_t crf : 1; 867215976Sjmallett uint64_t drf : 1; 868215976Sjmallett uint64_t gfu : 1; 869215976Sjmallett uint64_t ifu : 1; 870215976Sjmallett uint64_t crq : 1; 871215976Sjmallett uint64_t reserved_23_63 : 41; 872215976Sjmallett#endif 873215976Sjmallett } cn31xx; 874215976Sjmallett struct cvmx_dfa_bst1_s cn38xx; 875215976Sjmallett struct cvmx_dfa_bst1_s cn38xxp2; 876215976Sjmallett struct cvmx_dfa_bst1_cn58xx 877215976Sjmallett { 878215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 879215976Sjmallett uint64_t reserved_23_63 : 41; 880215976Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 881215976Sjmallett - 0: GOOD (or bist in progress/never run) 882215976Sjmallett - 1: BAD */ 883215976Sjmallett uint64_t ifu : 1; /**< Bist Results for IFU RAM 884215976Sjmallett - 0: GOOD (or bist in progress/never run) 885215976Sjmallett - 1: BAD */ 886215976Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 887215976Sjmallett - 0: GOOD (or bist in progress/never run) 888215976Sjmallett - 1: BAD */ 889215976Sjmallett uint64_t reserved_19_19 : 1; 890215976Sjmallett uint64_t crf : 1; /**< Bist Results for CRF RAM 891215976Sjmallett - 0: GOOD (or bist in progress/never run) 892215976Sjmallett - 1: BAD */ 893215976Sjmallett uint64_t p0_bwb : 1; /**< Bist Results for P0_BWB RAM 894215976Sjmallett - 0: GOOD (or bist in progress/never run) 895215976Sjmallett - 1: BAD */ 896215976Sjmallett uint64_t p1_bwb : 1; /**< Bist Results for P1_BWB RAM 897215976Sjmallett - 0: GOOD (or bist in progress/never run) 898215976Sjmallett - 1: BAD */ 899215976Sjmallett uint64_t p0_brf : 8; /**< Bist Results for P0_BRF RAM 900215976Sjmallett - 0: GOOD (or bist in progress/never run) 901215976Sjmallett - 1: BAD */ 902215976Sjmallett uint64_t p1_brf : 8; /**< Bist Results for P1_BRF RAM 903215976Sjmallett - 0: GOOD (or bist in progress/never run) 904215976Sjmallett - 1: BAD */ 905215976Sjmallett#else 906215976Sjmallett uint64_t p1_brf : 8; 907215976Sjmallett uint64_t p0_brf : 8; 908215976Sjmallett uint64_t p1_bwb : 1; 909215976Sjmallett uint64_t p0_bwb : 1; 910215976Sjmallett uint64_t crf : 1; 911215976Sjmallett uint64_t reserved_19_19 : 1; 912215976Sjmallett uint64_t gfu : 1; 913215976Sjmallett uint64_t ifu : 1; 914215976Sjmallett uint64_t crq : 1; 915215976Sjmallett uint64_t reserved_23_63 : 41; 916215976Sjmallett#endif 917215976Sjmallett } cn58xx; 918215976Sjmallett struct cvmx_dfa_bst1_cn58xx cn58xxp1; 919215976Sjmallett}; 920215976Sjmalletttypedef union cvmx_dfa_bst1 cvmx_dfa_bst1_t; 921215976Sjmallett 922215976Sjmallett/** 923215976Sjmallett * cvmx_dfa_cfg 924215976Sjmallett * 925215976Sjmallett * Specify the RSL base addresses for the block 926215976Sjmallett * 927215976Sjmallett * DFA_CFG = DFA Configuration 928215976Sjmallett * 929215976Sjmallett * Description: 930215976Sjmallett */ 931215976Sjmallettunion cvmx_dfa_cfg 932215976Sjmallett{ 933215976Sjmallett uint64_t u64; 934215976Sjmallett struct cvmx_dfa_cfg_s 935215976Sjmallett { 936215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 937215976Sjmallett uint64_t reserved_4_63 : 60; 938215976Sjmallett uint64_t nrpl_ena : 1; /**< When set, allows the per-node replication feature to be 939215976Sjmallett enabled. 940215976Sjmallett In 36-bit mode: The IWORD0[31:30]=SNREPL field AND 941215976Sjmallett bits [21:20] of the Next Node ptr are used in generating 942215976Sjmallett the next node address (see OCTEON HRM - DFA Chapter for 943215976Sjmallett psuedo-code of DTE next node address generation). 944215976Sjmallett NOTE: When NRPL_ENA=1 and IWORD0[TY]=1(36b mode), 945215976Sjmallett (regardless of IWORD0[NRPLEN]), the Resultant Word1+ 946215976Sjmallett [[47:44],[23:20]] = Next Node's [27:20] bits. This allows 947215976Sjmallett SW to use the RESERVED bits of the final node for SW 948215976Sjmallett caching. Also, if required, SW will use [22:21]=Node 949215976Sjmallett Replication to re-start the same graph walk(if graph 950215976Sjmallett walk prematurely terminated (ie: DATA_GONE). 951215976Sjmallett In 18-bit mode: The IWORD0[31:30]=SNREPL field AND 952215976Sjmallett bit [16:14] of the Next Node ptr are used in generating 953215976Sjmallett the next node address (see OCTEON HRM - DFA Chapter for 954215976Sjmallett psuedo-code of DTE next node address generation). 955215976Sjmallett If (IWORD0[NREPLEN]=1 and DFA_CFG[NRPL_ENA]=1) [ 956215976Sjmallett If next node ptr[16] is set [ 957215976Sjmallett next node ptr[15:14] indicates the next node repl 958215976Sjmallett next node ptr[13:0] indicates the position of the 959215976Sjmallett node relative to the first normal node (i.e. 960215976Sjmallett IWORD3[Msize] must be added to get the final node) 961215976Sjmallett ] 962215976Sjmallett else If next node ptr[16] is not set [ 963215976Sjmallett next node ptr[15:0] indicates the next node id 964215976Sjmallett next node repl = 0 965215976Sjmallett ] 966215976Sjmallett ] 967215976Sjmallett NOTE: For 18b node replication, MAX node space=64KB(2^16) 968215976Sjmallett is used in detecting terminal node space(see HRM for full 969215976Sjmallett description). 970215976Sjmallett NOTE: The DFA graphs MUST BE built/written to DFA LLM memory 971215976Sjmallett aware of the "per-node" replication. */ 972215976Sjmallett uint64_t nxor_ena : 1; /**< When set, allows the DTE Instruction IWORD0[NXOREN] 973215976Sjmallett to be used to enable/disable the per-node address 'scramble' 974215976Sjmallett of the LLM address to lessen the effects of bank conflicts. 975215976Sjmallett If IWORD0[NXOREN] is also set, then: 976215976Sjmallett In 36-bit mode: The node_Id[7:0] 8-bit value is XORed 977215976Sjmallett against the LLM address addr[9:2]. 978215976Sjmallett In 18-bit mode: The node_id[6:0] 7-bit value is XORed 979215976Sjmallett against the LLM address addr[8:2]. (note: we don't address 980215976Sjmallett scramble outside the mode's node space). 981215976Sjmallett NOTE: The DFA graphs MUST BE built/written to DFA LLM memory 982215976Sjmallett aware of the "per-node" address scramble. 983215976Sjmallett NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph 984215976Sjmallett read/write operations. */ 985215976Sjmallett uint64_t gxor_ena : 1; /**< When set, the DTE Instruction IWORD0[GXOR] 986215976Sjmallett field is used to 'scramble' the LLM address 987215976Sjmallett to lessen the effects of bank conflicts. 988215976Sjmallett In 36-bit mode: The GXOR[7:0] 8-bit value is XORed 989215976Sjmallett against the LLM address addr[9:2]. 990215976Sjmallett In 18-bit mode: GXOR[6:0] 7-bit value is XORed against 991215976Sjmallett the LLM address addr[8:2]. (note: we don't address 992215976Sjmallett scramble outside the mode's node space) 993215976Sjmallett NOTE: The DFA graphs MUST BE built/written to DFA LLM memory 994215976Sjmallett aware of the "per-graph" address scramble. 995215976Sjmallett NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph 996215976Sjmallett read/write operations. */ 997215976Sjmallett uint64_t sarb : 1; /**< DFA Source Arbiter Mode 998215976Sjmallett Selects the arbitration mode used to select DFA 999215976Sjmallett requests issued from either CP2 or the DTE (NCB-CSR 1000215976Sjmallett or DFA HW engine). 1001215976Sjmallett - 0: Fixed Priority [Highest=CP2, Lowest=DTE] 1002215976Sjmallett - 1: Round-Robin 1003215976Sjmallett NOTE: This should only be written to a different value 1004215976Sjmallett during power-on SW initialization. */ 1005215976Sjmallett#else 1006215976Sjmallett uint64_t sarb : 1; 1007215976Sjmallett uint64_t gxor_ena : 1; 1008215976Sjmallett uint64_t nxor_ena : 1; 1009215976Sjmallett uint64_t nrpl_ena : 1; 1010215976Sjmallett uint64_t reserved_4_63 : 60; 1011215976Sjmallett#endif 1012215976Sjmallett } s; 1013215976Sjmallett struct cvmx_dfa_cfg_s cn38xx; 1014215976Sjmallett struct cvmx_dfa_cfg_cn38xxp2 1015215976Sjmallett { 1016215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1017215976Sjmallett uint64_t reserved_1_63 : 63; 1018215976Sjmallett uint64_t sarb : 1; /**< DFA Source Arbiter Mode 1019215976Sjmallett Selects the arbitration mode used to select DFA 1020215976Sjmallett requests issued from either CP2 or the DTE (NCB-CSR 1021215976Sjmallett or DFA HW engine). 1022215976Sjmallett - 0: Fixed Priority [Highest=CP2, Lowest=DTE] 1023215976Sjmallett - 1: Round-Robin 1024215976Sjmallett NOTE: This should only be written to a different value 1025215976Sjmallett during power-on SW initialization. */ 1026215976Sjmallett#else 1027215976Sjmallett uint64_t sarb : 1; 1028215976Sjmallett uint64_t reserved_1_63 : 63; 1029215976Sjmallett#endif 1030215976Sjmallett } cn38xxp2; 1031215976Sjmallett struct cvmx_dfa_cfg_s cn58xx; 1032215976Sjmallett struct cvmx_dfa_cfg_s cn58xxp1; 1033215976Sjmallett}; 1034215976Sjmalletttypedef union cvmx_dfa_cfg cvmx_dfa_cfg_t; 1035215976Sjmallett 1036215976Sjmallett/** 1037215976Sjmallett * cvmx_dfa_config 1038215976Sjmallett * 1039215976Sjmallett * Specify the RSL base addresses for the block 1040215976Sjmallett * 1041215976Sjmallett * DFA_CONFIG = DFA Configuration Register 1042215976Sjmallett * 1043215976Sjmallett * Description: 1044215976Sjmallett */ 1045215976Sjmallettunion cvmx_dfa_config 1046215976Sjmallett{ 1047215976Sjmallett uint64_t u64; 1048215976Sjmallett struct cvmx_dfa_config_s 1049215976Sjmallett { 1050215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1051215976Sjmallett uint64_t reserved_9_63 : 55; 1052215976Sjmallett uint64_t repl_ena : 1; /**< Replication Mode Enable 1053215976Sjmallett *** o63-P2 NEW *** 1054215976Sjmallett When set, enables replication mode performance enhancement 1055215976Sjmallett feature. This enables the DFA to communicate address 1056215976Sjmallett replication information during memory references to the DFM 1057215976Sjmallett (memory controller). This in turn is used by the DFM to support 1058215976Sjmallett graph data in multiple banks (or bank sets), so that the least 1059215976Sjmallett full bank can be selected to minimize the effects of DDR3 bank 1060215976Sjmallett conflicts (ie: tRC=row cycle time). 1061215976Sjmallett SWNOTE: Using this mode requires the DFA SW compiler and DFA 1062215976Sjmallett driver to be aware of the o63-P2 address replication changes. 1063215976Sjmallett This involves changes to the MLOAD/GWALK DFA instruction format 1064215976Sjmallett (see: IWORD2.SREPL), as well as changes to node arc and metadata 1065215976Sjmallett definitions which now support an additional REPL field. 1066215976Sjmallett When clear, replication mode is disabled, and DFA will interpret 1067215976Sjmallett o63-P1 DFA instructions and node-arc formats which DO NOT have 1068215976Sjmallett address replication information. */ 1069215976Sjmallett uint64_t clmskcrip : 4; /**< Cluster Cripple Mask 1070215976Sjmallett A one in each bit of the mask represents which DTE cluster to 1071215976Sjmallett cripple. 1072215976Sjmallett NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0] 1073215976Sjmallett is the only bit used. 1074215976Sjmallett o2 has 4 clusters, where all CLMSKCRIP mask bits are used. 1075215976Sjmallett SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will 1076215976Sjmallett be forced into this register at reset. Any fuse bits that 1077215976Sjmallett contain '1' will be disallowed during a write and will always 1078215976Sjmallett be read as '1'. */ 1079215976Sjmallett uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each 1080215976Sjmallett cluster. Typically DTE_CLCRIP=0 which enables all DTEs 1081215976Sjmallett within each cluster. However, when the DFA performance 1082215976Sjmallett counters are used, SW may want to limit the \#of DTEs 1083215976Sjmallett per cluster available, as there are only 4 parallel 1084215976Sjmallett performance counters. 1085215976Sjmallett DTE_CLCRIP | \#DTEs crippled(per cluster) 1086215976Sjmallett ------------+----------------------------- 1087215976Sjmallett 0 | 0 DTE[15:0]:ON 1088215976Sjmallett 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON 1089215976Sjmallett 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON 1090215976Sjmallett 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON 1091215976Sjmallett 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON 1092215976Sjmallett 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON 1093215976Sjmallett 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON 1094215976Sjmallett 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON 1095215976Sjmallett NOTE: Higher numbered DTEs are crippled first. For instance, 1096215976Sjmallett on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then 1097215976Sjmallett DTE#s [15:8] within the cluster are crippled and only 1098215976Sjmallett DTE#s [7:0] are available. 1099215976Sjmallett IMPNOTE: The encodings are done in such a way as to later 1100215976Sjmallett be used with fuses (for future o2 revisions which will disable 1101215976Sjmallett some \#of DTEs). Blowing a fuse has the effect that there will 1102215976Sjmallett always be fewer DTEs available. [ie: we never want a customer 1103215976Sjmallett to blow additional fuses to get more DTEs]. 1104215976Sjmallett SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will 1105215976Sjmallett be forced into this register at reset. Any fuse bits that 1106215976Sjmallett contain '1' will be disallowed during a write and will always 1107215976Sjmallett be read as '1'. */ 1108215976Sjmallett uint64_t dteclkdis : 1; /**< DFA Clock Disable Source 1109215976Sjmallett When SET, the DFA clocks for DTE(thread engine) 1110215976Sjmallett operation are disabled (to conserve overall chip clocking 1111215976Sjmallett power when the DFA function is not used). 1112215976Sjmallett NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR 1113215976Sjmallett operations to the DFA (will result in NCB Bus Timeout 1114215976Sjmallett errors). 1115215976Sjmallett NOTE: This should only be written to a different value 1116215976Sjmallett during power-on SW initialization. 1117215976Sjmallett SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will 1118215976Sjmallett be forced into this register at reset. If the fuse bit 1119215976Sjmallett contains '1', writes to DTECLKDIS are disallowed and 1120215976Sjmallett will always be read as '1'. */ 1121215976Sjmallett#else 1122215976Sjmallett uint64_t dteclkdis : 1; 1123215976Sjmallett uint64_t cldtecrip : 3; 1124215976Sjmallett uint64_t clmskcrip : 4; 1125215976Sjmallett uint64_t repl_ena : 1; 1126215976Sjmallett uint64_t reserved_9_63 : 55; 1127215976Sjmallett#endif 1128215976Sjmallett } s; 1129215976Sjmallett struct cvmx_dfa_config_s cn63xx; 1130215976Sjmallett struct cvmx_dfa_config_cn63xxp1 1131215976Sjmallett { 1132215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1133215976Sjmallett uint64_t reserved_8_63 : 56; 1134215976Sjmallett uint64_t clmskcrip : 4; /**< Cluster Cripple Mask 1135215976Sjmallett A one in each bit of the mask represents which DTE cluster to 1136215976Sjmallett cripple. 1137215976Sjmallett NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0] 1138215976Sjmallett is the only bit used. 1139215976Sjmallett o2 has 4 clusters, where all CLMSKCRIP mask bits are used. 1140215976Sjmallett SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will 1141215976Sjmallett be forced into this register at reset. Any fuse bits that 1142215976Sjmallett contain '1' will be disallowed during a write and will always 1143215976Sjmallett be read as '1'. */ 1144215976Sjmallett uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each 1145215976Sjmallett cluster. Typically DTE_CLCRIP=0 which enables all DTEs 1146215976Sjmallett within each cluster. However, when the DFA performance 1147215976Sjmallett counters are used, SW may want to limit the \#of DTEs 1148215976Sjmallett per cluster available, as there are only 4 parallel 1149215976Sjmallett performance counters. 1150215976Sjmallett DTE_CLCRIP | \#DTEs crippled(per cluster) 1151215976Sjmallett ------------+----------------------------- 1152215976Sjmallett 0 | 0 DTE[15:0]:ON 1153215976Sjmallett 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON 1154215976Sjmallett 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON 1155215976Sjmallett 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON 1156215976Sjmallett 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON 1157215976Sjmallett 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON 1158215976Sjmallett 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON 1159215976Sjmallett 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON 1160215976Sjmallett NOTE: Higher numbered DTEs are crippled first. For instance, 1161215976Sjmallett on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then 1162215976Sjmallett DTE#s [15:8] within the cluster are crippled and only 1163215976Sjmallett DTE#s [7:0] are available. 1164215976Sjmallett IMPNOTE: The encodings are done in such a way as to later 1165215976Sjmallett be used with fuses (for future o2 revisions which will disable 1166215976Sjmallett some \#of DTEs). Blowing a fuse has the effect that there will 1167215976Sjmallett always be fewer DTEs available. [ie: we never want a customer 1168215976Sjmallett to blow additional fuses to get more DTEs]. 1169215976Sjmallett SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will 1170215976Sjmallett be forced into this register at reset. Any fuse bits that 1171215976Sjmallett contain '1' will be disallowed during a write and will always 1172215976Sjmallett be read as '1'. */ 1173215976Sjmallett uint64_t dteclkdis : 1; /**< DFA Clock Disable Source 1174215976Sjmallett When SET, the DFA clocks for DTE(thread engine) 1175215976Sjmallett operation are disabled (to conserve overall chip clocking 1176215976Sjmallett power when the DFA function is not used). 1177215976Sjmallett NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR 1178215976Sjmallett operations to the DFA (will result in NCB Bus Timeout 1179215976Sjmallett errors). 1180215976Sjmallett NOTE: This should only be written to a different value 1181215976Sjmallett during power-on SW initialization. 1182215976Sjmallett SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will 1183215976Sjmallett be forced into this register at reset. If the fuse bit 1184215976Sjmallett contains '1', writes to DTECLKDIS are disallowed and 1185215976Sjmallett will always be read as '1'. */ 1186215976Sjmallett#else 1187215976Sjmallett uint64_t dteclkdis : 1; 1188215976Sjmallett uint64_t cldtecrip : 3; 1189215976Sjmallett uint64_t clmskcrip : 4; 1190215976Sjmallett uint64_t reserved_8_63 : 56; 1191215976Sjmallett#endif 1192215976Sjmallett } cn63xxp1; 1193215976Sjmallett}; 1194215976Sjmalletttypedef union cvmx_dfa_config cvmx_dfa_config_t; 1195215976Sjmallett 1196215976Sjmallett/** 1197215976Sjmallett * cvmx_dfa_control 1198215976Sjmallett * 1199215976Sjmallett * DFA_CONTROL = DFA Control Register 1200215976Sjmallett * 1201215976Sjmallett * Description: 1202215976Sjmallett */ 1203215976Sjmallettunion cvmx_dfa_control 1204215976Sjmallett{ 1205215976Sjmallett uint64_t u64; 1206215976Sjmallett struct cvmx_dfa_control_s 1207215976Sjmallett { 1208215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1209215976Sjmallett uint64_t reserved_10_63 : 54; 1210215976Sjmallett uint64_t sbdnum : 4; /**< SBD Debug Entry# 1211215976Sjmallett *FOR INTERNAL USE ONLY* 1212215976Sjmallett DFA Scoreboard debug control 1213215976Sjmallett Selects which one of 8 DFA Scoreboard entries is 1214215976Sjmallett latched into the DFA_SBD_DBG[0-3] registers. */ 1215215976Sjmallett uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 1216215976Sjmallett *FOR INTERNAL USE ONLY* 1217215976Sjmallett DFA Scoreboard debug control 1218215976Sjmallett When written with a '1', the DFA Scoreboard Debug 1219215976Sjmallett registers (DFA_SBD_DBG[0-3]) are all locked down. 1220215976Sjmallett This allows SW to lock down the contents of the entire 1221215976Sjmallett SBD for a single instant in time. All subsequent reads 1222215976Sjmallett of the DFA scoreboard registers will return the data 1223215976Sjmallett from that instant in time. */ 1224215976Sjmallett uint64_t reserved_3_4 : 2; 1225215976Sjmallett uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 1226215976Sjmallett (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 1227215976Sjmallett NOTE: This should only be written to a different value 1228215976Sjmallett during power-on SW initialization. */ 1229215976Sjmallett uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 1230215976Sjmallett (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 1231215976Sjmallett NOTE: This should only be written to a different value 1232215976Sjmallett during power-on SW initialization. */ 1233215976Sjmallett uint64_t imode : 1; /**< NCB-Inbound Arbiter 1234215976Sjmallett (0=FP [LP=NRQ,HP=NRP], 1=RR) 1235215976Sjmallett NOTE: This should only be written to a different value 1236215976Sjmallett during power-on SW initialization. */ 1237215976Sjmallett#else 1238215976Sjmallett uint64_t imode : 1; 1239215976Sjmallett uint64_t qmode : 1; 1240215976Sjmallett uint64_t pmode : 1; 1241215976Sjmallett uint64_t reserved_3_4 : 2; 1242215976Sjmallett uint64_t sbdlck : 1; 1243215976Sjmallett uint64_t sbdnum : 4; 1244215976Sjmallett uint64_t reserved_10_63 : 54; 1245215976Sjmallett#endif 1246215976Sjmallett } s; 1247215976Sjmallett struct cvmx_dfa_control_s cn63xx; 1248215976Sjmallett struct cvmx_dfa_control_s cn63xxp1; 1249215976Sjmallett}; 1250215976Sjmalletttypedef union cvmx_dfa_control cvmx_dfa_control_t; 1251215976Sjmallett 1252215976Sjmallett/** 1253215976Sjmallett * cvmx_dfa_dbell 1254215976Sjmallett * 1255215976Sjmallett * DFA_DBELL = DFA Doorbell Register 1256215976Sjmallett * 1257215976Sjmallett * Description: 1258215976Sjmallett * NOTE: To write to the DFA_DBELL register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b00. 1259215976Sjmallett * To read the DFA_DBELL register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b00. 1260215976Sjmallett * 1261215976Sjmallett * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DBELL register do not take effect. 1262215976Sjmallett * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DBELL register do not take effect. 1263215976Sjmallett */ 1264215976Sjmallettunion cvmx_dfa_dbell 1265215976Sjmallett{ 1266215976Sjmallett uint64_t u64; 1267215976Sjmallett struct cvmx_dfa_dbell_s 1268215976Sjmallett { 1269215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1270215976Sjmallett uint64_t reserved_20_63 : 44; 1271215976Sjmallett uint64_t dbell : 20; /**< Represents the cumulative total of pending 1272215976Sjmallett DFA instructions which SW has previously written 1273215976Sjmallett into the DFA Instruction FIFO (DIF) in main memory. 1274215976Sjmallett Each DFA instruction contains a fixed size 32B 1275215976Sjmallett instruction word which is executed by the DFA HW. 1276215976Sjmallett The DBL register can hold up to 1M-1 (2^20-1) 1277215976Sjmallett pending DFA instruction requests. 1278215976Sjmallett During a read (by SW), the 'most recent' contents 1279215976Sjmallett of the DFA_DBELL register are returned at the time 1280215976Sjmallett the NCB-INB bus is driven. 1281215976Sjmallett NOTE: Since DFA HW updates this register, its 1282215976Sjmallett contents are unpredictable in SW. */ 1283215976Sjmallett#else 1284215976Sjmallett uint64_t dbell : 20; 1285215976Sjmallett uint64_t reserved_20_63 : 44; 1286215976Sjmallett#endif 1287215976Sjmallett } s; 1288215976Sjmallett struct cvmx_dfa_dbell_s cn31xx; 1289215976Sjmallett struct cvmx_dfa_dbell_s cn38xx; 1290215976Sjmallett struct cvmx_dfa_dbell_s cn38xxp2; 1291215976Sjmallett struct cvmx_dfa_dbell_s cn58xx; 1292215976Sjmallett struct cvmx_dfa_dbell_s cn58xxp1; 1293215976Sjmallett struct cvmx_dfa_dbell_s cn63xx; 1294215976Sjmallett struct cvmx_dfa_dbell_s cn63xxp1; 1295215976Sjmallett}; 1296215976Sjmalletttypedef union cvmx_dfa_dbell cvmx_dfa_dbell_t; 1297215976Sjmallett 1298215976Sjmallett/** 1299215976Sjmallett * cvmx_dfa_ddr2_addr 1300215976Sjmallett * 1301215976Sjmallett * DFA_DDR2_ADDR = DFA DDR2 fclk-domain Memory Address Config Register 1302215976Sjmallett * 1303215976Sjmallett * 1304215976Sjmallett * Description: The following registers are used to compose the DFA's DDR2 address into ROW/COL/BNK 1305215976Sjmallett * etc. 1306215976Sjmallett */ 1307215976Sjmallettunion cvmx_dfa_ddr2_addr 1308215976Sjmallett{ 1309215976Sjmallett uint64_t u64; 1310215976Sjmallett struct cvmx_dfa_ddr2_addr_s 1311215976Sjmallett { 1312215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1313215976Sjmallett uint64_t reserved_9_63 : 55; 1314215976Sjmallett uint64_t rdimm_ena : 1; /**< If there is a need to insert a register chip on the 1315215976Sjmallett system (the equivalent of a registered DIMM) to 1316215976Sjmallett provide better setup for the command and control bits 1317215976Sjmallett turn this mode on. 1318215976Sjmallett RDIMM_ENA 1319215976Sjmallett 0 Registered Mode OFF 1320215976Sjmallett 1 Registered Mode ON */ 1321215976Sjmallett uint64_t num_rnks : 2; /**< NUM_RNKS is programmed based on how many ranks there 1322215976Sjmallett are in the system. This needs to be programmed correctly 1323215976Sjmallett regardless of whether we are in RNK_LO mode or not. 1324215976Sjmallett NUM_RNKS \# of Ranks 1325215976Sjmallett 0 1 1326215976Sjmallett 1 2 1327215976Sjmallett 2 4 1328215976Sjmallett 3 RESERVED */ 1329215976Sjmallett uint64_t rnk_lo : 1; /**< When this mode is turned on, consecutive addresses 1330215976Sjmallett outside the bank boundary 1331215976Sjmallett are programmed to go to different ranks in order to 1332215976Sjmallett minimize bank conflicts. It is useful in 4-bank DDR2 1333215976Sjmallett parts based memory to extend out the \#physical banks 1334215976Sjmallett available and minimize bank conflicts. 1335215976Sjmallett On 8 bank ddr2 parts, this mode is not very useful 1336215976Sjmallett because this mode does come with 1337215976Sjmallett a penalty which is that every successive reads that 1338215976Sjmallett cross rank boundary will need a 1 cycle bubble 1339215976Sjmallett inserted to prevent bus turnaround conflicts. 1340215976Sjmallett RNK_LO 1341215976Sjmallett 0 - OFF 1342215976Sjmallett 1 - ON */ 1343215976Sjmallett uint64_t num_colrows : 3; /**< NUM_COLROWS is used to set the MSB of the ROW_ADDR 1344215976Sjmallett and the LSB of RANK address when not in RNK_LO mode. 1345215976Sjmallett Calculate the sum of \#COL and \#ROW and program the 1346215976Sjmallett controller appropriately 1347215976Sjmallett RANK_LSB \#COLs + \#ROWs 1348215976Sjmallett ------------------------------ 1349215976Sjmallett - 000: 22 1350215976Sjmallett - 001: 23 1351215976Sjmallett - 010: 24 1352215976Sjmallett - 011: 25 1353215976Sjmallett - 100-111: RESERVED */ 1354215976Sjmallett uint64_t num_cols : 2; /**< The Long word address that the controller receives 1355215976Sjmallett needs to be converted to Row, Col, Rank and Bank 1356215976Sjmallett addresses depending on the memory part's micro arch. 1357215976Sjmallett NUM_COL tells the controller how many colum bits 1358215976Sjmallett there are and the controller uses this info to map 1359215976Sjmallett the LSB of the row address 1360215976Sjmallett - 00: num_cols = 9 1361215976Sjmallett - 01: num_cols = 10 1362215976Sjmallett - 10: num_cols = 11 1363215976Sjmallett - 11: RESERVED */ 1364215976Sjmallett#else 1365215976Sjmallett uint64_t num_cols : 2; 1366215976Sjmallett uint64_t num_colrows : 3; 1367215976Sjmallett uint64_t rnk_lo : 1; 1368215976Sjmallett uint64_t num_rnks : 2; 1369215976Sjmallett uint64_t rdimm_ena : 1; 1370215976Sjmallett uint64_t reserved_9_63 : 55; 1371215976Sjmallett#endif 1372215976Sjmallett } s; 1373215976Sjmallett struct cvmx_dfa_ddr2_addr_s cn31xx; 1374215976Sjmallett}; 1375215976Sjmalletttypedef union cvmx_dfa_ddr2_addr cvmx_dfa_ddr2_addr_t; 1376215976Sjmallett 1377215976Sjmallett/** 1378215976Sjmallett * cvmx_dfa_ddr2_bus 1379215976Sjmallett * 1380215976Sjmallett * DFA_DDR2_BUS = DFA DDR Bus Activity Counter 1381215976Sjmallett * 1382215976Sjmallett * 1383215976Sjmallett * Description: This counter counts \# cycles that the memory bus is doing a read/write/command 1384215976Sjmallett * Useful to benchmark the bus utilization as a ratio of 1385215976Sjmallett * \#Cycles of Data Transfer/\#Cycles since init or 1386215976Sjmallett * \#Cycles of Data Transfer/\#Cycles that memory controller is active 1387215976Sjmallett */ 1388215976Sjmallettunion cvmx_dfa_ddr2_bus 1389215976Sjmallett{ 1390215976Sjmallett uint64_t u64; 1391215976Sjmallett struct cvmx_dfa_ddr2_bus_s 1392215976Sjmallett { 1393215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1394215976Sjmallett uint64_t reserved_47_63 : 17; 1395215976Sjmallett uint64_t bus_cnt : 47; /**< Counter counts the \# cycles of Data transfer */ 1396215976Sjmallett#else 1397215976Sjmallett uint64_t bus_cnt : 47; 1398215976Sjmallett uint64_t reserved_47_63 : 17; 1399215976Sjmallett#endif 1400215976Sjmallett } s; 1401215976Sjmallett struct cvmx_dfa_ddr2_bus_s cn31xx; 1402215976Sjmallett}; 1403215976Sjmalletttypedef union cvmx_dfa_ddr2_bus cvmx_dfa_ddr2_bus_t; 1404215976Sjmallett 1405215976Sjmallett/** 1406215976Sjmallett * cvmx_dfa_ddr2_cfg 1407215976Sjmallett * 1408215976Sjmallett * DFA_DDR2_CFG = DFA DDR2 fclk-domain Memory Configuration \#0 Register 1409215976Sjmallett * 1410215976Sjmallett * Description: 1411215976Sjmallett */ 1412215976Sjmallettunion cvmx_dfa_ddr2_cfg 1413215976Sjmallett{ 1414215976Sjmallett uint64_t u64; 1415215976Sjmallett struct cvmx_dfa_ddr2_cfg_s 1416215976Sjmallett { 1417215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1418215976Sjmallett uint64_t reserved_41_63 : 23; 1419215976Sjmallett uint64_t trfc : 5; /**< Establishes tRFC(from DDR2 data sheets) in \# of 1420215976Sjmallett 4 fclk intervals. 1421215976Sjmallett General Equation: 1422215976Sjmallett TRFC(csr) = ROUNDUP[tRFC(data-sheet-ns)/(4 * fclk(ns))] 1423215976Sjmallett Example: 1424215976Sjmallett tRFC(data-sheet-ns) = 127.5ns 1425215976Sjmallett Operational Frequency: 533MHz DDR rate 1426215976Sjmallett [fclk=266MHz(3.75ns)] 1427215976Sjmallett Then: 1428215976Sjmallett TRFC(csr) = ROUNDUP[127.5ns/(4 * 3.75ns)] 1429215976Sjmallett = 9 */ 1430215976Sjmallett uint64_t mrs_pgm : 1; /**< When clear, the HW initialization sequence fixes 1431215976Sjmallett some of the *MRS register bit definitions. 1432215976Sjmallett EMRS: 1433215976Sjmallett A[14:13] = 0 RESERVED 1434215976Sjmallett A[12] = 0 Output Buffers Enabled (FIXED) 1435215976Sjmallett A[11] = 0 RDQS Disabled (FIXED) 1436215976Sjmallett A[10] = 0 DQSn Enabled (FIXED) 1437215976Sjmallett A[9:7] = 0 OCD Not supported (FIXED) 1438215976Sjmallett A[6] = 0 RTT Disabled (FIXED) 1439215976Sjmallett A[5:3]=DFA_DDR2_TMG[ADDLAT] (if DFA_DDR2_TMG[POCAS]=1) 1440215976Sjmallett Additive LATENCY (Programmable) 1441215976Sjmallett A[2]=0 RTT Disabled (FIXED) 1442215976Sjmallett A[1]=DFA_DDR2_TMG[DIC] (Programmable) 1443215976Sjmallett A[0] = 0 DLL Enabled (FIXED) 1444215976Sjmallett MRS: 1445215976Sjmallett A[14:13] = 0 RESERVED 1446215976Sjmallett A[12] = 0 Fast Active Power Down Mode (FIXED) 1447215976Sjmallett A[11:9] = DFA_DDR2_TMG[TWR](Programmable) 1448215976Sjmallett A[8] = 1 DLL Reset (FIXED) 1449215976Sjmallett A[7] = 0 Test Mode (FIXED) 1450215976Sjmallett A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (Programmable) 1451215976Sjmallett A[3] = 0 Burst Type(must be 0:Sequential) (FIXED) 1452215976Sjmallett A[2:0] = 2 Burst Length=4 (must be 0:Sequential) (FIXED) 1453215976Sjmallett When set, the HW initialization sequence sources 1454215976Sjmallett the DFA_DDR2_MRS, DFA_DDR2_EMRS registers which are 1455215976Sjmallett driven onto the DFA_A[] pins. (this allows the MRS/EMRS 1456215976Sjmallett fields to be completely programmable - however care 1457215976Sjmallett must be taken by software). 1458215976Sjmallett This mode is useful for customers who wish to: 1459215976Sjmallett 1) override the FIXED definitions(above), or 1460215976Sjmallett 2) Use a "clamshell mode" of operation where the 1461215976Sjmallett address bits(per rank) are swizzled on the 1462215976Sjmallett board to reduce stub lengths for optimal 1463215976Sjmallett frequency operation. 1464215976Sjmallett Use this in combination with DFA_DDR2_CFG[RNK_MSK] 1465215976Sjmallett to specify the INIT sequence for each of the 4 1466215976Sjmallett supported ranks. */ 1467215976Sjmallett uint64_t fpip : 3; /**< Early Fill Programmable Pipe [\#fclks] 1468215976Sjmallett This field dictates the \#fclks prior to the arrival 1469215976Sjmallett of fill data(in fclk domain), to start the 'early' fill 1470215976Sjmallett command pipe (in the eclk domain) so as to minimize the 1471215976Sjmallett overall fill latency. 1472215976Sjmallett The programmable early fill command signal is synchronized 1473215976Sjmallett into the eclk domain, where it is used to pull data out of 1474215976Sjmallett asynchronous RAM as fast as possible. 1475215976Sjmallett NOTE: A value of FPIP=0 is the 'safest' setting and will 1476215976Sjmallett result in the early fill command pipe starting in the 1477215976Sjmallett same cycle as the fill data. 1478215976Sjmallett General Equation: (for FPIP) 1479215976Sjmallett FPIP <= MIN[6, (ROUND_DOWN[6/EF_RATIO] + 1)] 1480215976Sjmallett where: 1481215976Sjmallett EF_RATIO = ECLK/FCLK Ratio [eclk(MHz)/fclk(MHz)] 1482215976Sjmallett Example: FCLK=200MHz/ECLK=600MHz 1483215976Sjmallett FPIP = MIN[6, (ROUND_DOWN[6/(600/200))] + 1)] 1484215976Sjmallett FPIP <= 3 */ 1485215976Sjmallett uint64_t reserved_29_31 : 3; 1486215976Sjmallett uint64_t ref_int : 13; /**< Refresh Interval (represented in \#of fclk 1487215976Sjmallett increments). 1488215976Sjmallett Each refresh interval will generate a single 1489215976Sjmallett auto-refresh command sequence which implicitly targets 1490215976Sjmallett all banks within the device: 1491215976Sjmallett Example: For fclk=200MHz(5ns)/400MHz(DDR): 1492215976Sjmallett trefint(ns) = [tREFI(max)=3.9us = 3900ns [datasheet] 1493215976Sjmallett REF_INT = ROUND_DOWN[(trefint/fclk)] 1494215976Sjmallett = ROUND_DOWN[(3900ns/5ns)] 1495215976Sjmallett = 780 fclks (0x30c) 1496215976Sjmallett NOTE: This should only be written to a different value 1497215976Sjmallett during power-on SW initialization. */ 1498215976Sjmallett uint64_t reserved_14_15 : 2; 1499215976Sjmallett uint64_t tskw : 2; /**< Board Skew (represented in \#fclks) 1500215976Sjmallett Represents additional board skew of DQ/DQS. 1501215976Sjmallett - 00: board-skew = 0 fclk 1502215976Sjmallett - 01: board-skew = 1 fclk 1503215976Sjmallett - 10: board-skew = 2 fclk 1504215976Sjmallett - 11: board-skew = 3 fclk 1505215976Sjmallett NOTE: This should only be written to a different value 1506215976Sjmallett during power-on SW initialization. */ 1507215976Sjmallett uint64_t rnk_msk : 4; /**< Controls the CS_N[3:0] during a) a HW Initialization 1508215976Sjmallett sequence (triggered by DFA_DDR2_CFG[INIT]) or 1509215976Sjmallett b) during a normal refresh sequence. If 1510215976Sjmallett the RNK_MSK[x]=1, the corresponding CS_N[x] is driven. 1511215976Sjmallett NOTE: This is required for DRAM used in a 1512215976Sjmallett clamshell configuration, since the address lines 1513215976Sjmallett carry Mode Register write data that is unique 1514215976Sjmallett per rank(or clam). In a clamshell configuration, 1515215976Sjmallett the N3K DFA_A[x] pin may be tied into Clam#0's A[x] 1516215976Sjmallett and also into Clam#1's 'mirrored' address bit A[y] 1517215976Sjmallett (eg: Clam0 sees A[5] and Clam1 sees A[15]). 1518215976Sjmallett To support clamshell designs, SW must initiate 1519215976Sjmallett separate HW init sequences each unique rank address 1520215976Sjmallett mapping. Before each HW init sequence is triggered, 1521215976Sjmallett SW must preload the DFA_DDR2_MRS/EMRS registers with 1522215976Sjmallett the data that will be driven onto the A[14:0] wires 1523215976Sjmallett during the EMRS/MRS mode register write(s). 1524215976Sjmallett NOTE: After the final HW initialization sequence has 1525215976Sjmallett been triggered, SW must wait 64K eclks before writing 1526215976Sjmallett the RNK_MSK[3:0] field = 3'b1111 (so that CS_N[3:0] 1527215976Sjmallett is driven during refresh sequences in normal operation. 1528215976Sjmallett NOTE: This should only be written to a different value 1529215976Sjmallett during power-on SW initialization. */ 1530215976Sjmallett uint64_t silo_qc : 1; /**< Enables Quarter Cycle move of the Rd sampling window */ 1531215976Sjmallett uint64_t silo_hc : 1; /**< A combination of SILO_HC, SILO_QC and TSKW 1532215976Sjmallett specifies the positioning of the sampling strobe 1533215976Sjmallett when receiving read data back from DDR2. This is 1534215976Sjmallett done to offset any board trace induced delay on 1535215976Sjmallett the DQ and DQS which inherently makes these 1536215976Sjmallett asynchronous with respect to the internal clk of 1537215976Sjmallett controller. TSKW moves this sampling window by 1538215976Sjmallett integer cycles. SILO_QC and HC move this quarter 1539215976Sjmallett and half a cycle respectively. */ 1540215976Sjmallett uint64_t sil_lat : 2; /**< Silo Latency (\#fclks): On reads, determines how many 1541215976Sjmallett additional fclks to wait (on top of CASLAT+1) before 1542215976Sjmallett pulling data out of the padring silos used for time 1543215976Sjmallett domain boundary crossing. 1544215976Sjmallett NOTE: This should only be written to a different value 1545215976Sjmallett during power-on SW initialization. */ 1546215976Sjmallett uint64_t bprch : 1; /**< Tristate Enable (back porch) (\#fclks) 1547215976Sjmallett On reads, allows user to control the shape of the 1548215976Sjmallett tristate disable back porch for the DQ data bus. 1549215976Sjmallett This parameter is also very dependent on the 1550215976Sjmallett RW_DLY and WR_DLY parameters and care must be 1551215976Sjmallett taken when programming these parameters to avoid 1552215976Sjmallett data bus contention. Valid range [0..2] 1553215976Sjmallett NOTE: This should only be written to a different value 1554215976Sjmallett during power-on SW initialization. */ 1555215976Sjmallett uint64_t fprch : 1; /**< Tristate Enable (front porch) (\#fclks) 1556215976Sjmallett On reads, allows user to control the shape of the 1557215976Sjmallett tristate disable front porch for the DQ data bus. 1558215976Sjmallett This parameter is also very dependent on the 1559215976Sjmallett RW_DLY and WR_DLY parameters and care must be 1560215976Sjmallett taken when programming these parameters to avoid 1561215976Sjmallett data bus contention. Valid range [0..2] 1562215976Sjmallett NOTE: This should only be written to a different value 1563215976Sjmallett during power-on SW initialization. */ 1564215976Sjmallett uint64_t init : 1; /**< When a '1' is written (and the previous value was '0'), 1565215976Sjmallett the HW init sequence(s) for the LLM Memory Port is 1566215976Sjmallett initiated. 1567215976Sjmallett NOTE: To initialize memory, SW must: 1568215976Sjmallett 1) Enable memory port 1569215976Sjmallett a) PRTENA=1 1570215976Sjmallett 2) Wait 200us (to ensure a stable clock 1571215976Sjmallett to the DDR2) - as per DDR2 spec. 1572215976Sjmallett 3) Write a '1' to the INIT which 1573215976Sjmallett will initiate a hardware initialization 1574215976Sjmallett sequence. 1575215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 1576215976Sjmallett cycles to ensure the HW init sequence has completed 1577215976Sjmallett before writing to ANY of the DFA_DDR2* registers. 1578215976Sjmallett NOTE: This should only be written to a different value 1579215976Sjmallett during power-on SW initialization. */ 1580215976Sjmallett uint64_t prtena : 1; /**< Enable DFA Memory 1581215976Sjmallett When enabled, this bit lets N3K be the default 1582215976Sjmallett driver for DFA-LLM memory port. */ 1583215976Sjmallett#else 1584215976Sjmallett uint64_t prtena : 1; 1585215976Sjmallett uint64_t init : 1; 1586215976Sjmallett uint64_t fprch : 1; 1587215976Sjmallett uint64_t bprch : 1; 1588215976Sjmallett uint64_t sil_lat : 2; 1589215976Sjmallett uint64_t silo_hc : 1; 1590215976Sjmallett uint64_t silo_qc : 1; 1591215976Sjmallett uint64_t rnk_msk : 4; 1592215976Sjmallett uint64_t tskw : 2; 1593215976Sjmallett uint64_t reserved_14_15 : 2; 1594215976Sjmallett uint64_t ref_int : 13; 1595215976Sjmallett uint64_t reserved_29_31 : 3; 1596215976Sjmallett uint64_t fpip : 3; 1597215976Sjmallett uint64_t mrs_pgm : 1; 1598215976Sjmallett uint64_t trfc : 5; 1599215976Sjmallett uint64_t reserved_41_63 : 23; 1600215976Sjmallett#endif 1601215976Sjmallett } s; 1602215976Sjmallett struct cvmx_dfa_ddr2_cfg_s cn31xx; 1603215976Sjmallett}; 1604215976Sjmalletttypedef union cvmx_dfa_ddr2_cfg cvmx_dfa_ddr2_cfg_t; 1605215976Sjmallett 1606215976Sjmallett/** 1607215976Sjmallett * cvmx_dfa_ddr2_comp 1608215976Sjmallett * 1609215976Sjmallett * DFA_DDR2_COMP = DFA DDR2 I/O PVT Compensation Configuration 1610215976Sjmallett * 1611215976Sjmallett * 1612215976Sjmallett * Description: The following are registers to program the DDR2 PLL and DLL 1613215976Sjmallett */ 1614215976Sjmallettunion cvmx_dfa_ddr2_comp 1615215976Sjmallett{ 1616215976Sjmallett uint64_t u64; 1617215976Sjmallett struct cvmx_dfa_ddr2_comp_s 1618215976Sjmallett { 1619215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1620215976Sjmallett uint64_t dfa__pctl : 4; /**< DFA DDR pctl from compensation circuit 1621215976Sjmallett Internal DBG only */ 1622215976Sjmallett uint64_t dfa__nctl : 4; /**< DFA DDR nctl from compensation circuit 1623215976Sjmallett Internal DBG only */ 1624215976Sjmallett uint64_t reserved_9_55 : 47; 1625215976Sjmallett uint64_t pctl_csr : 4; /**< Compensation control bits */ 1626215976Sjmallett uint64_t nctl_csr : 4; /**< Compensation control bits */ 1627215976Sjmallett uint64_t comp_bypass : 1; /**< Compensation Bypass */ 1628215976Sjmallett#else 1629215976Sjmallett uint64_t comp_bypass : 1; 1630215976Sjmallett uint64_t nctl_csr : 4; 1631215976Sjmallett uint64_t pctl_csr : 4; 1632215976Sjmallett uint64_t reserved_9_55 : 47; 1633215976Sjmallett uint64_t dfa__nctl : 4; 1634215976Sjmallett uint64_t dfa__pctl : 4; 1635215976Sjmallett#endif 1636215976Sjmallett } s; 1637215976Sjmallett struct cvmx_dfa_ddr2_comp_s cn31xx; 1638215976Sjmallett}; 1639215976Sjmalletttypedef union cvmx_dfa_ddr2_comp cvmx_dfa_ddr2_comp_t; 1640215976Sjmallett 1641215976Sjmallett/** 1642215976Sjmallett * cvmx_dfa_ddr2_emrs 1643215976Sjmallett * 1644215976Sjmallett * DFA_DDR2_EMRS = DDR2 EMRS Register(s) EMRS1[14:0], EMRS1_OCD[14:0] 1645215976Sjmallett * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT 1646215976Sjmallett * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init 1647215976Sjmallett * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these 1648215976Sjmallett * registers during the HW initialization sequence (see N3K specific restrictions in notes below). 1649215976Sjmallett * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature. 1650215976Sjmallett * 1651215976Sjmallett * Notes: 1652215976Sjmallett * For DDR-II please consult your device's data sheet for further details: 1653215976Sjmallett * 1654215976Sjmallett */ 1655215976Sjmallettunion cvmx_dfa_ddr2_emrs 1656215976Sjmallett{ 1657215976Sjmallett uint64_t u64; 1658215976Sjmallett struct cvmx_dfa_ddr2_emrs_s 1659215976Sjmallett { 1660215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1661215976Sjmallett uint64_t reserved_31_63 : 33; 1662215976Sjmallett uint64_t emrs1_ocd : 15; /**< Memory Address[14:0] during "EMRS1 (OCD Calibration)" 1663215976Sjmallett step \#12a "EMRS OCD Default Command" A[9:7]=111 1664215976Sjmallett of DDR2 HW initialization sequence. 1665215976Sjmallett (See JEDEC DDR2 specification (JESD79-2): 1666215976Sjmallett Power Up and initialization sequence). 1667215976Sjmallett A[14:13] = 0, RESERVED 1668215976Sjmallett A[12] = 0, Output Buffers Enabled 1669215976Sjmallett A[11] = 0, RDQS Disabled (we do not support RDQS) 1670215976Sjmallett A[10] = 0, DQSn Enabled 1671215976Sjmallett A[9:7] = 7, OCD Calibration Mode Default 1672215976Sjmallett A[6] = 0, ODT Disabled 1673215976Sjmallett A[5:3]=DFA_DDR2_TMG[ADDLAT] Additive LATENCY (Default 0) 1674215976Sjmallett A[2]=0 Termination Res RTT (ODT off Default) 1675215976Sjmallett [A6,A2] = 0 -> ODT Disabled 1676215976Sjmallett 1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved 1677215976Sjmallett A[1]=0 Normal Output Driver Imp mode 1678215976Sjmallett (1 - weak ie., 60% of normal drive strength) 1679215976Sjmallett A[0] = 0 DLL Enabled */ 1680215976Sjmallett uint64_t reserved_15_15 : 1; 1681215976Sjmallett uint64_t emrs1 : 15; /**< Memory Address[14:0] during: 1682215976Sjmallett a) Step \#7 "EMRS1 to enable DLL (A[0]=0)" 1683215976Sjmallett b) Step \#12b "EMRS OCD Calibration Mode Exit" 1684215976Sjmallett steps of DDR2 HW initialization sequence. 1685215976Sjmallett (See JEDEC DDR2 specification (JESD79-2): Power Up and 1686215976Sjmallett initialization sequence). 1687215976Sjmallett A[14:13] = 0, RESERVED 1688215976Sjmallett A[12] = 0, Output Buffers Enabled 1689215976Sjmallett A[11] = 0, RDQS Disabled (we do not support RDQS) 1690215976Sjmallett A[10] = 0, DQSn Enabled 1691215976Sjmallett A[9:7] = 0, OCD Calibration Mode exit/maintain 1692215976Sjmallett A[6] = 0, ODT Disabled 1693215976Sjmallett A[5:3]=DFA_DDR2_TMG[ADDLAT] Additive LATENCY (Default 0) 1694215976Sjmallett A[2]=0 Termination Res RTT (ODT off Default) 1695215976Sjmallett [A6,A2] = 0 -> ODT Disabled 1696215976Sjmallett 1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved 1697215976Sjmallett A[1]=0 Normal Output Driver Imp mode 1698215976Sjmallett (1 - weak ie., 60% of normal drive strength) 1699215976Sjmallett A[0] = 0 DLL Enabled */ 1700215976Sjmallett#else 1701215976Sjmallett uint64_t emrs1 : 15; 1702215976Sjmallett uint64_t reserved_15_15 : 1; 1703215976Sjmallett uint64_t emrs1_ocd : 15; 1704215976Sjmallett uint64_t reserved_31_63 : 33; 1705215976Sjmallett#endif 1706215976Sjmallett } s; 1707215976Sjmallett struct cvmx_dfa_ddr2_emrs_s cn31xx; 1708215976Sjmallett}; 1709215976Sjmalletttypedef union cvmx_dfa_ddr2_emrs cvmx_dfa_ddr2_emrs_t; 1710215976Sjmallett 1711215976Sjmallett/** 1712215976Sjmallett * cvmx_dfa_ddr2_fcnt 1713215976Sjmallett * 1714215976Sjmallett * DFA_DDR2_FCNT = DFA FCLK Counter 1715215976Sjmallett * 1716215976Sjmallett * 1717215976Sjmallett * Description: This FCLK cycle counter gets going after memory has been initialized 1718215976Sjmallett */ 1719215976Sjmallettunion cvmx_dfa_ddr2_fcnt 1720215976Sjmallett{ 1721215976Sjmallett uint64_t u64; 1722215976Sjmallett struct cvmx_dfa_ddr2_fcnt_s 1723215976Sjmallett { 1724215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1725215976Sjmallett uint64_t reserved_47_63 : 17; 1726215976Sjmallett uint64_t fcyc_cnt : 47; /**< Counter counts FCLK cycles or \# cycles that the memory 1727215976Sjmallett controller has requests queued up depending on FCNT_MODE 1728215976Sjmallett If FCNT_MODE = 0, this counter counts the \# FCLK cycles 1729215976Sjmallett If FCNT_MODE = 1, this counter counts the \# cycles the 1730215976Sjmallett controller is active with memory requests. */ 1731215976Sjmallett#else 1732215976Sjmallett uint64_t fcyc_cnt : 47; 1733215976Sjmallett uint64_t reserved_47_63 : 17; 1734215976Sjmallett#endif 1735215976Sjmallett } s; 1736215976Sjmallett struct cvmx_dfa_ddr2_fcnt_s cn31xx; 1737215976Sjmallett}; 1738215976Sjmalletttypedef union cvmx_dfa_ddr2_fcnt cvmx_dfa_ddr2_fcnt_t; 1739215976Sjmallett 1740215976Sjmallett/** 1741215976Sjmallett * cvmx_dfa_ddr2_mrs 1742215976Sjmallett * 1743215976Sjmallett * DFA_DDR2_MRS = DDR2 MRS Register(s) MRS_DLL[14:0], MRS[14:0] 1744215976Sjmallett * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT 1745215976Sjmallett * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init 1746215976Sjmallett * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these 1747215976Sjmallett * registers during the HW initialization sequence (see N3K specific restrictions in notes below). 1748215976Sjmallett * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature. 1749215976Sjmallett * 1750215976Sjmallett * Notes: 1751215976Sjmallett * For DDR-II please consult your device's data sheet for further details: 1752215976Sjmallett * 1753215976Sjmallett */ 1754215976Sjmallettunion cvmx_dfa_ddr2_mrs 1755215976Sjmallett{ 1756215976Sjmallett uint64_t u64; 1757215976Sjmallett struct cvmx_dfa_ddr2_mrs_s 1758215976Sjmallett { 1759215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1760215976Sjmallett uint64_t reserved_31_63 : 33; 1761215976Sjmallett uint64_t mrs : 15; /**< Memory Address[14:0] during "MRS without resetting 1762215976Sjmallett DLL A[8]=0" step of HW initialization sequence. 1763215976Sjmallett (See JEDEC DDR2 specification (JESD79-2): Power Up 1764215976Sjmallett and initialization sequence - Step \#11). 1765215976Sjmallett A[14:13] = 0, RESERVED 1766215976Sjmallett A[12] = 0, Fast Active Power Down Mode 1767215976Sjmallett A[11:9] = DFA_DDR2_TMG[TWR] 1768215976Sjmallett A[8] = 0, for DLL Reset 1769215976Sjmallett A[7] =0 Test Mode (must be 0 for normal operation) 1770215976Sjmallett A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4) 1771215976Sjmallett A[3]=0 Burst Type(must be 0:Sequential) 1772215976Sjmallett A[2:0]=2 Burst Length=4(default) */ 1773215976Sjmallett uint64_t reserved_15_15 : 1; 1774215976Sjmallett uint64_t mrs_dll : 15; /**< Memory Address[14:0] during "MRS for DLL_RESET A[8]=1" 1775215976Sjmallett step of HW initialization sequence. 1776215976Sjmallett (See JEDEC DDR2 specification (JESD79-2): Power Up 1777215976Sjmallett and initialization sequence - Step \#8). 1778215976Sjmallett A[14:13] = 0, RESERVED 1779215976Sjmallett A[12] = 0, Fast Active Power Down Mode 1780215976Sjmallett A[11:9] = DFA_DDR2_TMG[TWR] 1781215976Sjmallett A[8] = 1, for DLL Reset 1782215976Sjmallett A[7] = 0 Test Mode (must be 0 for normal operation) 1783215976Sjmallett A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4) 1784215976Sjmallett A[3] = 0 Burst Type(must be 0:Sequential) 1785215976Sjmallett A[2:0] = 2 Burst Length=4(default) */ 1786215976Sjmallett#else 1787215976Sjmallett uint64_t mrs_dll : 15; 1788215976Sjmallett uint64_t reserved_15_15 : 1; 1789215976Sjmallett uint64_t mrs : 15; 1790215976Sjmallett uint64_t reserved_31_63 : 33; 1791215976Sjmallett#endif 1792215976Sjmallett } s; 1793215976Sjmallett struct cvmx_dfa_ddr2_mrs_s cn31xx; 1794215976Sjmallett}; 1795215976Sjmalletttypedef union cvmx_dfa_ddr2_mrs cvmx_dfa_ddr2_mrs_t; 1796215976Sjmallett 1797215976Sjmallett/** 1798215976Sjmallett * cvmx_dfa_ddr2_opt 1799215976Sjmallett * 1800215976Sjmallett * DFA_DDR2_OPT = DFA DDR2 Optimization Registers 1801215976Sjmallett * 1802215976Sjmallett * 1803215976Sjmallett * Description: The following are registers to tweak certain parameters to boost performance 1804215976Sjmallett */ 1805215976Sjmallettunion cvmx_dfa_ddr2_opt 1806215976Sjmallett{ 1807215976Sjmallett uint64_t u64; 1808215976Sjmallett struct cvmx_dfa_ddr2_opt_s 1809215976Sjmallett { 1810215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1811215976Sjmallett uint64_t reserved_10_63 : 54; 1812215976Sjmallett uint64_t max_read_batch : 5; /**< Maximum number of consecutive read to service before 1813215976Sjmallett allowing write to interrupt. */ 1814215976Sjmallett uint64_t max_write_batch : 5; /**< Maximum number of consecutive writes to service before 1815215976Sjmallett allowing reads to interrupt. */ 1816215976Sjmallett#else 1817215976Sjmallett uint64_t max_write_batch : 5; 1818215976Sjmallett uint64_t max_read_batch : 5; 1819215976Sjmallett uint64_t reserved_10_63 : 54; 1820215976Sjmallett#endif 1821215976Sjmallett } s; 1822215976Sjmallett struct cvmx_dfa_ddr2_opt_s cn31xx; 1823215976Sjmallett}; 1824215976Sjmalletttypedef union cvmx_dfa_ddr2_opt cvmx_dfa_ddr2_opt_t; 1825215976Sjmallett 1826215976Sjmallett/** 1827215976Sjmallett * cvmx_dfa_ddr2_pll 1828215976Sjmallett * 1829215976Sjmallett * DFA_DDR2_PLL = DFA DDR2 PLL and DLL Configuration 1830215976Sjmallett * 1831215976Sjmallett * 1832215976Sjmallett * Description: The following are registers to program the DDR2 PLL and DLL 1833215976Sjmallett */ 1834215976Sjmallettunion cvmx_dfa_ddr2_pll 1835215976Sjmallett{ 1836215976Sjmallett uint64_t u64; 1837215976Sjmallett struct cvmx_dfa_ddr2_pll_s 1838215976Sjmallett { 1839215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1840215976Sjmallett uint64_t pll_setting : 17; /**< Internal Debug Use Only */ 1841215976Sjmallett uint64_t reserved_32_46 : 15; 1842215976Sjmallett uint64_t setting90 : 5; /**< Contains the setting of DDR DLL; Internal DBG only */ 1843215976Sjmallett uint64_t reserved_21_26 : 6; 1844215976Sjmallett uint64_t dll_setting : 5; /**< Contains the open loop setting value for the DDR90 delay 1845215976Sjmallett line. */ 1846215976Sjmallett uint64_t dll_byp : 1; /**< DLL Bypass. When set, the DDR90 DLL is bypassed and 1847215976Sjmallett the DLL behaves in Open Loop giving a fixed delay 1848215976Sjmallett set by DLL_SETTING */ 1849215976Sjmallett uint64_t qdll_ena : 1; /**< DDR Quad DLL Enable: A 0->1 transition on this bit after 1850215976Sjmallett erst deassertion will reset the DDR 90 DLL. Allow 1851215976Sjmallett 200 micro seconds for Lock before DDR Init. */ 1852215976Sjmallett uint64_t bw_ctl : 4; /**< Internal Use Only - for Debug */ 1853215976Sjmallett uint64_t bw_upd : 1; /**< Internal Use Only - for Debug */ 1854215976Sjmallett uint64_t pll_div2 : 1; /**< PLL Output is further divided by 2. Useful for slow 1855215976Sjmallett fclk frequencies where the PLL may be out of range. */ 1856215976Sjmallett uint64_t reserved_7_7 : 1; 1857215976Sjmallett uint64_t pll_ratio : 5; /**< Bits <6:2> sets the clk multiplication ratio 1858215976Sjmallett If the fclk frequency desired is less than 260MHz 1859215976Sjmallett (lower end saturation point of the pll), write 2x 1860215976Sjmallett the ratio desired in this register and set PLL_DIV2 */ 1861215976Sjmallett uint64_t pll_bypass : 1; /**< PLL Bypass. Uses the ref_clk without multiplication. */ 1862215976Sjmallett uint64_t pll_init : 1; /**< Need a 0 to 1 pulse on this CSR to get the DFA 1863215976Sjmallett Clk Generator Started. Write this register before 1864215976Sjmallett starting anything. Allow 200 uS for PLL Lock before 1865215976Sjmallett doing anything. */ 1866215976Sjmallett#else 1867215976Sjmallett uint64_t pll_init : 1; 1868215976Sjmallett uint64_t pll_bypass : 1; 1869215976Sjmallett uint64_t pll_ratio : 5; 1870215976Sjmallett uint64_t reserved_7_7 : 1; 1871215976Sjmallett uint64_t pll_div2 : 1; 1872215976Sjmallett uint64_t bw_upd : 1; 1873215976Sjmallett uint64_t bw_ctl : 4; 1874215976Sjmallett uint64_t qdll_ena : 1; 1875215976Sjmallett uint64_t dll_byp : 1; 1876215976Sjmallett uint64_t dll_setting : 5; 1877215976Sjmallett uint64_t reserved_21_26 : 6; 1878215976Sjmallett uint64_t setting90 : 5; 1879215976Sjmallett uint64_t reserved_32_46 : 15; 1880215976Sjmallett uint64_t pll_setting : 17; 1881215976Sjmallett#endif 1882215976Sjmallett } s; 1883215976Sjmallett struct cvmx_dfa_ddr2_pll_s cn31xx; 1884215976Sjmallett}; 1885215976Sjmalletttypedef union cvmx_dfa_ddr2_pll cvmx_dfa_ddr2_pll_t; 1886215976Sjmallett 1887215976Sjmallett/** 1888215976Sjmallett * cvmx_dfa_ddr2_tmg 1889215976Sjmallett * 1890215976Sjmallett * DFA_DDR2_TMG = DFA DDR2 Memory Timing Config Register 1891215976Sjmallett * 1892215976Sjmallett * 1893215976Sjmallett * Description: The following are registers to program the DDR2 memory timing parameters. 1894215976Sjmallett */ 1895215976Sjmallettunion cvmx_dfa_ddr2_tmg 1896215976Sjmallett{ 1897215976Sjmallett uint64_t u64; 1898215976Sjmallett struct cvmx_dfa_ddr2_tmg_s 1899215976Sjmallett { 1900215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1901215976Sjmallett uint64_t reserved_47_63 : 17; 1902215976Sjmallett uint64_t fcnt_mode : 1; /**< If FCNT_MODE = 0, this counter counts the \# FCLK cycles 1903215976Sjmallett If FCNT_MODE = 1, this counter counts the \# cycles the 1904215976Sjmallett controller is active with memory requests. */ 1905215976Sjmallett uint64_t cnt_clr : 1; /**< Clears the FCLK Cyc & Bus Util counter */ 1906215976Sjmallett uint64_t cavmipo : 1; /**< RESERVED */ 1907215976Sjmallett uint64_t ctr_rst : 1; /**< Reset oneshot pulse for refresh counter & Perf counters 1908215976Sjmallett SW should first write this field to a one to clear 1909215976Sjmallett & then write to a zero for normal operation */ 1910215976Sjmallett uint64_t odt_rtt : 2; /**< DDR2 Termination Resistor Setting 1911215976Sjmallett These two bits are loaded into the RTT 1912215976Sjmallett portion of the EMRS register bits A6 & A2. If DDR2's 1913215976Sjmallett termination (for the memory's DQ/DQS/DM pads) is not 1914215976Sjmallett desired, set it to 00. If it is, chose between 1915215976Sjmallett 01 for 75 ohm and 10 for 150 ohm termination. 1916215976Sjmallett 00 = ODT Disabled 1917215976Sjmallett 01 = 75 ohm Termination 1918215976Sjmallett 10 = 150 ohm Termination 1919215976Sjmallett 11 = 50 ohm Termination */ 1920215976Sjmallett uint64_t dqsn_ena : 1; /**< For DDR-II Mode, DIC[1] is used to load into EMRS 1921215976Sjmallett bit 10 - DQSN Enable/Disable field. By default, we 1922215976Sjmallett program the DDR's to drive the DQSN also. Set it to 1923215976Sjmallett 1 if DQSN should be Hi-Z. 1924215976Sjmallett 0 - DQSN Enable 1925215976Sjmallett 1 - DQSN Disable */ 1926215976Sjmallett uint64_t dic : 1; /**< Drive Strength Control: 1927215976Sjmallett For DDR-I/II Mode, DIC[0] is 1928215976Sjmallett loaded into the Extended Mode Register (EMRS) A1 bit 1929215976Sjmallett during initialization. (see DDR-I data sheet EMRS 1930215976Sjmallett description) 1931215976Sjmallett 0 = Normal 1932215976Sjmallett 1 = Reduced */ 1933215976Sjmallett uint64_t r2r_slot : 1; /**< A 1 on this register will force the controller to 1934215976Sjmallett slot a bubble between every reads */ 1935215976Sjmallett uint64_t tfaw : 5; /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1 1936215976Sjmallett Four Access Window time. Relevant only in 1937215976Sjmallett 8-bank parts. 1938215976Sjmallett TFAW = 5'b0 for DDR2-4bank 1939215976Sjmallett TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */ 1940215976Sjmallett uint64_t twtr : 4; /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)] 1941215976Sjmallett Last Wr Data to Rd Command time. 1942215976Sjmallett (Represented in fclk cycles) 1943215976Sjmallett TYP=15ns 1944215976Sjmallett - 0000: RESERVED 1945215976Sjmallett - 0001: 1 1946215976Sjmallett - ... 1947215976Sjmallett - 0111: 7 1948215976Sjmallett - 1000-1111: RESERVED */ 1949215976Sjmallett uint64_t twr : 3; /**< DDR Write Recovery time (tWR). Last Wr Brst to Prech 1950215976Sjmallett This is not a direct encoding of the value. Its 1951215976Sjmallett programmed as below per DDR2 spec. The decimal number 1952215976Sjmallett on the right is RNDUP(tWR(ns) / clkFreq) 1953215976Sjmallett TYP=15ns 1954215976Sjmallett - 000: RESERVED 1955215976Sjmallett - 001: 2 1956215976Sjmallett - 010: 3 1957215976Sjmallett - 011: 4 1958215976Sjmallett - 100: 5 1959215976Sjmallett - 101: 6 1960215976Sjmallett - 110-111: RESERVED */ 1961215976Sjmallett uint64_t trp : 4; /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)] 1962215976Sjmallett (Represented in fclk cycles) 1963215976Sjmallett TYP=15ns 1964215976Sjmallett - 0000: RESERVED 1965215976Sjmallett - 0001: 1 1966215976Sjmallett - ... 1967215976Sjmallett - 0111: 7 1968215976Sjmallett - 1000-1111: RESERVED 1969215976Sjmallett When using parts with 8 banks (DFA_CFG->MAX_BNK 1970215976Sjmallett is 1), load tRP cycles + 1 into this register. */ 1971215976Sjmallett uint64_t tras : 5; /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)] 1972215976Sjmallett (Represented in fclk cycles) 1973215976Sjmallett TYP=45ns 1974215976Sjmallett - 00000-0001: RESERVED 1975215976Sjmallett - 00010: 2 1976215976Sjmallett - ... 1977215976Sjmallett - 10100: 20 1978215976Sjmallett - 10101-11111: RESERVED */ 1979215976Sjmallett uint64_t trrd : 3; /**< tRRD cycles: ACT-ACT timing parameter for different 1980215976Sjmallett banks. (Represented in fclk cycles) 1981215976Sjmallett For DDR2, TYP=7.5ns 1982215976Sjmallett - 000: RESERVED 1983215976Sjmallett - 001: 1 tCYC 1984215976Sjmallett - 010: 2 tCYC 1985215976Sjmallett - 011: 3 tCYC 1986215976Sjmallett - 100: 4 tCYC 1987215976Sjmallett - 101: 5 tCYC 1988215976Sjmallett - 110-111: RESERVED */ 1989215976Sjmallett uint64_t trcd : 4; /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)] 1990215976Sjmallett (Represented in fclk cycles) 1991215976Sjmallett TYP=15ns 1992215976Sjmallett - 0000: RESERVED 1993215976Sjmallett - 0001: 2 (2 is the smallest value allowed) 1994215976Sjmallett - 0002: 2 1995215976Sjmallett - ... 1996215976Sjmallett - 0111: 7 1997215976Sjmallett - 1110-1111: RESERVED */ 1998215976Sjmallett uint64_t addlat : 3; /**< When in Posted CAS mode ADDLAT needs to be programmed 1999215976Sjmallett to tRCD-1 2000215976Sjmallett ADDLAT \#additional latency cycles 2001215976Sjmallett 000 0 2002215976Sjmallett 001 1 (tRCD = 2 fclk's) 2003215976Sjmallett 010 2 (tRCD = 3 fclk's) 2004215976Sjmallett 011 3 (tRCD = 4 fclk's) 2005215976Sjmallett 100 4 (tRCD = 5 fclk's) 2006215976Sjmallett 101 5 (tRCD = 6 fclk's) 2007215976Sjmallett 110 6 (tRCD = 7 fclk's) 2008215976Sjmallett 111 7 (tRCD = 8 fclk's) */ 2009215976Sjmallett uint64_t pocas : 1; /**< Posted CAS mode. When 1, we use DDR2's Posted CAS 2010215976Sjmallett feature. When using this mode, ADDLAT needs to be 2011215976Sjmallett programmed as well */ 2012215976Sjmallett uint64_t caslat : 3; /**< CAS Latency in \# fclk Cycles 2013215976Sjmallett CASLAT \# CAS latency cycles 2014215976Sjmallett 000 - 010 RESERVED 2015215976Sjmallett 011 3 2016215976Sjmallett 100 4 2017215976Sjmallett 101 5 2018215976Sjmallett 110 6 2019215976Sjmallett 111 7 */ 2020215976Sjmallett uint64_t tmrd : 2; /**< tMRD Cycles 2021215976Sjmallett (Represented in fclk tCYC) 2022215976Sjmallett For DDR2, its TYP 2*tCYC) 2023215976Sjmallett - 000: RESERVED 2024215976Sjmallett - 001: 1 2025215976Sjmallett - 010: 2 2026215976Sjmallett - 011: 3 */ 2027215976Sjmallett uint64_t ddr2t : 1; /**< When 2T mode is turned on, command signals are 2028215976Sjmallett setup a cycle ahead of when the CS is enabled 2029215976Sjmallett and kept for a total of 2 cycles. This mode is 2030215976Sjmallett enabled in higher speeds when there is difficulty 2031215976Sjmallett meeting setup. Performance could 2032215976Sjmallett be negatively affected in 2T mode */ 2033215976Sjmallett#else 2034215976Sjmallett uint64_t ddr2t : 1; 2035215976Sjmallett uint64_t tmrd : 2; 2036215976Sjmallett uint64_t caslat : 3; 2037215976Sjmallett uint64_t pocas : 1; 2038215976Sjmallett uint64_t addlat : 3; 2039215976Sjmallett uint64_t trcd : 4; 2040215976Sjmallett uint64_t trrd : 3; 2041215976Sjmallett uint64_t tras : 5; 2042215976Sjmallett uint64_t trp : 4; 2043215976Sjmallett uint64_t twr : 3; 2044215976Sjmallett uint64_t twtr : 4; 2045215976Sjmallett uint64_t tfaw : 5; 2046215976Sjmallett uint64_t r2r_slot : 1; 2047215976Sjmallett uint64_t dic : 1; 2048215976Sjmallett uint64_t dqsn_ena : 1; 2049215976Sjmallett uint64_t odt_rtt : 2; 2050215976Sjmallett uint64_t ctr_rst : 1; 2051215976Sjmallett uint64_t cavmipo : 1; 2052215976Sjmallett uint64_t cnt_clr : 1; 2053215976Sjmallett uint64_t fcnt_mode : 1; 2054215976Sjmallett uint64_t reserved_47_63 : 17; 2055215976Sjmallett#endif 2056215976Sjmallett } s; 2057215976Sjmallett struct cvmx_dfa_ddr2_tmg_s cn31xx; 2058215976Sjmallett}; 2059215976Sjmalletttypedef union cvmx_dfa_ddr2_tmg cvmx_dfa_ddr2_tmg_t; 2060215976Sjmallett 2061215976Sjmallett/** 2062215976Sjmallett * cvmx_dfa_debug0 2063215976Sjmallett * 2064215976Sjmallett * DFA_DEBUG0 = DFA Scoreboard Debug \#0 Register 2065215976Sjmallett * *FOR INTERNAL USE ONLY* 2066215976Sjmallett * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2067215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2068215976Sjmallett * CSR read. 2069215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2070215976Sjmallett * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2071215976Sjmallett * instruction. 2072215976Sjmallett */ 2073215976Sjmallettunion cvmx_dfa_debug0 2074215976Sjmallett{ 2075215976Sjmallett uint64_t u64; 2076215976Sjmallett struct cvmx_dfa_debug0_s 2077215976Sjmallett { 2078215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2079215976Sjmallett uint64_t sbd0 : 64; /**< DFA ScoreBoard \#0 Data 2080215976Sjmallett (DFA Scoreboard Debug) 2081215976Sjmallett [63:38] (26) rptr[28:3]: Result Base Pointer (QW-aligned) 2082215976Sjmallett [37:22] (16) Cumulative Result Write Counter (for HDR write) 2083215976Sjmallett [21] (1) Waiting for GRdRsp EOT 2084215976Sjmallett [20] (1) Waiting for GRdReq Issue (to NRQ) 2085215976Sjmallett [19] (1) GLPTR/GLCNT Valid 2086215976Sjmallett [18] (1) Completion Mark Detected 2087215976Sjmallett [17:15] (3) Completion Code [0=PDGONE/1=PERR/2=RFULL/3=TERM] 2088215976Sjmallett [14] (1) Completion Detected 2089215976Sjmallett [13] (1) Waiting for HDR RWrCmtRsp 2090215976Sjmallett [12] (1) Waiting for LAST RESULT RWrCmtRsp 2091215976Sjmallett [11] (1) Waiting for HDR RWrReq 2092215976Sjmallett [10] (1) Waiting for RWrReq 2093215976Sjmallett [9] (1) Waiting for WQWrReq issue 2094215976Sjmallett [8] (1) Waiting for PRdRsp EOT 2095215976Sjmallett [7] (1) Waiting for PRdReq Issue (to NRQ) 2096215976Sjmallett [6] (1) Packet Data Valid 2097215976Sjmallett [5] (1) WQVLD 2098215976Sjmallett [4] (1) WQ Done Point (either WQWrReq issued (for WQPTR<>0) OR HDR RWrCmtRsp) 2099215976Sjmallett [3] (1) Resultant write STF/P Mode 2100215976Sjmallett [2] (1) Packet Data LDT mode 2101215976Sjmallett [1] (1) Gather Mode 2102215976Sjmallett [0] (1) Valid */ 2103215976Sjmallett#else 2104215976Sjmallett uint64_t sbd0 : 64; 2105215976Sjmallett#endif 2106215976Sjmallett } s; 2107215976Sjmallett struct cvmx_dfa_debug0_s cn63xx; 2108215976Sjmallett struct cvmx_dfa_debug0_s cn63xxp1; 2109215976Sjmallett}; 2110215976Sjmalletttypedef union cvmx_dfa_debug0 cvmx_dfa_debug0_t; 2111215976Sjmallett 2112215976Sjmallett/** 2113215976Sjmallett * cvmx_dfa_debug1 2114215976Sjmallett * 2115215976Sjmallett * DFA_DEBUG1 = DFA Scoreboard Debug \#1 Register 2116215976Sjmallett * *FOR INTERNAL USE ONLY* 2117215976Sjmallett * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2118215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2119215976Sjmallett * CSR read. 2120215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2121215976Sjmallett * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2122215976Sjmallett * instruction. 2123215976Sjmallett */ 2124215976Sjmallettunion cvmx_dfa_debug1 2125215976Sjmallett{ 2126215976Sjmallett uint64_t u64; 2127215976Sjmallett struct cvmx_dfa_debug1_s 2128215976Sjmallett { 2129215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2130215976Sjmallett uint64_t sbd1 : 64; /**< DFA ScoreBoard \#1 Data 2131215976Sjmallett DFA Scoreboard Debug Data 2132215976Sjmallett [63:56] (8) UNUSED 2133215976Sjmallett [55:16] (40) Packet Data Pointer 2134215976Sjmallett [15:0] (16) Packet Data Counter */ 2135215976Sjmallett#else 2136215976Sjmallett uint64_t sbd1 : 64; 2137215976Sjmallett#endif 2138215976Sjmallett } s; 2139215976Sjmallett struct cvmx_dfa_debug1_s cn63xx; 2140215976Sjmallett struct cvmx_dfa_debug1_s cn63xxp1; 2141215976Sjmallett}; 2142215976Sjmalletttypedef union cvmx_dfa_debug1 cvmx_dfa_debug1_t; 2143215976Sjmallett 2144215976Sjmallett/** 2145215976Sjmallett * cvmx_dfa_debug2 2146215976Sjmallett * 2147215976Sjmallett * DFA_DEBUG2 = DFA Scoreboard Debug \#2 Register 2148215976Sjmallett * 2149215976Sjmallett * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2150215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2151215976Sjmallett * CSR read. 2152215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2153215976Sjmallett * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2154215976Sjmallett * instruction. 2155215976Sjmallett */ 2156215976Sjmallettunion cvmx_dfa_debug2 2157215976Sjmallett{ 2158215976Sjmallett uint64_t u64; 2159215976Sjmallett struct cvmx_dfa_debug2_s 2160215976Sjmallett { 2161215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2162215976Sjmallett uint64_t sbd2 : 64; /**< DFA ScoreBoard \#2 Data 2163215976Sjmallett [63:45] (19) UNUSED 2164215976Sjmallett [44:42] (3) Instruction Type 2165215976Sjmallett [41:5] (37) rwptr[39:3]: Result Write Pointer 2166215976Sjmallett [4:0] (5) prwcnt[4:0]: Pending Result Write Counter */ 2167215976Sjmallett#else 2168215976Sjmallett uint64_t sbd2 : 64; 2169215976Sjmallett#endif 2170215976Sjmallett } s; 2171215976Sjmallett struct cvmx_dfa_debug2_s cn63xx; 2172215976Sjmallett struct cvmx_dfa_debug2_s cn63xxp1; 2173215976Sjmallett}; 2174215976Sjmalletttypedef union cvmx_dfa_debug2 cvmx_dfa_debug2_t; 2175215976Sjmallett 2176215976Sjmallett/** 2177215976Sjmallett * cvmx_dfa_debug3 2178215976Sjmallett * 2179215976Sjmallett * DFA_DEBUG3 = DFA Scoreboard Debug \#3 Register 2180215976Sjmallett * 2181215976Sjmallett * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2182215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2183215976Sjmallett * CSR read. 2184215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2185215976Sjmallett * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2186215976Sjmallett * instruction. 2187215976Sjmallett */ 2188215976Sjmallettunion cvmx_dfa_debug3 2189215976Sjmallett{ 2190215976Sjmallett uint64_t u64; 2191215976Sjmallett struct cvmx_dfa_debug3_s 2192215976Sjmallett { 2193215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2194215976Sjmallett uint64_t sbd3 : 64; /**< DFA ScoreBoard \#3 Data 2195215976Sjmallett [63:52] (11) rptr[39:29]: Result Base Pointer (QW-aligned) 2196215976Sjmallett [52:16] (37) glptr[39:3]: Gather List Pointer 2197215976Sjmallett [15:0] (16) glcnt Gather List Counter */ 2198215976Sjmallett#else 2199215976Sjmallett uint64_t sbd3 : 64; 2200215976Sjmallett#endif 2201215976Sjmallett } s; 2202215976Sjmallett struct cvmx_dfa_debug3_s cn63xx; 2203215976Sjmallett struct cvmx_dfa_debug3_s cn63xxp1; 2204215976Sjmallett}; 2205215976Sjmalletttypedef union cvmx_dfa_debug3 cvmx_dfa_debug3_t; 2206215976Sjmallett 2207215976Sjmallett/** 2208215976Sjmallett * cvmx_dfa_difctl 2209215976Sjmallett * 2210215976Sjmallett * DFA_DIFCTL = DFA Instruction FIFO (DIF) Control Register 2211215976Sjmallett * 2212215976Sjmallett * Description: 2213215976Sjmallett * NOTE: To write to the DFA_DIFCTL register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b110. 2214215976Sjmallett * To read the DFA_DIFCTL register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b110. 2215215976Sjmallett * 2216215976Sjmallett * NOTE: This register is intended to ONLY be written once (at power-up). Any future writes could 2217215976Sjmallett * cause the DFA and FPA HW to become unpredictable. 2218215976Sjmallett * 2219215976Sjmallett * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFCTL register do not take effect. 2220215976Sjmallett * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFCTL register do not take effect. 2221215976Sjmallett */ 2222215976Sjmallettunion cvmx_dfa_difctl 2223215976Sjmallett{ 2224215976Sjmallett uint64_t u64; 2225215976Sjmallett struct cvmx_dfa_difctl_s 2226215976Sjmallett { 2227215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2228215976Sjmallett uint64_t reserved_20_63 : 44; 2229215976Sjmallett uint64_t dwbcnt : 8; /**< Represents the \# of cache lines in the instruction 2230215976Sjmallett buffer that may be dirty and should not be 2231215976Sjmallett written-back to memory when the instruction 2232215976Sjmallett chunk is returned to the Free Page list. 2233215976Sjmallett NOTE: Typically SW will want to mark all DFA 2234215976Sjmallett Instruction memory returned to the Free Page list 2235215976Sjmallett as DWB (Don't WriteBack), therefore SW should 2236215976Sjmallett seed this register as: 2237215976Sjmallett DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */ 2238215976Sjmallett uint64_t pool : 3; /**< Represents the 3bit buffer pool-id used by DFA HW 2239215976Sjmallett when the DFA instruction chunk is recycled back 2240215976Sjmallett to the Free Page List maintained by the FPA HW 2241215976Sjmallett (once the DFA instruction has been issued). */ 2242215976Sjmallett uint64_t size : 9; /**< Represents the \# of 32B instructions contained 2243215976Sjmallett within each DFA instruction chunk. At Power-on, 2244215976Sjmallett SW will seed the SIZE register with a fixed 2245215976Sjmallett chunk-size. (Must be at least 3) 2246215976Sjmallett DFA HW uses this field to determine the size 2247215976Sjmallett of each DFA instruction chunk, in order to: 2248215976Sjmallett a) determine when to read the next DFA 2249215976Sjmallett instruction chunk pointer which is 2250215976Sjmallett written by SW at the end of the current 2251215976Sjmallett DFA instruction chunk (see DFA description 2252215976Sjmallett of next chunk buffer Ptr for format). 2253215976Sjmallett b) determine when a DFA instruction chunk 2254215976Sjmallett can be returned to the Free Page List 2255215976Sjmallett maintained by the FPA HW. */ 2256215976Sjmallett#else 2257215976Sjmallett uint64_t size : 9; 2258215976Sjmallett uint64_t pool : 3; 2259215976Sjmallett uint64_t dwbcnt : 8; 2260215976Sjmallett uint64_t reserved_20_63 : 44; 2261215976Sjmallett#endif 2262215976Sjmallett } s; 2263215976Sjmallett struct cvmx_dfa_difctl_s cn31xx; 2264215976Sjmallett struct cvmx_dfa_difctl_s cn38xx; 2265215976Sjmallett struct cvmx_dfa_difctl_s cn38xxp2; 2266215976Sjmallett struct cvmx_dfa_difctl_s cn58xx; 2267215976Sjmallett struct cvmx_dfa_difctl_s cn58xxp1; 2268215976Sjmallett struct cvmx_dfa_difctl_s cn63xx; 2269215976Sjmallett struct cvmx_dfa_difctl_s cn63xxp1; 2270215976Sjmallett}; 2271215976Sjmalletttypedef union cvmx_dfa_difctl cvmx_dfa_difctl_t; 2272215976Sjmallett 2273215976Sjmallett/** 2274215976Sjmallett * cvmx_dfa_difrdptr 2275215976Sjmallett * 2276215976Sjmallett * DFA_DIFRDPTR = DFA Instruction FIFO (DIF) RDPTR Register 2277215976Sjmallett * 2278215976Sjmallett * Description: 2279215976Sjmallett * NOTE: To write to the DFA_DIFRDPTR register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b01. 2280215976Sjmallett * To read the DFA_DIFRDPTR register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b01. 2281215976Sjmallett * 2282215976Sjmallett * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFRDPTR register do not take effect. 2283215976Sjmallett * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFRDPTR register do not take effect. 2284215976Sjmallett */ 2285215976Sjmallettunion cvmx_dfa_difrdptr 2286215976Sjmallett{ 2287215976Sjmallett uint64_t u64; 2288215976Sjmallett struct cvmx_dfa_difrdptr_s 2289215976Sjmallett { 2290215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2291215976Sjmallett uint64_t reserved_40_63 : 24; 2292215976Sjmallett uint64_t rdptr : 35; /**< Represents the 32B-aligned address of the current 2293215976Sjmallett instruction in the DFA Instruction FIFO in main 2294215976Sjmallett memory. The RDPTR must be seeded by software at 2295215976Sjmallett boot time, and is then maintained thereafter 2296215976Sjmallett by DFA HW. 2297215976Sjmallett During the seed write (by SW), RDPTR[6:5]=0, 2298215976Sjmallett since DFA instruction chunks must be 128B aligned. 2299215976Sjmallett During a read (by SW), the 'most recent' contents 2300215976Sjmallett of the RDPTR register are returned at the time 2301215976Sjmallett the NCB-INB bus is driven. 2302215976Sjmallett NOTE: Since DFA HW updates this register, its 2303215976Sjmallett contents are unpredictable in SW (unless 2304215976Sjmallett its guaranteed that no new DoorBell register 2305215976Sjmallett writes have occurred and the DoorBell register is 2306215976Sjmallett read as zero). */ 2307215976Sjmallett uint64_t reserved_0_4 : 5; 2308215976Sjmallett#else 2309215976Sjmallett uint64_t reserved_0_4 : 5; 2310215976Sjmallett uint64_t rdptr : 35; 2311215976Sjmallett uint64_t reserved_40_63 : 24; 2312215976Sjmallett#endif 2313215976Sjmallett } s; 2314215976Sjmallett struct cvmx_dfa_difrdptr_cn31xx 2315215976Sjmallett { 2316215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2317215976Sjmallett uint64_t reserved_36_63 : 28; 2318215976Sjmallett uint64_t rdptr : 31; /**< Represents the 32B-aligned address of the current 2319215976Sjmallett instruction in the DFA Instruction FIFO in main 2320215976Sjmallett memory. The RDPTR must be seeded by software at 2321215976Sjmallett boot time, and is then maintained thereafter 2322215976Sjmallett by DFA HW. 2323215976Sjmallett During the seed write (by SW), RDPTR[6:5]=0, 2324215976Sjmallett since DFA instruction chunks must be 128B aligned. 2325215976Sjmallett During a read (by SW), the 'most recent' contents 2326215976Sjmallett of the RDPTR register are returned at the time 2327215976Sjmallett the NCB-INB bus is driven. 2328215976Sjmallett NOTE: Since DFA HW updates this register, its 2329215976Sjmallett contents are unpredictable in SW (unless 2330215976Sjmallett its guaranteed that no new DoorBell register 2331215976Sjmallett writes have occurred and the DoorBell register is 2332215976Sjmallett read as zero). */ 2333215976Sjmallett uint64_t reserved_0_4 : 5; 2334215976Sjmallett#else 2335215976Sjmallett uint64_t reserved_0_4 : 5; 2336215976Sjmallett uint64_t rdptr : 31; 2337215976Sjmallett uint64_t reserved_36_63 : 28; 2338215976Sjmallett#endif 2339215976Sjmallett } cn31xx; 2340215976Sjmallett struct cvmx_dfa_difrdptr_cn31xx cn38xx; 2341215976Sjmallett struct cvmx_dfa_difrdptr_cn31xx cn38xxp2; 2342215976Sjmallett struct cvmx_dfa_difrdptr_cn31xx cn58xx; 2343215976Sjmallett struct cvmx_dfa_difrdptr_cn31xx cn58xxp1; 2344215976Sjmallett struct cvmx_dfa_difrdptr_s cn63xx; 2345215976Sjmallett struct cvmx_dfa_difrdptr_s cn63xxp1; 2346215976Sjmallett}; 2347215976Sjmalletttypedef union cvmx_dfa_difrdptr cvmx_dfa_difrdptr_t; 2348215976Sjmallett 2349215976Sjmallett/** 2350215976Sjmallett * cvmx_dfa_dtcfadr 2351215976Sjmallett * 2352215976Sjmallett * DFA_DTCFADR = DFA DTC Failing Address Register 2353215976Sjmallett * 2354215976Sjmallett * Description: DFA Node Cache Failing Address/Control Error Capture information 2355215976Sjmallett * This register contains useful information to help in isolating a Node Cache RAM failure. 2356215976Sjmallett * NOTE: The first detected PERR failure is captured in DFA_DTCFADR (locked down), until the 2357215976Sjmallett * corresponding PERR Interrupt is cleared by writing one (W1C). (see: DFA_ERR[DC0PERR[2:0]]). 2358215976Sjmallett */ 2359215976Sjmallettunion cvmx_dfa_dtcfadr 2360215976Sjmallett{ 2361215976Sjmallett uint64_t u64; 2362215976Sjmallett struct cvmx_dfa_dtcfadr_s 2363215976Sjmallett { 2364215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2365215976Sjmallett uint64_t reserved_44_63 : 20; 2366215976Sjmallett uint64_t ram3fadr : 12; /**< DFA RAM3 Failing Address 2367215976Sjmallett If DFA_ERR[DC0PERR<2>]=1, this field indicates the 2368215976Sjmallett failing RAM3 Address. The failing address is locked 2369215976Sjmallett down until the DC0PERR<2> W1C occurs. */ 2370215976Sjmallett uint64_t reserved_25_31 : 7; 2371215976Sjmallett uint64_t ram2fadr : 9; /**< DFA RAM2 Failing Address 2372215976Sjmallett If DFA_ERR[DC0PERR<1>]=1, this field indicates the 2373215976Sjmallett failing RAM2 Address. The failing address is locked 2374215976Sjmallett down until the DC0PERR<1> W1C occurs. */ 2375215976Sjmallett uint64_t reserved_14_15 : 2; 2376215976Sjmallett uint64_t ram1fadr : 14; /**< DFA RAM1 Failing Address 2377215976Sjmallett If DFA_ERR[DC0PERR<0>]=1, this field indicates the 2378215976Sjmallett failing RAM1 Address. The failing address is locked 2379215976Sjmallett down until the DC0PERR<0> W1C occurs. */ 2380215976Sjmallett#else 2381215976Sjmallett uint64_t ram1fadr : 14; 2382215976Sjmallett uint64_t reserved_14_15 : 2; 2383215976Sjmallett uint64_t ram2fadr : 9; 2384215976Sjmallett uint64_t reserved_25_31 : 7; 2385215976Sjmallett uint64_t ram3fadr : 12; 2386215976Sjmallett uint64_t reserved_44_63 : 20; 2387215976Sjmallett#endif 2388215976Sjmallett } s; 2389215976Sjmallett struct cvmx_dfa_dtcfadr_s cn63xx; 2390215976Sjmallett struct cvmx_dfa_dtcfadr_s cn63xxp1; 2391215976Sjmallett}; 2392215976Sjmalletttypedef union cvmx_dfa_dtcfadr cvmx_dfa_dtcfadr_t; 2393215976Sjmallett 2394215976Sjmallett/** 2395215976Sjmallett * cvmx_dfa_eclkcfg 2396215976Sjmallett * 2397215976Sjmallett * Specify the RSL base addresses for the block 2398215976Sjmallett * 2399215976Sjmallett * DFA_ECLKCFG = DFA eclk-domain Configuration Registers 2400215976Sjmallett * 2401215976Sjmallett * Description: 2402215976Sjmallett */ 2403215976Sjmallettunion cvmx_dfa_eclkcfg 2404215976Sjmallett{ 2405215976Sjmallett uint64_t u64; 2406215976Sjmallett struct cvmx_dfa_eclkcfg_s 2407215976Sjmallett { 2408215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2409215976Sjmallett uint64_t reserved_19_63 : 45; 2410215976Sjmallett uint64_t sbdnum : 3; /**< SBD Debug Entry# 2411215976Sjmallett For internal use only. (DFA Scoreboard debug) 2412215976Sjmallett Selects which one of 8 DFA Scoreboard entries is 2413215976Sjmallett latched into the DFA_SBD_DBG[0-3] registers. */ 2414215976Sjmallett uint64_t reserved_15_15 : 1; 2415215976Sjmallett uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 2416215976Sjmallett For internal use only. (DFA Scoreboard debug) 2417215976Sjmallett When written with a '1', the DFA Scoreboard Debug 2418215976Sjmallett registers (DFA_SBD_DBG[0-3]) are all locked down. 2419215976Sjmallett This allows SW to lock down the contents of the entire 2420215976Sjmallett SBD for a single instant in time. All subsequent reads 2421215976Sjmallett of the DFA scoreboard registers will return the data 2422215976Sjmallett from that instant in time. */ 2423215976Sjmallett uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode 2424215976Sjmallett DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR) 2425215976Sjmallett NOTE: This should only be written to a different value 2426215976Sjmallett during power-on SW initialization. */ 2427215976Sjmallett uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode 2428215976Sjmallett DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR) 2429215976Sjmallett NOTE: This should only be written to a different value 2430215976Sjmallett during power-on SW initialization. */ 2431215976Sjmallett uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 2432215976Sjmallett (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 2433215976Sjmallett NOTE: This should only be written to a different value 2434215976Sjmallett during power-on SW initialization. */ 2435215976Sjmallett uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 2436215976Sjmallett (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 2437215976Sjmallett NOTE: This should only be written to a different value 2438215976Sjmallett during power-on SW initialization. */ 2439215976Sjmallett uint64_t imode : 1; /**< NCB-Inbound Arbiter 2440215976Sjmallett (0=FP [LP=NRQ,HP=NRP], 1=RR) 2441215976Sjmallett NOTE: This should only be written to a different value 2442215976Sjmallett during power-on SW initialization. */ 2443215976Sjmallett uint64_t sarb : 1; /**< DFA Source Arbiter Mode 2444215976Sjmallett Selects the arbitration mode used to select DFA requests 2445215976Sjmallett issued from either CP2 or the DTE (NCB-CSR or DFA HW engine). 2446215976Sjmallett - 0: Fixed Priority [Highest=CP2, Lowest=DTE] 2447215976Sjmallett - 1: Round-Robin 2448215976Sjmallett NOTE: This should only be written to a different value 2449215976Sjmallett during power-on SW initialization. */ 2450215976Sjmallett uint64_t reserved_3_7 : 5; 2451215976Sjmallett uint64_t dteclkdis : 1; /**< DFA DTE Clock Disable 2452215976Sjmallett When SET, the DFA clocks for DTE(thread engine) 2453215976Sjmallett operation are disabled. 2454215976Sjmallett NOTE: When SET, SW MUST NEVER issue ANY operations to 2455215976Sjmallett the DFA via the NCB Bus. All DFA Operations must be 2456215976Sjmallett issued solely through the CP2 interface. */ 2457215976Sjmallett uint64_t maxbnk : 1; /**< Maximum Banks per-device (used by the address mapper 2458215976Sjmallett when extracting address bits for the memory bank#. 2459215976Sjmallett - 0: 4 banks/device 2460215976Sjmallett - 1: 8 banks/device */ 2461215976Sjmallett uint64_t dfa_frstn : 1; /**< Hold this 0 until the DFA DDR PLL and DLL lock 2462215976Sjmallett and then write a 1. A 1 on this register deasserts 2463215976Sjmallett the internal frst_n. Refer to DFA_DDR2_PLL registers for more 2464215976Sjmallett startup information. 2465215976Sjmallett Startup sequence if DFA interface needs to be ON: 2466215976Sjmallett After valid power up, 2467215976Sjmallett Write DFA_DDR2_PLL-> PLL_RATIO & PLL_DIV2 & PLL_BYPASS 2468215976Sjmallett to the appropriate values 2469215976Sjmallett Wait a few cycles 2470215976Sjmallett Write a 1 DFA_DDR2_PLL -> PLL_INIT 2471215976Sjmallett Wait 100 microseconds 2472215976Sjmallett Write a 1 to DFA_DDR2_PLL -> QDLL_ENA 2473215976Sjmallett Wait 10 microseconds 2474215976Sjmallett Write a 1 to this register DFA_FRSTN to pull DFA out of 2475215976Sjmallett reset 2476215976Sjmallett Now the DFA block is ready to be initialized (follow the 2477215976Sjmallett DDR init sequence). */ 2478215976Sjmallett#else 2479215976Sjmallett uint64_t dfa_frstn : 1; 2480215976Sjmallett uint64_t maxbnk : 1; 2481215976Sjmallett uint64_t dteclkdis : 1; 2482215976Sjmallett uint64_t reserved_3_7 : 5; 2483215976Sjmallett uint64_t sarb : 1; 2484215976Sjmallett uint64_t imode : 1; 2485215976Sjmallett uint64_t qmode : 1; 2486215976Sjmallett uint64_t pmode : 1; 2487215976Sjmallett uint64_t dtmode : 1; 2488215976Sjmallett uint64_t dcmode : 1; 2489215976Sjmallett uint64_t sbdlck : 1; 2490215976Sjmallett uint64_t reserved_15_15 : 1; 2491215976Sjmallett uint64_t sbdnum : 3; 2492215976Sjmallett uint64_t reserved_19_63 : 45; 2493215976Sjmallett#endif 2494215976Sjmallett } s; 2495215976Sjmallett struct cvmx_dfa_eclkcfg_s cn31xx; 2496215976Sjmallett}; 2497215976Sjmalletttypedef union cvmx_dfa_eclkcfg cvmx_dfa_eclkcfg_t; 2498215976Sjmallett 2499215976Sjmallett/** 2500215976Sjmallett * cvmx_dfa_err 2501215976Sjmallett * 2502215976Sjmallett * DFA_ERR = DFA ERROR Register 2503215976Sjmallett * 2504215976Sjmallett * Description: 2505215976Sjmallett */ 2506215976Sjmallettunion cvmx_dfa_err 2507215976Sjmallett{ 2508215976Sjmallett uint64_t u64; 2509215976Sjmallett struct cvmx_dfa_err_s 2510215976Sjmallett { 2511215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2512215976Sjmallett uint64_t reserved_33_63 : 31; 2513215976Sjmallett uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 2514215976Sjmallett When set, doorbell overflow conditions are reported. */ 2515215976Sjmallett uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 2516215976Sjmallett When set, the 20b accumulated doorbell register 2517215976Sjmallett had overflowed (SW wrote too many doorbell requests). 2518215976Sjmallett If the DBLINA had previously been enabled(set), 2519215976Sjmallett an interrupt will be posted. Software can clear 2520215976Sjmallett the interrupt by writing a 1 to this register bit. 2521215976Sjmallett NOTE: Detection of a Doorbell Register overflow 2522215976Sjmallett is a catastrophic error which may leave the DFA 2523215976Sjmallett HW in an unrecoverable state. */ 2524215976Sjmallett uint64_t cp2pina : 1; /**< CP2 LW Mode Parity Error Interrupt Enable bit. 2525215976Sjmallett When set, all PP-generated LW Mode read 2526215976Sjmallett transactions which encounter a parity error (across 2527215976Sjmallett the 36b of data) are reported. */ 2528215976Sjmallett uint64_t cp2perr : 1; /**< PP-CP2 Parity Error Detected - Status bit 2529215976Sjmallett When set, a parity error had been detected for a 2530215976Sjmallett PP-generated LW Mode read transaction. 2531215976Sjmallett If the CP2PINA had previously been enabled(set), 2532215976Sjmallett an interrupt will be posted. Software can clear 2533215976Sjmallett the interrupt by writing a 1 to this register bit. 2534215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 2535215976Sjmallett about the memory address/control to help isolate 2536215976Sjmallett the failure. */ 2537215976Sjmallett uint64_t cp2parena : 1; /**< CP2 LW Mode Parity Error Enable 2538215976Sjmallett When set, all PP-generated LW Mode read 2539215976Sjmallett transactions which encounter a parity error (across 2540215976Sjmallett the 36b of data) are reported. 2541215976Sjmallett NOTE: This signal must only be written to a different 2542215976Sjmallett value when there are no PP-CP2 transactions 2543215976Sjmallett (preferrably during power-on software initialization). */ 2544215976Sjmallett uint64_t dtepina : 1; /**< DTE Parity Error Interrupt Enable bit 2545215976Sjmallett (for 18b SIMPLE mode ONLY). 2546215976Sjmallett When set, all DTE-generated 18b SIMPLE Mode read 2547215976Sjmallett transactions which encounter a parity error (across 2548215976Sjmallett the 17b of data) are reported. */ 2549215976Sjmallett uint64_t dteperr : 1; /**< DTE Parity Error Detected (for 18b SIMPLE mode ONLY) 2550215976Sjmallett When set, all DTE-generated 18b SIMPLE Mode read 2551215976Sjmallett transactions which encounter a parity error (across 2552215976Sjmallett the 17b of data) are reported. */ 2553215976Sjmallett uint64_t dteparena : 1; /**< DTE Parity Error Enable (for 18b SIMPLE mode ONLY) 2554215976Sjmallett When set, all DTE-generated 18b SIMPLE Mode read 2555215976Sjmallett transactions which encounter a parity error (across 2556215976Sjmallett the 17b of data) are reported. 2557215976Sjmallett NOTE: This signal must only be written to a different 2558215976Sjmallett value when there are no DFA thread engines active 2559215976Sjmallett (preferrably during power-on). */ 2560215976Sjmallett uint64_t dtesyn : 7; /**< DTE 29b ECC Failing 6bit Syndrome 2561215976Sjmallett When DTESBE or DTEDBE are set, this field contains 2562215976Sjmallett the failing 7b ECC syndrome. */ 2563215976Sjmallett uint64_t dtedbina : 1; /**< DTE 29b Double Bit Error Interrupt Enable bit 2564215976Sjmallett When set, an interrupt is posted for any DTE-generated 2565215976Sjmallett 36b SIMPLE Mode read which encounters a double bit 2566215976Sjmallett error. */ 2567215976Sjmallett uint64_t dtesbina : 1; /**< DTE 29b Single Bit Error Interrupt Enable bit 2568215976Sjmallett When set, an interrupt is posted for any DTE-generated 2569215976Sjmallett 36b SIMPLE Mode read which encounters a single bit 2570215976Sjmallett error (which is also corrected). */ 2571215976Sjmallett uint64_t dtedbe : 1; /**< DTE 29b Double Bit Error Detected - Status bit 2572215976Sjmallett When set, a double bit error had been detected 2573215976Sjmallett for a DTE-generated 36b SIMPLE Mode read transaction. 2574215976Sjmallett The DTESYN contains the failing syndrome. 2575215976Sjmallett If the DTEDBINA had previously been enabled(set), 2576215976Sjmallett an interrupt will be posted. Software can clear 2577215976Sjmallett the interrupt by writing a 1 to this register bit. 2578215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 2579215976Sjmallett about the memory address/control to help isolate 2580215976Sjmallett the failure. 2581215976Sjmallett NOTE: DTE-generated 18b SIMPLE Mode Read transactions 2582215976Sjmallett do not participate in ECC check/correct). */ 2583215976Sjmallett uint64_t dtesbe : 1; /**< DTE 29b Single Bit Error Corrected - Status bit 2584215976Sjmallett When set, a single bit error had been detected and 2585215976Sjmallett corrected for a DTE-generated 36b SIMPLE Mode read 2586215976Sjmallett transaction. 2587215976Sjmallett If the DTEDBE=0, then the DTESYN contains the 2588215976Sjmallett failing syndrome (used during correction). 2589215976Sjmallett NOTE: DTE-generated 18b SIMPLE Mode Read 2590215976Sjmallett transactions do not participate in ECC check/correct). 2591215976Sjmallett If the DTESBINA had previously been enabled(set), 2592215976Sjmallett an interrupt will be posted. Software can clear 2593215976Sjmallett the interrupt by writing a 1 to this register bit. 2594215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 2595215976Sjmallett about the memory address/control to help isolate 2596215976Sjmallett the failure. */ 2597215976Sjmallett uint64_t dteeccena : 1; /**< DTE 29b ECC Enable (for 36b SIMPLE mode ONLY) 2598215976Sjmallett When set, 29b ECC is enabled on all DTE-generated 2599215976Sjmallett 36b SIMPLE Mode read transactions. 2600215976Sjmallett NOTE: This signal must only be written to a different 2601215976Sjmallett value when there are no DFA thread engines active 2602215976Sjmallett (preferrably during power-on software initialization). */ 2603215976Sjmallett uint64_t cp2syn : 8; /**< PP-CP2 QW ECC Failing 8bit Syndrome 2604215976Sjmallett When CP2SBE or CP2DBE are set, this field contains 2605215976Sjmallett the failing ECC 8b syndrome. 2606215976Sjmallett Refer to CP2ECCENA. */ 2607215976Sjmallett uint64_t cp2dbina : 1; /**< PP-CP2 Double Bit Error Interrupt Enable bit 2608215976Sjmallett When set, an interrupt is posted for any PP-generated 2609215976Sjmallett QW Mode read which encounters a double bit error. 2610215976Sjmallett Refer to CP2DBE. */ 2611215976Sjmallett uint64_t cp2sbina : 1; /**< PP-CP2 Single Bit Error Interrupt Enable bit 2612215976Sjmallett When set, an interrupt is posted for any PP-generated 2613215976Sjmallett QW Mode read which encounters a single bit error 2614215976Sjmallett (which is also corrected). 2615215976Sjmallett Refer to CP2SBE. */ 2616215976Sjmallett uint64_t cp2dbe : 1; /**< PP-CP2 Double Bit Error Detected - Status bit 2617215976Sjmallett When set, a double bit error had been detected 2618215976Sjmallett for a PP-generated QW Mode read transaction. 2619215976Sjmallett The CP2SYN contains the failing syndrome. 2620215976Sjmallett NOTE: PP-generated LW Mode Read transactions 2621215976Sjmallett do not participate in ECC check/correct). 2622215976Sjmallett Refer to CP2ECCENA. 2623215976Sjmallett If the CP2DBINA had previously been enabled(set), 2624215976Sjmallett an interrupt will be posted. Software can clear 2625215976Sjmallett the interrupt by writing a 1 to this register bit. 2626215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 2627215976Sjmallett about the memory address/control to help isolate 2628215976Sjmallett the failure. */ 2629215976Sjmallett uint64_t cp2sbe : 1; /**< PP-CP2 Single Bit Error Corrected - Status bit 2630215976Sjmallett When set, a single bit error had been detected and 2631215976Sjmallett corrected for a PP-generated QW Mode read 2632215976Sjmallett transaction. 2633215976Sjmallett If the CP2DBE=0, then the CP2SYN contains the 2634215976Sjmallett failing syndrome (used during correction). 2635215976Sjmallett Refer to CP2ECCENA. 2636215976Sjmallett If the CP2SBINA had previously been enabled(set), 2637215976Sjmallett an interrupt will be posted. Software can clear 2638215976Sjmallett the interrupt by writing a 1 to this register bit. 2639215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 2640215976Sjmallett about the memory address/control to help isolate 2641215976Sjmallett the failure. 2642215976Sjmallett NOTE: PP-generated LW Mode Read transactions 2643215976Sjmallett do not participate in ECC check/correct). */ 2644215976Sjmallett uint64_t cp2eccena : 1; /**< PP-CP2 QW ECC Enable (for QW Mode transactions) 2645215976Sjmallett When set, 8bit QW ECC is enabled on all PP-generated 2646215976Sjmallett QW Mode read transactions, CP2SBE and 2647215976Sjmallett CP2DBE may be set, and CP2SYN may be filled. 2648215976Sjmallett NOTE: This signal must only be written to a different 2649215976Sjmallett value when there are no PP-CP2 transactions 2650215976Sjmallett (preferrably during power-on software initialization). 2651215976Sjmallett NOTE: QW refers to a 64-bit LLM Load/Store (intiated 2652215976Sjmallett by a processor core). LW refers to a 36-bit load/store. */ 2653215976Sjmallett#else 2654215976Sjmallett uint64_t cp2eccena : 1; 2655215976Sjmallett uint64_t cp2sbe : 1; 2656215976Sjmallett uint64_t cp2dbe : 1; 2657215976Sjmallett uint64_t cp2sbina : 1; 2658215976Sjmallett uint64_t cp2dbina : 1; 2659215976Sjmallett uint64_t cp2syn : 8; 2660215976Sjmallett uint64_t dteeccena : 1; 2661215976Sjmallett uint64_t dtesbe : 1; 2662215976Sjmallett uint64_t dtedbe : 1; 2663215976Sjmallett uint64_t dtesbina : 1; 2664215976Sjmallett uint64_t dtedbina : 1; 2665215976Sjmallett uint64_t dtesyn : 7; 2666215976Sjmallett uint64_t dteparena : 1; 2667215976Sjmallett uint64_t dteperr : 1; 2668215976Sjmallett uint64_t dtepina : 1; 2669215976Sjmallett uint64_t cp2parena : 1; 2670215976Sjmallett uint64_t cp2perr : 1; 2671215976Sjmallett uint64_t cp2pina : 1; 2672215976Sjmallett uint64_t dblovf : 1; 2673215976Sjmallett uint64_t dblina : 1; 2674215976Sjmallett uint64_t reserved_33_63 : 31; 2675215976Sjmallett#endif 2676215976Sjmallett } s; 2677215976Sjmallett struct cvmx_dfa_err_s cn31xx; 2678215976Sjmallett struct cvmx_dfa_err_s cn38xx; 2679215976Sjmallett struct cvmx_dfa_err_s cn38xxp2; 2680215976Sjmallett struct cvmx_dfa_err_s cn58xx; 2681215976Sjmallett struct cvmx_dfa_err_s cn58xxp1; 2682215976Sjmallett}; 2683215976Sjmalletttypedef union cvmx_dfa_err cvmx_dfa_err_t; 2684215976Sjmallett 2685215976Sjmallett/** 2686215976Sjmallett * cvmx_dfa_error 2687215976Sjmallett * 2688215976Sjmallett * DFA_ERROR = DFA ERROR Register 2689215976Sjmallett * 2690215976Sjmallett * Description: 2691215976Sjmallett */ 2692215976Sjmallettunion cvmx_dfa_error 2693215976Sjmallett{ 2694215976Sjmallett uint64_t u64; 2695215976Sjmallett struct cvmx_dfa_error_s 2696215976Sjmallett { 2697215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2698215976Sjmallett uint64_t reserved_17_63 : 47; 2699215976Sjmallett uint64_t cndrd : 1; /**< If DC0PERR[0]=1 indicating a RAM1 Parity error, 2700215976Sjmallett this additional bit further specifies that the 2701215976Sjmallett RAM1 parity error was detected during a CND-RD 2702215976Sjmallett (Cache Node Metadata Read). 2703215976Sjmallett 2704215976Sjmallett For CNDRD Parity Error, the previous CNA arc fetch 2705215976Sjmallett information is written to RWORD1+ as follows: 2706215976Sjmallett RWORD1+[NTYPE]=MNODE 2707215976Sjmallett RWORD1+[NDNID]=cna.ndnid 2708215976Sjmallett RWORD1+[NHMSK]=cna.hmsk 2709215976Sjmallett RWORD1+[NNPTR]=cna.nnptr[13:0] */ 2710215976Sjmallett uint64_t reserved_4_15 : 12; 2711215976Sjmallett uint64_t dc0perr : 3; /**< RAM[3:1] Parity Error Detected from Node Cluster \#0 2712215976Sjmallett See also DFA_DTCFADR register which contains the 2713215976Sjmallett failing addresses for the internal node cache RAMs. */ 2714215976Sjmallett uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 2715215976Sjmallett When set, the 20b accumulated doorbell register 2716215976Sjmallett had overflowed (SW wrote too many doorbell requests). 2717215976Sjmallett If the DBLINA had previously been enabled(set), 2718215976Sjmallett an interrupt will be posted. Software can clear 2719215976Sjmallett the interrupt by writing a 1 to this register bit. 2720215976Sjmallett NOTE: Detection of a Doorbell Register overflow 2721215976Sjmallett is a catastrophic error which may leave the DFA 2722215976Sjmallett HW in an unrecoverable state. */ 2723215976Sjmallett#else 2724215976Sjmallett uint64_t dblovf : 1; 2725215976Sjmallett uint64_t dc0perr : 3; 2726215976Sjmallett uint64_t reserved_4_15 : 12; 2727215976Sjmallett uint64_t cndrd : 1; 2728215976Sjmallett uint64_t reserved_17_63 : 47; 2729215976Sjmallett#endif 2730215976Sjmallett } s; 2731215976Sjmallett struct cvmx_dfa_error_s cn63xx; 2732215976Sjmallett struct cvmx_dfa_error_s cn63xxp1; 2733215976Sjmallett}; 2734215976Sjmalletttypedef union cvmx_dfa_error cvmx_dfa_error_t; 2735215976Sjmallett 2736215976Sjmallett/** 2737215976Sjmallett * cvmx_dfa_intmsk 2738215976Sjmallett * 2739215976Sjmallett * DFA_INTMSK = DFA ERROR Interrupt Mask Register 2740215976Sjmallett * 2741215976Sjmallett * Description: 2742215976Sjmallett */ 2743215976Sjmallettunion cvmx_dfa_intmsk 2744215976Sjmallett{ 2745215976Sjmallett uint64_t u64; 2746215976Sjmallett struct cvmx_dfa_intmsk_s 2747215976Sjmallett { 2748215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2749215976Sjmallett uint64_t reserved_4_63 : 60; 2750215976Sjmallett uint64_t dc0pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */ 2751215976Sjmallett uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 2752215976Sjmallett When set, doorbell overflow conditions are reported. */ 2753215976Sjmallett#else 2754215976Sjmallett uint64_t dblina : 1; 2755215976Sjmallett uint64_t dc0pena : 3; 2756215976Sjmallett uint64_t reserved_4_63 : 60; 2757215976Sjmallett#endif 2758215976Sjmallett } s; 2759215976Sjmallett struct cvmx_dfa_intmsk_s cn63xx; 2760215976Sjmallett struct cvmx_dfa_intmsk_s cn63xxp1; 2761215976Sjmallett}; 2762215976Sjmalletttypedef union cvmx_dfa_intmsk cvmx_dfa_intmsk_t; 2763215976Sjmallett 2764215976Sjmallett/** 2765215976Sjmallett * cvmx_dfa_memcfg0 2766215976Sjmallett * 2767215976Sjmallett * DFA_MEMCFG0 = DFA Memory Configuration 2768215976Sjmallett * 2769215976Sjmallett * Description: 2770215976Sjmallett */ 2771215976Sjmallettunion cvmx_dfa_memcfg0 2772215976Sjmallett{ 2773215976Sjmallett uint64_t u64; 2774215976Sjmallett struct cvmx_dfa_memcfg0_s 2775215976Sjmallett { 2776215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2777215976Sjmallett uint64_t reserved_32_63 : 32; 2778215976Sjmallett uint64_t rldqck90_rst : 1; /**< RLDCK90 and RLDQK90 DLL SW Reset 2779215976Sjmallett When written with a '1' the RLDCK90 and RLDQK90 DLL are 2780215976Sjmallett in soft-reset. */ 2781215976Sjmallett uint64_t rldck_rst : 1; /**< RLDCK Zero Delay DLL(Clock Generator) SW Reset 2782215976Sjmallett When written with a '1' the RLDCK zero delay DLL is in 2783215976Sjmallett soft-reset. */ 2784215976Sjmallett uint64_t clkdiv : 2; /**< RLDCLK Divisor Select 2785215976Sjmallett - 0: RLDx_CK_H/L = Core Clock /2 2786215976Sjmallett - 1: RESERVED (must not be used) 2787215976Sjmallett - 2: RLDx_CK_H/L = Core Clock /3 2788215976Sjmallett - 3: RLDx_CK_H/L = Core Clock /4 2789215976Sjmallett The DFA LLM interface(s) are tied to the core clock 2790215976Sjmallett frequency through this programmable clock divisor. 2791215976Sjmallett Examples: 2792215976Sjmallett Core Clock(MHz) | DFA-LLM Clock(MHz) | CLKDIV 2793215976Sjmallett -----------------+--------------------+-------- 2794215976Sjmallett 800 | 400/(800-DDR) | /2 2795215976Sjmallett 1000 | 333/(666-DDR) | /3 2796215976Sjmallett 800 | 200/(400-DDR) | /4 2797215976Sjmallett NOTE: This value MUST BE programmed BEFORE doing a 2798215976Sjmallett Hardware init sequence (see: DFA_MEMCFG0[INIT_Px] bits). */ 2799215976Sjmallett uint64_t lpp_ena : 1; /**< PP Linear Port Addressing Mode Enable 2800215976Sjmallett When enabled, PP-core LLM accesses to the lower-512MB 2801215976Sjmallett LLM address space are sent to the single DFA port 2802215976Sjmallett which is enabled. NOTE: If LPP_ENA=1, only 2803215976Sjmallett one DFA RLDRAM port may be enabled for RLDRAM accesses 2804215976Sjmallett (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set). 2805215976Sjmallett PP-core LLM accesses to the upper-512MB LLM address 2806215976Sjmallett space are sent to the other 'disabled' DFA port. 2807215976Sjmallett SW RESTRICTION: If LPP_ENA=1, then only one DFA port 2808215976Sjmallett may be enabled for RLDRAM accesses (ie: ENA_P0 and 2809215976Sjmallett ENA_P1 CAN NEVER BOTH be set). 2810215976Sjmallett NOTE: This bit is used to allow PP-Core LLM accesses to a 2811215976Sjmallett disabled port, such that each port can be sequentially 2812215976Sjmallett addressed (ie: disable LW address interleaving). 2813215976Sjmallett Enabling this bit allows BOTH PORTs to be active and 2814215976Sjmallett sequentially addressable. The single port that is 2815215976Sjmallett enabled(ENA_Px) will respond to the low-512MB LLM address 2816215976Sjmallett space, and the other 'disabled' port will respond to the 2817215976Sjmallett high-512MB LLM address space. 2818215976Sjmallett Example usage: 2819215976Sjmallett - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses) 2820215976Sjmallett - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses). 2821215976Sjmallett USAGE NOTE: 2822215976Sjmallett If LPP_ENA=1 and SW DOES NOT initialize the disabled port 2823215976Sjmallett (ie: INIT_Px=0->1), then refreshes and the HW init 2824215976Sjmallett sequence WILL NOT occur for the disabled port. 2825215976Sjmallett If LPP_ENA=1 and SW does initialize the disabled port 2826215976Sjmallett (INIT_Px=0->1 with ENA_Px=0), then refreshes and 2827215976Sjmallett the HW init sequence WILL occur to the disabled port. */ 2828215976Sjmallett uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization 2829215976Sjmallett sequence (triggered by DFA_MEMCFG0[INIT_Px]) or 2830215976Sjmallett b) during a normal refresh sequence. If 2831215976Sjmallett the BNK_INIT[x]=1, the corresponding CS_N[x] is driven. 2832215976Sjmallett NOTE: This is required for DRAM used in a 2833215976Sjmallett clamshell configuration, since the address lines 2834215976Sjmallett carry Mode Register write data that is unique 2835215976Sjmallett per bunk(or clam). In a clamshell configuration, 2836215976Sjmallett The N3K A[x] pin may be tied into Clam#0's A[x] 2837215976Sjmallett and also into Clam#1's 'mirrored' address bit A[y] 2838215976Sjmallett (eg: Clam0 sees A[5] and Clam1 sees A[15]). 2839215976Sjmallett To support clamshell designs, SW must initiate 2840215976Sjmallett two separate HW init sequences for the two bunks 2841215976Sjmallett (or clams) . Before each HW init sequence is triggered, 2842215976Sjmallett SW must preload the DFA_MEMRLD[22:0] with the data 2843215976Sjmallett that will be driven onto the A[22:0] wires during 2844215976Sjmallett an MRS mode register write. 2845215976Sjmallett NOTE: After the final HW initialization sequence has 2846215976Sjmallett been triggered, SW must wait 64K eclks before writing 2847215976Sjmallett the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is 2848215976Sjmallett driven during refresh sequences in normal operation. 2849215976Sjmallett NOTE: This should only be written to a different value 2850215976Sjmallett during power-on SW initialization. */ 2851215976Sjmallett uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'), 2852215976Sjmallett the HW init sequence(s) for Memory Port \#0 is 2853215976Sjmallett initiated. 2854215976Sjmallett NOTE: To initialize memory, SW must: 2855215976Sjmallett 1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended 2856215976Sjmallett RLDRAM operation. 2857215976Sjmallett [legal values 0: DIV2 2: DIV3 3: DIV4] 2858215976Sjmallett 2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST] 2859215976Sjmallett and DFA_MEM_CFG0[RLDQCK90_RST] field at 2860215976Sjmallett the SAME TIME. This step puts all three DLLs in 2861215976Sjmallett SW reset (RLDCK, RLDCK90, RLDQK90 DLLs). 2862215976Sjmallett 3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field. 2863215976Sjmallett This step takes the RLDCK DLL out of soft-reset so 2864215976Sjmallett that the DLL can generate the RLDx_CK_H/L clock pins. 2865215976Sjmallett 4) Wait 1ms (for RLDCK DLL to achieve lock) 2866215976Sjmallett 5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field. 2867215976Sjmallett This step takes the RLDCK90 DLL AND RLDQK90 DLL out 2868215976Sjmallett of soft-reset. 2869215976Sjmallett 6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock) 2870215976Sjmallett 7) Enable memory port(s): ENA_P0=1/ENA_P1=1 2871215976Sjmallett 8) Wait 100us (to ensure a stable clock 2872215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 2873215976Sjmallett - - - - - Hardware Initialization Sequence - - - - - 2874215976Sjmallett 9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s) 2875215976Sjmallett intended to be initialized. 2876215976Sjmallett 10) Write a '1' to the corresponding INIT_Px which 2877215976Sjmallett will initiate a hardware initialization 2878215976Sjmallett sequence to that'specific' port. 2879215976Sjmallett 11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles. 2880215976Sjmallett [to ensure the HW init sequence has completed 2881215976Sjmallett before writing to ANY of the DFA_MEM* registers] 2882215976Sjmallett - - - - - Hardware Initialization Sequence - - - - - 2883215976Sjmallett 12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable 2884215976Sjmallett refreshes to BOTH bunks. 2885215976Sjmallett NOTE: In some cases (where the address wires are routed 2886215976Sjmallett differently between the front and back 'bunks'), 2887215976Sjmallett SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to 2888215976Sjmallett control the Hardware initialization sequence for a 2889215976Sjmallett 'specific bunk'. In these cases, SW would setup the 2890215976Sjmallett BUNK_INIT and repeat Steps \#9-11 for each bunk/port. 2891215976Sjmallett NOTE: This should only be written to a different value 2892215976Sjmallett during power-on SW initialization. 2893215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 2894215976Sjmallett RLD0_* pins. */ 2895215976Sjmallett uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'), 2896215976Sjmallett the HW init sequence(s) for Memory Port \#1 is 2897215976Sjmallett initiated. 2898215976Sjmallett NOTE: To initialize memory, SW must: 2899215976Sjmallett 1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended 2900215976Sjmallett RLDRAM operation. 2901215976Sjmallett [legal values 0: DIV2 2: DIV3 3: DIV4] 2902215976Sjmallett 2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST] 2903215976Sjmallett and DFA_MEM_CFG0[RLDQCK90_RST] field at 2904215976Sjmallett the SAME TIME. This step puts all three DLLs in 2905215976Sjmallett SW reset (RLDCK, RLDCK90, RLDQK90 DLLs). 2906215976Sjmallett 3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field. 2907215976Sjmallett This step takes the RLDCK DLL out of soft-reset so 2908215976Sjmallett that the DLL can generate the RLDx_CK_H/L clock pins. 2909215976Sjmallett 4) Wait 1ms (for RLDCK DLL to achieve lock) 2910215976Sjmallett 5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field. 2911215976Sjmallett This step takes the RLDCK90 DLL AND RLDQK90 DLL out 2912215976Sjmallett of soft-reset. 2913215976Sjmallett 6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock) 2914215976Sjmallett 7) Enable memory port(s) ENA_P0=1/ENA_P1=1 2915215976Sjmallett 8) Wait 100us (to ensure a stable clock 2916215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 2917215976Sjmallett - - - - - Hardware Initialization Sequence - - - - - 2918215976Sjmallett 9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s) 2919215976Sjmallett intended to be initialized. 2920215976Sjmallett 10) Write a '1' to the corresponding INIT_Px which 2921215976Sjmallett will initiate a hardware initialization 2922215976Sjmallett sequence to that'specific' port. 2923215976Sjmallett 11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles. 2924215976Sjmallett [to ensure the HW init sequence has completed 2925215976Sjmallett before writing to ANY of the DFA_MEM* registers] 2926215976Sjmallett - - - - - Hardware Initialization Sequence - - - - - 2927215976Sjmallett 12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable 2928215976Sjmallett refreshes to BOTH bunks. 2929215976Sjmallett NOTE: In some cases (where the address wires are routed 2930215976Sjmallett differently between the front and back 'bunks'), 2931215976Sjmallett SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to 2932215976Sjmallett control the Hardware initialization sequence for a 2933215976Sjmallett 'specific bunk'. In these cases, SW would setup the 2934215976Sjmallett BUNK_INIT and repeat Steps \#9-11 for each bunk/port. 2935215976Sjmallett NOTE: This should only be written to a different value 2936215976Sjmallett during power-on SW initialization. 2937215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 2938215976Sjmallett RLD1_* pins. */ 2939215976Sjmallett uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted 2940215976Sjmallett if back to back reads are issued to different physical 2941215976Sjmallett bunks. This is to avoid DQ data bus collisions when 2942215976Sjmallett references cross between physical bunks. 2943215976Sjmallett [NOTE: the physical bunk address boundary is determined 2944215976Sjmallett by the PBUNK bit]. 2945215976Sjmallett NOTE: This should only be written to a different value 2946215976Sjmallett during power-on SW initialization. */ 2947215976Sjmallett uint64_t pbunk : 3; /**< Physical Bunk address bit pointer. 2948215976Sjmallett Specifies which address bit within the Longword 2949215976Sjmallett Memory address MA[23:0] is used to determine the 2950215976Sjmallett chip selects. 2951215976Sjmallett [RLD_CS0_N corresponds to physical bunk \#0, and 2952215976Sjmallett RLD_CS1_N corresponds to physical bunk \#1]. 2953215976Sjmallett - 000: CS0_N = MA[19]/CS1_N = !MA[19] 2954215976Sjmallett - 001: CS0_N = MA[20]/CS1_N = !MA[20] 2955215976Sjmallett - 010: CS0_N = MA[21]/CS1_N = !MA[21] 2956215976Sjmallett - 011: CS0_N = MA[22]/CS1_N = !MA[22] 2957215976Sjmallett - 100: CS0_N = MA[23]/CS1_N = !MA[23] 2958215976Sjmallett - 101-111: CS0_N = 0 /CS1_N = 1 2959215976Sjmallett Example(s): 2960215976Sjmallett To build out a 128MB DFA memory, 4x 32Mx9 2961215976Sjmallett parts could be used to fill out TWO physical 2962215976Sjmallett bunks (clamshell configuration). Each (of the 2963215976Sjmallett two) physical bunks contains 2x 32Mx9 = 16Mx36. 2964215976Sjmallett Each RLDRAM device also contains 8 internal banks, 2965215976Sjmallett therefore the memory Address is 16M/8banks = 2M 2966215976Sjmallett addresses/bunk (2^21). In this case, MA[21] would 2967215976Sjmallett select the physical bunk. 2968215976Sjmallett NOTE: This should only be written to a different value 2969215976Sjmallett during power-on SW initialization. 2970215976Sjmallett be used to determine the Chip Select(s). */ 2971215976Sjmallett uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst) 2972215976Sjmallett NOTE: RLDRAM-II MUST USE BLEN=0(2-burst) */ 2973215976Sjmallett uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks) 2974215976Sjmallett On reads, allows user to control the shape of the 2975215976Sjmallett tristate disable back porch for the DQ data bus. 2976215976Sjmallett This parameter is also very dependent on the 2977215976Sjmallett RW_DLY and WR_DLY parameters and care must be 2978215976Sjmallett taken when programming these parameters to avoid 2979215976Sjmallett data bus contention. Valid range [0..2] 2980215976Sjmallett NOTE: This should only be written to a different value 2981215976Sjmallett during power-on SW initialization. */ 2982215976Sjmallett uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks) 2983215976Sjmallett On reads, allows user to control the shape of the 2984215976Sjmallett tristate disable front porch for the DQ data bus. 2985215976Sjmallett This parameter is also very dependent on the 2986215976Sjmallett RW_DLY and WR_DLY parameters and care must be 2987215976Sjmallett taken when programming these parameters to avoid 2988215976Sjmallett data bus contention. Valid range [0..2] 2989215976Sjmallett NOTE: This should only be written to a different value 2990215976Sjmallett during power-on SW initialization. */ 2991215976Sjmallett uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks): 2992215976Sjmallett Determines \#mclk cycles to insert when controller 2993215976Sjmallett switches from write to read. This allows programmer 2994215976Sjmallett to control the data bus contention. 2995215976Sjmallett For RLDRAM-II(BL2): (TBL=1) 2996215976Sjmallett WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1 2997215976Sjmallett NOTE: This should only be written to a different value 2998215976Sjmallett during power-on SW initialization. 2999215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3000215976Sjmallett the WR_DLY 'may' be tuned down(-1) if bus fight 3001215976Sjmallett on W->R transitions is not pronounced. */ 3002215976Sjmallett uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks): 3003215976Sjmallett Determines \#mclk cycles to insert when controller 3004215976Sjmallett switches from read to write. This allows programmer 3005215976Sjmallett to control the data bus contention. 3006215976Sjmallett For RLDRAM-II(BL2): (TBL=1) 3007215976Sjmallett RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1 3008215976Sjmallett NOTE: This should only be written to a different value 3009215976Sjmallett during power-on SW initialization. 3010215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3011215976Sjmallett the RW_DLY 'may' be tuned down(-1) if bus fight 3012215976Sjmallett on R->W transitions is not pronounced. */ 3013215976Sjmallett uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many 3014215976Sjmallett additional dclks to wait (on top of tRL+1) before 3015215976Sjmallett pulling data out of the padring silos used for time 3016215976Sjmallett domain boundary crossing. 3017215976Sjmallett NOTE: This should only be written to a different value 3018215976Sjmallett during power-on SW initialization. */ 3019215976Sjmallett uint64_t mtype : 1; /**< FCRAM-II Memory Type 3020215976Sjmallett *** CN58XX UNSUPPORTED *** */ 3021215976Sjmallett uint64_t reserved_2_2 : 1; 3022215976Sjmallett uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0 3023215976Sjmallett When enabled, this bit lets N3K be the default 3024215976Sjmallett driver for memory port \#0. 3025215976Sjmallett NOTE: a customer is at 3026215976Sjmallett liberty to enable either Port#0 or Port#1 or both. 3027215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 3028215976Sjmallett be re-enabled. [the only way to enable a port is 3029215976Sjmallett through a chip reset]. 3030215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 3031215976Sjmallett RLD0_* pins. */ 3032215976Sjmallett uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1 3033215976Sjmallett When enabled, this bit lets N3K be the default 3034215976Sjmallett driver for memory port \#1. 3035215976Sjmallett NOTE: a customer is at 3036215976Sjmallett liberty to enable either Port#0 or Port#1 or both. 3037215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 3038215976Sjmallett be re-enabled. [the only way to enable a port is 3039215976Sjmallett through a chip reset]. 3040215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 3041215976Sjmallett RLD1_* pins. */ 3042215976Sjmallett#else 3043215976Sjmallett uint64_t ena_p1 : 1; 3044215976Sjmallett uint64_t ena_p0 : 1; 3045215976Sjmallett uint64_t reserved_2_2 : 1; 3046215976Sjmallett uint64_t mtype : 1; 3047215976Sjmallett uint64_t sil_lat : 2; 3048215976Sjmallett uint64_t rw_dly : 4; 3049215976Sjmallett uint64_t wr_dly : 4; 3050215976Sjmallett uint64_t fprch : 2; 3051215976Sjmallett uint64_t bprch : 2; 3052215976Sjmallett uint64_t blen : 1; 3053215976Sjmallett uint64_t pbunk : 3; 3054215976Sjmallett uint64_t r2r_pbunk : 1; 3055215976Sjmallett uint64_t init_p1 : 1; 3056215976Sjmallett uint64_t init_p0 : 1; 3057215976Sjmallett uint64_t bunk_init : 2; 3058215976Sjmallett uint64_t lpp_ena : 1; 3059215976Sjmallett uint64_t clkdiv : 2; 3060215976Sjmallett uint64_t rldck_rst : 1; 3061215976Sjmallett uint64_t rldqck90_rst : 1; 3062215976Sjmallett uint64_t reserved_32_63 : 32; 3063215976Sjmallett#endif 3064215976Sjmallett } s; 3065215976Sjmallett struct cvmx_dfa_memcfg0_cn38xx 3066215976Sjmallett { 3067215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3068215976Sjmallett uint64_t reserved_28_63 : 36; 3069215976Sjmallett uint64_t lpp_ena : 1; /**< PP Linear Port Addressing Mode Enable 3070215976Sjmallett When enabled, PP-core LLM accesses to the lower-512MB 3071215976Sjmallett LLM address space are sent to the single DFA port 3072215976Sjmallett which is enabled. NOTE: If LPP_ENA=1, only 3073215976Sjmallett one DFA RLDRAM port may be enabled for RLDRAM accesses 3074215976Sjmallett (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set). 3075215976Sjmallett PP-core LLM accesses to the upper-512MB LLM address 3076215976Sjmallett space are sent to the other 'disabled' DFA port. 3077215976Sjmallett SW RESTRICTION: If LPP_ENA=1, then only one DFA port 3078215976Sjmallett may be enabled for RLDRAM accesses (ie: ENA_P0 and 3079215976Sjmallett ENA_P1 CAN NEVER BOTH be set). 3080215976Sjmallett NOTE: This bit is used to allow PP-Core LLM accesses to a 3081215976Sjmallett disabled port, such that each port can be sequentially 3082215976Sjmallett addressed (ie: disable LW address interleaving). 3083215976Sjmallett Enabling this bit allows BOTH PORTs to be active and 3084215976Sjmallett sequentially addressable. The single port that is 3085215976Sjmallett enabled(ENA_Px) will respond to the low-512MB LLM address 3086215976Sjmallett space, and the other 'disabled' port will respond to the 3087215976Sjmallett high-512MB LLM address space. 3088215976Sjmallett Example usage: 3089215976Sjmallett - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses) 3090215976Sjmallett - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses). 3091215976Sjmallett USAGE NOTE: 3092215976Sjmallett If LPP_ENA=1 and SW DOES NOT initialize the disabled port 3093215976Sjmallett (ie: INIT_Px=0->1), then refreshes and the HW init 3094215976Sjmallett sequence WILL NOT occur for the disabled port. 3095215976Sjmallett If LPP_ENA=1 and SW does initialize the disabled port 3096215976Sjmallett (INIT_Px=0->1 with ENA_Px=0), then refreshes and 3097215976Sjmallett the HW init sequence WILL occur to the disabled port. */ 3098215976Sjmallett uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization 3099215976Sjmallett sequence (triggered by DFA_MEMCFG0[INIT_Px]) or 3100215976Sjmallett b) during a normal refresh sequence. If 3101215976Sjmallett the BNK_INIT[x]=1, the corresponding CS_N[x] is driven. 3102215976Sjmallett NOTE: This is required for DRAM used in a 3103215976Sjmallett clamshell configuration, since the address lines 3104215976Sjmallett carry Mode Register write data that is unique 3105215976Sjmallett per bunk(or clam). In a clamshell configuration, 3106215976Sjmallett The N3K A[x] pin may be tied into Clam#0's A[x] 3107215976Sjmallett and also into Clam#1's 'mirrored' address bit A[y] 3108215976Sjmallett (eg: Clam0 sees A[5] and Clam1 sees A[15]). 3109215976Sjmallett To support clamshell designs, SW must initiate 3110215976Sjmallett two separate HW init sequences for the two bunks 3111215976Sjmallett (or clams) . Before each HW init sequence is triggered, 3112215976Sjmallett SW must preload the DFA_MEMRLD[22:0] with the data 3113215976Sjmallett that will be driven onto the A[22:0] wires during 3114215976Sjmallett an MRS mode register write. 3115215976Sjmallett NOTE: After the final HW initialization sequence has 3116215976Sjmallett been triggered, SW must wait 64K eclks before writing 3117215976Sjmallett the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is 3118215976Sjmallett driven during refresh sequences in normal operation. 3119215976Sjmallett NOTE: This should only be written to a different value 3120215976Sjmallett during power-on SW initialization. 3121215976Sjmallett NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE 3122215976Sjmallett initialized independently. In other words, a HW init 3123215976Sjmallett must be done for Bunk#0, and then another HW init 3124215976Sjmallett must be done for Bunk#1 at power-on. */ 3125215976Sjmallett uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'), 3126215976Sjmallett the HW init sequence(s) for Memory Port \#0 is 3127215976Sjmallett initiated. 3128215976Sjmallett NOTE: To initialize memory, SW must: 3129215976Sjmallett 1) Enable memory port(s): 3130215976Sjmallett a) ENA_P1=1 (single port in pass 1) OR 3131215976Sjmallett b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 3132215976Sjmallett 2) Wait 100us (to ensure a stable clock 3133215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 3134215976Sjmallett 3) Write a '1' to the corresponding INIT_Px which 3135215976Sjmallett will initiate a hardware initialization 3136215976Sjmallett sequence. 3137215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 3138215976Sjmallett cycles to ensure the HW init sequence has completed 3139215976Sjmallett before writing to ANY of the DFA_MEM* registers. 3140215976Sjmallett NOTE: This should only be written to a different value 3141215976Sjmallett during power-on SW initialization. 3142215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 3143215976Sjmallett RLD0_* pins. */ 3144215976Sjmallett uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'), 3145215976Sjmallett the HW init sequence(s) for Memory Port \#1 is 3146215976Sjmallett initiated. 3147215976Sjmallett NOTE: To initialize memory, SW must: 3148215976Sjmallett 1) Enable memory port(s): 3149215976Sjmallett a) ENA_P1=1 (single port in pass 1) OR 3150215976Sjmallett b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 3151215976Sjmallett 2) Wait 100us (to ensure a stable clock 3152215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 3153215976Sjmallett 3) Write a '1' to the corresponding INIT_Px which 3154215976Sjmallett will initiate a hardware initialization 3155215976Sjmallett sequence. 3156215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 3157215976Sjmallett cycles to ensure the HW init sequence has completed 3158215976Sjmallett before writing to ANY of the DFA_MEM* registers. 3159215976Sjmallett NOTE: This should only be written to a different value 3160215976Sjmallett during power-on SW initialization. 3161215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 3162215976Sjmallett RLD1_* pins. */ 3163215976Sjmallett uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted 3164215976Sjmallett if back to back reads are issued to different physical 3165215976Sjmallett bunks. This is to avoid DQ data bus collisions when 3166215976Sjmallett references cross between physical bunks. 3167215976Sjmallett [NOTE: the physical bunk address boundary is determined 3168215976Sjmallett by the PBUNK bit]. 3169215976Sjmallett NOTE: This should only be written to a different value 3170215976Sjmallett during power-on SW initialization. 3171215976Sjmallett When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE 3172215976Sjmallett ZERO(for optimal performance). However, if electrically, 3173215976Sjmallett DQ-sharing becomes a power/heat issue, then R2R_PBUNK 3174215976Sjmallett should be set (but at a cost to performance (1/2 BW). */ 3175215976Sjmallett uint64_t pbunk : 3; /**< Physical Bunk address bit pointer. 3176215976Sjmallett Specifies which address bit within the Longword 3177215976Sjmallett Memory address MA[23:0] is used to determine the 3178215976Sjmallett chip selects. 3179215976Sjmallett [RLD_CS0_N corresponds to physical bunk \#0, and 3180215976Sjmallett RLD_CS1_N corresponds to physical bunk \#1]. 3181215976Sjmallett - 000: CS0_N = MA[19]/CS1_N = !MA[19] 3182215976Sjmallett - 001: CS0_N = MA[20]/CS1_N = !MA[20] 3183215976Sjmallett - 010: CS0_N = MA[21]/CS1_N = !MA[21] 3184215976Sjmallett - 011: CS0_N = MA[22]/CS1_N = !MA[22] 3185215976Sjmallett - 100: CS0_N = MA[23]/CS1_N = !MA[23] 3186215976Sjmallett - 101-111: CS0_N = 0 /CS1_N = 1 3187215976Sjmallett Example(s): 3188215976Sjmallett To build out a 128MB DFA memory, 4x 32Mx9 3189215976Sjmallett parts could be used to fill out TWO physical 3190215976Sjmallett bunks (clamshell configuration). Each (of the 3191215976Sjmallett two) physical bunks contains 2x 32Mx9 = 16Mx36. 3192215976Sjmallett Each RLDRAM device also contains 8 internal banks, 3193215976Sjmallett therefore the memory Address is 16M/8banks = 2M 3194215976Sjmallett addresses/bunk (2^21). In this case, MA[21] would 3195215976Sjmallett select the physical bunk. 3196215976Sjmallett NOTE: This should only be written to a different value 3197215976Sjmallett during power-on SW initialization. 3198215976Sjmallett be used to determine the Chip Select(s). 3199215976Sjmallett NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a 3200215976Sjmallett "Redundant Bunk" scheme is employed to provide the 3201215976Sjmallett highest overall performance (1 Req/ MCLK cycle). 3202215976Sjmallett In this mode, it's imperative that SW set the PBUNK 3203215976Sjmallett field +1 'above' the highest address bit. (such that 3204215976Sjmallett the PBUNK extracted from the address will always be 3205215976Sjmallett zero). In this mode, the CS_N[1:0] pins are driven 3206215976Sjmallett to each redundant bunk based on a TDM scheme: 3207215976Sjmallett [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */ 3208215976Sjmallett uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst) 3209215976Sjmallett When BLEN=0(BL2), all QW reads/writes from CP2 are 3210215976Sjmallett decomposed into 2 separate BL2(LW) requests to the 3211215976Sjmallett Low-Latency memory. 3212215976Sjmallett When BLEN=1(BL4), a LW request (from CP2 or NCB) is 3213215976Sjmallett treated as 1 BL4(QW) request to the low latency memory. 3214215976Sjmallett NOTE: QW refers to a 64-bit LLM Load/Store (intiated 3215215976Sjmallett by a processor core). LW refers to a 36-bit load/store. 3216215976Sjmallett NOTE: This should only be written to a different value 3217215976Sjmallett during power-on SW initialization before the DFA LLM 3218215976Sjmallett (low latency memory) is used. 3219215976Sjmallett NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst) 3220215976Sjmallett NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a 3221215976Sjmallett multi-bunk(clam) board design. 3222215976Sjmallett NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4), 3223215976Sjmallett SW SHOULD use CP2 QW read/write requests (for 3224215976Sjmallett optimal low-latency bus performance). 3225215976Sjmallett [LW length read/write requests(in BL4 mode) use 50% 3226215976Sjmallett of the available bus bandwidth] 3227215976Sjmallett NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only 3228215976Sjmallett be used with FCRAM-II devices which support BL2 mode 3229215976Sjmallett (see: Toshiba FCRAM-II, where DQ tristate after 2 data 3230215976Sjmallett transfers). 3231215976Sjmallett NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW 3232215976Sjmallett write requests (FCRAM-II+ device specification has removed 3233215976Sjmallett the variable write mask function from the devices). 3234215976Sjmallett As such, if this mode is used, SW must be careful to 3235215976Sjmallett issue only PP-CP2 QW write requests. */ 3236215976Sjmallett uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks) 3237215976Sjmallett On reads, allows user to control the shape of the 3238215976Sjmallett tristate disable back porch for the DQ data bus. 3239215976Sjmallett This parameter is also very dependent on the 3240215976Sjmallett RW_DLY and WR_DLY parameters and care must be 3241215976Sjmallett taken when programming these parameters to avoid 3242215976Sjmallett data bus contention. Valid range [0..2] 3243215976Sjmallett NOTE: This should only be written to a different value 3244215976Sjmallett during power-on SW initialization. */ 3245215976Sjmallett uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks) 3246215976Sjmallett On reads, allows user to control the shape of the 3247215976Sjmallett tristate disable front porch for the DQ data bus. 3248215976Sjmallett This parameter is also very dependent on the 3249215976Sjmallett RW_DLY and WR_DLY parameters and care must be 3250215976Sjmallett taken when programming these parameters to avoid 3251215976Sjmallett data bus contention. Valid range [0..2] 3252215976Sjmallett NOTE: This should only be written to a different value 3253215976Sjmallett during power-on SW initialization. */ 3254215976Sjmallett uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks): 3255215976Sjmallett Determines \#mclk cycles to insert when controller 3256215976Sjmallett switches from write to read. This allows programmer 3257215976Sjmallett to control the data bus contention. 3258215976Sjmallett For RLDRAM-II(BL2): (TBL=1) 3259215976Sjmallett For FCRAM-II (BL4): (TBL=2) 3260215976Sjmallett For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1) 3261215976Sjmallett For FCRAM-II (BL2 grepl>=2x): (TBL=3) 3262215976Sjmallett NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode), 3263215976Sjmallett grepl>=2x, writes require redundant bunk writes 3264215976Sjmallett which require an additional 2 cycles before slotting 3265215976Sjmallett the next read. 3266215976Sjmallett WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1 3267215976Sjmallett NOTE: This should only be written to a different value 3268215976Sjmallett during power-on SW initialization. 3269215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3270215976Sjmallett the WR_DLY 'may' be tuned down(-1) if bus fight 3271215976Sjmallett on W->R transitions is not pronounced. */ 3272215976Sjmallett uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks): 3273215976Sjmallett Determines \#mclk cycles to insert when controller 3274215976Sjmallett switches from read to write. This allows programmer 3275215976Sjmallett to control the data bus contention. 3276215976Sjmallett For RLDRAM-II/FCRAM-II (BL2): (TBL=1) 3277215976Sjmallett For FCRAM-II (BL4): (TBL=2) 3278215976Sjmallett RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1 3279215976Sjmallett NOTE: This should only be written to a different value 3280215976Sjmallett during power-on SW initialization. 3281215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3282215976Sjmallett the RW_DLY 'may' be tuned down(-1) if bus fight 3283215976Sjmallett on R->W transitions is not pronounced. */ 3284215976Sjmallett uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many 3285215976Sjmallett additional dclks to wait (on top of tRL+1) before 3286215976Sjmallett pulling data out of the padring silos used for time 3287215976Sjmallett domain boundary crossing. 3288215976Sjmallett NOTE: This should only be written to a different value 3289215976Sjmallett during power-on SW initialization. */ 3290215976Sjmallett uint64_t mtype : 1; /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM) 3291215976Sjmallett NOTE: N3K-P1 only supports RLDRAM-II 3292215976Sjmallett NOTE: This should only be written to a different value 3293215976Sjmallett during power-on SW initialization. 3294215976Sjmallett NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the 3295215976Sjmallett "unidirectional DS/QS" mode is supported. (see FCRAM 3296215976Sjmallett data sheet EMRS[A6:A5]=SS(Strobe Select) register 3297215976Sjmallett definition. [in FCRAM 2-burst mode, we use FCRAM 3298215976Sjmallett in a clamshell configuration such that clam0 is 3299215976Sjmallett addressed independently of clam1, and DQ is shared 3300215976Sjmallett for optimal performance. As such it's imperative that 3301215976Sjmallett the QS are conditionally received (and are NOT 3302215976Sjmallett free-running), as the N3K receive data capture silos 3303215976Sjmallett OR the clam0/1 QS strobes. 3304215976Sjmallett NOTE: If this bit is SET, the ASX0/1 3305215976Sjmallett ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET 3306215976Sjmallett in order for the RLD0/1-PHY(s) to support FCRAM devices. */ 3307215976Sjmallett uint64_t reserved_2_2 : 1; 3308215976Sjmallett uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0 3309215976Sjmallett When enabled, this bit lets N3K be the default 3310215976Sjmallett driver for memory port \#0. 3311215976Sjmallett NOTE: For N3K-P1, to enable Port#0(2nd port), 3312215976Sjmallett Port#1 MUST ALSO be enabled. 3313215976Sjmallett NOTE: For N3K-P2, single port mode, a customer is at 3314215976Sjmallett liberty to enable either Port#0 or Port#1. 3315215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 3316215976Sjmallett be re-enabled. [the only way to enable a port is 3317215976Sjmallett through a chip reset]. 3318215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 3319215976Sjmallett RLD0_* pins. */ 3320215976Sjmallett uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1 3321215976Sjmallett When enabled, this bit lets N3K be the default 3322215976Sjmallett driver for memory port \#1. 3323215976Sjmallett NOTE: For N3K-P1, If the customer wishes to use a 3324215976Sjmallett single port, s/he must enable Port#1 (and not Port#0). 3325215976Sjmallett NOTE: For N3K-P2, single port mode, a customer is at 3326215976Sjmallett liberty to enable either Port#0 or Port#1. 3327215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 3328215976Sjmallett be re-enabled. [the only way to enable a port is 3329215976Sjmallett through a chip reset]. 3330215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 3331215976Sjmallett RLD1_* pins. */ 3332215976Sjmallett#else 3333215976Sjmallett uint64_t ena_p1 : 1; 3334215976Sjmallett uint64_t ena_p0 : 1; 3335215976Sjmallett uint64_t reserved_2_2 : 1; 3336215976Sjmallett uint64_t mtype : 1; 3337215976Sjmallett uint64_t sil_lat : 2; 3338215976Sjmallett uint64_t rw_dly : 4; 3339215976Sjmallett uint64_t wr_dly : 4; 3340215976Sjmallett uint64_t fprch : 2; 3341215976Sjmallett uint64_t bprch : 2; 3342215976Sjmallett uint64_t blen : 1; 3343215976Sjmallett uint64_t pbunk : 3; 3344215976Sjmallett uint64_t r2r_pbunk : 1; 3345215976Sjmallett uint64_t init_p1 : 1; 3346215976Sjmallett uint64_t init_p0 : 1; 3347215976Sjmallett uint64_t bunk_init : 2; 3348215976Sjmallett uint64_t lpp_ena : 1; 3349215976Sjmallett uint64_t reserved_28_63 : 36; 3350215976Sjmallett#endif 3351215976Sjmallett } cn38xx; 3352215976Sjmallett struct cvmx_dfa_memcfg0_cn38xxp2 3353215976Sjmallett { 3354215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3355215976Sjmallett uint64_t reserved_27_63 : 37; 3356215976Sjmallett uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization 3357215976Sjmallett sequence (triggered by DFA_MEMCFG0[INIT_Px]) or 3358215976Sjmallett b) during a normal refresh sequence. If 3359215976Sjmallett the BNK_INIT[x]=1, the corresponding CS_N[x] is driven. 3360215976Sjmallett NOTE: This is required for DRAM used in a 3361215976Sjmallett clamshell configuration, since the address lines 3362215976Sjmallett carry Mode Register write data that is unique 3363215976Sjmallett per bunk(or clam). In a clamshell configuration, 3364215976Sjmallett The N3K A[x] pin may be tied into Clam#0's A[x] 3365215976Sjmallett and also into Clam#1's 'mirrored' address bit A[y] 3366215976Sjmallett (eg: Clam0 sees A[5] and Clam1 sees A[15]). 3367215976Sjmallett To support clamshell designs, SW must initiate 3368215976Sjmallett two separate HW init sequences for the two bunks 3369215976Sjmallett (or clams) . Before each HW init sequence is triggered, 3370215976Sjmallett SW must preload the DFA_MEMRLD[22:0] with the data 3371215976Sjmallett that will be driven onto the A[22:0] wires during 3372215976Sjmallett an MRS mode register write. 3373215976Sjmallett NOTE: After the final HW initialization sequence has 3374215976Sjmallett been triggered, SW must wait 64K eclks before writing 3375215976Sjmallett the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is 3376215976Sjmallett driven during refresh sequences in normal operation. 3377215976Sjmallett NOTE: This should only be written to a different value 3378215976Sjmallett during power-on SW initialization. 3379215976Sjmallett NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE 3380215976Sjmallett initialized independently. In other words, a HW init 3381215976Sjmallett must be done for Bunk#0, and then another HW init 3382215976Sjmallett must be done for Bunk#1 at power-on. */ 3383215976Sjmallett uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'), 3384215976Sjmallett the HW init sequence(s) for Memory Port \#0 is 3385215976Sjmallett initiated. 3386215976Sjmallett NOTE: To initialize memory, SW must: 3387215976Sjmallett 1) Enable memory port(s): 3388215976Sjmallett a) ENA_P1=1 (single port in pass 1) OR 3389215976Sjmallett b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 3390215976Sjmallett 2) Wait 100us (to ensure a stable clock 3391215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 3392215976Sjmallett 3) Write a '1' to the corresponding INIT_Px which 3393215976Sjmallett will initiate a hardware initialization 3394215976Sjmallett sequence. 3395215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 3396215976Sjmallett cycles to ensure the HW init sequence has completed 3397215976Sjmallett before writing to ANY of the DFA_MEM* registers. 3398215976Sjmallett NOTE: This should only be written to a different value 3399215976Sjmallett during power-on SW initialization. 3400215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 3401215976Sjmallett RLD0_* pins. */ 3402215976Sjmallett uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'), 3403215976Sjmallett the HW init sequence(s) for Memory Port \#1 is 3404215976Sjmallett initiated. 3405215976Sjmallett NOTE: To initialize memory, SW must: 3406215976Sjmallett 1) Enable memory port(s): 3407215976Sjmallett a) ENA_P1=1 (single port in pass 1) OR 3408215976Sjmallett b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 3409215976Sjmallett 2) Wait 100us (to ensure a stable clock 3410215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 3411215976Sjmallett 3) Write a '1' to the corresponding INIT_Px which 3412215976Sjmallett will initiate a hardware initialization 3413215976Sjmallett sequence. 3414215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 3415215976Sjmallett cycles to ensure the HW init sequence has completed 3416215976Sjmallett before writing to ANY of the DFA_MEM* registers. 3417215976Sjmallett NOTE: This should only be written to a different value 3418215976Sjmallett during power-on SW initialization. 3419215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 3420215976Sjmallett RLD1_* pins. */ 3421215976Sjmallett uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted 3422215976Sjmallett if back to back reads are issued to different physical 3423215976Sjmallett bunks. This is to avoid DQ data bus collisions when 3424215976Sjmallett references cross between physical bunks. 3425215976Sjmallett [NOTE: the physical bunk address boundary is determined 3426215976Sjmallett by the PBUNK bit]. 3427215976Sjmallett NOTE: This should only be written to a different value 3428215976Sjmallett during power-on SW initialization. 3429215976Sjmallett When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE 3430215976Sjmallett ZERO(for optimal performance). However, if electrically, 3431215976Sjmallett DQ-sharing becomes a power/heat issue, then R2R_PBUNK 3432215976Sjmallett should be set (but at a cost to performance (1/2 BW). */ 3433215976Sjmallett uint64_t pbunk : 3; /**< Physical Bunk address bit pointer. 3434215976Sjmallett Specifies which address bit within the Longword 3435215976Sjmallett Memory address MA[23:0] is used to determine the 3436215976Sjmallett chip selects. 3437215976Sjmallett [RLD_CS0_N corresponds to physical bunk \#0, and 3438215976Sjmallett RLD_CS1_N corresponds to physical bunk \#1]. 3439215976Sjmallett - 000: CS0_N = MA[19]/CS1_N = !MA[19] 3440215976Sjmallett - 001: CS0_N = MA[20]/CS1_N = !MA[20] 3441215976Sjmallett - 010: CS0_N = MA[21]/CS1_N = !MA[21] 3442215976Sjmallett - 011: CS0_N = MA[22]/CS1_N = !MA[22] 3443215976Sjmallett - 100: CS0_N = MA[23]/CS1_N = !MA[23] 3444215976Sjmallett - 101-111: CS0_N = 0 /CS1_N = 1 3445215976Sjmallett Example(s): 3446215976Sjmallett To build out a 128MB DFA memory, 4x 32Mx9 3447215976Sjmallett parts could be used to fill out TWO physical 3448215976Sjmallett bunks (clamshell configuration). Each (of the 3449215976Sjmallett two) physical bunks contains 2x 32Mx9 = 16Mx36. 3450215976Sjmallett Each RLDRAM device also contains 8 internal banks, 3451215976Sjmallett therefore the memory Address is 16M/8banks = 2M 3452215976Sjmallett addresses/bunk (2^21). In this case, MA[21] would 3453215976Sjmallett select the physical bunk. 3454215976Sjmallett NOTE: This should only be written to a different value 3455215976Sjmallett during power-on SW initialization. 3456215976Sjmallett be used to determine the Chip Select(s). 3457215976Sjmallett NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a 3458215976Sjmallett "Redundant Bunk" scheme is employed to provide the 3459215976Sjmallett highest overall performance (1 Req/ MCLK cycle). 3460215976Sjmallett In this mode, it's imperative that SW set the PBUNK 3461215976Sjmallett field +1 'above' the highest address bit. (such that 3462215976Sjmallett the PBUNK extracted from the address will always be 3463215976Sjmallett zero). In this mode, the CS_N[1:0] pins are driven 3464215976Sjmallett to each redundant bunk based on a TDM scheme: 3465215976Sjmallett [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */ 3466215976Sjmallett uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst) 3467215976Sjmallett When BLEN=0(BL2), all QW reads/writes from CP2 are 3468215976Sjmallett decomposed into 2 separate BL2(LW) requests to the 3469215976Sjmallett Low-Latency memory. 3470215976Sjmallett When BLEN=1(BL4), a LW request (from CP2 or NCB) is 3471215976Sjmallett treated as 1 BL4(QW) request to the low latency memory. 3472215976Sjmallett NOTE: QW refers to a 64-bit LLM Load/Store (intiated 3473215976Sjmallett by a processor core). LW refers to a 36-bit load/store. 3474215976Sjmallett NOTE: This should only be written to a different value 3475215976Sjmallett during power-on SW initialization before the DFA LLM 3476215976Sjmallett (low latency memory) is used. 3477215976Sjmallett NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst) 3478215976Sjmallett NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a 3479215976Sjmallett multi-bunk(clam) board design. 3480215976Sjmallett NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4), 3481215976Sjmallett SW SHOULD use CP2 QW read/write requests (for 3482215976Sjmallett optimal low-latency bus performance). 3483215976Sjmallett [LW length read/write requests(in BL4 mode) use 50% 3484215976Sjmallett of the available bus bandwidth] 3485215976Sjmallett NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only 3486215976Sjmallett be used with FCRAM-II devices which support BL2 mode 3487215976Sjmallett (see: Toshiba FCRAM-II, where DQ tristate after 2 data 3488215976Sjmallett transfers). 3489215976Sjmallett NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW 3490215976Sjmallett write requests (FCRAM-II+ device specification has removed 3491215976Sjmallett the variable write mask function from the devices). 3492215976Sjmallett As such, if this mode is used, SW must be careful to 3493215976Sjmallett issue only PP-CP2 QW write requests. */ 3494215976Sjmallett uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks) 3495215976Sjmallett On reads, allows user to control the shape of the 3496215976Sjmallett tristate disable back porch for the DQ data bus. 3497215976Sjmallett This parameter is also very dependent on the 3498215976Sjmallett RW_DLY and WR_DLY parameters and care must be 3499215976Sjmallett taken when programming these parameters to avoid 3500215976Sjmallett data bus contention. Valid range [0..2] 3501215976Sjmallett NOTE: This should only be written to a different value 3502215976Sjmallett during power-on SW initialization. */ 3503215976Sjmallett uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks) 3504215976Sjmallett On reads, allows user to control the shape of the 3505215976Sjmallett tristate disable front porch for the DQ data bus. 3506215976Sjmallett This parameter is also very dependent on the 3507215976Sjmallett RW_DLY and WR_DLY parameters and care must be 3508215976Sjmallett taken when programming these parameters to avoid 3509215976Sjmallett data bus contention. Valid range [0..2] 3510215976Sjmallett NOTE: This should only be written to a different value 3511215976Sjmallett during power-on SW initialization. */ 3512215976Sjmallett uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks): 3513215976Sjmallett Determines \#mclk cycles to insert when controller 3514215976Sjmallett switches from write to read. This allows programmer 3515215976Sjmallett to control the data bus contention. 3516215976Sjmallett For RLDRAM-II(BL2): (TBL=1) 3517215976Sjmallett For FCRAM-II (BL4): (TBL=2) 3518215976Sjmallett For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1) 3519215976Sjmallett For FCRAM-II (BL2 grepl>=2x): (TBL=3) 3520215976Sjmallett NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode), 3521215976Sjmallett grepl>=2x, writes require redundant bunk writes 3522215976Sjmallett which require an additional 2 cycles before slotting 3523215976Sjmallett the next read. 3524215976Sjmallett WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1 3525215976Sjmallett NOTE: This should only be written to a different value 3526215976Sjmallett during power-on SW initialization. 3527215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3528215976Sjmallett the WR_DLY 'may' be tuned down(-1) if bus fight 3529215976Sjmallett on W->R transitions is not pronounced. */ 3530215976Sjmallett uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks): 3531215976Sjmallett Determines \#mclk cycles to insert when controller 3532215976Sjmallett switches from read to write. This allows programmer 3533215976Sjmallett to control the data bus contention. 3534215976Sjmallett For RLDRAM-II/FCRAM-II (BL2): (TBL=1) 3535215976Sjmallett For FCRAM-II (BL4): (TBL=2) 3536215976Sjmallett RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1 3537215976Sjmallett NOTE: This should only be written to a different value 3538215976Sjmallett during power-on SW initialization. 3539215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3540215976Sjmallett the RW_DLY 'may' be tuned down(-1) if bus fight 3541215976Sjmallett on R->W transitions is not pronounced. */ 3542215976Sjmallett uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many 3543215976Sjmallett additional dclks to wait (on top of tRL+1) before 3544215976Sjmallett pulling data out of the padring silos used for time 3545215976Sjmallett domain boundary crossing. 3546215976Sjmallett NOTE: This should only be written to a different value 3547215976Sjmallett during power-on SW initialization. */ 3548215976Sjmallett uint64_t mtype : 1; /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM) 3549215976Sjmallett NOTE: N3K-P1 only supports RLDRAM-II 3550215976Sjmallett NOTE: This should only be written to a different value 3551215976Sjmallett during power-on SW initialization. 3552215976Sjmallett NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the 3553215976Sjmallett "unidirectional DS/QS" mode is supported. (see FCRAM 3554215976Sjmallett data sheet EMRS[A6:A5]=SS(Strobe Select) register 3555215976Sjmallett definition. [in FCRAM 2-burst mode, we use FCRAM 3556215976Sjmallett in a clamshell configuration such that clam0 is 3557215976Sjmallett addressed independently of clam1, and DQ is shared 3558215976Sjmallett for optimal performance. As such it's imperative that 3559215976Sjmallett the QS are conditionally received (and are NOT 3560215976Sjmallett free-running), as the N3K receive data capture silos 3561215976Sjmallett OR the clam0/1 QS strobes. 3562215976Sjmallett NOTE: If this bit is SET, the ASX0/1 3563215976Sjmallett ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET 3564215976Sjmallett in order for the RLD0/1-PHY(s) to support FCRAM devices. */ 3565215976Sjmallett uint64_t reserved_2_2 : 1; 3566215976Sjmallett uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0 3567215976Sjmallett When enabled, this bit lets N3K be the default 3568215976Sjmallett driver for memory port \#0. 3569215976Sjmallett NOTE: For N3K-P1, to enable Port#0(2nd port), 3570215976Sjmallett Port#1 MUST ALSO be enabled. 3571215976Sjmallett NOTE: For N3K-P2, single port mode, a customer is at 3572215976Sjmallett liberty to enable either Port#0 or Port#1. 3573215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 3574215976Sjmallett be re-enabled. [the only way to enable a port is 3575215976Sjmallett through a chip reset]. 3576215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 3577215976Sjmallett RLD0_* pins. */ 3578215976Sjmallett uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1 3579215976Sjmallett When enabled, this bit lets N3K be the default 3580215976Sjmallett driver for memory port \#1. 3581215976Sjmallett NOTE: For N3K-P1, If the customer wishes to use a 3582215976Sjmallett single port, s/he must enable Port#1 (and not Port#0). 3583215976Sjmallett NOTE: For N3K-P2, single port mode, a customer is at 3584215976Sjmallett liberty to enable either Port#0 or Port#1. 3585215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 3586215976Sjmallett be re-enabled. [the only way to enable a port is 3587215976Sjmallett through a chip reset]. 3588215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 3589215976Sjmallett RLD1_* pins. */ 3590215976Sjmallett#else 3591215976Sjmallett uint64_t ena_p1 : 1; 3592215976Sjmallett uint64_t ena_p0 : 1; 3593215976Sjmallett uint64_t reserved_2_2 : 1; 3594215976Sjmallett uint64_t mtype : 1; 3595215976Sjmallett uint64_t sil_lat : 2; 3596215976Sjmallett uint64_t rw_dly : 4; 3597215976Sjmallett uint64_t wr_dly : 4; 3598215976Sjmallett uint64_t fprch : 2; 3599215976Sjmallett uint64_t bprch : 2; 3600215976Sjmallett uint64_t blen : 1; 3601215976Sjmallett uint64_t pbunk : 3; 3602215976Sjmallett uint64_t r2r_pbunk : 1; 3603215976Sjmallett uint64_t init_p1 : 1; 3604215976Sjmallett uint64_t init_p0 : 1; 3605215976Sjmallett uint64_t bunk_init : 2; 3606215976Sjmallett uint64_t reserved_27_63 : 37; 3607215976Sjmallett#endif 3608215976Sjmallett } cn38xxp2; 3609215976Sjmallett struct cvmx_dfa_memcfg0_s cn58xx; 3610215976Sjmallett struct cvmx_dfa_memcfg0_s cn58xxp1; 3611215976Sjmallett}; 3612215976Sjmalletttypedef union cvmx_dfa_memcfg0 cvmx_dfa_memcfg0_t; 3613215976Sjmallett 3614215976Sjmallett/** 3615215976Sjmallett * cvmx_dfa_memcfg1 3616215976Sjmallett * 3617215976Sjmallett * DFA_MEMCFG1 = RLDRAM Memory Timing Configuration 3618215976Sjmallett * 3619215976Sjmallett * Description: 3620215976Sjmallett */ 3621215976Sjmallettunion cvmx_dfa_memcfg1 3622215976Sjmallett{ 3623215976Sjmallett uint64_t u64; 3624215976Sjmallett struct cvmx_dfa_memcfg1_s 3625215976Sjmallett { 3626215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3627215976Sjmallett uint64_t reserved_34_63 : 30; 3628215976Sjmallett uint64_t ref_intlo : 9; /**< Burst Refresh Interval[8:0] (\#dclks) 3629215976Sjmallett For finer refresh interval granularity control. 3630215976Sjmallett This field provides an additional level of granularity 3631215976Sjmallett for the refresh interval. It specifies the additional 3632215976Sjmallett \#dclks [0...511] to be added to the REF_INT[3:0] field. 3633215976Sjmallett For RLDRAM-II: For dclk(400MHz=2.5ns): 3634215976Sjmallett Example: 64K AREF cycles required within tREF=32ms 3635215976Sjmallett trefint = tREF(ms)/(64K cycles/8banks) 3636215976Sjmallett = 32ms/8K = 3.9us = 3900ns 3637215976Sjmallett REF_INT[3:0] = ROUND_DOWN[(trefint/dclk)/512] 3638215976Sjmallett = ROUND_DOWN[(3900/2.5)/512] 3639215976Sjmallett = 3 3640215976Sjmallett REF_INTLO[8:0] = MOD[(trefint/dclk)/512] 3641215976Sjmallett = MOD[(3900/2.5)/512] 3642215976Sjmallett = 24 3643215976Sjmallett NOTE: This should only be written to a different value 3644215976Sjmallett during power-on SW initialization. */ 3645215976Sjmallett uint64_t aref_ena : 1; /**< Auto Refresh Cycle Enable 3646215976Sjmallett INTERNAL USE ONLY: 3647215976Sjmallett NOTE: This mode bit is ONLY intended to be used by 3648215976Sjmallett low-level power-on initialization routines in the 3649215976Sjmallett event that the hardware initialization routine 3650215976Sjmallett does not work. It allows SW to create AREF 3651215976Sjmallett commands on the RLDRAM bus directly. 3652215976Sjmallett When this bit is set, ALL RLDRAM writes (issued by 3653215976Sjmallett a PP through the NCB or CP2) are converted to AREF 3654215976Sjmallett commands on the RLDRAM bus. The write-address is 3655215976Sjmallett presented on the A[20:0]/BA[2:0] pins (for which 3656215976Sjmallett the RLDRAM only interprets BA[2:0]). 3657215976Sjmallett When this bit is set, only writes are allowed 3658215976Sjmallett and MUST use grepl=0 (1x). 3659215976Sjmallett NOTE: This should only be written to a different value 3660215976Sjmallett during power-on SW initialization. 3661215976Sjmallett NOTE: MRS_ENA and AREF_ENA are mutually exclusive 3662215976Sjmallett (SW can set one or the other, but never both!) 3663215976Sjmallett NOTE: AREF commands generated using this method target 3664215976Sjmallett the 'addressed' bunk. */ 3665215976Sjmallett uint64_t mrs_ena : 1; /**< Mode Register Set Cycle Enable 3666215976Sjmallett INTERNAL USE ONLY: 3667215976Sjmallett NOTE: This mode bit is ONLY intended to be used by 3668215976Sjmallett low-level power-on initialization routines in the 3669215976Sjmallett event that the hardware initialization routine 3670215976Sjmallett does not work. It allows SW to create MRS 3671215976Sjmallett commands on the RLDRAM bus directly. 3672215976Sjmallett When this bit is set, ALL RLDRAM writes (issued by 3673215976Sjmallett a PP through the NCB or CP2) are converted to MRS 3674215976Sjmallett commands on the RLDRAM bus. The write-address is 3675215976Sjmallett presented on the A[20:0]/BA[2:0] pins (for which 3676215976Sjmallett the RLDRAM only interprets A[17:0]). 3677215976Sjmallett When this bit is set, only writes are allowed 3678215976Sjmallett and MUST use grepl=0 (1x). 3679215976Sjmallett NOTE: This should only be written to a different value 3680215976Sjmallett during power-on SW initialization. 3681215976Sjmallett NOTE: MRS_ENA and AREF_ENA are mutually exclusive 3682215976Sjmallett (SW can set one or the other, but never both!) 3683215976Sjmallett NOTE: MRS commands generated using this method target 3684215976Sjmallett the 'addressed' bunk. */ 3685215976Sjmallett uint64_t tmrsc : 3; /**< Mode Register Set Cycle Time (represented in \#mclks) 3686215976Sjmallett - 000-001: RESERVED 3687215976Sjmallett - 010: tMRSC = 2 mclks 3688215976Sjmallett - 011: tMRSC = 3 mclks 3689215976Sjmallett - ... 3690215976Sjmallett - 111: tMRSC = 7 mclks 3691215976Sjmallett NOTE: The device tMRSC parameter is a function of CL 3692215976Sjmallett (which during HW initialization is not known. Its 3693215976Sjmallett recommended to load tMRSC(MAX) value to avoid timing 3694215976Sjmallett violations. 3695215976Sjmallett NOTE: This should only be written to a different value 3696215976Sjmallett during power-on SW initialization. */ 3697215976Sjmallett uint64_t trc : 4; /**< Row Cycle Time (represented in \#mclks) 3698215976Sjmallett see also: DFA_MEMRLD[RLCFG] field which must 3699215976Sjmallett correspond with tRL/tWL parameter(s). 3700215976Sjmallett - 0000-0010: RESERVED 3701215976Sjmallett - 0011: tRC = 3 mclks 3702215976Sjmallett - 0100: tRC = 4 mclks 3703215976Sjmallett - 0101: tRC = 5 mclks 3704215976Sjmallett - 0110: tRC = 6 mclks 3705215976Sjmallett - 0111: tRC = 7 mclks 3706215976Sjmallett - 1000: tRC = 8 mclks 3707215976Sjmallett - 1001: tRC = 9 mclks 3708215976Sjmallett - 1010-1111: RESERVED 3709215976Sjmallett NOTE: This should only be written to a different value 3710215976Sjmallett during power-on SW initialization. */ 3711215976Sjmallett uint64_t twl : 4; /**< Write Latency (represented in \#mclks) 3712215976Sjmallett see also: DFA_MEMRLD[RLCFG] field which must 3713215976Sjmallett correspond with tRL/tWL parameter(s). 3714215976Sjmallett - 0000-0001: RESERVED 3715215976Sjmallett - 0010: Write Latency (WL=2.0 mclk) 3716215976Sjmallett - 0011: Write Latency (WL=3.0 mclks) 3717215976Sjmallett - 0100: Write Latency (WL=4.0 mclks) 3718215976Sjmallett - 0101: Write Latency (WL=5.0 mclks) 3719215976Sjmallett - 0110: Write Latency (WL=6.0 mclks) 3720215976Sjmallett - 0111: Write Latency (WL=7.0 mclks) 3721215976Sjmallett - 1000: Write Latency (WL=8.0 mclks) 3722215976Sjmallett - 1001: Write Latency (WL=9.0 mclks) 3723215976Sjmallett - 1010: Write Latency (WL=10.0 mclks) 3724215976Sjmallett - 1011-1111: RESERVED 3725215976Sjmallett NOTE: This should only be written to a different value 3726215976Sjmallett during power-on SW initialization. */ 3727215976Sjmallett uint64_t trl : 4; /**< Read Latency (represented in \#mclks) 3728215976Sjmallett see also: DFA_MEMRLD[RLCFG] field which must 3729215976Sjmallett correspond with tRL/tWL parameter(s). 3730215976Sjmallett - 0000-0010: RESERVED 3731215976Sjmallett - 0011: Read Latency = 3 mclks 3732215976Sjmallett - 0100: Read Latency = 4 mclks 3733215976Sjmallett - 0101: Read Latency = 5 mclks 3734215976Sjmallett - 0110: Read Latency = 6 mclks 3735215976Sjmallett - 0111: Read Latency = 7 mclks 3736215976Sjmallett - 1000: Read Latency = 8 mclks 3737215976Sjmallett - 1001: Read Latency = 9 mclks 3738215976Sjmallett - 1010: Read Latency = 10 mclks 3739215976Sjmallett - 1011-1111: RESERVED 3740215976Sjmallett NOTE: This should only be written to a different value 3741215976Sjmallett during power-on SW initialization. */ 3742215976Sjmallett uint64_t reserved_6_7 : 2; 3743215976Sjmallett uint64_t tskw : 2; /**< Board Skew (represented in \#dclks) 3744215976Sjmallett Represents additional board skew of DQ/DQS. 3745215976Sjmallett - 00: board-skew = 0 dclk 3746215976Sjmallett - 01: board-skew = 1 dclk 3747215976Sjmallett - 10: board-skew = 2 dclk 3748215976Sjmallett - 11: board-skew = 3 dclk 3749215976Sjmallett NOTE: This should only be written to a different value 3750215976Sjmallett during power-on SW initialization. */ 3751215976Sjmallett uint64_t ref_int : 4; /**< Refresh Interval (represented in \#of 512 dclk 3752215976Sjmallett increments). 3753215976Sjmallett - 0000: RESERVED 3754215976Sjmallett - 0001: 1 * 512 = 512 dclks 3755215976Sjmallett - ... 3756215976Sjmallett - 1111: 15 * 512 = 7680 dclks 3757215976Sjmallett NOTE: For finer level of granularity, refer to 3758215976Sjmallett REF_INTLO[8:0] field. 3759215976Sjmallett For RLDRAM-II, each refresh interval will 3760215976Sjmallett generate a burst of 8 AREF commands, one to each of 3761215976Sjmallett 8 explicit banks (referenced using the RLD_BA[2:0] 3762215976Sjmallett pins. 3763215976Sjmallett Example: For mclk=200MHz/dclk(400MHz=2.5ns): 3764215976Sjmallett 64K AREF cycles required within tREF=32ms 3765215976Sjmallett trefint = tREF(ms)/(64K cycles/8banks) 3766215976Sjmallett = 32ms/8K = 3.9us = 3900ns 3767215976Sjmallett REF_INT = ROUND_DOWN[(trefint/dclk)/512] 3768215976Sjmallett = ROUND_DOWN[(3900/2.5)/512] 3769215976Sjmallett = 3 3770215976Sjmallett NOTE: This should only be written to a different value 3771215976Sjmallett during power-on SW initialization. */ 3772215976Sjmallett#else 3773215976Sjmallett uint64_t ref_int : 4; 3774215976Sjmallett uint64_t tskw : 2; 3775215976Sjmallett uint64_t reserved_6_7 : 2; 3776215976Sjmallett uint64_t trl : 4; 3777215976Sjmallett uint64_t twl : 4; 3778215976Sjmallett uint64_t trc : 4; 3779215976Sjmallett uint64_t tmrsc : 3; 3780215976Sjmallett uint64_t mrs_ena : 1; 3781215976Sjmallett uint64_t aref_ena : 1; 3782215976Sjmallett uint64_t ref_intlo : 9; 3783215976Sjmallett uint64_t reserved_34_63 : 30; 3784215976Sjmallett#endif 3785215976Sjmallett } s; 3786215976Sjmallett struct cvmx_dfa_memcfg1_s cn38xx; 3787215976Sjmallett struct cvmx_dfa_memcfg1_s cn38xxp2; 3788215976Sjmallett struct cvmx_dfa_memcfg1_s cn58xx; 3789215976Sjmallett struct cvmx_dfa_memcfg1_s cn58xxp1; 3790215976Sjmallett}; 3791215976Sjmalletttypedef union cvmx_dfa_memcfg1 cvmx_dfa_memcfg1_t; 3792215976Sjmallett 3793215976Sjmallett/** 3794215976Sjmallett * cvmx_dfa_memcfg2 3795215976Sjmallett * 3796215976Sjmallett * DFA_MEMCFG2 = DFA Memory Config Register \#2 3797215976Sjmallett * *** NOTE: Pass2 Addition 3798215976Sjmallett * 3799215976Sjmallett * Description: Additional Memory Configuration CSRs to support FCRAM-II/II+ and Network DRAM-II 3800215976Sjmallett */ 3801215976Sjmallettunion cvmx_dfa_memcfg2 3802215976Sjmallett{ 3803215976Sjmallett uint64_t u64; 3804215976Sjmallett struct cvmx_dfa_memcfg2_s 3805215976Sjmallett { 3806215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3807215976Sjmallett uint64_t reserved_12_63 : 52; 3808215976Sjmallett uint64_t dteclkdis : 1; /**< DFA DTE Clock Disable 3809215976Sjmallett When SET, the DFA clocks for DTE(thread engine) 3810215976Sjmallett operation are disabled. 3811215976Sjmallett NOTE: When SET, SW MUST NEVER issue ANY operations to 3812215976Sjmallett the DFA via the NCB Bus. All DFA Operations must be 3813215976Sjmallett issued solely through the CP2 interface. 3814215976Sjmallett 3815215976Sjmallett NOTE: When DTECLKDIS=1, if CP2 Errors are encountered 3816215976Sjmallett (ie: CP2SBE, CP2DBE, CP2PERR), the DFA_MEMFADR CSR 3817215976Sjmallett does not reflect the failing address/ctl information. */ 3818215976Sjmallett uint64_t silrst : 1; /**< LLM-PHY Silo Reset 3819215976Sjmallett When a '1' is written (when the previous 3820215976Sjmallett value was a '0') causes the the LLM-PHY Silo read/write 3821215976Sjmallett pointers to be reset. 3822215976Sjmallett NOTE: SW MUST WAIT 400 dclks after the LAST HW Init 3823215976Sjmallett sequence was launched (ie: INIT_START 0->1 CSR write), 3824215976Sjmallett before the SILRST can be triggered (0->1). */ 3825215976Sjmallett uint64_t trfc : 5; /**< FCRAM-II Refresh Interval 3826215976Sjmallett *** CN58XX UNSUPPORTED *** */ 3827215976Sjmallett uint64_t refshort : 1; /**< FCRAM Short Refresh Mode 3828215976Sjmallett *** CN58XX UNSUPPORTED *** */ 3829215976Sjmallett uint64_t ua_start : 2; /**< FCRAM-II Upper Addres Start 3830215976Sjmallett *** CN58XX UNSUPPORTED *** */ 3831215976Sjmallett uint64_t maxbnk : 1; /**< Maximum Banks per-device (used by the address mapper 3832215976Sjmallett when extracting address bits for the memory bank#. 3833215976Sjmallett - 0: 4 banks/device 3834215976Sjmallett - 1: 8 banks/device */ 3835215976Sjmallett uint64_t fcram2p : 1; /**< FCRAM-II+ Mode Enable 3836215976Sjmallett *** CN58XX UNSUPPORTED *** */ 3837215976Sjmallett#else 3838215976Sjmallett uint64_t fcram2p : 1; 3839215976Sjmallett uint64_t maxbnk : 1; 3840215976Sjmallett uint64_t ua_start : 2; 3841215976Sjmallett uint64_t refshort : 1; 3842215976Sjmallett uint64_t trfc : 5; 3843215976Sjmallett uint64_t silrst : 1; 3844215976Sjmallett uint64_t dteclkdis : 1; 3845215976Sjmallett uint64_t reserved_12_63 : 52; 3846215976Sjmallett#endif 3847215976Sjmallett } s; 3848215976Sjmallett struct cvmx_dfa_memcfg2_s cn38xx; 3849215976Sjmallett struct cvmx_dfa_memcfg2_s cn38xxp2; 3850215976Sjmallett struct cvmx_dfa_memcfg2_s cn58xx; 3851215976Sjmallett struct cvmx_dfa_memcfg2_s cn58xxp1; 3852215976Sjmallett}; 3853215976Sjmalletttypedef union cvmx_dfa_memcfg2 cvmx_dfa_memcfg2_t; 3854215976Sjmallett 3855215976Sjmallett/** 3856215976Sjmallett * cvmx_dfa_memfadr 3857215976Sjmallett * 3858215976Sjmallett * DFA_MEMFADR = RLDRAM Failing Address/Control Register 3859215976Sjmallett * 3860215976Sjmallett * Description: DFA Memory Failing Address/Control Error Capture information 3861215976Sjmallett * This register contains useful information to help in isolating an RLDRAM memory failure. 3862215976Sjmallett * NOTE: The first detected SEC/DED/PERR failure is captured in DFA_MEMFADR, however, a DED or PERR (which is 3863215976Sjmallett * more severe) will always overwrite a SEC error. The user can 'infer' the source of the interrupt 3864215976Sjmallett * via the FSRC field. 3865215976Sjmallett * NOTE: If DFA_MEMCFG2[DTECLKDIS]=1, the contents of this register are UNDEFINED. 3866215976Sjmallett */ 3867215976Sjmallettunion cvmx_dfa_memfadr 3868215976Sjmallett{ 3869215976Sjmallett uint64_t u64; 3870215976Sjmallett struct cvmx_dfa_memfadr_s 3871215976Sjmallett { 3872215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3873215976Sjmallett uint64_t reserved_24_63 : 40; 3874215976Sjmallett uint64_t maddr : 24; /**< Memory Address */ 3875215976Sjmallett#else 3876215976Sjmallett uint64_t maddr : 24; 3877215976Sjmallett uint64_t reserved_24_63 : 40; 3878215976Sjmallett#endif 3879215976Sjmallett } s; 3880215976Sjmallett struct cvmx_dfa_memfadr_cn31xx 3881215976Sjmallett { 3882215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3883215976Sjmallett uint64_t reserved_40_63 : 24; 3884215976Sjmallett uint64_t fdst : 9; /**< Fill-Destination 3885215976Sjmallett FSRC[1:0] | FDST[8:0] 3886215976Sjmallett -------------+------------------------------------- 3887215976Sjmallett 0(NCB-DTE) | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)] 3888215976Sjmallett 1(NCB-CSR) | [ncbSRC[8:0]] 3889215976Sjmallett 3(CP2-PP) | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)] 3890215976Sjmallett where: 3891215976Sjmallett DTE: DFA Thread Engine ID# 3892215976Sjmallett PP: Packet Processor ID# 3893215976Sjmallett FID: Fill-ID# (unique per PP) 3894215976Sjmallett WIDX: 16b SIMPLE Mode (index) 3895215976Sjmallett DMODE: (0=16b SIMPLE/1=32b SIMPLE) 3896215976Sjmallett SIZE: (0=LW Mode access/1=QW Mode Access) 3897215976Sjmallett INDEX: (0=Low LW/1=High LW) 3898215976Sjmallett NOTE: QW refers to a 56/64-bit LLM Load/Store (intiated 3899215976Sjmallett by a processor core). LW refers to a 32-bit load/store. */ 3900215976Sjmallett uint64_t fsrc : 2; /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */ 3901215976Sjmallett uint64_t pnum : 1; /**< Memory Port 3902215976Sjmallett NOTE: For O2P, this bit will always return zero. */ 3903215976Sjmallett uint64_t bnum : 3; /**< Memory Bank 3904215976Sjmallett When DFA_DDR2_ADDR[RNK_LO]=1, BNUM[2]=RANK[0]. 3905215976Sjmallett (RANK[1] can be inferred from MADDR[24:0]) */ 3906215976Sjmallett uint64_t maddr : 25; /**< Memory Address */ 3907215976Sjmallett#else 3908215976Sjmallett uint64_t maddr : 25; 3909215976Sjmallett uint64_t bnum : 3; 3910215976Sjmallett uint64_t pnum : 1; 3911215976Sjmallett uint64_t fsrc : 2; 3912215976Sjmallett uint64_t fdst : 9; 3913215976Sjmallett uint64_t reserved_40_63 : 24; 3914215976Sjmallett#endif 3915215976Sjmallett } cn31xx; 3916215976Sjmallett struct cvmx_dfa_memfadr_cn38xx 3917215976Sjmallett { 3918215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3919215976Sjmallett uint64_t reserved_39_63 : 25; 3920215976Sjmallett uint64_t fdst : 9; /**< Fill-Destination 3921215976Sjmallett FSRC[1:0] | FDST[8:0] 3922215976Sjmallett -------------+------------------------------------- 3923215976Sjmallett 0(NCB-DTE) | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)] 3924215976Sjmallett 1(NCB-CSR) | [ncbSRC[8:0]] 3925215976Sjmallett 3(CP2-PP) | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)] 3926215976Sjmallett where: 3927215976Sjmallett DTE: DFA Thread Engine ID# 3928215976Sjmallett PP: Packet Processor ID# 3929215976Sjmallett FID: Fill-ID# (unique per PP) 3930215976Sjmallett WIDX: 18b SIMPLE Mode (index) 3931215976Sjmallett DMODE: (0=18b SIMPLE/1=36b SIMPLE) 3932215976Sjmallett SIZE: (0=LW Mode access/1=QW Mode Access) 3933215976Sjmallett INDEX: (0=Low LW/1=High LW) 3934215976Sjmallett NOTE: QW refers to a 64-bit LLM Load/Store (intiated 3935215976Sjmallett by a processor core). LW refers to a 36-bit load/store. */ 3936215976Sjmallett uint64_t fsrc : 2; /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */ 3937215976Sjmallett uint64_t pnum : 1; /**< Memory Port 3938215976Sjmallett NOTE: the port id's are reversed 3939215976Sjmallett PNUM==0 => port#1 3940215976Sjmallett PNUM==1 => port#0 */ 3941215976Sjmallett uint64_t bnum : 3; /**< Memory Bank */ 3942215976Sjmallett uint64_t maddr : 24; /**< Memory Address */ 3943215976Sjmallett#else 3944215976Sjmallett uint64_t maddr : 24; 3945215976Sjmallett uint64_t bnum : 3; 3946215976Sjmallett uint64_t pnum : 1; 3947215976Sjmallett uint64_t fsrc : 2; 3948215976Sjmallett uint64_t fdst : 9; 3949215976Sjmallett uint64_t reserved_39_63 : 25; 3950215976Sjmallett#endif 3951215976Sjmallett } cn38xx; 3952215976Sjmallett struct cvmx_dfa_memfadr_cn38xx cn38xxp2; 3953215976Sjmallett struct cvmx_dfa_memfadr_cn38xx cn58xx; 3954215976Sjmallett struct cvmx_dfa_memfadr_cn38xx cn58xxp1; 3955215976Sjmallett}; 3956215976Sjmalletttypedef union cvmx_dfa_memfadr cvmx_dfa_memfadr_t; 3957215976Sjmallett 3958215976Sjmallett/** 3959215976Sjmallett * cvmx_dfa_memfcr 3960215976Sjmallett * 3961215976Sjmallett * DFA_MEMFCR = FCRAM MRS Register(s) EMRS2[14:0], EMRS1[14:0], MRS[14:0] 3962215976Sjmallett * *** CN58XX UNSUPPORTED *** 3963215976Sjmallett * 3964215976Sjmallett * Notes: 3965215976Sjmallett * For FCRAM-II please consult your device's data sheet for further details: 3966215976Sjmallett * MRS Definition: 3967215976Sjmallett * A[13:8]=0 RESERVED 3968215976Sjmallett * A[7]=0 TEST MODE (N3K requires test mode 0:"disabled") 3969215976Sjmallett * A[6:4] CAS LATENCY (fully programmable - SW must ensure that the value programmed 3970215976Sjmallett * into DFA_MEM_CFG0[TRL] corresponds with this value). 3971215976Sjmallett * A[3]=0 BURST TYPE (N3K requires 0:"Sequential" Burst Type) 3972215976Sjmallett * A[2:0] BURST LENGTH Burst Length [1:BL2/2:BL4] (N3K only supports BL=2,4) 3973215976Sjmallett * 3974215976Sjmallett * In BL2 mode(for highest performance), only 1/2 the phsyical 3975215976Sjmallett * memory is unique (ie: each bunk stores the same information). 3976215976Sjmallett * In BL4 mode(highest capacity), all of the physical memory 3977215976Sjmallett * is unique (ie: each bunk is uniquely addressable). 3978215976Sjmallett * EMRS Definition: 3979215976Sjmallett * A[13:12] REFRESH MODE (N3K Supports only 0:"Conventional" and 1:"Short" auto-refresh modes) 3980215976Sjmallett * 3981215976Sjmallett * (SW must ensure that the value programmed into DFA_MEMCFG2[REFSHORT] 3982215976Sjmallett * is also reflected in the Refresh Mode encoding). 3983215976Sjmallett * A[11:7]=0 RESERVED 3984215976Sjmallett * A[6:5]=2 STROBE SELECT (N3K supports only 2:"Unidirectional DS/QS" mode - the read capture 3985215976Sjmallett * silos rely on a conditional QS strobe) 3986215976Sjmallett * A[4:3] DIC(QS) QS Drive Strength: fully programmable (consult your FCRAM-II data sheet) 3987215976Sjmallett * [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive] 3988215976Sjmallett * A[2:1] DIC(DQ) DQ Drive Strength: fully programmable (consult your FCRAM-II data sheet) 3989215976Sjmallett * [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive] 3990215976Sjmallett * A[0] DLL DLL Enable: Programmable [0:DLL Enable/1: DLL Disable] 3991215976Sjmallett * 3992215976Sjmallett * EMRS2 Definition: (for FCRAM-II+) 3993215976Sjmallett * A[13:11]=0 RESERVED 3994215976Sjmallett * A[10:8] ODTDS On Die Termination (DS+/-) 3995215976Sjmallett * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED] 3996215976Sjmallett * A[7:6]=0 MBW Multi-Bank Write: (N3K requires use of 0:"single bank" mode only) 3997215976Sjmallett * A[5:3] ODTin On Die Termination (input pin) 3998215976Sjmallett * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED] 3999215976Sjmallett * A[2:0] ODTDQ On Die Termination (DQ) 4000215976Sjmallett * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED] 4001215976Sjmallett */ 4002215976Sjmallettunion cvmx_dfa_memfcr 4003215976Sjmallett{ 4004215976Sjmallett uint64_t u64; 4005215976Sjmallett struct cvmx_dfa_memfcr_s 4006215976Sjmallett { 4007215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4008215976Sjmallett uint64_t reserved_47_63 : 17; 4009215976Sjmallett uint64_t emrs2 : 15; /**< Memory Address[14:0] during EMRS2(for FCRAM-II+) 4010215976Sjmallett *** CN58XX UNSUPPORTED *** */ 4011215976Sjmallett uint64_t reserved_31_31 : 1; 4012215976Sjmallett uint64_t emrs : 15; /**< Memory Address[14:0] during EMRS 4013215976Sjmallett *** CN58XX UNSUPPORTED *** 4014215976Sjmallett A[0]=1: DLL Enabled) */ 4015215976Sjmallett uint64_t reserved_15_15 : 1; 4016215976Sjmallett uint64_t mrs : 15; /**< FCRAM Memory Address[14:0] during MRS 4017215976Sjmallett *** CN58XX UNSUPPORTED *** 4018215976Sjmallett A[6:4]=4 CAS LATENCY=4(default) 4019215976Sjmallett A[3]=0 Burst Type(must be 0:Sequential) 4020215976Sjmallett A[2:0]=2 Burst Length=4(default) */ 4021215976Sjmallett#else 4022215976Sjmallett uint64_t mrs : 15; 4023215976Sjmallett uint64_t reserved_15_15 : 1; 4024215976Sjmallett uint64_t emrs : 15; 4025215976Sjmallett uint64_t reserved_31_31 : 1; 4026215976Sjmallett uint64_t emrs2 : 15; 4027215976Sjmallett uint64_t reserved_47_63 : 17; 4028215976Sjmallett#endif 4029215976Sjmallett } s; 4030215976Sjmallett struct cvmx_dfa_memfcr_s cn38xx; 4031215976Sjmallett struct cvmx_dfa_memfcr_s cn38xxp2; 4032215976Sjmallett struct cvmx_dfa_memfcr_s cn58xx; 4033215976Sjmallett struct cvmx_dfa_memfcr_s cn58xxp1; 4034215976Sjmallett}; 4035215976Sjmalletttypedef union cvmx_dfa_memfcr cvmx_dfa_memfcr_t; 4036215976Sjmallett 4037215976Sjmallett/** 4038215976Sjmallett * cvmx_dfa_memhidat 4039215976Sjmallett * 4040215976Sjmallett * DFA_MEMHIDAT = DFA NCB-Direct CSR access to DFM Memory Space (High QW) 4041215976Sjmallett * 4042215976Sjmallett * Description: 4043215976Sjmallett * DFA supports NCB-Direct CSR acccesses to DFM Memory space for debug purposes. Unfortunately, NCB-Direct accesses 4044215976Sjmallett * are limited to QW-size(64bits), whereas the minimum access granularity for DFM Memory space is OW(128bits). To 4045215976Sjmallett * support writes to DFM Memory space, the Hi-QW of data is sourced from the DFA_MEMHIDAT register. Recall, the 4046215976Sjmallett * OW(128b) in DDR3 memory space is fixed format: 4047215976Sjmallett * OWDATA[127:118]: OWECC[9:0] 10bits of in-band OWECC SEC/DED codeword 4048215976Sjmallett * This can be precomputed/written by SW OR 4049215976Sjmallett * if DFM_FNTCTL[ECC_WENA]=1, DFM hardware will auto-compute the 10b OWECC and place in the 4050215976Sjmallett * OWDATA[127:118] before being written to memory. 4051215976Sjmallett * OWDATA[117:0]: Memory Data (contains fixed MNODE/MONODE arc formats for use by DTEs(thread engines). 4052215976Sjmallett * Or, a user may choose to treat DFM Memory Space as 'scratch pad' in which case the 4053215976Sjmallett * OWDATA[117:0] may contain user-specified information accessible via NCB-Direct CSR mode 4054215976Sjmallett * accesses to DFA Memory Space. 4055215976Sjmallett * NOTE: To write to the DFA_MEMHIDAT register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b111. 4056215976Sjmallett * To read the DFA_MEMHIDAT register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b111. 4057215976Sjmallett * 4058215976Sjmallett * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_MEMHIDAT register do not take effect. 4059215976Sjmallett * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_MEMHIDAT register do not take effect. 4060215976Sjmallett */ 4061215976Sjmallettunion cvmx_dfa_memhidat 4062215976Sjmallett{ 4063215976Sjmallett uint64_t u64; 4064215976Sjmallett struct cvmx_dfa_memhidat_s 4065215976Sjmallett { 4066215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4067215976Sjmallett uint64_t hidat : 64; /**< DFA Hi-QW of Write data during NCB-Direct DFM DDR3 4068215976Sjmallett Memory accesses. 4069215976Sjmallett All DFM DDR3 memory accesses are OW(128b) references, 4070215976Sjmallett and since NCB-Direct Mode writes only support QW(64b), 4071215976Sjmallett the Hi QW of data must be sourced from a CSR register. 4072215976Sjmallett NOTE: This single register is 'shared' for ALL DFM 4073215976Sjmallett DDR3 Memory writes. */ 4074215976Sjmallett#else 4075215976Sjmallett uint64_t hidat : 64; 4076215976Sjmallett#endif 4077215976Sjmallett } s; 4078215976Sjmallett struct cvmx_dfa_memhidat_s cn63xx; 4079215976Sjmallett struct cvmx_dfa_memhidat_s cn63xxp1; 4080215976Sjmallett}; 4081215976Sjmalletttypedef union cvmx_dfa_memhidat cvmx_dfa_memhidat_t; 4082215976Sjmallett 4083215976Sjmallett/** 4084215976Sjmallett * cvmx_dfa_memrld 4085215976Sjmallett * 4086215976Sjmallett * DFA_MEMRLD = DFA RLDRAM MRS Register Values 4087215976Sjmallett * 4088215976Sjmallett * Description: 4089215976Sjmallett */ 4090215976Sjmallettunion cvmx_dfa_memrld 4091215976Sjmallett{ 4092215976Sjmallett uint64_t u64; 4093215976Sjmallett struct cvmx_dfa_memrld_s 4094215976Sjmallett { 4095215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4096215976Sjmallett uint64_t reserved_23_63 : 41; 4097215976Sjmallett uint64_t mrsdat : 23; /**< This field represents the data driven onto the 4098215976Sjmallett A[22:0] address lines during MRS(Mode Register Set) 4099215976Sjmallett commands (during a HW init sequence). This field 4100215976Sjmallett corresponds with the Mode Register Bit Map from 4101215976Sjmallett your RLDRAM-II device specific data sheet. 4102215976Sjmallett A[17:10]: RESERVED 4103215976Sjmallett A[9]: ODT (on die termination) 4104215976Sjmallett A[8]: Impedance Matching 4105215976Sjmallett A[7]: DLL Reset 4106215976Sjmallett A[6]: UNUSED 4107215976Sjmallett A[5]: Address Mux (for N3K: MUST BE ZERO) 4108215976Sjmallett A[4:3]: Burst Length (for N3K: MUST BE ZERO) 4109215976Sjmallett A[2:0]: Configuration (see data sheet for 4110215976Sjmallett specific RLDRAM-II device). 4111215976Sjmallett - 000-001: CFG=1 [tRC=4/tRL=4/tWL=5] 4112215976Sjmallett - 010: CFG=2 [tRC=6/tRL=6/tWL=7] 4113215976Sjmallett - 011: CFG=3 [tRC=8/tRL=8/tWL=9] 4114215976Sjmallett - 100-111: RESERVED 4115215976Sjmallett NOTE: For additional density, the RLDRAM-II parts 4116215976Sjmallett can be 'clamshelled' (ie: two devices mounted on 4117215976Sjmallett different sides of the PCB board), since the BGA 4118215976Sjmallett pinout supports 'mirroring'. 4119215976Sjmallett To support a clamshell design, SW must preload 4120215976Sjmallett the MRSDAT[22:0] with the proper A[22:0] pin mapping 4121215976Sjmallett which is dependent on the 'selected' bunk/clam 4122215976Sjmallett (see also: DFA_MEMCFG0[BUNK_INIT] field). 4123215976Sjmallett NOTE: Care MUST BE TAKEN NOT to write to this register 4124215976Sjmallett within 64K eclk cycles of a HW INIT (see: INIT_P0/INIT_P1). 4125215976Sjmallett NOTE: This should only be written to a different value 4126215976Sjmallett during power-on SW initialization. */ 4127215976Sjmallett#else 4128215976Sjmallett uint64_t mrsdat : 23; 4129215976Sjmallett uint64_t reserved_23_63 : 41; 4130215976Sjmallett#endif 4131215976Sjmallett } s; 4132215976Sjmallett struct cvmx_dfa_memrld_s cn38xx; 4133215976Sjmallett struct cvmx_dfa_memrld_s cn38xxp2; 4134215976Sjmallett struct cvmx_dfa_memrld_s cn58xx; 4135215976Sjmallett struct cvmx_dfa_memrld_s cn58xxp1; 4136215976Sjmallett}; 4137215976Sjmalletttypedef union cvmx_dfa_memrld cvmx_dfa_memrld_t; 4138215976Sjmallett 4139215976Sjmallett/** 4140215976Sjmallett * cvmx_dfa_ncbctl 4141215976Sjmallett * 4142215976Sjmallett * DFA_NCBCTL = DFA NCB CTL Register 4143215976Sjmallett * 4144215976Sjmallett * Description: 4145215976Sjmallett */ 4146215976Sjmallettunion cvmx_dfa_ncbctl 4147215976Sjmallett{ 4148215976Sjmallett uint64_t u64; 4149215976Sjmallett struct cvmx_dfa_ncbctl_s 4150215976Sjmallett { 4151215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4152215976Sjmallett uint64_t reserved_11_63 : 53; 4153215976Sjmallett uint64_t sbdnum : 5; /**< SBD Debug Entry# 4154215976Sjmallett For internal use only. (DFA Scoreboard debug) 4155215976Sjmallett Selects which one of 32 DFA Scoreboard entries is 4156215976Sjmallett latched into the DFA_SBD_DBG[0-3] registers. */ 4157215976Sjmallett uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 4158215976Sjmallett For internal use only. (DFA Scoreboard debug) 4159215976Sjmallett When written with a '1', the DFA Scoreboard Debug 4160215976Sjmallett registers (DFA_SBD_DBG[0-3]) are all locked down. 4161215976Sjmallett This allows SW to lock down the contents of the entire 4162215976Sjmallett SBD for a single instant in time. All subsequent reads 4163215976Sjmallett of the DFA scoreboard registers will return the data 4164215976Sjmallett from that instant in time. */ 4165215976Sjmallett uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode 4166215976Sjmallett DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR) 4167215976Sjmallett NOTE: This should only be written to a different value 4168215976Sjmallett during power-on SW initialization. */ 4169215976Sjmallett uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode 4170215976Sjmallett DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR) 4171215976Sjmallett NOTE: This should only be written to a different value 4172215976Sjmallett during power-on SW initialization. */ 4173215976Sjmallett uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 4174215976Sjmallett (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 4175215976Sjmallett NOTE: This should only be written to a different value 4176215976Sjmallett during power-on SW initialization. */ 4177215976Sjmallett uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 4178215976Sjmallett (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 4179215976Sjmallett NOTE: This should only be written to a different value 4180215976Sjmallett during power-on SW initialization. */ 4181215976Sjmallett uint64_t imode : 1; /**< NCB-Inbound Arbiter 4182215976Sjmallett (0=FP [LP=NRQ,HP=NRP], 1=RR) 4183215976Sjmallett NOTE: This should only be written to a different value 4184215976Sjmallett during power-on SW initialization. */ 4185215976Sjmallett#else 4186215976Sjmallett uint64_t imode : 1; 4187215976Sjmallett uint64_t qmode : 1; 4188215976Sjmallett uint64_t pmode : 1; 4189215976Sjmallett uint64_t dtmode : 1; 4190215976Sjmallett uint64_t dcmode : 1; 4191215976Sjmallett uint64_t sbdlck : 1; 4192215976Sjmallett uint64_t sbdnum : 5; 4193215976Sjmallett uint64_t reserved_11_63 : 53; 4194215976Sjmallett#endif 4195215976Sjmallett } s; 4196215976Sjmallett struct cvmx_dfa_ncbctl_cn38xx 4197215976Sjmallett { 4198215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4199215976Sjmallett uint64_t reserved_10_63 : 54; 4200215976Sjmallett uint64_t sbdnum : 4; /**< SBD Debug Entry# 4201215976Sjmallett For internal use only. (DFA Scoreboard debug) 4202215976Sjmallett Selects which one of 16 DFA Scoreboard entries is 4203215976Sjmallett latched into the DFA_SBD_DBG[0-3] registers. */ 4204215976Sjmallett uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 4205215976Sjmallett For internal use only. (DFA Scoreboard debug) 4206215976Sjmallett When written with a '1', the DFA Scoreboard Debug 4207215976Sjmallett registers (DFA_SBD_DBG[0-3]) are all locked down. 4208215976Sjmallett This allows SW to lock down the contents of the entire 4209215976Sjmallett SBD for a single instant in time. All subsequent reads 4210215976Sjmallett of the DFA scoreboard registers will return the data 4211215976Sjmallett from that instant in time. */ 4212215976Sjmallett uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode 4213215976Sjmallett DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR) 4214215976Sjmallett NOTE: This should only be written to a different value 4215215976Sjmallett during power-on SW initialization. */ 4216215976Sjmallett uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode 4217215976Sjmallett DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR) 4218215976Sjmallett NOTE: This should only be written to a different value 4219215976Sjmallett during power-on SW initialization. */ 4220215976Sjmallett uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 4221215976Sjmallett (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 4222215976Sjmallett NOTE: This should only be written to a different value 4223215976Sjmallett during power-on SW initialization. */ 4224215976Sjmallett uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 4225215976Sjmallett (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 4226215976Sjmallett NOTE: This should only be written to a different value 4227215976Sjmallett during power-on SW initialization. */ 4228215976Sjmallett uint64_t imode : 1; /**< NCB-Inbound Arbiter 4229215976Sjmallett (0=FP [LP=NRQ,HP=NRP], 1=RR) 4230215976Sjmallett NOTE: This should only be written to a different value 4231215976Sjmallett during power-on SW initialization. */ 4232215976Sjmallett#else 4233215976Sjmallett uint64_t imode : 1; 4234215976Sjmallett uint64_t qmode : 1; 4235215976Sjmallett uint64_t pmode : 1; 4236215976Sjmallett uint64_t dtmode : 1; 4237215976Sjmallett uint64_t dcmode : 1; 4238215976Sjmallett uint64_t sbdlck : 1; 4239215976Sjmallett uint64_t sbdnum : 4; 4240215976Sjmallett uint64_t reserved_10_63 : 54; 4241215976Sjmallett#endif 4242215976Sjmallett } cn38xx; 4243215976Sjmallett struct cvmx_dfa_ncbctl_cn38xx cn38xxp2; 4244215976Sjmallett struct cvmx_dfa_ncbctl_s cn58xx; 4245215976Sjmallett struct cvmx_dfa_ncbctl_s cn58xxp1; 4246215976Sjmallett}; 4247215976Sjmalletttypedef union cvmx_dfa_ncbctl cvmx_dfa_ncbctl_t; 4248215976Sjmallett 4249215976Sjmallett/** 4250215976Sjmallett * cvmx_dfa_pfc0_cnt 4251215976Sjmallett * 4252215976Sjmallett * DFA_PFC0_CNT = DFA Performance Counter \#0 4253215976Sjmallett * *FOR INTERNAL USE ONLY* 4254215976Sjmallett * Description: 4255215976Sjmallett */ 4256215976Sjmallettunion cvmx_dfa_pfc0_cnt 4257215976Sjmallett{ 4258215976Sjmallett uint64_t u64; 4259215976Sjmallett struct cvmx_dfa_pfc0_cnt_s 4260215976Sjmallett { 4261215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4262215976Sjmallett uint64_t pfcnt0 : 64; /**< Performance Counter \#0 4263215976Sjmallett When DFA_PFC_GCTL[CNT0ENA]=1, the event selected 4264215976Sjmallett by DFA_PFC0_CTL[EVSEL] is counted. 4265215976Sjmallett See also DFA_PFC_GCTL[CNT0WCLR] and DFA_PFC_GCTL 4266215976Sjmallett [CNT0RCLR] for special clear count cases available 4267215976Sjmallett for SW data collection. */ 4268215976Sjmallett#else 4269215976Sjmallett uint64_t pfcnt0 : 64; 4270215976Sjmallett#endif 4271215976Sjmallett } s; 4272215976Sjmallett struct cvmx_dfa_pfc0_cnt_s cn63xx; 4273215976Sjmallett struct cvmx_dfa_pfc0_cnt_s cn63xxp1; 4274215976Sjmallett}; 4275215976Sjmalletttypedef union cvmx_dfa_pfc0_cnt cvmx_dfa_pfc0_cnt_t; 4276215976Sjmallett 4277215976Sjmallett/** 4278215976Sjmallett * cvmx_dfa_pfc0_ctl 4279215976Sjmallett * 4280215976Sjmallett * DFA_PFC0_CTL = DFA Performance Counter#0 Control 4281215976Sjmallett * *FOR INTERNAL USE ONLY* 4282215976Sjmallett * Description: 4283215976Sjmallett */ 4284215976Sjmallettunion cvmx_dfa_pfc0_ctl 4285215976Sjmallett{ 4286215976Sjmallett uint64_t u64; 4287215976Sjmallett struct cvmx_dfa_pfc0_ctl_s 4288215976Sjmallett { 4289215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4290215976Sjmallett uint64_t reserved_14_63 : 50; 4291215976Sjmallett uint64_t evsel : 6; /**< Performance Counter#0 Event Selector 4292215976Sjmallett // Events [0-31] are based on PMODE(0:per cluster-DTE 1:per graph) 4293215976Sjmallett - 0: \#Total Cycles 4294215976Sjmallett - 1: \#LDNODE visits 4295215976Sjmallett - 2: \#SDNODE visits 4296215976Sjmallett - 3: \#DNODE visits (LD/SD) 4297215976Sjmallett - 4: \#LCNODE visits 4298215976Sjmallett - 5: \#SCNODE visits 4299215976Sjmallett - 6: \#CNODE visits (LC/SC) 4300215976Sjmallett - 7: \#LMNODE visits 4301215976Sjmallett - 8: \#SMNODE visits 4302215976Sjmallett - 9: \#MNODE visits (LM/SM) 4303215976Sjmallett - 10: \#MONODE visits 4304215976Sjmallett - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 4305215976Sjmallett - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 4306215976Sjmallett - 13: \#MEMORY visits (MNODE+MONODE) 4307215976Sjmallett - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 4308215976Sjmallett - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 4309215976Sjmallett - 16: \#RESCANs detected (occur when HASH collision is detected) 4310215976Sjmallett - 17: \#GWALK iterations STALLED - Packet data/Result Buffer 4311215976Sjmallett - 18: \#GWALK iterations NON-STALLED 4312215976Sjmallett - 19: \#CLOAD iterations 4313215976Sjmallett - 20: \#MLOAD iterations 4314215976Sjmallett [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#]. 4315215976Sjmallett - 21: \#RWORD1+ writes 4316215976Sjmallett - 22: \#cycles Cluster is busy 4317215976Sjmallett - 23: \#GWALK Instructions 4318215976Sjmallett - 24: \#CLOAD Instructions 4319215976Sjmallett - 25: \#MLOAD Instructions 4320215976Sjmallett [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#]. 4321215976Sjmallett - 26: \#GFREE Instructions 4322215976Sjmallett - 27-30: RESERVED 4323215976Sjmallett - 31: \# Node Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE,EDNODE] registers 4324215976Sjmallett //============================================================= 4325215976Sjmallett // Events [32-63] are used ONLY FOR PMODE=0(per-cluster DTE mode): 4326215976Sjmallett - 32: \#cycles a specific cluster-DTE remains active(valid state) 4327215976Sjmallett - 33: \#cycles a specific cluster-DTE waits for Memory Response Data 4328215976Sjmallett - 34: \#cycles a specific cluster-DTE waits in resource stall state 4329215976Sjmallett (waiting for packet data or result buffer space) 4330215976Sjmallett - 35: \#cycles a specific cluster-DTE waits in resource pending state 4331215976Sjmallett - 36-63: RESERVED 4332215976Sjmallett //============================================================= */ 4333215976Sjmallett uint64_t reserved_6_7 : 2; 4334215976Sjmallett uint64_t cldte : 4; /**< Performance Counter#0 Cluster DTE Selector 4335215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 4336215976Sjmallett is used to select/monitor the cluster's DTE# for all events 4337215976Sjmallett associated with Performance Counter#0. */ 4338215976Sjmallett uint64_t clnum : 2; /**< Performance Counter#0 Cluster Selector 4339215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 4340215976Sjmallett is used to select/monitor the cluster# for all events 4341215976Sjmallett associated with Performance Counter#0. */ 4342215976Sjmallett#else 4343215976Sjmallett uint64_t clnum : 2; 4344215976Sjmallett uint64_t cldte : 4; 4345215976Sjmallett uint64_t reserved_6_7 : 2; 4346215976Sjmallett uint64_t evsel : 6; 4347215976Sjmallett uint64_t reserved_14_63 : 50; 4348215976Sjmallett#endif 4349215976Sjmallett } s; 4350215976Sjmallett struct cvmx_dfa_pfc0_ctl_s cn63xx; 4351215976Sjmallett struct cvmx_dfa_pfc0_ctl_s cn63xxp1; 4352215976Sjmallett}; 4353215976Sjmalletttypedef union cvmx_dfa_pfc0_ctl cvmx_dfa_pfc0_ctl_t; 4354215976Sjmallett 4355215976Sjmallett/** 4356215976Sjmallett * cvmx_dfa_pfc1_cnt 4357215976Sjmallett * 4358215976Sjmallett * DFA_PFC1_CNT = DFA Performance Counter \#1 4359215976Sjmallett * *FOR INTERNAL USE ONLY* 4360215976Sjmallett * Description: 4361215976Sjmallett */ 4362215976Sjmallettunion cvmx_dfa_pfc1_cnt 4363215976Sjmallett{ 4364215976Sjmallett uint64_t u64; 4365215976Sjmallett struct cvmx_dfa_pfc1_cnt_s 4366215976Sjmallett { 4367215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4368215976Sjmallett uint64_t pfcnt1 : 64; /**< Performance Counter \#1 4369215976Sjmallett When DFA_PFC_GCTL[CNT1ENA]=1, the event selected 4370215976Sjmallett by DFA_PFC1_CTL[EVSEL] is counted. 4371215976Sjmallett See also DFA_PFC_GCTL[CNT1WCLR] and DFA_PFC_GCTL 4372215976Sjmallett [CNT1RCLR] for special clear count cases available 4373215976Sjmallett for SW data collection. */ 4374215976Sjmallett#else 4375215976Sjmallett uint64_t pfcnt1 : 64; 4376215976Sjmallett#endif 4377215976Sjmallett } s; 4378215976Sjmallett struct cvmx_dfa_pfc1_cnt_s cn63xx; 4379215976Sjmallett struct cvmx_dfa_pfc1_cnt_s cn63xxp1; 4380215976Sjmallett}; 4381215976Sjmalletttypedef union cvmx_dfa_pfc1_cnt cvmx_dfa_pfc1_cnt_t; 4382215976Sjmallett 4383215976Sjmallett/** 4384215976Sjmallett * cvmx_dfa_pfc1_ctl 4385215976Sjmallett * 4386215976Sjmallett * DFA_PFC1_CTL = DFA Performance Counter#1 Control 4387215976Sjmallett * *FOR INTERNAL USE ONLY* 4388215976Sjmallett * Description: 4389215976Sjmallett */ 4390215976Sjmallettunion cvmx_dfa_pfc1_ctl 4391215976Sjmallett{ 4392215976Sjmallett uint64_t u64; 4393215976Sjmallett struct cvmx_dfa_pfc1_ctl_s 4394215976Sjmallett { 4395215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4396215976Sjmallett uint64_t reserved_14_63 : 50; 4397215976Sjmallett uint64_t evsel : 6; /**< Performance Counter#1 Event Selector 4398215976Sjmallett - 0: \#Cycles 4399215976Sjmallett - 1: \#LDNODE visits 4400215976Sjmallett - 2: \#SDNODE visits 4401215976Sjmallett - 3: \#DNODE visits (LD/SD) 4402215976Sjmallett - 4: \#LCNODE visits 4403215976Sjmallett - 5: \#SCNODE visits 4404215976Sjmallett - 6: \#CNODE visits (LC/SC) 4405215976Sjmallett - 7: \#LMNODE visits 4406215976Sjmallett - 8: \#SMNODE visits 4407215976Sjmallett - 9: \#MNODE visits (LM/SM) 4408215976Sjmallett - 10: \#MONODE visits 4409215976Sjmallett - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 4410215976Sjmallett - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 4411215976Sjmallett - 13: \#MEMORY visits (MNODE+MONODE) 4412215976Sjmallett - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 4413215976Sjmallett - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 4414215976Sjmallett - 16: \#RESCANs detected (occur when HASH collision is detected) 4415215976Sjmallett - 17: \#GWALK STALLs detected - Packet data/Result Buffer 4416215976Sjmallett - 18: \#GWALK DTE cycles (all DTE-GNT[3a]) 4417215976Sjmallett - 19: \#CLOAD DTE cycles 4418215976Sjmallett - 20: \#MLOAD DTE cycles 4419215976Sjmallett - 21: \#cycles waiting for Memory Response Data 4420215976Sjmallett - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space) 4421215976Sjmallett - 23: \#cycles waiting in resource pending state 4422215976Sjmallett - 24: \#RWORD1+ writes 4423215976Sjmallett - 25: \#DTE-VLD cycles 4424215976Sjmallett - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers 4425215976Sjmallett - 27: \#GWALK Instructions 4426215976Sjmallett - 28: \#CLOAD Instructions 4427215976Sjmallett - 29: \#MLOAD Instructions 4428215976Sjmallett - 30: \#GFREE Instructions (== \#GFREE DTE cycles) 4429215976Sjmallett - 31: RESERVED 4430215976Sjmallett - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */ 4431215976Sjmallett uint64_t reserved_6_7 : 2; 4432215976Sjmallett uint64_t cldte : 4; /**< Performance Counter#1 Cluster DTE Selector 4433215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 4434215976Sjmallett is used to select/monitor the cluster's DTE# for all events 4435215976Sjmallett associated with Performance Counter#1. */ 4436215976Sjmallett uint64_t clnum : 2; /**< Performance Counter#1 Cluster Selector 4437215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 4438215976Sjmallett is used to select/monitor the cluster# for all events 4439215976Sjmallett associated with Performance Counter#1. */ 4440215976Sjmallett#else 4441215976Sjmallett uint64_t clnum : 2; 4442215976Sjmallett uint64_t cldte : 4; 4443215976Sjmallett uint64_t reserved_6_7 : 2; 4444215976Sjmallett uint64_t evsel : 6; 4445215976Sjmallett uint64_t reserved_14_63 : 50; 4446215976Sjmallett#endif 4447215976Sjmallett } s; 4448215976Sjmallett struct cvmx_dfa_pfc1_ctl_s cn63xx; 4449215976Sjmallett struct cvmx_dfa_pfc1_ctl_s cn63xxp1; 4450215976Sjmallett}; 4451215976Sjmalletttypedef union cvmx_dfa_pfc1_ctl cvmx_dfa_pfc1_ctl_t; 4452215976Sjmallett 4453215976Sjmallett/** 4454215976Sjmallett * cvmx_dfa_pfc2_cnt 4455215976Sjmallett * 4456215976Sjmallett * DFA_PFC2_CNT = DFA Performance Counter \#2 4457215976Sjmallett * *FOR INTERNAL USE ONLY* 4458215976Sjmallett * Description: 4459215976Sjmallett */ 4460215976Sjmallettunion cvmx_dfa_pfc2_cnt 4461215976Sjmallett{ 4462215976Sjmallett uint64_t u64; 4463215976Sjmallett struct cvmx_dfa_pfc2_cnt_s 4464215976Sjmallett { 4465215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4466215976Sjmallett uint64_t pfcnt2 : 64; /**< Performance Counter \#2 4467215976Sjmallett When DFA_PFC_GCTL[CNT2ENA]=1, the event selected 4468215976Sjmallett by DFA_PFC2_CTL[EVSEL] is counted. 4469215976Sjmallett See also DFA_PFC_GCTL[CNT2WCLR] and DFA_PFC_GCTL 4470215976Sjmallett [CNT2RCLR] for special clear count cases available 4471215976Sjmallett for SW data collection. */ 4472215976Sjmallett#else 4473215976Sjmallett uint64_t pfcnt2 : 64; 4474215976Sjmallett#endif 4475215976Sjmallett } s; 4476215976Sjmallett struct cvmx_dfa_pfc2_cnt_s cn63xx; 4477215976Sjmallett struct cvmx_dfa_pfc2_cnt_s cn63xxp1; 4478215976Sjmallett}; 4479215976Sjmalletttypedef union cvmx_dfa_pfc2_cnt cvmx_dfa_pfc2_cnt_t; 4480215976Sjmallett 4481215976Sjmallett/** 4482215976Sjmallett * cvmx_dfa_pfc2_ctl 4483215976Sjmallett * 4484215976Sjmallett * DFA_PFC2_CTL = DFA Performance Counter#2 Control 4485215976Sjmallett * *FOR INTERNAL USE ONLY* 4486215976Sjmallett * Description: 4487215976Sjmallett */ 4488215976Sjmallettunion cvmx_dfa_pfc2_ctl 4489215976Sjmallett{ 4490215976Sjmallett uint64_t u64; 4491215976Sjmallett struct cvmx_dfa_pfc2_ctl_s 4492215976Sjmallett { 4493215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4494215976Sjmallett uint64_t reserved_14_63 : 50; 4495215976Sjmallett uint64_t evsel : 6; /**< Performance Counter#2 Event Selector 4496215976Sjmallett - 0: \#Cycles 4497215976Sjmallett - 1: \#LDNODE visits 4498215976Sjmallett - 2: \#SDNODE visits 4499215976Sjmallett - 3: \#DNODE visits (LD/SD) 4500215976Sjmallett - 4: \#LCNODE visits 4501215976Sjmallett - 5: \#SCNODE visits 4502215976Sjmallett - 6: \#CNODE visits (LC/SC) 4503215976Sjmallett - 7: \#LMNODE visits 4504215976Sjmallett - 8: \#SMNODE visits 4505215976Sjmallett - 9: \#MNODE visits (LM/SM) 4506215976Sjmallett - 10: \#MONODE visits 4507215976Sjmallett - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 4508215976Sjmallett - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 4509215976Sjmallett - 13: \#MEMORY visits (MNODE+MONODE) 4510215976Sjmallett - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 4511215976Sjmallett - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 4512215976Sjmallett - 16: \#RESCANs detected (occur when HASH collision is detected) 4513215976Sjmallett - 17: \#GWALK STALLs detected - Packet data/Result Buffer 4514215976Sjmallett - 18: \#GWALK DTE cycles (all DTE-GNT[3a]) 4515215976Sjmallett - 19: \#CLOAD DTE cycles 4516215976Sjmallett - 20: \#MLOAD DTE cycles 4517215976Sjmallett - 21: \#cycles waiting for Memory Response Data 4518215976Sjmallett - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space) 4519215976Sjmallett - 23: \#cycles waiting in resource pending state 4520215976Sjmallett - 24: \#RWORD1+ writes 4521215976Sjmallett - 25: \#DTE-VLD cycles 4522215976Sjmallett - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers 4523215976Sjmallett - 27: \#GWALK Instructions 4524215976Sjmallett - 28: \#CLOAD Instructions 4525215976Sjmallett - 29: \#MLOAD Instructions 4526215976Sjmallett - 30: \#GFREE Instructions (== \#GFREE DTE cycles) 4527215976Sjmallett - 31: RESERVED 4528215976Sjmallett - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */ 4529215976Sjmallett uint64_t reserved_6_7 : 2; 4530215976Sjmallett uint64_t cldte : 4; /**< Performance Counter#2 Cluster DTE Selector 4531215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 4532215976Sjmallett is used to select/monitor the cluster's DTE# for all events 4533215976Sjmallett associated with Performance Counter#2. */ 4534215976Sjmallett uint64_t clnum : 2; /**< Performance Counter#2 Cluster Selector 4535215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 4536215976Sjmallett is used to select/monitor the cluster# for all events 4537215976Sjmallett associated with Performance Counter#2. */ 4538215976Sjmallett#else 4539215976Sjmallett uint64_t clnum : 2; 4540215976Sjmallett uint64_t cldte : 4; 4541215976Sjmallett uint64_t reserved_6_7 : 2; 4542215976Sjmallett uint64_t evsel : 6; 4543215976Sjmallett uint64_t reserved_14_63 : 50; 4544215976Sjmallett#endif 4545215976Sjmallett } s; 4546215976Sjmallett struct cvmx_dfa_pfc2_ctl_s cn63xx; 4547215976Sjmallett struct cvmx_dfa_pfc2_ctl_s cn63xxp1; 4548215976Sjmallett}; 4549215976Sjmalletttypedef union cvmx_dfa_pfc2_ctl cvmx_dfa_pfc2_ctl_t; 4550215976Sjmallett 4551215976Sjmallett/** 4552215976Sjmallett * cvmx_dfa_pfc3_cnt 4553215976Sjmallett * 4554215976Sjmallett * DFA_PFC3_CNT = DFA Performance Counter \#3 4555215976Sjmallett * *FOR INTERNAL USE ONLY* 4556215976Sjmallett * Description: 4557215976Sjmallett */ 4558215976Sjmallettunion cvmx_dfa_pfc3_cnt 4559215976Sjmallett{ 4560215976Sjmallett uint64_t u64; 4561215976Sjmallett struct cvmx_dfa_pfc3_cnt_s 4562215976Sjmallett { 4563215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4564215976Sjmallett uint64_t pfcnt3 : 64; /**< Performance Counter \#3 4565215976Sjmallett When DFA_PFC_GCTL[CNT3ENA]=1, the event selected 4566215976Sjmallett by DFA_PFC3_CTL[EVSEL] is counted. 4567215976Sjmallett See also DFA_PFC_GCTL[CNT3WCLR] and DFA_PFC_GCTL 4568215976Sjmallett [CNT3RCLR] for special clear count cases available 4569215976Sjmallett for SW data collection. */ 4570215976Sjmallett#else 4571215976Sjmallett uint64_t pfcnt3 : 64; 4572215976Sjmallett#endif 4573215976Sjmallett } s; 4574215976Sjmallett struct cvmx_dfa_pfc3_cnt_s cn63xx; 4575215976Sjmallett struct cvmx_dfa_pfc3_cnt_s cn63xxp1; 4576215976Sjmallett}; 4577215976Sjmalletttypedef union cvmx_dfa_pfc3_cnt cvmx_dfa_pfc3_cnt_t; 4578215976Sjmallett 4579215976Sjmallett/** 4580215976Sjmallett * cvmx_dfa_pfc3_ctl 4581215976Sjmallett * 4582215976Sjmallett * DFA_PFC3_CTL = DFA Performance Counter#3 Control 4583215976Sjmallett * *FOR INTERNAL USE ONLY* 4584215976Sjmallett * Description: 4585215976Sjmallett */ 4586215976Sjmallettunion cvmx_dfa_pfc3_ctl 4587215976Sjmallett{ 4588215976Sjmallett uint64_t u64; 4589215976Sjmallett struct cvmx_dfa_pfc3_ctl_s 4590215976Sjmallett { 4591215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4592215976Sjmallett uint64_t reserved_14_63 : 50; 4593215976Sjmallett uint64_t evsel : 6; /**< Performance Counter#3 Event Selector 4594215976Sjmallett - 0: \#Cycles 4595215976Sjmallett - 1: \#LDNODE visits 4596215976Sjmallett - 2: \#SDNODE visits 4597215976Sjmallett - 3: \#DNODE visits (LD/SD) 4598215976Sjmallett - 4: \#LCNODE visits 4599215976Sjmallett - 5: \#SCNODE visits 4600215976Sjmallett - 6: \#CNODE visits (LC/SC) 4601215976Sjmallett - 7: \#LMNODE visits 4602215976Sjmallett - 8: \#SMNODE visits 4603215976Sjmallett - 9: \#MNODE visits (LM/SM) 4604215976Sjmallett - 10: \#MONODE visits 4605215976Sjmallett - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 4606215976Sjmallett - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 4607215976Sjmallett - 13: \#MEMORY visits (MNODE+MONODE) 4608215976Sjmallett - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 4609215976Sjmallett - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 4610215976Sjmallett - 16: \#RESCANs detected (occur when HASH collision is detected) 4611215976Sjmallett - 17: \#GWALK STALLs detected - Packet data/Result Buffer 4612215976Sjmallett - 18: \#GWALK DTE cycles (all DTE-GNT[3a]) 4613215976Sjmallett - 19: \#CLOAD DTE cycles 4614215976Sjmallett - 20: \#MLOAD DTE cycles 4615215976Sjmallett - 21: \#cycles waiting for Memory Response Data 4616215976Sjmallett - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space) 4617215976Sjmallett - 23: \#cycles waiting in resource pending state 4618215976Sjmallett - 24: \#RWORD1+ writes 4619215976Sjmallett - 25: \#DTE-VLD cycles 4620215976Sjmallett - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers 4621215976Sjmallett - 27: \#GWALK Instructions 4622215976Sjmallett - 28: \#CLOAD Instructions 4623215976Sjmallett - 29: \#MLOAD Instructions 4624215976Sjmallett - 30: \#GFREE Instructions (== \#GFREE DTE cycles) 4625215976Sjmallett - 31: RESERVED 4626215976Sjmallett - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */ 4627215976Sjmallett uint64_t reserved_6_7 : 2; 4628215976Sjmallett uint64_t cldte : 4; /**< Performance Counter#3 Cluster DTE Selector 4629215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 4630215976Sjmallett is used to select/monitor the cluster's DTE# for all events 4631215976Sjmallett associated with Performance Counter#3. */ 4632215976Sjmallett uint64_t clnum : 2; /**< Performance Counter#3 Cluster Selector 4633215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 4634215976Sjmallett is used to select/monitor the cluster# for all events 4635215976Sjmallett associated with Performance Counter#3. */ 4636215976Sjmallett#else 4637215976Sjmallett uint64_t clnum : 2; 4638215976Sjmallett uint64_t cldte : 4; 4639215976Sjmallett uint64_t reserved_6_7 : 2; 4640215976Sjmallett uint64_t evsel : 6; 4641215976Sjmallett uint64_t reserved_14_63 : 50; 4642215976Sjmallett#endif 4643215976Sjmallett } s; 4644215976Sjmallett struct cvmx_dfa_pfc3_ctl_s cn63xx; 4645215976Sjmallett struct cvmx_dfa_pfc3_ctl_s cn63xxp1; 4646215976Sjmallett}; 4647215976Sjmalletttypedef union cvmx_dfa_pfc3_ctl cvmx_dfa_pfc3_ctl_t; 4648215976Sjmallett 4649215976Sjmallett/** 4650215976Sjmallett * cvmx_dfa_pfc_gctl 4651215976Sjmallett * 4652215976Sjmallett * DFA_PFC_GCTL = DFA Performance Counter Global Control 4653215976Sjmallett * *FOR INTERNAL USE ONLY* 4654215976Sjmallett * Description: 4655215976Sjmallett */ 4656215976Sjmallettunion cvmx_dfa_pfc_gctl 4657215976Sjmallett{ 4658215976Sjmallett uint64_t u64; 4659215976Sjmallett struct cvmx_dfa_pfc_gctl_s 4660215976Sjmallett { 4661215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4662215976Sjmallett uint64_t reserved_29_63 : 35; 4663215976Sjmallett uint64_t vgid : 8; /**< Virtual Graph Id# 4664215976Sjmallett When PMODE=1(per-graph selector), this field is used 4665215976Sjmallett to select/monitor only those events which are 4666215976Sjmallett associated with this selected VGID(virtual graph ID). 4667215976Sjmallett This field is used globally across all four performance 4668215976Sjmallett counters. 4669215976Sjmallett IMPNOTE: I implemented a global VGID across all 4 performance 4670215976Sjmallett counters to save wires/area. */ 4671215976Sjmallett uint64_t pmode : 1; /**< Select Mode 4672215976Sjmallett - 0: Events are selected on a per-cluster DTE# (CLNUM/CLDTE) 4673215976Sjmallett DFA_PFCx_CTL[CLNUM,CLDTE] specifies the cluster-DTE for 4674215976Sjmallett each 1(of 4) performance counters. 4675215976Sjmallett - 1: Events are selected on a per-graph basis (VGID=virtual Graph ID). 4676215976Sjmallett NOTE: Only EVSEL=[0...31] can be used in conjunction with PMODE=1. 4677215976Sjmallett DFA_PFC_GCTL[VGID] specifies the Virtual graph ID used across 4678215976Sjmallett all four performance counters. */ 4679215976Sjmallett uint64_t ednode : 2; /**< Ending DNODE Selector 4680215976Sjmallett When ENODE=0/1(*DNODE), this field is used to further 4681215976Sjmallett specify the Ending DNODE transition sub-type: 4682215976Sjmallett - 0: ALL DNODE sub-types 4683215976Sjmallett - 1: ->D2e (explicit DNODE transition node-arc alone transitions to DNODE) 4684215976Sjmallett - 2: ->D2i (implicit DNODE transition:arc-present triggers transition) 4685215976Sjmallett - 3: ->D1r (rescan DNODE transition) */ 4686215976Sjmallett uint64_t enode : 3; /**< Ending Node Selector 4687215976Sjmallett When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the ENODE 4688215976Sjmallett field is used to select Ending Node, and the SNODE 4689215976Sjmallett field is used to select the Starting Node. 4690215976Sjmallett - 0: LDNODE 4691215976Sjmallett - 1: SDNODE 4692215976Sjmallett - 2: LCNODE 4693215976Sjmallett - 3: SCNODE 4694215976Sjmallett - 4: LMNODE 4695215976Sjmallett - 5: SMNODE 4696215976Sjmallett - 6: MONODE 4697215976Sjmallett - 7: RESERVED */ 4698215976Sjmallett uint64_t snode : 3; /**< Starting Node Selector 4699215976Sjmallett When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the SNODE 4700215976Sjmallett field is used to select Starting Node, and the ENODE 4701215976Sjmallett field is used to select the Ending Node. 4702215976Sjmallett - 0: LDNODE 4703215976Sjmallett - 1: SDNODE 4704215976Sjmallett - 2: LCNODE 4705215976Sjmallett - 3: SCNODE 4706215976Sjmallett - 4: LMNODE 4707215976Sjmallett - 5: SMNODE 4708215976Sjmallett - 6: MONODE 4709215976Sjmallett - 7: RESERVED */ 4710215976Sjmallett uint64_t cnt3rclr : 1; /**< Performance Counter \#3 Read Clear 4711215976Sjmallett If this bit is set, CSR reads to the DFA_PFC3_CNT 4712215976Sjmallett will clear the count value. This allows SW to maintain 4713215976Sjmallett 'cumulative' counters to avoid HW wraparound. */ 4714215976Sjmallett uint64_t cnt2rclr : 1; /**< Performance Counter \#2 Read Clear 4715215976Sjmallett If this bit is set, CSR reads to the DFA_PFC2_CNT 4716215976Sjmallett will clear the count value. This allows SW to maintain 4717215976Sjmallett 'cumulative' counters to avoid HW wraparound. */ 4718215976Sjmallett uint64_t cnt1rclr : 1; /**< Performance Counter \#1 Read Clear 4719215976Sjmallett If this bit is set, CSR reads to the DFA_PFC1_CNT 4720215976Sjmallett will clear the count value. This allows SW to maintain 4721215976Sjmallett 'cumulative' counters to avoid HW wraparound. */ 4722215976Sjmallett uint64_t cnt0rclr : 1; /**< Performance Counter \#0 Read Clear 4723215976Sjmallett If this bit is set, CSR reads to the DFA_PFC0_CNT 4724215976Sjmallett will clear the count value. This allows SW to maintain 4725215976Sjmallett 'cumulative' counters to avoid HW wraparound. */ 4726215976Sjmallett uint64_t cnt3wclr : 1; /**< Performance Counter \#3 Write Clear 4727215976Sjmallett If this bit is set, CSR writes to the DFA_PFC3_CNT 4728215976Sjmallett will clear the count value. 4729215976Sjmallett If this bit is clear, CSR writes to the DFA_PFC3_CNT 4730215976Sjmallett will continue the count from the written value. */ 4731215976Sjmallett uint64_t cnt2wclr : 1; /**< Performance Counter \#2 Write Clear 4732215976Sjmallett If this bit is set, CSR writes to the DFA_PFC2_CNT 4733215976Sjmallett will clear the count value. 4734215976Sjmallett If this bit is clear, CSR writes to the DFA_PFC2_CNT 4735215976Sjmallett will continue the count from the written value. */ 4736215976Sjmallett uint64_t cnt1wclr : 1; /**< Performance Counter \#1 Write Clear 4737215976Sjmallett If this bit is set, CSR writes to the DFA_PFC1_CNT 4738215976Sjmallett will clear the count value. 4739215976Sjmallett If this bit is clear, CSR writes to the DFA_PFC1_CNT 4740215976Sjmallett will continue the count from the written value. */ 4741215976Sjmallett uint64_t cnt0wclr : 1; /**< Performance Counter \#0 Write Clear 4742215976Sjmallett If this bit is set, CSR writes to the DFA_PFC0_CNT 4743215976Sjmallett will clear the count value. 4744215976Sjmallett If this bit is clear, CSR writes to the DFA_PFC0_CNT 4745215976Sjmallett will continue the count from the written value. */ 4746215976Sjmallett uint64_t cnt3ena : 1; /**< Performance Counter 3 Enable 4747215976Sjmallett When this bit is set, the performance counter \#3 4748215976Sjmallett is enabled. */ 4749215976Sjmallett uint64_t cnt2ena : 1; /**< Performance Counter 2 Enable 4750215976Sjmallett When this bit is set, the performance counter \#2 4751215976Sjmallett is enabled. */ 4752215976Sjmallett uint64_t cnt1ena : 1; /**< Performance Counter 1 Enable 4753215976Sjmallett When this bit is set, the performance counter \#1 4754215976Sjmallett is enabled. */ 4755215976Sjmallett uint64_t cnt0ena : 1; /**< Performance Counter 0 Enable 4756215976Sjmallett When this bit is set, the performance counter \#0 4757215976Sjmallett is enabled. */ 4758215976Sjmallett#else 4759215976Sjmallett uint64_t cnt0ena : 1; 4760215976Sjmallett uint64_t cnt1ena : 1; 4761215976Sjmallett uint64_t cnt2ena : 1; 4762215976Sjmallett uint64_t cnt3ena : 1; 4763215976Sjmallett uint64_t cnt0wclr : 1; 4764215976Sjmallett uint64_t cnt1wclr : 1; 4765215976Sjmallett uint64_t cnt2wclr : 1; 4766215976Sjmallett uint64_t cnt3wclr : 1; 4767215976Sjmallett uint64_t cnt0rclr : 1; 4768215976Sjmallett uint64_t cnt1rclr : 1; 4769215976Sjmallett uint64_t cnt2rclr : 1; 4770215976Sjmallett uint64_t cnt3rclr : 1; 4771215976Sjmallett uint64_t snode : 3; 4772215976Sjmallett uint64_t enode : 3; 4773215976Sjmallett uint64_t ednode : 2; 4774215976Sjmallett uint64_t pmode : 1; 4775215976Sjmallett uint64_t vgid : 8; 4776215976Sjmallett uint64_t reserved_29_63 : 35; 4777215976Sjmallett#endif 4778215976Sjmallett } s; 4779215976Sjmallett struct cvmx_dfa_pfc_gctl_s cn63xx; 4780215976Sjmallett struct cvmx_dfa_pfc_gctl_s cn63xxp1; 4781215976Sjmallett}; 4782215976Sjmalletttypedef union cvmx_dfa_pfc_gctl cvmx_dfa_pfc_gctl_t; 4783215976Sjmallett 4784215976Sjmallett/** 4785215976Sjmallett * cvmx_dfa_rodt_comp_ctl 4786215976Sjmallett * 4787215976Sjmallett * DFA_RODT_COMP_CTL = DFA RLD Compensation control (For read "on die termination") 4788215976Sjmallett * 4789215976Sjmallett */ 4790215976Sjmallettunion cvmx_dfa_rodt_comp_ctl 4791215976Sjmallett{ 4792215976Sjmallett uint64_t u64; 4793215976Sjmallett struct cvmx_dfa_rodt_comp_ctl_s 4794215976Sjmallett { 4795215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4796215976Sjmallett uint64_t reserved_17_63 : 47; 4797215976Sjmallett uint64_t enable : 1; /**< Read On Die Termination Enable 4798215976Sjmallett (0=disable, 1=enable) */ 4799215976Sjmallett uint64_t reserved_12_15 : 4; 4800215976Sjmallett uint64_t nctl : 4; /**< Compensation control bits */ 4801215976Sjmallett uint64_t reserved_5_7 : 3; 4802215976Sjmallett uint64_t pctl : 5; /**< Compensation control bits */ 4803215976Sjmallett#else 4804215976Sjmallett uint64_t pctl : 5; 4805215976Sjmallett uint64_t reserved_5_7 : 3; 4806215976Sjmallett uint64_t nctl : 4; 4807215976Sjmallett uint64_t reserved_12_15 : 4; 4808215976Sjmallett uint64_t enable : 1; 4809215976Sjmallett uint64_t reserved_17_63 : 47; 4810215976Sjmallett#endif 4811215976Sjmallett } s; 4812215976Sjmallett struct cvmx_dfa_rodt_comp_ctl_s cn58xx; 4813215976Sjmallett struct cvmx_dfa_rodt_comp_ctl_s cn58xxp1; 4814215976Sjmallett}; 4815215976Sjmalletttypedef union cvmx_dfa_rodt_comp_ctl cvmx_dfa_rodt_comp_ctl_t; 4816215976Sjmallett 4817215976Sjmallett/** 4818215976Sjmallett * cvmx_dfa_sbd_dbg0 4819215976Sjmallett * 4820215976Sjmallett * DFA_SBD_DBG0 = DFA Scoreboard Debug \#0 Register 4821215976Sjmallett * 4822215976Sjmallett * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 4823215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 4824215976Sjmallett * CSR read. 4825215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 4826215976Sjmallett * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 4827215976Sjmallett * instruction. 4828215976Sjmallett */ 4829215976Sjmallettunion cvmx_dfa_sbd_dbg0 4830215976Sjmallett{ 4831215976Sjmallett uint64_t u64; 4832215976Sjmallett struct cvmx_dfa_sbd_dbg0_s 4833215976Sjmallett { 4834215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4835215976Sjmallett uint64_t sbd0 : 64; /**< DFA ScoreBoard \#0 Data 4836215976Sjmallett For internal use only! (DFA Scoreboard Debug) 4837215976Sjmallett [63:40] rptr[26:3]: Result Base Pointer 4838215976Sjmallett [39:24] rwcnt[15:0] Cumulative Result Write Counter 4839215976Sjmallett [23] lastgrdrsp: Last Gather-Rd Response 4840215976Sjmallett [22] wtgrdrsp: Waiting Gather-Rd Response 4841215976Sjmallett [21] wtgrdreq: Waiting for Gather-Rd Issue 4842215976Sjmallett [20] glvld: GLPTR/GLCNT Valid 4843215976Sjmallett [19] cmpmark: Completion Marked Node Detected 4844215976Sjmallett [18:17] cmpcode[1:0]: Completion Code 4845215976Sjmallett [0=PDGONE/1=PERR/2=RFULL/3=TERM] 4846215976Sjmallett [16] cmpdet: Completion Detected 4847215976Sjmallett [15] wthdrwrcmtrsp: Waiting for HDR RWrCmtRsp 4848215976Sjmallett [14] wtlastwrcmtrsp: Waiting for LAST RESULT 4849215976Sjmallett RWrCmtRsp 4850215976Sjmallett [13] hdrwrreq: Waiting for HDR RWrReq 4851215976Sjmallett [12] wtrwrreq: Waiting for RWrReq 4852215976Sjmallett [11] wtwqwrreq: Waiting for WQWrReq issue 4853215976Sjmallett [10] lastprdrspeot: Last Packet-Rd Response 4854215976Sjmallett [9] lastprdrsp: Last Packet-Rd Response 4855215976Sjmallett [8] wtprdrsp: Waiting for PRdRsp EOT 4856215976Sjmallett [7] wtprdreq: Waiting for PRdReq Issue 4857215976Sjmallett [6] lastpdvld: PDPTR/PDLEN Valid 4858215976Sjmallett [5] pdvld: Packet Data Valid 4859215976Sjmallett [4] wqvld: WQVLD 4860215976Sjmallett [3] wqdone: WorkQueue Done condition 4861215976Sjmallett a) WQWrReq issued(for WQPTR<>0) OR 4862215976Sjmallett b) HDR RWrCmtRsp completed) 4863215976Sjmallett [2] rwstf: Resultant write STF/P Mode 4864215976Sjmallett [1] pdldt: Packet-Data LDT mode 4865215976Sjmallett [0] gmode: Gather-Mode */ 4866215976Sjmallett#else 4867215976Sjmallett uint64_t sbd0 : 64; 4868215976Sjmallett#endif 4869215976Sjmallett } s; 4870215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn31xx; 4871215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn38xx; 4872215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn38xxp2; 4873215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn58xx; 4874215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn58xxp1; 4875215976Sjmallett}; 4876215976Sjmalletttypedef union cvmx_dfa_sbd_dbg0 cvmx_dfa_sbd_dbg0_t; 4877215976Sjmallett 4878215976Sjmallett/** 4879215976Sjmallett * cvmx_dfa_sbd_dbg1 4880215976Sjmallett * 4881215976Sjmallett * DFA_SBD_DBG1 = DFA Scoreboard Debug \#1 Register 4882215976Sjmallett * 4883215976Sjmallett * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 4884215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 4885215976Sjmallett * CSR read. 4886215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 4887215976Sjmallett * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 4888215976Sjmallett * instruction. 4889215976Sjmallett */ 4890215976Sjmallettunion cvmx_dfa_sbd_dbg1 4891215976Sjmallett{ 4892215976Sjmallett uint64_t u64; 4893215976Sjmallett struct cvmx_dfa_sbd_dbg1_s 4894215976Sjmallett { 4895215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4896215976Sjmallett uint64_t sbd1 : 64; /**< DFA ScoreBoard \#1 Data 4897215976Sjmallett For internal use only! (DFA Scoreboard Debug) 4898215976Sjmallett [63:61] wqptr[35:33]: Work Queue Pointer 4899215976Sjmallett [60:52] rptr[35:27]: Result Base Pointer 4900215976Sjmallett [51:16] pdptr[35:0]: Packet Data Pointer 4901215976Sjmallett [15:0] pdcnt[15:0]: Packet Data Counter */ 4902215976Sjmallett#else 4903215976Sjmallett uint64_t sbd1 : 64; 4904215976Sjmallett#endif 4905215976Sjmallett } s; 4906215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn31xx; 4907215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn38xx; 4908215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn38xxp2; 4909215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn58xx; 4910215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn58xxp1; 4911215976Sjmallett}; 4912215976Sjmalletttypedef union cvmx_dfa_sbd_dbg1 cvmx_dfa_sbd_dbg1_t; 4913215976Sjmallett 4914215976Sjmallett/** 4915215976Sjmallett * cvmx_dfa_sbd_dbg2 4916215976Sjmallett * 4917215976Sjmallett * DFA_SBD_DBG2 = DFA Scoreboard Debug \#2 Register 4918215976Sjmallett * 4919215976Sjmallett * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 4920215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 4921215976Sjmallett * CSR read. 4922215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 4923215976Sjmallett * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 4924215976Sjmallett * instruction. 4925215976Sjmallett */ 4926215976Sjmallettunion cvmx_dfa_sbd_dbg2 4927215976Sjmallett{ 4928215976Sjmallett uint64_t u64; 4929215976Sjmallett struct cvmx_dfa_sbd_dbg2_s 4930215976Sjmallett { 4931215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4932215976Sjmallett uint64_t sbd2 : 64; /**< DFA ScoreBoard \#2 Data 4933215976Sjmallett [63:49] wqptr[17:3]: Work Queue Pointer 4934215976Sjmallett [48:16] rwptr[35:3]: Result Write Pointer 4935215976Sjmallett [15:0] prwcnt[15:0]: Pending Result Write Counter */ 4936215976Sjmallett#else 4937215976Sjmallett uint64_t sbd2 : 64; 4938215976Sjmallett#endif 4939215976Sjmallett } s; 4940215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn31xx; 4941215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn38xx; 4942215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn38xxp2; 4943215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn58xx; 4944215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn58xxp1; 4945215976Sjmallett}; 4946215976Sjmalletttypedef union cvmx_dfa_sbd_dbg2 cvmx_dfa_sbd_dbg2_t; 4947215976Sjmallett 4948215976Sjmallett/** 4949215976Sjmallett * cvmx_dfa_sbd_dbg3 4950215976Sjmallett * 4951215976Sjmallett * DFA_SBD_DBG3 = DFA Scoreboard Debug \#3 Register 4952215976Sjmallett * 4953215976Sjmallett * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 4954215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 4955215976Sjmallett * CSR read. 4956215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 4957215976Sjmallett * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 4958215976Sjmallett * instruction. 4959215976Sjmallett */ 4960215976Sjmallettunion cvmx_dfa_sbd_dbg3 4961215976Sjmallett{ 4962215976Sjmallett uint64_t u64; 4963215976Sjmallett struct cvmx_dfa_sbd_dbg3_s 4964215976Sjmallett { 4965215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4966215976Sjmallett uint64_t sbd3 : 64; /**< DFA ScoreBoard \#3 Data 4967215976Sjmallett [63:49] wqptr[32:18]: Work Queue Pointer 4968215976Sjmallett [48:16] glptr[35:3]: Gather List Pointer 4969215976Sjmallett [15:0] glcnt[15:0]: Gather List Counter */ 4970215976Sjmallett#else 4971215976Sjmallett uint64_t sbd3 : 64; 4972215976Sjmallett#endif 4973215976Sjmallett } s; 4974215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn31xx; 4975215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn38xx; 4976215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn38xxp2; 4977215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn58xx; 4978215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn58xxp1; 4979215976Sjmallett}; 4980215976Sjmalletttypedef union cvmx_dfa_sbd_dbg3 cvmx_dfa_sbd_dbg3_t; 4981215976Sjmallett 4982215976Sjmallett#endif 4983