1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-dbg-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon dbg. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_DBG_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_DBG_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_DBG_DATA_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 60215976Sjmallett cvmx_warn("CVMX_DBG_DATA not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000001E8ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull)) 65215976Sjmallett#endif 66215976Sjmallett 67215976Sjmallett/** 68215976Sjmallett * cvmx_dbg_data 69215976Sjmallett * 70215976Sjmallett * DBG_DATA = Debug Data Register 71215976Sjmallett * 72215976Sjmallett * Value returned on the debug-data lines from the RSLs 73215976Sjmallett */ 74215976Sjmallettunion cvmx_dbg_data 75215976Sjmallett{ 76215976Sjmallett uint64_t u64; 77215976Sjmallett struct cvmx_dbg_data_s 78215976Sjmallett { 79215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 80215976Sjmallett uint64_t reserved_23_63 : 41; 81215976Sjmallett uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */ 82215976Sjmallett uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 83215976Sjmallett debug select value. */ 84215976Sjmallett uint64_t data : 17; /**< Value on the debug data lines. */ 85215976Sjmallett#else 86215976Sjmallett uint64_t data : 17; 87215976Sjmallett uint64_t dsel_ext : 1; 88215976Sjmallett uint64_t c_mul : 5; 89215976Sjmallett uint64_t reserved_23_63 : 41; 90215976Sjmallett#endif 91215976Sjmallett } s; 92215976Sjmallett struct cvmx_dbg_data_cn30xx 93215976Sjmallett { 94215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 95215976Sjmallett uint64_t reserved_31_63 : 33; 96215976Sjmallett uint64_t pll_mul : 3; /**< pll_mul pins sampled at DCOK assertion */ 97215976Sjmallett uint64_t reserved_23_27 : 5; 98215976Sjmallett uint64_t c_mul : 5; /**< Core PLL multiplier sampled at DCOK assertion */ 99215976Sjmallett uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 100215976Sjmallett debug select value. */ 101215976Sjmallett uint64_t data : 17; /**< Value on the debug data lines. */ 102215976Sjmallett#else 103215976Sjmallett uint64_t data : 17; 104215976Sjmallett uint64_t dsel_ext : 1; 105215976Sjmallett uint64_t c_mul : 5; 106215976Sjmallett uint64_t reserved_23_27 : 5; 107215976Sjmallett uint64_t pll_mul : 3; 108215976Sjmallett uint64_t reserved_31_63 : 33; 109215976Sjmallett#endif 110215976Sjmallett } cn30xx; 111215976Sjmallett struct cvmx_dbg_data_cn30xx cn31xx; 112215976Sjmallett struct cvmx_dbg_data_cn38xx 113215976Sjmallett { 114215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 115215976Sjmallett uint64_t reserved_29_63 : 35; 116215976Sjmallett uint64_t d_mul : 4; /**< D_MUL pins sampled on DCOK assertion */ 117215976Sjmallett uint64_t dclk_mul2 : 1; /**< Should always be set for fast DDR-II operation */ 118215976Sjmallett uint64_t cclk_div2 : 1; /**< Should always be clear for fast core clock */ 119215976Sjmallett uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */ 120215976Sjmallett uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 121215976Sjmallett debug select value. */ 122215976Sjmallett uint64_t data : 17; /**< Value on the debug data lines. */ 123215976Sjmallett#else 124215976Sjmallett uint64_t data : 17; 125215976Sjmallett uint64_t dsel_ext : 1; 126215976Sjmallett uint64_t c_mul : 5; 127215976Sjmallett uint64_t cclk_div2 : 1; 128215976Sjmallett uint64_t dclk_mul2 : 1; 129215976Sjmallett uint64_t d_mul : 4; 130215976Sjmallett uint64_t reserved_29_63 : 35; 131215976Sjmallett#endif 132215976Sjmallett } cn38xx; 133215976Sjmallett struct cvmx_dbg_data_cn38xx cn38xxp2; 134215976Sjmallett struct cvmx_dbg_data_cn30xx cn50xx; 135215976Sjmallett struct cvmx_dbg_data_cn58xx 136215976Sjmallett { 137215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 138215976Sjmallett uint64_t reserved_29_63 : 35; 139215976Sjmallett uint64_t rem : 6; /**< Remaining debug_select pins sampled at DCOK */ 140215976Sjmallett uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */ 141215976Sjmallett uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 142215976Sjmallett debug select value. */ 143215976Sjmallett uint64_t data : 17; /**< Value on the debug data lines. */ 144215976Sjmallett#else 145215976Sjmallett uint64_t data : 17; 146215976Sjmallett uint64_t dsel_ext : 1; 147215976Sjmallett uint64_t c_mul : 5; 148215976Sjmallett uint64_t rem : 6; 149215976Sjmallett uint64_t reserved_29_63 : 35; 150215976Sjmallett#endif 151215976Sjmallett } cn58xx; 152215976Sjmallett struct cvmx_dbg_data_cn58xx cn58xxp1; 153215976Sjmallett}; 154215976Sjmalletttypedef union cvmx_dbg_data cvmx_dbg_data_t; 155215976Sjmallett 156215976Sjmallett#endif 157