1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-agl-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon agl. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_AGL_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_AGL_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60215976Sjmallett cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000518ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void) 69215976Sjmallett{ 70215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 71215976Sjmallett cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000400ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_AGL_GMX_DRV_CTL CVMX_AGL_GMX_DRV_CTL_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_DRV_CTL_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 82215976Sjmallett cvmx_warn("CVMX_AGL_GMX_DRV_CTL not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00007F0ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_AGL_GMX_INF_MODE CVMX_AGL_GMX_INF_MODE_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_INF_MODE_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 93215976Sjmallett cvmx_warn("CVMX_AGL_GMX_INF_MODE not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00007F8ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_PRTX_CFG(unsigned long offset) 101215976Sjmallett{ 102215976Sjmallett if (!( 103215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 104215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 105215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 106215976Sjmallett cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset); 107215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048; 108215976Sjmallett} 109215976Sjmallett#else 110215976Sjmallett#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048) 111215976Sjmallett#endif 112215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 113215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM0(unsigned long offset) 114215976Sjmallett{ 115215976Sjmallett if (!( 116215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 117215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 118215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 119215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset); 120215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048; 121215976Sjmallett} 122215976Sjmallett#else 123215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048) 124215976Sjmallett#endif 125215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 126215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM1(unsigned long offset) 127215976Sjmallett{ 128215976Sjmallett if (!( 129215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 130215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 131215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 132215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset); 133215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048; 134215976Sjmallett} 135215976Sjmallett#else 136215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048) 137215976Sjmallett#endif 138215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 139215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM2(unsigned long offset) 140215976Sjmallett{ 141215976Sjmallett if (!( 142215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 143215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 144215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 145215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset); 146215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048; 147215976Sjmallett} 148215976Sjmallett#else 149215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048) 150215976Sjmallett#endif 151215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM3(unsigned long offset) 153215976Sjmallett{ 154215976Sjmallett if (!( 155215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 156215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 157215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 158215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset); 159215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048; 160215976Sjmallett} 161215976Sjmallett#else 162215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048) 163215976Sjmallett#endif 164215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 165215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM4(unsigned long offset) 166215976Sjmallett{ 167215976Sjmallett if (!( 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 169215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 170215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 171215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset); 172215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048; 173215976Sjmallett} 174215976Sjmallett#else 175215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048) 176215976Sjmallett#endif 177215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 178215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM5(unsigned long offset) 179215976Sjmallett{ 180215976Sjmallett if (!( 181215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 182215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 183215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 184215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset); 185215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048; 186215976Sjmallett} 187215976Sjmallett#else 188215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048) 189215976Sjmallett#endif 190215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM_EN(unsigned long offset) 192215976Sjmallett{ 193215976Sjmallett if (!( 194215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 195215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 196215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 197215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset); 198215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048; 199215976Sjmallett} 200215976Sjmallett#else 201215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048) 202215976Sjmallett#endif 203215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 204215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CTL(unsigned long offset) 205215976Sjmallett{ 206215976Sjmallett if (!( 207215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 208215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 209215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 210215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset); 211215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048; 212215976Sjmallett} 213215976Sjmallett#else 214215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048) 215215976Sjmallett#endif 216215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 217215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_DECISION(unsigned long offset) 218215976Sjmallett{ 219215976Sjmallett if (!( 220215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 221215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 222215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 223215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset); 224215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048; 225215976Sjmallett} 226215976Sjmallett#else 227215976Sjmallett#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048) 228215976Sjmallett#endif 229215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 230215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_FRM_CHK(unsigned long offset) 231215976Sjmallett{ 232215976Sjmallett if (!( 233215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 234215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 235215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 236215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset); 237215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048; 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_FRM_CTL(unsigned long offset) 244215976Sjmallett{ 245215976Sjmallett if (!( 246215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 247215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 248215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 249215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset); 250215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048; 251215976Sjmallett} 252215976Sjmallett#else 253215976Sjmallett#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048) 254215976Sjmallett#endif 255215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 256215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_FRM_MAX(unsigned long offset) 257215976Sjmallett{ 258215976Sjmallett if (!( 259215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 260215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 261215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 262215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset); 263215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048; 264215976Sjmallett} 265215976Sjmallett#else 266215976Sjmallett#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048) 267215976Sjmallett#endif 268215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 269215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_FRM_MIN(unsigned long offset) 270215976Sjmallett{ 271215976Sjmallett if (!( 272215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 273215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 274215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 275215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset); 276215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048; 277215976Sjmallett} 278215976Sjmallett#else 279215976Sjmallett#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048) 280215976Sjmallett#endif 281215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 282215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_IFG(unsigned long offset) 283215976Sjmallett{ 284215976Sjmallett if (!( 285215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 286215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 287215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 288215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset); 289215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048; 290215976Sjmallett} 291215976Sjmallett#else 292215976Sjmallett#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048) 293215976Sjmallett#endif 294215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 295215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_INT_EN(unsigned long offset) 296215976Sjmallett{ 297215976Sjmallett if (!( 298215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 299215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 300215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 301215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset); 302215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048; 303215976Sjmallett} 304215976Sjmallett#else 305215976Sjmallett#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048) 306215976Sjmallett#endif 307215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_INT_REG(unsigned long offset) 309215976Sjmallett{ 310215976Sjmallett if (!( 311215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 312215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 313215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 314215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset); 315215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048; 316215976Sjmallett} 317215976Sjmallett#else 318215976Sjmallett#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048) 319215976Sjmallett#endif 320215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 321215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_JABBER(unsigned long offset) 322215976Sjmallett{ 323215976Sjmallett if (!( 324215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 325215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 326215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 327215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset); 328215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048; 329215976Sjmallett} 330215976Sjmallett#else 331215976Sjmallett#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048) 332215976Sjmallett#endif 333215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 334215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset) 335215976Sjmallett{ 336215976Sjmallett if (!( 337215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 338215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 339215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 340215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset); 341215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048; 342215976Sjmallett} 343215976Sjmallett#else 344215976Sjmallett#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048) 345215976Sjmallett#endif 346215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 347215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_RX_INBND(unsigned long offset) 348215976Sjmallett{ 349215976Sjmallett if (!( 350215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 351215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_RX_INBND(%lu) is invalid on this chip\n", offset); 352215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048; 353215976Sjmallett} 354215976Sjmallett#else 355215976Sjmallett#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048) 356215976Sjmallett#endif 357215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 358215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_CTL(unsigned long offset) 359215976Sjmallett{ 360215976Sjmallett if (!( 361215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 362215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 363215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 364215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset); 365215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048; 366215976Sjmallett} 367215976Sjmallett#else 368215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048) 369215976Sjmallett#endif 370215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS(unsigned long offset) 372215976Sjmallett{ 373215976Sjmallett if (!( 374215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 375215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 376215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 377215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset); 378215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048; 379215976Sjmallett} 380215976Sjmallett#else 381215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048) 382215976Sjmallett#endif 383215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 384215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(unsigned long offset) 385215976Sjmallett{ 386215976Sjmallett if (!( 387215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 388215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 389215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 390215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset); 391215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048; 392215976Sjmallett} 393215976Sjmallett#else 394215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048) 395215976Sjmallett#endif 396215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(unsigned long offset) 398215976Sjmallett{ 399215976Sjmallett if (!( 400215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 401215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 402215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 403215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset); 404215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048; 405215976Sjmallett} 406215976Sjmallett#else 407215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048) 408215976Sjmallett#endif 409215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 410215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(unsigned long offset) 411215976Sjmallett{ 412215976Sjmallett if (!( 413215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 414215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 415215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 416215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset); 417215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048; 418215976Sjmallett} 419215976Sjmallett#else 420215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048) 421215976Sjmallett#endif 422215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 423215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS(unsigned long offset) 424215976Sjmallett{ 425215976Sjmallett if (!( 426215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 427215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 428215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 429215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset); 430215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048; 431215976Sjmallett} 432215976Sjmallett#else 433215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048) 434215976Sjmallett#endif 435215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 436215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(unsigned long offset) 437215976Sjmallett{ 438215976Sjmallett if (!( 439215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 440215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 441215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 442215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset); 443215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048; 444215976Sjmallett} 445215976Sjmallett#else 446215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048) 447215976Sjmallett#endif 448215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 449215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(unsigned long offset) 450215976Sjmallett{ 451215976Sjmallett if (!( 452215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 453215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 454215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 455215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset); 456215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048; 457215976Sjmallett} 458215976Sjmallett#else 459215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048) 460215976Sjmallett#endif 461215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 462215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(unsigned long offset) 463215976Sjmallett{ 464215976Sjmallett if (!( 465215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 466215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 467215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 468215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset); 469215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048; 470215976Sjmallett} 471215976Sjmallett#else 472215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048) 473215976Sjmallett#endif 474215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 475215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(unsigned long offset) 476215976Sjmallett{ 477215976Sjmallett if (!( 478215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 479215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 480215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 481215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset); 482215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048; 483215976Sjmallett} 484215976Sjmallett#else 485215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048) 486215976Sjmallett#endif 487215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 488215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_UDD_SKP(unsigned long offset) 489215976Sjmallett{ 490215976Sjmallett if (!( 491215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 492215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 493215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 494215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset); 495215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048; 496215976Sjmallett} 497215976Sjmallett#else 498215976Sjmallett#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048) 499215976Sjmallett#endif 500215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 501215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_BP_DROPX(unsigned long offset) 502215976Sjmallett{ 503215976Sjmallett if (!( 504215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 505215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 506215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 507215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset); 508215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8; 509215976Sjmallett} 510215976Sjmallett#else 511215976Sjmallett#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8) 512215976Sjmallett#endif 513215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 514215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_BP_OFFX(unsigned long offset) 515215976Sjmallett{ 516215976Sjmallett if (!( 517215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 518215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 519215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 520215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset); 521215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8; 522215976Sjmallett} 523215976Sjmallett#else 524215976Sjmallett#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8) 525215976Sjmallett#endif 526215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 527215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset) 528215976Sjmallett{ 529215976Sjmallett if (!( 530215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 531215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 532215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 533215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset); 534215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8; 535215976Sjmallett} 536215976Sjmallett#else 537215976Sjmallett#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8) 538215976Sjmallett#endif 539215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540215976Sjmallett#define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC() 541215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void) 542215976Sjmallett{ 543215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 544215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n"); 545215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004E8ull); 546215976Sjmallett} 547215976Sjmallett#else 548215976Sjmallett#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull)) 549215976Sjmallett#endif 550215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551215976Sjmallett#define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC() 552215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void) 553215976Sjmallett{ 554215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 555215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n"); 556215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00007E8ull); 557215976Sjmallett} 558215976Sjmallett#else 559215976Sjmallett#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull)) 560215976Sjmallett#endif 561215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset) 563215976Sjmallett{ 564215976Sjmallett if (!( 565215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 566215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 567215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 568215976Sjmallett cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset); 569215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048; 570215976Sjmallett} 571215976Sjmallett#else 572215976Sjmallett#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048) 573215976Sjmallett#endif 574215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 575215976Sjmallett#define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC() 576215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void) 577215976Sjmallett{ 578215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 579215976Sjmallett cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n"); 580215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000520ull); 581215976Sjmallett} 582215976Sjmallett#else 583215976Sjmallett#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull)) 584215976Sjmallett#endif 585215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 586215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset) 587215976Sjmallett{ 588215976Sjmallett if (!( 589215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 590215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 591215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 592215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset); 593215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048; 594215976Sjmallett} 595215976Sjmallett#else 596215976Sjmallett#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048) 597215976Sjmallett#endif 598215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 599215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_CLK(unsigned long offset) 600215976Sjmallett{ 601215976Sjmallett if (!( 602215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 603215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_CLK(%lu) is invalid on this chip\n", offset); 604215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048; 605215976Sjmallett} 606215976Sjmallett#else 607215976Sjmallett#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048) 608215976Sjmallett#endif 609215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 610215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_CTL(unsigned long offset) 611215976Sjmallett{ 612215976Sjmallett if (!( 613215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 614215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 615215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 616215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset); 617215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048; 618215976Sjmallett} 619215976Sjmallett#else 620215976Sjmallett#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048) 621215976Sjmallett#endif 622215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 623215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_MIN_PKT(unsigned long offset) 624215976Sjmallett{ 625215976Sjmallett if (!( 626215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 627215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 628215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 629215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset); 630215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048; 631215976Sjmallett} 632215976Sjmallett#else 633215976Sjmallett#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048) 634215976Sjmallett#endif 635215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 636215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset) 637215976Sjmallett{ 638215976Sjmallett if (!( 639215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 640215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 641215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 642215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset); 643215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048; 644215976Sjmallett} 645215976Sjmallett#else 646215976Sjmallett#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048) 647215976Sjmallett#endif 648215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 649215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(unsigned long offset) 650215976Sjmallett{ 651215976Sjmallett if (!( 652215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 653215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 654215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 655215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset); 656215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048; 657215976Sjmallett} 658215976Sjmallett#else 659215976Sjmallett#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048) 660215976Sjmallett#endif 661215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 662215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_TOGO(unsigned long offset) 663215976Sjmallett{ 664215976Sjmallett if (!( 665215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 666215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 667215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 668215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset); 669215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048; 670215976Sjmallett} 671215976Sjmallett#else 672215976Sjmallett#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048) 673215976Sjmallett#endif 674215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 675215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_ZERO(unsigned long offset) 676215976Sjmallett{ 677215976Sjmallett if (!( 678215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 679215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 680215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 681215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset); 682215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048; 683215976Sjmallett} 684215976Sjmallett#else 685215976Sjmallett#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048) 686215976Sjmallett#endif 687215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 688215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_SOFT_PAUSE(unsigned long offset) 689215976Sjmallett{ 690215976Sjmallett if (!( 691215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 692215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 693215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 694215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset); 695215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048; 696215976Sjmallett} 697215976Sjmallett#else 698215976Sjmallett#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048) 699215976Sjmallett#endif 700215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 701215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT0(unsigned long offset) 702215976Sjmallett{ 703215976Sjmallett if (!( 704215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 705215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 706215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 707215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset); 708215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048; 709215976Sjmallett} 710215976Sjmallett#else 711215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048) 712215976Sjmallett#endif 713215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 714215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT1(unsigned long offset) 715215976Sjmallett{ 716215976Sjmallett if (!( 717215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 718215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 719215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 720215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset); 721215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048; 722215976Sjmallett} 723215976Sjmallett#else 724215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048) 725215976Sjmallett#endif 726215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT2(unsigned long offset) 728215976Sjmallett{ 729215976Sjmallett if (!( 730215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 731215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 732215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 733215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset); 734215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048; 735215976Sjmallett} 736215976Sjmallett#else 737215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048) 738215976Sjmallett#endif 739215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 740215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT3(unsigned long offset) 741215976Sjmallett{ 742215976Sjmallett if (!( 743215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 744215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 745215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 746215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset); 747215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048; 748215976Sjmallett} 749215976Sjmallett#else 750215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048) 751215976Sjmallett#endif 752215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 753215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT4(unsigned long offset) 754215976Sjmallett{ 755215976Sjmallett if (!( 756215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 757215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 758215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 759215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset); 760215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048; 761215976Sjmallett} 762215976Sjmallett#else 763215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048) 764215976Sjmallett#endif 765215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 766215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT5(unsigned long offset) 767215976Sjmallett{ 768215976Sjmallett if (!( 769215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 770215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 771215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 772215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset); 773215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048; 774215976Sjmallett} 775215976Sjmallett#else 776215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048) 777215976Sjmallett#endif 778215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 779215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT6(unsigned long offset) 780215976Sjmallett{ 781215976Sjmallett if (!( 782215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 783215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 784215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 785215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset); 786215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048; 787215976Sjmallett} 788215976Sjmallett#else 789215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048) 790215976Sjmallett#endif 791215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 792215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT7(unsigned long offset) 793215976Sjmallett{ 794215976Sjmallett if (!( 795215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 796215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 797215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 798215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT7(%lu) is invalid on this chip\n", offset); 799215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048; 800215976Sjmallett} 801215976Sjmallett#else 802215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048) 803215976Sjmallett#endif 804215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 805215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT8(unsigned long offset) 806215976Sjmallett{ 807215976Sjmallett if (!( 808215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 809215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 810215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 811215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT8(%lu) is invalid on this chip\n", offset); 812215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048; 813215976Sjmallett} 814215976Sjmallett#else 815215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048) 816215976Sjmallett#endif 817215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 818215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT9(unsigned long offset) 819215976Sjmallett{ 820215976Sjmallett if (!( 821215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 822215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 823215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 824215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT9(%lu) is invalid on this chip\n", offset); 825215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048; 826215976Sjmallett} 827215976Sjmallett#else 828215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048) 829215976Sjmallett#endif 830215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 831215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STATS_CTL(unsigned long offset) 832215976Sjmallett{ 833215976Sjmallett if (!( 834215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 835215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 836215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 837215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STATS_CTL(%lu) is invalid on this chip\n", offset); 838215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048; 839215976Sjmallett} 840215976Sjmallett#else 841215976Sjmallett#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048) 842215976Sjmallett#endif 843215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 844215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset) 845215976Sjmallett{ 846215976Sjmallett if (!( 847215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 848215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 849215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 850215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_THRESH(%lu) is invalid on this chip\n", offset); 851215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048; 852215976Sjmallett} 853215976Sjmallett#else 854215976Sjmallett#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048) 855215976Sjmallett#endif 856215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 857215976Sjmallett#define CVMX_AGL_GMX_TX_BP CVMX_AGL_GMX_TX_BP_FUNC() 858215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void) 859215976Sjmallett{ 860215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 861215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_BP not supported on this chip\n"); 862215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004D0ull); 863215976Sjmallett} 864215976Sjmallett#else 865215976Sjmallett#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull)) 866215976Sjmallett#endif 867215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 868215976Sjmallett#define CVMX_AGL_GMX_TX_COL_ATTEMPT CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC() 869215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void) 870215976Sjmallett{ 871215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 872215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_COL_ATTEMPT not supported on this chip\n"); 873215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000498ull); 874215976Sjmallett} 875215976Sjmallett#else 876215976Sjmallett#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull)) 877215976Sjmallett#endif 878215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 879215976Sjmallett#define CVMX_AGL_GMX_TX_IFG CVMX_AGL_GMX_TX_IFG_FUNC() 880215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void) 881215976Sjmallett{ 882215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 883215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_IFG not supported on this chip\n"); 884215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000488ull); 885215976Sjmallett} 886215976Sjmallett#else 887215976Sjmallett#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull)) 888215976Sjmallett#endif 889215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 890215976Sjmallett#define CVMX_AGL_GMX_TX_INT_EN CVMX_AGL_GMX_TX_INT_EN_FUNC() 891215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void) 892215976Sjmallett{ 893215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 894215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_INT_EN not supported on this chip\n"); 895215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000508ull); 896215976Sjmallett} 897215976Sjmallett#else 898215976Sjmallett#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull)) 899215976Sjmallett#endif 900215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 901215976Sjmallett#define CVMX_AGL_GMX_TX_INT_REG CVMX_AGL_GMX_TX_INT_REG_FUNC() 902215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void) 903215976Sjmallett{ 904215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 905215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_INT_REG not supported on this chip\n"); 906215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000500ull); 907215976Sjmallett} 908215976Sjmallett#else 909215976Sjmallett#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull)) 910215976Sjmallett#endif 911215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 912215976Sjmallett#define CVMX_AGL_GMX_TX_JAM CVMX_AGL_GMX_TX_JAM_FUNC() 913215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void) 914215976Sjmallett{ 915215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 916215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_JAM not supported on this chip\n"); 917215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000490ull); 918215976Sjmallett} 919215976Sjmallett#else 920215976Sjmallett#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull)) 921215976Sjmallett#endif 922215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 923215976Sjmallett#define CVMX_AGL_GMX_TX_LFSR CVMX_AGL_GMX_TX_LFSR_FUNC() 924215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void) 925215976Sjmallett{ 926215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 927215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_LFSR not supported on this chip\n"); 928215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004F8ull); 929215976Sjmallett} 930215976Sjmallett#else 931215976Sjmallett#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull)) 932215976Sjmallett#endif 933215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 934215976Sjmallett#define CVMX_AGL_GMX_TX_OVR_BP CVMX_AGL_GMX_TX_OVR_BP_FUNC() 935215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void) 936215976Sjmallett{ 937215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 938215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_OVR_BP not supported on this chip\n"); 939215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004C8ull); 940215976Sjmallett} 941215976Sjmallett#else 942215976Sjmallett#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull)) 943215976Sjmallett#endif 944215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 945215976Sjmallett#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC() 946215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void) 947215976Sjmallett{ 948215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 949215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC not supported on this chip\n"); 950215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004A0ull); 951215976Sjmallett} 952215976Sjmallett#else 953215976Sjmallett#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull)) 954215976Sjmallett#endif 955215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 956215976Sjmallett#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC() 957215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void) 958215976Sjmallett{ 959215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 960215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE not supported on this chip\n"); 961215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004A8ull); 962215976Sjmallett} 963215976Sjmallett#else 964215976Sjmallett#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull)) 965215976Sjmallett#endif 966215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 967215976Sjmallettstatic inline uint64_t CVMX_AGL_PRTX_CTL(unsigned long offset) 968215976Sjmallett{ 969215976Sjmallett if (!( 970215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 971215976Sjmallett cvmx_warn("CVMX_AGL_PRTX_CTL(%lu) is invalid on this chip\n", offset); 972215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8; 973215976Sjmallett} 974215976Sjmallett#else 975215976Sjmallett#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8) 976215976Sjmallett#endif 977215976Sjmallett 978215976Sjmallett/** 979215976Sjmallett * cvmx_agl_gmx_bad_reg 980215976Sjmallett * 981215976Sjmallett * AGL_GMX_BAD_REG = A collection of things that have gone very, very wrong 982215976Sjmallett * 983215976Sjmallett * 984215976Sjmallett * Notes: 985215976Sjmallett * OUT_OVR[0], LOSTSTAT[0], OVRFLW, TXPOP, TXPSH will be reset when MIX0_CTL[RESET] is set to 1. 986215976Sjmallett * OUT_OVR[1], LOSTSTAT[1], OVRFLW1, TXPOP1, TXPSH1 will be reset when MIX1_CTL[RESET] is set to 1. 987215976Sjmallett * STATOVR will be reset when both MIX0/1_CTL[RESET] are set to 1. 988215976Sjmallett */ 989215976Sjmallettunion cvmx_agl_gmx_bad_reg 990215976Sjmallett{ 991215976Sjmallett uint64_t u64; 992215976Sjmallett struct cvmx_agl_gmx_bad_reg_s 993215976Sjmallett { 994215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 995215976Sjmallett uint64_t reserved_38_63 : 26; 996215976Sjmallett uint64_t txpsh1 : 1; /**< TX FIFO overflow (MII1) */ 997215976Sjmallett uint64_t txpop1 : 1; /**< TX FIFO underflow (MII1) */ 998215976Sjmallett uint64_t ovrflw1 : 1; /**< RX FIFO overflow (MII1) */ 999215976Sjmallett uint64_t txpsh : 1; /**< TX FIFO overflow (MII0) */ 1000215976Sjmallett uint64_t txpop : 1; /**< TX FIFO underflow (MII0) */ 1001215976Sjmallett uint64_t ovrflw : 1; /**< RX FIFO overflow (MII0) */ 1002215976Sjmallett uint64_t reserved_27_31 : 5; 1003215976Sjmallett uint64_t statovr : 1; /**< TX Statistics overflow */ 1004215976Sjmallett uint64_t reserved_24_25 : 2; 1005215976Sjmallett uint64_t loststat : 2; /**< TX Statistics data was over-written 1006215976Sjmallett In MII/RGMII, one bit per port 1007215976Sjmallett TX Stats are corrupted */ 1008215976Sjmallett uint64_t reserved_4_21 : 18; 1009215976Sjmallett uint64_t out_ovr : 2; /**< Outbound data FIFO overflow */ 1010215976Sjmallett uint64_t reserved_0_1 : 2; 1011215976Sjmallett#else 1012215976Sjmallett uint64_t reserved_0_1 : 2; 1013215976Sjmallett uint64_t out_ovr : 2; 1014215976Sjmallett uint64_t reserved_4_21 : 18; 1015215976Sjmallett uint64_t loststat : 2; 1016215976Sjmallett uint64_t reserved_24_25 : 2; 1017215976Sjmallett uint64_t statovr : 1; 1018215976Sjmallett uint64_t reserved_27_31 : 5; 1019215976Sjmallett uint64_t ovrflw : 1; 1020215976Sjmallett uint64_t txpop : 1; 1021215976Sjmallett uint64_t txpsh : 1; 1022215976Sjmallett uint64_t ovrflw1 : 1; 1023215976Sjmallett uint64_t txpop1 : 1; 1024215976Sjmallett uint64_t txpsh1 : 1; 1025215976Sjmallett uint64_t reserved_38_63 : 26; 1026215976Sjmallett#endif 1027215976Sjmallett } s; 1028215976Sjmallett struct cvmx_agl_gmx_bad_reg_cn52xx 1029215976Sjmallett { 1030215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1031215976Sjmallett uint64_t reserved_38_63 : 26; 1032215976Sjmallett uint64_t txpsh1 : 1; /**< TX FIFO overflow (MII1) */ 1033215976Sjmallett uint64_t txpop1 : 1; /**< TX FIFO underflow (MII1) */ 1034215976Sjmallett uint64_t ovrflw1 : 1; /**< RX FIFO overflow (MII1) */ 1035215976Sjmallett uint64_t txpsh : 1; /**< TX FIFO overflow (MII0) */ 1036215976Sjmallett uint64_t txpop : 1; /**< TX FIFO underflow (MII0) */ 1037215976Sjmallett uint64_t ovrflw : 1; /**< RX FIFO overflow (MII0) */ 1038215976Sjmallett uint64_t reserved_27_31 : 5; 1039215976Sjmallett uint64_t statovr : 1; /**< TX Statistics overflow */ 1040215976Sjmallett uint64_t reserved_23_25 : 3; 1041215976Sjmallett uint64_t loststat : 1; /**< TX Statistics data was over-written 1042215976Sjmallett TX Stats are corrupted */ 1043215976Sjmallett uint64_t reserved_4_21 : 18; 1044215976Sjmallett uint64_t out_ovr : 2; /**< Outbound data FIFO overflow */ 1045215976Sjmallett uint64_t reserved_0_1 : 2; 1046215976Sjmallett#else 1047215976Sjmallett uint64_t reserved_0_1 : 2; 1048215976Sjmallett uint64_t out_ovr : 2; 1049215976Sjmallett uint64_t reserved_4_21 : 18; 1050215976Sjmallett uint64_t loststat : 1; 1051215976Sjmallett uint64_t reserved_23_25 : 3; 1052215976Sjmallett uint64_t statovr : 1; 1053215976Sjmallett uint64_t reserved_27_31 : 5; 1054215976Sjmallett uint64_t ovrflw : 1; 1055215976Sjmallett uint64_t txpop : 1; 1056215976Sjmallett uint64_t txpsh : 1; 1057215976Sjmallett uint64_t ovrflw1 : 1; 1058215976Sjmallett uint64_t txpop1 : 1; 1059215976Sjmallett uint64_t txpsh1 : 1; 1060215976Sjmallett uint64_t reserved_38_63 : 26; 1061215976Sjmallett#endif 1062215976Sjmallett } cn52xx; 1063215976Sjmallett struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1; 1064215976Sjmallett struct cvmx_agl_gmx_bad_reg_cn56xx 1065215976Sjmallett { 1066215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1067215976Sjmallett uint64_t reserved_35_63 : 29; 1068215976Sjmallett uint64_t txpsh : 1; /**< TX FIFO overflow */ 1069215976Sjmallett uint64_t txpop : 1; /**< TX FIFO underflow */ 1070215976Sjmallett uint64_t ovrflw : 1; /**< RX FIFO overflow */ 1071215976Sjmallett uint64_t reserved_27_31 : 5; 1072215976Sjmallett uint64_t statovr : 1; /**< TX Statistics overflow */ 1073215976Sjmallett uint64_t reserved_23_25 : 3; 1074215976Sjmallett uint64_t loststat : 1; /**< TX Statistics data was over-written 1075215976Sjmallett TX Stats are corrupted */ 1076215976Sjmallett uint64_t reserved_3_21 : 19; 1077215976Sjmallett uint64_t out_ovr : 1; /**< Outbound data FIFO overflow */ 1078215976Sjmallett uint64_t reserved_0_1 : 2; 1079215976Sjmallett#else 1080215976Sjmallett uint64_t reserved_0_1 : 2; 1081215976Sjmallett uint64_t out_ovr : 1; 1082215976Sjmallett uint64_t reserved_3_21 : 19; 1083215976Sjmallett uint64_t loststat : 1; 1084215976Sjmallett uint64_t reserved_23_25 : 3; 1085215976Sjmallett uint64_t statovr : 1; 1086215976Sjmallett uint64_t reserved_27_31 : 5; 1087215976Sjmallett uint64_t ovrflw : 1; 1088215976Sjmallett uint64_t txpop : 1; 1089215976Sjmallett uint64_t txpsh : 1; 1090215976Sjmallett uint64_t reserved_35_63 : 29; 1091215976Sjmallett#endif 1092215976Sjmallett } cn56xx; 1093215976Sjmallett struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; 1094215976Sjmallett struct cvmx_agl_gmx_bad_reg_s cn63xx; 1095215976Sjmallett struct cvmx_agl_gmx_bad_reg_s cn63xxp1; 1096215976Sjmallett}; 1097215976Sjmalletttypedef union cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bad_reg_t; 1098215976Sjmallett 1099215976Sjmallett/** 1100215976Sjmallett * cvmx_agl_gmx_bist 1101215976Sjmallett * 1102215976Sjmallett * AGL_GMX_BIST = GMX BIST Results 1103215976Sjmallett * 1104215976Sjmallett * 1105215976Sjmallett * Notes: 1106215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1107215976Sjmallett * 1108215976Sjmallett */ 1109215976Sjmallettunion cvmx_agl_gmx_bist 1110215976Sjmallett{ 1111215976Sjmallett uint64_t u64; 1112215976Sjmallett struct cvmx_agl_gmx_bist_s 1113215976Sjmallett { 1114215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1115215976Sjmallett uint64_t reserved_25_63 : 39; 1116215976Sjmallett uint64_t status : 25; /**< BIST Results. 1117215976Sjmallett HW sets a bit in BIST for for memory that fails 1118215976Sjmallett - 0: gmx#.inb.fif_bnk0 1119215976Sjmallett - 1: gmx#.inb.fif_bnk1 1120215976Sjmallett - 2: gmx#.inb.fif_bnk2 1121215976Sjmallett - 3: gmx#.inb.fif_bnk3 1122215976Sjmallett - 4: gmx#.inb.fif_bnk_ext0 1123215976Sjmallett - 5: gmx#.inb.fif_bnk_ext1 1124215976Sjmallett - 6: gmx#.inb.fif_bnk_ext2 1125215976Sjmallett - 7: gmx#.inb.fif_bnk_ext3 1126215976Sjmallett - 8: gmx#.outb.fif.fif_bnk0 1127215976Sjmallett - 9: gmx#.outb.fif.fif_bnk1 1128215976Sjmallett - 10: RAZ 1129215976Sjmallett - 11: RAZ 1130215976Sjmallett - 12: gmx#.outb.fif.fif_bnk_ext0 1131215976Sjmallett - 13: gmx#.outb.fif.fif_bnk_ext1 1132215976Sjmallett - 14: RAZ 1133215976Sjmallett - 15: RAZ 1134215976Sjmallett - 16: gmx#.csr.gmi0.srf8x64m1_bist 1135215976Sjmallett - 17: gmx#.csr.gmi1.srf8x64m1_bist 1136215976Sjmallett - 18: RAZ 1137215976Sjmallett - 19: RAZ 1138215976Sjmallett - 20: gmx#.csr.drf20x32m2_bist 1139215976Sjmallett - 21: gmx#.csr.drf20x48m2_bist 1140215976Sjmallett - 22: gmx#.outb.stat.drf16x27m1_bist 1141215976Sjmallett - 23: gmx#.outb.stat.drf40x64m1_bist 1142215976Sjmallett - 24: RAZ */ 1143215976Sjmallett#else 1144215976Sjmallett uint64_t status : 25; 1145215976Sjmallett uint64_t reserved_25_63 : 39; 1146215976Sjmallett#endif 1147215976Sjmallett } s; 1148215976Sjmallett struct cvmx_agl_gmx_bist_cn52xx 1149215976Sjmallett { 1150215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1151215976Sjmallett uint64_t reserved_10_63 : 54; 1152215976Sjmallett uint64_t status : 10; /**< BIST Results. 1153215976Sjmallett HW sets a bit in BIST for for memory that fails 1154215976Sjmallett - 0: gmx#.inb.drf128x78m1_bist 1155215976Sjmallett - 1: gmx#.outb.fif.drf128x71m1_bist 1156215976Sjmallett - 2: gmx#.csr.gmi0.srf8x64m1_bist 1157215976Sjmallett - 3: gmx#.csr.gmi1.srf8x64m1_bist 1158215976Sjmallett - 4: 0 1159215976Sjmallett - 5: 0 1160215976Sjmallett - 6: gmx#.csr.drf20x80m1_bist 1161215976Sjmallett - 7: gmx#.outb.stat.drf16x27m1_bist 1162215976Sjmallett - 8: gmx#.outb.stat.drf40x64m1_bist 1163215976Sjmallett - 9: 0 */ 1164215976Sjmallett#else 1165215976Sjmallett uint64_t status : 10; 1166215976Sjmallett uint64_t reserved_10_63 : 54; 1167215976Sjmallett#endif 1168215976Sjmallett } cn52xx; 1169215976Sjmallett struct cvmx_agl_gmx_bist_cn52xx cn52xxp1; 1170215976Sjmallett struct cvmx_agl_gmx_bist_cn52xx cn56xx; 1171215976Sjmallett struct cvmx_agl_gmx_bist_cn52xx cn56xxp1; 1172215976Sjmallett struct cvmx_agl_gmx_bist_s cn63xx; 1173215976Sjmallett struct cvmx_agl_gmx_bist_s cn63xxp1; 1174215976Sjmallett}; 1175215976Sjmalletttypedef union cvmx_agl_gmx_bist cvmx_agl_gmx_bist_t; 1176215976Sjmallett 1177215976Sjmallett/** 1178215976Sjmallett * cvmx_agl_gmx_drv_ctl 1179215976Sjmallett * 1180215976Sjmallett * AGL_GMX_DRV_CTL = GMX Drive Control 1181215976Sjmallett * 1182215976Sjmallett * 1183215976Sjmallett * Notes: 1184215976Sjmallett * NCTL, PCTL, BYP_EN will be reset when MIX0_CTL[RESET] is set to 1. 1185215976Sjmallett * NCTL1, PCTL1, BYP_EN1 will be reset when MIX1_CTL[RESET] is set to 1. 1186215976Sjmallett */ 1187215976Sjmallettunion cvmx_agl_gmx_drv_ctl 1188215976Sjmallett{ 1189215976Sjmallett uint64_t u64; 1190215976Sjmallett struct cvmx_agl_gmx_drv_ctl_s 1191215976Sjmallett { 1192215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1193215976Sjmallett uint64_t reserved_49_63 : 15; 1194215976Sjmallett uint64_t byp_en1 : 1; /**< Compensation Controller Bypass Enable (MII1) */ 1195215976Sjmallett uint64_t reserved_45_47 : 3; 1196215976Sjmallett uint64_t pctl1 : 5; /**< AGL PCTL (MII1) */ 1197215976Sjmallett uint64_t reserved_37_39 : 3; 1198215976Sjmallett uint64_t nctl1 : 5; /**< AGL NCTL (MII1) */ 1199215976Sjmallett uint64_t reserved_17_31 : 15; 1200215976Sjmallett uint64_t byp_en : 1; /**< Compensation Controller Bypass Enable */ 1201215976Sjmallett uint64_t reserved_13_15 : 3; 1202215976Sjmallett uint64_t pctl : 5; /**< AGL PCTL */ 1203215976Sjmallett uint64_t reserved_5_7 : 3; 1204215976Sjmallett uint64_t nctl : 5; /**< AGL NCTL */ 1205215976Sjmallett#else 1206215976Sjmallett uint64_t nctl : 5; 1207215976Sjmallett uint64_t reserved_5_7 : 3; 1208215976Sjmallett uint64_t pctl : 5; 1209215976Sjmallett uint64_t reserved_13_15 : 3; 1210215976Sjmallett uint64_t byp_en : 1; 1211215976Sjmallett uint64_t reserved_17_31 : 15; 1212215976Sjmallett uint64_t nctl1 : 5; 1213215976Sjmallett uint64_t reserved_37_39 : 3; 1214215976Sjmallett uint64_t pctl1 : 5; 1215215976Sjmallett uint64_t reserved_45_47 : 3; 1216215976Sjmallett uint64_t byp_en1 : 1; 1217215976Sjmallett uint64_t reserved_49_63 : 15; 1218215976Sjmallett#endif 1219215976Sjmallett } s; 1220215976Sjmallett struct cvmx_agl_gmx_drv_ctl_s cn52xx; 1221215976Sjmallett struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; 1222215976Sjmallett struct cvmx_agl_gmx_drv_ctl_cn56xx 1223215976Sjmallett { 1224215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1225215976Sjmallett uint64_t reserved_17_63 : 47; 1226215976Sjmallett uint64_t byp_en : 1; /**< Compensation Controller Bypass Enable */ 1227215976Sjmallett uint64_t reserved_13_15 : 3; 1228215976Sjmallett uint64_t pctl : 5; /**< AGL PCTL */ 1229215976Sjmallett uint64_t reserved_5_7 : 3; 1230215976Sjmallett uint64_t nctl : 5; /**< AGL NCTL */ 1231215976Sjmallett#else 1232215976Sjmallett uint64_t nctl : 5; 1233215976Sjmallett uint64_t reserved_5_7 : 3; 1234215976Sjmallett uint64_t pctl : 5; 1235215976Sjmallett uint64_t reserved_13_15 : 3; 1236215976Sjmallett uint64_t byp_en : 1; 1237215976Sjmallett uint64_t reserved_17_63 : 47; 1238215976Sjmallett#endif 1239215976Sjmallett } cn56xx; 1240215976Sjmallett struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; 1241215976Sjmallett}; 1242215976Sjmalletttypedef union cvmx_agl_gmx_drv_ctl cvmx_agl_gmx_drv_ctl_t; 1243215976Sjmallett 1244215976Sjmallett/** 1245215976Sjmallett * cvmx_agl_gmx_inf_mode 1246215976Sjmallett * 1247215976Sjmallett * AGL_GMX_INF_MODE = Interface Mode 1248215976Sjmallett * 1249215976Sjmallett * 1250215976Sjmallett * Notes: 1251215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1252215976Sjmallett * 1253215976Sjmallett */ 1254215976Sjmallettunion cvmx_agl_gmx_inf_mode 1255215976Sjmallett{ 1256215976Sjmallett uint64_t u64; 1257215976Sjmallett struct cvmx_agl_gmx_inf_mode_s 1258215976Sjmallett { 1259215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1260215976Sjmallett uint64_t reserved_2_63 : 62; 1261215976Sjmallett uint64_t en : 1; /**< Interface Enable */ 1262215976Sjmallett uint64_t reserved_0_0 : 1; 1263215976Sjmallett#else 1264215976Sjmallett uint64_t reserved_0_0 : 1; 1265215976Sjmallett uint64_t en : 1; 1266215976Sjmallett uint64_t reserved_2_63 : 62; 1267215976Sjmallett#endif 1268215976Sjmallett } s; 1269215976Sjmallett struct cvmx_agl_gmx_inf_mode_s cn52xx; 1270215976Sjmallett struct cvmx_agl_gmx_inf_mode_s cn52xxp1; 1271215976Sjmallett struct cvmx_agl_gmx_inf_mode_s cn56xx; 1272215976Sjmallett struct cvmx_agl_gmx_inf_mode_s cn56xxp1; 1273215976Sjmallett}; 1274215976Sjmalletttypedef union cvmx_agl_gmx_inf_mode cvmx_agl_gmx_inf_mode_t; 1275215976Sjmallett 1276215976Sjmallett/** 1277215976Sjmallett * cvmx_agl_gmx_prt#_cfg 1278215976Sjmallett * 1279215976Sjmallett * AGL_GMX_PRT_CFG = Port description 1280215976Sjmallett * 1281215976Sjmallett * 1282215976Sjmallett * Notes: 1283215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1284215976Sjmallett * 1285215976Sjmallett */ 1286215976Sjmallettunion cvmx_agl_gmx_prtx_cfg 1287215976Sjmallett{ 1288215976Sjmallett uint64_t u64; 1289215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_s 1290215976Sjmallett { 1291215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1292215976Sjmallett uint64_t reserved_14_63 : 50; 1293215976Sjmallett uint64_t tx_idle : 1; /**< TX Machine is idle */ 1294215976Sjmallett uint64_t rx_idle : 1; /**< RX Machine is idle */ 1295215976Sjmallett uint64_t reserved_9_11 : 3; 1296215976Sjmallett uint64_t speed_msb : 1; /**< Link Speed MSB [SPEED_MSB:SPEED] 1297215976Sjmallett 10 = 10Mbs operation 1298215976Sjmallett 00 = 100Mbs operation 1299215976Sjmallett 01 = 1000Mbs operation 1300215976Sjmallett 11 = Reserved */ 1301215976Sjmallett uint64_t reserved_7_7 : 1; 1302215976Sjmallett uint64_t burst : 1; /**< Half-Duplex Burst Enable 1303215976Sjmallett Only valid for 1000Mbs half-duplex operation 1304215976Sjmallett 0 = burst length of 0x2000 (halfdup / 1000Mbs) 1305215976Sjmallett 1 = burst length of 0x0 (all other modes) */ 1306215976Sjmallett uint64_t tx_en : 1; /**< Port enable. Must be set for Octane to send 1307215976Sjmallett RMGII traffic. When this bit clear on a given 1308215976Sjmallett port, then all packet cycles will appear as 1309215976Sjmallett inter-frame cycles. */ 1310215976Sjmallett uint64_t rx_en : 1; /**< Port enable. Must be set for Octane to receive 1311215976Sjmallett RMGII traffic. When this bit clear on a given 1312215976Sjmallett port, then the all packet cycles will appear as 1313215976Sjmallett inter-frame cycles. */ 1314215976Sjmallett uint64_t slottime : 1; /**< Slot Time for Half-Duplex operation 1315215976Sjmallett 0 = 512 bitimes (10/100Mbs operation) 1316215976Sjmallett 1 = 4096 bitimes (1000Mbs operation) */ 1317215976Sjmallett uint64_t duplex : 1; /**< Duplex 1318215976Sjmallett 0 = Half Duplex (collisions/extentions/bursts) 1319215976Sjmallett 1 = Full Duplex */ 1320215976Sjmallett uint64_t speed : 1; /**< Link Speed LSB [SPEED_MSB:SPEED] 1321215976Sjmallett 10 = 10Mbs operation 1322215976Sjmallett 00 = 100Mbs operation 1323215976Sjmallett 01 = 1000Mbs operation 1324215976Sjmallett 11 = Reserved */ 1325215976Sjmallett uint64_t en : 1; /**< Link Enable 1326215976Sjmallett When EN is clear, packets will not be received 1327215976Sjmallett or transmitted (including PAUSE and JAM packets). 1328215976Sjmallett If EN is cleared while a packet is currently 1329215976Sjmallett being received or transmitted, the packet will 1330215976Sjmallett be allowed to complete before the bus is idled. 1331215976Sjmallett On the RX side, subsequent packets in a burst 1332215976Sjmallett will be ignored. */ 1333215976Sjmallett#else 1334215976Sjmallett uint64_t en : 1; 1335215976Sjmallett uint64_t speed : 1; 1336215976Sjmallett uint64_t duplex : 1; 1337215976Sjmallett uint64_t slottime : 1; 1338215976Sjmallett uint64_t rx_en : 1; 1339215976Sjmallett uint64_t tx_en : 1; 1340215976Sjmallett uint64_t burst : 1; 1341215976Sjmallett uint64_t reserved_7_7 : 1; 1342215976Sjmallett uint64_t speed_msb : 1; 1343215976Sjmallett uint64_t reserved_9_11 : 3; 1344215976Sjmallett uint64_t rx_idle : 1; 1345215976Sjmallett uint64_t tx_idle : 1; 1346215976Sjmallett uint64_t reserved_14_63 : 50; 1347215976Sjmallett#endif 1348215976Sjmallett } s; 1349215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_cn52xx 1350215976Sjmallett { 1351215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1352215976Sjmallett uint64_t reserved_6_63 : 58; 1353215976Sjmallett uint64_t tx_en : 1; /**< Port enable. Must be set for Octane to send 1354215976Sjmallett RMGII traffic. When this bit clear on a given 1355215976Sjmallett port, then all MII cycles will appear as 1356215976Sjmallett inter-frame cycles. */ 1357215976Sjmallett uint64_t rx_en : 1; /**< Port enable. Must be set for Octane to receive 1358215976Sjmallett RMGII traffic. When this bit clear on a given 1359215976Sjmallett port, then the all MII cycles will appear as 1360215976Sjmallett inter-frame cycles. */ 1361215976Sjmallett uint64_t slottime : 1; /**< Slot Time for Half-Duplex operation 1362215976Sjmallett 0 = 512 bitimes (10/100Mbs operation) 1363215976Sjmallett 1 = Reserved */ 1364215976Sjmallett uint64_t duplex : 1; /**< Duplex 1365215976Sjmallett 0 = Half Duplex (collisions/extentions/bursts) 1366215976Sjmallett 1 = Full Duplex */ 1367215976Sjmallett uint64_t speed : 1; /**< Link Speed 1368215976Sjmallett 0 = 10/100Mbs operation 1369215976Sjmallett 1 = Reserved */ 1370215976Sjmallett uint64_t en : 1; /**< Link Enable 1371215976Sjmallett When EN is clear, packets will not be received 1372215976Sjmallett or transmitted (including PAUSE and JAM packets). 1373215976Sjmallett If EN is cleared while a packet is currently 1374215976Sjmallett being received or transmitted, the packet will 1375215976Sjmallett be allowed to complete before the bus is idled. 1376215976Sjmallett On the RX side, subsequent packets in a burst 1377215976Sjmallett will be ignored. */ 1378215976Sjmallett#else 1379215976Sjmallett uint64_t en : 1; 1380215976Sjmallett uint64_t speed : 1; 1381215976Sjmallett uint64_t duplex : 1; 1382215976Sjmallett uint64_t slottime : 1; 1383215976Sjmallett uint64_t rx_en : 1; 1384215976Sjmallett uint64_t tx_en : 1; 1385215976Sjmallett uint64_t reserved_6_63 : 58; 1386215976Sjmallett#endif 1387215976Sjmallett } cn52xx; 1388215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1; 1389215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx; 1390215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1; 1391215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_s cn63xx; 1392215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1; 1393215976Sjmallett}; 1394215976Sjmalletttypedef union cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_prtx_cfg_t; 1395215976Sjmallett 1396215976Sjmallett/** 1397215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam0 1398215976Sjmallett * 1399215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1400215976Sjmallett * 1401215976Sjmallett * 1402215976Sjmallett * Notes: 1403215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1404215976Sjmallett * 1405215976Sjmallett */ 1406215976Sjmallettunion cvmx_agl_gmx_rxx_adr_cam0 1407215976Sjmallett{ 1408215976Sjmallett uint64_t u64; 1409215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s 1410215976Sjmallett { 1411215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1412215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1413215976Sjmallett Each entry contributes 8bits to one of 8 matchers 1414215976Sjmallett Write transactions to AGL_GMX_RX_ADR_CAM will not 1415215976Sjmallett change the CSR when AGL_GMX_PRT_CFG[EN] is enabled 1416215976Sjmallett The CAM matches against unicst or multicst DMAC 1417215976Sjmallett addresses. */ 1418215976Sjmallett#else 1419215976Sjmallett uint64_t adr : 64; 1420215976Sjmallett#endif 1421215976Sjmallett } s; 1422215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; 1423215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; 1424215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; 1425215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; 1426215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx; 1427215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1; 1428215976Sjmallett}; 1429215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam0_t; 1430215976Sjmallett 1431215976Sjmallett/** 1432215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam1 1433215976Sjmallett * 1434215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1435215976Sjmallett * 1436215976Sjmallett * 1437215976Sjmallett * Notes: 1438215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1439215976Sjmallett * 1440215976Sjmallett */ 1441215976Sjmallettunion cvmx_agl_gmx_rxx_adr_cam1 1442215976Sjmallett{ 1443215976Sjmallett uint64_t u64; 1444215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s 1445215976Sjmallett { 1446215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1447215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1448215976Sjmallett Each entry contributes 8bits to one of 8 matchers 1449215976Sjmallett Write transactions to AGL_GMX_RX_ADR_CAM will not 1450215976Sjmallett change the CSR when AGL_GMX_PRT_CFG[EN] is enabled 1451215976Sjmallett The CAM matches against unicst or multicst DMAC 1452215976Sjmallett addresses. */ 1453215976Sjmallett#else 1454215976Sjmallett uint64_t adr : 64; 1455215976Sjmallett#endif 1456215976Sjmallett } s; 1457215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; 1458215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; 1459215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; 1460215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; 1461215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx; 1462215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1; 1463215976Sjmallett}; 1464215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam1 cvmx_agl_gmx_rxx_adr_cam1_t; 1465215976Sjmallett 1466215976Sjmallett/** 1467215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam2 1468215976Sjmallett * 1469215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1470215976Sjmallett * 1471215976Sjmallett * 1472215976Sjmallett * Notes: 1473215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1474215976Sjmallett * 1475215976Sjmallett */ 1476215976Sjmallettunion cvmx_agl_gmx_rxx_adr_cam2 1477215976Sjmallett{ 1478215976Sjmallett uint64_t u64; 1479215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s 1480215976Sjmallett { 1481215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1482215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1483215976Sjmallett Each entry contributes 8bits to one of 8 matchers 1484215976Sjmallett Write transactions to AGL_GMX_RX_ADR_CAM will not 1485215976Sjmallett change the CSR when AGL_GMX_PRT_CFG[EN] is enabled 1486215976Sjmallett The CAM matches against unicst or multicst DMAC 1487215976Sjmallett addresses. */ 1488215976Sjmallett#else 1489215976Sjmallett uint64_t adr : 64; 1490215976Sjmallett#endif 1491215976Sjmallett } s; 1492215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; 1493215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; 1494215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; 1495215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; 1496215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx; 1497215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1; 1498215976Sjmallett}; 1499215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam2_t; 1500215976Sjmallett 1501215976Sjmallett/** 1502215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam3 1503215976Sjmallett * 1504215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1505215976Sjmallett * 1506215976Sjmallett * 1507215976Sjmallett * Notes: 1508215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1509215976Sjmallett * 1510215976Sjmallett */ 1511215976Sjmallettunion cvmx_agl_gmx_rxx_adr_cam3 1512215976Sjmallett{ 1513215976Sjmallett uint64_t u64; 1514215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s 1515215976Sjmallett { 1516215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1517215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1518215976Sjmallett Each entry contributes 8bits to one of 8 matchers 1519215976Sjmallett Write transactions to AGL_GMX_RX_ADR_CAM will not 1520215976Sjmallett change the CSR when AGL_GMX_PRT_CFG[EN] is enabled 1521215976Sjmallett The CAM matches against unicst or multicst DMAC 1522215976Sjmallett addresses. */ 1523215976Sjmallett#else 1524215976Sjmallett uint64_t adr : 64; 1525215976Sjmallett#endif 1526215976Sjmallett } s; 1527215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; 1528215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; 1529215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; 1530215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; 1531215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx; 1532215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1; 1533215976Sjmallett}; 1534215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam3_t; 1535215976Sjmallett 1536215976Sjmallett/** 1537215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam4 1538215976Sjmallett * 1539215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1540215976Sjmallett * 1541215976Sjmallett * 1542215976Sjmallett * Notes: 1543215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1544215976Sjmallett * 1545215976Sjmallett */ 1546215976Sjmallettunion cvmx_agl_gmx_rxx_adr_cam4 1547215976Sjmallett{ 1548215976Sjmallett uint64_t u64; 1549215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s 1550215976Sjmallett { 1551215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1552215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1553215976Sjmallett Each entry contributes 8bits to one of 8 matchers 1554215976Sjmallett Write transactions to AGL_GMX_RX_ADR_CAM will not 1555215976Sjmallett change the CSR when AGL_GMX_PRT_CFG[EN] is enabled 1556215976Sjmallett The CAM matches against unicst or multicst DMAC 1557215976Sjmallett addresses. */ 1558215976Sjmallett#else 1559215976Sjmallett uint64_t adr : 64; 1560215976Sjmallett#endif 1561215976Sjmallett } s; 1562215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; 1563215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; 1564215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; 1565215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; 1566215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx; 1567215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1; 1568215976Sjmallett}; 1569215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam4 cvmx_agl_gmx_rxx_adr_cam4_t; 1570215976Sjmallett 1571215976Sjmallett/** 1572215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam5 1573215976Sjmallett * 1574215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1575215976Sjmallett * 1576215976Sjmallett * 1577215976Sjmallett * Notes: 1578215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1579215976Sjmallett * 1580215976Sjmallett */ 1581215976Sjmallettunion cvmx_agl_gmx_rxx_adr_cam5 1582215976Sjmallett{ 1583215976Sjmallett uint64_t u64; 1584215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s 1585215976Sjmallett { 1586215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1587215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1588215976Sjmallett Each entry contributes 8bits to one of 8 matchers 1589215976Sjmallett Write transactions to AGL_GMX_RX_ADR_CAM will not 1590215976Sjmallett change the CSR when AGL_GMX_PRT_CFG[EN] is enabled 1591215976Sjmallett The CAM matches against unicst or multicst DMAC 1592215976Sjmallett addresses. */ 1593215976Sjmallett#else 1594215976Sjmallett uint64_t adr : 64; 1595215976Sjmallett#endif 1596215976Sjmallett } s; 1597215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; 1598215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; 1599215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; 1600215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; 1601215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx; 1602215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1; 1603215976Sjmallett}; 1604215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam5_t; 1605215976Sjmallett 1606215976Sjmallett/** 1607215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam_en 1608215976Sjmallett * 1609215976Sjmallett * AGL_GMX_RX_ADR_CAM_EN = Address Filtering Control Enable 1610215976Sjmallett * 1611215976Sjmallett * 1612215976Sjmallett * Notes: 1613215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1614215976Sjmallett * 1615215976Sjmallett */ 1616215976Sjmallettunion cvmx_agl_gmx_rxx_adr_cam_en 1617215976Sjmallett{ 1618215976Sjmallett uint64_t u64; 1619215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s 1620215976Sjmallett { 1621215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1622215976Sjmallett uint64_t reserved_8_63 : 56; 1623215976Sjmallett uint64_t en : 8; /**< CAM Entry Enables */ 1624215976Sjmallett#else 1625215976Sjmallett uint64_t en : 8; 1626215976Sjmallett uint64_t reserved_8_63 : 56; 1627215976Sjmallett#endif 1628215976Sjmallett } s; 1629215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; 1630215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; 1631215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; 1632215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; 1633215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx; 1634215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1; 1635215976Sjmallett}; 1636215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_cam_en_t; 1637215976Sjmallett 1638215976Sjmallett/** 1639215976Sjmallett * cvmx_agl_gmx_rx#_adr_ctl 1640215976Sjmallett * 1641215976Sjmallett * AGL_GMX_RX_ADR_CTL = Address Filtering Control 1642215976Sjmallett * 1643215976Sjmallett * 1644215976Sjmallett * Notes: 1645215976Sjmallett * * ALGORITHM 1646215976Sjmallett * Here is some pseudo code that represents the address filter behavior. 1647215976Sjmallett * 1648215976Sjmallett * @verbatim 1649215976Sjmallett * bool dmac_addr_filter(uint8 prt, uint48 dmac) [ 1650215976Sjmallett * ASSERT(prt >= 0 && prt <= 3); 1651215976Sjmallett * if (is_bcst(dmac)) // broadcast accept 1652215976Sjmallett * return (AGL_GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT); 1653215976Sjmallett * if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 1) // multicast reject 1654215976Sjmallett * return REJECT; 1655215976Sjmallett * if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 2) // multicast accept 1656215976Sjmallett * return ACCEPT; 1657215976Sjmallett * 1658215976Sjmallett * cam_hit = 0; 1659215976Sjmallett * 1660215976Sjmallett * for (i=0; i<8; i++) [ 1661215976Sjmallett * if (AGL_GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0) 1662215976Sjmallett * continue; 1663215976Sjmallett * uint48 unswizzled_mac_adr = 0x0; 1664215976Sjmallett * for (j=5; j>=0; j--) [ 1665215976Sjmallett * unswizzled_mac_adr = (unswizzled_mac_adr << 8) | AGL_GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>]; 1666215976Sjmallett * ] 1667215976Sjmallett * if (unswizzled_mac_adr == dmac) [ 1668215976Sjmallett * cam_hit = 1; 1669215976Sjmallett * break; 1670215976Sjmallett * ] 1671215976Sjmallett * ] 1672215976Sjmallett * 1673215976Sjmallett * if (cam_hit) 1674215976Sjmallett * return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT); 1675215976Sjmallett * else 1676215976Sjmallett * return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT); 1677215976Sjmallett * ] 1678215976Sjmallett * @endverbatim 1679215976Sjmallett * 1680215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1681215976Sjmallett */ 1682215976Sjmallettunion cvmx_agl_gmx_rxx_adr_ctl 1683215976Sjmallett{ 1684215976Sjmallett uint64_t u64; 1685215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s 1686215976Sjmallett { 1687215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1688215976Sjmallett uint64_t reserved_4_63 : 60; 1689215976Sjmallett uint64_t cam_mode : 1; /**< Allow or deny DMAC address filter 1690215976Sjmallett 0 = reject the packet on DMAC address match 1691215976Sjmallett 1 = accept the packet on DMAC address match */ 1692215976Sjmallett uint64_t mcst : 2; /**< Multicast Mode 1693215976Sjmallett 0 = Use the Address Filter CAM 1694215976Sjmallett 1 = Force reject all multicast packets 1695215976Sjmallett 2 = Force accept all multicast packets 1696215976Sjmallett 3 = Reserved */ 1697215976Sjmallett uint64_t bcst : 1; /**< Accept All Broadcast Packets */ 1698215976Sjmallett#else 1699215976Sjmallett uint64_t bcst : 1; 1700215976Sjmallett uint64_t mcst : 2; 1701215976Sjmallett uint64_t cam_mode : 1; 1702215976Sjmallett uint64_t reserved_4_63 : 60; 1703215976Sjmallett#endif 1704215976Sjmallett } s; 1705215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; 1706215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; 1707215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; 1708215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; 1709215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx; 1710215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1; 1711215976Sjmallett}; 1712215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_ctl cvmx_agl_gmx_rxx_adr_ctl_t; 1713215976Sjmallett 1714215976Sjmallett/** 1715215976Sjmallett * cvmx_agl_gmx_rx#_decision 1716215976Sjmallett * 1717215976Sjmallett * AGL_GMX_RX_DECISION = The byte count to decide when to accept or filter a packet 1718215976Sjmallett * 1719215976Sjmallett * 1720215976Sjmallett * Notes: 1721215976Sjmallett * As each byte in a packet is received by GMX, the L2 byte count is compared 1722215976Sjmallett * against the AGL_GMX_RX_DECISION[CNT]. The L2 byte count is the number of bytes 1723215976Sjmallett * from the beginning of the L2 header (DMAC). In normal operation, the L2 1724215976Sjmallett * header begins after the PREAMBLE+SFD (AGL_GMX_RX_FRM_CTL[PRE_CHK]=1) and any 1725215976Sjmallett * optional UDD skip data (AGL_GMX_RX_UDD_SKP[LEN]). 1726215976Sjmallett * 1727215976Sjmallett * When AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the 1728215976Sjmallett * packet and would require UDD skip length to account for them. 1729215976Sjmallett * 1730215976Sjmallett * L2 Size 1731215976Sjmallett * Port Mode <=AGL_GMX_RX_DECISION bytes (default=24) >AGL_GMX_RX_DECISION bytes (default=24) 1732215976Sjmallett * 1733215976Sjmallett * MII/Full Duplex accept packet apply filters 1734215976Sjmallett * no filtering is applied accept packet based on DMAC and PAUSE packet filters 1735215976Sjmallett * 1736215976Sjmallett * MII/Half Duplex drop packet apply filters 1737215976Sjmallett * packet is unconditionally dropped accept packet based on DMAC 1738215976Sjmallett * 1739215976Sjmallett * where l2_size = MAX(0, total_packet_size - AGL_GMX_RX_UDD_SKP[LEN] - ((AGL_GMX_RX_FRM_CTL[PRE_CHK]==1)*8) 1740215976Sjmallett * 1741215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1742215976Sjmallett */ 1743215976Sjmallettunion cvmx_agl_gmx_rxx_decision 1744215976Sjmallett{ 1745215976Sjmallett uint64_t u64; 1746215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s 1747215976Sjmallett { 1748215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1749215976Sjmallett uint64_t reserved_5_63 : 59; 1750215976Sjmallett uint64_t cnt : 5; /**< The byte count to decide when to accept or filter 1751215976Sjmallett a packet. */ 1752215976Sjmallett#else 1753215976Sjmallett uint64_t cnt : 5; 1754215976Sjmallett uint64_t reserved_5_63 : 59; 1755215976Sjmallett#endif 1756215976Sjmallett } s; 1757215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn52xx; 1758215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; 1759215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn56xx; 1760215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; 1761215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn63xx; 1762215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn63xxp1; 1763215976Sjmallett}; 1764215976Sjmalletttypedef union cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_decision_t; 1765215976Sjmallett 1766215976Sjmallett/** 1767215976Sjmallett * cvmx_agl_gmx_rx#_frm_chk 1768215976Sjmallett * 1769215976Sjmallett * AGL_GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame 1770215976Sjmallett * 1771215976Sjmallett * 1772215976Sjmallett * Notes: 1773215976Sjmallett * If AGL_GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW. 1774215976Sjmallett * 1775215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1776215976Sjmallett */ 1777215976Sjmallettunion cvmx_agl_gmx_rxx_frm_chk 1778215976Sjmallett{ 1779215976Sjmallett uint64_t u64; 1780215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s 1781215976Sjmallett { 1782215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1783215976Sjmallett uint64_t reserved_10_63 : 54; 1784215976Sjmallett uint64_t niberr : 1; /**< Nibble error */ 1785215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 1786215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with packet data reception error */ 1787215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 1788215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 1789215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 1790215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 1791215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1792215976Sjmallett uint64_t carext : 1; /**< Carrier extend error */ 1793215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1794215976Sjmallett#else 1795215976Sjmallett uint64_t minerr : 1; 1796215976Sjmallett uint64_t carext : 1; 1797215976Sjmallett uint64_t maxerr : 1; 1798215976Sjmallett uint64_t jabber : 1; 1799215976Sjmallett uint64_t fcserr : 1; 1800215976Sjmallett uint64_t alnerr : 1; 1801215976Sjmallett uint64_t lenerr : 1; 1802215976Sjmallett uint64_t rcverr : 1; 1803215976Sjmallett uint64_t skperr : 1; 1804215976Sjmallett uint64_t niberr : 1; 1805215976Sjmallett uint64_t reserved_10_63 : 54; 1806215976Sjmallett#endif 1807215976Sjmallett } s; 1808215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_cn52xx 1809215976Sjmallett { 1810215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1811215976Sjmallett uint64_t reserved_9_63 : 55; 1812215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 1813215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with MII Data reception error */ 1814215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 1815215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 1816215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 1817215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 1818215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1819215976Sjmallett uint64_t reserved_1_1 : 1; 1820215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1821215976Sjmallett#else 1822215976Sjmallett uint64_t minerr : 1; 1823215976Sjmallett uint64_t reserved_1_1 : 1; 1824215976Sjmallett uint64_t maxerr : 1; 1825215976Sjmallett uint64_t jabber : 1; 1826215976Sjmallett uint64_t fcserr : 1; 1827215976Sjmallett uint64_t alnerr : 1; 1828215976Sjmallett uint64_t lenerr : 1; 1829215976Sjmallett uint64_t rcverr : 1; 1830215976Sjmallett uint64_t skperr : 1; 1831215976Sjmallett uint64_t reserved_9_63 : 55; 1832215976Sjmallett#endif 1833215976Sjmallett } cn52xx; 1834215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1; 1835215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx; 1836215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1; 1837215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx; 1838215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1; 1839215976Sjmallett}; 1840215976Sjmalletttypedef union cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_chk_t; 1841215976Sjmallett 1842215976Sjmallett/** 1843215976Sjmallett * cvmx_agl_gmx_rx#_frm_ctl 1844215976Sjmallett * 1845215976Sjmallett * AGL_GMX_RX_FRM_CTL = Frame Control 1846215976Sjmallett * 1847215976Sjmallett * 1848215976Sjmallett * Notes: 1849215976Sjmallett * * PRE_STRP 1850215976Sjmallett * When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP 1851215976Sjmallett * determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane 1852215976Sjmallett * core as part of the packet. 1853215976Sjmallett * 1854215976Sjmallett * In either mode, the PREAMBLE+SFD bytes are not counted toward the packet 1855215976Sjmallett * size when checking against the MIN and MAX bounds. Furthermore, the bytes 1856215976Sjmallett * are skipped when locating the start of the L2 header for DMAC and Control 1857215976Sjmallett * frame recognition. 1858215976Sjmallett * 1859215976Sjmallett * * CTL_BCK/CTL_DRP 1860215976Sjmallett * These bits control how the HW handles incoming PAUSE packets. Here are 1861215976Sjmallett * the most common modes of operation: 1862215976Sjmallett * CTL_BCK=1,CTL_DRP=1 - HW does it all 1863215976Sjmallett * CTL_BCK=0,CTL_DRP=0 - SW sees all pause frames 1864215976Sjmallett * CTL_BCK=0,CTL_DRP=1 - all pause frames are completely ignored 1865215976Sjmallett * 1866215976Sjmallett * These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode. 1867215976Sjmallett * Since PAUSE packets only apply to fulldup operation, any PAUSE packet 1868215976Sjmallett * would constitute an exception which should be handled by the processing 1869215976Sjmallett * cores. PAUSE packets should not be forwarded. 1870215976Sjmallett * 1871215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1872215976Sjmallett */ 1873215976Sjmallettunion cvmx_agl_gmx_rxx_frm_ctl 1874215976Sjmallett{ 1875215976Sjmallett uint64_t u64; 1876215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s 1877215976Sjmallett { 1878215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1879215976Sjmallett uint64_t reserved_13_63 : 51; 1880215976Sjmallett uint64_t ptp_mode : 1; /**< Timestamp mode 1881215976Sjmallett When PTP_MODE is set, a 64-bit timestamp will be 1882215976Sjmallett prepended to every incoming packet. The timestamp 1883215976Sjmallett bytes are added to the packet in such a way as to 1884215976Sjmallett not modify the packet's receive byte count. This 1885215976Sjmallett implies that the AGL_GMX_RX_JABBER, 1886215976Sjmallett AGL_GMX_RX_FRM_MIN, AGL_GMX_RX_FRM_MAX, 1887215976Sjmallett AGL_GMX_RX_DECISION, AGL_GMX_RX_UDD_SKP, and the 1888215976Sjmallett AGL_GMX_RX_STATS_* do not require any adjustment 1889215976Sjmallett as they operate on the received packet size. 1890215976Sjmallett If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */ 1891215976Sjmallett uint64_t reserved_11_11 : 1; 1892215976Sjmallett uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks 1893215976Sjmallett due to PARITAL packets */ 1894215976Sjmallett uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte 1895215976Sjmallett regardless of the number of previous PREAMBLE 1896215976Sjmallett nibbles. In this mode, PRE_STRP should be set to 1897215976Sjmallett account for the variable nature of the PREAMBLE. 1898215976Sjmallett PRE_CHK must be set to enable this and all 1899215976Sjmallett PREAMBLE features. */ 1900215976Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for non-min 1901215976Sjmallett sized pkts with padding in the client data */ 1902215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 1903215976Sjmallett uint64_t pre_free : 1; /**< When set, PREAMBLE checking is less strict. 1904215976Sjmallett AGL will begin the frame at the first SFD. 1905215976Sjmallett PRE_FREE must be set if PRE_ALIGN is set. 1906215976Sjmallett PRE_CHK must be set to enable this and all 1907215976Sjmallett PREAMBLE features. */ 1908215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 1909215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 1910215976Sjmallett Multicast address */ 1911215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 1912215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 1913215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 1914215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 1915215976Sjmallett 1=PREAMBLE+SFD is dropped 1916215976Sjmallett PRE_STRP must be set if PRE_ALIGN is set. 1917215976Sjmallett PRE_CHK must be set to enable this and all 1918215976Sjmallett PREAMBLE features. */ 1919215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send a valid 802.3 1920215976Sjmallett PREAMBLE to begin every frame. AGL checks that a 1921215976Sjmallett valid PREAMBLE is received (based on PRE_FREE). 1922215976Sjmallett When a problem does occur within the PREAMBLE 1923215976Sjmallett seqeunce, the frame is marked as bad and not sent 1924215976Sjmallett into the core. The AGL_GMX_RX_INT_REG[PCTERR] 1925215976Sjmallett interrupt is also raised. */ 1926215976Sjmallett#else 1927215976Sjmallett uint64_t pre_chk : 1; 1928215976Sjmallett uint64_t pre_strp : 1; 1929215976Sjmallett uint64_t ctl_drp : 1; 1930215976Sjmallett uint64_t ctl_bck : 1; 1931215976Sjmallett uint64_t ctl_mcst : 1; 1932215976Sjmallett uint64_t ctl_smac : 1; 1933215976Sjmallett uint64_t pre_free : 1; 1934215976Sjmallett uint64_t vlan_len : 1; 1935215976Sjmallett uint64_t pad_len : 1; 1936215976Sjmallett uint64_t pre_align : 1; 1937215976Sjmallett uint64_t null_dis : 1; 1938215976Sjmallett uint64_t reserved_11_11 : 1; 1939215976Sjmallett uint64_t ptp_mode : 1; 1940215976Sjmallett uint64_t reserved_13_63 : 51; 1941215976Sjmallett#endif 1942215976Sjmallett } s; 1943215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx 1944215976Sjmallett { 1945215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1946215976Sjmallett uint64_t reserved_10_63 : 54; 1947215976Sjmallett uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte 1948215976Sjmallett regardless of the number of previous PREAMBLE 1949215976Sjmallett nibbles. In this mode, PREAMBLE can be consumed 1950215976Sjmallett by the HW so when PRE_ALIGN is set, PRE_FREE, 1951215976Sjmallett PRE_STRP must be set for correct operation. 1952215976Sjmallett PRE_CHK must be set to enable this and all 1953215976Sjmallett PREAMBLE features. */ 1954215976Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for non-min 1955215976Sjmallett sized pkts with padding in the client data */ 1956215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 1957215976Sjmallett uint64_t pre_free : 1; /**< When set, PREAMBLE checking is less strict. 1958215976Sjmallett 0 - 254 cycles of PREAMBLE followed by SFD 1959215976Sjmallett PRE_FREE must be set if PRE_ALIGN is set. 1960215976Sjmallett PRE_CHK must be set to enable this and all 1961215976Sjmallett PREAMBLE features. */ 1962215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 1963215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 1964215976Sjmallett Multicast address */ 1965215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 1966215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 1967215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 1968215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 1969215976Sjmallett 1=PREAMBLE+SFD is dropped 1970215976Sjmallett PRE_STRP must be set if PRE_ALIGN is set. 1971215976Sjmallett PRE_CHK must be set to enable this and all 1972215976Sjmallett PREAMBLE features. */ 1973215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send PREAMBLE+SFD 1974215976Sjmallett to begin every frame. GMX checks that the 1975215976Sjmallett PREAMBLE is sent correctly */ 1976215976Sjmallett#else 1977215976Sjmallett uint64_t pre_chk : 1; 1978215976Sjmallett uint64_t pre_strp : 1; 1979215976Sjmallett uint64_t ctl_drp : 1; 1980215976Sjmallett uint64_t ctl_bck : 1; 1981215976Sjmallett uint64_t ctl_mcst : 1; 1982215976Sjmallett uint64_t ctl_smac : 1; 1983215976Sjmallett uint64_t pre_free : 1; 1984215976Sjmallett uint64_t vlan_len : 1; 1985215976Sjmallett uint64_t pad_len : 1; 1986215976Sjmallett uint64_t pre_align : 1; 1987215976Sjmallett uint64_t reserved_10_63 : 54; 1988215976Sjmallett#endif 1989215976Sjmallett } cn52xx; 1990215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1; 1991215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx; 1992215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1; 1993215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx; 1994215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1; 1995215976Sjmallett}; 1996215976Sjmalletttypedef union cvmx_agl_gmx_rxx_frm_ctl cvmx_agl_gmx_rxx_frm_ctl_t; 1997215976Sjmallett 1998215976Sjmallett/** 1999215976Sjmallett * cvmx_agl_gmx_rx#_frm_max 2000215976Sjmallett * 2001215976Sjmallett * AGL_GMX_RX_FRM_MAX = Frame Max length 2002215976Sjmallett * 2003215976Sjmallett * 2004215976Sjmallett * Notes: 2005215976Sjmallett * When changing the LEN field, be sure that LEN does not exceed 2006215976Sjmallett * AGL_GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that 2007215976Sjmallett * are within the maximum length parameter to be rejected because they exceed 2008215976Sjmallett * the AGL_GMX_RX_JABBER[CNT] limit. 2009215976Sjmallett * 2010215976Sjmallett * Notes: 2011215976Sjmallett * 2012215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2013215976Sjmallett */ 2014215976Sjmallettunion cvmx_agl_gmx_rxx_frm_max 2015215976Sjmallett{ 2016215976Sjmallett uint64_t u64; 2017215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s 2018215976Sjmallett { 2019215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2020215976Sjmallett uint64_t reserved_16_63 : 48; 2021215976Sjmallett uint64_t len : 16; /**< Byte count for Max-sized frame check 2022215976Sjmallett AGL_GMX_RXn_FRM_CHK[MAXERR] enables the check 2023215976Sjmallett for port n. 2024215976Sjmallett If enabled, failing packets set the MAXERR 2025215976Sjmallett interrupt and the MIX opcode is set to OVER_FCS 2026215976Sjmallett (0x3, if packet has bad FCS) or OVER_ERR (0x4, if 2027215976Sjmallett packet has good FCS). 2028215976Sjmallett LEN <= AGL_GMX_RX_JABBER[CNT] */ 2029215976Sjmallett#else 2030215976Sjmallett uint64_t len : 16; 2031215976Sjmallett uint64_t reserved_16_63 : 48; 2032215976Sjmallett#endif 2033215976Sjmallett } s; 2034215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; 2035215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; 2036215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; 2037215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; 2038215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn63xx; 2039215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1; 2040215976Sjmallett}; 2041215976Sjmalletttypedef union cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_max_t; 2042215976Sjmallett 2043215976Sjmallett/** 2044215976Sjmallett * cvmx_agl_gmx_rx#_frm_min 2045215976Sjmallett * 2046215976Sjmallett * AGL_GMX_RX_FRM_MIN = Frame Min length 2047215976Sjmallett * 2048215976Sjmallett * 2049215976Sjmallett * Notes: 2050215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2051215976Sjmallett * 2052215976Sjmallett */ 2053215976Sjmallettunion cvmx_agl_gmx_rxx_frm_min 2054215976Sjmallett{ 2055215976Sjmallett uint64_t u64; 2056215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s 2057215976Sjmallett { 2058215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2059215976Sjmallett uint64_t reserved_16_63 : 48; 2060215976Sjmallett uint64_t len : 16; /**< Byte count for Min-sized frame check 2061215976Sjmallett AGL_GMX_RXn_FRM_CHK[MINERR] enables the check 2062215976Sjmallett for port n. 2063215976Sjmallett If enabled, failing packets set the MINERR 2064215976Sjmallett interrupt and the MIX opcode is set to UNDER_FCS 2065215976Sjmallett (0x6, if packet has bad FCS) or UNDER_ERR (0x8, 2066215976Sjmallett if packet has good FCS). */ 2067215976Sjmallett#else 2068215976Sjmallett uint64_t len : 16; 2069215976Sjmallett uint64_t reserved_16_63 : 48; 2070215976Sjmallett#endif 2071215976Sjmallett } s; 2072215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; 2073215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; 2074215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; 2075215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; 2076215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn63xx; 2077215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1; 2078215976Sjmallett}; 2079215976Sjmalletttypedef union cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_frm_min_t; 2080215976Sjmallett 2081215976Sjmallett/** 2082215976Sjmallett * cvmx_agl_gmx_rx#_ifg 2083215976Sjmallett * 2084215976Sjmallett * AGL_GMX_RX_IFG = RX Min IFG 2085215976Sjmallett * 2086215976Sjmallett * 2087215976Sjmallett * Notes: 2088215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2089215976Sjmallett * 2090215976Sjmallett */ 2091215976Sjmallettunion cvmx_agl_gmx_rxx_ifg 2092215976Sjmallett{ 2093215976Sjmallett uint64_t u64; 2094215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s 2095215976Sjmallett { 2096215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2097215976Sjmallett uint64_t reserved_4_63 : 60; 2098215976Sjmallett uint64_t ifg : 4; /**< Min IFG (in IFG*8 bits) between packets used to 2099215976Sjmallett determine IFGERR. Normally IFG is 96 bits. 2100215976Sjmallett Note in some operating modes, IFG cycles can be 2101215976Sjmallett inserted or removed in order to achieve clock rate 2102215976Sjmallett adaptation. For these reasons, the default value 2103215976Sjmallett is slightly conservative and does not check upto 2104215976Sjmallett the full 96 bits of IFG. */ 2105215976Sjmallett#else 2106215976Sjmallett uint64_t ifg : 4; 2107215976Sjmallett uint64_t reserved_4_63 : 60; 2108215976Sjmallett#endif 2109215976Sjmallett } s; 2110215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn52xx; 2111215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; 2112215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn56xx; 2113215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; 2114215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn63xx; 2115215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1; 2116215976Sjmallett}; 2117215976Sjmalletttypedef union cvmx_agl_gmx_rxx_ifg cvmx_agl_gmx_rxx_ifg_t; 2118215976Sjmallett 2119215976Sjmallett/** 2120215976Sjmallett * cvmx_agl_gmx_rx#_int_en 2121215976Sjmallett * 2122215976Sjmallett * AGL_GMX_RX_INT_EN = Interrupt Enable 2123215976Sjmallett * 2124215976Sjmallett * 2125215976Sjmallett * Notes: 2126215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2127215976Sjmallett * 2128215976Sjmallett */ 2129215976Sjmallettunion cvmx_agl_gmx_rxx_int_en 2130215976Sjmallett{ 2131215976Sjmallett uint64_t u64; 2132215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_s 2133215976Sjmallett { 2134215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2135215976Sjmallett uint64_t reserved_20_63 : 44; 2136215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 2137215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex | NS */ 2138215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed | NS */ 2139215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus | NS */ 2140215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation */ 2141215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 2142215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 2143215976Sjmallett uint64_t rsverr : 1; /**< Packet reserved opcodes */ 2144215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 2145215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow */ 2146215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) | NS */ 2147215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 2148215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 2149215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2150215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 2151215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 2152215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 2153215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2154215976Sjmallett uint64_t carext : 1; /**< Carrier extend error */ 2155215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2156215976Sjmallett#else 2157215976Sjmallett uint64_t minerr : 1; 2158215976Sjmallett uint64_t carext : 1; 2159215976Sjmallett uint64_t maxerr : 1; 2160215976Sjmallett uint64_t jabber : 1; 2161215976Sjmallett uint64_t fcserr : 1; 2162215976Sjmallett uint64_t alnerr : 1; 2163215976Sjmallett uint64_t lenerr : 1; 2164215976Sjmallett uint64_t rcverr : 1; 2165215976Sjmallett uint64_t skperr : 1; 2166215976Sjmallett uint64_t niberr : 1; 2167215976Sjmallett uint64_t ovrerr : 1; 2168215976Sjmallett uint64_t pcterr : 1; 2169215976Sjmallett uint64_t rsverr : 1; 2170215976Sjmallett uint64_t falerr : 1; 2171215976Sjmallett uint64_t coldet : 1; 2172215976Sjmallett uint64_t ifgerr : 1; 2173215976Sjmallett uint64_t phy_link : 1; 2174215976Sjmallett uint64_t phy_spd : 1; 2175215976Sjmallett uint64_t phy_dupx : 1; 2176215976Sjmallett uint64_t pause_drp : 1; 2177215976Sjmallett uint64_t reserved_20_63 : 44; 2178215976Sjmallett#endif 2179215976Sjmallett } s; 2180215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_cn52xx 2181215976Sjmallett { 2182215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2183215976Sjmallett uint64_t reserved_20_63 : 44; 2184215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 2185215976Sjmallett uint64_t reserved_16_18 : 3; 2186215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation */ 2187215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 2188215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 2189215976Sjmallett uint64_t rsverr : 1; /**< MII reserved opcodes */ 2190215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 2191215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow */ 2192215976Sjmallett uint64_t reserved_9_9 : 1; 2193215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 2194215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 2195215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2196215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 2197215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 2198215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 2199215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2200215976Sjmallett uint64_t reserved_1_1 : 1; 2201215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2202215976Sjmallett#else 2203215976Sjmallett uint64_t minerr : 1; 2204215976Sjmallett uint64_t reserved_1_1 : 1; 2205215976Sjmallett uint64_t maxerr : 1; 2206215976Sjmallett uint64_t jabber : 1; 2207215976Sjmallett uint64_t fcserr : 1; 2208215976Sjmallett uint64_t alnerr : 1; 2209215976Sjmallett uint64_t lenerr : 1; 2210215976Sjmallett uint64_t rcverr : 1; 2211215976Sjmallett uint64_t skperr : 1; 2212215976Sjmallett uint64_t reserved_9_9 : 1; 2213215976Sjmallett uint64_t ovrerr : 1; 2214215976Sjmallett uint64_t pcterr : 1; 2215215976Sjmallett uint64_t rsverr : 1; 2216215976Sjmallett uint64_t falerr : 1; 2217215976Sjmallett uint64_t coldet : 1; 2218215976Sjmallett uint64_t ifgerr : 1; 2219215976Sjmallett uint64_t reserved_16_18 : 3; 2220215976Sjmallett uint64_t pause_drp : 1; 2221215976Sjmallett uint64_t reserved_20_63 : 44; 2222215976Sjmallett#endif 2223215976Sjmallett } cn52xx; 2224215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1; 2225215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx; 2226215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1; 2227215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_s cn63xx; 2228215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1; 2229215976Sjmallett}; 2230215976Sjmalletttypedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t; 2231215976Sjmallett 2232215976Sjmallett/** 2233215976Sjmallett * cvmx_agl_gmx_rx#_int_reg 2234215976Sjmallett * 2235215976Sjmallett * AGL_GMX_RX_INT_REG = Interrupt Register 2236215976Sjmallett * 2237215976Sjmallett * 2238215976Sjmallett * Notes: 2239215976Sjmallett * (1) exceptions will only be raised to the control processor if the 2240215976Sjmallett * corresponding bit in the AGL_GMX_RX_INT_EN register is set. 2241215976Sjmallett * 2242215976Sjmallett * (2) exception conditions 10:0 can also set the rcv/opcode in the received 2243215976Sjmallett * packet's workQ entry. The AGL_GMX_RX_FRM_CHK register provides a bit mask 2244215976Sjmallett * for configuring which conditions set the error. 2245215976Sjmallett * 2246215976Sjmallett * (3) in half duplex operation, the expectation is that collisions will appear 2247215976Sjmallett * as MINERRs. 2248215976Sjmallett * 2249215976Sjmallett * (4) JABBER - An RX Jabber error indicates that a packet was received which 2250215976Sjmallett * is longer than the maximum allowed packet as defined by the 2251215976Sjmallett * system. GMX will truncate the packet at the JABBER count. 2252215976Sjmallett * Failure to do so could lead to system instabilty. 2253215976Sjmallett * 2254215976Sjmallett * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS > 2255215976Sjmallett * AGL_GMX_RX_FRM_MAX. For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS 2256215976Sjmallett * > AGL_GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED. 2257215976Sjmallett * 2258215976Sjmallett * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < AGL_GMX_RX_FRM_MIN. 2259215976Sjmallett * 2260215976Sjmallett * (8) ALNERR - Indicates that the packet received was not an integer number of 2261215976Sjmallett * bytes. If FCS checking is enabled, ALNERR will only assert if 2262215976Sjmallett * the FCS is bad. If FCS checking is disabled, ALNERR will 2263215976Sjmallett * assert in all non-integer frame cases. 2264215976Sjmallett * 2265215976Sjmallett * (9) Collisions - Collisions can only occur in half-duplex mode. A collision 2266215976Sjmallett * is assumed by the receiver when the received 2267215976Sjmallett * frame < AGL_GMX_RX_FRM_MIN - this is normally a MINERR 2268215976Sjmallett * 2269215976Sjmallett * (A) LENERR - Length errors occur when the received packet does not match the 2270215976Sjmallett * length field. LENERR is only checked for packets between 64 2271215976Sjmallett * and 1500 bytes. For untagged frames, the length must exact 2272215976Sjmallett * match. For tagged frames the length or length+4 must match. 2273215976Sjmallett * 2274215976Sjmallett * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence. 2275215976Sjmallett * Does not check the number of PREAMBLE cycles. 2276215976Sjmallett * 2277215976Sjmallett * (C) OVRERR - Not to be included in the HRM 2278215976Sjmallett * 2279215976Sjmallett * OVRERR is an architectural assertion check internal to GMX to 2280215976Sjmallett * make sure no assumption was violated. In a correctly operating 2281215976Sjmallett * system, this interrupt can never fire. 2282215976Sjmallett * 2283215976Sjmallett * GMX has an internal arbiter which selects which of 4 ports to 2284215976Sjmallett * buffer in the main RX FIFO. If we normally buffer 8 bytes, 2285215976Sjmallett * then each port will typically push a tick every 8 cycles - if 2286215976Sjmallett * the packet interface is going as fast as possible. If there 2287215976Sjmallett * are four ports, they push every two cycles. So that's the 2288215976Sjmallett * assumption. That the inbound module will always be able to 2289215976Sjmallett * consume the tick before another is produced. If that doesn't 2290215976Sjmallett * happen - that's when OVRERR will assert. 2291215976Sjmallett * 2292215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2293215976Sjmallett */ 2294215976Sjmallettunion cvmx_agl_gmx_rxx_int_reg 2295215976Sjmallett{ 2296215976Sjmallett uint64_t u64; 2297215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s 2298215976Sjmallett { 2299215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2300215976Sjmallett uint64_t reserved_20_63 : 44; 2301215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 2302215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RGMII inbound LinkDuplex | NS */ 2303215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RGMII inbound LinkSpeed | NS */ 2304215976Sjmallett uint64_t phy_link : 1; /**< Change in the RGMII inbound LinkStatus | NS */ 2305215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 2306215976Sjmallett Does not necessarily indicate a failure */ 2307215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 2308215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 2309215976Sjmallett uint64_t rsverr : 1; /**< Packet reserved opcodes */ 2310215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 2311215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 2312215976Sjmallett This interrupt should never assert */ 2313215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) | NS */ 2314215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 2315215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Packet Data reception error */ 2316215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2317215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 2318215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 2319215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 2320215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2321215976Sjmallett uint64_t carext : 1; /**< Carrier extend error */ 2322215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2323215976Sjmallett#else 2324215976Sjmallett uint64_t minerr : 1; 2325215976Sjmallett uint64_t carext : 1; 2326215976Sjmallett uint64_t maxerr : 1; 2327215976Sjmallett uint64_t jabber : 1; 2328215976Sjmallett uint64_t fcserr : 1; 2329215976Sjmallett uint64_t alnerr : 1; 2330215976Sjmallett uint64_t lenerr : 1; 2331215976Sjmallett uint64_t rcverr : 1; 2332215976Sjmallett uint64_t skperr : 1; 2333215976Sjmallett uint64_t niberr : 1; 2334215976Sjmallett uint64_t ovrerr : 1; 2335215976Sjmallett uint64_t pcterr : 1; 2336215976Sjmallett uint64_t rsverr : 1; 2337215976Sjmallett uint64_t falerr : 1; 2338215976Sjmallett uint64_t coldet : 1; 2339215976Sjmallett uint64_t ifgerr : 1; 2340215976Sjmallett uint64_t phy_link : 1; 2341215976Sjmallett uint64_t phy_spd : 1; 2342215976Sjmallett uint64_t phy_dupx : 1; 2343215976Sjmallett uint64_t pause_drp : 1; 2344215976Sjmallett uint64_t reserved_20_63 : 44; 2345215976Sjmallett#endif 2346215976Sjmallett } s; 2347215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_cn52xx 2348215976Sjmallett { 2349215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2350215976Sjmallett uint64_t reserved_20_63 : 44; 2351215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 2352215976Sjmallett uint64_t reserved_16_18 : 3; 2353215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 2354215976Sjmallett Does not necessarily indicate a failure */ 2355215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 2356215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 2357215976Sjmallett uint64_t rsverr : 1; /**< MII reserved opcodes */ 2358215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 2359215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 2360215976Sjmallett This interrupt should never assert */ 2361215976Sjmallett uint64_t reserved_9_9 : 1; 2362215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 2363215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with MII Data reception error */ 2364215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2365215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 2366215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 2367215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 2368215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2369215976Sjmallett uint64_t reserved_1_1 : 1; 2370215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2371215976Sjmallett#else 2372215976Sjmallett uint64_t minerr : 1; 2373215976Sjmallett uint64_t reserved_1_1 : 1; 2374215976Sjmallett uint64_t maxerr : 1; 2375215976Sjmallett uint64_t jabber : 1; 2376215976Sjmallett uint64_t fcserr : 1; 2377215976Sjmallett uint64_t alnerr : 1; 2378215976Sjmallett uint64_t lenerr : 1; 2379215976Sjmallett uint64_t rcverr : 1; 2380215976Sjmallett uint64_t skperr : 1; 2381215976Sjmallett uint64_t reserved_9_9 : 1; 2382215976Sjmallett uint64_t ovrerr : 1; 2383215976Sjmallett uint64_t pcterr : 1; 2384215976Sjmallett uint64_t rsverr : 1; 2385215976Sjmallett uint64_t falerr : 1; 2386215976Sjmallett uint64_t coldet : 1; 2387215976Sjmallett uint64_t ifgerr : 1; 2388215976Sjmallett uint64_t reserved_16_18 : 3; 2389215976Sjmallett uint64_t pause_drp : 1; 2390215976Sjmallett uint64_t reserved_20_63 : 44; 2391215976Sjmallett#endif 2392215976Sjmallett } cn52xx; 2393215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1; 2394215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx; 2395215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1; 2396215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s cn63xx; 2397215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1; 2398215976Sjmallett}; 2399215976Sjmalletttypedef union cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_int_reg_t; 2400215976Sjmallett 2401215976Sjmallett/** 2402215976Sjmallett * cvmx_agl_gmx_rx#_jabber 2403215976Sjmallett * 2404215976Sjmallett * AGL_GMX_RX_JABBER = The max size packet after which GMX will truncate 2405215976Sjmallett * 2406215976Sjmallett * 2407215976Sjmallett * Notes: 2408215976Sjmallett * CNT must be 8-byte aligned such that CNT[2:0] == 0 2409215976Sjmallett * 2410215976Sjmallett * The packet that will be sent to the packet input logic will have an 2411215976Sjmallett * additionl 8 bytes if AGL_GMX_RX_FRM_CTL[PRE_CHK] is set and 2412215976Sjmallett * AGL_GMX_RX_FRM_CTL[PRE_STRP] is clear. The max packet that will be sent is 2413215976Sjmallett * defined as... 2414215976Sjmallett * 2415215976Sjmallett * max_sized_packet = AGL_GMX_RX_JABBER[CNT]+((AGL_GMX_RX_FRM_CTL[PRE_CHK] & !AGL_GMX_RX_FRM_CTL[PRE_STRP])*8) 2416215976Sjmallett * 2417215976Sjmallett * Be sure the CNT field value is at least as large as the 2418215976Sjmallett * AGL_GMX_RX_FRM_MAX[LEN] value. Failure to meet this constraint will cause 2419215976Sjmallett * packets that are within the AGL_GMX_RX_FRM_MAX[LEN] length to be rejected 2420215976Sjmallett * because they exceed the CNT limit. 2421215976Sjmallett * 2422215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2423215976Sjmallett */ 2424215976Sjmallettunion cvmx_agl_gmx_rxx_jabber 2425215976Sjmallett{ 2426215976Sjmallett uint64_t u64; 2427215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s 2428215976Sjmallett { 2429215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2430215976Sjmallett uint64_t reserved_16_63 : 48; 2431215976Sjmallett uint64_t cnt : 16; /**< Byte count for jabber check 2432215976Sjmallett Failing packets set the JABBER interrupt and are 2433215976Sjmallett optionally sent with opcode==JABBER 2434215976Sjmallett GMX will truncate the packet to CNT bytes 2435215976Sjmallett CNT >= AGL_GMX_RX_FRM_MAX[LEN] */ 2436215976Sjmallett#else 2437215976Sjmallett uint64_t cnt : 16; 2438215976Sjmallett uint64_t reserved_16_63 : 48; 2439215976Sjmallett#endif 2440215976Sjmallett } s; 2441215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn52xx; 2442215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; 2443215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn56xx; 2444215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; 2445215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn63xx; 2446215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1; 2447215976Sjmallett}; 2448215976Sjmalletttypedef union cvmx_agl_gmx_rxx_jabber cvmx_agl_gmx_rxx_jabber_t; 2449215976Sjmallett 2450215976Sjmallett/** 2451215976Sjmallett * cvmx_agl_gmx_rx#_pause_drop_time 2452215976Sjmallett * 2453215976Sjmallett * AGL_GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition 2454215976Sjmallett * 2455215976Sjmallett * 2456215976Sjmallett * Notes: 2457215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2458215976Sjmallett * 2459215976Sjmallett */ 2460215976Sjmallettunion cvmx_agl_gmx_rxx_pause_drop_time 2461215976Sjmallett{ 2462215976Sjmallett uint64_t u64; 2463215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s 2464215976Sjmallett { 2465215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2466215976Sjmallett uint64_t reserved_16_63 : 48; 2467215976Sjmallett uint64_t status : 16; /**< Time extracted from the dropped PAUSE packet */ 2468215976Sjmallett#else 2469215976Sjmallett uint64_t status : 16; 2470215976Sjmallett uint64_t reserved_16_63 : 48; 2471215976Sjmallett#endif 2472215976Sjmallett } s; 2473215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; 2474215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; 2475215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; 2476215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; 2477215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx; 2478215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1; 2479215976Sjmallett}; 2480215976Sjmalletttypedef union cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_pause_drop_time_t; 2481215976Sjmallett 2482215976Sjmallett/** 2483215976Sjmallett * cvmx_agl_gmx_rx#_rx_inbnd 2484215976Sjmallett * 2485215976Sjmallett * AGL_GMX_RX_INBND = RGMII InBand Link Status 2486215976Sjmallett * 2487215976Sjmallett * 2488215976Sjmallett * Notes: 2489215976Sjmallett * These fields are only valid if the attached PHY is operating in RGMII mode 2490215976Sjmallett * and supports the optional in-band status (see section 3.4.1 of the RGMII 2491215976Sjmallett * specification, version 1.3 for more information). 2492215976Sjmallett * 2493215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2494215976Sjmallett */ 2495215976Sjmallettunion cvmx_agl_gmx_rxx_rx_inbnd 2496215976Sjmallett{ 2497215976Sjmallett uint64_t u64; 2498215976Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s 2499215976Sjmallett { 2500215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2501215976Sjmallett uint64_t reserved_4_63 : 60; 2502215976Sjmallett uint64_t duplex : 1; /**< RGMII Inbound LinkDuplex | NS 2503215976Sjmallett 0=half-duplex 2504215976Sjmallett 1=full-duplex */ 2505215976Sjmallett uint64_t speed : 2; /**< RGMII Inbound LinkSpeed | NS 2506215976Sjmallett 00=2.5MHz 2507215976Sjmallett 01=25MHz 2508215976Sjmallett 10=125MHz 2509215976Sjmallett 11=Reserved */ 2510215976Sjmallett uint64_t status : 1; /**< RGMII Inbound LinkStatus | NS 2511215976Sjmallett 0=down 2512215976Sjmallett 1=up */ 2513215976Sjmallett#else 2514215976Sjmallett uint64_t status : 1; 2515215976Sjmallett uint64_t speed : 2; 2516215976Sjmallett uint64_t duplex : 1; 2517215976Sjmallett uint64_t reserved_4_63 : 60; 2518215976Sjmallett#endif 2519215976Sjmallett } s; 2520215976Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx; 2521215976Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1; 2522215976Sjmallett}; 2523215976Sjmalletttypedef union cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_rx_inbnd_t; 2524215976Sjmallett 2525215976Sjmallett/** 2526215976Sjmallett * cvmx_agl_gmx_rx#_stats_ctl 2527215976Sjmallett * 2528215976Sjmallett * AGL_GMX_RX_STATS_CTL = RX Stats Control register 2529215976Sjmallett * 2530215976Sjmallett * 2531215976Sjmallett * Notes: 2532215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2533215976Sjmallett * 2534215976Sjmallett */ 2535215976Sjmallettunion cvmx_agl_gmx_rxx_stats_ctl 2536215976Sjmallett{ 2537215976Sjmallett uint64_t u64; 2538215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s 2539215976Sjmallett { 2540215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2541215976Sjmallett uint64_t reserved_1_63 : 63; 2542215976Sjmallett uint64_t rd_clr : 1; /**< RX Stats registers will clear on reads */ 2543215976Sjmallett#else 2544215976Sjmallett uint64_t rd_clr : 1; 2545215976Sjmallett uint64_t reserved_1_63 : 63; 2546215976Sjmallett#endif 2547215976Sjmallett } s; 2548215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; 2549215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; 2550215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; 2551215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; 2552215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx; 2553215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1; 2554215976Sjmallett}; 2555215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_ctl cvmx_agl_gmx_rxx_stats_ctl_t; 2556215976Sjmallett 2557215976Sjmallett/** 2558215976Sjmallett * cvmx_agl_gmx_rx#_stats_octs 2559215976Sjmallett * 2560215976Sjmallett * Notes: 2561215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2562215976Sjmallett * - Counters will wrap 2563215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2564215976Sjmallett */ 2565215976Sjmallettunion cvmx_agl_gmx_rxx_stats_octs 2566215976Sjmallett{ 2567215976Sjmallett uint64_t u64; 2568215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s 2569215976Sjmallett { 2570215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2571215976Sjmallett uint64_t reserved_48_63 : 16; 2572215976Sjmallett uint64_t cnt : 48; /**< Octet count of received good packets */ 2573215976Sjmallett#else 2574215976Sjmallett uint64_t cnt : 48; 2575215976Sjmallett uint64_t reserved_48_63 : 16; 2576215976Sjmallett#endif 2577215976Sjmallett } s; 2578215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; 2579215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; 2580215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; 2581215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; 2582215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx; 2583215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1; 2584215976Sjmallett}; 2585215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_t; 2586215976Sjmallett 2587215976Sjmallett/** 2588215976Sjmallett * cvmx_agl_gmx_rx#_stats_octs_ctl 2589215976Sjmallett * 2590215976Sjmallett * Notes: 2591215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2592215976Sjmallett * - Counters will wrap 2593215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2594215976Sjmallett */ 2595215976Sjmallettunion cvmx_agl_gmx_rxx_stats_octs_ctl 2596215976Sjmallett{ 2597215976Sjmallett uint64_t u64; 2598215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s 2599215976Sjmallett { 2600215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2601215976Sjmallett uint64_t reserved_48_63 : 16; 2602215976Sjmallett uint64_t cnt : 48; /**< Octet count of received pause packets */ 2603215976Sjmallett#else 2604215976Sjmallett uint64_t cnt : 48; 2605215976Sjmallett uint64_t reserved_48_63 : 16; 2606215976Sjmallett#endif 2607215976Sjmallett } s; 2608215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; 2609215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; 2610215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; 2611215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; 2612215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx; 2613215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1; 2614215976Sjmallett}; 2615215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_ctl_t; 2616215976Sjmallett 2617215976Sjmallett/** 2618215976Sjmallett * cvmx_agl_gmx_rx#_stats_octs_dmac 2619215976Sjmallett * 2620215976Sjmallett * Notes: 2621215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2622215976Sjmallett * - Counters will wrap 2623215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2624215976Sjmallett */ 2625215976Sjmallettunion cvmx_agl_gmx_rxx_stats_octs_dmac 2626215976Sjmallett{ 2627215976Sjmallett uint64_t u64; 2628215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s 2629215976Sjmallett { 2630215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2631215976Sjmallett uint64_t reserved_48_63 : 16; 2632215976Sjmallett uint64_t cnt : 48; /**< Octet count of filtered dmac packets */ 2633215976Sjmallett#else 2634215976Sjmallett uint64_t cnt : 48; 2635215976Sjmallett uint64_t reserved_48_63 : 16; 2636215976Sjmallett#endif 2637215976Sjmallett } s; 2638215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; 2639215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; 2640215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; 2641215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; 2642215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx; 2643215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1; 2644215976Sjmallett}; 2645215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_octs_dmac cvmx_agl_gmx_rxx_stats_octs_dmac_t; 2646215976Sjmallett 2647215976Sjmallett/** 2648215976Sjmallett * cvmx_agl_gmx_rx#_stats_octs_drp 2649215976Sjmallett * 2650215976Sjmallett * Notes: 2651215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2652215976Sjmallett * - Counters will wrap 2653215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2654215976Sjmallett */ 2655215976Sjmallettunion cvmx_agl_gmx_rxx_stats_octs_drp 2656215976Sjmallett{ 2657215976Sjmallett uint64_t u64; 2658215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s 2659215976Sjmallett { 2660215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2661215976Sjmallett uint64_t reserved_48_63 : 16; 2662215976Sjmallett uint64_t cnt : 48; /**< Octet count of dropped packets */ 2663215976Sjmallett#else 2664215976Sjmallett uint64_t cnt : 48; 2665215976Sjmallett uint64_t reserved_48_63 : 16; 2666215976Sjmallett#endif 2667215976Sjmallett } s; 2668215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; 2669215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; 2670215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; 2671215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; 2672215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx; 2673215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1; 2674215976Sjmallett}; 2675215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_octs_drp_t; 2676215976Sjmallett 2677215976Sjmallett/** 2678215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts 2679215976Sjmallett * 2680215976Sjmallett * AGL_GMX_RX_STATS_PKTS 2681215976Sjmallett * 2682215976Sjmallett * Count of good received packets - packets that are not recognized as PAUSE 2683215976Sjmallett * packets, dropped due the DMAC filter, dropped due FIFO full status, or 2684215976Sjmallett * have any other OPCODE (FCS, Length, etc). 2685215976Sjmallett * 2686215976Sjmallett * Notes: 2687215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2688215976Sjmallett * - Counters will wrap 2689215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2690215976Sjmallett */ 2691215976Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts 2692215976Sjmallett{ 2693215976Sjmallett uint64_t u64; 2694215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s 2695215976Sjmallett { 2696215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2697215976Sjmallett uint64_t reserved_32_63 : 32; 2698215976Sjmallett uint64_t cnt : 32; /**< Count of received good packets */ 2699215976Sjmallett#else 2700215976Sjmallett uint64_t cnt : 32; 2701215976Sjmallett uint64_t reserved_32_63 : 32; 2702215976Sjmallett#endif 2703215976Sjmallett } s; 2704215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; 2705215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; 2706215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; 2707215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; 2708215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx; 2709215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1; 2710215976Sjmallett}; 2711215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_t; 2712215976Sjmallett 2713215976Sjmallett/** 2714215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts_bad 2715215976Sjmallett * 2716215976Sjmallett * AGL_GMX_RX_STATS_PKTS_BAD 2717215976Sjmallett * 2718215976Sjmallett * Count of all packets received with some error that were not dropped 2719215976Sjmallett * either due to the dmac filter or lack of room in the receive FIFO. 2720215976Sjmallett * 2721215976Sjmallett * Notes: 2722215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2723215976Sjmallett * - Counters will wrap 2724215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2725215976Sjmallett */ 2726215976Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts_bad 2727215976Sjmallett{ 2728215976Sjmallett uint64_t u64; 2729215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s 2730215976Sjmallett { 2731215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2732215976Sjmallett uint64_t reserved_32_63 : 32; 2733215976Sjmallett uint64_t cnt : 32; /**< Count of bad packets */ 2734215976Sjmallett#else 2735215976Sjmallett uint64_t cnt : 32; 2736215976Sjmallett uint64_t reserved_32_63 : 32; 2737215976Sjmallett#endif 2738215976Sjmallett } s; 2739215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; 2740215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; 2741215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; 2742215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; 2743215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx; 2744215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1; 2745215976Sjmallett}; 2746215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts_bad cvmx_agl_gmx_rxx_stats_pkts_bad_t; 2747215976Sjmallett 2748215976Sjmallett/** 2749215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts_ctl 2750215976Sjmallett * 2751215976Sjmallett * AGL_GMX_RX_STATS_PKTS_CTL 2752215976Sjmallett * 2753215976Sjmallett * Count of all packets received that were recognized as Flow Control or 2754215976Sjmallett * PAUSE packets. PAUSE packets with any kind of error are counted in 2755215976Sjmallett * AGL_GMX_RX_STATS_PKTS_BAD. Pause packets can be optionally dropped or 2756215976Sjmallett * forwarded based on the AGL_GMX_RX_FRM_CTL[CTL_DRP] bit. This count 2757215976Sjmallett * increments regardless of whether the packet is dropped. Pause packets 2758215976Sjmallett * will never be counted in AGL_GMX_RX_STATS_PKTS. Packets dropped due the dmac 2759215976Sjmallett * filter will be counted in AGL_GMX_RX_STATS_PKTS_DMAC and not here. 2760215976Sjmallett * 2761215976Sjmallett * Notes: 2762215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2763215976Sjmallett * - Counters will wrap 2764215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2765215976Sjmallett */ 2766215976Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts_ctl 2767215976Sjmallett{ 2768215976Sjmallett uint64_t u64; 2769215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s 2770215976Sjmallett { 2771215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2772215976Sjmallett uint64_t reserved_32_63 : 32; 2773215976Sjmallett uint64_t cnt : 32; /**< Count of received pause packets */ 2774215976Sjmallett#else 2775215976Sjmallett uint64_t cnt : 32; 2776215976Sjmallett uint64_t reserved_32_63 : 32; 2777215976Sjmallett#endif 2778215976Sjmallett } s; 2779215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; 2780215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; 2781215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; 2782215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; 2783215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx; 2784215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1; 2785215976Sjmallett}; 2786215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_ctl_t; 2787215976Sjmallett 2788215976Sjmallett/** 2789215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts_dmac 2790215976Sjmallett * 2791215976Sjmallett * AGL_GMX_RX_STATS_PKTS_DMAC 2792215976Sjmallett * 2793215976Sjmallett * Count of all packets received that were dropped by the dmac filter. 2794215976Sjmallett * Packets that match the DMAC will be dropped and counted here regardless 2795215976Sjmallett * of if they were bad packets. These packets will never be counted in 2796215976Sjmallett * AGL_GMX_RX_STATS_PKTS. 2797215976Sjmallett * 2798215976Sjmallett * Some packets that were not able to satisify the DECISION_CNT may not 2799215976Sjmallett * actually be dropped by Octeon, but they will be counted here as if they 2800215976Sjmallett * were dropped. 2801215976Sjmallett * 2802215976Sjmallett * Notes: 2803215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2804215976Sjmallett * - Counters will wrap 2805215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2806215976Sjmallett */ 2807215976Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts_dmac 2808215976Sjmallett{ 2809215976Sjmallett uint64_t u64; 2810215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s 2811215976Sjmallett { 2812215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2813215976Sjmallett uint64_t reserved_32_63 : 32; 2814215976Sjmallett uint64_t cnt : 32; /**< Count of filtered dmac packets */ 2815215976Sjmallett#else 2816215976Sjmallett uint64_t cnt : 32; 2817215976Sjmallett uint64_t reserved_32_63 : 32; 2818215976Sjmallett#endif 2819215976Sjmallett } s; 2820215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; 2821215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; 2822215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; 2823215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; 2824215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx; 2825215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1; 2826215976Sjmallett}; 2827215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_dmac_t; 2828215976Sjmallett 2829215976Sjmallett/** 2830215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts_drp 2831215976Sjmallett * 2832215976Sjmallett * AGL_GMX_RX_STATS_PKTS_DRP 2833215976Sjmallett * 2834215976Sjmallett * Count of all packets received that were dropped due to a full receive 2835215976Sjmallett * FIFO. This counts good and bad packets received - all packets dropped by 2836215976Sjmallett * the FIFO. It does not count packets dropped by the dmac or pause packet 2837215976Sjmallett * filters. 2838215976Sjmallett * 2839215976Sjmallett * Notes: 2840215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2841215976Sjmallett * - Counters will wrap 2842215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2843215976Sjmallett */ 2844215976Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts_drp 2845215976Sjmallett{ 2846215976Sjmallett uint64_t u64; 2847215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s 2848215976Sjmallett { 2849215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2850215976Sjmallett uint64_t reserved_32_63 : 32; 2851215976Sjmallett uint64_t cnt : 32; /**< Count of dropped packets */ 2852215976Sjmallett#else 2853215976Sjmallett uint64_t cnt : 32; 2854215976Sjmallett uint64_t reserved_32_63 : 32; 2855215976Sjmallett#endif 2856215976Sjmallett } s; 2857215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; 2858215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; 2859215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; 2860215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; 2861215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx; 2862215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1; 2863215976Sjmallett}; 2864215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts_drp cvmx_agl_gmx_rxx_stats_pkts_drp_t; 2865215976Sjmallett 2866215976Sjmallett/** 2867215976Sjmallett * cvmx_agl_gmx_rx#_udd_skp 2868215976Sjmallett * 2869215976Sjmallett * AGL_GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data 2870215976Sjmallett * 2871215976Sjmallett * 2872215976Sjmallett * Notes: 2873215976Sjmallett * (1) The skip bytes are part of the packet and will be sent down the NCB 2874215976Sjmallett * packet interface and will be handled by PKI. 2875215976Sjmallett * 2876215976Sjmallett * (2) The system can determine if the UDD bytes are included in the FCS check 2877215976Sjmallett * by using the FCSSEL field - if the FCS check is enabled. 2878215976Sjmallett * 2879215976Sjmallett * (3) Assume that the preamble/sfd is always at the start of the frame - even 2880215976Sjmallett * before UDD bytes. In most cases, there will be no preamble in these 2881215976Sjmallett * cases since it will be MII to MII communication without a PHY 2882215976Sjmallett * involved. 2883215976Sjmallett * 2884215976Sjmallett * (4) We can still do address filtering and control packet filtering is the 2885215976Sjmallett * user desires. 2886215976Sjmallett * 2887215976Sjmallett * (5) UDD_SKP must be 0 in half-duplex operation unless 2888215976Sjmallett * AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear. If AGL_GMX_RX_FRM_CTL[PRE_CHK] is set, 2889215976Sjmallett * then UDD_SKP will normally be 8. 2890215976Sjmallett * 2891215976Sjmallett * (6) In all cases, the UDD bytes will be sent down the packet interface as 2892215976Sjmallett * part of the packet. The UDD bytes are never stripped from the actual 2893215976Sjmallett * packet. 2894215976Sjmallett * 2895215976Sjmallett * (7) If LEN != 0, then AGL_GMX_RX_FRM_CHK[LENERR] will be disabled and AGL_GMX_RX_INT_REG[LENERR] will be zero 2896215976Sjmallett * 2897215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2898215976Sjmallett */ 2899215976Sjmallettunion cvmx_agl_gmx_rxx_udd_skp 2900215976Sjmallett{ 2901215976Sjmallett uint64_t u64; 2902215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s 2903215976Sjmallett { 2904215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2905215976Sjmallett uint64_t reserved_9_63 : 55; 2906215976Sjmallett uint64_t fcssel : 1; /**< Include the skip bytes in the FCS calculation 2907215976Sjmallett 0 = all skip bytes are included in FCS 2908215976Sjmallett 1 = the skip bytes are not included in FCS */ 2909215976Sjmallett uint64_t reserved_7_7 : 1; 2910215976Sjmallett uint64_t len : 7; /**< Amount of User-defined data before the start of 2911215976Sjmallett the L2 data. Zero means L2 comes first. 2912215976Sjmallett Max value is 64. */ 2913215976Sjmallett#else 2914215976Sjmallett uint64_t len : 7; 2915215976Sjmallett uint64_t reserved_7_7 : 1; 2916215976Sjmallett uint64_t fcssel : 1; 2917215976Sjmallett uint64_t reserved_9_63 : 55; 2918215976Sjmallett#endif 2919215976Sjmallett } s; 2920215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; 2921215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; 2922215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; 2923215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; 2924215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx; 2925215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1; 2926215976Sjmallett}; 2927215976Sjmalletttypedef union cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_rxx_udd_skp_t; 2928215976Sjmallett 2929215976Sjmallett/** 2930215976Sjmallett * cvmx_agl_gmx_rx_bp_drop# 2931215976Sjmallett * 2932215976Sjmallett * AGL_GMX_RX_BP_DROP = FIFO mark for packet drop 2933215976Sjmallett * 2934215976Sjmallett * 2935215976Sjmallett * Notes: 2936215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2937215976Sjmallett * 2938215976Sjmallett */ 2939215976Sjmallettunion cvmx_agl_gmx_rx_bp_dropx 2940215976Sjmallett{ 2941215976Sjmallett uint64_t u64; 2942215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s 2943215976Sjmallett { 2944215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2945215976Sjmallett uint64_t reserved_6_63 : 58; 2946215976Sjmallett uint64_t mark : 6; /**< Number of 8B ticks to reserve in the RX FIFO. 2947215976Sjmallett When the FIFO exceeds this count, packets will 2948215976Sjmallett be dropped and not buffered. 2949215976Sjmallett MARK should typically be programmed to 2. 2950215976Sjmallett Failure to program correctly can lead to system 2951215976Sjmallett instability. */ 2952215976Sjmallett#else 2953215976Sjmallett uint64_t mark : 6; 2954215976Sjmallett uint64_t reserved_6_63 : 58; 2955215976Sjmallett#endif 2956215976Sjmallett } s; 2957215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; 2958215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; 2959215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; 2960215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; 2961215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx; 2962215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1; 2963215976Sjmallett}; 2964215976Sjmalletttypedef union cvmx_agl_gmx_rx_bp_dropx cvmx_agl_gmx_rx_bp_dropx_t; 2965215976Sjmallett 2966215976Sjmallett/** 2967215976Sjmallett * cvmx_agl_gmx_rx_bp_off# 2968215976Sjmallett * 2969215976Sjmallett * AGL_GMX_RX_BP_OFF = Lowater mark for packet drop 2970215976Sjmallett * 2971215976Sjmallett * 2972215976Sjmallett * Notes: 2973215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2974215976Sjmallett * 2975215976Sjmallett */ 2976215976Sjmallettunion cvmx_agl_gmx_rx_bp_offx 2977215976Sjmallett{ 2978215976Sjmallett uint64_t u64; 2979215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s 2980215976Sjmallett { 2981215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2982215976Sjmallett uint64_t reserved_6_63 : 58; 2983215976Sjmallett uint64_t mark : 6; /**< Water mark (8B ticks) to deassert backpressure */ 2984215976Sjmallett#else 2985215976Sjmallett uint64_t mark : 6; 2986215976Sjmallett uint64_t reserved_6_63 : 58; 2987215976Sjmallett#endif 2988215976Sjmallett } s; 2989215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; 2990215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; 2991215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; 2992215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; 2993215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn63xx; 2994215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1; 2995215976Sjmallett}; 2996215976Sjmalletttypedef union cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_offx_t; 2997215976Sjmallett 2998215976Sjmallett/** 2999215976Sjmallett * cvmx_agl_gmx_rx_bp_on# 3000215976Sjmallett * 3001215976Sjmallett * AGL_GMX_RX_BP_ON = Hiwater mark for port/interface backpressure 3002215976Sjmallett * 3003215976Sjmallett * 3004215976Sjmallett * Notes: 3005215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3006215976Sjmallett * 3007215976Sjmallett */ 3008215976Sjmallettunion cvmx_agl_gmx_rx_bp_onx 3009215976Sjmallett{ 3010215976Sjmallett uint64_t u64; 3011215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s 3012215976Sjmallett { 3013215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3014215976Sjmallett uint64_t reserved_9_63 : 55; 3015215976Sjmallett uint64_t mark : 9; /**< Hiwater mark (8B ticks) for backpressure. */ 3016215976Sjmallett#else 3017215976Sjmallett uint64_t mark : 9; 3018215976Sjmallett uint64_t reserved_9_63 : 55; 3019215976Sjmallett#endif 3020215976Sjmallett } s; 3021215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; 3022215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; 3023215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; 3024215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; 3025215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn63xx; 3026215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1; 3027215976Sjmallett}; 3028215976Sjmalletttypedef union cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_bp_onx_t; 3029215976Sjmallett 3030215976Sjmallett/** 3031215976Sjmallett * cvmx_agl_gmx_rx_prt_info 3032215976Sjmallett * 3033215976Sjmallett * AGL_GMX_RX_PRT_INFO = state information for the ports 3034215976Sjmallett * 3035215976Sjmallett * 3036215976Sjmallett * Notes: 3037215976Sjmallett * COMMIT[0], DROP[0] will be reset when MIX0_CTL[RESET] is set to 1. 3038215976Sjmallett * COMMIT[1], DROP[1] will be reset when MIX1_CTL[RESET] is set to 1. 3039215976Sjmallett */ 3040215976Sjmallettunion cvmx_agl_gmx_rx_prt_info 3041215976Sjmallett{ 3042215976Sjmallett uint64_t u64; 3043215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_s 3044215976Sjmallett { 3045215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3046215976Sjmallett uint64_t reserved_18_63 : 46; 3047215976Sjmallett uint64_t drop : 2; /**< Port indication that data was dropped */ 3048215976Sjmallett uint64_t reserved_2_15 : 14; 3049215976Sjmallett uint64_t commit : 2; /**< Port indication that SOP was accepted */ 3050215976Sjmallett#else 3051215976Sjmallett uint64_t commit : 2; 3052215976Sjmallett uint64_t reserved_2_15 : 14; 3053215976Sjmallett uint64_t drop : 2; 3054215976Sjmallett uint64_t reserved_18_63 : 46; 3055215976Sjmallett#endif 3056215976Sjmallett } s; 3057215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn52xx; 3058215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; 3059215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_cn56xx 3060215976Sjmallett { 3061215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3062215976Sjmallett uint64_t reserved_17_63 : 47; 3063215976Sjmallett uint64_t drop : 1; /**< Port indication that data was dropped */ 3064215976Sjmallett uint64_t reserved_1_15 : 15; 3065215976Sjmallett uint64_t commit : 1; /**< Port indication that SOP was accepted */ 3066215976Sjmallett#else 3067215976Sjmallett uint64_t commit : 1; 3068215976Sjmallett uint64_t reserved_1_15 : 15; 3069215976Sjmallett uint64_t drop : 1; 3070215976Sjmallett uint64_t reserved_17_63 : 47; 3071215976Sjmallett#endif 3072215976Sjmallett } cn56xx; 3073215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; 3074215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn63xx; 3075215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1; 3076215976Sjmallett}; 3077215976Sjmalletttypedef union cvmx_agl_gmx_rx_prt_info cvmx_agl_gmx_rx_prt_info_t; 3078215976Sjmallett 3079215976Sjmallett/** 3080215976Sjmallett * cvmx_agl_gmx_rx_tx_status 3081215976Sjmallett * 3082215976Sjmallett * AGL_GMX_RX_TX_STATUS = GMX RX/TX Status 3083215976Sjmallett * 3084215976Sjmallett * 3085215976Sjmallett * Notes: 3086215976Sjmallett * RX[0], TX[0] will be reset when MIX0_CTL[RESET] is set to 1. 3087215976Sjmallett * RX[1], TX[1] will be reset when MIX1_CTL[RESET] is set to 1. 3088215976Sjmallett */ 3089215976Sjmallettunion cvmx_agl_gmx_rx_tx_status 3090215976Sjmallett{ 3091215976Sjmallett uint64_t u64; 3092215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_s 3093215976Sjmallett { 3094215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3095215976Sjmallett uint64_t reserved_6_63 : 58; 3096215976Sjmallett uint64_t tx : 2; /**< Transmit data since last read */ 3097215976Sjmallett uint64_t reserved_2_3 : 2; 3098215976Sjmallett uint64_t rx : 2; /**< Receive data since last read */ 3099215976Sjmallett#else 3100215976Sjmallett uint64_t rx : 2; 3101215976Sjmallett uint64_t reserved_2_3 : 2; 3102215976Sjmallett uint64_t tx : 2; 3103215976Sjmallett uint64_t reserved_6_63 : 58; 3104215976Sjmallett#endif 3105215976Sjmallett } s; 3106215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn52xx; 3107215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; 3108215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_cn56xx 3109215976Sjmallett { 3110215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3111215976Sjmallett uint64_t reserved_5_63 : 59; 3112215976Sjmallett uint64_t tx : 1; /**< Transmit data since last read */ 3113215976Sjmallett uint64_t reserved_1_3 : 3; 3114215976Sjmallett uint64_t rx : 1; /**< Receive data since last read */ 3115215976Sjmallett#else 3116215976Sjmallett uint64_t rx : 1; 3117215976Sjmallett uint64_t reserved_1_3 : 3; 3118215976Sjmallett uint64_t tx : 1; 3119215976Sjmallett uint64_t reserved_5_63 : 59; 3120215976Sjmallett#endif 3121215976Sjmallett } cn56xx; 3122215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; 3123215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn63xx; 3124215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1; 3125215976Sjmallett}; 3126215976Sjmalletttypedef union cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rx_tx_status_t; 3127215976Sjmallett 3128215976Sjmallett/** 3129215976Sjmallett * cvmx_agl_gmx_smac# 3130215976Sjmallett * 3131215976Sjmallett * AGL_GMX_SMAC = Packet SMAC 3132215976Sjmallett * 3133215976Sjmallett * 3134215976Sjmallett * Notes: 3135215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3136215976Sjmallett * 3137215976Sjmallett */ 3138215976Sjmallettunion cvmx_agl_gmx_smacx 3139215976Sjmallett{ 3140215976Sjmallett uint64_t u64; 3141215976Sjmallett struct cvmx_agl_gmx_smacx_s 3142215976Sjmallett { 3143215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3144215976Sjmallett uint64_t reserved_48_63 : 16; 3145215976Sjmallett uint64_t smac : 48; /**< The SMAC field is used for generating and 3146215976Sjmallett accepting Control Pause packets */ 3147215976Sjmallett#else 3148215976Sjmallett uint64_t smac : 48; 3149215976Sjmallett uint64_t reserved_48_63 : 16; 3150215976Sjmallett#endif 3151215976Sjmallett } s; 3152215976Sjmallett struct cvmx_agl_gmx_smacx_s cn52xx; 3153215976Sjmallett struct cvmx_agl_gmx_smacx_s cn52xxp1; 3154215976Sjmallett struct cvmx_agl_gmx_smacx_s cn56xx; 3155215976Sjmallett struct cvmx_agl_gmx_smacx_s cn56xxp1; 3156215976Sjmallett struct cvmx_agl_gmx_smacx_s cn63xx; 3157215976Sjmallett struct cvmx_agl_gmx_smacx_s cn63xxp1; 3158215976Sjmallett}; 3159215976Sjmalletttypedef union cvmx_agl_gmx_smacx cvmx_agl_gmx_smacx_t; 3160215976Sjmallett 3161215976Sjmallett/** 3162215976Sjmallett * cvmx_agl_gmx_stat_bp 3163215976Sjmallett * 3164215976Sjmallett * AGL_GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation 3165215976Sjmallett * 3166215976Sjmallett * 3167215976Sjmallett * Notes: 3168215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 3169215976Sjmallett * 3170215976Sjmallett */ 3171215976Sjmallettunion cvmx_agl_gmx_stat_bp 3172215976Sjmallett{ 3173215976Sjmallett uint64_t u64; 3174215976Sjmallett struct cvmx_agl_gmx_stat_bp_s 3175215976Sjmallett { 3176215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3177215976Sjmallett uint64_t reserved_17_63 : 47; 3178215976Sjmallett uint64_t bp : 1; /**< Current BP state */ 3179215976Sjmallett uint64_t cnt : 16; /**< Number of cycles that BP has been asserted 3180215976Sjmallett Saturating counter */ 3181215976Sjmallett#else 3182215976Sjmallett uint64_t cnt : 16; 3183215976Sjmallett uint64_t bp : 1; 3184215976Sjmallett uint64_t reserved_17_63 : 47; 3185215976Sjmallett#endif 3186215976Sjmallett } s; 3187215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn52xx; 3188215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn52xxp1; 3189215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn56xx; 3190215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn56xxp1; 3191215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn63xx; 3192215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn63xxp1; 3193215976Sjmallett}; 3194215976Sjmalletttypedef union cvmx_agl_gmx_stat_bp cvmx_agl_gmx_stat_bp_t; 3195215976Sjmallett 3196215976Sjmallett/** 3197215976Sjmallett * cvmx_agl_gmx_tx#_append 3198215976Sjmallett * 3199215976Sjmallett * AGL_GMX_TX_APPEND = Packet TX Append Control 3200215976Sjmallett * 3201215976Sjmallett * 3202215976Sjmallett * Notes: 3203215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3204215976Sjmallett * 3205215976Sjmallett */ 3206215976Sjmallettunion cvmx_agl_gmx_txx_append 3207215976Sjmallett{ 3208215976Sjmallett uint64_t u64; 3209215976Sjmallett struct cvmx_agl_gmx_txx_append_s 3210215976Sjmallett { 3211215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3212215976Sjmallett uint64_t reserved_4_63 : 60; 3213215976Sjmallett uint64_t force_fcs : 1; /**< Append the Ethernet FCS on each pause packet 3214215976Sjmallett when FCS is clear. Pause packets are normally 3215215976Sjmallett padded to 60 bytes. If 3216215976Sjmallett AGL_GMX_TX_MIN_PKT[MIN_SIZE] exceeds 59, then 3217215976Sjmallett FORCE_FCS will not be used. */ 3218215976Sjmallett uint64_t fcs : 1; /**< Append the Ethernet FCS on each packet */ 3219215976Sjmallett uint64_t pad : 1; /**< Append PAD bytes such that min sized */ 3220215976Sjmallett uint64_t preamble : 1; /**< Prepend the Ethernet preamble on each transfer */ 3221215976Sjmallett#else 3222215976Sjmallett uint64_t preamble : 1; 3223215976Sjmallett uint64_t pad : 1; 3224215976Sjmallett uint64_t fcs : 1; 3225215976Sjmallett uint64_t force_fcs : 1; 3226215976Sjmallett uint64_t reserved_4_63 : 60; 3227215976Sjmallett#endif 3228215976Sjmallett } s; 3229215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn52xx; 3230215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn52xxp1; 3231215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn56xx; 3232215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn56xxp1; 3233215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn63xx; 3234215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn63xxp1; 3235215976Sjmallett}; 3236215976Sjmalletttypedef union cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_append_t; 3237215976Sjmallett 3238215976Sjmallett/** 3239215976Sjmallett * cvmx_agl_gmx_tx#_clk 3240215976Sjmallett * 3241215976Sjmallett * AGL_GMX_TX_CLK = RGMII TX Clock Generation Register 3242215976Sjmallett * 3243215976Sjmallett * 3244215976Sjmallett * Notes: 3245215976Sjmallett * Normal Programming Values: 3246215976Sjmallett * (1) RGMII, 1000Mbs (AGL_GMX_PRT_CFG[SPEED]==1), CLK_CNT == 1 3247215976Sjmallett * (2) RGMII, 10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 50/5 3248215976Sjmallett * (3) MII, 10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 1 3249215976Sjmallett * 3250215976Sjmallett * RGMII Example: 3251215976Sjmallett * Given a 125MHz PLL reference clock... 3252215976Sjmallett * CLK_CNT == 1 ==> 125.0MHz TXC clock period (8ns* 1) 3253215976Sjmallett * CLK_CNT == 5 ==> 25.0MHz TXC clock period (8ns* 5) 3254215976Sjmallett * CLK_CNT == 50 ==> 2.5MHz TXC clock period (8ns*50) 3255215976Sjmallett * 3256215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3257215976Sjmallett */ 3258215976Sjmallettunion cvmx_agl_gmx_txx_clk 3259215976Sjmallett{ 3260215976Sjmallett uint64_t u64; 3261215976Sjmallett struct cvmx_agl_gmx_txx_clk_s 3262215976Sjmallett { 3263215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3264215976Sjmallett uint64_t reserved_6_63 : 58; 3265215976Sjmallett uint64_t clk_cnt : 6; /**< Controls the RGMII TXC frequency | NS 3266215976Sjmallett TXC(period) = 3267215976Sjmallett rgm_ref_clk(period)*CLK_CNT */ 3268215976Sjmallett#else 3269215976Sjmallett uint64_t clk_cnt : 6; 3270215976Sjmallett uint64_t reserved_6_63 : 58; 3271215976Sjmallett#endif 3272215976Sjmallett } s; 3273215976Sjmallett struct cvmx_agl_gmx_txx_clk_s cn63xx; 3274215976Sjmallett struct cvmx_agl_gmx_txx_clk_s cn63xxp1; 3275215976Sjmallett}; 3276215976Sjmalletttypedef union cvmx_agl_gmx_txx_clk cvmx_agl_gmx_txx_clk_t; 3277215976Sjmallett 3278215976Sjmallett/** 3279215976Sjmallett * cvmx_agl_gmx_tx#_ctl 3280215976Sjmallett * 3281215976Sjmallett * AGL_GMX_TX_CTL = TX Control register 3282215976Sjmallett * 3283215976Sjmallett * 3284215976Sjmallett * Notes: 3285215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3286215976Sjmallett * 3287215976Sjmallett */ 3288215976Sjmallettunion cvmx_agl_gmx_txx_ctl 3289215976Sjmallett{ 3290215976Sjmallett uint64_t u64; 3291215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s 3292215976Sjmallett { 3293215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3294215976Sjmallett uint64_t reserved_2_63 : 62; 3295215976Sjmallett uint64_t xsdef_en : 1; /**< Enables the excessive deferral check for stats 3296215976Sjmallett and interrupts */ 3297215976Sjmallett uint64_t xscol_en : 1; /**< Enables the excessive collision check for stats 3298215976Sjmallett and interrupts */ 3299215976Sjmallett#else 3300215976Sjmallett uint64_t xscol_en : 1; 3301215976Sjmallett uint64_t xsdef_en : 1; 3302215976Sjmallett uint64_t reserved_2_63 : 62; 3303215976Sjmallett#endif 3304215976Sjmallett } s; 3305215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn52xx; 3306215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; 3307215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn56xx; 3308215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; 3309215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn63xx; 3310215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn63xxp1; 3311215976Sjmallett}; 3312215976Sjmalletttypedef union cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_ctl_t; 3313215976Sjmallett 3314215976Sjmallett/** 3315215976Sjmallett * cvmx_agl_gmx_tx#_min_pkt 3316215976Sjmallett * 3317215976Sjmallett * AGL_GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size) 3318215976Sjmallett * 3319215976Sjmallett * 3320215976Sjmallett * Notes: 3321215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3322215976Sjmallett * 3323215976Sjmallett */ 3324215976Sjmallettunion cvmx_agl_gmx_txx_min_pkt 3325215976Sjmallett{ 3326215976Sjmallett uint64_t u64; 3327215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s 3328215976Sjmallett { 3329215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3330215976Sjmallett uint64_t reserved_8_63 : 56; 3331215976Sjmallett uint64_t min_size : 8; /**< Min frame in bytes before the FCS is applied 3332215976Sjmallett Padding is only appened when 3333215976Sjmallett AGL_GMX_TX_APPEND[PAD] for the coresponding packet 3334215976Sjmallett port is set. Packets will be padded to 3335215976Sjmallett MIN_SIZE+1 The reset value will pad to 60 bytes. */ 3336215976Sjmallett#else 3337215976Sjmallett uint64_t min_size : 8; 3338215976Sjmallett uint64_t reserved_8_63 : 56; 3339215976Sjmallett#endif 3340215976Sjmallett } s; 3341215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; 3342215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; 3343215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; 3344215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; 3345215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn63xx; 3346215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1; 3347215976Sjmallett}; 3348215976Sjmalletttypedef union cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_min_pkt_t; 3349215976Sjmallett 3350215976Sjmallett/** 3351215976Sjmallett * cvmx_agl_gmx_tx#_pause_pkt_interval 3352215976Sjmallett * 3353215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent 3354215976Sjmallett * 3355215976Sjmallett * 3356215976Sjmallett * Notes: 3357215976Sjmallett * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and 3358215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system 3359215976Sjmallett * designer. It is suggested that TIME be much greater than INTERVAL and 3360215976Sjmallett * AGL_GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE 3361215976Sjmallett * count and then when the backpressure condition is lifted, a PAUSE packet 3362215976Sjmallett * with TIME==0 will be sent indicating that Octane is ready for additional 3363215976Sjmallett * data. 3364215976Sjmallett * 3365215976Sjmallett * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is 3366215976Sjmallett * suggested that TIME and INTERVAL are programmed such that they satisify the 3367215976Sjmallett * following rule... 3368215976Sjmallett * 3369215976Sjmallett * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size) 3370215976Sjmallett * 3371215976Sjmallett * where largest_pkt_size is that largest packet that the system can send 3372215976Sjmallett * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size 3373215976Sjmallett * of the PAUSE packet (normally 64B). 3374215976Sjmallett * 3375215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3376215976Sjmallett */ 3377215976Sjmallettunion cvmx_agl_gmx_txx_pause_pkt_interval 3378215976Sjmallett{ 3379215976Sjmallett uint64_t u64; 3380215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s 3381215976Sjmallett { 3382215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3383215976Sjmallett uint64_t reserved_16_63 : 48; 3384215976Sjmallett uint64_t interval : 16; /**< Arbitrate for a pause packet every (INTERVAL*512) 3385215976Sjmallett bit-times. 3386215976Sjmallett Normally, 0 < INTERVAL < AGL_GMX_TX_PAUSE_PKT_TIME 3387215976Sjmallett INTERVAL=0, will only send a single PAUSE packet 3388215976Sjmallett for each backpressure event */ 3389215976Sjmallett#else 3390215976Sjmallett uint64_t interval : 16; 3391215976Sjmallett uint64_t reserved_16_63 : 48; 3392215976Sjmallett#endif 3393215976Sjmallett } s; 3394215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; 3395215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; 3396215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; 3397215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; 3398215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx; 3399215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1; 3400215976Sjmallett}; 3401215976Sjmalletttypedef union cvmx_agl_gmx_txx_pause_pkt_interval cvmx_agl_gmx_txx_pause_pkt_interval_t; 3402215976Sjmallett 3403215976Sjmallett/** 3404215976Sjmallett * cvmx_agl_gmx_tx#_pause_pkt_time 3405215976Sjmallett * 3406215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field 3407215976Sjmallett * 3408215976Sjmallett * 3409215976Sjmallett * Notes: 3410215976Sjmallett * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and 3411215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system 3412215976Sjmallett * designer. It is suggested that TIME be much greater than INTERVAL and 3413215976Sjmallett * AGL_GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE 3414215976Sjmallett * count and then when the backpressure condition is lifted, a PAUSE packet 3415215976Sjmallett * with TIME==0 will be sent indicating that Octane is ready for additional 3416215976Sjmallett * data. 3417215976Sjmallett * 3418215976Sjmallett * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is 3419215976Sjmallett * suggested that TIME and INTERVAL are programmed such that they satisify the 3420215976Sjmallett * following rule... 3421215976Sjmallett * 3422215976Sjmallett * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size) 3423215976Sjmallett * 3424215976Sjmallett * where largest_pkt_size is that largest packet that the system can send 3425215976Sjmallett * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size 3426215976Sjmallett * of the PAUSE packet (normally 64B). 3427215976Sjmallett * 3428215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3429215976Sjmallett */ 3430215976Sjmallettunion cvmx_agl_gmx_txx_pause_pkt_time 3431215976Sjmallett{ 3432215976Sjmallett uint64_t u64; 3433215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s 3434215976Sjmallett { 3435215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3436215976Sjmallett uint64_t reserved_16_63 : 48; 3437215976Sjmallett uint64_t time : 16; /**< The pause_time field placed is outbnd pause pkts 3438215976Sjmallett pause_time is in 512 bit-times 3439215976Sjmallett Normally, TIME > AGL_GMX_TX_PAUSE_PKT_INTERVAL */ 3440215976Sjmallett#else 3441215976Sjmallett uint64_t time : 16; 3442215976Sjmallett uint64_t reserved_16_63 : 48; 3443215976Sjmallett#endif 3444215976Sjmallett } s; 3445215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; 3446215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; 3447215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; 3448215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; 3449215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx; 3450215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1; 3451215976Sjmallett}; 3452215976Sjmalletttypedef union cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_pkt_time_t; 3453215976Sjmallett 3454215976Sjmallett/** 3455215976Sjmallett * cvmx_agl_gmx_tx#_pause_togo 3456215976Sjmallett * 3457215976Sjmallett * AGL_GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure 3458215976Sjmallett * 3459215976Sjmallett * 3460215976Sjmallett * Notes: 3461215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3462215976Sjmallett * 3463215976Sjmallett */ 3464215976Sjmallettunion cvmx_agl_gmx_txx_pause_togo 3465215976Sjmallett{ 3466215976Sjmallett uint64_t u64; 3467215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s 3468215976Sjmallett { 3469215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3470215976Sjmallett uint64_t reserved_16_63 : 48; 3471215976Sjmallett uint64_t time : 16; /**< Amount of time remaining to backpressure */ 3472215976Sjmallett#else 3473215976Sjmallett uint64_t time : 16; 3474215976Sjmallett uint64_t reserved_16_63 : 48; 3475215976Sjmallett#endif 3476215976Sjmallett } s; 3477215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; 3478215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; 3479215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; 3480215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; 3481215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn63xx; 3482215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1; 3483215976Sjmallett}; 3484215976Sjmalletttypedef union cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_togo_t; 3485215976Sjmallett 3486215976Sjmallett/** 3487215976Sjmallett * cvmx_agl_gmx_tx#_pause_zero 3488215976Sjmallett * 3489215976Sjmallett * AGL_GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure 3490215976Sjmallett * 3491215976Sjmallett * 3492215976Sjmallett * Notes: 3493215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3494215976Sjmallett * 3495215976Sjmallett */ 3496215976Sjmallettunion cvmx_agl_gmx_txx_pause_zero 3497215976Sjmallett{ 3498215976Sjmallett uint64_t u64; 3499215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s 3500215976Sjmallett { 3501215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3502215976Sjmallett uint64_t reserved_1_63 : 63; 3503215976Sjmallett uint64_t send : 1; /**< When backpressure condition clear, send PAUSE 3504215976Sjmallett packet with pause_time of zero to enable the 3505215976Sjmallett channel */ 3506215976Sjmallett#else 3507215976Sjmallett uint64_t send : 1; 3508215976Sjmallett uint64_t reserved_1_63 : 63; 3509215976Sjmallett#endif 3510215976Sjmallett } s; 3511215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; 3512215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; 3513215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; 3514215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; 3515215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn63xx; 3516215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1; 3517215976Sjmallett}; 3518215976Sjmalletttypedef union cvmx_agl_gmx_txx_pause_zero cvmx_agl_gmx_txx_pause_zero_t; 3519215976Sjmallett 3520215976Sjmallett/** 3521215976Sjmallett * cvmx_agl_gmx_tx#_soft_pause 3522215976Sjmallett * 3523215976Sjmallett * AGL_GMX_TX_SOFT_PAUSE = Packet TX Software Pause 3524215976Sjmallett * 3525215976Sjmallett * 3526215976Sjmallett * Notes: 3527215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3528215976Sjmallett * 3529215976Sjmallett */ 3530215976Sjmallettunion cvmx_agl_gmx_txx_soft_pause 3531215976Sjmallett{ 3532215976Sjmallett uint64_t u64; 3533215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s 3534215976Sjmallett { 3535215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3536215976Sjmallett uint64_t reserved_16_63 : 48; 3537215976Sjmallett uint64_t time : 16; /**< Back off the TX bus for (TIME*512) bit-times 3538215976Sjmallett for full-duplex operation only */ 3539215976Sjmallett#else 3540215976Sjmallett uint64_t time : 16; 3541215976Sjmallett uint64_t reserved_16_63 : 48; 3542215976Sjmallett#endif 3543215976Sjmallett } s; 3544215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; 3545215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; 3546215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; 3547215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; 3548215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn63xx; 3549215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1; 3550215976Sjmallett}; 3551215976Sjmalletttypedef union cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_soft_pause_t; 3552215976Sjmallett 3553215976Sjmallett/** 3554215976Sjmallett * cvmx_agl_gmx_tx#_stat0 3555215976Sjmallett * 3556215976Sjmallett * AGL_GMX_TX_STAT0 = AGL_GMX_TX_STATS_XSDEF / AGL_GMX_TX_STATS_XSCOL 3557215976Sjmallett * 3558215976Sjmallett * 3559215976Sjmallett * Notes: 3560215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3561215976Sjmallett * - Counters will wrap 3562215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3563215976Sjmallett */ 3564215976Sjmallettunion cvmx_agl_gmx_txx_stat0 3565215976Sjmallett{ 3566215976Sjmallett uint64_t u64; 3567215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s 3568215976Sjmallett { 3569215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3570215976Sjmallett uint64_t xsdef : 32; /**< Number of packets dropped (never successfully 3571215976Sjmallett sent) due to excessive deferal */ 3572215976Sjmallett uint64_t xscol : 32; /**< Number of packets dropped (never successfully 3573215976Sjmallett sent) due to excessive collision. Defined by 3574215976Sjmallett AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */ 3575215976Sjmallett#else 3576215976Sjmallett uint64_t xscol : 32; 3577215976Sjmallett uint64_t xsdef : 32; 3578215976Sjmallett#endif 3579215976Sjmallett } s; 3580215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn52xx; 3581215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; 3582215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn56xx; 3583215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; 3584215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn63xx; 3585215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn63xxp1; 3586215976Sjmallett}; 3587215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat0_t; 3588215976Sjmallett 3589215976Sjmallett/** 3590215976Sjmallett * cvmx_agl_gmx_tx#_stat1 3591215976Sjmallett * 3592215976Sjmallett * AGL_GMX_TX_STAT1 = AGL_GMX_TX_STATS_SCOL / AGL_GMX_TX_STATS_MCOL 3593215976Sjmallett * 3594215976Sjmallett * 3595215976Sjmallett * Notes: 3596215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3597215976Sjmallett * - Counters will wrap 3598215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3599215976Sjmallett */ 3600215976Sjmallettunion cvmx_agl_gmx_txx_stat1 3601215976Sjmallett{ 3602215976Sjmallett uint64_t u64; 3603215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s 3604215976Sjmallett { 3605215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3606215976Sjmallett uint64_t scol : 32; /**< Number of packets sent with a single collision */ 3607215976Sjmallett uint64_t mcol : 32; /**< Number of packets sent with multiple collisions 3608215976Sjmallett but < AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */ 3609215976Sjmallett#else 3610215976Sjmallett uint64_t mcol : 32; 3611215976Sjmallett uint64_t scol : 32; 3612215976Sjmallett#endif 3613215976Sjmallett } s; 3614215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn52xx; 3615215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; 3616215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn56xx; 3617215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; 3618215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn63xx; 3619215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn63xxp1; 3620215976Sjmallett}; 3621215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat1 cvmx_agl_gmx_txx_stat1_t; 3622215976Sjmallett 3623215976Sjmallett/** 3624215976Sjmallett * cvmx_agl_gmx_tx#_stat2 3625215976Sjmallett * 3626215976Sjmallett * AGL_GMX_TX_STAT2 = AGL_GMX_TX_STATS_OCTS 3627215976Sjmallett * 3628215976Sjmallett * 3629215976Sjmallett * Notes: 3630215976Sjmallett * - Octect counts are the sum of all data transmitted on the wire including 3631215976Sjmallett * packet data, pad bytes, fcs bytes, pause bytes, and jam bytes. The octect 3632215976Sjmallett * counts do not include PREAMBLE byte or EXTEND cycles. 3633215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3634215976Sjmallett * - Counters will wrap 3635215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3636215976Sjmallett */ 3637215976Sjmallettunion cvmx_agl_gmx_txx_stat2 3638215976Sjmallett{ 3639215976Sjmallett uint64_t u64; 3640215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s 3641215976Sjmallett { 3642215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3643215976Sjmallett uint64_t reserved_48_63 : 16; 3644215976Sjmallett uint64_t octs : 48; /**< Number of total octets sent on the interface. 3645215976Sjmallett Does not count octets from frames that were 3646215976Sjmallett truncated due to collisions in halfdup mode. */ 3647215976Sjmallett#else 3648215976Sjmallett uint64_t octs : 48; 3649215976Sjmallett uint64_t reserved_48_63 : 16; 3650215976Sjmallett#endif 3651215976Sjmallett } s; 3652215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn52xx; 3653215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; 3654215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn56xx; 3655215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; 3656215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn63xx; 3657215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn63xxp1; 3658215976Sjmallett}; 3659215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat2_t; 3660215976Sjmallett 3661215976Sjmallett/** 3662215976Sjmallett * cvmx_agl_gmx_tx#_stat3 3663215976Sjmallett * 3664215976Sjmallett * AGL_GMX_TX_STAT3 = AGL_GMX_TX_STATS_PKTS 3665215976Sjmallett * 3666215976Sjmallett * 3667215976Sjmallett * Notes: 3668215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3669215976Sjmallett * - Counters will wrap 3670215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3671215976Sjmallett */ 3672215976Sjmallettunion cvmx_agl_gmx_txx_stat3 3673215976Sjmallett{ 3674215976Sjmallett uint64_t u64; 3675215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s 3676215976Sjmallett { 3677215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3678215976Sjmallett uint64_t reserved_32_63 : 32; 3679215976Sjmallett uint64_t pkts : 32; /**< Number of total frames sent on the interface. 3680215976Sjmallett Does not count frames that were truncated due to 3681215976Sjmallett collisions in halfdup mode. */ 3682215976Sjmallett#else 3683215976Sjmallett uint64_t pkts : 32; 3684215976Sjmallett uint64_t reserved_32_63 : 32; 3685215976Sjmallett#endif 3686215976Sjmallett } s; 3687215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn52xx; 3688215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; 3689215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn56xx; 3690215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; 3691215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn63xx; 3692215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn63xxp1; 3693215976Sjmallett}; 3694215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat3_t; 3695215976Sjmallett 3696215976Sjmallett/** 3697215976Sjmallett * cvmx_agl_gmx_tx#_stat4 3698215976Sjmallett * 3699215976Sjmallett * AGL_GMX_TX_STAT4 = AGL_GMX_TX_STATS_HIST1 (64) / AGL_GMX_TX_STATS_HIST0 (<64) 3700215976Sjmallett * 3701215976Sjmallett * 3702215976Sjmallett * Notes: 3703215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 3704215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 3705215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 3706215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3707215976Sjmallett * - Counters will wrap 3708215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3709215976Sjmallett */ 3710215976Sjmallettunion cvmx_agl_gmx_txx_stat4 3711215976Sjmallett{ 3712215976Sjmallett uint64_t u64; 3713215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s 3714215976Sjmallett { 3715215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3716215976Sjmallett uint64_t hist1 : 32; /**< Number of packets sent with an octet count of 64. */ 3717215976Sjmallett uint64_t hist0 : 32; /**< Number of packets sent with an octet count 3718215976Sjmallett of < 64. */ 3719215976Sjmallett#else 3720215976Sjmallett uint64_t hist0 : 32; 3721215976Sjmallett uint64_t hist1 : 32; 3722215976Sjmallett#endif 3723215976Sjmallett } s; 3724215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn52xx; 3725215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; 3726215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn56xx; 3727215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; 3728215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn63xx; 3729215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn63xxp1; 3730215976Sjmallett}; 3731215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat4 cvmx_agl_gmx_txx_stat4_t; 3732215976Sjmallett 3733215976Sjmallett/** 3734215976Sjmallett * cvmx_agl_gmx_tx#_stat5 3735215976Sjmallett * 3736215976Sjmallett * AGL_GMX_TX_STAT5 = AGL_GMX_TX_STATS_HIST3 (128- 255) / AGL_GMX_TX_STATS_HIST2 (65- 127) 3737215976Sjmallett * 3738215976Sjmallett * 3739215976Sjmallett * Notes: 3740215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 3741215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 3742215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 3743215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3744215976Sjmallett * - Counters will wrap 3745215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3746215976Sjmallett */ 3747215976Sjmallettunion cvmx_agl_gmx_txx_stat5 3748215976Sjmallett{ 3749215976Sjmallett uint64_t u64; 3750215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s 3751215976Sjmallett { 3752215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3753215976Sjmallett uint64_t hist3 : 32; /**< Number of packets sent with an octet count of 3754215976Sjmallett 128 - 255. */ 3755215976Sjmallett uint64_t hist2 : 32; /**< Number of packets sent with an octet count of 3756215976Sjmallett 65 - 127. */ 3757215976Sjmallett#else 3758215976Sjmallett uint64_t hist2 : 32; 3759215976Sjmallett uint64_t hist3 : 32; 3760215976Sjmallett#endif 3761215976Sjmallett } s; 3762215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn52xx; 3763215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; 3764215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn56xx; 3765215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; 3766215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn63xx; 3767215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn63xxp1; 3768215976Sjmallett}; 3769215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat5_t; 3770215976Sjmallett 3771215976Sjmallett/** 3772215976Sjmallett * cvmx_agl_gmx_tx#_stat6 3773215976Sjmallett * 3774215976Sjmallett * AGL_GMX_TX_STAT6 = AGL_GMX_TX_STATS_HIST5 (512-1023) / AGL_GMX_TX_STATS_HIST4 (256-511) 3775215976Sjmallett * 3776215976Sjmallett * 3777215976Sjmallett * Notes: 3778215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 3779215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 3780215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 3781215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3782215976Sjmallett * - Counters will wrap 3783215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3784215976Sjmallett */ 3785215976Sjmallettunion cvmx_agl_gmx_txx_stat6 3786215976Sjmallett{ 3787215976Sjmallett uint64_t u64; 3788215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s 3789215976Sjmallett { 3790215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3791215976Sjmallett uint64_t hist5 : 32; /**< Number of packets sent with an octet count of 3792215976Sjmallett 512 - 1023. */ 3793215976Sjmallett uint64_t hist4 : 32; /**< Number of packets sent with an octet count of 3794215976Sjmallett 256 - 511. */ 3795215976Sjmallett#else 3796215976Sjmallett uint64_t hist4 : 32; 3797215976Sjmallett uint64_t hist5 : 32; 3798215976Sjmallett#endif 3799215976Sjmallett } s; 3800215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn52xx; 3801215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; 3802215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn56xx; 3803215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; 3804215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn63xx; 3805215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn63xxp1; 3806215976Sjmallett}; 3807215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat6_t; 3808215976Sjmallett 3809215976Sjmallett/** 3810215976Sjmallett * cvmx_agl_gmx_tx#_stat7 3811215976Sjmallett * 3812215976Sjmallett * AGL_GMX_TX_STAT7 = AGL_GMX_TX_STATS_HIST7 (1024-1518) / AGL_GMX_TX_STATS_HIST6 (>1518) 3813215976Sjmallett * 3814215976Sjmallett * 3815215976Sjmallett * Notes: 3816215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 3817215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 3818215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 3819215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3820215976Sjmallett * - Counters will wrap 3821215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3822215976Sjmallett */ 3823215976Sjmallettunion cvmx_agl_gmx_txx_stat7 3824215976Sjmallett{ 3825215976Sjmallett uint64_t u64; 3826215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s 3827215976Sjmallett { 3828215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3829215976Sjmallett uint64_t hist7 : 32; /**< Number of packets sent with an octet count 3830215976Sjmallett of > 1518. */ 3831215976Sjmallett uint64_t hist6 : 32; /**< Number of packets sent with an octet count of 3832215976Sjmallett 1024 - 1518. */ 3833215976Sjmallett#else 3834215976Sjmallett uint64_t hist6 : 32; 3835215976Sjmallett uint64_t hist7 : 32; 3836215976Sjmallett#endif 3837215976Sjmallett } s; 3838215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn52xx; 3839215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; 3840215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn56xx; 3841215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; 3842215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn63xx; 3843215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn63xxp1; 3844215976Sjmallett}; 3845215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat7 cvmx_agl_gmx_txx_stat7_t; 3846215976Sjmallett 3847215976Sjmallett/** 3848215976Sjmallett * cvmx_agl_gmx_tx#_stat8 3849215976Sjmallett * 3850215976Sjmallett * AGL_GMX_TX_STAT8 = AGL_GMX_TX_STATS_MCST / AGL_GMX_TX_STATS_BCST 3851215976Sjmallett * 3852215976Sjmallett * 3853215976Sjmallett * Notes: 3854215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3855215976Sjmallett * - Counters will wrap 3856215976Sjmallett * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the 3857215976Sjmallett * packet. GMX assumes that the DMAC lies in the first 6 bytes of the packet 3858215976Sjmallett * as per the 802.3 frame definition. If the system requires additional data 3859215976Sjmallett * before the L2 header, then the MCST and BCST counters may not reflect 3860215976Sjmallett * reality and should be ignored by software. 3861215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3862215976Sjmallett */ 3863215976Sjmallettunion cvmx_agl_gmx_txx_stat8 3864215976Sjmallett{ 3865215976Sjmallett uint64_t u64; 3866215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s 3867215976Sjmallett { 3868215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3869215976Sjmallett uint64_t mcst : 32; /**< Number of packets sent to multicast DMAC. 3870215976Sjmallett Does not include BCST packets. */ 3871215976Sjmallett uint64_t bcst : 32; /**< Number of packets sent to broadcast DMAC. 3872215976Sjmallett Does not include MCST packets. */ 3873215976Sjmallett#else 3874215976Sjmallett uint64_t bcst : 32; 3875215976Sjmallett uint64_t mcst : 32; 3876215976Sjmallett#endif 3877215976Sjmallett } s; 3878215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn52xx; 3879215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; 3880215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn56xx; 3881215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; 3882215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn63xx; 3883215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn63xxp1; 3884215976Sjmallett}; 3885215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat8_t; 3886215976Sjmallett 3887215976Sjmallett/** 3888215976Sjmallett * cvmx_agl_gmx_tx#_stat9 3889215976Sjmallett * 3890215976Sjmallett * AGL_GMX_TX_STAT9 = AGL_GMX_TX_STATS_UNDFLW / AGL_GMX_TX_STATS_CTL 3891215976Sjmallett * 3892215976Sjmallett * 3893215976Sjmallett * Notes: 3894215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3895215976Sjmallett * - Counters will wrap 3896215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3897215976Sjmallett */ 3898215976Sjmallettunion cvmx_agl_gmx_txx_stat9 3899215976Sjmallett{ 3900215976Sjmallett uint64_t u64; 3901215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s 3902215976Sjmallett { 3903215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3904215976Sjmallett uint64_t undflw : 32; /**< Number of underflow packets */ 3905215976Sjmallett uint64_t ctl : 32; /**< Number of Control packets (PAUSE flow control) 3906215976Sjmallett generated by GMX. It does not include control 3907215976Sjmallett packets forwarded or generated by the PP's. */ 3908215976Sjmallett#else 3909215976Sjmallett uint64_t ctl : 32; 3910215976Sjmallett uint64_t undflw : 32; 3911215976Sjmallett#endif 3912215976Sjmallett } s; 3913215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn52xx; 3914215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; 3915215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn56xx; 3916215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; 3917215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn63xx; 3918215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn63xxp1; 3919215976Sjmallett}; 3920215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stat9_t; 3921215976Sjmallett 3922215976Sjmallett/** 3923215976Sjmallett * cvmx_agl_gmx_tx#_stats_ctl 3924215976Sjmallett * 3925215976Sjmallett * AGL_GMX_TX_STATS_CTL = TX Stats Control register 3926215976Sjmallett * 3927215976Sjmallett * 3928215976Sjmallett * Notes: 3929215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3930215976Sjmallett * 3931215976Sjmallett */ 3932215976Sjmallettunion cvmx_agl_gmx_txx_stats_ctl 3933215976Sjmallett{ 3934215976Sjmallett uint64_t u64; 3935215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s 3936215976Sjmallett { 3937215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3938215976Sjmallett uint64_t reserved_1_63 : 63; 3939215976Sjmallett uint64_t rd_clr : 1; /**< Stats registers will clear on reads */ 3940215976Sjmallett#else 3941215976Sjmallett uint64_t rd_clr : 1; 3942215976Sjmallett uint64_t reserved_1_63 : 63; 3943215976Sjmallett#endif 3944215976Sjmallett } s; 3945215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; 3946215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; 3947215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; 3948215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; 3949215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx; 3950215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1; 3951215976Sjmallett}; 3952215976Sjmalletttypedef union cvmx_agl_gmx_txx_stats_ctl cvmx_agl_gmx_txx_stats_ctl_t; 3953215976Sjmallett 3954215976Sjmallett/** 3955215976Sjmallett * cvmx_agl_gmx_tx#_thresh 3956215976Sjmallett * 3957215976Sjmallett * AGL_GMX_TX_THRESH = Packet TX Threshold 3958215976Sjmallett * 3959215976Sjmallett * 3960215976Sjmallett * Notes: 3961215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3962215976Sjmallett * 3963215976Sjmallett */ 3964215976Sjmallettunion cvmx_agl_gmx_txx_thresh 3965215976Sjmallett{ 3966215976Sjmallett uint64_t u64; 3967215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s 3968215976Sjmallett { 3969215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3970215976Sjmallett uint64_t reserved_6_63 : 58; 3971215976Sjmallett uint64_t cnt : 6; /**< Number of 16B ticks to accumulate in the TX FIFO 3972215976Sjmallett before sending on the packet interface 3973215976Sjmallett This register should be large enough to prevent 3974215976Sjmallett underflow on the packet interface and must never 3975215976Sjmallett be set below 4. This register cannot exceed the 3976215976Sjmallett the TX FIFO depth which is 128, 8B entries. */ 3977215976Sjmallett#else 3978215976Sjmallett uint64_t cnt : 6; 3979215976Sjmallett uint64_t reserved_6_63 : 58; 3980215976Sjmallett#endif 3981215976Sjmallett } s; 3982215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn52xx; 3983215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; 3984215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn56xx; 3985215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; 3986215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn63xx; 3987215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn63xxp1; 3988215976Sjmallett}; 3989215976Sjmalletttypedef union cvmx_agl_gmx_txx_thresh cvmx_agl_gmx_txx_thresh_t; 3990215976Sjmallett 3991215976Sjmallett/** 3992215976Sjmallett * cvmx_agl_gmx_tx_bp 3993215976Sjmallett * 3994215976Sjmallett * AGL_GMX_TX_BP = Packet TX BackPressure Register 3995215976Sjmallett * 3996215976Sjmallett * 3997215976Sjmallett * Notes: 3998215976Sjmallett * BP[0] will be reset when MIX0_CTL[RESET] is set to 1. 3999215976Sjmallett * BP[1] will be reset when MIX1_CTL[RESET] is set to 1. 4000215976Sjmallett */ 4001215976Sjmallettunion cvmx_agl_gmx_tx_bp 4002215976Sjmallett{ 4003215976Sjmallett uint64_t u64; 4004215976Sjmallett struct cvmx_agl_gmx_tx_bp_s 4005215976Sjmallett { 4006215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4007215976Sjmallett uint64_t reserved_2_63 : 62; 4008215976Sjmallett uint64_t bp : 2; /**< Port BackPressure status 4009215976Sjmallett 0=Port is available 4010215976Sjmallett 1=Port should be back pressured */ 4011215976Sjmallett#else 4012215976Sjmallett uint64_t bp : 2; 4013215976Sjmallett uint64_t reserved_2_63 : 62; 4014215976Sjmallett#endif 4015215976Sjmallett } s; 4016215976Sjmallett struct cvmx_agl_gmx_tx_bp_s cn52xx; 4017215976Sjmallett struct cvmx_agl_gmx_tx_bp_s cn52xxp1; 4018215976Sjmallett struct cvmx_agl_gmx_tx_bp_cn56xx 4019215976Sjmallett { 4020215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4021215976Sjmallett uint64_t reserved_1_63 : 63; 4022215976Sjmallett uint64_t bp : 1; /**< Port BackPressure status 4023215976Sjmallett 0=Port is available 4024215976Sjmallett 1=Port should be back pressured */ 4025215976Sjmallett#else 4026215976Sjmallett uint64_t bp : 1; 4027215976Sjmallett uint64_t reserved_1_63 : 63; 4028215976Sjmallett#endif 4029215976Sjmallett } cn56xx; 4030215976Sjmallett struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; 4031215976Sjmallett struct cvmx_agl_gmx_tx_bp_s cn63xx; 4032215976Sjmallett struct cvmx_agl_gmx_tx_bp_s cn63xxp1; 4033215976Sjmallett}; 4034215976Sjmalletttypedef union cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_bp_t; 4035215976Sjmallett 4036215976Sjmallett/** 4037215976Sjmallett * cvmx_agl_gmx_tx_col_attempt 4038215976Sjmallett * 4039215976Sjmallett * AGL_GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame 4040215976Sjmallett * 4041215976Sjmallett * 4042215976Sjmallett * Notes: 4043215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4044215976Sjmallett * 4045215976Sjmallett */ 4046215976Sjmallettunion cvmx_agl_gmx_tx_col_attempt 4047215976Sjmallett{ 4048215976Sjmallett uint64_t u64; 4049215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s 4050215976Sjmallett { 4051215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4052215976Sjmallett uint64_t reserved_5_63 : 59; 4053215976Sjmallett uint64_t limit : 5; /**< Collision Attempts */ 4054215976Sjmallett#else 4055215976Sjmallett uint64_t limit : 5; 4056215976Sjmallett uint64_t reserved_5_63 : 59; 4057215976Sjmallett#endif 4058215976Sjmallett } s; 4059215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; 4060215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; 4061215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; 4062215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; 4063215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn63xx; 4064215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1; 4065215976Sjmallett}; 4066215976Sjmalletttypedef union cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_col_attempt_t; 4067215976Sjmallett 4068215976Sjmallett/** 4069215976Sjmallett * cvmx_agl_gmx_tx_ifg 4070215976Sjmallett * 4071215976Sjmallett * Common 4072215976Sjmallett * 4073215976Sjmallett * 4074215976Sjmallett * AGL_GMX_TX_IFG = Packet TX Interframe Gap 4075215976Sjmallett * 4076215976Sjmallett * Notes: 4077215976Sjmallett * Notes: 4078215976Sjmallett * * Programming IFG1 and IFG2. 4079215976Sjmallett * 4080215976Sjmallett * For half-duplex systems that require IEEE 802.3 compatibility, IFG1 must 4081215976Sjmallett * be in the range of 1-8, IFG2 must be in the range of 4-12, and the 4082215976Sjmallett * IFG1+IFG2 sum must be 12. 4083215976Sjmallett * 4084215976Sjmallett * For full-duplex systems that require IEEE 802.3 compatibility, IFG1 must 4085215976Sjmallett * be in the range of 1-11, IFG2 must be in the range of 1-11, and the 4086215976Sjmallett * IFG1+IFG2 sum must be 12. 4087215976Sjmallett * 4088215976Sjmallett * For all other systems, IFG1 and IFG2 can be any value in the range of 4089215976Sjmallett * 1-15. Allowing for a total possible IFG sum of 2-30. 4090215976Sjmallett * 4091215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4092215976Sjmallett */ 4093215976Sjmallettunion cvmx_agl_gmx_tx_ifg 4094215976Sjmallett{ 4095215976Sjmallett uint64_t u64; 4096215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s 4097215976Sjmallett { 4098215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4099215976Sjmallett uint64_t reserved_8_63 : 56; 4100215976Sjmallett uint64_t ifg2 : 4; /**< 1/3 of the interframe gap timing 4101215976Sjmallett If CRS is detected during IFG2, then the 4102215976Sjmallett interFrameSpacing timer is not reset and a frame 4103215976Sjmallett is transmited once the timer expires. */ 4104215976Sjmallett uint64_t ifg1 : 4; /**< 2/3 of the interframe gap timing 4105215976Sjmallett If CRS is detected during IFG1, then the 4106215976Sjmallett interFrameSpacing timer is reset and a frame is 4107215976Sjmallett not transmited. */ 4108215976Sjmallett#else 4109215976Sjmallett uint64_t ifg1 : 4; 4110215976Sjmallett uint64_t ifg2 : 4; 4111215976Sjmallett uint64_t reserved_8_63 : 56; 4112215976Sjmallett#endif 4113215976Sjmallett } s; 4114215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn52xx; 4115215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; 4116215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn56xx; 4117215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; 4118215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn63xx; 4119215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn63xxp1; 4120215976Sjmallett}; 4121215976Sjmalletttypedef union cvmx_agl_gmx_tx_ifg cvmx_agl_gmx_tx_ifg_t; 4122215976Sjmallett 4123215976Sjmallett/** 4124215976Sjmallett * cvmx_agl_gmx_tx_int_en 4125215976Sjmallett * 4126215976Sjmallett * AGL_GMX_TX_INT_EN = Interrupt Enable 4127215976Sjmallett * 4128215976Sjmallett * 4129215976Sjmallett * Notes: 4130215976Sjmallett * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1. 4131215976Sjmallett * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1. 4132215976Sjmallett * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1. 4133215976Sjmallett */ 4134215976Sjmallettunion cvmx_agl_gmx_tx_int_en 4135215976Sjmallett{ 4136215976Sjmallett uint64_t u64; 4137215976Sjmallett struct cvmx_agl_gmx_tx_int_en_s 4138215976Sjmallett { 4139215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4140215976Sjmallett uint64_t reserved_22_63 : 42; 4141215976Sjmallett uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be 4142215976Sjmallett sent due to XSCOL */ 4143215976Sjmallett uint64_t reserved_18_19 : 2; 4144215976Sjmallett uint64_t late_col : 2; /**< TX Late Collision */ 4145215976Sjmallett uint64_t reserved_14_15 : 2; 4146215976Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral (halfdup mode only) */ 4147215976Sjmallett uint64_t reserved_10_11 : 2; 4148215976Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions (halfdup mode only) */ 4149215976Sjmallett uint64_t reserved_4_7 : 4; 4150215976Sjmallett uint64_t undflw : 2; /**< TX Underflow */ 4151215976Sjmallett uint64_t reserved_1_1 : 1; 4152215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4153215976Sjmallett#else 4154215976Sjmallett uint64_t pko_nxa : 1; 4155215976Sjmallett uint64_t reserved_1_1 : 1; 4156215976Sjmallett uint64_t undflw : 2; 4157215976Sjmallett uint64_t reserved_4_7 : 4; 4158215976Sjmallett uint64_t xscol : 2; 4159215976Sjmallett uint64_t reserved_10_11 : 2; 4160215976Sjmallett uint64_t xsdef : 2; 4161215976Sjmallett uint64_t reserved_14_15 : 2; 4162215976Sjmallett uint64_t late_col : 2; 4163215976Sjmallett uint64_t reserved_18_19 : 2; 4164215976Sjmallett uint64_t ptp_lost : 2; 4165215976Sjmallett uint64_t reserved_22_63 : 42; 4166215976Sjmallett#endif 4167215976Sjmallett } s; 4168215976Sjmallett struct cvmx_agl_gmx_tx_int_en_cn52xx 4169215976Sjmallett { 4170215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4171215976Sjmallett uint64_t reserved_18_63 : 46; 4172215976Sjmallett uint64_t late_col : 2; /**< TX Late Collision */ 4173215976Sjmallett uint64_t reserved_14_15 : 2; 4174215976Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral (MII/halfdup mode only) */ 4175215976Sjmallett uint64_t reserved_10_11 : 2; 4176215976Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions (MII/halfdup mode only) */ 4177215976Sjmallett uint64_t reserved_4_7 : 4; 4178215976Sjmallett uint64_t undflw : 2; /**< TX Underflow (MII mode only) */ 4179215976Sjmallett uint64_t reserved_1_1 : 1; 4180215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4181215976Sjmallett#else 4182215976Sjmallett uint64_t pko_nxa : 1; 4183215976Sjmallett uint64_t reserved_1_1 : 1; 4184215976Sjmallett uint64_t undflw : 2; 4185215976Sjmallett uint64_t reserved_4_7 : 4; 4186215976Sjmallett uint64_t xscol : 2; 4187215976Sjmallett uint64_t reserved_10_11 : 2; 4188215976Sjmallett uint64_t xsdef : 2; 4189215976Sjmallett uint64_t reserved_14_15 : 2; 4190215976Sjmallett uint64_t late_col : 2; 4191215976Sjmallett uint64_t reserved_18_63 : 46; 4192215976Sjmallett#endif 4193215976Sjmallett } cn52xx; 4194215976Sjmallett struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1; 4195215976Sjmallett struct cvmx_agl_gmx_tx_int_en_cn56xx 4196215976Sjmallett { 4197215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4198215976Sjmallett uint64_t reserved_17_63 : 47; 4199215976Sjmallett uint64_t late_col : 1; /**< TX Late Collision */ 4200215976Sjmallett uint64_t reserved_13_15 : 3; 4201215976Sjmallett uint64_t xsdef : 1; /**< TX Excessive deferral (MII/halfdup mode only) */ 4202215976Sjmallett uint64_t reserved_9_11 : 3; 4203215976Sjmallett uint64_t xscol : 1; /**< TX Excessive collisions (MII/halfdup mode only) */ 4204215976Sjmallett uint64_t reserved_3_7 : 5; 4205215976Sjmallett uint64_t undflw : 1; /**< TX Underflow (MII mode only) */ 4206215976Sjmallett uint64_t reserved_1_1 : 1; 4207215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4208215976Sjmallett#else 4209215976Sjmallett uint64_t pko_nxa : 1; 4210215976Sjmallett uint64_t reserved_1_1 : 1; 4211215976Sjmallett uint64_t undflw : 1; 4212215976Sjmallett uint64_t reserved_3_7 : 5; 4213215976Sjmallett uint64_t xscol : 1; 4214215976Sjmallett uint64_t reserved_9_11 : 3; 4215215976Sjmallett uint64_t xsdef : 1; 4216215976Sjmallett uint64_t reserved_13_15 : 3; 4217215976Sjmallett uint64_t late_col : 1; 4218215976Sjmallett uint64_t reserved_17_63 : 47; 4219215976Sjmallett#endif 4220215976Sjmallett } cn56xx; 4221215976Sjmallett struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; 4222215976Sjmallett struct cvmx_agl_gmx_tx_int_en_s cn63xx; 4223215976Sjmallett struct cvmx_agl_gmx_tx_int_en_s cn63xxp1; 4224215976Sjmallett}; 4225215976Sjmalletttypedef union cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_en_t; 4226215976Sjmallett 4227215976Sjmallett/** 4228215976Sjmallett * cvmx_agl_gmx_tx_int_reg 4229215976Sjmallett * 4230215976Sjmallett * AGL_GMX_TX_INT_REG = Interrupt Register 4231215976Sjmallett * 4232215976Sjmallett * 4233215976Sjmallett * Notes: 4234215976Sjmallett * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1. 4235215976Sjmallett * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1. 4236215976Sjmallett * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1. 4237215976Sjmallett */ 4238215976Sjmallettunion cvmx_agl_gmx_tx_int_reg 4239215976Sjmallett{ 4240215976Sjmallett uint64_t u64; 4241215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_s 4242215976Sjmallett { 4243215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4244215976Sjmallett uint64_t reserved_22_63 : 42; 4245215976Sjmallett uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be 4246215976Sjmallett sent due to XSCOL */ 4247215976Sjmallett uint64_t reserved_18_19 : 2; 4248215976Sjmallett uint64_t late_col : 2; /**< TX Late Collision */ 4249215976Sjmallett uint64_t reserved_14_15 : 2; 4250215976Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral (halfdup mode only) */ 4251215976Sjmallett uint64_t reserved_10_11 : 2; 4252215976Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions (halfdup mode only) */ 4253215976Sjmallett uint64_t reserved_4_7 : 4; 4254215976Sjmallett uint64_t undflw : 2; /**< TX Underflow */ 4255215976Sjmallett uint64_t reserved_1_1 : 1; 4256215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4257215976Sjmallett#else 4258215976Sjmallett uint64_t pko_nxa : 1; 4259215976Sjmallett uint64_t reserved_1_1 : 1; 4260215976Sjmallett uint64_t undflw : 2; 4261215976Sjmallett uint64_t reserved_4_7 : 4; 4262215976Sjmallett uint64_t xscol : 2; 4263215976Sjmallett uint64_t reserved_10_11 : 2; 4264215976Sjmallett uint64_t xsdef : 2; 4265215976Sjmallett uint64_t reserved_14_15 : 2; 4266215976Sjmallett uint64_t late_col : 2; 4267215976Sjmallett uint64_t reserved_18_19 : 2; 4268215976Sjmallett uint64_t ptp_lost : 2; 4269215976Sjmallett uint64_t reserved_22_63 : 42; 4270215976Sjmallett#endif 4271215976Sjmallett } s; 4272215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_cn52xx 4273215976Sjmallett { 4274215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4275215976Sjmallett uint64_t reserved_18_63 : 46; 4276215976Sjmallett uint64_t late_col : 2; /**< TX Late Collision */ 4277215976Sjmallett uint64_t reserved_14_15 : 2; 4278215976Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral (MII/halfdup mode only) */ 4279215976Sjmallett uint64_t reserved_10_11 : 2; 4280215976Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions (MII/halfdup mode only) */ 4281215976Sjmallett uint64_t reserved_4_7 : 4; 4282215976Sjmallett uint64_t undflw : 2; /**< TX Underflow (MII mode only) */ 4283215976Sjmallett uint64_t reserved_1_1 : 1; 4284215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4285215976Sjmallett#else 4286215976Sjmallett uint64_t pko_nxa : 1; 4287215976Sjmallett uint64_t reserved_1_1 : 1; 4288215976Sjmallett uint64_t undflw : 2; 4289215976Sjmallett uint64_t reserved_4_7 : 4; 4290215976Sjmallett uint64_t xscol : 2; 4291215976Sjmallett uint64_t reserved_10_11 : 2; 4292215976Sjmallett uint64_t xsdef : 2; 4293215976Sjmallett uint64_t reserved_14_15 : 2; 4294215976Sjmallett uint64_t late_col : 2; 4295215976Sjmallett uint64_t reserved_18_63 : 46; 4296215976Sjmallett#endif 4297215976Sjmallett } cn52xx; 4298215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1; 4299215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_cn56xx 4300215976Sjmallett { 4301215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4302215976Sjmallett uint64_t reserved_17_63 : 47; 4303215976Sjmallett uint64_t late_col : 1; /**< TX Late Collision */ 4304215976Sjmallett uint64_t reserved_13_15 : 3; 4305215976Sjmallett uint64_t xsdef : 1; /**< TX Excessive deferral (MII/halfdup mode only) */ 4306215976Sjmallett uint64_t reserved_9_11 : 3; 4307215976Sjmallett uint64_t xscol : 1; /**< TX Excessive collisions (MII/halfdup mode only) */ 4308215976Sjmallett uint64_t reserved_3_7 : 5; 4309215976Sjmallett uint64_t undflw : 1; /**< TX Underflow (MII mode only) */ 4310215976Sjmallett uint64_t reserved_1_1 : 1; 4311215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4312215976Sjmallett#else 4313215976Sjmallett uint64_t pko_nxa : 1; 4314215976Sjmallett uint64_t reserved_1_1 : 1; 4315215976Sjmallett uint64_t undflw : 1; 4316215976Sjmallett uint64_t reserved_3_7 : 5; 4317215976Sjmallett uint64_t xscol : 1; 4318215976Sjmallett uint64_t reserved_9_11 : 3; 4319215976Sjmallett uint64_t xsdef : 1; 4320215976Sjmallett uint64_t reserved_13_15 : 3; 4321215976Sjmallett uint64_t late_col : 1; 4322215976Sjmallett uint64_t reserved_17_63 : 47; 4323215976Sjmallett#endif 4324215976Sjmallett } cn56xx; 4325215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; 4326215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_s cn63xx; 4327215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1; 4328215976Sjmallett}; 4329215976Sjmalletttypedef union cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_int_reg_t; 4330215976Sjmallett 4331215976Sjmallett/** 4332215976Sjmallett * cvmx_agl_gmx_tx_jam 4333215976Sjmallett * 4334215976Sjmallett * AGL_GMX_TX_JAM = Packet TX Jam Pattern 4335215976Sjmallett * 4336215976Sjmallett * 4337215976Sjmallett * Notes: 4338215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4339215976Sjmallett * 4340215976Sjmallett */ 4341215976Sjmallettunion cvmx_agl_gmx_tx_jam 4342215976Sjmallett{ 4343215976Sjmallett uint64_t u64; 4344215976Sjmallett struct cvmx_agl_gmx_tx_jam_s 4345215976Sjmallett { 4346215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4347215976Sjmallett uint64_t reserved_8_63 : 56; 4348215976Sjmallett uint64_t jam : 8; /**< Jam pattern */ 4349215976Sjmallett#else 4350215976Sjmallett uint64_t jam : 8; 4351215976Sjmallett uint64_t reserved_8_63 : 56; 4352215976Sjmallett#endif 4353215976Sjmallett } s; 4354215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn52xx; 4355215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn52xxp1; 4356215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn56xx; 4357215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn56xxp1; 4358215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn63xx; 4359215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn63xxp1; 4360215976Sjmallett}; 4361215976Sjmalletttypedef union cvmx_agl_gmx_tx_jam cvmx_agl_gmx_tx_jam_t; 4362215976Sjmallett 4363215976Sjmallett/** 4364215976Sjmallett * cvmx_agl_gmx_tx_lfsr 4365215976Sjmallett * 4366215976Sjmallett * AGL_GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff 4367215976Sjmallett * 4368215976Sjmallett * 4369215976Sjmallett * Notes: 4370215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4371215976Sjmallett * 4372215976Sjmallett */ 4373215976Sjmallettunion cvmx_agl_gmx_tx_lfsr 4374215976Sjmallett{ 4375215976Sjmallett uint64_t u64; 4376215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s 4377215976Sjmallett { 4378215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4379215976Sjmallett uint64_t reserved_16_63 : 48; 4380215976Sjmallett uint64_t lfsr : 16; /**< The current state of the LFSR used to feed random 4381215976Sjmallett numbers to compute truncated binary exponential 4382215976Sjmallett backoff. */ 4383215976Sjmallett#else 4384215976Sjmallett uint64_t lfsr : 16; 4385215976Sjmallett uint64_t reserved_16_63 : 48; 4386215976Sjmallett#endif 4387215976Sjmallett } s; 4388215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn52xx; 4389215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; 4390215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn56xx; 4391215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; 4392215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn63xx; 4393215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1; 4394215976Sjmallett}; 4395215976Sjmalletttypedef union cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_lfsr_t; 4396215976Sjmallett 4397215976Sjmallett/** 4398215976Sjmallett * cvmx_agl_gmx_tx_ovr_bp 4399215976Sjmallett * 4400215976Sjmallett * AGL_GMX_TX_OVR_BP = Packet TX Override BackPressure 4401215976Sjmallett * 4402215976Sjmallett * 4403215976Sjmallett * Notes: 4404215976Sjmallett * IGN_FULL[0], BP[0], EN[0] will be reset when MIX0_CTL[RESET] is set to 1. 4405215976Sjmallett * IGN_FULL[1], BP[1], EN[1] will be reset when MIX1_CTL[RESET] is set to 1. 4406215976Sjmallett */ 4407215976Sjmallettunion cvmx_agl_gmx_tx_ovr_bp 4408215976Sjmallett{ 4409215976Sjmallett uint64_t u64; 4410215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s 4411215976Sjmallett { 4412215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4413215976Sjmallett uint64_t reserved_10_63 : 54; 4414215976Sjmallett uint64_t en : 2; /**< Per port Enable back pressure override */ 4415215976Sjmallett uint64_t reserved_6_7 : 2; 4416215976Sjmallett uint64_t bp : 2; /**< Port BackPressure status to use 4417215976Sjmallett 0=Port is available 4418215976Sjmallett 1=Port should be back pressured */ 4419215976Sjmallett uint64_t reserved_2_3 : 2; 4420215976Sjmallett uint64_t ign_full : 2; /**< Ignore the RX FIFO full when computing BP */ 4421215976Sjmallett#else 4422215976Sjmallett uint64_t ign_full : 2; 4423215976Sjmallett uint64_t reserved_2_3 : 2; 4424215976Sjmallett uint64_t bp : 2; 4425215976Sjmallett uint64_t reserved_6_7 : 2; 4426215976Sjmallett uint64_t en : 2; 4427215976Sjmallett uint64_t reserved_10_63 : 54; 4428215976Sjmallett#endif 4429215976Sjmallett } s; 4430215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; 4431215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; 4432215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_cn56xx 4433215976Sjmallett { 4434215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4435215976Sjmallett uint64_t reserved_9_63 : 55; 4436215976Sjmallett uint64_t en : 1; /**< Per port Enable back pressure override */ 4437215976Sjmallett uint64_t reserved_5_7 : 3; 4438215976Sjmallett uint64_t bp : 1; /**< Port BackPressure status to use 4439215976Sjmallett 0=Port is available 4440215976Sjmallett 1=Port should be back pressured */ 4441215976Sjmallett uint64_t reserved_1_3 : 3; 4442215976Sjmallett uint64_t ign_full : 1; /**< Ignore the RX FIFO full when computing BP */ 4443215976Sjmallett#else 4444215976Sjmallett uint64_t ign_full : 1; 4445215976Sjmallett uint64_t reserved_1_3 : 3; 4446215976Sjmallett uint64_t bp : 1; 4447215976Sjmallett uint64_t reserved_5_7 : 3; 4448215976Sjmallett uint64_t en : 1; 4449215976Sjmallett uint64_t reserved_9_63 : 55; 4450215976Sjmallett#endif 4451215976Sjmallett } cn56xx; 4452215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; 4453215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx; 4454215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1; 4455215976Sjmallett}; 4456215976Sjmalletttypedef union cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_ovr_bp_t; 4457215976Sjmallett 4458215976Sjmallett/** 4459215976Sjmallett * cvmx_agl_gmx_tx_pause_pkt_dmac 4460215976Sjmallett * 4461215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field 4462215976Sjmallett * 4463215976Sjmallett * 4464215976Sjmallett * Notes: 4465215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4466215976Sjmallett * 4467215976Sjmallett */ 4468215976Sjmallettunion cvmx_agl_gmx_tx_pause_pkt_dmac 4469215976Sjmallett{ 4470215976Sjmallett uint64_t u64; 4471215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s 4472215976Sjmallett { 4473215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4474215976Sjmallett uint64_t reserved_48_63 : 16; 4475215976Sjmallett uint64_t dmac : 48; /**< The DMAC field placed is outbnd pause pkts */ 4476215976Sjmallett#else 4477215976Sjmallett uint64_t dmac : 48; 4478215976Sjmallett uint64_t reserved_48_63 : 16; 4479215976Sjmallett#endif 4480215976Sjmallett } s; 4481215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; 4482215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; 4483215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; 4484215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; 4485215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx; 4486215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1; 4487215976Sjmallett}; 4488215976Sjmalletttypedef union cvmx_agl_gmx_tx_pause_pkt_dmac cvmx_agl_gmx_tx_pause_pkt_dmac_t; 4489215976Sjmallett 4490215976Sjmallett/** 4491215976Sjmallett * cvmx_agl_gmx_tx_pause_pkt_type 4492215976Sjmallett * 4493215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_TYPE = Packet TX Pause Packet TYPE field 4494215976Sjmallett * 4495215976Sjmallett * 4496215976Sjmallett * Notes: 4497215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4498215976Sjmallett * 4499215976Sjmallett */ 4500215976Sjmallettunion cvmx_agl_gmx_tx_pause_pkt_type 4501215976Sjmallett{ 4502215976Sjmallett uint64_t u64; 4503215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s 4504215976Sjmallett { 4505215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4506215976Sjmallett uint64_t reserved_16_63 : 48; 4507215976Sjmallett uint64_t type : 16; /**< The TYPE field placed is outbnd pause pkts */ 4508215976Sjmallett#else 4509215976Sjmallett uint64_t type : 16; 4510215976Sjmallett uint64_t reserved_16_63 : 48; 4511215976Sjmallett#endif 4512215976Sjmallett } s; 4513215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; 4514215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; 4515215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; 4516215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; 4517215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx; 4518215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1; 4519215976Sjmallett}; 4520215976Sjmalletttypedef union cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_tx_pause_pkt_type_t; 4521215976Sjmallett 4522215976Sjmallett/** 4523215976Sjmallett * cvmx_agl_prt#_ctl 4524215976Sjmallett * 4525215976Sjmallett * AGL_PRT_CTL = AGL Port Control 4526215976Sjmallett * 4527215976Sjmallett * 4528215976Sjmallett * Notes: 4529215976Sjmallett * AGL_PRT0_CTL will be reset when MIX0_CTL[RESET] is set to 1. 4530215976Sjmallett * AGL_PRT1_CTL will be reset when MIX1_CTL[RESET] is set to 1. 4531215976Sjmallett */ 4532215976Sjmallettunion cvmx_agl_prtx_ctl 4533215976Sjmallett{ 4534215976Sjmallett uint64_t u64; 4535215976Sjmallett struct cvmx_agl_prtx_ctl_s 4536215976Sjmallett { 4537215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4538215976Sjmallett uint64_t drv_byp : 1; /**< Bypass the compensation controller and use 4539215976Sjmallett DRV_NCTL and DRV_PCTL 4540215976Sjmallett Note: the reset value was changed from pass1 4541215976Sjmallett to pass2. */ 4542215976Sjmallett uint64_t reserved_62_62 : 1; 4543215976Sjmallett uint64_t cmp_pctl : 6; /**< PCTL drive strength from the compensation ctl */ 4544215976Sjmallett uint64_t reserved_54_55 : 2; 4545215976Sjmallett uint64_t cmp_nctl : 6; /**< NCTL drive strength from the compensation ctl */ 4546215976Sjmallett uint64_t reserved_46_47 : 2; 4547215976Sjmallett uint64_t drv_pctl : 6; /**< PCTL drive strength to use in bypass mode 4548215976Sjmallett Reset value of 19 is for 50 ohm termination */ 4549215976Sjmallett uint64_t reserved_38_39 : 2; 4550215976Sjmallett uint64_t drv_nctl : 6; /**< NCTL drive strength to use in bypass mode 4551215976Sjmallett Reset value of 15 is for 50 ohm termination */ 4552215976Sjmallett uint64_t reserved_29_31 : 3; 4553215976Sjmallett uint64_t clk_set : 5; /**< The clock delay as determined by the DLL */ 4554215976Sjmallett uint64_t clkrx_byp : 1; /**< Bypass the RX clock delay setting 4555215976Sjmallett Skews RXC from RXD,RXCTL in RGMII mode 4556215976Sjmallett By default, HW internally shifts the RXC clock 4557215976Sjmallett to sample RXD,RXCTL assuming clock and data and 4558215976Sjmallett sourced synchronously from the link partner. 4559215976Sjmallett In MII mode, the CLKRX_BYP is forced to 1. */ 4560215976Sjmallett uint64_t reserved_21_22 : 2; 4561215976Sjmallett uint64_t clkrx_set : 5; /**< RX clock delay setting to use in bypass mode 4562215976Sjmallett Skews RXC from RXD in RGMII mode */ 4563215976Sjmallett uint64_t clktx_byp : 1; /**< Bypass the TX clock delay setting 4564215976Sjmallett Skews TXC from TXD,TXCTL in RGMII mode 4565215976Sjmallett Skews RXC from RXD,RXCTL in RGMII mode 4566215976Sjmallett By default, clock and data and sourced 4567215976Sjmallett synchronously. 4568215976Sjmallett In MII mode, the CLKRX_BYP is forced to 1. */ 4569215976Sjmallett uint64_t reserved_13_14 : 2; 4570215976Sjmallett uint64_t clktx_set : 5; /**< TX clock delay setting to use in bypass mode 4571215976Sjmallett Skews TXC from TXD in RGMII mode */ 4572215976Sjmallett uint64_t reserved_5_7 : 3; 4573215976Sjmallett uint64_t dllrst : 1; /**< DLL Reset */ 4574215976Sjmallett uint64_t comp : 1; /**< Compensation Enable */ 4575215976Sjmallett uint64_t enable : 1; /**< Port Enable 4576215976Sjmallett Note: the reset value was changed from pass1 4577215976Sjmallett to pass2. */ 4578215976Sjmallett uint64_t clkrst : 1; /**< Clock Tree Reset */ 4579215976Sjmallett uint64_t mode : 1; /**< Port Mode 4580215976Sjmallett MODE must be set the same for all ports in which 4581215976Sjmallett AGL_PRTx_CTL[ENABLE] is set. 4582215976Sjmallett 0=RGMII 4583215976Sjmallett 1=MII */ 4584215976Sjmallett#else 4585215976Sjmallett uint64_t mode : 1; 4586215976Sjmallett uint64_t clkrst : 1; 4587215976Sjmallett uint64_t enable : 1; 4588215976Sjmallett uint64_t comp : 1; 4589215976Sjmallett uint64_t dllrst : 1; 4590215976Sjmallett uint64_t reserved_5_7 : 3; 4591215976Sjmallett uint64_t clktx_set : 5; 4592215976Sjmallett uint64_t reserved_13_14 : 2; 4593215976Sjmallett uint64_t clktx_byp : 1; 4594215976Sjmallett uint64_t clkrx_set : 5; 4595215976Sjmallett uint64_t reserved_21_22 : 2; 4596215976Sjmallett uint64_t clkrx_byp : 1; 4597215976Sjmallett uint64_t clk_set : 5; 4598215976Sjmallett uint64_t reserved_29_31 : 3; 4599215976Sjmallett uint64_t drv_nctl : 6; 4600215976Sjmallett uint64_t reserved_38_39 : 2; 4601215976Sjmallett uint64_t drv_pctl : 6; 4602215976Sjmallett uint64_t reserved_46_47 : 2; 4603215976Sjmallett uint64_t cmp_nctl : 6; 4604215976Sjmallett uint64_t reserved_54_55 : 2; 4605215976Sjmallett uint64_t cmp_pctl : 6; 4606215976Sjmallett uint64_t reserved_62_62 : 1; 4607215976Sjmallett uint64_t drv_byp : 1; 4608215976Sjmallett#endif 4609215976Sjmallett } s; 4610215976Sjmallett struct cvmx_agl_prtx_ctl_s cn63xx; 4611215976Sjmallett struct cvmx_agl_prtx_ctl_s cn63xxp1; 4612215976Sjmallett}; 4613215976Sjmalletttypedef union cvmx_agl_prtx_ctl cvmx_agl_prtx_ctl_t; 4614215976Sjmallett 4615215976Sjmallett#endif 4616