1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2008, Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35#ifndef _SYS_PMC_H_ 36#define _SYS_PMC_H_ 37 38#include <dev/hwpmc/pmc_events.h> 39#include <sys/proc.h> 40#include <sys/counter.h> 41#include <machine/pmc_mdep.h> 42#include <machine/profile.h> 43#ifdef _KERNEL 44#include <sys/epoch.h> 45#include <ck_queue.h> 46#endif 47 48#define PMC_MODULE_NAME "hwpmc" 49#define PMC_NAME_MAX 64 /* HW counter name size */ 50#define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 51 52/* 53 * Kernel<->userland API version number [MMmmpppp] 54 * 55 * Major numbers are to be incremented when an incompatible change to 56 * the ABI occurs that older clients will not be able to handle. 57 * 58 * Minor numbers are incremented when a backwards compatible change 59 * occurs that allows older correct programs to run unchanged. For 60 * example, when support for a new PMC type is added. 61 * 62 * The patch version is incremented for every bug fix. 63 */ 64#define PMC_VERSION_MAJOR 0x09 65#define PMC_VERSION_MINOR 0x03 66#define PMC_VERSION_PATCH 0x0000 67 68#define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 69 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 70 71#define PMC_CPUID_LEN 64 72/* cpu model name for pmu lookup */ 73extern char pmc_cpuid[PMC_CPUID_LEN]; 74 75/* 76 * Kinds of CPUs known. 77 * 78 * We keep track of CPU variants that need to be distinguished in 79 * some way for PMC operations. CPU names are grouped by manufacturer 80 * and numbered sparsely in order to minimize changes to the ABI involved 81 * when new CPUs are added. 82 */ 83 84#define __PMC_CPUS() \ 85 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ 86 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 87 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \ 88 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \ 89 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \ 90 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \ 91 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \ 92 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \ 93 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \ 94 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 95 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 96 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 97 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 98 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 99 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 100 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 101 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 102 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 103 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 104 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 105 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 106 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 107 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 108 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ 109 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ 110 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ 111 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ 112 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ 113 __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ 114 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ 115 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ 116 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ 117 __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ 118 __PMC_CPU(MIPS_BERI, 0x203, "BERI") \ 119 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 120 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ 121 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 122 __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ 123 __PMC_CPU(GENERIC, 0x400, "Generic") \ 124 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ 125 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ 126 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ 127 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ 128 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ 129 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ 130 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ 131 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ 132 __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") 133 134enum pmc_cputype { 135#undef __PMC_CPU 136#define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 137 __PMC_CPUS() 138}; 139 140#define PMC_CPU_FIRST PMC_CPU_AMD_K7 141#define PMC_CPU_LAST PMC_CPU_GENERIC 142 143/* 144 * Classes of PMCs 145 */ 146 147#define __PMC_CLASSES() \ 148 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ 149 __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ 150 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ 151 __PMC_CLASS(P5, 0x03, "Intel Pentium counters") \ 152 __PMC_CLASS(P6, 0x04, "Intel Pentium Pro counters") \ 153 __PMC_CLASS(P4, 0x05, "Intel Pentium-IV counters") \ 154 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ 155 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ 156 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ 157 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ 158 __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ 159 __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \ 160 __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \ 161 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ 162 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ 163 __PMC_CLASS(SOFT, 0x0F, "Software events") \ 164 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ 165 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ 166 __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \ 167 __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ 168 __PMC_CLASS(BERI, 0x14, "MIPS BERI") \ 169 __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") 170 171enum pmc_class { 172#undef __PMC_CLASS 173#define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V, 174 __PMC_CLASSES() 175}; 176 177#define PMC_CLASS_FIRST PMC_CLASS_TSC 178#define PMC_CLASS_LAST PMC_CLASS_POWER8 179 180/* 181 * A PMC can be in the following states: 182 * 183 * Hardware states: 184 * DISABLED -- administratively prohibited from being used. 185 * FREE -- HW available for use 186 * Software states: 187 * ALLOCATED -- allocated 188 * STOPPED -- allocated, but not counting events 189 * RUNNING -- allocated, and in operation; 'pm_runcount' 190 * holds the number of CPUs using this PMC at 191 * a given instant 192 * DELETED -- being destroyed 193 */ 194 195#define __PMC_HWSTATES() \ 196 __PMC_STATE(DISABLED) \ 197 __PMC_STATE(FREE) 198 199#define __PMC_SWSTATES() \ 200 __PMC_STATE(ALLOCATED) \ 201 __PMC_STATE(STOPPED) \ 202 __PMC_STATE(RUNNING) \ 203 __PMC_STATE(DELETED) 204 205#define __PMC_STATES() \ 206 __PMC_HWSTATES() \ 207 __PMC_SWSTATES() 208 209enum pmc_state { 210#undef __PMC_STATE 211#define __PMC_STATE(S) PMC_STATE_##S, 212 __PMC_STATES() 213 __PMC_STATE(MAX) 214}; 215 216#define PMC_STATE_FIRST PMC_STATE_DISABLED 217#define PMC_STATE_LAST PMC_STATE_DELETED 218 219/* 220 * An allocated PMC may used as a 'global' counter or as a 221 * 'thread-private' one. Each such mode of use can be in either 222 * statistical sampling mode or in counting mode. Thus a PMC in use 223 * 224 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 225 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 226 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 227 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 228 * 229 * Statistical profiling modes rely on the PMC periodically delivering 230 * a interrupt to the CPU (when the configured number of events have 231 * been measured), so the PMC must have the ability to generate 232 * interrupts. 233 * 234 * In counting modes, the PMC counts its configured events, with the 235 * value of the PMC being read whenever needed by its owner process. 236 * 237 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 238 * to be thread private and count events only when the profiled thread 239 * actually executes on the CPU. 240 * 241 * The system-wide "global" modes keep the PMCs running all the time 242 * and are used to measure the behaviour of the whole system. 243 */ 244 245#define __PMC_MODES() \ 246 __PMC_MODE(SS, 0) \ 247 __PMC_MODE(SC, 1) \ 248 __PMC_MODE(TS, 2) \ 249 __PMC_MODE(TC, 3) 250 251enum pmc_mode { 252#undef __PMC_MODE 253#define __PMC_MODE(M,N) PMC_MODE_##M = N, 254 __PMC_MODES() 255}; 256 257#define PMC_MODE_FIRST PMC_MODE_SS 258#define PMC_MODE_LAST PMC_MODE_TC 259 260#define PMC_IS_COUNTING_MODE(mode) \ 261 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 262#define PMC_IS_SYSTEM_MODE(mode) \ 263 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 264#define PMC_IS_SAMPLING_MODE(mode) \ 265 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 266#define PMC_IS_VIRTUAL_MODE(mode) \ 267 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 268 269/* 270 * PMC row disposition 271 */ 272 273#define __PMC_DISPOSITIONS(N) \ 274 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 275 __PMC_DISP(FREE) /* free/available */ \ 276 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 277 __PMC_DISP(UNKNOWN) /* sentinel */ 278 279enum pmc_disp { 280#undef __PMC_DISP 281#define __PMC_DISP(D) PMC_DISP_##D , 282 __PMC_DISPOSITIONS() 283}; 284 285#define PMC_DISP_FIRST PMC_DISP_STANDALONE 286#define PMC_DISP_LAST PMC_DISP_THREAD 287 288/* 289 * Counter capabilities 290 * 291 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 292 */ 293 294#define __PMC_CAPS() \ 295 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 296 __PMC_CAP(USER, 1, "count user-mode events") \ 297 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 298 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 299 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 300 __PMC_CAP(READ, 5, "read PMC counter") \ 301 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 302 __PMC_CAP(INVERT, 7, "invert comparison sense") \ 303 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 304 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 305 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 306 __PMC_CAP(CASCADE, 11, "cascade counters") 307 308enum pmc_caps 309{ 310#undef __PMC_CAP 311#define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 312 __PMC_CAPS() 313}; 314 315#define PMC_CAP_FIRST PMC_CAP_INTERRUPT 316#define PMC_CAP_LAST PMC_CAP_CASCADE 317 318/* 319 * PMC Event Numbers 320 * 321 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 322 */ 323 324enum pmc_event { 325#undef __PMC_EV 326#undef __PMC_EV_BLOCK 327#define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 328#define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 329 __PMC_EVENTS() 330}; 331 332/* 333 * PMC SYSCALL INTERFACE 334 */ 335 336/* 337 * "PMC_OPS" -- these are the commands recognized by the kernel 338 * module, and are used when performing a system call from userland. 339 */ 340#define __PMC_OPS() \ 341 __PMC_OP(CONFIGURELOG, "Set log file") \ 342 __PMC_OP(FLUSHLOG, "Flush log file") \ 343 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 344 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 345 __PMC_OP(GETMODULEVERSION, "Get module version") \ 346 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 347 __PMC_OP(PMCADMIN, "Set PMC state") \ 348 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 349 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 350 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 351 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 352 __PMC_OP(PMCRELEASE, "Release a PMC") \ 353 __PMC_OP(PMCRW, "Read/Set a PMC") \ 354 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 355 __PMC_OP(PMCSTART, "Start a PMC") \ 356 __PMC_OP(PMCSTOP, "Stop a PMC") \ 357 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 358 __PMC_OP(CLOSELOG, "Close log file") \ 359 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") 360 361enum pmc_ops { 362#undef __PMC_OP 363#define __PMC_OP(N, D) PMC_OP_##N, 364 __PMC_OPS() 365}; 366 367/* 368 * Flags used in operations on PMCs. 369 */ 370 371#define PMC_F_UNUSED1 0x00000001 /* unused */ 372#define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 373#define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 374#define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 375#define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 376#define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 377 378/* V2 API */ 379#define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 380#define PMC_F_USERCALLCHAIN 0x00000100 /*OP ALLOCATE use userspace stack */ 381 382/* internal flags */ 383#define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 384#define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 385#define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 386 387#define PMC_CALLCHAIN_DEPTH_MAX 512 388 389#define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 390 391/* 392 * Cookies used to denote allocated PMCs, and the values of PMCs. 393 */ 394 395typedef uint32_t pmc_id_t; 396typedef uint64_t pmc_value_t; 397 398#define PMC_ID_INVALID (~ (pmc_id_t) 0) 399 400/* 401 * PMC IDs have the following format: 402 * 403 * +-----------------------+-------+-----------+ 404 * | CPU | PMC MODE | CLASS | ROW INDEX | 405 * +-----------------------+-------+-----------+ 406 * 407 * where CPU is 12 bits, MODE 8, CLASS 4, and ROW INDEX 8 Field 'CPU' 408 * is set to the requested CPU for system-wide PMCs or PMC_CPU_ANY for 409 * process-mode PMCs. Field 'PMC MODE' is the allocated PMC mode. 410 * Field 'PMC CLASS' is the class of the PMC. Field 'ROW INDEX' is the 411 * row index for the PMC. 412 * 413 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 414 * number of hardware PMCs on this cpu. 415 */ 416 417#define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 418#define PMC_ID_TO_CLASS(ID) (((ID) & 0xF00) >> 8) 419#define PMC_ID_TO_MODE(ID) (((ID) & 0xFF000) >> 12) 420#define PMC_ID_TO_CPU(ID) (((ID) & 0xFFF00000) >> 20) 421#define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 422 ((((CPU) & 0xFFF) << 20) | (((MODE) & 0xFF) << 12) | \ 423 (((CLASS) & 0xF) << 8) | ((ROWINDEX) & 0xFF)) 424 425/* 426 * Data structures for system calls supported by the pmc driver. 427 */ 428 429/* 430 * OP PMCALLOCATE 431 * 432 * Allocate a PMC on the named CPU. 433 */ 434 435#define PMC_CPU_ANY ~0 436 437struct pmc_op_pmcallocate { 438 uint32_t pm_caps; /* PMC_CAP_* */ 439 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 440 enum pmc_class pm_class; /* class of PMC desired */ 441 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 442 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 443 enum pmc_mode pm_mode; /* desired mode */ 444 pmc_id_t pm_pmcid; /* [return] process pmc id */ 445 pmc_value_t pm_count; /* initial/sample count */ 446 447 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 448}; 449 450/* 451 * OP PMCADMIN 452 * 453 * Set the administrative state (i.e., whether enabled or disabled) of 454 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 455 * absolute PMC number and need not have been first allocated by the 456 * calling process. 457 */ 458 459struct pmc_op_pmcadmin { 460 int pm_cpu; /* CPU# */ 461 uint32_t pm_flags; /* flags */ 462 int pm_pmc; /* PMC# */ 463 enum pmc_state pm_state; /* desired state */ 464}; 465 466/* 467 * OP PMCATTACH / OP PMCDETACH 468 * 469 * Attach/detach a PMC and a process. 470 */ 471 472struct pmc_op_pmcattach { 473 pmc_id_t pm_pmc; /* PMC to attach to */ 474 pid_t pm_pid; /* target process */ 475}; 476 477/* 478 * OP PMCSETCOUNT 479 * 480 * Set the sampling rate (i.e., the reload count) for statistical counters. 481 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 482 */ 483 484struct pmc_op_pmcsetcount { 485 pmc_value_t pm_count; /* initial/sample count */ 486 pmc_id_t pm_pmcid; /* PMC id to set */ 487}; 488 489/* 490 * OP PMCRW 491 * 492 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 493 * to have been previously allocated using PMCALLOCATE. 494 */ 495 496struct pmc_op_pmcrw { 497 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 498 pmc_id_t pm_pmcid; /* pmc id */ 499 pmc_value_t pm_value; /* new&returned value */ 500}; 501 502/* 503 * OP GETPMCINFO 504 * 505 * retrieve PMC state for a named CPU. The caller is expected to 506 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 507 * values. 508 */ 509 510struct pmc_info { 511 char pm_name[PMC_NAME_MAX]; /* pmc name */ 512 enum pmc_class pm_class; /* enum pmc_class */ 513 int pm_enabled; /* whether enabled */ 514 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 515 pid_t pm_ownerpid; /* owner, or -1 */ 516 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 517 enum pmc_event pm_event; /* current event */ 518 uint32_t pm_flags; /* current flags */ 519 pmc_value_t pm_reloadcount; /* sampling counters only */ 520}; 521 522struct pmc_op_getpmcinfo { 523 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 524 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 525}; 526 527/* 528 * OP GETCPUINFO 529 * 530 * Retrieve system CPU information. 531 */ 532 533struct pmc_classinfo { 534 enum pmc_class pm_class; /* class id */ 535 uint32_t pm_caps; /* counter capabilities */ 536 uint32_t pm_width; /* width of the PMC */ 537 uint32_t pm_num; /* number of PMCs in class */ 538}; 539 540struct pmc_op_getcpuinfo { 541 enum pmc_cputype pm_cputype; /* what kind of CPU */ 542 uint32_t pm_ncpu; /* max CPU number */ 543 uint32_t pm_npmc; /* #PMCs per CPU */ 544 uint32_t pm_nclass; /* #classes of PMCs */ 545 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 546}; 547 548/* 549 * OP CONFIGURELOG 550 * 551 * Configure a log file for writing system-wide statistics to. 552 */ 553 554struct pmc_op_configurelog { 555 int pm_flags; 556 int pm_logfd; /* logfile fd (or -1) */ 557}; 558 559/* 560 * OP GETDRIVERSTATS 561 * 562 * Retrieve pmc(4) driver-wide statistics. 563 */ 564#ifdef _KERNEL 565struct pmc_driverstats { 566 counter_u64_t pm_intr_ignored; /* #interrupts ignored */ 567 counter_u64_t pm_intr_processed; /* #interrupts processed */ 568 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */ 569 counter_u64_t pm_syscalls; /* #syscalls */ 570 counter_u64_t pm_syscall_errors; /* #syscalls with errors */ 571 counter_u64_t pm_buffer_requests; /* #buffer requests */ 572 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */ 573 counter_u64_t pm_log_sweeps; /* #sample buffer processing 574 passes */ 575 counter_u64_t pm_merges; /* merged k+u */ 576 counter_u64_t pm_overwrites; /* UR overwrites */ 577}; 578#endif 579 580struct pmc_op_getdriverstats { 581 unsigned int pm_intr_ignored; /* #interrupts ignored */ 582 unsigned int pm_intr_processed; /* #interrupts processed */ 583 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 584 unsigned int pm_syscalls; /* #syscalls */ 585 unsigned int pm_syscall_errors; /* #syscalls with errors */ 586 unsigned int pm_buffer_requests; /* #buffer requests */ 587 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ 588 unsigned int pm_log_sweeps; /* #sample buffer processing 589 passes */ 590}; 591 592/* 593 * OP RELEASE / OP START / OP STOP 594 * 595 * Simple operations on a PMC id. 596 */ 597 598struct pmc_op_simple { 599 pmc_id_t pm_pmcid; 600}; 601 602/* 603 * OP WRITELOG 604 * 605 * Flush the current log buffer and write 4 bytes of user data to it. 606 */ 607 608struct pmc_op_writelog { 609 uint32_t pm_userdata; 610}; 611 612/* 613 * OP GETMSR 614 * 615 * Retrieve the machine specific address associated with the allocated 616 * PMC. This number can be used subsequently with a read-performance-counter 617 * instruction. 618 */ 619 620struct pmc_op_getmsr { 621 uint32_t pm_msr; /* machine specific address */ 622 pmc_id_t pm_pmcid; /* allocated pmc id */ 623}; 624 625/* 626 * OP GETDYNEVENTINFO 627 * 628 * Retrieve a PMC dynamic class events list. 629 */ 630 631struct pmc_dyn_event_descr { 632 char pm_ev_name[PMC_NAME_MAX]; 633 enum pmc_event pm_ev_code; 634}; 635 636struct pmc_op_getdyneventinfo { 637 enum pmc_class pm_class; 638 unsigned int pm_nevent; 639 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 640}; 641 642#ifdef _KERNEL 643 644#include <sys/malloc.h> 645#include <sys/sysctl.h> 646#include <sys/_cpuset.h> 647 648#include <machine/frame.h> 649 650#define PMC_HASH_SIZE 1024 651#define PMC_MTXPOOL_SIZE 2048 652#define PMC_LOG_BUFFER_SIZE 256 653#define PMC_NLOGBUFFERS_PCPU 32 654#define PMC_NSAMPLES 256 655#define PMC_CALLCHAIN_DEPTH 128 656#define PMC_THREADLIST_MAX 128 657 658#define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 659 660/* 661 * Locking keys 662 * 663 * (b) - pmc_bufferlist_mtx (spin lock) 664 * (k) - pmc_kthread_mtx (sleep lock) 665 * (o) - po->po_mtx (spin lock) 666 * (g) - global_epoch_preempt (epoch) 667 * (p) - pmc_sx (sx) 668 */ 669 670/* 671 * PMC commands 672 */ 673 674struct pmc_syscall_args { 675 register_t pmop_code; /* one of PMC_OP_* */ 676 void *pmop_data; /* syscall parameter */ 677}; 678 679/* 680 * Interface to processor specific s1tuff 681 */ 682 683/* 684 * struct pmc_descr 685 * 686 * Machine independent (i.e., the common parts) of a human readable 687 * PMC description. 688 */ 689 690struct pmc_descr { 691 char pd_name[PMC_NAME_MAX]; /* name */ 692 uint32_t pd_caps; /* capabilities */ 693 enum pmc_class pd_class; /* class of the PMC */ 694 uint32_t pd_width; /* width in bits */ 695}; 696 697/* 698 * struct pmc_target 699 * 700 * This structure records all the target processes associated with a 701 * PMC. 702 */ 703 704struct pmc_target { 705 LIST_ENTRY(pmc_target) pt_next; 706 struct pmc_process *pt_process; /* target descriptor */ 707}; 708 709/* 710 * struct pmc 711 * 712 * Describes each allocated PMC. 713 * 714 * Each PMC has precisely one owner, namely the process that allocated 715 * the PMC. 716 * 717 * A PMC may be attached to multiple target processes. The 718 * 'pm_targets' field links all the target processes being monitored 719 * by this PMC. 720 * 721 * The 'pm_savedvalue' field is protected by a mutex. 722 * 723 * On a multi-cpu machine, multiple target threads associated with a 724 * process-virtual PMC could be concurrently executing on different 725 * CPUs. The 'pm_runcount' field is atomically incremented every time 726 * the PMC gets scheduled on a CPU and atomically decremented when it 727 * get descheduled. Deletion of a PMC is only permitted when this 728 * field is '0'. 729 * 730 */ 731struct pmc_pcpu_state { 732 uint32_t pps_overflowcnt; /* count overflow interrupts */ 733 uint8_t pps_stalled; 734 uint8_t pps_cpustate; 735} __aligned(CACHE_LINE_SIZE); 736struct pmc { 737 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 738 LIST_ENTRY(pmc) pm_next; /* owner's list */ 739 740 /* 741 * System-wide PMCs are allocated on a CPU and are not moved 742 * around. For system-wide PMCs we record the CPU the PMC was 743 * allocated on in the 'CPU' field of the pmc ID. 744 * 745 * Virtual PMCs run on whichever CPU is currently executing 746 * their targets' threads. For these PMCs we need to save 747 * their current PMC counter values when they are taken off 748 * CPU. 749 */ 750 751 union { 752 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 753 } pm_gv; 754 755 /* 756 * For sampling mode PMCs, we keep track of the PMC's "reload 757 * count", which is the counter value to be loaded in when 758 * arming the PMC for the next counting session. For counting 759 * modes on PMCs that are read-only (e.g., the x86 TSC), we 760 * keep track of the initial value at the start of 761 * counting-mode operation. 762 */ 763 764 union { 765 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 766 pmc_value_t pm_initial; /* counting PMC modes */ 767 } pm_sc; 768 769 struct pmc_pcpu_state *pm_pcpu_state; 770 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ 771 uint32_t pm_caps; /* PMC capabilities */ 772 enum pmc_event pm_event; /* event being measured */ 773 uint32_t pm_flags; /* additional flags PMC_F_... */ 774 struct pmc_owner *pm_owner; /* owner thread state */ 775 counter_u64_t pm_runcount; /* #cpus currently on */ 776 enum pmc_state pm_state; /* current PMC state */ 777 778 /* 779 * The PMC ID field encodes the row-index for the PMC, its 780 * mode, class and the CPU# associated with the PMC. 781 */ 782 783 pmc_id_t pm_id; /* allocated PMC id */ 784 enum pmc_class pm_class; 785 786 /* md extensions */ 787 union pmc_md_pmc pm_md; 788}; 789 790/* 791 * Accessor macros for 'struct pmc' 792 */ 793 794#define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 795#define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 796#define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 797#define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 798 799/* 800 * struct pmc_threadpmcstate 801 * 802 * Record per-PMC, per-thread state. 803 */ 804struct pmc_threadpmcstate { 805 pmc_value_t pt_pmcval; /* per-thread reload count */ 806}; 807 808/* 809 * struct pmc_thread 810 * 811 * Record a 'target' thread being profiled. 812 */ 813struct pmc_thread { 814 LIST_ENTRY(pmc_thread) pt_next; /* linked list */ 815 struct thread *pt_td; /* target thread */ 816 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */ 817}; 818 819/* 820 * struct pmc_process 821 * 822 * Record a 'target' process being profiled. 823 * 824 * The target process being profiled could be different from the owner 825 * process which allocated the PMCs. Each target process descriptor 826 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 827 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 828 * array. The size of this structure is thus PMC architecture 829 * dependent. 830 * 831 */ 832 833struct pmc_targetstate { 834 struct pmc *pp_pmc; /* target PMC */ 835 pmc_value_t pp_pmcval; /* per-process value */ 836}; 837 838struct pmc_process { 839 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 840 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */ 841 struct mtx *pp_tdslock; /* lock on pp_tds thread list */ 842 int pp_refcnt; /* reference count */ 843 uint32_t pp_flags; /* flags PMC_PP_* */ 844 struct proc *pp_proc; /* target process */ 845 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 846}; 847 848#define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 849 850/* 851 * struct pmc_owner 852 * 853 * We associate a PMC with an 'owner' process. 854 * 855 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 856 * lifetime, where NCPUS is the numbers of CPUS in the system and 857 * NHWPMC is the number of hardware PMCs per CPU. These are 858 * maintained in the list headed by the 'po_pmcs' to save on space. 859 * 860 */ 861 862struct pmc_owner { 863 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 864 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* (g/p) list of SS PMC owners */ 865 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 866 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 867 struct mtx po_mtx; /* spin lock for (o) */ 868 struct proc *po_owner; /* owner proc */ 869 uint32_t po_flags; /* (k) flags PMC_PO_* */ 870 struct proc *po_kthread; /* (k) helper kthread */ 871 struct file *po_file; /* file reference */ 872 int po_error; /* recorded error */ 873 short po_sscount; /* # SS PMCs owned */ 874 short po_logprocmaps; /* global mappings done */ 875 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */ 876}; 877 878#define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 879#define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 880#define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 881 882/* 883 * struct pmc_hw -- describe the state of the PMC hardware 884 * 885 * When in use, a HW PMC is associated with one allocated 'struct pmc' 886 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 887 * 888 * On an SMP box, one or more HW PMC's in process virtual mode with 889 * the same 'phw_pmc' could be executing on different CPUs. In order 890 * to handle this case correctly, we need to ensure that only 891 * incremental counts get added to the saved value in the associated 892 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 893 * value at the time the hardware is started during this context 894 * switch (i.e., the difference between the new (hardware) count and 895 * the saved count is atomically added to the count field in 'struct 896 * pmc' at context switch time). 897 * 898 */ 899 900struct pmc_hw { 901 uint32_t phw_state; /* see PHW_* macros below */ 902 struct pmc *phw_pmc; /* current thread PMC */ 903}; 904 905#define PMC_PHW_RI_MASK 0x000000FF 906#define PMC_PHW_CPU_SHIFT 8 907#define PMC_PHW_CPU_MASK 0x0000FF00 908#define PMC_PHW_FLAGS_SHIFT 16 909#define PMC_PHW_FLAGS_MASK 0xFFFF0000 910 911#define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 912#define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 913#define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 914 PMC_PHW_CPU_MASK) 915#define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 916 PMC_PHW_CPU_SHIFT) 917#define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 918 PMC_PHW_FLAGS_MASK) 919#define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 920 PMC_PHW_FLAGS_SHIFT) 921#define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 922#define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 923 924/* 925 * struct pmc_sample 926 * 927 * Space for N (tunable) PC samples and associated control data. 928 */ 929 930struct pmc_sample { 931 uint16_t ps_nsamples; /* callchain depth */ 932 uint16_t ps_nsamples_actual; 933 uint16_t ps_cpu; /* cpu number */ 934 uint16_t ps_flags; /* other flags */ 935 lwpid_t ps_tid; /* thread id */ 936 pid_t ps_pid; /* process PID or -1 */ 937 int ps_ticks; /* ticks at sample time */ 938 /* pad */ 939 struct thread *ps_td; /* which thread */ 940 struct pmc *ps_pmc; /* interrupting PMC */ 941 uintptr_t *ps_pc; /* (const) callchain start */ 942 uint64_t ps_tsc; /* tsc value */ 943}; 944 945#define PMC_SAMPLE_FREE ((uint16_t) 0) 946#define PMC_USER_CALLCHAIN_PENDING ((uint16_t) 0xFFFF) 947 948struct pmc_samplebuffer { 949 volatile uint64_t ps_prodidx; /* producer index */ 950 volatile uint64_t ps_considx; /* consumer index */ 951 uintptr_t *ps_callchains; /* all saved call chains */ 952 struct pmc_sample ps_samples[]; /* array of sample entries */ 953}; 954 955#define PMC_CONS_SAMPLE(psb) \ 956 (&(psb)->ps_samples[(psb)->ps_considx & pmc_sample_mask]) 957 958#define PMC_CONS_SAMPLE_OFF(psb, off) \ 959 (&(psb)->ps_samples[(off) & pmc_sample_mask]) 960 961#define PMC_PROD_SAMPLE(psb) \ 962 (&(psb)->ps_samples[(psb)->ps_prodidx & pmc_sample_mask]) 963 964/* 965 * struct pmc_cpustate 966 * 967 * A CPU is modelled as a collection of HW PMCs with space for additional 968 * flags. 969 */ 970 971struct pmc_cpu { 972 uint32_t pc_state; /* physical cpu number + flags */ 973 struct pmc_samplebuffer *pc_sb[3]; /* space for samples */ 974 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 975}; 976 977#define PMC_PCPU_CPU_MASK 0x000000FF 978#define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 979#define PMC_PCPU_FLAGS_SHIFT 8 980#define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 981#define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 982#define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 983#define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 984#define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 985 986/* 987 * struct pmc_binding 988 * 989 * CPU binding information. 990 */ 991 992struct pmc_binding { 993 int pb_bound; /* is bound? */ 994 int pb_cpu; /* if so, to which CPU */ 995}; 996 997struct pmc_mdep; 998 999/* 1000 * struct pmc_classdep 1001 * 1002 * PMC class-dependent operations. 1003 */ 1004struct pmc_classdep { 1005 uint32_t pcd_caps; /* class capabilities */ 1006 enum pmc_class pcd_class; /* class id */ 1007 int pcd_num; /* number of PMCs */ 1008 int pcd_ri; /* row index of the first PMC in class */ 1009 int pcd_width; /* width of the PMC */ 1010 1011 /* configuring/reading/writing the hardware PMCs */ 1012 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 1013 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 1014 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value); 1015 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value); 1016 1017 /* pmc allocation/release */ 1018 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 1019 const struct pmc_op_pmcallocate *_a); 1020 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 1021 1022 /* starting and stopping PMCs */ 1023 int (*pcd_start_pmc)(int _cpu, int _ri); 1024 int (*pcd_stop_pmc)(int _cpu, int _ri); 1025 1026 /* description */ 1027 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 1028 struct pmc **_ppmc); 1029 1030 /* class-dependent initialization & finalization */ 1031 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1032 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1033 1034 /* machine-specific interface */ 1035 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 1036}; 1037 1038/* 1039 * struct pmc_mdep 1040 * 1041 * Machine dependent bits needed per CPU type. 1042 */ 1043 1044struct pmc_mdep { 1045 uint32_t pmd_cputype; /* from enum pmc_cputype */ 1046 uint32_t pmd_npmc; /* number of PMCs per CPU */ 1047 uint32_t pmd_nclass; /* number of PMC classes present */ 1048 1049 /* 1050 * Machine dependent methods. 1051 */ 1052 1053 /* per-cpu initialization and finalization */ 1054 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1055 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1056 1057 /* thread context switch in/out */ 1058 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 1059 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 1060 1061 /* handle a PMC interrupt */ 1062 int (*pmd_intr)(struct trapframe *_tf); 1063 1064 /* 1065 * PMC class dependent information. 1066 */ 1067 struct pmc_classdep pmd_classdep[]; 1068}; 1069 1070/* 1071 * Per-CPU state. This is an array of 'mp_ncpu' pointers 1072 * to struct pmc_cpu descriptors. 1073 */ 1074 1075extern struct pmc_cpu **pmc_pcpu; 1076 1077/* driver statistics */ 1078extern struct pmc_driverstats pmc_stats; 1079 1080#if defined(HWPMC_DEBUG) 1081#include <sys/ktr.h> 1082 1083/* debug flags, major flag groups */ 1084struct pmc_debugflags { 1085 int pdb_CPU; 1086 int pdb_CSW; 1087 int pdb_LOG; 1088 int pdb_MDP; 1089 int pdb_MOD; 1090 int pdb_OWN; 1091 int pdb_PMC; 1092 int pdb_PRC; 1093 int pdb_SAM; 1094}; 1095 1096extern struct pmc_debugflags pmc_debugflags; 1097 1098#define KTR_PMC KTR_SUBSYS 1099 1100#define PMC_DEBUG_STRSIZE 128 1101#define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1102 1103#define PMCDBG0(M, N, L, F) do { \ 1104 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1105 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \ 1106} while (0) 1107#define PMCDBG1(M, N, L, F, p1) do { \ 1108 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1109 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \ 1110} while (0) 1111#define PMCDBG2(M, N, L, F, p1, p2) do { \ 1112 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1113 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \ 1114} while (0) 1115#define PMCDBG3(M, N, L, F, p1, p2, p3) do { \ 1116 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1117 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \ 1118} while (0) 1119#define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \ 1120 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1121 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\ 1122} while (0) 1123#define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \ 1124 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1125 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1126 p5); \ 1127} while (0) 1128#define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \ 1129 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1130 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1131 p5, p6); \ 1132} while (0) 1133 1134/* Major numbers */ 1135#define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1136#define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1137#define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1138#define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1139#define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1140#define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1141#define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1142#define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1143#define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1144 1145/* Minor numbers */ 1146 1147/* Common (8 bits) */ 1148#define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1149#define PMC_DEBUG_MIN_REL 1 /* release */ 1150#define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1151#define PMC_DEBUG_MIN_INI 3 /* init */ 1152#define PMC_DEBUG_MIN_FND 4 /* find */ 1153 1154/* MODULE */ 1155#define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1156#define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1157 1158/* OWN */ 1159#define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1160#define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1161 1162/* PROCESSES */ 1163#define PMC_DEBUG_MIN_TLK 8 /* link target */ 1164#define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1165#define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1166#define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1167#define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1168#define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1169#define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1170 1171/* CONTEXT SWITCHES */ 1172#define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1173#define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1174 1175/* PMC */ 1176#define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1177#define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1178 1179/* MACHINE DEPENDENT LAYER */ 1180#define PMC_DEBUG_MIN_REA 8 /* read */ 1181#define PMC_DEBUG_MIN_WRI 9 /* write */ 1182#define PMC_DEBUG_MIN_CFG 10 /* config */ 1183#define PMC_DEBUG_MIN_STA 11 /* start */ 1184#define PMC_DEBUG_MIN_STO 12 /* stop */ 1185#define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1186 1187/* CPU */ 1188#define PMC_DEBUG_MIN_BND 8 /* bind */ 1189#define PMC_DEBUG_MIN_SEL 9 /* select */ 1190 1191/* LOG */ 1192#define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1193#define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1194#define PMC_DEBUG_MIN_FLS 10 /* flush */ 1195#define PMC_DEBUG_MIN_SAM 11 /* sample */ 1196#define PMC_DEBUG_MIN_CLO 12 /* close */ 1197 1198#else 1199#define PMCDBG0(M, N, L, F) /* nothing */ 1200#define PMCDBG1(M, N, L, F, p1) 1201#define PMCDBG2(M, N, L, F, p1, p2) 1202#define PMCDBG3(M, N, L, F, p1, p2, p3) 1203#define PMCDBG4(M, N, L, F, p1, p2, p3, p4) 1204#define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) 1205#define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) 1206#endif 1207 1208/* declare a dedicated memory pool */ 1209MALLOC_DECLARE(M_PMC); 1210 1211/* 1212 * Functions 1213 */ 1214 1215struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1216void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1217int pmc_getrowdisp(int _ri); 1218int pmc_process_interrupt(int _ring, struct pmc *_pm, struct trapframe *_tf); 1219int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1220 struct trapframe *_tf); 1221int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1222 struct trapframe *_tf); 1223struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1224void pmc_mdep_free(struct pmc_mdep *md); 1225uint64_t pmc_rdtsc(void); 1226#endif /* _KERNEL */ 1227#endif /* _SYS_PMC_H_ */ 1228