1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1996, Sujal M. Patel 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Sujal M. Patel 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 * from: pnp.h,v 1.7 1998/09/13 22:15:44 eivind Exp 36 */ 37 38#ifndef _ISA_PNPREG_H_ 39#define _ISA_PNPREG_H_ 40 41/* Maximum Number of PnP Devices. 8 should be plenty */ 42#define PNP_MAX_CARDS 8 43 44/* Static ports to access PnP state machine */ 45#define _PNP_ADDRESS 0x279 46#define _PNP_WRITE_DATA 0xa79 47 48/* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */ 49#define PNP_SET_RD_DATA 0x00 50 /*** 51 Writing to this location modifies the address of the port used for 52 reading from the Plug and Play ISA cards. Bits[7:0] become I/O 53 read port address bits[9:2]. Reads from this register are ignored. 54 ***/ 55 56#define PNP_SERIAL_ISOLATION 0x01 57 /*** 58 A read to this register causes a Plug and Play cards in the Isolation 59 state to compare one bit of the boards ID. 60 This register is read only. 61 ***/ 62 63#define PNP_CONFIG_CONTROL 0x02 64#define PNP_CONFIG_CONTROL_RESET_CSN 0x04 65#define PNP_CONFIG_CONTROL_WAIT_FOR_KEY 0x02 66#define PNP_CONFIG_CONTROL_RESET 0x01 67 /*** 68 Bit[2] Reset CSN to 0 69 Bit[1] Return to the Wait for Key state 70 Bit[0] Reset all logical devices and restore configuration 71 registers to their power-up values. 72 73 A write to bit[0] of this register performs a reset function on 74 all logical devices. This resets the contents of configuration 75 registers to their default state. All card's logical devices 76 enter their default state and the CSN is preserved. 77 78 A write to bit[1] of this register causes all cards to enter the 79 Wait for Key state but all CSNs are preserved and logical devices 80 are not affected. 81 82 A write to bit[2] of this register causes all cards to reset their 83 CSN to zero . 84 85 This register is write-only. The values are not sticky, that is, 86 hardware will automatically clear them and there is no need for 87 software to clear the bits. 88 ***/ 89 90#define PNP_WAKE 0x03 91 /*** 92 A write to this port will cause all cards that have a CSN that 93 matches the write data[7:0] to go from the Sleep state to the either 94 the Isolation state if the write data for this command is zero or 95 the Config state if the write data is not zero. Additionally, the 96 pointer to the byte-serial device is reset. This register is 97 writeonly. 98 ***/ 99 100#define PNP_RESOURCE_DATA 0x04 101 /*** 102 A read from this address reads the next byte of resource information. 103 The Status register must be polled until bit[0] is set before this 104 register may be read. This register is read only. 105 ***/ 106 107#define PNP_STATUS 0x05 108 /*** 109 Bit[0] when set indicates it is okay to read the next data byte 110 from the Resource Data register. This register is readonly. 111 ***/ 112 113#define PNP_SET_CSN 0x06 114 /*** 115 A write to this port sets a card's CSN. The CSN is a value uniquely 116 assigned to each ISA card after the serial identification process 117 so that each card may be individually selected during a Wake[CSN] 118 command. This register is read/write. 119 ***/ 120 121#define PNP_SET_LDN 0x07 122 /*** 123 Selects the current logical device. All reads and writes of memory, 124 I/O, interrupt and DMA configuration information access the registers 125 of the logical device written here. In addition, the I/O Range 126 Check and Activate commands operate only on the selected logical 127 device. This register is read/write. If a card has only 1 logical 128 device, this location should be a read-only value of 0x00. 129 ***/ 130 131/*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/ 132/*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/ 133 134#define PNP_ACTIVATE 0x30 135 /*** 136 For each logical device there is one activate register that controls 137 whether or not the logical device is active on the ISA bus. Bit[0], 138 if set, activates the logical device. Bits[7:1] are reserved and 139 must return 0 on reads. This is a read/write register. Before a 140 logical device is activated, I/O range check must be disabled. 141 ***/ 142 143#define PNP_IO_RANGE_CHECK 0x31 144#define PNP_IO_RANGE_CHECK_ENABLE 0x02 145#define PNP_IO_RANGE_CHECK_READ_AS_55 0x01 146 /*** 147 This register is used to perform a conflict check on the I/O port 148 range programmed for use by a logical device. 149 150 Bit[7:2] Reserved and must return 0 on reads 151 Bit[1] Enable I/O Range check, if set then I/O Range Check 152 is enabled. I/O range check is only valid when the logical 153 device is inactive. 154 155 Bit[0], if set, forces the logical device to respond to I/O reads 156 of the logical device's assigned I/O range with a 0x55 when I/O 157 range check is in operation. If clear, the logical device drives 158 0xAA. This register is read/write. 159 ***/ 160 161/*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/ 162/*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/ 163 164#define PNP_MEM_BASE_HIGH(i) (0x40 + 8*(i)) 165#define PNP_MEM_BASE_LOW(i) (0x41 + 8*(i)) 166#define PNP_MEM_CONTROL(i) (0x42 * 8*(i)) 167#define PNP_MEM_CONTROL_16BIT 0x2 168#define PNP_MEM_CONTROL_LIMIT 0x1 169#define PNP_MEM_RANGE_HIGH(i) (0x43 + 8*(i)) 170#define PNP_MEM_RANGE_LOW(i) (0x44 + 8*(i)) 171 /*** 172 Four memory resource registers per range, four ranges. 173 Fill with 0 if no ranges are enabled. 174 175 Offset 0: RW Memory base address bits[23:16] 176 Offset 1: RW Memory base address bits[15:8] 177 Offset 2: Memory control 178 Bit[1] specifies 8/16-bit control. This bit is set to indicate 179 16-bit memory, and cleared to indicate 8-bit memory. 180 Bit[0], if cleared, indicates the next field can be used as a range 181 length for decode (implies range length and base alignment of memory 182 descriptor are equal). 183 Bit[0], if set, indicates the next field is the upper limit for 184 the address. - - Bit[0] is read-only. 185 Offset 3: RW upper limit or range len, bits[23:16] 186 Offset 4: RW upper limit or range len, bits[15:8] 187 Offset 5-Offset 7: filler, unused. 188 ***/ 189 190#define PNP_IO_BASE_HIGH(i) (0x60 + 2*(i)) 191#define PNP_IO_BASE_LOW(i) (0x61 + 2*(i)) 192 /*** 193 Eight ranges, two bytes per range. 194 Offset 0: I/O port base address bits[15:8] 195 Offset 1: I/O port base address bits[7:0] 196 ***/ 197 198#define PNP_IRQ_LEVEL(i) (0x70 + 2*(i)) 199#define PNP_IRQ_TYPE(i) (0x71 + 2*(i)) 200 /*** 201 Two entries, two bytes per entry. 202 Offset 0: RW interrupt level (1..15, 0=unused). 203 Offset 1: Bit[1]: level(1:hi, 0:low), 204 Bit[0]: type (1:level, 0:edge) 205 byte 1 can be readonly if 1 type of int is used. 206 ***/ 207 208#define PNP_DMA_CHANNEL(i) (0x74 + 1*(i)) 209 /*** 210 Two entries, one byte per entry. Bits[2:0] select 211 which DMA channel is in use for DMA 0. Zero selects DMA channel 212 0, seven selects DMA channel 7. DMA channel 4, the cascade channel 213 is used to indicate no DMA channel is active. 214 ***/ 215 216/*** 32-bit memory accesses are at 0x76 ***/ 217 218/* Macros to parse Resource IDs */ 219#define PNP_RES_TYPE(a) (a >> 7) 220#define PNP_SRES_NUM(a) (a >> 3) 221#define PNP_SRES_LEN(a) (a & 0x07) 222#define PNP_LRES_NUM(a) (a & 0x7f) 223 224/* Small Resource Item names */ 225#define PNP_TAG_VERSION 0x1 226#define PNP_TAG_LOGICAL_DEVICE 0x2 227#define PNP_TAG_COMPAT_DEVICE 0x3 228#define PNP_TAG_IRQ_FORMAT 0x4 229#define PNP_TAG_DMA_FORMAT 0x5 230#define PNP_TAG_START_DEPENDANT 0x6 231#define PNP_TAG_END_DEPENDANT 0x7 232#define PNP_TAG_IO_RANGE 0x8 233#define PNP_TAG_IO_FIXED 0x9 234#define PNP_TAG_RESERVED 0xa-0xd 235#define PNP_TAG_VENDOR 0xe 236#define PNP_TAG_END 0xf 237 238/* Large Resource Item names */ 239#define PNP_TAG_MEMORY_RANGE 0x1 240#define PNP_TAG_ID_ANSI 0x2 241#define PNP_TAG_ID_UNICODE 0x3 242#define PNP_TAG_LARGE_VENDOR 0x4 243#define PNP_TAG_MEMORY32_RANGE 0x5 244#define PNP_TAG_MEMORY32_FIXED 0x6 245#define PNP_TAG_LARGE_RESERVED 0x7-0x7f 246 247#endif /* !_ISA_PNPREG_H_ */ 248