1/* 2 * Copyright (c) 1996, Sujal M. Patel 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Sujal M. Patel 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35#ifndef _I386_ISA_PNP_H_ 36#define _I386_ISA_PNP_H_ 37 38/* Maximum Number of PnP Devices. 8 should be plenty */ 39#define MAX_PNP_CARDS 8 40/* 41 * the following is the maximum number of PnP Logical devices that 42 * userconfig can handle. 43 */ 44#define MAX_PNP_LDN 20 45 46/* Static ports to access PnP state machine */ 47#ifndef _KERNEL 48#define _PNP_ADDRESS 0x279 49#define _PNP_WRITE_DATA 0xa79 50#endif 51 52/* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */ 53#define SET_RD_DATA 0x00 54 /*** 55 Writing to this location modifies the address of the port used for 56 reading from the Plug and Play ISA cards. Bits[7:0] become I/O 57 read port address bits[9:2]. Reads from this register are ignored. 58 ***/ 59 60#define SERIAL_ISOLATION 0x01 61 /*** 62 A read to this register causes a Plug and Play cards in the Isolation 63 state to compare one bit of the boards ID. 64 This register is read only. 65 ***/ 66 67#define CONFIG_CONTROL 0x02 68 /*** 69 Bit[2] Reset CSN to 0 70 Bit[1] Return to the Wait for Key state 71 Bit[0] Reset all logical devices and restore configuration 72 registers to their power-up values. 73 74 A write to bit[0] of this register performs a reset function on 75 all logical devices. This resets the contents of configuration 76 registers to their default state. All card's logical devices 77 enter their default state and the CSN is preserved. 78 79 A write to bit[1] of this register causes all cards to enter the 80 Wait for Key state but all CSNs are preserved and logical devices 81 are not affected. 82 83 A write to bit[2] of this register causes all cards to reset their 84 CSN to zero . 85 86 This register is write-only. The values are not sticky, that is, 87 hardware will automatically clear them and there is no need for 88 software to clear the bits. 89 ***/ 90 91#define WAKE 0x03 92 /*** 93 A write to this port will cause all cards that have a CSN that 94 matches the write data[7:0] to go from the Sleep state to the either 95 the Isolation state if the write data for this command is zero or 96 the Config state if the write data is not zero. Additionally, the 97 pointer to the byte-serial device is reset. This register is 98 writeonly. 99 ***/ 100 101#define RESOURCE_DATA 0x04 102 /*** 103 A read from this address reads the next byte of resource information. 104 The Status register must be polled until bit[0] is set before this 105 register may be read. This register is read only. 106 ***/ 107 108#define STATUS 0x05 109 /*** 110 Bit[0] when set indicates it is okay to read the next data byte 111 from the Resource Data register. This register is readonly. 112 ***/ 113 114#define SET_CSN 0x06 115 /*** 116 A write to this port sets a card's CSN. The CSN is a value uniquely 117 assigned to each ISA card after the serial identification process 118 so that each card may be individually selected during a Wake[CSN] 119 command. This register is read/write. 120 ***/ 121 122#define SET_LDN 0x07 123 /*** 124 Selects the current logical device. All reads and writes of memory, 125 I/O, interrupt and DMA configuration information access the registers 126 of the logical device written here. In addition, the I/O Range 127 Check and Activate commands operate only on the selected logical 128 device. This register is read/write. If a card has only 1 logical 129 device, this location should be a read-only value of 0x00. 130 ***/ 131 132/*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/ 133/*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/ 134 135#define ACTIVATE 0x30 136 /*** 137 For each logical device there is one activate register that controls 138 whether or not the logical device is active on the ISA bus. Bit[0], 139 if set, activates the logical device. Bits[7:1] are reserved and 140 must return 0 on reads. This is a read/write register. Before a 141 logical device is activated, I/O range check must be disabled. 142 ***/ 143 144#define IO_RANGE_CHECK 0x31 145 /*** 146 This register is used to perform a conflict check on the I/O port 147 range programmed for use by a logical device. 148 149 Bit[7:2] Reserved and must return 0 on reads 150 Bit[1] Enable I/O Range check, if set then I/O Range Check 151 is enabled. I/O range check is only valid when the logical 152 device is inactive. 153 154 Bit[0], if set, forces the logical device to respond to I/O reads 155 of the logical device's assigned I/O range with a 0x55 when I/O 156 range check is in operation. If clear, the logical device drives 157 0xAA. This register is read/write. 158 ***/ 159 160/*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/ 161/*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/ 162 163#define MEM_CONFIG 0x40 164 /*** 165 Four memory resource registers per range, four ranges. 166 Fill with 0 if no ranges are enabled. 167 168 Offset 0: RW Memory base address bits[23:16] 169 Offset 1: RW Memory base address bits[15:8] 170 Offset 2: Memory control 171 Bit[1] specifies 8/16-bit control. This bit is set to indicate 172 16-bit memory, and cleared to indicate 8-bit memory. 173 Bit[0], if cleared, indicates the next field can be used as a range 174 length for decode (implies range length and base alignment of memory 175 descriptor are equal). 176 Bit[0], if set, indicates the next field is the upper limit for 177 the address. - - Bit[0] is read-only. 178 Offset 3: RW upper limit or range len, bits[23:16] 179 Offset 4: RW upper limit or range len, bits[15:8] 180 Offset 5-Offset 7: filler, unused. 181 ***/ 182 183#define IO_CONFIG_BASE 0x60 184 /*** 185 Eight ranges, two bytes per range. 186 Offset 0: I/O port base address bits[15:8] 187 Offset 1: I/O port base address bits[7:0] 188 ***/ 189 190#define IRQ_CONFIG 0x70 191 /*** 192 Two entries, two bytes per entry. 193 Offset 0: RW interrupt level (1..15, 0=unused). 194 Offset 1: Bit[1]: level(1:hi, 0:low), 195 Bit[0]: type (1:level, 0:edge) 196 byte 1 can be readonly if 1 type of int is used. 197 ***/ 198 199#define DRQ_CONFIG 0x74 200 /*** 201 Two entries, one byte per entry. Bits[2:0] select 202 which DMA channel is in use for DMA 0. Zero selects DMA channel 203 0, seven selects DMA channel 7. DMA channel 4, the cascade channel 204 is used to indicate no DMA channel is active. 205 ***/ 206 207/*** 32-bit memory accesses are at 0x76 ***/ 208 209/* Macros to parse Resource IDs */ 210#define PNP_RES_TYPE(a) (a >> 7) 211#define PNP_SRES_NUM(a) (a >> 3) 212#define PNP_SRES_LEN(a) (a & 0x07) 213#define PNP_LRES_NUM(a) (a & 0x7f) 214 215/* Small Resource Item names */ 216#define PNP_VERSION 0x1 217#define LOG_DEVICE_ID 0x2 218#define COMP_DEVICE_ID 0x3 219#define IRQ_FORMAT 0x4 220#define DMA_FORMAT 0x5 221#define START_DEPEND_FUNC 0x6 222#define END_DEPEND_FUNC 0x7 223#define IO_PORT_DESC 0x8 224#define FIXED_IO_PORT_DESC 0x9 225#define SM_RES_RESERVED 0xa-0xd 226#define SM_VENDOR_DEFINED 0xe 227#define END_TAG 0xf 228 229/* Large Resource Item names */ 230#define MEMORY_RANGE_DESC 0x1 231#define ID_STRING_ANSI 0x2 232#define ID_STRING_UNICODE 0x3 233#define LG_VENDOR_DEFINED 0x4 234#define _32BIT_MEM_RANGE_DESC 0x5 235#define _32BIT_FIXED_LOC_DESC 0x6 236#define LG_RES_RESERVED 0x7-0x7f 237 238/* 239 * pnp_cinfo contains Configuration Information. They are used 240 * to communicate to the device driver the actual configuration 241 * of the device, and also by the userconfig menu to let the 242 * operating system override any configuration set by the bios. 243 * 244 */ 245struct pnp_cinfo { 246 u_int vendor_id; /* board id */ 247 u_int serial; /* Board's Serial Number */ 248 u_long flags; /* OS-reserved flags */ 249 u_char csn; /* assigned Card Select Number */ 250 u_char ldn; /* Logical Device Number */ 251 u_char enable; /* pnp enable */ 252 u_char override; /* override bios parms (in userconfig) */ 253 u_char irq[2]; /* IRQ Number */ 254 u_char irq_type[2]; /* IRQ Type */ 255 u_char drq[2]; 256 u_short port[8]; /* The Base Address of the Port */ 257 struct { 258 u_long base; /* Memory Base Address */ 259 int control; /* Memory Control Register */ 260 u_long range; /* Memory Range *OR* Upper Limit */ 261 } mem[4]; 262}; 263 264#ifdef _KERNEL 265 266struct pnp_device { 267 char *pd_name; 268 char * (*pd_probe ) (u_long csn, u_long vendor_id); 269 void (*pd_attach ) (u_long csn, u_long vend_id, char * name, 270 struct isa_device *dev); 271 u_long *pd_count; 272 u_int *imask ; 273}; 274 275struct _pnp_id { 276 u_long vendor_id; 277 u_long serial; 278 u_char checksum; 279} ; 280 281struct pnp_dlist_node { 282 struct pnp_device *pnp; 283 struct isa_device dev; 284 struct pnp_dlist_node *next; 285}; 286 287typedef struct _pnp_id pnp_id; 288extern struct pnp_dlist_node *pnp_device_list; 289extern pnp_id pnp_devices[MAX_PNP_CARDS]; 290extern struct pnp_cinfo pnp_ldn_overrides[MAX_PNP_LDN]; 291extern int pnp_overrides_valid; 292 293/* 294 * these two functions are for use in drivers 295 */ 296int read_pnp_parms(struct pnp_cinfo *d, int ldn); 297int write_pnp_parms(struct pnp_cinfo *d, int ldn); 298int enable_pnp_card(void); 299 300/* 301 * used by autoconfigure to actually probe and attach drivers 302 */ 303void pnp_configure(void); 304 305#endif /* _KERNEL */ 306 307#endif /* !_I386_ISA_PNP_H_ */ 308