cap.c revision 331722
1/*- 2 * Copyright (c) 2007 Yahoo!, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#ifndef lint 32static const char rcsid[] = 33 "$FreeBSD: stable/11/usr.sbin/pciconf/cap.c 331722 2018-03-29 02:50:57Z eadler $"; 34#endif /* not lint */ 35 36#include <sys/types.h> 37 38#include <err.h> 39#include <stdio.h> 40#include <strings.h> 41#include <sys/agpio.h> 42#include <sys/pciio.h> 43 44#include <dev/agp/agpreg.h> 45#include <dev/pci/pcireg.h> 46 47#include "pciconf.h" 48 49static void list_ecaps(int fd, struct pci_conf *p); 50 51static void 52cap_power(int fd, struct pci_conf *p, uint8_t ptr) 53{ 54 uint16_t cap, status; 55 56 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 57 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 58 printf("powerspec %d supports D0%s%s D3 current D%d", 59 cap & PCIM_PCAP_SPEC, 60 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 61 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 62 status & PCIM_PSTAT_DMASK); 63} 64 65static void 66cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 67{ 68 uint32_t status, command; 69 70 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 71 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 72 printf("AGP "); 73 if (AGP_MODE_GET_MODE_3(status)) { 74 printf("v3 "); 75 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 76 printf("8x "); 77 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 78 printf("4x "); 79 } else { 80 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 81 printf("4x "); 82 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 83 printf("2x "); 84 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 85 printf("1x "); 86 } 87 if (AGP_MODE_GET_SBA(status)) 88 printf("SBA "); 89 if (AGP_MODE_GET_AGP(command)) { 90 printf("enabled at "); 91 if (AGP_MODE_GET_MODE_3(command)) { 92 printf("v3 "); 93 switch (AGP_MODE_GET_RATE(command)) { 94 case AGP_MODE_V3_RATE_8x: 95 printf("8x "); 96 break; 97 case AGP_MODE_V3_RATE_4x: 98 printf("4x "); 99 break; 100 } 101 } else 102 switch (AGP_MODE_GET_RATE(command)) { 103 case AGP_MODE_V2_RATE_4x: 104 printf("4x "); 105 break; 106 case AGP_MODE_V2_RATE_2x: 107 printf("2x "); 108 break; 109 case AGP_MODE_V2_RATE_1x: 110 printf("1x "); 111 break; 112 } 113 if (AGP_MODE_GET_SBA(command)) 114 printf("SBA "); 115 } else 116 printf("disabled"); 117} 118 119static void 120cap_vpd(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 121{ 122 123 printf("VPD"); 124} 125 126static void 127cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 128{ 129 uint16_t ctrl; 130 int msgnum; 131 132 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 133 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 134 printf("MSI supports %d message%s%s%s ", msgnum, 135 (msgnum == 1) ? "" : "s", 136 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 137 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 138 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 139 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 140 printf("enabled with %d message%s", msgnum, 141 (msgnum == 1) ? "" : "s"); 142 } 143} 144 145static void 146cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 147{ 148 uint32_t status; 149 int comma, max_splits, max_burst_read; 150 151 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 152 printf("PCI-X "); 153 if (status & PCIXM_STATUS_64BIT) 154 printf("64-bit "); 155 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 156 printf("bridge "); 157 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 158 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 159 printf("supports"); 160 comma = 0; 161 if (status & PCIXM_STATUS_133CAP) { 162 printf(" 133MHz"); 163 comma = 1; 164 } 165 if (status & PCIXM_STATUS_266CAP) { 166 printf("%s 266MHz", comma ? "," : ""); 167 comma = 1; 168 } 169 if (status & PCIXM_STATUS_533CAP) { 170 printf("%s 533MHz", comma ? "," : ""); 171 comma = 1; 172 } 173 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 174 return; 175 max_burst_read = 0; 176 switch (status & PCIXM_STATUS_MAX_READ) { 177 case PCIXM_STATUS_MAX_READ_512: 178 max_burst_read = 512; 179 break; 180 case PCIXM_STATUS_MAX_READ_1024: 181 max_burst_read = 1024; 182 break; 183 case PCIXM_STATUS_MAX_READ_2048: 184 max_burst_read = 2048; 185 break; 186 case PCIXM_STATUS_MAX_READ_4096: 187 max_burst_read = 4096; 188 break; 189 } 190 max_splits = 0; 191 switch (status & PCIXM_STATUS_MAX_SPLITS) { 192 case PCIXM_STATUS_MAX_SPLITS_1: 193 max_splits = 1; 194 break; 195 case PCIXM_STATUS_MAX_SPLITS_2: 196 max_splits = 2; 197 break; 198 case PCIXM_STATUS_MAX_SPLITS_3: 199 max_splits = 3; 200 break; 201 case PCIXM_STATUS_MAX_SPLITS_4: 202 max_splits = 4; 203 break; 204 case PCIXM_STATUS_MAX_SPLITS_8: 205 max_splits = 8; 206 break; 207 case PCIXM_STATUS_MAX_SPLITS_12: 208 max_splits = 12; 209 break; 210 case PCIXM_STATUS_MAX_SPLITS_16: 211 max_splits = 16; 212 break; 213 case PCIXM_STATUS_MAX_SPLITS_32: 214 max_splits = 32; 215 break; 216 } 217 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 218 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 219} 220 221static void 222cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 223{ 224 uint32_t reg; 225 uint16_t command; 226 227 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 228 printf("HT "); 229 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 230 printf("slave"); 231 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 232 printf("host"); 233 else 234 switch (command & PCIM_HTCMD_CAP_MASK) { 235 case PCIM_HTCAP_SWITCH: 236 printf("switch"); 237 break; 238 case PCIM_HTCAP_INTERRUPT: 239 printf("interrupt"); 240 break; 241 case PCIM_HTCAP_REVISION_ID: 242 printf("revision ID"); 243 break; 244 case PCIM_HTCAP_UNITID_CLUMPING: 245 printf("unit ID clumping"); 246 break; 247 case PCIM_HTCAP_EXT_CONFIG_SPACE: 248 printf("extended config space"); 249 break; 250 case PCIM_HTCAP_ADDRESS_MAPPING: 251 printf("address mapping"); 252 break; 253 case PCIM_HTCAP_MSI_MAPPING: 254 printf("MSI %saddress window %s at 0x", 255 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 256 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 257 "disabled"); 258 if (command & PCIM_HTCMD_MSI_FIXED) 259 printf("fee00000"); 260 else { 261 reg = read_config(fd, &p->pc_sel, 262 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 263 if (reg != 0) 264 printf("%08x", reg); 265 reg = read_config(fd, &p->pc_sel, 266 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 267 printf("%08x", reg); 268 } 269 break; 270 case PCIM_HTCAP_DIRECT_ROUTE: 271 printf("direct route"); 272 break; 273 case PCIM_HTCAP_VCSET: 274 printf("VC set"); 275 break; 276 case PCIM_HTCAP_RETRY_MODE: 277 printf("retry mode"); 278 break; 279 case PCIM_HTCAP_X86_ENCODING: 280 printf("X86 encoding"); 281 break; 282 case PCIM_HTCAP_GEN3: 283 printf("Gen3"); 284 break; 285 case PCIM_HTCAP_FLE: 286 printf("function-level extension"); 287 break; 288 case PCIM_HTCAP_PM: 289 printf("power management"); 290 break; 291 case PCIM_HTCAP_HIGH_NODE_COUNT: 292 printf("high node count"); 293 break; 294 default: 295 printf("unknown %02x", command); 296 break; 297 } 298} 299 300static void 301cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 302{ 303 uint8_t length; 304 305 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 306 printf("vendor (length %d)", length); 307 if (p->pc_vendor == 0x8086) { 308 /* Intel */ 309 uint8_t version; 310 311 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 312 1); 313 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 314 if (version >> 4 == 1 && length == 12) { 315 /* Feature Detection */ 316 uint32_t fvec; 317 int comma; 318 319 comma = 0; 320 fvec = read_config(fd, &p->pc_sel, ptr + 321 PCIR_VENDOR_DATA + 5, 4); 322 printf("\n\t\t features:"); 323 if (fvec & (1 << 0)) { 324 printf(" AMT"); 325 comma = 1; 326 } 327 fvec = read_config(fd, &p->pc_sel, ptr + 328 PCIR_VENDOR_DATA + 1, 4); 329 if (fvec & (1 << 21)) { 330 printf("%s Quick Resume", comma ? "," : ""); 331 comma = 1; 332 } 333 if (fvec & (1 << 18)) { 334 printf("%s SATA RAID-5", comma ? "," : ""); 335 comma = 1; 336 } 337 if (fvec & (1 << 9)) { 338 printf("%s Mobile", comma ? "," : ""); 339 comma = 1; 340 } 341 if (fvec & (1 << 7)) { 342 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 343 comma = 1; 344 } else { 345 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 346 comma = 1; 347 } 348 if (fvec & (1 << 5)) { 349 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 350 comma = 1; 351 } 352 if (fvec & (1 << 3)) 353 printf(", SATA AHCI"); 354 } 355 } 356} 357 358static void 359cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 360{ 361 uint16_t debug_port; 362 363 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 364 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 365 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 366} 367 368static void 369cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 370{ 371 uint32_t id; 372 373 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 374 printf("PCI Bridge card=0x%08x", id); 375} 376 377#define MAX_PAYLOAD(field) (128 << (field)) 378 379static const char * 380link_speed_string(uint8_t speed) 381{ 382 383 switch (speed) { 384 case 1: 385 return ("2.5"); 386 case 2: 387 return ("5.0"); 388 case 3: 389 return ("8.0"); 390 default: 391 return ("undef"); 392 } 393} 394 395static const char * 396aspm_string(uint8_t aspm) 397{ 398 399 switch (aspm) { 400 case 1: 401 return ("L0s"); 402 case 2: 403 return ("L1"); 404 case 3: 405 return ("L0s/L1"); 406 default: 407 return ("disabled"); 408 } 409} 410 411static int 412slot_power(uint32_t cap) 413{ 414 int mwatts; 415 416 mwatts = (cap & PCIEM_SLOT_CAP_SPLV) >> 7; 417 switch (cap & PCIEM_SLOT_CAP_SPLS) { 418 case 0x0: 419 mwatts *= 1000; 420 break; 421 case 0x1: 422 mwatts *= 100; 423 break; 424 case 0x2: 425 mwatts *= 10; 426 break; 427 default: 428 break; 429 } 430 return (mwatts); 431} 432 433static void 434cap_express(int fd, struct pci_conf *p, uint8_t ptr) 435{ 436 uint32_t cap; 437 uint16_t ctl, flags, sta; 438 unsigned int version; 439 440 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 441 version = flags & PCIEM_FLAGS_VERSION; 442 printf("PCI-Express %u ", version); 443 switch (flags & PCIEM_FLAGS_TYPE) { 444 case PCIEM_TYPE_ENDPOINT: 445 printf("endpoint"); 446 break; 447 case PCIEM_TYPE_LEGACY_ENDPOINT: 448 printf("legacy endpoint"); 449 break; 450 case PCIEM_TYPE_ROOT_PORT: 451 printf("root port"); 452 break; 453 case PCIEM_TYPE_UPSTREAM_PORT: 454 printf("upstream port"); 455 break; 456 case PCIEM_TYPE_DOWNSTREAM_PORT: 457 printf("downstream port"); 458 break; 459 case PCIEM_TYPE_PCI_BRIDGE: 460 printf("PCI bridge"); 461 break; 462 case PCIEM_TYPE_PCIE_BRIDGE: 463 printf("PCI to PCIe bridge"); 464 break; 465 case PCIEM_TYPE_ROOT_INT_EP: 466 printf("root endpoint"); 467 break; 468 case PCIEM_TYPE_ROOT_EC: 469 printf("event collector"); 470 break; 471 default: 472 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 473 break; 474 } 475 if (flags & PCIEM_FLAGS_IRQ) 476 printf(" MSI %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 477 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 478 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 479 printf(" max data %d(%d)", 480 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5), 481 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD)); 482 if ((cap & PCIEM_CAP_FLR) != 0) 483 printf(" FLR"); 484 if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE) 485 printf(" RO"); 486 if (ctl & PCIEM_CTL_NOSNOOP_ENABLE) 487 printf(" NS"); 488 if (version >= 2) { 489 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4); 490 if ((cap & PCIEM_CAP2_ARI) != 0) { 491 ctl = read_config(fd, &p->pc_sel, 492 ptr + PCIER_DEVICE_CTL2, 4); 493 printf(" ARI %s", 494 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled"); 495 } 496 } 497 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 498 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2); 499 if (cap == 0 && sta == 0) 500 return; 501 printf("\n "); 502 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4, 503 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 504 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 505 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ? 506 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED), 507 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED)); 508 } 509 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 510 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 511 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC), 512 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10)); 513 } 514 if (!(flags & PCIEM_FLAGS_SLOT)) 515 return; 516 cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4); 517 sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_STA, 2); 518 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CTL, 2); 519 printf("\n "); 520 printf(" slot %d", (cap & PCIEM_SLOT_CAP_PSN) >> 19); 521 printf(" power limit %d mW", slot_power(cap)); 522 if (cap & PCIEM_SLOT_CAP_HPC) 523 printf(" HotPlug(%s)", sta & PCIEM_SLOT_STA_PDS ? "present" : 524 "empty"); 525 if (cap & PCIEM_SLOT_CAP_HPS) 526 printf(" surprise"); 527 if (cap & PCIEM_SLOT_CAP_APB) 528 printf(" Attn Button"); 529 if (cap & PCIEM_SLOT_CAP_PCP) 530 printf(" PC(%s)", ctl & PCIEM_SLOT_CTL_PCC ? "off" : "on"); 531 if (cap & PCIEM_SLOT_CAP_MRLSP) 532 printf(" MRL(%s)", sta & PCIEM_SLOT_STA_MRLSS ? "open" : 533 "closed"); 534 if (cap & PCIEM_SLOT_CAP_EIP) 535 printf(" EI(%s)", sta & PCIEM_SLOT_STA_EIS ? "engaged" : 536 "disengaged"); 537} 538 539static void 540cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 541{ 542 uint32_t pba_offset, table_offset, val; 543 int msgnum, pba_bar, table_bar; 544 uint16_t ctrl; 545 546 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 547 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 548 549 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 550 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 551 table_offset = val & ~PCIM_MSIX_BIR_MASK; 552 553 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 554 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 555 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 556 557 printf("MSI-X supports %d message%s%s\n", msgnum, 558 (msgnum == 1) ? "" : "s", 559 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 560 561 printf(" "); 562 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 563 table_bar, table_offset, pba_bar, pba_offset); 564} 565 566static void 567cap_sata(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 568{ 569 570 printf("SATA Index-Data Pair"); 571} 572 573static void 574cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 575{ 576 uint8_t cap; 577 578 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 579 printf("PCI Advanced Features:%s%s", 580 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 581 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 582} 583 584static const char * 585ea_bei_to_name(int bei) 586{ 587 static const char *barstr[] = { 588 "BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5" 589 }; 590 static const char *vfbarstr[] = { 591 "VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5" 592 }; 593 594 if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5)) 595 return (barstr[bei - PCIM_EA_BEI_BAR_0]); 596 if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5)) 597 return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]); 598 599 switch (bei) { 600 case PCIM_EA_BEI_BRIDGE: 601 return "BRIDGE"; 602 case PCIM_EA_BEI_ENI: 603 return "ENI"; 604 case PCIM_EA_BEI_ROM: 605 return "ROM"; 606 case PCIM_EA_BEI_RESERVED: 607 default: 608 return "RSVD"; 609 } 610} 611 612static const char * 613ea_prop_to_name(uint8_t prop) 614{ 615 616 switch (prop) { 617 case PCIM_EA_P_MEM: 618 return "Non-Prefetchable Memory"; 619 case PCIM_EA_P_MEM_PREFETCH: 620 return "Prefetchable Memory"; 621 case PCIM_EA_P_IO: 622 return "I/O Space"; 623 case PCIM_EA_P_VF_MEM_PREFETCH: 624 return "VF Prefetchable Memory"; 625 case PCIM_EA_P_VF_MEM: 626 return "VF Non-Prefetchable Memory"; 627 case PCIM_EA_P_BRIDGE_MEM: 628 return "Bridge Non-Prefetchable Memory"; 629 case PCIM_EA_P_BRIDGE_MEM_PREFETCH: 630 return "Bridge Prefetchable Memory"; 631 case PCIM_EA_P_BRIDGE_IO: 632 return "Bridge I/O Space"; 633 case PCIM_EA_P_MEM_RESERVED: 634 return "Reserved Memory"; 635 case PCIM_EA_P_IO_RESERVED: 636 return "Reserved I/O Space"; 637 case PCIM_EA_P_UNAVAILABLE: 638 return "Unavailable"; 639 default: 640 return "Reserved"; 641 } 642} 643 644static void 645cap_ea(int fd, struct pci_conf *p, uint8_t ptr) 646{ 647 int num_ent; 648 int a, b; 649 uint32_t bei; 650 uint32_t val; 651 int ent_size; 652 uint32_t dw[4]; 653 uint32_t flags, flags_pp, flags_sp; 654 uint64_t base, max_offset; 655 uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr; 656 657 /* Determine the number of entries */ 658 num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2); 659 num_ent &= PCIM_EA_NUM_ENT_MASK; 660 661 printf("PCI Enhanced Allocation (%d entries)", num_ent); 662 663 /* Find the first entry to care of */ 664 ptr += PCIR_EA_FIRST_ENT; 665 666 /* Print BUS numbers for bridges */ 667 if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) { 668 val = read_config(fd, &p->pc_sel, ptr, 4); 669 670 fixed_sec_bus_nr = PCIM_EA_SEC_NR(val); 671 fixed_sub_bus_nr = PCIM_EA_SUB_NR(val); 672 673 printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]", 674 fixed_sec_bus_nr, fixed_sub_bus_nr); 675 ptr += 4; 676 } 677 678 for (a = 0; a < num_ent; a++) { 679 /* Read a number of dwords in the entry */ 680 val = read_config(fd, &p->pc_sel, ptr, 4); 681 ptr += 4; 682 ent_size = (val & PCIM_EA_ES); 683 684 for (b = 0; b < ent_size; b++) { 685 dw[b] = read_config(fd, &p->pc_sel, ptr, 4); 686 ptr += 4; 687 } 688 689 flags = val; 690 flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET; 691 flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET; 692 bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 693 694 base = dw[0] & PCIM_EA_FIELD_MASK; 695 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 696 b = 2; 697 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 698 base |= (uint64_t)dw[b] << 32UL; 699 b++; 700 } 701 if (((dw[1] & PCIM_EA_IS_64) != 0) 702 && (b < ent_size)) { 703 max_offset |= (uint64_t)dw[b] << 32UL; 704 b++; 705 } 706 707 printf("\n\t\t [%d] %s, %s, %s, base [0x%jx], size [0x%jx]" 708 "\n\t\t\tPrimary properties [0x%x] (%s)" 709 "\n\t\t\tSecondary properties [0x%x] (%s)", 710 bei, ea_bei_to_name(bei), 711 (flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"), 712 (flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"), 713 (uintmax_t)base, (uintmax_t)(max_offset + 1), 714 flags_pp, ea_prop_to_name(flags_pp), 715 flags_sp, ea_prop_to_name(flags_sp)); 716 } 717} 718 719void 720list_caps(int fd, struct pci_conf *p) 721{ 722 int express; 723 uint16_t sta; 724 uint8_t ptr, cap; 725 726 /* Are capabilities present for this device? */ 727 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 728 if (!(sta & PCIM_STATUS_CAPPRESENT)) 729 return; 730 731 switch (p->pc_hdr & PCIM_HDRTYPE) { 732 case PCIM_HDRTYPE_NORMAL: 733 case PCIM_HDRTYPE_BRIDGE: 734 ptr = PCIR_CAP_PTR; 735 break; 736 case PCIM_HDRTYPE_CARDBUS: 737 ptr = PCIR_CAP_PTR_2; 738 break; 739 default: 740 errx(1, "list_caps: bad header type"); 741 } 742 743 /* Walk the capability list. */ 744 express = 0; 745 ptr = read_config(fd, &p->pc_sel, ptr, 1); 746 while (ptr != 0 && ptr != 0xff) { 747 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 748 printf(" cap %02x[%02x] = ", cap, ptr); 749 switch (cap) { 750 case PCIY_PMG: 751 cap_power(fd, p, ptr); 752 break; 753 case PCIY_AGP: 754 cap_agp(fd, p, ptr); 755 break; 756 case PCIY_VPD: 757 cap_vpd(fd, p, ptr); 758 break; 759 case PCIY_MSI: 760 cap_msi(fd, p, ptr); 761 break; 762 case PCIY_PCIX: 763 cap_pcix(fd, p, ptr); 764 break; 765 case PCIY_HT: 766 cap_ht(fd, p, ptr); 767 break; 768 case PCIY_VENDOR: 769 cap_vendor(fd, p, ptr); 770 break; 771 case PCIY_DEBUG: 772 cap_debug(fd, p, ptr); 773 break; 774 case PCIY_SUBVENDOR: 775 cap_subvendor(fd, p, ptr); 776 break; 777 case PCIY_EXPRESS: 778 express = 1; 779 cap_express(fd, p, ptr); 780 break; 781 case PCIY_MSIX: 782 cap_msix(fd, p, ptr); 783 break; 784 case PCIY_SATA: 785 cap_sata(fd, p, ptr); 786 break; 787 case PCIY_PCIAF: 788 cap_pciaf(fd, p, ptr); 789 break; 790 case PCIY_EA: 791 cap_ea(fd, p, ptr); 792 break; 793 default: 794 printf("unknown"); 795 break; 796 } 797 printf("\n"); 798 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 799 } 800 801 if (express) 802 list_ecaps(fd, p); 803} 804 805/* From <sys/systm.h>. */ 806static __inline uint32_t 807bitcount32(uint32_t x) 808{ 809 810 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 811 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 812 x = (x + (x >> 4)) & 0x0f0f0f0f; 813 x = (x + (x >> 8)); 814 x = (x + (x >> 16)) & 0x000000ff; 815 return (x); 816} 817 818static void 819ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 820{ 821 uint32_t sta, mask; 822 823 printf("AER %d", ver); 824 if (ver < 1) 825 return; 826 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 827 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 828 printf(" %d fatal", bitcount32(sta & mask)); 829 printf(" %d non-fatal", bitcount32(sta & ~mask)); 830 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 831 printf(" %d corrected\n", bitcount32(sta)); 832} 833 834static void 835ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 836{ 837 uint32_t cap1; 838 839 printf("VC %d", ver); 840 if (ver < 1) 841 return; 842 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 843 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 844 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 845 printf(" lowpri VC0-VC%d", 846 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 847 printf("\n"); 848} 849 850static void 851ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 852{ 853 uint32_t high, low; 854 855 printf("Serial %d", ver); 856 if (ver < 1) 857 return; 858 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 859 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 860 printf(" %08x%08x\n", high, low); 861} 862 863static void 864ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 865{ 866 uint32_t val; 867 868 printf("Vendor %d", ver); 869 if (ver < 1) 870 return; 871 val = read_config(fd, &p->pc_sel, ptr + 4, 4); 872 printf(" ID %d\n", val & 0xffff); 873} 874 875static void 876ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 877{ 878 uint32_t val; 879 880 printf("PCIe Sec %d", ver); 881 if (ver < 1) 882 return; 883 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 884 printf(" lane errors %#x\n", val); 885} 886 887static const char * 888check_enabled(int value) 889{ 890 891 return (value ? "enabled" : "disabled"); 892} 893 894static void 895ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 896{ 897 const char *comma, *enabled; 898 uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did; 899 uint32_t page_caps, page_size, page_shift, size; 900 int i; 901 902 printf("SR-IOV %d ", ver); 903 904 iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2); 905 printf("IOV %s, Memory Space %s, ARI %s\n", 906 check_enabled(iov_ctl & PCIM_SRIOV_VF_EN), 907 check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE), 908 check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN)); 909 910 total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2); 911 num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2); 912 printf(" "); 913 printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs); 914 915 vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2); 916 vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2); 917 printf(" "); 918 printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset, 919 vf_stride); 920 921 vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2); 922 printf(" VF Device ID 0x%04x\n", vf_did); 923 924 page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4); 925 page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4); 926 printf(" "); 927 printf("Page Sizes: "); 928 comma = ""; 929 while (page_caps != 0) { 930 page_shift = ffs(page_caps) - 1; 931 932 if (page_caps & page_size) 933 enabled = " (enabled)"; 934 else 935 enabled = ""; 936 937 size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT)); 938 printf("%s%d%s", comma, size, enabled); 939 comma = ", "; 940 941 page_caps &= ~(1 << page_shift); 942 } 943 printf("\n"); 944 945 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 946 print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i)); 947} 948 949static struct { 950 uint16_t id; 951 const char *name; 952} ecap_names[] = { 953 { PCIZ_PWRBDGT, "Power Budgeting" }, 954 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 955 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 956 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 957 { PCIZ_MFVC, "MFVC" }, 958 { PCIZ_RCRB, "RCRB" }, 959 { PCIZ_ACS, "ACS" }, 960 { PCIZ_ARI, "ARI" }, 961 { PCIZ_ATS, "ATS" }, 962 { PCIZ_MULTICAST, "Multicast" }, 963 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 964 { PCIZ_DPA, "DPA" }, 965 { PCIZ_TPH_REQ, "TPH Requester" }, 966 { PCIZ_LTR, "LTR" }, 967 { 0, NULL } 968}; 969 970static void 971list_ecaps(int fd, struct pci_conf *p) 972{ 973 const char *name; 974 uint32_t ecap; 975 uint16_t ptr; 976 int i; 977 978 ptr = PCIR_EXTCAP; 979 ecap = read_config(fd, &p->pc_sel, ptr, 4); 980 if (ecap == 0xffffffff || ecap == 0) 981 return; 982 for (;;) { 983 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 984 switch (PCI_EXTCAP_ID(ecap)) { 985 case PCIZ_AER: 986 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 987 break; 988 case PCIZ_VC: 989 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 990 break; 991 case PCIZ_SERNUM: 992 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 993 break; 994 case PCIZ_VENDOR: 995 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 996 break; 997 case PCIZ_SEC_PCIE: 998 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 999 break; 1000 case PCIZ_SRIOV: 1001 ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1002 break; 1003 default: 1004 name = "unknown"; 1005 for (i = 0; ecap_names[i].name != NULL; i++) 1006 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 1007 name = ecap_names[i].name; 1008 break; 1009 } 1010 printf("%s %d\n", name, PCI_EXTCAP_VER(ecap)); 1011 break; 1012 } 1013 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1014 if (ptr == 0) 1015 break; 1016 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1017 } 1018} 1019 1020/* Find offset of a specific capability. Returns 0 on failure. */ 1021uint8_t 1022pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 1023{ 1024 uint16_t sta; 1025 uint8_t ptr, cap; 1026 1027 /* Are capabilities present for this device? */ 1028 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 1029 if (!(sta & PCIM_STATUS_CAPPRESENT)) 1030 return (0); 1031 1032 switch (p->pc_hdr & PCIM_HDRTYPE) { 1033 case PCIM_HDRTYPE_NORMAL: 1034 case PCIM_HDRTYPE_BRIDGE: 1035 ptr = PCIR_CAP_PTR; 1036 break; 1037 case PCIM_HDRTYPE_CARDBUS: 1038 ptr = PCIR_CAP_PTR_2; 1039 break; 1040 default: 1041 return (0); 1042 } 1043 1044 ptr = read_config(fd, &p->pc_sel, ptr, 1); 1045 while (ptr != 0 && ptr != 0xff) { 1046 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 1047 if (cap == id) 1048 return (ptr); 1049 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 1050 } 1051 return (0); 1052} 1053 1054/* Find offset of a specific extended capability. Returns 0 on failure. */ 1055uint16_t 1056pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 1057{ 1058 uint32_t ecap; 1059 uint16_t ptr; 1060 1061 ptr = PCIR_EXTCAP; 1062 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1063 if (ecap == 0xffffffff || ecap == 0) 1064 return (0); 1065 for (;;) { 1066 if (PCI_EXTCAP_ID(ecap) == id) 1067 return (ptr); 1068 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1069 if (ptr == 0) 1070 break; 1071 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1072 } 1073 return (0); 1074} 1075