intr_machdep.h revision 367457 
1/*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/11/sys/x86/include/intr_machdep.h 367457 2020-11-07 18:10:59Z dim $
26 */
27
28#ifndef __X86_INTR_MACHDEP_H__
29#define	__X86_INTR_MACHDEP_H__
30
31#ifdef _KERNEL
32
33/*
34 * Values used in determining the allocation of IRQ values among
35 * different types of I/O interrupts.  These values are used as
36 * indices into a interrupt source array to map I/O interrupts to a
37 * device interrupt source whether it be a pin on an interrupt
38 * controller or an MSI interrupt.  The 16 ISA IRQs are assigned fixed
39 * IDT vectors, but all other device interrupts allocate IDT vectors
40 * on demand.  Currently we have 191 IDT vectors available for device
41 * interrupts on each CPU.  On many systems with I/O APICs, a lot of
42 * the IRQs are not used, so the total number of IRQ values reserved
43 * can exceed the number of available IDT slots.
44 *
45 * The first 16 IRQs (0 - 15) are reserved for ISA IRQs.  Interrupt
46 * pins on I/O APICs for non-ISA interrupts use IRQ values starting at
47 * IRQ 17.  This layout matches the GSI numbering used by ACPI so that
48 * IRQ values returned by ACPI methods such as _CRS can be used
49 * directly by the ACPI bus driver.
50 *
51 * MSI interrupts allocate a block of interrupts starting at either
52 * the end of the I/O APIC range or 256, whichever is higher.  When
53 * running under the Xen Hypervisor, an additional range of IRQ values
54 * are available for binding to event channel events.  We use 256 as
55 * the minimum IRQ value for MSI interrupts to attempt to leave 255
56 * unused since 255 is used in PCI to indicate an invalid INTx IRQ.
57 */
58#define	MINIMUM_MSI_INT	256
59
60extern u_int first_msi_irq;
61extern u_int num_io_irqs;
62extern u_int num_msi_irqs;
63
64/*
65 * Default base address for MSI messages on x86 platforms.
66 */
67#define	MSI_INTEL_ADDR_BASE		0xfee00000
68
69#ifndef LOCORE
70
71typedef void inthand_t(void);
72
73#define	IDTVEC(name)	__CONCAT(X,name)
74
75struct intsrc;
76
77/*
78 * Methods that a PIC provides to mask/unmask a given interrupt source,
79 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
80 * return the vector associated with this source.
81 */
82struct pic {
83	void (*pic_register_sources)(struct pic *);
84	void (*pic_enable_source)(struct intsrc *);
85	void (*pic_disable_source)(struct intsrc *, int);
86	void (*pic_eoi_source)(struct intsrc *);
87	void (*pic_enable_intr)(struct intsrc *);
88	void (*pic_disable_intr)(struct intsrc *);
89	int (*pic_vector)(struct intsrc *);
90	int (*pic_source_pending)(struct intsrc *);
91	void (*pic_suspend)(struct pic *);
92	void (*pic_resume)(struct pic *, bool suspend_cancelled);
93	int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
94	    enum intr_polarity);
95	int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
96	void (*pic_reprogram_pin)(struct intsrc *);
97	TAILQ_ENTRY(pic) pics;
98};
99
100/* Flags for pic_disable_source() */
101enum {
102	PIC_EOI,
103	PIC_NO_EOI,
104};
105
106/*
107 * An interrupt source.  The upper-layer code uses the PIC methods to
108 * control a given source.  The lower-layer PIC drivers can store additional
109 * private data in a given interrupt source such as an interrupt pin number
110 * or an I/O APIC pointer.
111 */
112struct intsrc {
113	struct pic *is_pic;
114	struct intr_event *is_event;
115	u_long *is_count;
116	u_long *is_straycount;
117	u_int is_index;
118	u_int is_handlers;
119};
120
121struct trapframe;
122
123#ifdef SMP
124extern cpuset_t intr_cpus;
125#endif
126extern struct mtx icu_lock;
127extern int elcr_found;
128#ifdef SMP
129extern int msix_disable_migration;
130#endif
131
132#ifndef DEV_ATPIC
133void	atpic_reset(void);
134#endif
135/* XXX: The elcr_* prototypes probably belong somewhere else. */
136int	elcr_probe(void);
137enum intr_trigger elcr_read_trigger(u_int irq);
138void	elcr_resume(void);
139void	elcr_write_trigger(u_int irq, enum intr_trigger trigger);
140#ifdef SMP
141void	intr_add_cpu(u_int cpu);
142#endif
143int	intr_add_handler(const char *name, int vector, driver_filter_t filter,
144			 driver_intr_t handler, void *arg, enum intr_type flags,
145			 void **cookiep);
146#ifdef SMP
147int	intr_bind(u_int vector, u_char cpu);
148#endif
149int	intr_config_intr(int vector, enum intr_trigger trig,
150    enum intr_polarity pol);
151int	intr_describe(u_int vector, void *ih, const char *descr);
152void	intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
153u_int	intr_next_cpu(void);
154struct intsrc *intr_lookup_source(int vector);
155int	intr_register_pic(struct pic *pic);
156int	intr_register_source(struct intsrc *isrc);
157int	intr_remove_handler(void *cookie);
158void	intr_resume(bool suspend_cancelled);
159void	intr_suspend(void);
160void	intr_reprogram(void);
161void	intrcnt_add(const char *name, u_long **countp);
162void	nexus_add_irq(u_long irq);
163int	msi_alloc(device_t dev, int count, int maxcount, int *irqs);
164void	msi_init(void);
165int	msi_map(int irq, uint64_t *addr, uint32_t *data);
166int	msi_release(int *irqs, int count);
167int	msix_alloc(device_t dev, int *irq);
168int	msix_release(int irq);
169#ifdef XENHVM
170void	xen_intr_alloc_irqs(void);
171#endif
172
173#endif	/* !LOCORE */
174#endif	/* _KERNEL */
175#endif	/* !__X86_INTR_MACHDEP_H__ */
176