gpio.h revision 324755
1/* $NetBSD: gpio.h,v 1.7 2009/09/25 20:27:50 mbalmer Exp $ */ 2/* $OpenBSD: gpio.h,v 1.7 2008/11/26 14:51:20 mbalmer Exp $ */ 3/*- 4 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/sys/gpio.h 324755 2017-10-19 16:07:57Z ian $ 30 * 31 */ 32 33/* 34 * Copyright (c) 2009 Marc Balmer <marc@msys.ch> 35 * Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50#ifndef __GPIO_H__ 51#define __GPIO_H__ 52 53#include <sys/ioccom.h> 54 55/* GPIO pin states */ 56#define GPIO_PIN_LOW 0x00 /* low level (logical 0) */ 57#define GPIO_PIN_HIGH 0x01 /* high level (logical 1) */ 58 59/* Max name length of a pin */ 60#define GPIOMAXNAME 64 61 62/* GPIO pin configuration flags */ 63#define GPIO_PIN_INPUT 0x00000001 /* input direction */ 64#define GPIO_PIN_OUTPUT 0x00000002 /* output direction */ 65#define GPIO_PIN_OPENDRAIN 0x00000004 /* open-drain output */ 66#define GPIO_PIN_PUSHPULL 0x00000008 /* push-pull output */ 67#define GPIO_PIN_TRISTATE 0x00000010 /* output disabled */ 68#define GPIO_PIN_PULLUP 0x00000020 /* internal pull-up enabled */ 69#define GPIO_PIN_PULLDOWN 0x00000040 /* internal pull-down enabled */ 70#define GPIO_PIN_INVIN 0x00000080 /* invert input */ 71#define GPIO_PIN_INVOUT 0x00000100 /* invert output */ 72#define GPIO_PIN_PULSATE 0x00000200 /* pulsate in hardware */ 73#define GPIO_PIN_PRESET_LOW 0x00000400 /* preset pin to high or */ 74#define GPIO_PIN_PRESET_HIGH 0x00000800 /* low before enabling output */ 75/* GPIO interrupt capabilities */ 76#define GPIO_INTR_NONE 0x00000000 /* no interrupt support */ 77#define GPIO_INTR_LEVEL_LOW 0x00010000 /* level trigger, low */ 78#define GPIO_INTR_LEVEL_HIGH 0x00020000 /* level trigger, high */ 79#define GPIO_INTR_EDGE_RISING 0x00040000 /* edge trigger, rising */ 80#define GPIO_INTR_EDGE_FALLING 0x00080000 /* edge trigger, falling */ 81#define GPIO_INTR_EDGE_BOTH 0x00100000 /* edge trigger, both */ 82#define GPIO_INTR_MASK (GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | \ 83 GPIO_INTR_EDGE_RISING | \ 84 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 85 86struct gpio_pin { 87 uint32_t gp_pin; /* pin number */ 88 char gp_name[GPIOMAXNAME]; /* human-readable name */ 89 uint32_t gp_caps; /* capabilities */ 90 uint32_t gp_flags; /* current flags */ 91}; 92 93/* GPIO pin request (read/write/toggle) */ 94struct gpio_req { 95 uint32_t gp_pin; /* pin number */ 96 uint32_t gp_value; /* value */ 97}; 98 99/* 100 * gpio_access_32 / GPIOACCESS32 101 * 102 * Simultaneously read and/or change up to 32 adjacent pins. 103 * If the device cannot change the pins simultaneously, returns EOPNOTSUPP. 104 * 105 * This accesses an adjacent set of up to 32 pins starting at first_pin within 106 * the device's collection of pins. How the hardware pins are mapped to the 32 107 * bits in the arguments is device-specific. It is expected that lower-numbered 108 * pins in the device's number space map linearly to lower-ordered bits within 109 * the 32-bit words (i.e., bit 0 is first_pin, bit 1 is first_pin+1, etc). 110 * Other mappings are possible; know your device. 111 * 112 * Some devices may limit the value of first_pin to 0, or to multiples of 16 or 113 * 32 or some other hardware-specific number; to access pin 2 would require 114 * first_pin to be zero and then manipulate bit (1 << 2) in the 32-bit word. 115 * Invalid values in first_pin result in an EINVAL error return. 116 * 117 * The starting state of the pins is captured and stored in orig_pins, then the 118 * pins are set to ((starting_state & ~clear_pins) ^ change_pins). 119 * 120 * Clear Change Hardware pin after call 121 * 0 0 No change 122 * 0 1 Opposite of current value 123 * 1 0 Cleared 124 * 1 1 Set 125 */ 126struct gpio_access_32 { 127 uint32_t first_pin; /* First pin in group of 32 adjacent */ 128 uint32_t clear_pins; /* Pins are changed using: */ 129 uint32_t change_pins; /* ((hwstate & ~clear_pins) ^ change_pins) */ 130 uint32_t orig_pins; /* Returned hwstate of pins before change. */ 131}; 132 133/* 134 * gpio_config_32 / GPIOCONFIG32 135 * 136 * Simultaneously configure up to 32 adjacent pins. This is intended to change 137 * the configuration of all the pins simultaneously, such that pins configured 138 * for output all begin to drive the configured values simultaneously, but not 139 * all hardware can do that, so the driver "does the best it can" in this 140 * regard. Notably unlike pin_access_32(), this does NOT fail if the pins 141 * cannot be atomically configured; it is expected that callers understand the 142 * hardware and have decided to live with any such limitations it may have. 143 * 144 * The pin_flags argument is an array of GPIO_PIN_xxxx flags. If the array 145 * contains any GPIO_PIN_OUTPUT flags, the driver will manipulate the hardware 146 * such that all output pins become driven with the proper initial values 147 * simultaneously if it can. The elements in the array map to pins in the same 148 * way that bits are mapped by pin_acces_32(), and the same restrictions may 149 * apply. For example, to configure pins 2 and 3 it may be necessary to set 150 * first_pin to zero and only populate pin_flags[2] and pin_flags[3]. If a 151 * given array entry doesn't contain GPIO_PIN_INPUT or GPIO_PIN_OUTPUT then no 152 * configuration is done for that pin. 153 * 154 * Some devices may limit the value of first_pin to 0, or to multiples of 16 or 155 * 32 or some other hardware-specific number. Invalid values in first_pin or 156 * num_pins result in an error return with errno set to EINVAL. 157 */ 158struct gpio_config_32 { 159 uint32_t first_pin; 160 uint32_t num_pins; 161 uint32_t pin_flags[32]; 162}; 163 164/* 165 * ioctls 166 */ 167#define GPIOMAXPIN _IOR('G', 0, int) 168#define GPIOGETCONFIG _IOWR('G', 1, struct gpio_pin) 169#define GPIOSETCONFIG _IOW('G', 2, struct gpio_pin) 170#define GPIOGET _IOWR('G', 3, struct gpio_req) 171#define GPIOSET _IOW('G', 4, struct gpio_req) 172#define GPIOTOGGLE _IOWR('G', 5, struct gpio_req) 173#define GPIOSETNAME _IOW('G', 6, struct gpio_pin) 174#define GPIOACCESS32 _IOWR('G', 7, struct gpio_access_32) 175#define GPIOCONFIG32 _IOW('G', 8, struct gpio_config_32) 176 177#endif /* __GPIO_H__ */ 178