viareg.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (C) 2008 Nathan Whitehorn
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/11/sys/powerpc/powermac/viareg.h 330897 2018-03-14 03:19:51Z eadler $
28 */
29
30#ifndef	_POWERPC_VIAREG_H_
31#define	_POWERPC_VIAREG_H_
32
33/* VIA interface registers */
34#define vBufB		0x0000	/* register B */
35#define vDirB		0x0400	/* data direction register */
36#define vDirA		0x0600	/* data direction register */
37#define vT1C		0x0800	/* Timer 1 counter Lo */
38#define vT1CH		0x0a00	/* Timer 1 counter Hi */
39#define vSR		0x1400	/* shift register */
40#define vACR		0x1600	/* aux control register */
41#define vPCR		0x1800	/* peripheral control register */
42#define vIFR		0x1a00	/* interrupt flag register */
43#define vIER		0x1c00	/* interrupt enable register */
44#define vBufA		0x1e00	/* register A */
45
46#define vPB		0x0000
47#define vPB3		0x08
48#define vPB4		0x10
49#define vPB5		0x20
50#define vSR_INT		0x04
51#define vSR_OUT		0x10
52
53#endif /* _POWERPC_VIAREG_H_ */
54