pci_mpc85xx.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2006-2007 by Juniper Networks. 5 * Copyright 2008 Semihalf. 6 * Copyright 2010 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 36 */ 37 38#include <sys/cdefs.h> 39__FBSDID("$FreeBSD: stable/11/sys/powerpc/mpc85xx/pci_mpc85xx.c 330897 2018-03-14 03:19:51Z eadler $"); 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/ktr.h> 44#include <sys/sockio.h> 45#include <sys/mbuf.h> 46#include <sys/malloc.h> 47#include <sys/kernel.h> 48#include <sys/module.h> 49#include <sys/socket.h> 50#include <sys/queue.h> 51#include <sys/bus.h> 52#include <sys/lock.h> 53#include <sys/mutex.h> 54#include <sys/rman.h> 55#include <sys/endian.h> 56 57#include <vm/vm.h> 58#include <vm/pmap.h> 59 60#include <dev/ofw/ofw_pci.h> 61#include <dev/ofw/ofw_bus.h> 62#include <dev/ofw/ofw_bus_subr.h> 63#include <dev/ofw/ofwpci.h> 64#include <dev/pci/pcivar.h> 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcib_private.h> 67 68#include "ofw_bus_if.h" 69#include "pcib_if.h" 70 71#include <machine/resource.h> 72#include <machine/bus.h> 73#include <machine/intr_machdep.h> 74 75#include <powerpc/mpc85xx/mpc85xx.h> 76 77#define REG_CFG_ADDR 0x0000 78#define CONFIG_ACCESS_ENABLE 0x80000000 79 80#define REG_CFG_DATA 0x0004 81#define REG_INT_ACK 0x0008 82 83#define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 84#define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 85#define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 86#define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 87 88#define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 89#define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 90#define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 91#define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 92 93#define REG_PEX_MES_DR 0x0020 94#define REG_PEX_MES_IER 0x0028 95#define REG_PEX_ERR_DR 0x0e00 96#define REG_PEX_ERR_EN 0x0e08 97 98#define REG_PEX_ERR_DR 0x0e00 99#define REG_PEX_ERR_DR_ME 0x80000000 100#define REG_PEX_ERR_DR_PCT 0x800000 101#define REG_PEX_ERR_DR_PAT 0x400000 102#define REG_PEX_ERR_DR_PCAC 0x200000 103#define REG_PEX_ERR_DR_PNM 0x100000 104#define REG_PEX_ERR_DR_CDNSC 0x80000 105#define REG_PEX_ERR_DR_CRSNC 0x40000 106#define REG_PEX_ERR_DR_ICCA 0x20000 107#define REG_PEX_ERR_DR_IACA 0x10000 108#define REG_PEX_ERR_DR_CRST 0x8000 109#define REG_PEX_ERR_DR_MIS 0x4000 110#define REG_PEX_ERR_DR_IOIS 0x2000 111#define REG_PEX_ERR_DR_CIS 0x1000 112#define REG_PEX_ERR_DR_CIEP 0x800 113#define REG_PEX_ERR_DR_IOIEP 0x400 114#define REG_PEX_ERR_DR_OAC 0x200 115#define REG_PEX_ERR_DR_IOIA 0x100 116#define REG_PEX_ERR_DR_IMBA 0x80 117#define REG_PEX_ERR_DR_IIOBA 0x40 118#define REG_PEX_ERR_DR_LDDE 0x20 119#define REG_PEX_ERR_EN 0x0e08 120 121#define PCIR_LTSSM 0x404 122#define LTSSM_STAT_L0 0x16 123 124#define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 125 126struct fsl_pcib_softc { 127 struct ofw_pci_softc pci_sc; 128 device_t sc_dev; 129 130 int sc_iomem_target; 131 bus_addr_t sc_iomem_start, sc_iomem_end; 132 int sc_ioport_target; 133 bus_addr_t sc_ioport_start, sc_ioport_end; 134 135 struct resource *sc_res; 136 bus_space_handle_t sc_bsh; 137 bus_space_tag_t sc_bst; 138 int sc_rid; 139 140 struct resource *sc_irq_res; 141 void *sc_ih; 142 143 int sc_busnr; 144 int sc_pcie; 145 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 146 147 /* Devices that need special attention. */ 148 int sc_devfn_tundra; 149 int sc_devfn_via_ide; 150}; 151 152struct fsl_pcib_err_dr { 153 const char *msg; 154 uint32_t err_dr_mask; 155}; 156 157static const struct fsl_pcib_err_dr pci_err[] = { 158 {"ME", REG_PEX_ERR_DR_ME}, 159 {"PCT", REG_PEX_ERR_DR_PCT}, 160 {"PAT", REG_PEX_ERR_DR_PAT}, 161 {"PCAC", REG_PEX_ERR_DR_PCAC}, 162 {"PNM", REG_PEX_ERR_DR_PNM}, 163 {"CDNSC", REG_PEX_ERR_DR_CDNSC}, 164 {"CRSNC", REG_PEX_ERR_DR_CRSNC}, 165 {"ICCA", REG_PEX_ERR_DR_ICCA}, 166 {"IACA", REG_PEX_ERR_DR_IACA}, 167 {"CRST", REG_PEX_ERR_DR_CRST}, 168 {"MIS", REG_PEX_ERR_DR_MIS}, 169 {"IOIS", REG_PEX_ERR_DR_IOIS}, 170 {"CIS", REG_PEX_ERR_DR_CIS}, 171 {"CIEP", REG_PEX_ERR_DR_CIEP}, 172 {"IOIEP", REG_PEX_ERR_DR_IOIEP}, 173 {"OAC", REG_PEX_ERR_DR_OAC}, 174 {"IOIA", REG_PEX_ERR_DR_IOIA}, 175 {"IMBA", REG_PEX_ERR_DR_IMBA}, 176 {"IIOBA", REG_PEX_ERR_DR_IIOBA}, 177 {"LDDE", REG_PEX_ERR_DR_LDDE} 178}; 179 180/* Local forward declerations. */ 181static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 182 u_int, int); 183static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 184 u_int, uint32_t, int); 185static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 186static void fsl_pcib_err_init(device_t); 187static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 188 uint64_t, uint64_t); 189static int fsl_pcib_init(struct fsl_pcib_softc *, int, int); 190static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 191 uint64_t, uint64_t); 192 193/* Forward declerations. */ 194static int fsl_pcib_attach(device_t); 195static int fsl_pcib_detach(device_t); 196static int fsl_pcib_probe(device_t); 197 198static int fsl_pcib_maxslots(device_t); 199static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 200static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 201 uint32_t, int); 202 203/* Configuration r/w mutex. */ 204struct mtx pcicfg_mtx; 205static int mtx_initialized = 0; 206 207/* 208 * Bus interface definitions. 209 */ 210static device_method_t fsl_pcib_methods[] = { 211 /* Device interface */ 212 DEVMETHOD(device_probe, fsl_pcib_probe), 213 DEVMETHOD(device_attach, fsl_pcib_attach), 214 DEVMETHOD(device_detach, fsl_pcib_detach), 215 216 /* pcib interface */ 217 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 218 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 219 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 220 221 DEVMETHOD_END 222}; 223 224static devclass_t fsl_pcib_devclass; 225 226DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 227 sizeof(struct fsl_pcib_softc), ofw_pci_driver); 228DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0); 229 230static int 231fsl_pcib_err_intr(void *v) 232{ 233 struct fsl_pcib_softc *sc; 234 device_t dev; 235 uint32_t err_reg, clear_reg; 236 uint8_t i; 237 238 dev = (device_t)v; 239 sc = device_get_softc(dev); 240 241 clear_reg = 0; 242 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR); 243 244 /* Check which one error occurred */ 245 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { 246 if (err_reg & pci_err[i].err_dr_mask) { 247 device_printf(dev, "PCI %d: report %s error\n", 248 device_get_unit(dev), pci_err[i].msg); 249 clear_reg |= pci_err[i].err_dr_mask; 250 } 251 } 252 253 /* Clear pending errors */ 254 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg); 255 256 return (0); 257} 258 259static int 260fsl_pcib_probe(device_t dev) 261{ 262 263 if (ofw_bus_get_type(dev) == NULL || 264 strcmp(ofw_bus_get_type(dev), "pci") != 0) 265 return (ENXIO); 266 267 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 268 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 269 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 270 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 271 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 272 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 273 return (ENXIO); 274 275 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 276 return (BUS_PROBE_DEFAULT); 277} 278 279static int 280fsl_pcib_attach(device_t dev) 281{ 282 struct fsl_pcib_softc *sc; 283 phandle_t node; 284 uint32_t cfgreg; 285 int error, maxslot, rid; 286 uint8_t ltssm, capptr; 287 288 sc = device_get_softc(dev); 289 sc->sc_dev = dev; 290 291 sc->sc_rid = 0; 292 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 293 RF_ACTIVE); 294 if (sc->sc_res == NULL) { 295 device_printf(dev, "could not map I/O memory\n"); 296 return (ENXIO); 297 } 298 sc->sc_bst = rman_get_bustag(sc->sc_res); 299 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 300 sc->sc_busnr = 0; 301 302 if (!mtx_initialized) { 303 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 304 mtx_initialized = 1; 305 } 306 307 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 308 if (cfgreg != 0x1057 && cfgreg != 0x1957) 309 goto err; 310 311 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 312 while (capptr != 0) { 313 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 314 switch (cfgreg & 0xff) { 315 case PCIY_PCIX: 316 break; 317 case PCIY_EXPRESS: 318 sc->sc_pcie = 1; 319 sc->sc_pcie_capreg = capptr; 320 break; 321 } 322 capptr = (cfgreg >> 8) & 0xff; 323 } 324 325 node = ofw_bus_get_node(dev); 326 327 /* 328 * Initialize generic OF PCI interface (ranges, etc.) 329 */ 330 331 error = ofw_pci_init(dev); 332 if (error) 333 return (error); 334 335 /* 336 * Configure decode windows for PCI(E) access. 337 */ 338 if (fsl_pcib_decode_win(node, sc) != 0) 339 goto err; 340 341 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 342 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 343 PCIM_CMD_PORTEN; 344 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 345 346 sc->sc_devfn_tundra = -1; 347 sc->sc_devfn_via_ide = -1; 348 349 350 /* 351 * Scan bus using firmware configured, 0 based bus numbering. 352 */ 353 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX; 354 fsl_pcib_init(sc, sc->sc_busnr, maxslot); 355 356 if (sc->sc_pcie) { 357 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 358 if (ltssm < LTSSM_STAT_L0) { 359 if (bootverbose) 360 printf("PCI %d: no PCIE link, skipping\n", 361 device_get_unit(dev)); 362 return (0); 363 } 364 } 365 366 /* Allocate irq */ 367 rid = 0; 368 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 369 RF_ACTIVE | RF_SHAREABLE); 370 if (sc->sc_irq_res == NULL) { 371 error = fsl_pcib_detach(dev); 372 if (error != 0) { 373 device_printf(dev, 374 "Detach of the driver failed with error %d\n", 375 error); 376 } 377 return (ENXIO); 378 } 379 380 /* Setup interrupt handler */ 381 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 382 NULL, (driver_intr_t *)fsl_pcib_err_intr, dev, &sc->sc_ih); 383 if (error != 0) { 384 device_printf(dev, "Could not setup irq, %d\n", error); 385 sc->sc_ih = NULL; 386 error = fsl_pcib_detach(dev); 387 if (error != 0) { 388 device_printf(dev, 389 "Detach of the driver failed with error %d\n", 390 error); 391 } 392 return (ENXIO); 393 } 394 395 fsl_pcib_err_init(dev); 396 397 return (ofw_pci_attach(dev)); 398 399err: 400 return (ENXIO); 401} 402 403static uint32_t 404fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 405 u_int reg, int bytes) 406{ 407 uint32_t addr, data; 408 409 addr = CONFIG_ACCESS_ENABLE; 410 addr |= (bus & 0xff) << 16; 411 addr |= (slot & 0x1f) << 11; 412 addr |= (func & 0x7) << 8; 413 addr |= reg & 0xfc; 414 if (sc->sc_pcie) 415 addr |= (reg & 0xf00) << 16; 416 417 mtx_lock_spin(&pcicfg_mtx); 418 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 419 420 switch (bytes) { 421 case 1: 422 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 423 REG_CFG_DATA + (reg & 3)); 424 break; 425 case 2: 426 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 427 REG_CFG_DATA + (reg & 2))); 428 break; 429 case 4: 430 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 431 REG_CFG_DATA)); 432 break; 433 default: 434 data = ~0; 435 break; 436 } 437 mtx_unlock_spin(&pcicfg_mtx); 438 return (data); 439} 440 441static void 442fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 443 u_int reg, uint32_t data, int bytes) 444{ 445 uint32_t addr; 446 447 addr = CONFIG_ACCESS_ENABLE; 448 addr |= (bus & 0xff) << 16; 449 addr |= (slot & 0x1f) << 11; 450 addr |= (func & 0x7) << 8; 451 addr |= reg & 0xfc; 452 if (sc->sc_pcie) 453 addr |= (reg & 0xf00) << 16; 454 455 mtx_lock_spin(&pcicfg_mtx); 456 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 457 458 switch (bytes) { 459 case 1: 460 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 461 REG_CFG_DATA + (reg & 3), data); 462 break; 463 case 2: 464 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 465 REG_CFG_DATA + (reg & 2), htole16(data)); 466 break; 467 case 4: 468 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 469 REG_CFG_DATA, htole32(data)); 470 break; 471 } 472 mtx_unlock_spin(&pcicfg_mtx); 473} 474 475#if 0 476static void 477dump(struct fsl_pcib_softc *sc) 478{ 479 unsigned int i; 480 481#define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 482 for (i = 0; i < 5; i++) { 483 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 484 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 485 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 486 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 487 } 488 printf("\n"); 489 for (i = 1; i < 4; i++) { 490 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 491 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 492 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 493 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 494 } 495 printf("\n"); 496#undef RD 497 498 for (i = 0; i < 0x48; i += 4) { 499 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 500 i, 4)); 501 } 502} 503#endif 504 505static int 506fsl_pcib_maxslots(device_t dev) 507{ 508 struct fsl_pcib_softc *sc = device_get_softc(dev); 509 510 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 511} 512 513static uint32_t 514fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 515 u_int reg, int bytes) 516{ 517 struct fsl_pcib_softc *sc = device_get_softc(dev); 518 u_int devfn; 519 520 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 521 return (~0); 522 devfn = DEVFN(bus, slot, func); 523 if (devfn == sc->sc_devfn_tundra) 524 return (~0); 525 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN) 526 return (1); 527 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 528} 529 530static void 531fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 532 u_int reg, uint32_t val, int bytes) 533{ 534 struct fsl_pcib_softc *sc = device_get_softc(dev); 535 536 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 537 return; 538 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 539} 540 541static void 542fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus, 543 int slot, int fn) 544{ 545 546 if (device == 0x0686) { 547 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1); 548 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1); 549 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1); 550 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1); 551 } else if (device == 0x0571) { 552 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn); 553 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1); 554 } 555} 556 557static int 558fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot) 559{ 560 int secbus; 561 int old_pribus, old_secbus, old_subbus; 562 int new_pribus, new_secbus, new_subbus; 563 int slot, func, maxfunc; 564 uint16_t vendor, device; 565 uint8_t command, hdrtype, subclass; 566 567 secbus = bus; 568 for (slot = 0; slot <= maxslot; slot++) { 569 maxfunc = 0; 570 for (func = 0; func <= maxfunc; func++) { 571 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot, 572 func, PCIR_HDRTYPE, 1); 573 574 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 575 continue; 576 577 if (func == 0 && (hdrtype & PCIM_MFDEV)) 578 maxfunc = PCI_FUNCMAX; 579 580 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot, 581 func, PCIR_VENDOR, 2); 582 device = fsl_pcib_read_config(sc->sc_dev, bus, slot, 583 func, PCIR_DEVICE, 2); 584 585 if (vendor == 0x1957 && device == 0x3fff) { 586 sc->sc_devfn_tundra = DEVFN(bus, slot, func); 587 continue; 588 } 589 590 command = fsl_pcib_read_config(sc->sc_dev, bus, slot, 591 func, PCIR_COMMAND, 1); 592 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 593 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 594 PCIR_COMMAND, command, 1); 595 596 if (vendor == 0x1106) 597 fsl_pcib_init_via(sc, device, bus, slot, func); 598 599 /* 600 * Handle PCI-PCI bridges 601 */ 602 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot, 603 func, PCIR_SUBCLASS, 1); 604 605 /* Allow all DEVTYPE 1 devices */ 606 if (hdrtype != PCIM_HDRTYPE_BRIDGE) 607 continue; 608 609 secbus++; 610 611 /* Read currect bus register configuration */ 612 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus, 613 slot, func, PCIR_PRIBUS_1, 1); 614 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus, 615 slot, func, PCIR_SECBUS_1, 1); 616 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus, 617 slot, func, PCIR_SUBBUS_1, 1); 618 619 if (bootverbose) 620 printf("PCI: reading firmware bus numbers for " 621 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n", 622 secbus, old_pribus, old_secbus, old_subbus); 623 624 new_pribus = bus; 625 new_secbus = secbus; 626 627 secbus = fsl_pcib_init(sc, secbus, 628 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0); 629 630 new_subbus = secbus; 631 632 if (bootverbose) 633 printf("PCI: translate firmware bus numbers " 634 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n", 635 secbus, old_pribus, old_secbus, old_subbus, 636 new_pribus, new_secbus, new_subbus); 637 638 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 639 PCIR_PRIBUS_1, new_pribus, 1); 640 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 641 PCIR_SECBUS_1, new_secbus, 1); 642 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 643 PCIR_SUBBUS_1, new_subbus, 1); 644 } 645 } 646 647 return (secbus); 648} 649 650static void 651fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 652 uint64_t size, uint64_t pci_start) 653{ 654 uint32_t attr, bar, tar; 655 656 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 657 658 switch (tgt) { 659 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */ 660 case OCP85XX_TGTIF_RAM1_85XX: 661 case OCP85XX_TGTIF_RAM1_QORIQ: 662 attr = 0xa0f55000 | (ffsl(size) - 2); 663 break; 664 default: 665 attr = 0; 666 break; 667 } 668 tar = start >> 12; 669 bar = pci_start >> 12; 670 671 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 672 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 673 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 674 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 675} 676 677static void 678fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 679 uint64_t size, uint64_t pci_start) 680{ 681 uint32_t attr, bar, tar; 682 683 switch (res) { 684 case SYS_RES_MEMORY: 685 attr = 0x80044000 | (ffsll(size) - 2); 686 break; 687 case SYS_RES_IOPORT: 688 attr = 0x80088000 | (ffsll(size) - 2); 689 break; 690 default: 691 attr = 0x0004401f; 692 break; 693 } 694 bar = start >> 12; 695 tar = pci_start >> 12; 696 697 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 698 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 699 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 700 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 701} 702 703 704static void 705fsl_pcib_err_init(device_t dev) 706{ 707 struct fsl_pcib_softc *sc; 708 uint16_t sec_stat, dsr; 709 uint32_t dcr, err_en; 710 711 sc = device_get_softc(dev); 712 713 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 714 if (sec_stat) 715 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 716 if (sc->sc_pcie) { 717 /* Clear error bits */ 718 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 719 0xffffffff); 720 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 721 0xffffffff); 722 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 723 0xffffffff); 724 725 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 726 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 727 if (dsr) 728 fsl_pcib_cfgwrite(sc, 0, 0, 0, 729 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 730 0xffff, 2); 731 732 /* Enable all errors reporting */ 733 err_en = 0x00bfff00; 734 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 735 err_en); 736 737 /* Enable error reporting: URR, FER, NFER */ 738 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 739 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 740 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 741 PCIEM_CTL_NFER_ENABLE; 742 fsl_pcib_cfgwrite(sc, 0, 0, 0, 743 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 744 } 745} 746 747static int 748fsl_pcib_detach(device_t dev) 749{ 750 751 if (mtx_initialized) { 752 mtx_destroy(&pcicfg_mtx); 753 mtx_initialized = 0; 754 } 755 return (bus_generic_detach(dev)); 756} 757 758static int 759fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 760{ 761 device_t dev; 762 int error, i, trgt; 763 764 dev = sc->sc_dev; 765 766 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 767 768 /* 769 * Configure LAW decode windows. 770 */ 771 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 772 &sc->sc_ioport_target); 773 if (error != 0) { 774 device_printf(dev, "could not retrieve PCI LAW target info\n"); 775 return (error); 776 } 777 778 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 779 switch (sc->pci_sc.sc_range[i].pci_hi & 780 OFW_PCI_PHYS_HI_SPACEMASK) { 781 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 782 continue; 783 case OFW_PCI_PHYS_HI_SPACE_IO: 784 trgt = sc->sc_ioport_target; 785 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 786 sc->pci_sc.sc_range[i].host, 787 sc->pci_sc.sc_range[i].size, 788 sc->pci_sc.sc_range[i].pci); 789 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 790 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 791 sc->pci_sc.sc_range[i].size - 1; 792 break; 793 case OFW_PCI_PHYS_HI_SPACE_MEM32: 794 case OFW_PCI_PHYS_HI_SPACE_MEM64: 795 trgt = sc->sc_iomem_target; 796 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 797 sc->pci_sc.sc_range[i].host, 798 sc->pci_sc.sc_range[i].size, 799 sc->pci_sc.sc_range[i].pci); 800 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 801 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 802 sc->pci_sc.sc_range[i].size - 1; 803 break; 804 default: 805 panic("Unknown range type %#x\n", 806 sc->pci_sc.sc_range[i].pci_hi & 807 OFW_PCI_PHYS_HI_SPACEMASK); 808 } 809 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 810 sc->pci_sc.sc_range[i].size); 811 if (error != 0) { 812 device_printf(dev, "could not program LAW for range " 813 "%d\n", i); 814 return (error); 815 } 816 } 817 818 /* 819 * Set outbout and inbound windows. 820 */ 821 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 822 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 823 824 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 825 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 826 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 827 2U * 1024U * 1024U * 1024U, 0); 828 829 return (0); 830} 831