dbdma.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Nathan Whitehorn 5 * All rights reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/11/sys/powerpc/include/dbdma.h 330897 2018-03-14 03:19:51Z eadler $ 29 */ 30 31#ifndef _MACHINE_DBDMA_H_ 32#define _MACHINE_DBDMA_H_ 33 34#include <sys/param.h> 35#include <machine/bus.h> 36 37/* 38 * Apple's DBDMA (Descriptor-based DMA) interface is a common DMA engine 39 * used by a variety of custom Apple ASICs. It is described in the CHRP 40 * specification and in the book Macintosh Technology in the Common 41 * Hardware Reference Platform, copyright 1995 Apple Computer. 42 */ 43 44/* DBDMA Command Values */ 45 46enum { 47 DBDMA_OUTPUT_MORE = 0, 48 DBDMA_OUTPUT_LAST = 1, 49 DBDMA_INPUT_MORE = 2, 50 DBDMA_INPUT_LAST = 3, 51 52 DBDMA_STORE_QUAD = 4, 53 DBDMA_LOAD_QUAD = 5, 54 DBDMA_NOP = 6, 55 DBDMA_STOP = 7 56}; 57 58/* These codes are for the interrupt, branch, and wait flags */ 59 60enum { 61 DBDMA_NEVER = 0, 62 DBDMA_COND_TRUE = 1, 63 DBDMA_COND_FALSE = 2, 64 DBDMA_ALWAYS = 3 65}; 66 67/* Channel status bits */ 68#define DBDMA_STATUS_RUN (0x01 << 15) 69#define DBDMA_STATUS_PAUSE (0x01 << 14) 70#define DBDMA_STATUS_FLUSH (0x01 << 13) 71#define DBDMA_STATUS_WAKE (0x01 << 12) 72#define DBDMA_STATUS_DEAD (0x01 << 11) 73#define DBDMA_STATUS_ACTIVE (0x01 << 10) 74 75/* Set by hardware if a branch was taken */ 76#define DBDMA_STATUS_BRANCH 8 77 78struct dbdma_command; 79typedef struct dbdma_command dbdma_command_t; 80struct dbdma_channel; 81typedef struct dbdma_channel dbdma_channel_t; 82 83int dbdma_allocate_channel(struct resource *dbdma_regs, u_int offset, 84 bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan); 85 86int dbdma_resize_channel(dbdma_channel_t *chan, int newslots); 87int dbdma_free_channel(dbdma_channel_t *chan); 88 89void dbdma_run(dbdma_channel_t *chan); 90void dbdma_stop(dbdma_channel_t *chan); 91void dbdma_reset(dbdma_channel_t *chan); 92void dbdma_set_current_cmd(dbdma_channel_t *chan, int slot); 93 94void dbdma_pause(dbdma_channel_t *chan); 95void dbdma_wake(dbdma_channel_t *chan); 96 97/* 98 * DBDMA uses a 16 bit channel control register to describe the current 99 * state of DMA on the channel. The high-order bits (8-15) contain information 100 * on the run state and are listed in the DBDMA_STATUS_* constants above. These 101 * are manipulated with the dbdma_run/stop/reset() routines above. 102 * 103 * The low order bits (0-7) are device dependent status bits. These can be set 104 * and read by both hardware and software. The mask is the set of bits to 105 * modify; if mask is 0x03 and value is 0, the lowest order 2 bits will be 106 * zeroed. 107 */ 108 109uint16_t dbdma_get_chan_status(dbdma_channel_t *chan); 110 111uint8_t dbdma_get_device_status(dbdma_channel_t *chan); 112void dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, 113 uint8_t value); 114 115/* 116 * Each DBDMA command word has the current channel status register and the 117 * number of residual bytes (requested - actually transferred) written to it 118 * at time of command completion. 119 */ 120 121uint16_t dbdma_get_cmd_status(dbdma_channel_t *chan, int slot); 122uint16_t dbdma_get_residuals(dbdma_channel_t *chan, int slot); 123 124void dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot); 125 126/* 127 * The interrupt/branch/wait selector let you specify a set of values 128 * of the device dependent status bits that will cause intterupt/branch/wait 129 * conditions to be taken if the flags for these are set to one of the 130 * DBDMA_COND_* values. 131 * 132 * The condition is considered true if (status & mask) == value. 133 */ 134 135void dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, 136 uint8_t value); 137void dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, 138 uint8_t value); 139void dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, 140 uint8_t value); 141 142void dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, 143 int stream, bus_addr_t data, size_t count, uint8_t interrupt, 144 uint8_t branch, uint8_t wait, uint32_t branch_slot); 145 146void dbdma_insert_stop(dbdma_channel_t *chan, int slot); 147void dbdma_insert_nop(dbdma_channel_t *chan, int slot); 148void dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot); 149 150void dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op); 151 152void dbdma_save_state(dbdma_channel_t *chan); 153void dbdma_restore_state(dbdma_channel_t *chan); 154 155#endif /* _MACHINE_DBDMA_H_ */ 156