gtreg.h revision 330897
1/* $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $ */ 2 3/*- 4 * SPDX-License-Identifier: BSD-2-Clause-NetBSD 5 * 6 * Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 11 * NASA Ames Research Center. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: stable/11/sys/mips/malta/gtreg.h 330897 2018-03-14 03:19:51Z eadler $ 35 */ 36 37 38 39#define GT_REGVAL(x) *((volatile u_int32_t *) \ 40 (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x)))) 41 42/* CPU Configuration Register Map */ 43#define GT_CPU_INT 0x000 44#define GT_MULTIGT 0x120 45 46/* CPU Address Decode Register Map */ 47 48/* CPU Error Report Register Map */ 49 50/* CPU Sync Barrier Register Map */ 51 52/* SDRAM and Device Address Decode Register Map */ 53 54/* SDRAM Configuration Register Map */ 55 56/* SDRAM Parameters Register Map */ 57 58/* ECC Register Map */ 59 60/* Device Parameters Register Map */ 61 62/* DMA Record Register Map */ 63 64/* DMA Arbiter Register Map */ 65 66/* Timer/Counter Register Map */ 67//#define GT_TC_0 0x850 68//#define GT_TC_1 0x854 69//#define GT_TC_2 0x858 70//#define GT_TC_3 0x85c 71//#define GT_TC_CONTROL 0x864 72 73/* PCI Internal Register Map */ 74#define GT_PCI0_CFG_ADDR 0xcf8 75#define GT_PCI0_CFG_DATA 0xcfc 76#define GT_PCI0_INTR_ACK 0xc34 77 78/* Interrupts Register Map */ 79#define GT_INTR_CAUSE 0xc18 80#define GTIC_INTSUM 0x00000001 81#define GTIC_MEMOUT 0x00000002 82#define GTIC_DMAOUT 0x00000004 83#define GTIC_CPUOUT 0x00000008 84#define GTIC_DMA0COMP 0x00000010 85#define GTIC_DMA1COMP 0x00000020 86#define GTIC_DMA2COMP 0x00000040 87#define GTIC_DMA3COMP 0x00000080 88#define GTIC_T0EXP 0x00000100 89#define GTIC_T1EXP 0x00000200 90#define GTIC_T2EXP 0x00000400 91#define GTIC_T3EXP 0x00000800 92#define GTIC_MASRDERR0 0x00001000 93#define GTIC_SLVWRERR0 0x00002000 94#define GTIC_MASWRERR0 0x00004000 95#define GTIC_SLVRDERR0 0x00008000 96#define GTIC_ADDRERR0 0x00010000 97#define GTIC_MEMERR 0x00020000 98#define GTIC_MASABORT0 0x00040000 99#define GTIC_TARABORT0 0x00080000 100#define GTIC_RETRYCNT0 0x00100000 101#define GTIC_PMCINT_0 0x00200000 102#define GTIC_CPUINT 0x0c300000 103#define GTIC_PCINT 0xc3000000 104#define GTIC_CPUINTSUM 0x40000000 105#define GTIC_PCIINTSUM 0x80000000 106 107/* PCI Configuration Register Map */ 108//#define GT_PCICONFIGBASE 0 109//#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00) 110//#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04) 111//#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08) 112//#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c) 113//#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10) 114//#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14) 115//#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18) 116//#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30) 117//#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c) 118 119/* PCI Configuration, Function 1, Register Map */ 120 121/* I2O Support Register Map */ 122