uart_cpu_octeonusart.c revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009 M. Warner Losh <imp@FreeBSD.org>
5 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $Id$
30 */
31#include "opt_uart.h"
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: stable/11/sys/mips/cavium/uart_cpu_octeonusart.c 330897 2018-03-14 03:19:51Z eadler $");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39#include <sys/cons.h>
40
41#include <machine/bus.h>
42
43#include <dev/uart/uart.h>
44#include <dev/uart/uart_cpu.h>
45
46#include <mips/cavium/octeon_pcmap_regs.h>
47
48#include <contrib/octeon-sdk/cvmx.h>
49
50bus_space_tag_t uart_bus_space_io;
51bus_space_tag_t uart_bus_space_mem;
52
53/*
54 * Specailized uart bus space.  We present a 1 apart byte oriented
55 * bus to the outside world, but internally translate to/from the 8-apart
56 * 64-bit word bus that's on the octeon.  We only support simple read/write
57 * in this space.  Everything else is undefined.
58 */
59static uint8_t
60ou_bs_r_1(void *t, bus_space_handle_t handle, bus_size_t offset)
61{
62
63	return (cvmx_read64_uint64(handle + offset));
64}
65
66static uint16_t
67ou_bs_r_2(void *t, bus_space_handle_t handle, bus_size_t offset)
68{
69
70	return (cvmx_read64_uint64(handle + offset));
71}
72
73static uint32_t
74ou_bs_r_4(void *t, bus_space_handle_t handle, bus_size_t offset)
75{
76
77	return (cvmx_read64_uint64(handle + offset));
78}
79
80static uint64_t
81ou_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset)
82{
83
84	return (cvmx_read64_uint64(handle + offset));
85}
86
87static void
88ou_bs_w_1(void *t, bus_space_handle_t bsh, bus_size_t offset, uint8_t value)
89{
90
91	cvmx_write64_uint64(bsh + offset, value);
92}
93
94static void
95ou_bs_w_2(void *t, bus_space_handle_t bsh, bus_size_t offset, uint16_t value)
96{
97
98	cvmx_write64_uint64(bsh + offset, value);
99}
100
101static void
102ou_bs_w_4(void *t, bus_space_handle_t bsh, bus_size_t offset, uint32_t value)
103{
104
105	cvmx_write64_uint64(bsh + offset, value);
106}
107
108static void
109ou_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset, uint64_t value)
110{
111
112	cvmx_write64_uint64(bsh + offset, value);
113}
114
115struct bus_space octeon_uart_tag = {
116	.bs_map = generic_bs_map,
117	.bs_unmap = generic_bs_unmap,
118	.bs_subregion = generic_bs_subregion,
119	.bs_barrier = generic_bs_barrier,
120	.bs_r_1 = ou_bs_r_1,
121	.bs_r_2 = ou_bs_r_2,
122	.bs_r_4 = ou_bs_r_4,
123	.bs_r_8 = ou_bs_r_8,
124	.bs_w_1 = ou_bs_w_1,
125	.bs_w_2 = ou_bs_w_2,
126	.bs_w_4 = ou_bs_w_4,
127	.bs_w_8 = ou_bs_w_8,
128};
129
130extern struct uart_class uart_oct16550_class;
131
132int
133uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
134{
135
136	return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
137}
138
139int
140uart_cpu_getdev(int devtype, struct uart_devinfo *di)
141{
142	struct uart_class *class = &uart_oct16550_class;
143
144	/*
145	 * These fields need to be setup corretly for uart_getenv to
146	 * work in all cases.
147	 */
148	uart_bus_space_io = NULL;		/* No io map for this device */
149	uart_bus_space_mem = &octeon_uart_tag;
150	di->bas.bst = uart_bus_space_mem;
151
152	/*
153	 * If env specification for UART exists it takes precedence:
154	 * hw.uart.console="mm:0xf1012000" or similar
155	 */
156	if (uart_getenv(devtype, di, class) == 0)
157		return (0);
158
159	/*
160	 * Fallback to UART0 for console.
161	 */
162	di->ops = uart_getops(class);
163	di->bas.chan = 0;
164	/* XXX */
165	if (bus_space_map(di->bas.bst, CVMX_MIO_UARTX_RBR(0),
166	    uart_getrange(class), 0, &di->bas.bsh) != 0)
167		return (ENXIO);
168	di->bas.regshft = 3;
169	di->bas.rclk = 0;
170	di->baudrate = 115200;
171	di->databits = 8;
172	di->stopbits = 1;
173	di->parity = UART_PARITY_NONE;
174
175	return (0);
176}
177