dwc_otg.c revision 330897
1/* $FreeBSD: stable/11/sys/dev/usb/controller/dwc_otg.c 330897 2018-03-14 03:19:51Z eadler $ */ 2/*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. 6 * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved. 7 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/* 32 * This file contains the driver for the DesignWare series USB 2.0 OTG 33 * Controller. 34 */ 35 36/* 37 * LIMITATION: Drivers must be bound to all OUT endpoints in the 38 * active configuration for this driver to work properly. Blocking any 39 * OUT endpoint will block all OUT endpoints including the control 40 * endpoint. Usually this is not a problem. 41 */ 42 43/* 44 * NOTE: Writing to non-existing registers appears to cause an 45 * internal reset. 46 */ 47 48#ifdef USB_GLOBAL_INCLUDE_FILE 49#include USB_GLOBAL_INCLUDE_FILE 50#else 51#include <sys/stdint.h> 52#include <sys/stddef.h> 53#include <sys/param.h> 54#include <sys/queue.h> 55#include <sys/types.h> 56#include <sys/systm.h> 57#include <sys/kernel.h> 58#include <sys/bus.h> 59#include <sys/module.h> 60#include <sys/lock.h> 61#include <sys/mutex.h> 62#include <sys/condvar.h> 63#include <sys/sysctl.h> 64#include <sys/sx.h> 65#include <sys/unistd.h> 66#include <sys/callout.h> 67#include <sys/malloc.h> 68#include <sys/priv.h> 69 70#include <dev/usb/usb.h> 71#include <dev/usb/usbdi.h> 72 73#define USB_DEBUG_VAR dwc_otg_debug 74 75#include <dev/usb/usb_core.h> 76#include <dev/usb/usb_debug.h> 77#include <dev/usb/usb_busdma.h> 78#include <dev/usb/usb_process.h> 79#include <dev/usb/usb_transfer.h> 80#include <dev/usb/usb_device.h> 81#include <dev/usb/usb_hub.h> 82#include <dev/usb/usb_util.h> 83 84#include <dev/usb/usb_controller.h> 85#include <dev/usb/usb_bus.h> 86#endif /* USB_GLOBAL_INCLUDE_FILE */ 87 88#include <dev/usb/controller/dwc_otg.h> 89#include <dev/usb/controller/dwc_otgreg.h> 90 91#define DWC_OTG_BUS2SC(bus) \ 92 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 93 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 94 95#define DWC_OTG_PC2UDEV(pc) \ 96 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 97 98#define DWC_OTG_MSK_GINT_THREAD_IRQ \ 99 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 100 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 101 GINTSTS_SESSREQINT) 102 103#define DWC_OTG_PHY_ULPI 0 104#define DWC_OTG_PHY_HSIC 1 105#define DWC_OTG_PHY_INTERNAL 2 106 107#ifndef DWC_OTG_PHY_DEFAULT 108#define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 109#endif 110 111static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 112 113static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 114SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 115 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL"); 116 117#ifdef USB_DEBUG 118static int dwc_otg_debug; 119 120SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 121 &dwc_otg_debug, 0, "DWC OTG debug level"); 122#endif 123 124#define DWC_OTG_INTR_ENDPT 1 125 126/* prototypes */ 127 128static const struct usb_bus_methods dwc_otg_bus_methods; 129static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 130static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 131 132static dwc_otg_cmd_t dwc_otg_setup_rx; 133static dwc_otg_cmd_t dwc_otg_data_rx; 134static dwc_otg_cmd_t dwc_otg_data_tx; 135static dwc_otg_cmd_t dwc_otg_data_tx_sync; 136 137static dwc_otg_cmd_t dwc_otg_host_setup_tx; 138static dwc_otg_cmd_t dwc_otg_host_data_tx; 139static dwc_otg_cmd_t dwc_otg_host_data_rx; 140 141static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 142static void dwc_otg_do_poll(struct usb_bus *); 143static void dwc_otg_standard_done(struct usb_xfer *); 144static void dwc_otg_root_intr(struct dwc_otg_softc *); 145static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 146 147/* 148 * Here is a configuration that the chip supports. 149 */ 150static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 151 152 [0] = { 153 .max_in_frame_size = 64,/* fixed */ 154 .max_out_frame_size = 64, /* fixed */ 155 .is_simplex = 1, 156 .support_control = 1, 157 } 158}; 159 160static void 161dwc_otg_get_hw_ep_profile(struct usb_device *udev, 162 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 163{ 164 struct dwc_otg_softc *sc; 165 166 sc = DWC_OTG_BUS2SC(udev->bus); 167 168 if (ep_addr < sc->sc_dev_ep_max) 169 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 170 else 171 *ppf = NULL; 172} 173 174static void 175dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 176 uint32_t offset, uint32_t fifo, uint32_t count) 177{ 178 uint32_t temp; 179 180 /* round down length to nearest 4-bytes */ 181 temp = count & ~3; 182 183 /* check if we can write the data directly */ 184 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 185 struct usb_page_search buf_res; 186 187 /* pre-subtract length */ 188 count -= temp; 189 190 /* iterate buffer list */ 191 do { 192 /* get current buffer pointer */ 193 usbd_get_page(pc, offset, &buf_res); 194 195 if (buf_res.length > temp) 196 buf_res.length = temp; 197 198 /* transfer data into FIFO */ 199 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 200 fifo, buf_res.buffer, buf_res.length / 4); 201 202 offset += buf_res.length; 203 fifo += buf_res.length; 204 temp -= buf_res.length; 205 } while (temp != 0); 206 } 207 208 /* check for remainder */ 209 if (count != 0) { 210 /* clear topmost word before copy */ 211 sc->sc_bounce_buffer[(count - 1) / 4] = 0; 212 213 /* copy out data */ 214 usbd_copy_out(pc, offset, 215 sc->sc_bounce_buffer, count); 216 217 /* transfer data into FIFO */ 218 bus_space_write_region_4(sc->sc_io_tag, 219 sc->sc_io_hdl, fifo, sc->sc_bounce_buffer, 220 (count + 3) / 4); 221 } 222} 223 224static void 225dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 226 uint32_t offset, uint32_t count) 227{ 228 uint32_t temp; 229 230 /* round down length to nearest 4-bytes */ 231 temp = count & ~3; 232 233 /* check if we can read the data directly */ 234 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 235 struct usb_page_search buf_res; 236 237 /* pre-subtract length */ 238 count -= temp; 239 240 /* iterate buffer list */ 241 do { 242 /* get current buffer pointer */ 243 usbd_get_page(pc, offset, &buf_res); 244 245 if (buf_res.length > temp) 246 buf_res.length = temp; 247 248 /* transfer data from FIFO */ 249 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 250 sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4); 251 252 offset += buf_res.length; 253 sc->sc_current_rx_fifo += buf_res.length; 254 sc->sc_current_rx_bytes -= buf_res.length; 255 temp -= buf_res.length; 256 } while (temp != 0); 257 } 258 259 /* check for remainder */ 260 if (count != 0) { 261 /* read data into bounce buffer */ 262 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 263 sc->sc_current_rx_fifo, 264 sc->sc_bounce_buffer, (count + 3) / 4); 265 266 /* store data into proper buffer */ 267 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count); 268 269 /* round length up to nearest 4 bytes */ 270 count = (count + 3) & ~3; 271 272 /* update counters */ 273 sc->sc_current_rx_bytes -= count; 274 sc->sc_current_rx_fifo += count; 275 } 276} 277 278static void 279dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) 280{ 281 uint32_t temp; 282 283 /* reset FIFO */ 284 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); 285 286 /* wait for reset to complete */ 287 for (temp = 0; temp != 16; temp++) { 288 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); 289 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) 290 break; 291 } 292} 293 294static int 295dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 296{ 297 struct dwc_otg_profile *pf; 298 uint32_t fifo_size; 299 uint32_t fifo_regs; 300 uint32_t tx_start; 301 uint8_t x; 302 303 fifo_size = sc->sc_fifo_size; 304 305 /* 306 * NOTE: Reserved fixed size area at end of RAM, which must 307 * not be allocated to the FIFOs: 308 */ 309 fifo_regs = 4 * 16; 310 311 if (fifo_size < fifo_regs) { 312 DPRINTF("Too little FIFO\n"); 313 return (EINVAL); 314 } 315 316 /* subtract FIFO regs from total once */ 317 fifo_size -= fifo_regs; 318 319 /* split equally for IN and OUT */ 320 fifo_size /= 2; 321 322 /* Align to 4 bytes boundary (refer to PGM) */ 323 fifo_size &= ~3; 324 325 /* set global receive FIFO size */ 326 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 327 328 tx_start = fifo_size; 329 330 if (fifo_size < 64) { 331 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 332 return (EINVAL); 333 } 334 335 if (mode == DWC_MODE_HOST) { 336 337 /* reset active endpoints */ 338 sc->sc_active_rx_ep = 0; 339 340 /* split equally for periodic and non-periodic */ 341 fifo_size /= 2; 342 343 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); 344 345 /* align to 4 bytes boundary */ 346 fifo_size &= ~3; 347 348 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 349 ((fifo_size / 4) << 16) | 350 (tx_start / 4)); 351 352 tx_start += fifo_size; 353 354 for (x = 0; x != sc->sc_host_ch_max; x++) { 355 /* enable all host interrupts */ 356 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 357 HCINT_DEFAULT_MASK); 358 } 359 360 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 361 ((fifo_size / 4) << 16) | 362 (tx_start / 4)); 363 364 /* reset host channel state */ 365 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 366 367 /* enable all host channel interrupts */ 368 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 369 (1U << sc->sc_host_ch_max) - 1U); 370 371 /* enable proper host channel interrupts */ 372 sc->sc_irq_mask |= GINTMSK_HCHINTMSK; 373 sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK; 374 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 375 } 376 377 if (mode == DWC_MODE_DEVICE) { 378 379 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 380 (0x10 << 16) | (tx_start / 4)); 381 fifo_size -= 0x40; 382 tx_start += 0x40; 383 384 /* setup control endpoint profile */ 385 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 386 387 /* reset active endpoints */ 388 sc->sc_active_rx_ep = 1; 389 390 for (x = 1; x != sc->sc_dev_ep_max; x++) { 391 392 pf = sc->sc_hw_ep_profile + x; 393 394 pf->usb.max_out_frame_size = 1024 * 3; 395 pf->usb.is_simplex = 0; /* assume duplex */ 396 pf->usb.support_bulk = 1; 397 pf->usb.support_interrupt = 1; 398 pf->usb.support_isochronous = 1; 399 pf->usb.support_out = 1; 400 401 if (x < sc->sc_dev_in_ep_max) { 402 uint32_t limit; 403 404 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 405 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 406 DWC_OTG_TX_MAX_FIFO_SIZE); 407 408 /* see if there is enough FIFO space */ 409 if (limit <= fifo_size) { 410 pf->max_buffer = limit; 411 pf->usb.support_in = 1; 412 } else { 413 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 414 if (limit <= fifo_size) { 415 pf->usb.support_in = 1; 416 } else { 417 pf->usb.is_simplex = 1; 418 limit = 0; 419 } 420 } 421 /* set FIFO size */ 422 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 423 ((limit / 4) << 16) | (tx_start / 4)); 424 tx_start += limit; 425 fifo_size -= limit; 426 pf->usb.max_in_frame_size = limit; 427 } else { 428 pf->usb.is_simplex = 1; 429 } 430 431 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 432 pf->usb.max_in_frame_size, 433 pf->usb.max_out_frame_size); 434 } 435 436 /* enable proper device channel interrupts */ 437 sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK; 438 sc->sc_irq_mask |= GINTMSK_IEPINTMSK; 439 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 440 } 441 442 /* reset RX FIFO */ 443 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); 444 445 if (mode != DWC_MODE_OTG) { 446 /* reset all TX FIFOs */ 447 dwc_otg_tx_fifo_reset(sc, 448 GRSTCTL_TXFIFO(0x10) | 449 GRSTCTL_TXFFLSH); 450 } else { 451 /* reset active endpoints */ 452 sc->sc_active_rx_ep = 0; 453 454 /* reset host channel state */ 455 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 456 } 457 return (0); 458} 459 460static uint8_t 461dwc_otg_uses_split(struct usb_device *udev) 462{ 463 /* 464 * When a LOW or FULL speed device is connected directly to 465 * the USB port we don't use split transactions: 466 */ 467 return (udev->speed != USB_SPEED_HIGH && 468 udev->parent_hs_hub != NULL && 469 udev->parent_hs_hub->parent_hub != NULL); 470} 471 472static void 473dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 474{ 475 476 /* 477 * Disabled until further. Assuming that the register is already 478 * programmed correctly by the boot loader. 479 */ 480#if 0 481 uint32_t temp; 482 483 /* setup HOST frame interval register, based on existing value */ 484 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 485 if (temp >= 10000) 486 temp /= 1000; 487 else 488 temp /= 125; 489 490 /* figure out nearest X-tal value */ 491 if (temp >= 54) 492 temp = 60; /* MHz */ 493 else if (temp >= 39) 494 temp = 48; /* MHz */ 495 else 496 temp = 30; /* MHz */ 497 498 if (sc->sc_flags.status_high_speed) 499 temp *= 125; 500 else 501 temp *= 1000; 502 503 DPRINTF("HFIR=0x%08x\n", temp); 504 505 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 506#endif 507} 508 509static void 510dwc_otg_clocks_on(struct dwc_otg_softc *sc) 511{ 512 if (sc->sc_flags.clocks_off && 513 sc->sc_flags.port_powered) { 514 515 DPRINTFN(5, "\n"); 516 517 /* TODO - platform specific */ 518 519 sc->sc_flags.clocks_off = 0; 520 } 521} 522 523static void 524dwc_otg_clocks_off(struct dwc_otg_softc *sc) 525{ 526 if (!sc->sc_flags.clocks_off) { 527 528 DPRINTFN(5, "\n"); 529 530 /* TODO - platform specific */ 531 532 sc->sc_flags.clocks_off = 1; 533 } 534} 535 536static void 537dwc_otg_pull_up(struct dwc_otg_softc *sc) 538{ 539 uint32_t temp; 540 541 /* pullup D+, if possible */ 542 543 if (!sc->sc_flags.d_pulled_up && 544 sc->sc_flags.port_powered) { 545 sc->sc_flags.d_pulled_up = 1; 546 547 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 548 temp &= ~DCTL_SFTDISCON; 549 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 550 } 551} 552 553static void 554dwc_otg_pull_down(struct dwc_otg_softc *sc) 555{ 556 uint32_t temp; 557 558 /* pulldown D+, if possible */ 559 560 if (sc->sc_flags.d_pulled_up) { 561 sc->sc_flags.d_pulled_up = 0; 562 563 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 564 temp |= DCTL_SFTDISCON; 565 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 566 } 567} 568 569static void 570dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 571{ 572 /* In device mode we don't use the SOF interrupt */ 573 if (sc->sc_flags.status_device_mode != 0) 574 return; 575 /* Ensure the SOF interrupt is not disabled */ 576 sc->sc_needsof = 1; 577 /* Check if the SOF interrupt is already enabled */ 578 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 579 return; 580 sc->sc_irq_mask |= GINTMSK_SOFMSK; 581 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 582} 583 584static void 585dwc_otg_resume_irq(struct dwc_otg_softc *sc) 586{ 587 if (sc->sc_flags.status_suspend) { 588 /* update status bits */ 589 sc->sc_flags.status_suspend = 0; 590 sc->sc_flags.change_suspend = 1; 591 592 if (sc->sc_flags.status_device_mode) { 593 /* 594 * Disable resume interrupt and enable suspend 595 * interrupt: 596 */ 597 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 598 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 599 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 600 } 601 602 /* complete root HUB interrupt endpoint */ 603 dwc_otg_root_intr(sc); 604 } 605} 606 607static void 608dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 609{ 610 if (!sc->sc_flags.status_suspend) { 611 /* update status bits */ 612 sc->sc_flags.status_suspend = 1; 613 sc->sc_flags.change_suspend = 1; 614 615 if (sc->sc_flags.status_device_mode) { 616 /* 617 * Disable suspend interrupt and enable resume 618 * interrupt: 619 */ 620 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 621 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 622 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 623 } 624 625 /* complete root HUB interrupt endpoint */ 626 dwc_otg_root_intr(sc); 627 } 628} 629 630static void 631dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 632{ 633 if (!sc->sc_flags.status_suspend) 634 return; 635 636 DPRINTFN(5, "Remote wakeup\n"); 637 638 if (sc->sc_flags.status_device_mode) { 639 uint32_t temp; 640 641 /* enable remote wakeup signalling */ 642 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 643 temp |= DCTL_RMTWKUPSIG; 644 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 645 646 /* Wait 8ms for remote wakeup to complete. */ 647 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 648 649 temp &= ~DCTL_RMTWKUPSIG; 650 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 651 } else { 652 /* enable USB port */ 653 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 654 655 /* wait 10ms */ 656 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 657 658 /* resume port */ 659 sc->sc_hprt_val |= HPRT_PRTRES; 660 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 661 662 /* Wait 100ms for resume signalling to complete. */ 663 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 664 665 /* clear suspend and resume */ 666 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 667 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 668 669 /* Wait 4ms */ 670 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 671 } 672 673 /* need to fake resume IRQ */ 674 dwc_otg_resume_irq(sc); 675} 676 677static void 678dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 679{ 680 uint32_t temp; 681 682 DPRINTFN(5, "addr=%d\n", addr); 683 684 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 685 temp &= ~DCFG_DEVADDR_SET(0x7F); 686 temp |= DCFG_DEVADDR_SET(addr); 687 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 688} 689 690static void 691dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 692{ 693 DPRINTFN(5, "RX status clear\n"); 694 695 /* enable RX FIFO level interrupt */ 696 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 697 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 698 699 if (sc->sc_current_rx_bytes != 0) { 700 /* need to dump remaining data */ 701 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 702 sc->sc_current_rx_fifo, sc->sc_bounce_buffer, 703 sc->sc_current_rx_bytes / 4); 704 /* clear number of active bytes to receive */ 705 sc->sc_current_rx_bytes = 0; 706 } 707 /* clear cached status */ 708 sc->sc_last_rx_status = 0; 709} 710 711static void 712dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 713{ 714 uint32_t hcint; 715 716 /* clear all pending interrupts */ 717 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 718 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 719 720 /* clear buffered interrupts */ 721 sc->sc_chan_state[x].hcint = 0; 722} 723 724static uint8_t 725dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 726{ 727 uint32_t temp; 728 729 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 730 731 if (td->ep_type == UE_ISOCHRONOUS) { 732 /* 733 * NOTE: USB INTERRUPT transactions are executed like 734 * USB CONTROL transactions! See the setup standard 735 * chain function for more information. 736 */ 737 if (!(temp & GINTSTS_PTXFEMP)) { 738 DPRINTF("Periodic TX FIFO is not empty\n"); 739 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { 740 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; 741 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 742 } 743 return (1); /* busy */ 744 } 745 } else { 746 if (!(temp & GINTSTS_NPTXFEMP)) { 747 DPRINTF("Non-periodic TX FIFO is not empty\n"); 748 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { 749 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; 750 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 751 } 752 return (1); /* busy */ 753 } 754 } 755 return (0); /* ready for transmit */ 756} 757 758static uint8_t 759dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, 760 struct dwc_otg_td *td, uint8_t is_out) 761{ 762 uint8_t x; 763 uint8_t y; 764 uint8_t z; 765 766 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) 767 return (0); /* already allocated */ 768 769 /* check if device is suspended */ 770 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 771 return (1); /* busy - cannot transfer data */ 772 773 /* compute needed TX FIFO size */ 774 if (is_out != 0) { 775 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0) 776 return (1); /* busy - cannot transfer data */ 777 } 778 z = td->max_packet_count; 779 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 780 /* check if channel is allocated */ 781 if (sc->sc_chan_state[x].allocated != 0) 782 continue; 783 /* check if channel is still enabled */ 784 if (sc->sc_chan_state[x].wait_halted != 0) 785 continue; 786 /* store channel number */ 787 td->channel[y++] = x; 788 /* check if we got all channels */ 789 if (y == z) 790 break; 791 } 792 if (y != z) { 793 /* reset channel variable */ 794 td->channel[0] = DWC_OTG_MAX_CHANNELS; 795 td->channel[1] = DWC_OTG_MAX_CHANNELS; 796 td->channel[2] = DWC_OTG_MAX_CHANNELS; 797 /* wait a bit */ 798 dwc_otg_enable_sof_irq(sc); 799 return (1); /* busy - not enough channels */ 800 } 801 802 for (y = 0; y != z; y++) { 803 x = td->channel[y]; 804 805 /* set allocated */ 806 sc->sc_chan_state[x].allocated = 1; 807 808 /* set wait halted */ 809 sc->sc_chan_state[x].wait_halted = 1; 810 811 /* clear interrupts */ 812 dwc_otg_clear_hcint(sc, x); 813 814 DPRINTF("CH=%d HCCHAR=0x%08x " 815 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 816 817 /* set active channel */ 818 sc->sc_active_rx_ep |= (1 << x); 819 } 820 return (0); /* allocated */ 821} 822 823static void 824dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index) 825{ 826 uint32_t hcchar; 827 uint8_t x; 828 829 if (td->channel[index] >= DWC_OTG_MAX_CHANNELS) 830 return; /* already freed */ 831 832 /* free channel */ 833 x = td->channel[index]; 834 td->channel[index] = DWC_OTG_MAX_CHANNELS; 835 836 DPRINTF("CH=%d\n", x); 837 838 /* 839 * We need to let programmed host channels run till complete 840 * else the host channel will stop functioning. 841 */ 842 sc->sc_chan_state[x].allocated = 0; 843 844 /* ack any pending messages */ 845 if (sc->sc_last_rx_status != 0 && 846 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 847 dwc_otg_common_rx_ack(sc); 848 } 849 850 /* clear active channel */ 851 sc->sc_active_rx_ep &= ~(1 << x); 852 853 /* check if already halted */ 854 if (sc->sc_chan_state[x].wait_halted == 0) 855 return; 856 857 /* disable host channel */ 858 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 859 if (hcchar & HCCHAR_CHENA) { 860 DPRINTF("Halting channel %d\n", x); 861 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 862 hcchar | HCCHAR_CHDIS); 863 /* don't write HCCHAR until the channel is halted */ 864 } else { 865 sc->sc_chan_state[x].wait_halted = 0; 866 } 867} 868 869static void 870dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 871{ 872 uint8_t x; 873 for (x = 0; x != td->max_packet_count; x++) 874 dwc_otg_host_channel_free_sub(sc, td, x); 875} 876 877static void 878dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 879{ 880 uint8_t x; 881 /* dump any pending messages */ 882 if (sc->sc_last_rx_status == 0) 883 return; 884 for (x = 0; x != td->max_packet_count; x++) { 885 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS || 886 td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) 887 continue; 888 dwc_otg_common_rx_ack(sc); 889 break; 890 } 891} 892 893static uint8_t 894dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 895{ 896 struct usb_device_request req __aligned(4); 897 uint32_t hcint; 898 uint32_t hcchar; 899 uint8_t delta; 900 901 dwc_otg_host_dump_rx(sc, td); 902 903 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) { 904 hcint = sc->sc_chan_state[td->channel[0]].hcint; 905 906 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 907 td->channel[0], td->state, hcint, 908 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])), 909 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0]))); 910 } else { 911 hcint = 0; 912 goto check_state; 913 } 914 915 if (hcint & (HCINT_RETRY | 916 HCINT_ACK | HCINT_NYET)) { 917 /* give success bits priority over failure bits */ 918 } else if (hcint & HCINT_STALL) { 919 DPRINTF("CH=%d STALL\n", td->channel[0]); 920 td->error_stall = 1; 921 td->error_any = 1; 922 goto complete; 923 } else if (hcint & HCINT_ERRORS) { 924 DPRINTF("CH=%d ERROR\n", td->channel[0]); 925 td->errcnt++; 926 if (td->hcsplt != 0 || td->errcnt >= 3) { 927 td->error_any = 1; 928 goto complete; 929 } 930 } 931 932 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 933 HCINT_ACK | HCINT_NYET)) { 934 if (!(hcint & HCINT_ERRORS)) 935 td->errcnt = 0; 936 } 937 938check_state: 939 switch (td->state) { 940 case DWC_CHAN_ST_START: 941 goto send_pkt; 942 943 case DWC_CHAN_ST_WAIT_ANE: 944 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 945 td->did_nak = 1; 946 td->tt_scheduled = 0; 947 goto send_pkt; 948 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 949 td->offset += td->tx_bytes; 950 td->remainder -= td->tx_bytes; 951 td->toggle = 1; 952 td->tt_scheduled = 0; 953 goto complete; 954 } 955 break; 956 957 case DWC_CHAN_ST_WAIT_S_ANE: 958 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 959 td->did_nak = 1; 960 td->tt_scheduled = 0; 961 goto send_pkt; 962 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 963 goto send_cpkt; 964 } 965 break; 966 967 case DWC_CHAN_ST_WAIT_C_ANE: 968 if (hcint & HCINT_NYET) { 969 goto send_cpkt; 970 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 971 td->did_nak = 1; 972 td->tt_scheduled = 0; 973 goto send_pkt; 974 } else if (hcint & HCINT_ACK) { 975 td->offset += td->tx_bytes; 976 td->remainder -= td->tx_bytes; 977 td->toggle = 1; 978 goto complete; 979 } 980 break; 981 982 case DWC_CHAN_ST_WAIT_C_PKT: 983 goto send_cpkt; 984 985 default: 986 break; 987 } 988 goto busy; 989 990send_pkt: 991 /* free existing channel, if any */ 992 dwc_otg_host_channel_free(sc, td); 993 994 if (sizeof(req) != td->remainder) { 995 td->error_any = 1; 996 goto complete; 997 } 998 999 if (td->hcsplt != 0) { 1000 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1001 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1002 td->state = DWC_CHAN_ST_START; 1003 goto busy; 1004 } 1005 delta = sc->sc_last_frame_num - td->tt_start_slot; 1006 if (delta > 5) { 1007 /* missed it */ 1008 td->tt_scheduled = 0; 1009 td->state = DWC_CHAN_ST_START; 1010 goto busy; 1011 } 1012 } 1013 1014 /* allocate a new channel */ 1015 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1016 td->state = DWC_CHAN_ST_START; 1017 goto busy; 1018 } 1019 1020 if (td->hcsplt != 0) { 1021 td->hcsplt &= ~HCSPLT_COMPSPLT; 1022 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1023 } else { 1024 td->state = DWC_CHAN_ST_WAIT_ANE; 1025 } 1026 1027 /* copy out control request */ 1028 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1029 1030 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1031 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 1032 (1 << HCTSIZ_PKTCNT_SHIFT) | 1033 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1034 1035 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1036 1037 hcchar = td->hcchar; 1038 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1039 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1040 1041 /* must enable channel before writing data to FIFO */ 1042 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1043 1044 /* transfer data into FIFO */ 1045 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1046 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4); 1047 1048 /* wait until next slot before trying complete split */ 1049 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1050 1051 /* store number of bytes transmitted */ 1052 td->tx_bytes = sizeof(req); 1053 goto busy; 1054 1055send_cpkt: 1056 /* free existing channel, if any */ 1057 dwc_otg_host_channel_free(sc, td); 1058 1059 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1060 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1061 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1062 goto busy; 1063 } 1064 delta = sc->sc_last_frame_num - td->tt_start_slot; 1065 if (delta > DWC_OTG_TT_SLOT_MAX) { 1066 /* we missed the service interval */ 1067 if (td->ep_type != UE_ISOCHRONOUS) 1068 td->error_any = 1; 1069 goto complete; 1070 } 1071 /* allocate a new channel */ 1072 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1073 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1074 goto busy; 1075 } 1076 1077 /* wait until next slot before trying complete split */ 1078 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1079 1080 td->hcsplt |= HCSPLT_COMPSPLT; 1081 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1082 1083 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1084 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1085 1086 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1087 1088 hcchar = td->hcchar; 1089 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1090 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1091 1092 /* must enable channel before writing data to FIFO */ 1093 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1094 1095busy: 1096 return (1); /* busy */ 1097 1098complete: 1099 dwc_otg_host_channel_free(sc, td); 1100 return (0); /* complete */ 1101} 1102 1103static uint8_t 1104dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1105{ 1106 struct usb_device_request req __aligned(4); 1107 uint32_t temp; 1108 uint16_t count; 1109 1110 /* check endpoint status */ 1111 1112 if (sc->sc_last_rx_status == 0) 1113 goto not_complete; 1114 1115 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 1116 goto not_complete; 1117 1118 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1119 GRXSTSRD_STP_DATA) { 1120 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1121 GRXSTSRD_STP_COMPLETE || td->remainder != 0) { 1122 /* release FIFO */ 1123 dwc_otg_common_rx_ack(sc); 1124 goto not_complete; 1125 } 1126 /* release FIFO */ 1127 dwc_otg_common_rx_ack(sc); 1128 return (0); /* complete */ 1129 } 1130 1131 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1132 GRXSTSRD_DPID_DATA0) { 1133 /* release FIFO */ 1134 dwc_otg_common_rx_ack(sc); 1135 goto not_complete; 1136 } 1137 1138 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 1139 1140 /* clear did stall */ 1141 td->did_stall = 0; 1142 1143 /* get the packet byte count */ 1144 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1145 1146 if (count != sizeof(req)) { 1147 DPRINTFN(0, "Unsupported SETUP packet " 1148 "length, %d bytes\n", count); 1149 /* release FIFO */ 1150 dwc_otg_common_rx_ack(sc); 1151 goto not_complete; 1152 } 1153 1154 /* read FIFO */ 1155 dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req)); 1156 1157 /* copy out control request */ 1158 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1159 1160 td->offset = sizeof(req); 1161 td->remainder = 0; 1162 1163 /* sneak peek the set address */ 1164 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1165 (req.bRequest == UR_SET_ADDRESS)) { 1166 /* must write address before ZLP */ 1167 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1168 } 1169 1170 /* don't send any data by default */ 1171 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); 1172 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); 1173 1174 /* reset IN endpoint buffer */ 1175 dwc_otg_tx_fifo_reset(sc, 1176 GRSTCTL_TXFIFO(0) | 1177 GRSTCTL_TXFFLSH); 1178 1179 /* acknowledge RX status */ 1180 dwc_otg_common_rx_ack(sc); 1181 td->did_stall = 1; 1182 1183not_complete: 1184 /* abort any ongoing transfer, before enabling again */ 1185 if (!td->did_stall) { 1186 td->did_stall = 1; 1187 1188 DPRINTFN(5, "stalling IN and OUT direction\n"); 1189 1190 temp = sc->sc_out_ctl[0]; 1191 1192 /* set stall after enabling endpoint */ 1193 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1194 temp | DOEPCTL_STALL); 1195 1196 temp = sc->sc_in_ctl[0]; 1197 1198 /* set stall assuming endpoint is enabled */ 1199 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1200 temp | DIEPCTL_STALL); 1201 } 1202 return (1); /* not complete */ 1203} 1204 1205static uint8_t 1206dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1207{ 1208 uint8_t delta; 1209 1210 delta = sc->sc_tmr_val - td->tmr_val; 1211 if (delta >= 128) 1212 return (1); /* busy */ 1213 1214 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1215 1216 /* set toggle, if any */ 1217 if (td->set_toggle) { 1218 td->set_toggle = 0; 1219 td->toggle = 1; 1220 } 1221 return (0); 1222} 1223 1224static uint8_t 1225dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1226{ 1227 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; 1228 1229 if (td->ep_type == UE_ISOCHRONOUS) { 1230 /* non TT isochronous traffic */ 1231 if (frame_num & (td->tmr_res - 1)) 1232 goto busy; 1233 if ((frame_num ^ td->tmr_val) & td->tmr_res) 1234 goto busy; 1235 td->tmr_val = td->tmr_res + sc->sc_last_frame_num; 1236 td->toggle = 0; 1237 return (0); 1238 } else if (td->ep_type == UE_INTERRUPT) { 1239 if (!td->tt_scheduled) 1240 goto busy; 1241 td->tt_scheduled = 0; 1242 return (0); 1243 } else if (td->did_nak != 0) { 1244 /* check if we should pause sending queries for 125us */ 1245 if (td->tmr_res == frame_num) { 1246 /* wait a bit */ 1247 dwc_otg_enable_sof_irq(sc); 1248 goto busy; 1249 } 1250 } else if (td->set_toggle) { 1251 td->set_toggle = 0; 1252 td->toggle = 1; 1253 } 1254 /* query for data one more time */ 1255 td->tmr_res = frame_num; 1256 td->did_nak = 0; 1257 return (0); 1258busy: 1259 return (1); 1260} 1261 1262static uint8_t 1263dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, 1264 uint8_t channel) 1265{ 1266 uint32_t count; 1267 1268 /* check endpoint status */ 1269 if (sc->sc_last_rx_status == 0) 1270 goto busy; 1271 1272 if (channel >= DWC_OTG_MAX_CHANNELS) 1273 goto busy; 1274 1275 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1276 goto busy; 1277 1278 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1279 case GRXSTSRH_IN_DATA: 1280 1281 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1282 (int)td->state, (int)sc->sc_last_rx_status); 1283 1284 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1285 /* 1286 * When using SPLIT transactions on interrupt 1287 * endpoints, sometimes data occurs twice. 1288 */ 1289 DPRINTF("Data already received\n"); 1290 break; 1291 } 1292 1293 /* get the packet byte count */ 1294 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1295 1296 /* check for ISOCHRONOUS endpoint */ 1297 if (td->ep_type == UE_ISOCHRONOUS) { 1298 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1299 GRXSTSRD_DPID_DATA0) { 1300 /* more data to be received */ 1301 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1302 } else { 1303 /* all data received */ 1304 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1305 /* verify the packet byte count */ 1306 if (count != td->remainder) { 1307 /* we have a short packet */ 1308 td->short_pkt = 1; 1309 td->got_short = 1; 1310 } 1311 } 1312 } else { 1313 /* verify the packet byte count */ 1314 if (count != td->max_packet_size) { 1315 if (count < td->max_packet_size) { 1316 /* we have a short packet */ 1317 td->short_pkt = 1; 1318 td->got_short = 1; 1319 } else { 1320 /* invalid USB packet */ 1321 td->error_any = 1; 1322 1323 /* release FIFO */ 1324 dwc_otg_common_rx_ack(sc); 1325 goto complete; 1326 } 1327 } 1328 td->toggle ^= 1; 1329 td->tt_scheduled = 0; 1330 } 1331 1332 /* verify the packet byte count */ 1333 if (count > td->remainder) { 1334 /* invalid USB packet */ 1335 td->error_any = 1; 1336 1337 /* release FIFO */ 1338 dwc_otg_common_rx_ack(sc); 1339 goto complete; 1340 } 1341 1342 /* read data from FIFO */ 1343 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1344 1345 td->remainder -= count; 1346 td->offset += count; 1347 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1348 break; 1349 default: 1350 break; 1351 } 1352 /* release FIFO */ 1353 dwc_otg_common_rx_ack(sc); 1354busy: 1355 return (0); 1356complete: 1357 return (1); 1358} 1359 1360static uint8_t 1361dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1362{ 1363 uint32_t hcint = 0; 1364 uint32_t hcchar; 1365 uint8_t delta; 1366 uint8_t channel; 1367 uint8_t x; 1368 1369 for (x = 0; x != td->max_packet_count; x++) { 1370 channel = td->channel[x]; 1371 if (channel >= DWC_OTG_MAX_CHANNELS) 1372 continue; 1373 hcint |= sc->sc_chan_state[channel].hcint; 1374 1375 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1376 channel, td->state, hcint, 1377 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1378 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1379 1380 /* check interrupt bits */ 1381 if (hcint & (HCINT_RETRY | 1382 HCINT_ACK | HCINT_NYET)) { 1383 /* give success bits priority over failure bits */ 1384 } else if (hcint & HCINT_STALL) { 1385 DPRINTF("CH=%d STALL\n", channel); 1386 td->error_stall = 1; 1387 td->error_any = 1; 1388 goto complete; 1389 } else if (hcint & HCINT_ERRORS) { 1390 DPRINTF("CH=%d ERROR\n", channel); 1391 td->errcnt++; 1392 if (td->hcsplt != 0 || td->errcnt >= 3) { 1393 if (td->ep_type != UE_ISOCHRONOUS) { 1394 td->error_any = 1; 1395 goto complete; 1396 } 1397 } 1398 } 1399 1400 /* check channels for data, if any */ 1401 if (dwc_otg_host_data_rx_sub(sc, td, channel)) 1402 goto complete; 1403 1404 /* refresh interrupt status */ 1405 hcint |= sc->sc_chan_state[channel].hcint; 1406 1407 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1408 HCINT_ACK | HCINT_NYET)) { 1409 if (!(hcint & HCINT_ERRORS)) 1410 td->errcnt = 0; 1411 } 1412 } 1413 1414 switch (td->state) { 1415 case DWC_CHAN_ST_START: 1416 if (td->hcsplt != 0) 1417 goto receive_spkt; 1418 else 1419 goto receive_pkt; 1420 1421 case DWC_CHAN_ST_WAIT_ANE: 1422 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1423 if (td->ep_type == UE_INTERRUPT) { 1424 /* 1425 * The USB specification does not 1426 * mandate a particular data toggle 1427 * value for USB INTERRUPT 1428 * transfers. Switch the data toggle 1429 * value to receive the packet 1430 * correctly: 1431 */ 1432 if (hcint & HCINT_DATATGLERR) { 1433 DPRINTF("Retrying packet due to " 1434 "data toggle error\n"); 1435 td->toggle ^= 1; 1436 goto receive_pkt; 1437 } 1438 } else if (td->ep_type == UE_ISOCHRONOUS) { 1439 goto complete; 1440 } 1441 td->did_nak = 1; 1442 td->tt_scheduled = 0; 1443 if (td->hcsplt != 0) 1444 goto receive_spkt; 1445 else 1446 goto receive_pkt; 1447 } else if (hcint & HCINT_NYET) { 1448 if (td->hcsplt != 0) { 1449 /* try again */ 1450 goto receive_pkt; 1451 } else { 1452 /* not a valid token for IN endpoints */ 1453 td->error_any = 1; 1454 goto complete; 1455 } 1456 } else if (hcint & HCINT_ACK) { 1457 /* wait for data - ACK arrived first */ 1458 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1459 goto busy; 1460 1461 if (td->ep_type == UE_ISOCHRONOUS) { 1462 /* check if we are complete */ 1463 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) { 1464 goto complete; 1465 } else { 1466 /* get more packets */ 1467 goto busy; 1468 } 1469 } else { 1470 /* check if we are complete */ 1471 if ((td->remainder == 0) || (td->got_short != 0)) { 1472 if (td->short_pkt) 1473 goto complete; 1474 1475 /* 1476 * Else need to receive a zero length 1477 * packet. 1478 */ 1479 } 1480 td->tt_scheduled = 0; 1481 td->did_nak = 0; 1482 if (td->hcsplt != 0) 1483 goto receive_spkt; 1484 else 1485 goto receive_pkt; 1486 } 1487 } 1488 break; 1489 1490 case DWC_CHAN_ST_WAIT_S_ANE: 1491 /* 1492 * NOTE: The DWC OTG hardware provides a fake ACK in 1493 * case of interrupt and isochronous transfers: 1494 */ 1495 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1496 td->did_nak = 1; 1497 td->tt_scheduled = 0; 1498 goto receive_spkt; 1499 } else if (hcint & HCINT_NYET) { 1500 td->tt_scheduled = 0; 1501 goto receive_spkt; 1502 } else if (hcint & HCINT_ACK) { 1503 td->did_nak = 0; 1504 goto receive_pkt; 1505 } 1506 break; 1507 1508 case DWC_CHAN_ST_WAIT_C_PKT: 1509 goto receive_pkt; 1510 1511 default: 1512 break; 1513 } 1514 goto busy; 1515 1516receive_pkt: 1517 /* free existing channel, if any */ 1518 dwc_otg_host_channel_free(sc, td); 1519 1520 if (td->hcsplt != 0) { 1521 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1522 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1523 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1524 goto busy; 1525 } 1526 delta = sc->sc_last_frame_num - td->tt_start_slot; 1527 if (delta > DWC_OTG_TT_SLOT_MAX) { 1528 if (td->ep_type != UE_ISOCHRONOUS) { 1529 /* we missed the service interval */ 1530 td->error_any = 1; 1531 } 1532 goto complete; 1533 } 1534 /* complete split */ 1535 td->hcsplt |= HCSPLT_COMPSPLT; 1536 } else if (dwc_otg_host_rate_check(sc, td)) { 1537 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1538 goto busy; 1539 } 1540 1541 /* allocate a new channel */ 1542 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1543 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1544 goto busy; 1545 } 1546 1547 /* set toggle, if any */ 1548 if (td->set_toggle) { 1549 td->set_toggle = 0; 1550 td->toggle = 1; 1551 } 1552 1553 td->state = DWC_CHAN_ST_WAIT_ANE; 1554 1555 for (x = 0; x != td->max_packet_count; x++) { 1556 channel = td->channel[x]; 1557 1558 /* receive one packet */ 1559 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1560 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1561 (1 << HCTSIZ_PKTCNT_SHIFT) | 1562 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1563 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1564 1565 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1566 1567 hcchar = td->hcchar; 1568 hcchar |= HCCHAR_EPDIR_IN; 1569 1570 /* receive complete split ASAP */ 1571 if ((sc->sc_last_frame_num & 1) != 0 && 1572 td->ep_type == UE_ISOCHRONOUS) 1573 hcchar |= HCCHAR_ODDFRM; 1574 else 1575 hcchar &= ~HCCHAR_ODDFRM; 1576 1577 /* must enable channel before data can be received */ 1578 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1579 } 1580 /* wait until next slot before trying complete split */ 1581 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1582 1583 goto busy; 1584 1585receive_spkt: 1586 /* free existing channel(s), if any */ 1587 dwc_otg_host_channel_free(sc, td); 1588 1589 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1590 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1591 td->state = DWC_CHAN_ST_START; 1592 goto busy; 1593 } 1594 delta = sc->sc_last_frame_num - td->tt_start_slot; 1595 if (delta > 5) { 1596 /* missed it */ 1597 td->tt_scheduled = 0; 1598 td->state = DWC_CHAN_ST_START; 1599 goto busy; 1600 } 1601 1602 /* allocate a new channel */ 1603 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1604 td->state = DWC_CHAN_ST_START; 1605 goto busy; 1606 } 1607 1608 channel = td->channel[0]; 1609 1610 td->hcsplt &= ~HCSPLT_COMPSPLT; 1611 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1612 1613 /* receive one packet */ 1614 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1615 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1616 1617 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1618 1619 /* send after next SOF event */ 1620 if ((sc->sc_last_frame_num & 1) == 0 && 1621 td->ep_type == UE_ISOCHRONOUS) 1622 td->hcchar |= HCCHAR_ODDFRM; 1623 else 1624 td->hcchar &= ~HCCHAR_ODDFRM; 1625 1626 hcchar = td->hcchar; 1627 hcchar |= HCCHAR_EPDIR_IN; 1628 1629 /* wait until next slot before trying complete split */ 1630 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1631 1632 /* must enable channel before data can be received */ 1633 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1634busy: 1635 return (1); /* busy */ 1636 1637complete: 1638 dwc_otg_host_channel_free(sc, td); 1639 return (0); /* complete */ 1640} 1641 1642static uint8_t 1643dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1644{ 1645 uint32_t temp; 1646 uint16_t count; 1647 uint8_t got_short; 1648 1649 got_short = 0; 1650 1651 /* check endpoint status */ 1652 if (sc->sc_last_rx_status == 0) 1653 goto not_complete; 1654 1655 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1656 goto not_complete; 1657 1658 /* check for SETUP packet */ 1659 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1660 GRXSTSRD_STP_DATA || 1661 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1662 GRXSTSRD_STP_COMPLETE) { 1663 if (td->remainder == 0) { 1664 /* 1665 * We are actually complete and have 1666 * received the next SETUP 1667 */ 1668 DPRINTFN(5, "faking complete\n"); 1669 return (0); /* complete */ 1670 } 1671 /* 1672 * USB Host Aborted the transfer. 1673 */ 1674 td->error_any = 1; 1675 return (0); /* complete */ 1676 } 1677 1678 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1679 GRXSTSRD_OUT_DATA) { 1680 /* release FIFO */ 1681 dwc_otg_common_rx_ack(sc); 1682 goto not_complete; 1683 } 1684 1685 /* get the packet byte count */ 1686 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1687 1688 /* verify the packet byte count */ 1689 if (count != td->max_packet_size) { 1690 if (count < td->max_packet_size) { 1691 /* we have a short packet */ 1692 td->short_pkt = 1; 1693 got_short = 1; 1694 } else { 1695 /* invalid USB packet */ 1696 td->error_any = 1; 1697 1698 /* release FIFO */ 1699 dwc_otg_common_rx_ack(sc); 1700 return (0); /* we are complete */ 1701 } 1702 } 1703 /* verify the packet byte count */ 1704 if (count > td->remainder) { 1705 /* invalid USB packet */ 1706 td->error_any = 1; 1707 1708 /* release FIFO */ 1709 dwc_otg_common_rx_ack(sc); 1710 return (0); /* we are complete */ 1711 } 1712 1713 /* read data from FIFO */ 1714 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1715 1716 td->remainder -= count; 1717 td->offset += count; 1718 1719 /* release FIFO */ 1720 dwc_otg_common_rx_ack(sc); 1721 1722 temp = sc->sc_out_ctl[td->ep_no]; 1723 1724 /* check for isochronous mode */ 1725 if ((temp & DIEPCTL_EPTYPE_MASK) == 1726 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1727 /* toggle odd or even frame bit */ 1728 if (temp & DIEPCTL_SETD1PID) { 1729 temp &= ~DIEPCTL_SETD1PID; 1730 temp |= DIEPCTL_SETD0PID; 1731 } else { 1732 temp &= ~DIEPCTL_SETD0PID; 1733 temp |= DIEPCTL_SETD1PID; 1734 } 1735 sc->sc_out_ctl[td->ep_no] = temp; 1736 } 1737 1738 /* check if we are complete */ 1739 if ((td->remainder == 0) || got_short) { 1740 if (td->short_pkt) { 1741 /* we are complete */ 1742 return (0); 1743 } 1744 /* else need to receive a zero length packet */ 1745 } 1746 1747not_complete: 1748 1749 /* enable SETUP and transfer complete interrupt */ 1750 if (td->ep_no == 0) { 1751 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1752 DXEPTSIZ_SET_MULTI(3) | 1753 DXEPTSIZ_SET_NPKT(1) | 1754 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1755 } else { 1756 /* allow reception of multiple packets */ 1757 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1758 DXEPTSIZ_SET_MULTI(1) | 1759 DXEPTSIZ_SET_NPKT(4) | 1760 DXEPTSIZ_SET_NBYTES(4 * 1761 ((td->max_packet_size + 3) & ~3))); 1762 } 1763 temp = sc->sc_out_ctl[td->ep_no]; 1764 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | 1765 DOEPCTL_EPENA | DOEPCTL_CNAK); 1766 1767 return (1); /* not complete */ 1768} 1769 1770static uint8_t 1771dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1772{ 1773 uint32_t count; 1774 uint32_t hcint; 1775 uint32_t hcchar; 1776 uint8_t delta; 1777 uint8_t channel; 1778 uint8_t x; 1779 1780 dwc_otg_host_dump_rx(sc, td); 1781 1782 /* check that last channel is complete */ 1783 channel = td->channel[td->npkt]; 1784 1785 if (channel < DWC_OTG_MAX_CHANNELS) { 1786 hcint = sc->sc_chan_state[channel].hcint; 1787 1788 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1789 channel, td->state, hcint, 1790 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1791 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1792 1793 if (hcint & (HCINT_RETRY | 1794 HCINT_ACK | HCINT_NYET)) { 1795 /* give success bits priority over failure bits */ 1796 } else if (hcint & HCINT_STALL) { 1797 DPRINTF("CH=%d STALL\n", channel); 1798 td->error_stall = 1; 1799 td->error_any = 1; 1800 goto complete; 1801 } else if (hcint & HCINT_ERRORS) { 1802 DPRINTF("CH=%d ERROR\n", channel); 1803 td->errcnt++; 1804 if (td->hcsplt != 0 || td->errcnt >= 3) { 1805 td->error_any = 1; 1806 goto complete; 1807 } 1808 } 1809 1810 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1811 HCINT_ACK | HCINT_NYET)) { 1812 1813 if (!(hcint & HCINT_ERRORS)) 1814 td->errcnt = 0; 1815 } 1816 } else { 1817 hcint = 0; 1818 } 1819 1820 switch (td->state) { 1821 case DWC_CHAN_ST_START: 1822 goto send_pkt; 1823 1824 case DWC_CHAN_ST_WAIT_ANE: 1825 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1826 td->did_nak = 1; 1827 td->tt_scheduled = 0; 1828 goto send_pkt; 1829 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1830 td->offset += td->tx_bytes; 1831 td->remainder -= td->tx_bytes; 1832 td->toggle ^= 1; 1833 /* check if next response will be a NAK */ 1834 if (hcint & HCINT_NYET) 1835 td->did_nak = 1; 1836 else 1837 td->did_nak = 0; 1838 td->tt_scheduled = 0; 1839 1840 /* check remainder */ 1841 if (td->remainder == 0) { 1842 if (td->short_pkt) 1843 goto complete; 1844 1845 /* 1846 * Else we need to transmit a short 1847 * packet: 1848 */ 1849 } 1850 goto send_pkt; 1851 } 1852 break; 1853 1854 case DWC_CHAN_ST_WAIT_S_ANE: 1855 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1856 td->did_nak = 1; 1857 td->tt_scheduled = 0; 1858 goto send_pkt; 1859 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1860 td->did_nak = 0; 1861 goto send_cpkt; 1862 } 1863 break; 1864 1865 case DWC_CHAN_ST_WAIT_C_ANE: 1866 if (hcint & HCINT_NYET) { 1867 goto send_cpkt; 1868 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1869 td->did_nak = 1; 1870 td->tt_scheduled = 0; 1871 goto send_pkt; 1872 } else if (hcint & HCINT_ACK) { 1873 td->offset += td->tx_bytes; 1874 td->remainder -= td->tx_bytes; 1875 td->toggle ^= 1; 1876 td->did_nak = 0; 1877 td->tt_scheduled = 0; 1878 1879 /* check remainder */ 1880 if (td->remainder == 0) { 1881 if (td->short_pkt) 1882 goto complete; 1883 1884 /* else we need to transmit a short packet */ 1885 } 1886 goto send_pkt; 1887 } 1888 break; 1889 1890 case DWC_CHAN_ST_WAIT_C_PKT: 1891 goto send_cpkt; 1892 1893 case DWC_CHAN_ST_TX_WAIT_ISOC: 1894 /* Check if ISOCHRONOUS OUT traffic is complete */ 1895 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1896 break; 1897 1898 td->offset += td->tx_bytes; 1899 td->remainder -= td->tx_bytes; 1900 goto complete; 1901 default: 1902 break; 1903 } 1904 goto busy; 1905 1906send_pkt: 1907 /* free existing channel(s), if any */ 1908 dwc_otg_host_channel_free(sc, td); 1909 1910 if (td->hcsplt != 0) { 1911 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1912 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1913 td->state = DWC_CHAN_ST_START; 1914 goto busy; 1915 } 1916 delta = sc->sc_last_frame_num - td->tt_start_slot; 1917 if (delta > 5) { 1918 /* missed it */ 1919 td->tt_scheduled = 0; 1920 td->state = DWC_CHAN_ST_START; 1921 goto busy; 1922 } 1923 } else if (dwc_otg_host_rate_check(sc, td)) { 1924 td->state = DWC_CHAN_ST_START; 1925 goto busy; 1926 } 1927 1928 /* allocate a new channel */ 1929 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1930 td->state = DWC_CHAN_ST_START; 1931 goto busy; 1932 } 1933 1934 /* set toggle, if any */ 1935 if (td->set_toggle) { 1936 td->set_toggle = 0; 1937 td->toggle = 1; 1938 } 1939 1940 if (td->ep_type == UE_ISOCHRONOUS) { 1941 /* ISOCHRONOUS OUT transfers don't have any ACKs */ 1942 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1943 td->hcsplt &= ~HCSPLT_COMPSPLT; 1944 if (td->hcsplt != 0) { 1945 /* get maximum transfer length */ 1946 count = td->remainder; 1947 if (count > HCSPLT_XACTLEN_BURST) { 1948 DPRINTF("TT overflow\n"); 1949 td->error_any = 1; 1950 goto complete; 1951 } 1952 /* Update transaction position */ 1953 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1954 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1955 } 1956 } else if (td->hcsplt != 0) { 1957 td->hcsplt &= ~HCSPLT_COMPSPLT; 1958 /* Wait for ACK/NAK/ERR from TT */ 1959 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1960 } else { 1961 /* Wait for ACK/NAK/STALL from device */ 1962 td->state = DWC_CHAN_ST_WAIT_ANE; 1963 } 1964 1965 td->tx_bytes = 0; 1966 1967 for (x = 0; x != td->max_packet_count; x++) { 1968 uint32_t rem_bytes; 1969 1970 channel = td->channel[x]; 1971 1972 /* send one packet at a time */ 1973 count = td->max_packet_size; 1974 rem_bytes = td->remainder - td->tx_bytes; 1975 if (rem_bytes < count) { 1976 /* we have a short packet */ 1977 td->short_pkt = 1; 1978 count = rem_bytes; 1979 } 1980 if (count == rem_bytes) { 1981 /* last packet */ 1982 switch (x) { 1983 case 0: 1984 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1985 (count << HCTSIZ_XFERSIZE_SHIFT) | 1986 (1 << HCTSIZ_PKTCNT_SHIFT) | 1987 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1988 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1989 break; 1990 case 1: 1991 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1992 (count << HCTSIZ_XFERSIZE_SHIFT) | 1993 (1 << HCTSIZ_PKTCNT_SHIFT) | 1994 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1995 break; 1996 default: 1997 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1998 (count << HCTSIZ_XFERSIZE_SHIFT) | 1999 (1 << HCTSIZ_PKTCNT_SHIFT) | 2000 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 2001 break; 2002 } 2003 } else if (td->ep_type == UE_ISOCHRONOUS && 2004 td->max_packet_count > 1) { 2005 /* ISOCHRONOUS multi packet */ 2006 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2007 (count << HCTSIZ_XFERSIZE_SHIFT) | 2008 (1 << HCTSIZ_PKTCNT_SHIFT) | 2009 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 2010 } else { 2011 /* TODO: HCTSIZ_DOPNG */ 2012 /* standard BULK/INTERRUPT/CONTROL packet */ 2013 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2014 (count << HCTSIZ_XFERSIZE_SHIFT) | 2015 (1 << HCTSIZ_PKTCNT_SHIFT) | 2016 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 2017 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 2018 } 2019 2020 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2021 2022 hcchar = td->hcchar; 2023 hcchar &= ~HCCHAR_EPDIR_IN; 2024 2025 /* send after next SOF event */ 2026 if ((sc->sc_last_frame_num & 1) == 0 && 2027 td->ep_type == UE_ISOCHRONOUS) 2028 hcchar |= HCCHAR_ODDFRM; 2029 else 2030 hcchar &= ~HCCHAR_ODDFRM; 2031 2032 /* must enable before writing data to FIFO */ 2033 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2034 2035 if (count != 0) { 2036 /* write data into FIFO */ 2037 dwc_otg_write_fifo(sc, td->pc, td->offset + 2038 td->tx_bytes, DOTG_DFIFO(channel), count); 2039 } 2040 2041 /* store number of bytes transmitted */ 2042 td->tx_bytes += count; 2043 2044 /* store last packet index */ 2045 td->npkt = x; 2046 2047 /* check for last packet */ 2048 if (count == rem_bytes) 2049 break; 2050 } 2051 goto busy; 2052 2053send_cpkt: 2054 /* free existing channel, if any */ 2055 dwc_otg_host_channel_free(sc, td); 2056 2057 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 2058 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 2059 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2060 goto busy; 2061 } 2062 delta = sc->sc_last_frame_num - td->tt_start_slot; 2063 if (delta > DWC_OTG_TT_SLOT_MAX) { 2064 /* we missed the service interval */ 2065 if (td->ep_type != UE_ISOCHRONOUS) 2066 td->error_any = 1; 2067 goto complete; 2068 } 2069 2070 /* allocate a new channel */ 2071 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 2072 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2073 goto busy; 2074 } 2075 2076 channel = td->channel[0]; 2077 2078 td->hcsplt |= HCSPLT_COMPSPLT; 2079 td->state = DWC_CHAN_ST_WAIT_C_ANE; 2080 2081 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2082 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 2083 2084 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2085 2086 hcchar = td->hcchar; 2087 hcchar &= ~HCCHAR_EPDIR_IN; 2088 2089 /* receive complete split ASAP */ 2090 if ((sc->sc_last_frame_num & 1) != 0 && 2091 td->ep_type == UE_ISOCHRONOUS) 2092 hcchar |= HCCHAR_ODDFRM; 2093 else 2094 hcchar &= ~HCCHAR_ODDFRM; 2095 2096 /* must enable channel before data can be received */ 2097 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2098 2099 /* wait until next slot before trying complete split */ 2100 td->tt_complete_slot = sc->sc_last_frame_num + 1; 2101busy: 2102 return (1); /* busy */ 2103 2104complete: 2105 dwc_otg_host_channel_free(sc, td); 2106 return (0); /* complete */ 2107} 2108 2109static uint8_t 2110dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2111{ 2112 uint32_t max_buffer; 2113 uint32_t count; 2114 uint32_t fifo_left; 2115 uint32_t mpkt; 2116 uint32_t temp; 2117 uint8_t to; 2118 2119 to = 3; /* don't loop forever! */ 2120 2121 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 2122 2123repeat: 2124 /* check for for endpoint 0 data */ 2125 2126 temp = sc->sc_last_rx_status; 2127 2128 if ((td->ep_no == 0) && (temp != 0) && 2129 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2130 2131 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2132 GRXSTSRD_STP_DATA && 2133 (temp & GRXSTSRD_PKTSTS_MASK) != 2134 GRXSTSRD_STP_COMPLETE) { 2135 2136 /* dump data - wrong direction */ 2137 dwc_otg_common_rx_ack(sc); 2138 } else { 2139 /* 2140 * The current transfer was cancelled 2141 * by the USB Host: 2142 */ 2143 td->error_any = 1; 2144 return (0); /* complete */ 2145 } 2146 } 2147 2148 /* fill in more TX data, if possible */ 2149 if (td->tx_bytes != 0) { 2150 2151 uint16_t cpkt; 2152 2153 /* check if packets have been transferred */ 2154 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2155 2156 /* get current packet number */ 2157 cpkt = DXEPTSIZ_GET_NPKT(temp); 2158 2159 if (cpkt >= td->npkt) { 2160 fifo_left = 0; 2161 } else { 2162 if (max_buffer != 0) { 2163 fifo_left = (td->npkt - cpkt) * 2164 td->max_packet_size; 2165 2166 if (fifo_left > max_buffer) 2167 fifo_left = max_buffer; 2168 } else { 2169 fifo_left = td->max_packet_size; 2170 } 2171 } 2172 2173 count = td->tx_bytes; 2174 if (count > fifo_left) 2175 count = fifo_left; 2176 2177 if (count != 0) { 2178 /* write data into FIFO */ 2179 dwc_otg_write_fifo(sc, td->pc, td->offset, 2180 DOTG_DFIFO(td->ep_no), count); 2181 2182 td->tx_bytes -= count; 2183 td->remainder -= count; 2184 td->offset += count; 2185 td->npkt = cpkt; 2186 } 2187 if (td->tx_bytes != 0) 2188 goto not_complete; 2189 2190 /* check remainder */ 2191 if (td->remainder == 0) { 2192 if (td->short_pkt) 2193 return (0); /* complete */ 2194 2195 /* else we need to transmit a short packet */ 2196 } 2197 } 2198 2199 if (!to--) 2200 goto not_complete; 2201 2202 /* check if not all packets have been transferred */ 2203 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2204 2205 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2206 2207 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2208 "DIEPCTL=0x%08x\n", td->ep_no, 2209 DXEPTSIZ_GET_NPKT(temp), 2210 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2211 2212 goto not_complete; 2213 } 2214 2215 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2216 2217 /* try to optimise by sending more data */ 2218 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2219 2220 /* send multiple packets at the same time */ 2221 mpkt = max_buffer / td->max_packet_size; 2222 2223 if (mpkt > 0x3FE) 2224 mpkt = 0x3FE; 2225 2226 count = td->remainder; 2227 if (count > 0x7FFFFF) 2228 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2229 2230 td->npkt = count / td->max_packet_size; 2231 2232 /* 2233 * NOTE: We could use 0x3FE instead of "mpkt" in the 2234 * check below to get more throughput, but then we 2235 * have a dependency towards non-generic chip features 2236 * to disable the TX-FIFO-EMPTY interrupts on a per 2237 * endpoint basis. Increase the maximum buffer size of 2238 * the IN endpoint to increase the performance. 2239 */ 2240 if (td->npkt > mpkt) { 2241 td->npkt = mpkt; 2242 count = td->max_packet_size * mpkt; 2243 } else if ((count == 0) || (count % td->max_packet_size)) { 2244 /* we are transmitting a short packet */ 2245 td->npkt++; 2246 td->short_pkt = 1; 2247 } 2248 } else { 2249 /* send one packet at a time */ 2250 mpkt = 1; 2251 count = td->max_packet_size; 2252 if (td->remainder < count) { 2253 /* we have a short packet */ 2254 td->short_pkt = 1; 2255 count = td->remainder; 2256 } 2257 td->npkt = 1; 2258 } 2259 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2260 DXEPTSIZ_SET_MULTI(1) | 2261 DXEPTSIZ_SET_NPKT(td->npkt) | 2262 DXEPTSIZ_SET_NBYTES(count)); 2263 2264 /* make room for buffering */ 2265 td->npkt += mpkt; 2266 2267 temp = sc->sc_in_ctl[td->ep_no]; 2268 2269 /* check for isochronous mode */ 2270 if ((temp & DIEPCTL_EPTYPE_MASK) == 2271 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2272 /* toggle odd or even frame bit */ 2273 if (temp & DIEPCTL_SETD1PID) { 2274 temp &= ~DIEPCTL_SETD1PID; 2275 temp |= DIEPCTL_SETD0PID; 2276 } else { 2277 temp &= ~DIEPCTL_SETD0PID; 2278 temp |= DIEPCTL_SETD1PID; 2279 } 2280 sc->sc_in_ctl[td->ep_no] = temp; 2281 } 2282 2283 /* must enable before writing data to FIFO */ 2284 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2285 DIEPCTL_EPENA | DIEPCTL_CNAK); 2286 2287 td->tx_bytes = count; 2288 2289 /* check remainder */ 2290 if (td->tx_bytes == 0 && 2291 td->remainder == 0) { 2292 if (td->short_pkt) 2293 return (0); /* complete */ 2294 2295 /* else we need to transmit a short packet */ 2296 } 2297 goto repeat; 2298 2299not_complete: 2300 return (1); /* not complete */ 2301} 2302 2303static uint8_t 2304dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2305{ 2306 uint32_t temp; 2307 2308 /* 2309 * If all packets are transferred we are complete: 2310 */ 2311 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2312 2313 /* check that all packets have been transferred */ 2314 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2315 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2316 goto not_complete; 2317 } 2318 return (0); 2319 2320not_complete: 2321 2322 /* we only want to know if there is a SETUP packet or free IN packet */ 2323 2324 temp = sc->sc_last_rx_status; 2325 2326 if ((td->ep_no == 0) && (temp != 0) && 2327 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2328 2329 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2330 GRXSTSRD_STP_DATA || 2331 (temp & GRXSTSRD_PKTSTS_MASK) == 2332 GRXSTSRD_STP_COMPLETE) { 2333 DPRINTFN(5, "faking complete\n"); 2334 /* 2335 * Race condition: We are complete! 2336 */ 2337 return (0); 2338 } else { 2339 /* dump data - wrong direction */ 2340 dwc_otg_common_rx_ack(sc); 2341 } 2342 } 2343 return (1); /* not complete */ 2344} 2345 2346static void 2347dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2348{ 2349 struct dwc_otg_td *td; 2350 uint8_t toggle; 2351 uint8_t tmr_val; 2352 uint8_t tmr_res; 2353 2354 DPRINTFN(9, "\n"); 2355 2356 td = xfer->td_transfer_cache; 2357 if (td == NULL) 2358 return; 2359 2360 while (1) { 2361 if ((td->func) (sc, td)) { 2362 /* operation in progress */ 2363 break; 2364 } 2365 if (((void *)td) == xfer->td_transfer_last) { 2366 goto done; 2367 } 2368 if (td->error_any) { 2369 goto done; 2370 } else if (td->remainder > 0) { 2371 /* 2372 * We had a short transfer. If there is no alternate 2373 * next, stop processing ! 2374 */ 2375 if (!td->alt_next) 2376 goto done; 2377 } 2378 2379 /* 2380 * Fetch the next transfer descriptor and transfer 2381 * some flags to the next transfer descriptor 2382 */ 2383 tmr_res = td->tmr_res; 2384 tmr_val = td->tmr_val; 2385 toggle = td->toggle; 2386 td = td->obj_next; 2387 xfer->td_transfer_cache = td; 2388 td->toggle = toggle; /* transfer toggle */ 2389 td->tmr_res = tmr_res; 2390 td->tmr_val = tmr_val; 2391 } 2392 return; 2393 2394done: 2395 xfer->td_transfer_cache = NULL; 2396 sc->sc_xfer_complete = 1; 2397} 2398 2399static uint8_t 2400dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2401{ 2402 struct dwc_otg_td *td; 2403 2404 DPRINTFN(9, "\n"); 2405 2406 td = xfer->td_transfer_cache; 2407 if (td == NULL) { 2408 /* compute all actual lengths */ 2409 dwc_otg_standard_done(xfer); 2410 return (1); 2411 } 2412 return (0); 2413} 2414 2415static void 2416dwc_otg_timer(void *_sc) 2417{ 2418 struct dwc_otg_softc *sc = _sc; 2419 2420 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2421 2422 DPRINTF("\n"); 2423 2424 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2425 2426 /* increment timer value */ 2427 sc->sc_tmr_val++; 2428 2429 /* enable SOF interrupt, which will poll jobs */ 2430 dwc_otg_enable_sof_irq(sc); 2431 2432 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2433 2434 if (sc->sc_timer_active) { 2435 /* restart timer */ 2436 usb_callout_reset(&sc->sc_timer, 2437 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2438 &dwc_otg_timer, sc); 2439 } 2440} 2441 2442static void 2443dwc_otg_timer_start(struct dwc_otg_softc *sc) 2444{ 2445 if (sc->sc_timer_active != 0) 2446 return; 2447 2448 sc->sc_timer_active = 1; 2449 2450 /* restart timer */ 2451 usb_callout_reset(&sc->sc_timer, 2452 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2453 &dwc_otg_timer, sc); 2454} 2455 2456static void 2457dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2458{ 2459 if (sc->sc_timer_active == 0) 2460 return; 2461 2462 sc->sc_timer_active = 0; 2463 2464 /* stop timer */ 2465 usb_callout_stop(&sc->sc_timer); 2466} 2467 2468static uint16_t 2469dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2470{ 2471 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2472 pinfo->slot_index++; 2473 return (pinfo->slot_index); 2474} 2475 2476static uint8_t 2477dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2478{ 2479 TAILQ_HEAD(, usb_xfer) head; 2480 struct usb_xfer *xfer; 2481 struct usb_xfer *xfer_next; 2482 struct dwc_otg_td *td; 2483 uint16_t temp; 2484 uint16_t slot; 2485 2486 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2487 2488 if (sc->sc_last_frame_num == temp) 2489 return (0); 2490 2491 sc->sc_last_frame_num = temp; 2492 2493 TAILQ_INIT(&head); 2494 2495 if ((temp & 7) == 0) { 2496 2497 /* reset the schedule */ 2498 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2499 2500 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2501 td = xfer->td_transfer_cache; 2502 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2503 continue; 2504 2505 /* check for IN direction */ 2506 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2507 continue; 2508 2509 sc->sc_needsof = 1; 2510 2511 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2512 continue; 2513 2514 /* compute slot */ 2515 slot = dwc_otg_compute_isoc_rx_tt_slot( 2516 sc->sc_tt_info + td->tt_index); 2517 if (slot > 3) { 2518 /* 2519 * Not enough time to get complete 2520 * split executed. 2521 */ 2522 continue; 2523 } 2524 /* Delayed start */ 2525 td->tt_start_slot = temp + slot; 2526 td->tt_scheduled = 1; 2527 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2528 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2529 } 2530 2531 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2532 td = xfer->td_transfer_cache; 2533 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2534 continue; 2535 2536 /* check for OUT direction */ 2537 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2538 continue; 2539 2540 sc->sc_needsof = 1; 2541 2542 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2543 continue; 2544 2545 /* Start ASAP */ 2546 td->tt_start_slot = temp; 2547 td->tt_scheduled = 1; 2548 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2549 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2550 } 2551 2552 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2553 td = xfer->td_transfer_cache; 2554 if (td == NULL || td->ep_type != UE_INTERRUPT) 2555 continue; 2556 2557 if (td->tt_scheduled != 0) { 2558 sc->sc_needsof = 1; 2559 continue; 2560 } 2561 2562 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2563 continue; 2564 2565 if (td->hcsplt == 0) { 2566 sc->sc_needsof = 1; 2567 td->tt_scheduled = 1; 2568 continue; 2569 } 2570 2571 /* start ASAP */ 2572 td->tt_start_slot = temp; 2573 sc->sc_needsof = 1; 2574 td->tt_scheduled = 1; 2575 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2576 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2577 } 2578 2579 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2580 td = xfer->td_transfer_cache; 2581 if (td == NULL || 2582 td->ep_type != UE_CONTROL) { 2583 continue; 2584 } 2585 2586 sc->sc_needsof = 1; 2587 2588 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2589 continue; 2590 2591 /* start ASAP */ 2592 td->tt_start_slot = temp; 2593 td->tt_scheduled = 1; 2594 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2595 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2596 } 2597 } 2598 if ((temp & 7) < 6) { 2599 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2600 td = xfer->td_transfer_cache; 2601 if (td == NULL || 2602 td->ep_type != UE_BULK) { 2603 continue; 2604 } 2605 2606 sc->sc_needsof = 1; 2607 2608 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2609 continue; 2610 2611 /* start ASAP */ 2612 td->tt_start_slot = temp; 2613 td->tt_scheduled = 1; 2614 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2615 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2616 } 2617 } 2618 2619 /* Put TT transfers in execution order at the end */ 2620 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2621 2622 /* move all TT transfers in front, keeping the current order */ 2623 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2624 td = xfer->td_transfer_cache; 2625 if (td == NULL || td->hcsplt == 0) 2626 continue; 2627 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2628 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2629 } 2630 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2631 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2632 2633 /* put non-TT non-ISOCHRONOUS transfers last */ 2634 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2635 td = xfer->td_transfer_cache; 2636 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS) 2637 continue; 2638 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2639 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2640 } 2641 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2642 2643 if ((temp & 7) == 0) { 2644 2645 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2646 (int)temp, (int)sc->sc_needsof); 2647 2648 /* update SOF IRQ mask */ 2649 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2650 if (sc->sc_needsof == 0) { 2651 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2652 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2653 } 2654 } else { 2655 if (sc->sc_needsof != 0) { 2656 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2657 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2658 } 2659 } 2660 2661 /* clear need SOF flag */ 2662 sc->sc_needsof = 0; 2663 } 2664 return (1); 2665} 2666 2667static void 2668dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2669{ 2670 struct usb_xfer *xfer; 2671 uint32_t count; 2672 uint32_t temp; 2673 uint32_t haint; 2674 uint8_t got_rx_status; 2675 uint8_t x; 2676 2677 if (sc->sc_flags.status_device_mode == 0) { 2678 /* 2679 * Update host transfer schedule, so that new 2680 * transfers can be issued: 2681 */ 2682 dwc_otg_update_host_transfer_schedule_locked(sc); 2683 } 2684 count = 0; 2685repeat: 2686 if (++count == 16) { 2687 /* give other interrupts a chance */ 2688 DPRINTF("Yield\n"); 2689 return; 2690 } 2691 2692 /* get all host channel interrupts */ 2693 haint = DWC_OTG_READ_4(sc, DOTG_HAINT); 2694 while (1) { 2695 x = ffs(haint) - 1; 2696 if (x >= sc->sc_host_ch_max) 2697 break; 2698 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2699 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2700 temp &= ~HCINT_SOFTWARE_ONLY; 2701 sc->sc_chan_state[x].hcint |= temp; 2702 haint &= ~(1U << x); 2703 } 2704 2705 if (sc->sc_last_rx_status == 0) { 2706 2707 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2708 if (temp & GINTSTS_RXFLVL) { 2709 /* pop current status */ 2710 sc->sc_last_rx_status = 2711 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2712 } 2713 2714 if (sc->sc_last_rx_status != 0) { 2715 2716 uint8_t ep_no; 2717 2718 temp = sc->sc_last_rx_status & 2719 GRXSTSRD_PKTSTS_MASK; 2720 2721 /* non-data messages we simply skip */ 2722 if (temp != GRXSTSRD_STP_DATA && 2723 temp != GRXSTSRD_STP_COMPLETE && 2724 temp != GRXSTSRD_OUT_DATA) { 2725 /* check for halted channel */ 2726 if (temp == GRXSTSRH_HALTED) { 2727 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); 2728 sc->sc_chan_state[ep_no].wait_halted = 0; 2729 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); 2730 } 2731 /* store bytes and FIFO offset */ 2732 sc->sc_current_rx_bytes = 0; 2733 sc->sc_current_rx_fifo = 0; 2734 2735 /* acknowledge status */ 2736 dwc_otg_common_rx_ack(sc); 2737 goto repeat; 2738 } 2739 2740 temp = GRXSTSRD_BCNT_GET( 2741 sc->sc_last_rx_status); 2742 ep_no = GRXSTSRD_CHNUM_GET( 2743 sc->sc_last_rx_status); 2744 2745 /* store bytes and FIFO offset */ 2746 sc->sc_current_rx_bytes = (temp + 3) & ~3; 2747 sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no); 2748 2749 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2750 2751 /* check if we should dump the data */ 2752 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2753 dwc_otg_common_rx_ack(sc); 2754 goto repeat; 2755 } 2756 2757 got_rx_status = 1; 2758 2759 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2760 sc->sc_last_rx_status, ep_no, 2761 (sc->sc_last_rx_status >> 15) & 3, 2762 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2763 (sc->sc_last_rx_status >> 17) & 15); 2764 } else { 2765 got_rx_status = 0; 2766 } 2767 } else { 2768 uint8_t ep_no; 2769 2770 ep_no = GRXSTSRD_CHNUM_GET( 2771 sc->sc_last_rx_status); 2772 2773 /* check if we should dump the data */ 2774 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2775 dwc_otg_common_rx_ack(sc); 2776 goto repeat; 2777 } 2778 2779 got_rx_status = 1; 2780 } 2781 2782 /* execute FIFOs */ 2783 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2784 dwc_otg_xfer_do_fifo(sc, xfer); 2785 2786 if (got_rx_status) { 2787 /* check if data was consumed */ 2788 if (sc->sc_last_rx_status == 0) 2789 goto repeat; 2790 2791 /* disable RX FIFO level interrupt */ 2792 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2793 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2794 } 2795} 2796 2797static void 2798dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2799{ 2800 struct usb_xfer *xfer; 2801repeat: 2802 /* scan for completion events */ 2803 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2804 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2805 goto repeat; 2806 } 2807} 2808 2809static void 2810dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2811{ 2812 DPRINTFN(5, "vbus = %u\n", is_on); 2813 2814 /* 2815 * If the USB host mode is forced, then assume VBUS is always 2816 * present else rely on the input to this function: 2817 */ 2818 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2819 2820 if (!sc->sc_flags.status_vbus) { 2821 sc->sc_flags.status_vbus = 1; 2822 2823 /* complete root HUB interrupt endpoint */ 2824 2825 dwc_otg_root_intr(sc); 2826 } 2827 } else { 2828 if (sc->sc_flags.status_vbus) { 2829 sc->sc_flags.status_vbus = 0; 2830 sc->sc_flags.status_bus_reset = 0; 2831 sc->sc_flags.status_suspend = 0; 2832 sc->sc_flags.change_suspend = 0; 2833 sc->sc_flags.change_connect = 1; 2834 2835 /* complete root HUB interrupt endpoint */ 2836 2837 dwc_otg_root_intr(sc); 2838 } 2839 } 2840} 2841 2842int 2843dwc_otg_filter_interrupt(void *arg) 2844{ 2845 struct dwc_otg_softc *sc = arg; 2846 int retval = FILTER_HANDLED; 2847 uint32_t status; 2848 2849 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2850 2851 /* read and clear interrupt status */ 2852 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2853 2854 /* clear interrupts we are handling here */ 2855 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2856 2857 /* check for USB state change interrupts */ 2858 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2859 retval = FILTER_SCHEDULE_THREAD; 2860 2861 /* clear FIFO empty interrupts */ 2862 if (status & sc->sc_irq_mask & 2863 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { 2864 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 2865 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2866 } 2867 /* clear all IN endpoint interrupts */ 2868 if (status & GINTSTS_IEPINT) { 2869 uint32_t temp; 2870 uint8_t x; 2871 2872 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2873 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2874 /* 2875 * NOTE: Need to clear all interrupt bits, 2876 * because some appears to be unmaskable and 2877 * can cause an interrupt loop: 2878 */ 2879 if (temp != 0) 2880 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp); 2881 } 2882 } 2883 2884 /* poll FIFOs, if any */ 2885 dwc_otg_interrupt_poll_locked(sc); 2886 2887 if (sc->sc_xfer_complete != 0) 2888 retval = FILTER_SCHEDULE_THREAD; 2889 2890 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2891 2892 return (retval); 2893} 2894 2895void 2896dwc_otg_interrupt(void *arg) 2897{ 2898 struct dwc_otg_softc *sc = arg; 2899 uint32_t status; 2900 2901 USB_BUS_LOCK(&sc->sc_bus); 2902 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2903 2904 /* read and clear interrupt status */ 2905 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2906 2907 /* clear interrupts we are handling here */ 2908 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2909 2910 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2911 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2912 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2913 2914 if (status & GINTSTS_USBRST) { 2915 2916 /* set correct state */ 2917 sc->sc_flags.status_device_mode = 1; 2918 sc->sc_flags.status_bus_reset = 0; 2919 sc->sc_flags.status_suspend = 0; 2920 sc->sc_flags.change_suspend = 0; 2921 sc->sc_flags.change_connect = 1; 2922 2923 /* Disable SOF interrupt */ 2924 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2925 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2926 2927 /* complete root HUB interrupt endpoint */ 2928 dwc_otg_root_intr(sc); 2929 } 2930 2931 /* check for any bus state change interrupts */ 2932 if (status & GINTSTS_ENUMDONE) { 2933 2934 uint32_t temp; 2935 2936 DPRINTFN(5, "end of reset\n"); 2937 2938 /* set correct state */ 2939 sc->sc_flags.status_device_mode = 1; 2940 sc->sc_flags.status_bus_reset = 1; 2941 sc->sc_flags.status_suspend = 0; 2942 sc->sc_flags.change_suspend = 0; 2943 sc->sc_flags.change_connect = 1; 2944 sc->sc_flags.status_low_speed = 0; 2945 sc->sc_flags.port_enabled = 1; 2946 2947 /* reset FIFOs */ 2948 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2949 2950 /* reset function address */ 2951 dwc_otg_set_address(sc, 0); 2952 2953 /* figure out enumeration speed */ 2954 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2955 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2956 sc->sc_flags.status_high_speed = 1; 2957 else 2958 sc->sc_flags.status_high_speed = 0; 2959 2960 /* 2961 * Disable resume and SOF interrupt, and enable 2962 * suspend and RX frame interrupt: 2963 */ 2964 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2965 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2966 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2967 2968 /* complete root HUB interrupt endpoint */ 2969 dwc_otg_root_intr(sc); 2970 } 2971 2972 if (status & GINTSTS_PRTINT) { 2973 uint32_t hprt; 2974 2975 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2976 2977 /* clear change bits */ 2978 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2979 HPRT_PRTPWR | HPRT_PRTENCHNG | 2980 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2981 sc->sc_hprt_val); 2982 2983 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2984 2985 sc->sc_flags.status_device_mode = 0; 2986 2987 if (hprt & HPRT_PRTCONNSTS) 2988 sc->sc_flags.status_bus_reset = 1; 2989 else 2990 sc->sc_flags.status_bus_reset = 0; 2991 2992 if ((hprt & HPRT_PRTENCHNG) && 2993 (hprt & HPRT_PRTENA) == 0) 2994 sc->sc_flags.change_enabled = 1; 2995 2996 if (hprt & HPRT_PRTENA) 2997 sc->sc_flags.port_enabled = 1; 2998 else 2999 sc->sc_flags.port_enabled = 0; 3000 3001 if (hprt & HPRT_PRTOVRCURRCHNG) 3002 sc->sc_flags.change_over_current = 1; 3003 3004 if (hprt & HPRT_PRTOVRCURRACT) 3005 sc->sc_flags.port_over_current = 1; 3006 else 3007 sc->sc_flags.port_over_current = 0; 3008 3009 if (hprt & HPRT_PRTPWR) 3010 sc->sc_flags.port_powered = 1; 3011 else 3012 sc->sc_flags.port_powered = 0; 3013 3014 if (((hprt & HPRT_PRTSPD_MASK) 3015 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 3016 sc->sc_flags.status_low_speed = 1; 3017 else 3018 sc->sc_flags.status_low_speed = 0; 3019 3020 if (((hprt & HPRT_PRTSPD_MASK) 3021 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 3022 sc->sc_flags.status_high_speed = 1; 3023 else 3024 sc->sc_flags.status_high_speed = 0; 3025 3026 if (hprt & HPRT_PRTCONNDET) 3027 sc->sc_flags.change_connect = 1; 3028 3029 if (hprt & HPRT_PRTSUSP) 3030 dwc_otg_suspend_irq(sc); 3031 else 3032 dwc_otg_resume_irq(sc); 3033 3034 /* complete root HUB interrupt endpoint */ 3035 dwc_otg_root_intr(sc); 3036 3037 /* update host frame interval */ 3038 dwc_otg_update_host_frame_interval(sc); 3039 } 3040 3041 /* 3042 * If resume and suspend is set at the same time we interpret 3043 * that like RESUME. Resume is set when there is at least 3 3044 * milliseconds of inactivity on the USB BUS. 3045 */ 3046 if (status & GINTSTS_WKUPINT) { 3047 3048 DPRINTFN(5, "resume interrupt\n"); 3049 3050 dwc_otg_resume_irq(sc); 3051 3052 } else if (status & GINTSTS_USBSUSP) { 3053 3054 DPRINTFN(5, "suspend interrupt\n"); 3055 3056 dwc_otg_suspend_irq(sc); 3057 } 3058 /* check VBUS */ 3059 if (status & (GINTSTS_USBSUSP | 3060 GINTSTS_USBRST | 3061 GINTMSK_OTGINTMSK | 3062 GINTSTS_SESSREQINT)) { 3063 uint32_t temp; 3064 3065 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3066 3067 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 3068 3069 dwc_otg_vbus_interrupt(sc, 3070 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3071 } 3072 3073 if (sc->sc_xfer_complete != 0) { 3074 sc->sc_xfer_complete = 0; 3075 3076 /* complete FIFOs, if any */ 3077 dwc_otg_interrupt_complete_locked(sc); 3078 } 3079 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3080 USB_BUS_UNLOCK(&sc->sc_bus); 3081} 3082 3083static void 3084dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 3085{ 3086 struct dwc_otg_td *td; 3087 3088 /* get current Transfer Descriptor */ 3089 td = temp->td_next; 3090 temp->td = td; 3091 3092 /* prepare for next TD */ 3093 temp->td_next = td->obj_next; 3094 3095 /* fill out the Transfer Descriptor */ 3096 td->func = temp->func; 3097 td->pc = temp->pc; 3098 td->offset = temp->offset; 3099 td->remainder = temp->len; 3100 td->tx_bytes = 0; 3101 td->error_any = 0; 3102 td->error_stall = 0; 3103 td->npkt = 0; 3104 td->did_stall = temp->did_stall; 3105 td->short_pkt = temp->short_pkt; 3106 td->alt_next = temp->setup_alt_next; 3107 td->set_toggle = 0; 3108 td->got_short = 0; 3109 td->did_nak = 0; 3110 td->channel[0] = DWC_OTG_MAX_CHANNELS; 3111 td->channel[1] = DWC_OTG_MAX_CHANNELS; 3112 td->channel[2] = DWC_OTG_MAX_CHANNELS; 3113 td->state = 0; 3114 td->errcnt = 0; 3115 td->tt_scheduled = 0; 3116 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 3117} 3118 3119static void 3120dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 3121{ 3122 struct dwc_otg_std_temp temp; 3123 struct dwc_otg_td *td; 3124 uint32_t x; 3125 uint8_t need_sync; 3126 uint8_t is_host; 3127 3128 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3129 xfer->address, UE_GET_ADDR(xfer->endpointno), 3130 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3131 3132 temp.max_frame_size = xfer->max_frame_size; 3133 3134 td = xfer->td_start[0]; 3135 xfer->td_transfer_first = td; 3136 xfer->td_transfer_cache = td; 3137 3138 /* setup temp */ 3139 3140 temp.pc = NULL; 3141 temp.td = NULL; 3142 temp.td_next = xfer->td_start[0]; 3143 temp.offset = 0; 3144 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3145 xfer->flags_int.isochronous_xfr; 3146 temp.did_stall = !xfer->flags_int.control_stall; 3147 3148 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3149 3150 /* check if we should prepend a setup message */ 3151 3152 if (xfer->flags_int.control_xfr) { 3153 if (xfer->flags_int.control_hdr) { 3154 3155 if (is_host) 3156 temp.func = &dwc_otg_host_setup_tx; 3157 else 3158 temp.func = &dwc_otg_setup_rx; 3159 3160 temp.len = xfer->frlengths[0]; 3161 temp.pc = xfer->frbuffers + 0; 3162 temp.short_pkt = temp.len ? 1 : 0; 3163 3164 /* check for last frame */ 3165 if (xfer->nframes == 1) { 3166 /* no STATUS stage yet, SETUP is last */ 3167 if (xfer->flags_int.control_act) 3168 temp.setup_alt_next = 0; 3169 } 3170 3171 dwc_otg_setup_standard_chain_sub(&temp); 3172 } 3173 x = 1; 3174 } else { 3175 x = 0; 3176 } 3177 3178 if (x != xfer->nframes) { 3179 if (xfer->endpointno & UE_DIR_IN) { 3180 if (is_host) { 3181 temp.func = &dwc_otg_host_data_rx; 3182 need_sync = 0; 3183 } else { 3184 temp.func = &dwc_otg_data_tx; 3185 need_sync = 1; 3186 } 3187 } else { 3188 if (is_host) { 3189 temp.func = &dwc_otg_host_data_tx; 3190 need_sync = 0; 3191 } else { 3192 temp.func = &dwc_otg_data_rx; 3193 need_sync = 0; 3194 } 3195 } 3196 3197 /* setup "pc" pointer */ 3198 temp.pc = xfer->frbuffers + x; 3199 } else { 3200 need_sync = 0; 3201 } 3202 while (x != xfer->nframes) { 3203 3204 /* DATA0 / DATA1 message */ 3205 3206 temp.len = xfer->frlengths[x]; 3207 3208 x++; 3209 3210 if (x == xfer->nframes) { 3211 if (xfer->flags_int.control_xfr) { 3212 if (xfer->flags_int.control_act) { 3213 temp.setup_alt_next = 0; 3214 } 3215 } else { 3216 temp.setup_alt_next = 0; 3217 } 3218 } 3219 if (temp.len == 0) { 3220 3221 /* make sure that we send an USB packet */ 3222 3223 temp.short_pkt = 0; 3224 3225 } else { 3226 3227 /* regular data transfer */ 3228 3229 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3230 } 3231 3232 dwc_otg_setup_standard_chain_sub(&temp); 3233 3234 if (xfer->flags_int.isochronous_xfr) { 3235 temp.offset += temp.len; 3236 } else { 3237 /* get next Page Cache pointer */ 3238 temp.pc = xfer->frbuffers + x; 3239 } 3240 } 3241 3242 if (xfer->flags_int.control_xfr) { 3243 3244 /* always setup a valid "pc" pointer for status and sync */ 3245 temp.pc = xfer->frbuffers + 0; 3246 temp.len = 0; 3247 temp.short_pkt = 0; 3248 temp.setup_alt_next = 0; 3249 3250 /* check if we need to sync */ 3251 if (need_sync) { 3252 /* we need a SYNC point after TX */ 3253 temp.func = &dwc_otg_data_tx_sync; 3254 dwc_otg_setup_standard_chain_sub(&temp); 3255 } 3256 3257 /* check if we should append a status stage */ 3258 if (!xfer->flags_int.control_act) { 3259 3260 /* 3261 * Send a DATA1 message and invert the current 3262 * endpoint direction. 3263 */ 3264 if (xfer->endpointno & UE_DIR_IN) { 3265 if (is_host) { 3266 temp.func = &dwc_otg_host_data_tx; 3267 need_sync = 0; 3268 } else { 3269 temp.func = &dwc_otg_data_rx; 3270 need_sync = 0; 3271 } 3272 } else { 3273 if (is_host) { 3274 temp.func = &dwc_otg_host_data_rx; 3275 need_sync = 0; 3276 } else { 3277 temp.func = &dwc_otg_data_tx; 3278 need_sync = 1; 3279 } 3280 } 3281 3282 dwc_otg_setup_standard_chain_sub(&temp); 3283 3284 /* data toggle should be DATA1 */ 3285 td = temp.td; 3286 td->set_toggle = 1; 3287 3288 if (need_sync) { 3289 /* we need a SYNC point after TX */ 3290 temp.func = &dwc_otg_data_tx_sync; 3291 dwc_otg_setup_standard_chain_sub(&temp); 3292 } 3293 } 3294 } else { 3295 /* check if we need to sync */ 3296 if (need_sync) { 3297 3298 temp.pc = xfer->frbuffers + 0; 3299 temp.len = 0; 3300 temp.short_pkt = 0; 3301 temp.setup_alt_next = 0; 3302 3303 /* we need a SYNC point after TX */ 3304 temp.func = &dwc_otg_data_tx_sync; 3305 dwc_otg_setup_standard_chain_sub(&temp); 3306 } 3307 } 3308 3309 /* must have at least one frame! */ 3310 td = temp.td; 3311 xfer->td_transfer_last = td; 3312 3313 if (is_host) { 3314 3315 struct dwc_otg_softc *sc; 3316 uint32_t hcchar; 3317 uint32_t hcsplt; 3318 3319 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3320 3321 /* get first again */ 3322 td = xfer->td_transfer_first; 3323 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3324 3325 hcchar = 3326 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3327 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3328 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3329 HCCHAR_CHENA; 3330 3331 /* 3332 * We are not always able to meet the timing 3333 * requirements of the USB interrupt endpoint's 3334 * complete split token, when doing transfers going 3335 * via a transaction translator. Use the CONTROL 3336 * transfer type instead of the INTERRUPT transfer 3337 * type in general, as a means to workaround 3338 * that. This trick should work for both FULL and LOW 3339 * speed USB traffic going through a TT. For non-TT 3340 * traffic it works as well. The reason for using 3341 * CONTROL type instead of BULK is that some TTs might 3342 * reject LOW speed BULK traffic. 3343 */ 3344 if (td->ep_type == UE_INTERRUPT) 3345 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3346 else 3347 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3348 3349 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3350 hcchar |= HCCHAR_EPDIR_IN; 3351 3352 switch (xfer->xroot->udev->speed) { 3353 case USB_SPEED_LOW: 3354 hcchar |= HCCHAR_LSPDDEV; 3355 /* FALLTHROUGH */ 3356 case USB_SPEED_FULL: 3357 /* check if root HUB port is running High Speed */ 3358 if (dwc_otg_uses_split(xfer->xroot->udev)) { 3359 hcsplt = HCSPLT_SPLTENA | 3360 (xfer->xroot->udev->hs_port_no << 3361 HCSPLT_PRTADDR_SHIFT) | 3362 (xfer->xroot->udev->hs_hub_addr << 3363 HCSPLT_HUBADDR_SHIFT); 3364 } else { 3365 hcsplt = 0; 3366 } 3367 if (td->ep_type == UE_INTERRUPT) { 3368 uint32_t ival; 3369 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3370 if (ival == 0) 3371 ival = 1; 3372 else if (ival > 127) 3373 ival = 127; 3374 td->tmr_val = sc->sc_tmr_val + ival; 3375 td->tmr_res = ival; 3376 } else if (td->ep_type == UE_ISOCHRONOUS) { 3377 td->tmr_res = 1; 3378 td->tmr_val = sc->sc_last_frame_num; 3379 if (td->hcchar & HCCHAR_EPDIR_IN) 3380 td->tmr_val++; 3381 } else { 3382 td->tmr_val = 0; 3383 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3384 } 3385 break; 3386 case USB_SPEED_HIGH: 3387 hcsplt = 0; 3388 if (td->ep_type == UE_INTERRUPT) { 3389 uint32_t ival; 3390 hcchar |= ((xfer->max_packet_count & 3) 3391 << HCCHAR_MC_SHIFT); 3392 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3393 if (ival == 0) 3394 ival = 1; 3395 else if (ival > 127) 3396 ival = 127; 3397 td->tmr_val = sc->sc_tmr_val + ival; 3398 td->tmr_res = ival; 3399 } else if (td->ep_type == UE_ISOCHRONOUS) { 3400 hcchar |= ((xfer->max_packet_count & 3) 3401 << HCCHAR_MC_SHIFT); 3402 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3403 td->tmr_val = sc->sc_last_frame_num; 3404 if (td->hcchar & HCCHAR_EPDIR_IN) 3405 td->tmr_val += td->tmr_res; 3406 3407 } else { 3408 td->tmr_val = 0; 3409 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3410 } 3411 break; 3412 default: 3413 hcsplt = 0; 3414 td->tmr_val = 0; 3415 td->tmr_res = 0; 3416 break; 3417 } 3418 3419 /* store configuration in all TD's */ 3420 while (1) { 3421 td->hcchar = hcchar; 3422 td->hcsplt = hcsplt; 3423 3424 if (((void *)td) == xfer->td_transfer_last) 3425 break; 3426 3427 td = td->obj_next; 3428 } 3429 } 3430} 3431 3432static void 3433dwc_otg_timeout(void *arg) 3434{ 3435 struct usb_xfer *xfer = arg; 3436 3437 DPRINTF("xfer=%p\n", xfer); 3438 3439 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3440 3441 /* transfer is transferred */ 3442 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3443} 3444 3445static void 3446dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3447{ 3448 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3449 3450 DPRINTFN(9, "\n"); 3451 3452 /* 3453 * Poll one time in device mode, which will turn on the 3454 * endpoint interrupts. Else wait for SOF interrupt in host 3455 * mode. 3456 */ 3457 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3458 3459 if (sc->sc_flags.status_device_mode != 0) { 3460 dwc_otg_xfer_do_fifo(sc, xfer); 3461 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3462 goto done; 3463 } else { 3464 struct dwc_otg_td *td = xfer->td_transfer_cache; 3465 if (td->ep_type == UE_ISOCHRONOUS && 3466 (td->hcchar & HCCHAR_EPDIR_IN) == 0) { 3467 /* 3468 * Need to start ISOCHRONOUS OUT transfer ASAP 3469 * because execution is delayed by one 125us 3470 * microframe: 3471 */ 3472 dwc_otg_xfer_do_fifo(sc, xfer); 3473 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3474 goto done; 3475 } 3476 } 3477 3478 /* put transfer on interrupt queue */ 3479 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3480 3481 /* start timeout, if any */ 3482 if (xfer->timeout != 0) { 3483 usbd_transfer_timeout_ms(xfer, 3484 &dwc_otg_timeout, xfer->timeout); 3485 } 3486 3487 if (sc->sc_flags.status_device_mode != 0) 3488 goto done; 3489 3490 /* enable SOF interrupt, if any */ 3491 dwc_otg_enable_sof_irq(sc); 3492done: 3493 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3494} 3495 3496static void 3497dwc_otg_root_intr(struct dwc_otg_softc *sc) 3498{ 3499 DPRINTFN(9, "\n"); 3500 3501 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3502 3503 /* set port bit */ 3504 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3505 3506 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3507 sizeof(sc->sc_hub_idata)); 3508} 3509 3510static usb_error_t 3511dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3512{ 3513 struct dwc_otg_td *td; 3514 uint32_t len; 3515 usb_error_t error; 3516 3517 DPRINTFN(9, "\n"); 3518 3519 td = xfer->td_transfer_cache; 3520 3521 do { 3522 len = td->remainder; 3523 3524 /* store last data toggle */ 3525 xfer->endpoint->toggle_next = td->toggle; 3526 3527 if (xfer->aframes != xfer->nframes) { 3528 /* 3529 * Verify the length and subtract 3530 * the remainder from "frlengths[]": 3531 */ 3532 if (len > xfer->frlengths[xfer->aframes]) { 3533 td->error_any = 1; 3534 } else { 3535 xfer->frlengths[xfer->aframes] -= len; 3536 } 3537 } 3538 /* Check for transfer error */ 3539 if (td->error_any) { 3540 /* the transfer is finished */ 3541 error = (td->error_stall ? 3542 USB_ERR_STALLED : USB_ERR_IOERROR); 3543 td = NULL; 3544 break; 3545 } 3546 /* Check for short transfer */ 3547 if (len > 0) { 3548 if (xfer->flags_int.short_frames_ok || 3549 xfer->flags_int.isochronous_xfr) { 3550 /* follow alt next */ 3551 if (td->alt_next) { 3552 td = td->obj_next; 3553 } else { 3554 td = NULL; 3555 } 3556 } else { 3557 /* the transfer is finished */ 3558 td = NULL; 3559 } 3560 error = 0; 3561 break; 3562 } 3563 td = td->obj_next; 3564 3565 /* this USB frame is complete */ 3566 error = 0; 3567 break; 3568 3569 } while (0); 3570 3571 /* update transfer cache */ 3572 3573 xfer->td_transfer_cache = td; 3574 3575 return (error); 3576} 3577 3578static void 3579dwc_otg_standard_done(struct usb_xfer *xfer) 3580{ 3581 usb_error_t err = 0; 3582 3583 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3584 xfer, xfer->endpoint); 3585 3586 /* reset scanner */ 3587 3588 xfer->td_transfer_cache = xfer->td_transfer_first; 3589 3590 if (xfer->flags_int.control_xfr) { 3591 3592 if (xfer->flags_int.control_hdr) { 3593 3594 err = dwc_otg_standard_done_sub(xfer); 3595 } 3596 xfer->aframes = 1; 3597 3598 if (xfer->td_transfer_cache == NULL) { 3599 goto done; 3600 } 3601 } 3602 while (xfer->aframes != xfer->nframes) { 3603 3604 err = dwc_otg_standard_done_sub(xfer); 3605 xfer->aframes++; 3606 3607 if (xfer->td_transfer_cache == NULL) { 3608 goto done; 3609 } 3610 } 3611 3612 if (xfer->flags_int.control_xfr && 3613 !xfer->flags_int.control_act) { 3614 3615 err = dwc_otg_standard_done_sub(xfer); 3616 } 3617done: 3618 dwc_otg_device_done(xfer, err); 3619} 3620 3621/*------------------------------------------------------------------------* 3622 * dwc_otg_device_done 3623 * 3624 * NOTE: this function can be called more than one time on the 3625 * same USB transfer! 3626 *------------------------------------------------------------------------*/ 3627static void 3628dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3629{ 3630 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3631 3632 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3633 xfer, xfer->endpoint, error); 3634 3635 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3636 3637 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3638 /* Interrupts are cleared by the interrupt handler */ 3639 } else { 3640 struct dwc_otg_td *td; 3641 3642 td = xfer->td_transfer_cache; 3643 if (td != NULL) 3644 dwc_otg_host_channel_free(sc, td); 3645 } 3646 /* dequeue transfer and start next transfer */ 3647 usbd_transfer_done(xfer, error); 3648 3649 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3650} 3651 3652static void 3653dwc_otg_xfer_stall(struct usb_xfer *xfer) 3654{ 3655 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3656} 3657 3658static void 3659dwc_otg_set_stall(struct usb_device *udev, 3660 struct usb_endpoint *ep, uint8_t *did_stall) 3661{ 3662 struct dwc_otg_softc *sc; 3663 uint32_t temp; 3664 uint32_t reg; 3665 uint8_t ep_no; 3666 3667 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3668 3669 /* check mode */ 3670 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3671 /* not supported */ 3672 return; 3673 } 3674 3675 sc = DWC_OTG_BUS2SC(udev->bus); 3676 3677 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3678 3679 /* get endpoint address */ 3680 ep_no = ep->edesc->bEndpointAddress; 3681 3682 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3683 3684 if (ep_no & UE_DIR_IN) { 3685 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3686 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3687 } else { 3688 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3689 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3690 } 3691 3692 /* disable and stall endpoint */ 3693 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3694 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3695 3696 /* clear active OUT ep */ 3697 if (!(ep_no & UE_DIR_IN)) { 3698 3699 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3700 3701 if (sc->sc_last_rx_status != 0 && 3702 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3703 sc->sc_last_rx_status)) { 3704 /* dump data */ 3705 dwc_otg_common_rx_ack(sc); 3706 /* poll interrupt */ 3707 dwc_otg_interrupt_poll_locked(sc); 3708 dwc_otg_interrupt_complete_locked(sc); 3709 } 3710 } 3711 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3712} 3713 3714static void 3715dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3716 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3717{ 3718 uint32_t reg; 3719 uint32_t temp; 3720 3721 if (ep_type == UE_CONTROL) { 3722 /* clearing stall is not needed */ 3723 return; 3724 } 3725 3726 if (ep_dir) { 3727 reg = DOTG_DIEPCTL(ep_no); 3728 } else { 3729 reg = DOTG_DOEPCTL(ep_no); 3730 sc->sc_active_rx_ep |= (1U << ep_no); 3731 } 3732 3733 /* round up and mask away the multiplier count */ 3734 mps = (mps + 3) & 0x7FC; 3735 3736 if (ep_type == UE_BULK) { 3737 temp = DIEPCTL_EPTYPE_SET( 3738 DIEPCTL_EPTYPE_BULK) | 3739 DIEPCTL_USBACTEP; 3740 } else if (ep_type == UE_INTERRUPT) { 3741 temp = DIEPCTL_EPTYPE_SET( 3742 DIEPCTL_EPTYPE_INTERRUPT) | 3743 DIEPCTL_USBACTEP; 3744 } else { 3745 temp = DIEPCTL_EPTYPE_SET( 3746 DIEPCTL_EPTYPE_ISOC) | 3747 DIEPCTL_USBACTEP; 3748 } 3749 3750 temp |= DIEPCTL_MPS_SET(mps); 3751 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3752 3753 if (ep_dir) 3754 sc->sc_in_ctl[ep_no] = temp; 3755 else 3756 sc->sc_out_ctl[ep_no] = temp; 3757 3758 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3759 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3760 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3761 3762 /* we only reset the transmit FIFO */ 3763 if (ep_dir) { 3764 dwc_otg_tx_fifo_reset(sc, 3765 GRSTCTL_TXFIFO(ep_no) | 3766 GRSTCTL_TXFFLSH); 3767 3768 DWC_OTG_WRITE_4(sc, 3769 DOTG_DIEPTSIZ(ep_no), 0); 3770 } 3771 3772 /* poll interrupt */ 3773 dwc_otg_interrupt_poll_locked(sc); 3774 dwc_otg_interrupt_complete_locked(sc); 3775} 3776 3777static void 3778dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3779{ 3780 struct dwc_otg_softc *sc; 3781 struct usb_endpoint_descriptor *ed; 3782 3783 DPRINTFN(5, "endpoint=%p\n", ep); 3784 3785 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3786 3787 /* check mode */ 3788 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3789 /* not supported */ 3790 return; 3791 } 3792 /* get softc */ 3793 sc = DWC_OTG_BUS2SC(udev->bus); 3794 3795 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3796 3797 /* get endpoint descriptor */ 3798 ed = ep->edesc; 3799 3800 /* reset endpoint */ 3801 dwc_otg_clear_stall_sub_locked(sc, 3802 UGETW(ed->wMaxPacketSize), 3803 (ed->bEndpointAddress & UE_ADDR), 3804 (ed->bmAttributes & UE_XFERTYPE), 3805 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3806 3807 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3808} 3809 3810static void 3811dwc_otg_device_state_change(struct usb_device *udev) 3812{ 3813 struct dwc_otg_softc *sc; 3814 uint8_t x; 3815 3816 /* check mode */ 3817 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3818 /* not supported */ 3819 return; 3820 } 3821 3822 /* get softc */ 3823 sc = DWC_OTG_BUS2SC(udev->bus); 3824 3825 /* deactivate all other endpoint but the control endpoint */ 3826 if (udev->state == USB_STATE_CONFIGURED || 3827 udev->state == USB_STATE_ADDRESSED) { 3828 3829 USB_BUS_LOCK(&sc->sc_bus); 3830 3831 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3832 3833 if (x < sc->sc_dev_in_ep_max) { 3834 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3835 DIEPCTL_EPDIS); 3836 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3837 } 3838 3839 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3840 DOEPCTL_EPDIS); 3841 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3842 } 3843 USB_BUS_UNLOCK(&sc->sc_bus); 3844 } 3845} 3846 3847int 3848dwc_otg_init(struct dwc_otg_softc *sc) 3849{ 3850 uint32_t temp; 3851 3852 DPRINTF("start\n"); 3853 3854 /* set up the bus structure */ 3855 sc->sc_bus.usbrev = USB_REV_2_0; 3856 sc->sc_bus.methods = &dwc_otg_bus_methods; 3857 3858 usb_callout_init_mtx(&sc->sc_timer, 3859 &sc->sc_bus.bus_mtx, 0); 3860 3861 USB_BUS_LOCK(&sc->sc_bus); 3862 3863 /* turn on clocks */ 3864 dwc_otg_clocks_on(sc); 3865 3866 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3867 DPRINTF("Version = 0x%08x\n", temp); 3868 3869 /* disconnect */ 3870 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3871 DCTL_SFTDISCON); 3872 3873 /* wait for host to detect disconnect */ 3874 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3875 3876 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3877 GRSTCTL_CSFTRST); 3878 3879 /* wait a little bit for block to reset */ 3880 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3881 3882 switch (sc->sc_mode) { 3883 case DWC_MODE_DEVICE: 3884 temp = GUSBCFG_FORCEDEVMODE; 3885 break; 3886 case DWC_MODE_HOST: 3887 temp = GUSBCFG_FORCEHOSTMODE; 3888 break; 3889 default: 3890 temp = 0; 3891 break; 3892 } 3893 3894 /* select HSIC, ULPI or internal PHY mode */ 3895 switch (dwc_otg_phy_type) { 3896 case DWC_OTG_PHY_HSIC: 3897 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3898 GUSBCFG_PHYIF | 3899 GUSBCFG_TRD_TIM_SET(5) | temp); 3900 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3901 0x000000EC); 3902 3903 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3904 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3905 temp & ~GLPMCFG_HSIC_CONN); 3906 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3907 temp | GLPMCFG_HSIC_CONN); 3908 break; 3909 case DWC_OTG_PHY_ULPI: 3910 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3911 GUSBCFG_ULPI_UTMI_SEL | 3912 GUSBCFG_TRD_TIM_SET(5) | temp); 3913 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3914 3915 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3916 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3917 temp & ~GLPMCFG_HSIC_CONN); 3918 break; 3919 case DWC_OTG_PHY_INTERNAL: 3920 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3921 GUSBCFG_PHYSEL | 3922 GUSBCFG_TRD_TIM_SET(5) | temp); 3923 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3924 3925 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3926 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3927 temp & ~GLPMCFG_HSIC_CONN); 3928 3929 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3930 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3931 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3932 DOTG_GGPIO_PWRDWN); 3933 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3934 break; 3935 default: 3936 break; 3937 } 3938 3939 /* clear global nak */ 3940 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3941 DCTL_CGOUTNAK | 3942 DCTL_CGNPINNAK); 3943 3944 /* disable USB port */ 3945 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3946 3947 /* wait 10ms */ 3948 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3949 3950 /* enable USB port */ 3951 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3952 3953 /* wait 10ms */ 3954 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3955 3956 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3957 3958 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3959 3960 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3961 3962 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3963 3964 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3965 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3966 3967 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3968 3969 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3970 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3971 3972 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3973 3974 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3975 3976 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3977 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3978 sc->sc_host_ch_max); 3979 3980 /* setup FIFO */ 3981 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3982 USB_BUS_UNLOCK(&sc->sc_bus); 3983 return (EINVAL); 3984 } 3985 3986 /* enable interrupts */ 3987 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ; 3988 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3989 3990 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3991 3992 /* enable all endpoint interrupts */ 3993 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3994 if (temp & GHWCFG2_MPI) { 3995 uint8_t x; 3996 3997 DPRINTF("Disable Multi Process Interrupts\n"); 3998 3999 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 4000 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 4001 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 4002 } 4003 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 4004 } 4005 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 4006 DIEPMSK_XFERCOMPLMSK); 4007 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 4008 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 4009 } 4010 4011 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 4012 /* setup clocks */ 4013 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 4014 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 4015 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 4016 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 4017 } 4018 4019 /* only enable global IRQ */ 4020 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 4021 GAHBCFG_GLBLINTRMSK); 4022 4023 /* turn off clocks */ 4024 dwc_otg_clocks_off(sc); 4025 4026 /* read initial VBUS state */ 4027 4028 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 4029 4030 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 4031 4032 dwc_otg_vbus_interrupt(sc, 4033 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 4034 4035 USB_BUS_UNLOCK(&sc->sc_bus); 4036 4037 /* catch any lost interrupts */ 4038 4039 dwc_otg_do_poll(&sc->sc_bus); 4040 4041 return (0); /* success */ 4042} 4043 4044void 4045dwc_otg_uninit(struct dwc_otg_softc *sc) 4046{ 4047 USB_BUS_LOCK(&sc->sc_bus); 4048 4049 /* stop host timer */ 4050 dwc_otg_timer_stop(sc); 4051 4052 /* set disconnect */ 4053 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 4054 DCTL_SFTDISCON); 4055 4056 /* turn off global IRQ */ 4057 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 4058 4059 sc->sc_flags.port_enabled = 0; 4060 sc->sc_flags.port_powered = 0; 4061 sc->sc_flags.status_vbus = 0; 4062 sc->sc_flags.status_bus_reset = 0; 4063 sc->sc_flags.status_suspend = 0; 4064 sc->sc_flags.change_suspend = 0; 4065 sc->sc_flags.change_connect = 1; 4066 4067 dwc_otg_pull_down(sc); 4068 dwc_otg_clocks_off(sc); 4069 4070 USB_BUS_UNLOCK(&sc->sc_bus); 4071 4072 usb_callout_drain(&sc->sc_timer); 4073} 4074 4075static void 4076dwc_otg_suspend(struct dwc_otg_softc *sc) 4077{ 4078 return; 4079} 4080 4081static void 4082dwc_otg_resume(struct dwc_otg_softc *sc) 4083{ 4084 return; 4085} 4086 4087static void 4088dwc_otg_do_poll(struct usb_bus *bus) 4089{ 4090 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4091 4092 USB_BUS_LOCK(&sc->sc_bus); 4093 USB_BUS_SPIN_LOCK(&sc->sc_bus); 4094 dwc_otg_interrupt_poll_locked(sc); 4095 dwc_otg_interrupt_complete_locked(sc); 4096 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 4097 USB_BUS_UNLOCK(&sc->sc_bus); 4098} 4099 4100/*------------------------------------------------------------------------* 4101 * DWC OTG bulk support 4102 * DWC OTG control support 4103 * DWC OTG interrupt support 4104 *------------------------------------------------------------------------*/ 4105static void 4106dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 4107{ 4108} 4109 4110static void 4111dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 4112{ 4113 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4114} 4115 4116static void 4117dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 4118{ 4119} 4120 4121static void 4122dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 4123{ 4124 /* setup TDs */ 4125 dwc_otg_setup_standard_chain(xfer); 4126 dwc_otg_start_standard_chain(xfer); 4127} 4128 4129static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4130{ 4131 .open = dwc_otg_device_non_isoc_open, 4132 .close = dwc_otg_device_non_isoc_close, 4133 .enter = dwc_otg_device_non_isoc_enter, 4134 .start = dwc_otg_device_non_isoc_start, 4135}; 4136 4137/*------------------------------------------------------------------------* 4138 * DWC OTG full speed isochronous support 4139 *------------------------------------------------------------------------*/ 4140static void 4141dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4142{ 4143} 4144 4145static void 4146dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4147{ 4148 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4149} 4150 4151static void 4152dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4153{ 4154} 4155 4156static void 4157dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4158{ 4159 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4160 uint32_t temp; 4161 uint32_t msframes; 4162 uint32_t framenum; 4163 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4164 4165 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4166 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4167 4168 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4169 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4170 4171 /* get the current frame index */ 4172 framenum = (temp & HFNUM_FRNUM_MASK); 4173 } else { 4174 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4175 4176 /* get the current frame index */ 4177 framenum = DSTS_SOFFN_GET(temp); 4178 } 4179 4180 /* 4181 * Check if port is doing 8000 or 1000 frames per second: 4182 */ 4183 if (sc->sc_flags.status_high_speed) 4184 framenum /= 8; 4185 4186 framenum &= DWC_OTG_FRAME_MASK; 4187 4188 /* 4189 * Compute number of milliseconds worth of data traffic for 4190 * this USB transfer: 4191 */ 4192 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4193 msframes = ((xfer->nframes << shift) + 7) / 8; 4194 else 4195 msframes = xfer->nframes; 4196 4197 /* 4198 * check if the frame index is within the window where the frames 4199 * will be inserted 4200 */ 4201 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4202 4203 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4204 /* 4205 * If there is data underflow or the pipe queue is 4206 * empty we schedule the transfer a few frames ahead 4207 * of the current frame position. Else two isochronous 4208 * transfers might overlap. 4209 */ 4210 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4211 xfer->endpoint->is_synced = 1; 4212 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4213 } 4214 /* 4215 * compute how many milliseconds the insertion is ahead of the 4216 * current frame position: 4217 */ 4218 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4219 4220 /* 4221 * pre-compute when the isochronous transfer will be finished: 4222 */ 4223 xfer->isoc_time_complete = 4224 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4225 4226 /* setup TDs */ 4227 dwc_otg_setup_standard_chain(xfer); 4228 4229 /* compute frame number for next insertion */ 4230 xfer->endpoint->isoc_next += msframes; 4231 4232 /* start TD chain */ 4233 dwc_otg_start_standard_chain(xfer); 4234} 4235 4236static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4237{ 4238 .open = dwc_otg_device_isoc_open, 4239 .close = dwc_otg_device_isoc_close, 4240 .enter = dwc_otg_device_isoc_enter, 4241 .start = dwc_otg_device_isoc_start, 4242}; 4243 4244/*------------------------------------------------------------------------* 4245 * DWC OTG root control support 4246 *------------------------------------------------------------------------* 4247 * Simulate a hardware HUB by handling all the necessary requests. 4248 *------------------------------------------------------------------------*/ 4249 4250static const struct usb_device_descriptor dwc_otg_devd = { 4251 .bLength = sizeof(struct usb_device_descriptor), 4252 .bDescriptorType = UDESC_DEVICE, 4253 .bcdUSB = {0x00, 0x02}, 4254 .bDeviceClass = UDCLASS_HUB, 4255 .bDeviceSubClass = UDSUBCLASS_HUB, 4256 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4257 .bMaxPacketSize = 64, 4258 .bcdDevice = {0x00, 0x01}, 4259 .iManufacturer = 1, 4260 .iProduct = 2, 4261 .bNumConfigurations = 1, 4262}; 4263 4264static const struct dwc_otg_config_desc dwc_otg_confd = { 4265 .confd = { 4266 .bLength = sizeof(struct usb_config_descriptor), 4267 .bDescriptorType = UDESC_CONFIG, 4268 .wTotalLength[0] = sizeof(dwc_otg_confd), 4269 .bNumInterface = 1, 4270 .bConfigurationValue = 1, 4271 .iConfiguration = 0, 4272 .bmAttributes = UC_SELF_POWERED, 4273 .bMaxPower = 0, 4274 }, 4275 .ifcd = { 4276 .bLength = sizeof(struct usb_interface_descriptor), 4277 .bDescriptorType = UDESC_INTERFACE, 4278 .bNumEndpoints = 1, 4279 .bInterfaceClass = UICLASS_HUB, 4280 .bInterfaceSubClass = UISUBCLASS_HUB, 4281 .bInterfaceProtocol = 0, 4282 }, 4283 .endpd = { 4284 .bLength = sizeof(struct usb_endpoint_descriptor), 4285 .bDescriptorType = UDESC_ENDPOINT, 4286 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4287 .bmAttributes = UE_INTERRUPT, 4288 .wMaxPacketSize[0] = 8, 4289 .bInterval = 255, 4290 }, 4291}; 4292 4293#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4294 4295static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4296 .bDescLength = sizeof(dwc_otg_hubd), 4297 .bDescriptorType = UDESC_HUB, 4298 .bNbrPorts = 1, 4299 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4300 .bPwrOn2PwrGood = 50, 4301 .bHubContrCurrent = 0, 4302 .DeviceRemovable = {0}, /* port is removable */ 4303}; 4304 4305#define STRING_VENDOR \ 4306 "D\0W\0C\0O\0T\0G" 4307 4308#define STRING_PRODUCT \ 4309 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4310 4311USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4312USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4313 4314static usb_error_t 4315dwc_otg_roothub_exec(struct usb_device *udev, 4316 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4317{ 4318 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4319 const void *ptr; 4320 uint16_t len; 4321 uint16_t value; 4322 uint16_t index; 4323 usb_error_t err; 4324 4325 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4326 4327 /* buffer reset */ 4328 ptr = (const void *)&sc->sc_hub_temp; 4329 len = 0; 4330 err = 0; 4331 4332 value = UGETW(req->wValue); 4333 index = UGETW(req->wIndex); 4334 4335 /* demultiplex the control request */ 4336 4337 switch (req->bmRequestType) { 4338 case UT_READ_DEVICE: 4339 switch (req->bRequest) { 4340 case UR_GET_DESCRIPTOR: 4341 goto tr_handle_get_descriptor; 4342 case UR_GET_CONFIG: 4343 goto tr_handle_get_config; 4344 case UR_GET_STATUS: 4345 goto tr_handle_get_status; 4346 default: 4347 goto tr_stalled; 4348 } 4349 break; 4350 4351 case UT_WRITE_DEVICE: 4352 switch (req->bRequest) { 4353 case UR_SET_ADDRESS: 4354 goto tr_handle_set_address; 4355 case UR_SET_CONFIG: 4356 goto tr_handle_set_config; 4357 case UR_CLEAR_FEATURE: 4358 goto tr_valid; /* nop */ 4359 case UR_SET_DESCRIPTOR: 4360 goto tr_valid; /* nop */ 4361 case UR_SET_FEATURE: 4362 default: 4363 goto tr_stalled; 4364 } 4365 break; 4366 4367 case UT_WRITE_ENDPOINT: 4368 switch (req->bRequest) { 4369 case UR_CLEAR_FEATURE: 4370 switch (UGETW(req->wValue)) { 4371 case UF_ENDPOINT_HALT: 4372 goto tr_handle_clear_halt; 4373 case UF_DEVICE_REMOTE_WAKEUP: 4374 goto tr_handle_clear_wakeup; 4375 default: 4376 goto tr_stalled; 4377 } 4378 break; 4379 case UR_SET_FEATURE: 4380 switch (UGETW(req->wValue)) { 4381 case UF_ENDPOINT_HALT: 4382 goto tr_handle_set_halt; 4383 case UF_DEVICE_REMOTE_WAKEUP: 4384 goto tr_handle_set_wakeup; 4385 default: 4386 goto tr_stalled; 4387 } 4388 break; 4389 case UR_SYNCH_FRAME: 4390 goto tr_valid; /* nop */ 4391 default: 4392 goto tr_stalled; 4393 } 4394 break; 4395 4396 case UT_READ_ENDPOINT: 4397 switch (req->bRequest) { 4398 case UR_GET_STATUS: 4399 goto tr_handle_get_ep_status; 4400 default: 4401 goto tr_stalled; 4402 } 4403 break; 4404 4405 case UT_WRITE_INTERFACE: 4406 switch (req->bRequest) { 4407 case UR_SET_INTERFACE: 4408 goto tr_handle_set_interface; 4409 case UR_CLEAR_FEATURE: 4410 goto tr_valid; /* nop */ 4411 case UR_SET_FEATURE: 4412 default: 4413 goto tr_stalled; 4414 } 4415 break; 4416 4417 case UT_READ_INTERFACE: 4418 switch (req->bRequest) { 4419 case UR_GET_INTERFACE: 4420 goto tr_handle_get_interface; 4421 case UR_GET_STATUS: 4422 goto tr_handle_get_iface_status; 4423 default: 4424 goto tr_stalled; 4425 } 4426 break; 4427 4428 case UT_WRITE_CLASS_INTERFACE: 4429 case UT_WRITE_VENDOR_INTERFACE: 4430 /* XXX forward */ 4431 break; 4432 4433 case UT_READ_CLASS_INTERFACE: 4434 case UT_READ_VENDOR_INTERFACE: 4435 /* XXX forward */ 4436 break; 4437 4438 case UT_WRITE_CLASS_DEVICE: 4439 switch (req->bRequest) { 4440 case UR_CLEAR_FEATURE: 4441 goto tr_valid; 4442 case UR_SET_DESCRIPTOR: 4443 case UR_SET_FEATURE: 4444 break; 4445 default: 4446 goto tr_stalled; 4447 } 4448 break; 4449 4450 case UT_WRITE_CLASS_OTHER: 4451 switch (req->bRequest) { 4452 case UR_CLEAR_FEATURE: 4453 goto tr_handle_clear_port_feature; 4454 case UR_SET_FEATURE: 4455 goto tr_handle_set_port_feature; 4456 case UR_CLEAR_TT_BUFFER: 4457 case UR_RESET_TT: 4458 case UR_STOP_TT: 4459 goto tr_valid; 4460 4461 default: 4462 goto tr_stalled; 4463 } 4464 break; 4465 4466 case UT_READ_CLASS_OTHER: 4467 switch (req->bRequest) { 4468 case UR_GET_TT_STATE: 4469 goto tr_handle_get_tt_state; 4470 case UR_GET_STATUS: 4471 goto tr_handle_get_port_status; 4472 default: 4473 goto tr_stalled; 4474 } 4475 break; 4476 4477 case UT_READ_CLASS_DEVICE: 4478 switch (req->bRequest) { 4479 case UR_GET_DESCRIPTOR: 4480 goto tr_handle_get_class_descriptor; 4481 case UR_GET_STATUS: 4482 goto tr_handle_get_class_status; 4483 4484 default: 4485 goto tr_stalled; 4486 } 4487 break; 4488 default: 4489 goto tr_stalled; 4490 } 4491 goto tr_valid; 4492 4493tr_handle_get_descriptor: 4494 switch (value >> 8) { 4495 case UDESC_DEVICE: 4496 if (value & 0xff) { 4497 goto tr_stalled; 4498 } 4499 len = sizeof(dwc_otg_devd); 4500 ptr = (const void *)&dwc_otg_devd; 4501 goto tr_valid; 4502 case UDESC_CONFIG: 4503 if (value & 0xff) { 4504 goto tr_stalled; 4505 } 4506 len = sizeof(dwc_otg_confd); 4507 ptr = (const void *)&dwc_otg_confd; 4508 goto tr_valid; 4509 case UDESC_STRING: 4510 switch (value & 0xff) { 4511 case 0: /* Language table */ 4512 len = sizeof(usb_string_lang_en); 4513 ptr = (const void *)&usb_string_lang_en; 4514 goto tr_valid; 4515 4516 case 1: /* Vendor */ 4517 len = sizeof(dwc_otg_vendor); 4518 ptr = (const void *)&dwc_otg_vendor; 4519 goto tr_valid; 4520 4521 case 2: /* Product */ 4522 len = sizeof(dwc_otg_product); 4523 ptr = (const void *)&dwc_otg_product; 4524 goto tr_valid; 4525 default: 4526 break; 4527 } 4528 break; 4529 default: 4530 goto tr_stalled; 4531 } 4532 goto tr_stalled; 4533 4534tr_handle_get_config: 4535 len = 1; 4536 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4537 goto tr_valid; 4538 4539tr_handle_get_status: 4540 len = 2; 4541 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4542 goto tr_valid; 4543 4544tr_handle_set_address: 4545 if (value & 0xFF00) { 4546 goto tr_stalled; 4547 } 4548 sc->sc_rt_addr = value; 4549 goto tr_valid; 4550 4551tr_handle_set_config: 4552 if (value >= 2) { 4553 goto tr_stalled; 4554 } 4555 sc->sc_conf = value; 4556 goto tr_valid; 4557 4558tr_handle_get_interface: 4559 len = 1; 4560 sc->sc_hub_temp.wValue[0] = 0; 4561 goto tr_valid; 4562 4563tr_handle_get_tt_state: 4564tr_handle_get_class_status: 4565tr_handle_get_iface_status: 4566tr_handle_get_ep_status: 4567 len = 2; 4568 USETW(sc->sc_hub_temp.wValue, 0); 4569 goto tr_valid; 4570 4571tr_handle_set_halt: 4572tr_handle_set_interface: 4573tr_handle_set_wakeup: 4574tr_handle_clear_wakeup: 4575tr_handle_clear_halt: 4576 goto tr_valid; 4577 4578tr_handle_clear_port_feature: 4579 if (index != 1) 4580 goto tr_stalled; 4581 4582 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4583 4584 switch (value) { 4585 case UHF_PORT_SUSPEND: 4586 dwc_otg_wakeup_peer(sc); 4587 break; 4588 4589 case UHF_PORT_ENABLE: 4590 if (sc->sc_flags.status_device_mode == 0) { 4591 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4592 sc->sc_hprt_val | HPRT_PRTENA); 4593 } 4594 sc->sc_flags.port_enabled = 0; 4595 break; 4596 4597 case UHF_C_PORT_RESET: 4598 sc->sc_flags.change_reset = 0; 4599 break; 4600 4601 case UHF_C_PORT_ENABLE: 4602 sc->sc_flags.change_enabled = 0; 4603 break; 4604 4605 case UHF_C_PORT_OVER_CURRENT: 4606 sc->sc_flags.change_over_current = 0; 4607 break; 4608 4609 case UHF_PORT_TEST: 4610 case UHF_PORT_INDICATOR: 4611 /* nops */ 4612 break; 4613 4614 case UHF_PORT_POWER: 4615 sc->sc_flags.port_powered = 0; 4616 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4617 sc->sc_hprt_val = 0; 4618 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4619 } 4620 dwc_otg_pull_down(sc); 4621 dwc_otg_clocks_off(sc); 4622 break; 4623 4624 case UHF_C_PORT_CONNECTION: 4625 /* clear connect change flag */ 4626 sc->sc_flags.change_connect = 0; 4627 break; 4628 4629 case UHF_C_PORT_SUSPEND: 4630 sc->sc_flags.change_suspend = 0; 4631 break; 4632 4633 default: 4634 err = USB_ERR_IOERROR; 4635 goto done; 4636 } 4637 goto tr_valid; 4638 4639tr_handle_set_port_feature: 4640 if (index != 1) { 4641 goto tr_stalled; 4642 } 4643 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4644 4645 switch (value) { 4646 case UHF_PORT_ENABLE: 4647 break; 4648 4649 case UHF_PORT_SUSPEND: 4650 if (sc->sc_flags.status_device_mode == 0) { 4651 /* set suspend BIT */ 4652 sc->sc_hprt_val |= HPRT_PRTSUSP; 4653 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4654 4655 /* generate HUB suspend event */ 4656 dwc_otg_suspend_irq(sc); 4657 } 4658 break; 4659 4660 case UHF_PORT_RESET: 4661 if (sc->sc_flags.status_device_mode == 0) { 4662 4663 DPRINTF("PORT RESET\n"); 4664 4665 /* enable PORT reset */ 4666 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4667 4668 /* Wait 62.5ms for reset to complete */ 4669 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4670 4671 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4672 4673 /* Wait 62.5ms for reset to complete */ 4674 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4675 4676 /* reset FIFOs */ 4677 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4678 4679 sc->sc_flags.change_reset = 1; 4680 } else { 4681 err = USB_ERR_IOERROR; 4682 } 4683 break; 4684 4685 case UHF_PORT_TEST: 4686 case UHF_PORT_INDICATOR: 4687 /* nops */ 4688 break; 4689 case UHF_PORT_POWER: 4690 sc->sc_flags.port_powered = 1; 4691 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4692 sc->sc_hprt_val |= HPRT_PRTPWR; 4693 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4694 } 4695 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4696 /* pull up D+, if any */ 4697 dwc_otg_pull_up(sc); 4698 } 4699 break; 4700 default: 4701 err = USB_ERR_IOERROR; 4702 goto done; 4703 } 4704 goto tr_valid; 4705 4706tr_handle_get_port_status: 4707 4708 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4709 4710 if (index != 1) 4711 goto tr_stalled; 4712 4713 if (sc->sc_flags.status_vbus) 4714 dwc_otg_clocks_on(sc); 4715 else 4716 dwc_otg_clocks_off(sc); 4717 4718 /* Select Device Side Mode */ 4719 4720 if (sc->sc_flags.status_device_mode) { 4721 value = UPS_PORT_MODE_DEVICE; 4722 dwc_otg_timer_stop(sc); 4723 } else { 4724 value = 0; 4725 dwc_otg_timer_start(sc); 4726 } 4727 4728 if (sc->sc_flags.status_high_speed) 4729 value |= UPS_HIGH_SPEED; 4730 else if (sc->sc_flags.status_low_speed) 4731 value |= UPS_LOW_SPEED; 4732 4733 if (sc->sc_flags.port_powered) 4734 value |= UPS_PORT_POWER; 4735 4736 if (sc->sc_flags.port_enabled) 4737 value |= UPS_PORT_ENABLED; 4738 4739 if (sc->sc_flags.port_over_current) 4740 value |= UPS_OVERCURRENT_INDICATOR; 4741 4742 if (sc->sc_flags.status_vbus && 4743 sc->sc_flags.status_bus_reset) 4744 value |= UPS_CURRENT_CONNECT_STATUS; 4745 4746 if (sc->sc_flags.status_suspend) 4747 value |= UPS_SUSPEND; 4748 4749 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4750 4751 value = 0; 4752 4753 if (sc->sc_flags.change_enabled) 4754 value |= UPS_C_PORT_ENABLED; 4755 if (sc->sc_flags.change_connect) 4756 value |= UPS_C_CONNECT_STATUS; 4757 if (sc->sc_flags.change_suspend) 4758 value |= UPS_C_SUSPEND; 4759 if (sc->sc_flags.change_reset) 4760 value |= UPS_C_PORT_RESET; 4761 if (sc->sc_flags.change_over_current) 4762 value |= UPS_C_OVERCURRENT_INDICATOR; 4763 4764 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4765 len = sizeof(sc->sc_hub_temp.ps); 4766 goto tr_valid; 4767 4768tr_handle_get_class_descriptor: 4769 if (value & 0xFF) { 4770 goto tr_stalled; 4771 } 4772 ptr = (const void *)&dwc_otg_hubd; 4773 len = sizeof(dwc_otg_hubd); 4774 goto tr_valid; 4775 4776tr_stalled: 4777 err = USB_ERR_STALLED; 4778tr_valid: 4779done: 4780 *plength = len; 4781 *pptr = ptr; 4782 return (err); 4783} 4784 4785static void 4786dwc_otg_xfer_setup(struct usb_setup_params *parm) 4787{ 4788 struct usb_xfer *xfer; 4789 void *last_obj; 4790 uint32_t ntd; 4791 uint32_t n; 4792 uint8_t ep_no; 4793 uint8_t ep_type; 4794 4795 xfer = parm->curr_xfer; 4796 4797 /* 4798 * NOTE: This driver does not use any of the parameters that 4799 * are computed from the following values. Just set some 4800 * reasonable dummies: 4801 */ 4802 parm->hc_max_packet_size = 0x500; 4803 parm->hc_max_packet_count = 3; 4804 parm->hc_max_frame_size = 3 * 0x500; 4805 4806 usbd_transfer_setup_sub(parm); 4807 4808 /* 4809 * compute maximum number of TDs 4810 */ 4811 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4812 4813 if (ep_type == UE_CONTROL) { 4814 4815 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4816 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4817 } else { 4818 4819 ntd = xfer->nframes + 1 /* SYNC */ ; 4820 } 4821 4822 /* 4823 * check if "usbd_transfer_setup_sub" set an error 4824 */ 4825 if (parm->err) 4826 return; 4827 4828 /* 4829 * allocate transfer descriptors 4830 */ 4831 last_obj = NULL; 4832 4833 ep_no = xfer->endpointno & UE_ADDR; 4834 4835 /* 4836 * Check for a valid endpoint profile in USB device mode: 4837 */ 4838 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4839 const struct usb_hw_ep_profile *pf; 4840 4841 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4842 4843 if (pf == NULL) { 4844 /* should not happen */ 4845 parm->err = USB_ERR_INVAL; 4846 return; 4847 } 4848 } 4849 4850 /* align data */ 4851 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4852 4853 for (n = 0; n != ntd; n++) { 4854 4855 struct dwc_otg_td *td; 4856 4857 if (parm->buf) { 4858 4859 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4860 4861 /* compute shared bandwidth resource index for TT */ 4862 if (dwc_otg_uses_split(parm->udev)) { 4863 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4864 td->tt_index = parm->udev->device_index; 4865 else 4866 td->tt_index = parm->udev->parent_hs_hub->device_index; 4867 } else { 4868 td->tt_index = parm->udev->device_index; 4869 } 4870 4871 /* init TD */ 4872 td->max_packet_size = xfer->max_packet_size; 4873 td->max_packet_count = xfer->max_packet_count; 4874 /* range check */ 4875 if (td->max_packet_count == 0 || td->max_packet_count > 3) 4876 td->max_packet_count = 1; 4877 td->ep_no = ep_no; 4878 td->ep_type = ep_type; 4879 td->obj_next = last_obj; 4880 4881 last_obj = td; 4882 } 4883 parm->size[0] += sizeof(*td); 4884 } 4885 4886 xfer->td_start[0] = last_obj; 4887} 4888 4889static void 4890dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4891{ 4892 return; 4893} 4894 4895static void 4896dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4897 struct usb_endpoint *ep) 4898{ 4899 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4900 4901 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4902 ep, udev->address, 4903 edesc->bEndpointAddress, udev->flags.usb_mode, 4904 sc->sc_rt_addr, udev->device_index); 4905 4906 if (udev->device_index != sc->sc_rt_addr) { 4907 4908 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4909 if (udev->speed != USB_SPEED_FULL && 4910 udev->speed != USB_SPEED_HIGH) { 4911 /* not supported */ 4912 return; 4913 } 4914 } else { 4915 if (udev->speed == USB_SPEED_HIGH && 4916 (edesc->wMaxPacketSize[1] & 0x18) != 0 && 4917 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { 4918 /* not supported */ 4919 DPRINTFN(-1, "Non-isochronous high bandwidth " 4920 "endpoint not supported\n"); 4921 return; 4922 } 4923 } 4924 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4925 ep->methods = &dwc_otg_device_isoc_methods; 4926 else 4927 ep->methods = &dwc_otg_device_non_isoc_methods; 4928 } 4929} 4930 4931static void 4932dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4933{ 4934 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4935 4936 switch (state) { 4937 case USB_HW_POWER_SUSPEND: 4938 dwc_otg_suspend(sc); 4939 break; 4940 case USB_HW_POWER_SHUTDOWN: 4941 dwc_otg_uninit(sc); 4942 break; 4943 case USB_HW_POWER_RESUME: 4944 dwc_otg_resume(sc); 4945 break; 4946 default: 4947 break; 4948 } 4949} 4950 4951static void 4952dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4953{ 4954 /* DMA delay - wait until any use of memory is finished */ 4955 *pus = (2125); /* microseconds */ 4956} 4957 4958static void 4959dwc_otg_device_resume(struct usb_device *udev) 4960{ 4961 DPRINTF("\n"); 4962 4963 /* poll all transfers again to restart resumed ones */ 4964 dwc_otg_do_poll(udev->bus); 4965} 4966 4967static void 4968dwc_otg_device_suspend(struct usb_device *udev) 4969{ 4970 DPRINTF("\n"); 4971} 4972 4973static const struct usb_bus_methods dwc_otg_bus_methods = 4974{ 4975 .endpoint_init = &dwc_otg_ep_init, 4976 .xfer_setup = &dwc_otg_xfer_setup, 4977 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4978 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4979 .xfer_stall = &dwc_otg_xfer_stall, 4980 .set_stall = &dwc_otg_set_stall, 4981 .clear_stall = &dwc_otg_clear_stall, 4982 .roothub_exec = &dwc_otg_roothub_exec, 4983 .xfer_poll = &dwc_otg_do_poll, 4984 .device_state_change = &dwc_otg_device_state_change, 4985 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4986 .get_dma_delay = &dwc_otg_get_dma_delay, 4987 .device_resume = &dwc_otg_device_resume, 4988 .device_suspend = &dwc_otg_device_suspend, 4989}; 4990