if_sn.c revision 315221
1/*- 2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Gardner Buchanan. 16 * 4. The name of Gardner Buchanan may not be used to endorse or promote 17 * products derived from this software without specific prior written 18 * permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/sys/dev/sn/if_sn.c 315221 2017-03-14 02:06:03Z pfg $"); 34 35/* 36 * This is a driver for SMC's 9000 series of Ethernet adapters. 37 * 38 * This FreeBSD driver is derived from the smc9194 Linux driver by 39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 40 * This driver also shamelessly borrows from the FreeBSD ep driver 41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca> 42 * All rights reserved. 43 * 44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded 45 * PC. It is adapted from Erik Stahlman's Linux driver which worked 46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook, 47 * it will work for the entire SMC 9xxx series. (Ha Ha) 48 * 49 * "Features" of the SMC chip: 50 * 4608 byte packet memory. (for the 91C92. Others have more) 51 * EEPROM for configuration 52 * AUI/TP selection 53 * 54 * Authors: 55 * Erik Stahlman erik@vt.edu 56 * Herb Peyerl hpeyerl@novatel.ca 57 * Andres Vega Garcia avega@sophia.inria.fr 58 * Serge Babkin babkin@hq.icb.chel.su 59 * Gardner Buchanan gbuchanan@shl.com 60 * 61 * Sources: 62 * o SMC databook 63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)" 64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp" 65 * 66 * Known Bugs: 67 * o Setting of the hardware address isn't supported. 68 * o Hardware padding isn't used. 69 */ 70 71/* 72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT) 73 * 74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org> 75 * BSD-nomads, Tokyo, Japan. 76 */ 77/* 78 * Multicast support by Kei TANAKA <kei@pal.xerox.com> 79 * Special thanks to itojun@itojun.org 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/errno.h> 85#include <sys/kernel.h> 86#include <sys/sockio.h> 87#include <sys/malloc.h> 88#include <sys/mbuf.h> 89#include <sys/socket.h> 90#include <sys/syslog.h> 91 92#include <sys/module.h> 93#include <sys/bus.h> 94 95#include <machine/bus.h> 96#include <machine/resource.h> 97#include <sys/rman.h> 98 99#include <net/ethernet.h> 100#include <net/if.h> 101#include <net/if_var.h> 102#include <net/if_arp.h> 103#include <net/if_dl.h> 104#include <net/if_types.h> 105#include <net/if_mib.h> 106 107#ifdef INET 108#include <netinet/in.h> 109#include <netinet/in_systm.h> 110#include <netinet/in_var.h> 111#include <netinet/ip.h> 112#endif 113 114#include <net/bpf.h> 115#include <net/bpfdesc.h> 116 117#include <dev/sn/if_snreg.h> 118#include <dev/sn/if_snvar.h> 119 120/* Exported variables */ 121devclass_t sn_devclass; 122 123static int snioctl(struct ifnet * ifp, u_long, caddr_t); 124 125static void snresume(struct ifnet *); 126 127static void snintr_locked(struct sn_softc *); 128static void sninit_locked(void *); 129static void snstart_locked(struct ifnet *); 130 131static void sninit(void *); 132static void snread(struct ifnet *); 133static void snstart(struct ifnet *); 134static void snstop(struct sn_softc *); 135static void snwatchdog(void *); 136 137static void sn_setmcast(struct sn_softc *); 138static int sn_getmcf(struct ifnet *ifp, u_char *mcf); 139 140/* I (GB) have been unlucky getting the hardware padding 141 * to work properly. 142 */ 143#define SW_PAD 144 145static const char *chip_ids[15] = { 146 NULL, NULL, NULL, 147 /* 3 */ "SMC91C90/91C92", 148 /* 4 */ "SMC91C94/91C96", 149 /* 5 */ "SMC91C95", 150 NULL, 151 /* 7 */ "SMC91C100", 152 /* 8 */ "SMC91C100FD", 153 /* 9 */ "SMC91C110", 154 NULL, NULL, 155 NULL, NULL, NULL 156}; 157 158int 159sn_attach(device_t dev) 160{ 161 struct sn_softc *sc = device_get_softc(dev); 162 struct ifnet *ifp; 163 uint16_t i; 164 uint8_t *p; 165 int rev; 166 uint16_t address; 167 int err; 168 u_char eaddr[6]; 169 170 ifp = sc->ifp = if_alloc(IFT_ETHER); 171 if (ifp == NULL) { 172 device_printf(dev, "can not if_alloc()\n"); 173 return (ENOSPC); 174 } 175 176 SN_LOCK_INIT(sc); 177 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0); 178 snstop(sc); 179 sc->pages_wanted = -1; 180 181 if (bootverbose || 1) { 182 SMC_SELECT_BANK(sc, 3); 183 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf; 184 if (chip_ids[rev]) 185 device_printf(dev, " %s ", chip_ids[rev]); 186 else 187 device_printf(dev, " unsupported chip: rev %d ", rev); 188 SMC_SELECT_BANK(sc, 1); 189 i = CSR_READ_2(sc, CONFIG_REG_W); 190 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP"); 191 } 192 193 /* 194 * Read the station address from the chip. The MAC address is bank 1, 195 * regs 4 - 9 196 */ 197 SMC_SELECT_BANK(sc, 1); 198 p = (uint8_t *) eaddr; 199 for (i = 0; i < 6; i += 2) { 200 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i); 201 p[i + 1] = address >> 8; 202 p[i] = address & 0xFF; 203 } 204 ifp->if_softc = sc; 205 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 206 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 207 ifp->if_start = snstart; 208 ifp->if_ioctl = snioctl; 209 ifp->if_init = sninit; 210 ifp->if_baudrate = 10000000; 211 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 212 ifp->if_snd.ifq_maxlen = ifqmaxlen; 213 IFQ_SET_READY(&ifp->if_snd); 214 215 ether_ifattach(ifp, eaddr); 216 217 /* 218 * Activate the interrupt so we can get card interrupts. This 219 * needs to be done last so that we don't have/hold the lock 220 * during startup to avoid LORs in the network layer. 221 */ 222 if ((err = bus_setup_intr(dev, sc->irq_res, 223 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc, 224 &sc->intrhand)) != 0) { 225 sn_detach(dev); 226 return err; 227 } 228 return 0; 229} 230 231 232int 233sn_detach(device_t dev) 234{ 235 struct sn_softc *sc = device_get_softc(dev); 236 struct ifnet *ifp = sc->ifp; 237 238 ether_ifdetach(ifp); 239 SN_LOCK(sc); 240 snstop(sc); 241 SN_UNLOCK(sc); 242 callout_drain(&sc->watchdog); 243 sn_deactivate(dev); 244 if_free(ifp); 245 SN_LOCK_DESTROY(sc); 246 return 0; 247} 248 249static void 250sninit(void *xsc) 251{ 252 struct sn_softc *sc = xsc; 253 SN_LOCK(sc); 254 sninit_locked(sc); 255 SN_UNLOCK(sc); 256} 257 258/* 259 * Reset and initialize the chip 260 */ 261static void 262sninit_locked(void *xsc) 263{ 264 struct sn_softc *sc = xsc; 265 struct ifnet *ifp = sc->ifp; 266 int flags; 267 int mask; 268 269 SN_ASSERT_LOCKED(sc); 270 271 /* 272 * This resets the registers mostly to defaults, but doesn't affect 273 * EEPROM. After the reset cycle, we pause briefly for the chip to 274 * be happy. 275 */ 276 SMC_SELECT_BANK(sc, 0); 277 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET); 278 SMC_DELAY(sc); 279 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 280 SMC_DELAY(sc); 281 SMC_DELAY(sc); 282 283 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 284 285 /* 286 * Set the control register to automatically release successfully 287 * transmitted packets (making the best use out of our limited 288 * memory) and to enable the EPH interrupt on certain TX errors. 289 */ 290 SMC_SELECT_BANK(sc, 1); 291 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | 292 CTR_CR_ENABLE | CTR_LE_ENABLE)); 293 294 /* Set squelch level to 240mV (default 480mV) */ 295 flags = CSR_READ_2(sc, CONFIG_REG_W); 296 flags |= CR_SET_SQLCH; 297 CSR_WRITE_2(sc, CONFIG_REG_W, flags); 298 299 /* 300 * Reset the MMU and wait for it to be un-busy. 301 */ 302 SMC_SELECT_BANK(sc, 2); 303 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET); 304 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 305 ; 306 307 /* 308 * Disable all interrupts 309 */ 310 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 311 312 sn_setmcast(sc); 313 314 /* 315 * Set the transmitter control. We want it enabled. 316 */ 317 flags = TCR_ENABLE; 318 319#ifndef SW_PAD 320 /* 321 * I (GB) have been unlucky getting this to work. 322 */ 323 flags |= TCR_PAD_ENABLE; 324#endif /* SW_PAD */ 325 326 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags); 327 328 329 /* 330 * Now, enable interrupts 331 */ 332 SMC_SELECT_BANK(sc, 2); 333 334 mask = IM_EPH_INT | 335 IM_RX_OVRN_INT | 336 IM_RCV_INT | 337 IM_TX_INT; 338 339 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 340 sc->intr_mask = mask; 341 sc->pages_wanted = -1; 342 343 344 /* 345 * Mark the interface running but not active. 346 */ 347 ifp->if_drv_flags |= IFF_DRV_RUNNING; 348 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 349 callout_reset(&sc->watchdog, hz, snwatchdog, sc); 350 351 /* 352 * Attempt to push out any waiting packets. 353 */ 354 snstart_locked(ifp); 355} 356 357static void 358snstart(struct ifnet *ifp) 359{ 360 struct sn_softc *sc = ifp->if_softc; 361 SN_LOCK(sc); 362 snstart_locked(ifp); 363 SN_UNLOCK(sc); 364} 365 366 367static void 368snstart_locked(struct ifnet *ifp) 369{ 370 struct sn_softc *sc = ifp->if_softc; 371 u_int len; 372 struct mbuf *m; 373 struct mbuf *top; 374 int pad; 375 int mask; 376 uint16_t length; 377 uint16_t numPages; 378 uint8_t packet_no; 379 int time_out; 380 int junk = 0; 381 382 SN_ASSERT_LOCKED(sc); 383 384 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 385 return; 386 if (sc->pages_wanted != -1) { 387 if_printf(ifp, "snstart() while memory allocation pending\n"); 388 return; 389 } 390startagain: 391 392 /* 393 * Sneak a peek at the next packet 394 */ 395 m = ifp->if_snd.ifq_head; 396 if (m == NULL) 397 return; 398 /* 399 * Compute the frame length and set pad to give an overall even 400 * number of bytes. Below we assume that the packet length is even. 401 */ 402 for (len = 0, top = m; m; m = m->m_next) 403 len += m->m_len; 404 405 pad = (len & 1); 406 407 /* 408 * We drop packets that are too large. Perhaps we should truncate 409 * them instead? 410 */ 411 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 412 if_printf(ifp, "large packet discarded (A)\n"); 413 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 414 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 415 m_freem(m); 416 goto readcheck; 417 } 418#ifdef SW_PAD 419 420 /* 421 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 422 */ 423 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 424 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 425 426#endif /* SW_PAD */ 427 428 length = pad + len; 429 430 /* 431 * The MMU wants the number of pages to be the number of 256 byte 432 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 433 * include space for the status word, byte count and control bytes in 434 * the allocation request. 435 */ 436 numPages = (length + 6) >> 8; 437 438 439 /* 440 * Now, try to allocate the memory 441 */ 442 SMC_SELECT_BANK(sc, 2); 443 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages); 444 445 /* 446 * Wait a short amount of time to see if the allocation request 447 * completes. Otherwise, I enable the interrupt and wait for 448 * completion asynchronously. 449 */ 450 451 time_out = MEMORY_WAIT_TIME; 452 do { 453 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT) 454 break; 455 } while (--time_out); 456 457 if (!time_out || junk > 10) { 458 459 /* 460 * No memory now. Oh well, wait until the chip finds memory 461 * later. Remember how many pages we were asking for and 462 * enable the allocation completion interrupt. Also set a 463 * watchdog in case we miss the interrupt. We mark the 464 * interface active since there is no point in attempting an 465 * snstart() until after the memory is available. 466 */ 467 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT; 468 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 469 sc->intr_mask = mask; 470 471 sc->timer = 1; 472 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 473 sc->pages_wanted = numPages; 474 return; 475 } 476 /* 477 * The memory allocation completed. Check the results. 478 */ 479 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 480 if (packet_no & ARR_FAILED) { 481 if (junk++ > 10) 482 if_printf(ifp, "Memory allocation failed\n"); 483 goto startagain; 484 } 485 /* 486 * We have a packet number, so tell the card to use it. 487 */ 488 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 489 490 /* 491 * Point to the beginning of the packet 492 */ 493 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 494 495 /* 496 * Send the packet length (+6 for status, length and control byte) 497 * and the status word (set to zeros) 498 */ 499 CSR_WRITE_2(sc, DATA_REG_W, 0); 500 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 501 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 502 503 /* 504 * Get the packet from the kernel. This will include the Ethernet 505 * frame header, MAC Addresses etc. 506 */ 507 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 508 509 /* 510 * Push out the data to the card. 511 */ 512 for (top = m; m != NULL; m = m->m_next) { 513 514 /* 515 * Push out words. 516 */ 517 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 518 m->m_len / 2); 519 520 /* 521 * Push out remaining byte. 522 */ 523 if (m->m_len & 1) 524 CSR_WRITE_1(sc, DATA_REG_B, 525 *(mtod(m, caddr_t) + m->m_len - 1)); 526 } 527 528 /* 529 * Push out padding. 530 */ 531 while (pad > 1) { 532 CSR_WRITE_2(sc, DATA_REG_W, 0); 533 pad -= 2; 534 } 535 if (pad) 536 CSR_WRITE_1(sc, DATA_REG_B, 0); 537 538 /* 539 * Push out control byte and unused packet byte The control byte is 0 540 * meaning the packet is even lengthed and no special CRC handling is 541 * desired. 542 */ 543 CSR_WRITE_2(sc, DATA_REG_W, 0); 544 545 /* 546 * Enable the interrupts and let the chipset deal with it Also set a 547 * watchdog in case we miss the interrupt. 548 */ 549 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 550 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 551 sc->intr_mask = mask; 552 553 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 554 555 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 556 sc->timer = 1; 557 558 BPF_MTAP(ifp, top); 559 560 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 561 m_freem(top); 562 563 564readcheck: 565 566 /* 567 * Is another packet coming in? We don't want to overflow the tiny 568 * RX FIFO. If nothing has arrived then attempt to queue another 569 * transmit packet. 570 */ 571 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY) 572 goto startagain; 573 return; 574} 575 576 577 578/* Resume a packet transmit operation after a memory allocation 579 * has completed. 580 * 581 * This is basically a hacked up copy of snstart() which handles 582 * a completed memory allocation the same way snstart() does. 583 * It then passes control to snstart to handle any other queued 584 * packets. 585 */ 586static void 587snresume(struct ifnet *ifp) 588{ 589 struct sn_softc *sc = ifp->if_softc; 590 u_int len; 591 struct mbuf *m; 592 struct mbuf *top; 593 int pad; 594 int mask; 595 uint16_t length; 596 uint16_t numPages; 597 uint16_t pages_wanted; 598 uint8_t packet_no; 599 600 if (sc->pages_wanted < 0) 601 return; 602 603 pages_wanted = sc->pages_wanted; 604 sc->pages_wanted = -1; 605 606 /* 607 * Sneak a peek at the next packet 608 */ 609 m = ifp->if_snd.ifq_head; 610 if (m == NULL) { 611 if_printf(ifp, "snresume() with nothing to send\n"); 612 return; 613 } 614 /* 615 * Compute the frame length and set pad to give an overall even 616 * number of bytes. Below we assume that the packet length is even. 617 */ 618 for (len = 0, top = m; m; m = m->m_next) 619 len += m->m_len; 620 621 pad = (len & 1); 622 623 /* 624 * We drop packets that are too large. Perhaps we should truncate 625 * them instead? 626 */ 627 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 628 if_printf(ifp, "large packet discarded (B)\n"); 629 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 630 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 631 m_freem(m); 632 return; 633 } 634#ifdef SW_PAD 635 636 /* 637 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 638 */ 639 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 640 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 641 642#endif /* SW_PAD */ 643 644 length = pad + len; 645 646 647 /* 648 * The MMU wants the number of pages to be the number of 256 byte 649 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 650 * include space for the status word, byte count and control bytes in 651 * the allocation request. 652 */ 653 numPages = (length + 6) >> 8; 654 655 656 SMC_SELECT_BANK(sc, 2); 657 658 /* 659 * The memory allocation completed. Check the results. If it failed, 660 * we simply set a watchdog timer and hope for the best. 661 */ 662 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 663 if (packet_no & ARR_FAILED) { 664 if_printf(ifp, "Memory allocation failed. Weird.\n"); 665 sc->timer = 1; 666 goto try_start; 667 } 668 /* 669 * We have a packet number, so tell the card to use it. 670 */ 671 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 672 673 /* 674 * Now, numPages should match the pages_wanted recorded when the 675 * memory allocation was initiated. 676 */ 677 if (pages_wanted != numPages) { 678 if_printf(ifp, "memory allocation wrong size. Weird.\n"); 679 /* 680 * If the allocation was the wrong size we simply release the 681 * memory once it is granted. Wait for the MMU to be un-busy. 682 */ 683 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 684 ; 685 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 686 687 return; 688 } 689 /* 690 * Point to the beginning of the packet 691 */ 692 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 693 694 /* 695 * Send the packet length (+6 for status, length and control byte) 696 * and the status word (set to zeros) 697 */ 698 CSR_WRITE_2(sc, DATA_REG_W, 0); 699 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 700 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 701 702 /* 703 * Get the packet from the kernel. This will include the Ethernet 704 * frame header, MAC Addresses etc. 705 */ 706 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 707 708 /* 709 * Push out the data to the card. 710 */ 711 for (top = m; m != NULL; m = m->m_next) { 712 713 /* 714 * Push out words. 715 */ 716 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 717 m->m_len / 2); 718 /* 719 * Push out remaining byte. 720 */ 721 if (m->m_len & 1) 722 CSR_WRITE_1(sc, DATA_REG_B, 723 *(mtod(m, caddr_t) + m->m_len - 1)); 724 } 725 726 /* 727 * Push out padding. 728 */ 729 while (pad > 1) { 730 CSR_WRITE_2(sc, DATA_REG_W, 0); 731 pad -= 2; 732 } 733 if (pad) 734 CSR_WRITE_1(sc, DATA_REG_B, 0); 735 736 /* 737 * Push out control byte and unused packet byte The control byte is 0 738 * meaning the packet is even lengthed and no special CRC handling is 739 * desired. 740 */ 741 CSR_WRITE_2(sc, DATA_REG_W, 0); 742 743 /* 744 * Enable the interrupts and let the chipset deal with it Also set a 745 * watchdog in case we miss the interrupt. 746 */ 747 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 748 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 749 sc->intr_mask = mask; 750 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 751 752 BPF_MTAP(ifp, top); 753 754 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 755 m_freem(top); 756 757try_start: 758 759 /* 760 * Now pass control to snstart() to queue any additional packets 761 */ 762 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 763 snstart_locked(ifp); 764 765 /* 766 * We've sent something, so we're active. Set a watchdog in case the 767 * TX_EMPTY interrupt is lost. 768 */ 769 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 770 sc->timer = 1; 771 772 return; 773} 774 775void 776sn_intr(void *arg) 777{ 778 struct sn_softc *sc = (struct sn_softc *) arg; 779 780 SN_LOCK(sc); 781 snintr_locked(sc); 782 SN_UNLOCK(sc); 783} 784 785static void 786snintr_locked(struct sn_softc *sc) 787{ 788 int status, interrupts; 789 struct ifnet *ifp = sc->ifp; 790 791 /* 792 * Chip state registers 793 */ 794 uint8_t mask; 795 uint8_t packet_no; 796 uint16_t tx_status; 797 uint16_t card_stats; 798 799 /* 800 * Clear the watchdog. 801 */ 802 sc->timer = 0; 803 804 SMC_SELECT_BANK(sc, 2); 805 806 /* 807 * Obtain the current interrupt mask and clear the hardware mask 808 * while servicing interrupts. 809 */ 810 mask = CSR_READ_1(sc, INTR_MASK_REG_B); 811 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 812 813 /* 814 * Get the set of interrupts which occurred and eliminate any which 815 * are masked. 816 */ 817 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B); 818 status = interrupts & mask; 819 820 /* 821 * Now, process each of the interrupt types. 822 */ 823 824 /* 825 * Receive Overrun. 826 */ 827 if (status & IM_RX_OVRN_INT) { 828 /* 829 * Acknowlege Interrupt 830 */ 831 SMC_SELECT_BANK(sc, 2); 832 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT); 833 834 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 835 } 836 /* 837 * Got a packet. 838 */ 839 if (status & IM_RCV_INT) { 840 int packet_number; 841 842 SMC_SELECT_BANK(sc, 2); 843 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 844 845 if (packet_number & FIFO_REMPTY) { 846 /* 847 * we got called , but nothing was on the FIFO 848 */ 849 printf("sn: Receive interrupt with nothing on FIFO\n"); 850 goto out; 851 } 852 snread(ifp); 853 } 854 /* 855 * An on-card memory allocation came through. 856 */ 857 if (status & IM_ALLOC_INT) { 858 /* 859 * Disable this interrupt. 860 */ 861 mask &= ~IM_ALLOC_INT; 862 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 863 snresume(ifp); 864 } 865 /* 866 * TX Completion. Handle a transmit error message. This will only be 867 * called when there is an error, because of the AUTO_RELEASE mode. 868 */ 869 if (status & IM_TX_INT) { 870 /* 871 * Acknowlege Interrupt 872 */ 873 SMC_SELECT_BANK(sc, 2); 874 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT); 875 876 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W); 877 packet_no &= FIFO_TX_MASK; 878 879 /* 880 * select this as the packet to read from 881 */ 882 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 883 884 /* 885 * Position the pointer to the first word from this packet 886 */ 887 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000); 888 889 /* 890 * Fetch the TX status word. The value found here will be a 891 * copy of the EPH_STATUS_REG_W at the time the transmit 892 * failed. 893 */ 894 tx_status = CSR_READ_2(sc, DATA_REG_W); 895 896 if (tx_status & EPHSR_TX_SUC) { 897 device_printf(sc->dev, 898 "Successful packet caused interrupt\n"); 899 } else { 900 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 901 } 902 903 if (tx_status & EPHSR_LATCOL) 904 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 905 906 /* 907 * Some of these errors will have disabled transmit. 908 * Re-enable transmit now. 909 */ 910 SMC_SELECT_BANK(sc, 0); 911 912#ifdef SW_PAD 913 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE); 914#else 915 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE); 916#endif /* SW_PAD */ 917 918 /* 919 * kill the failed packet. Wait for the MMU to be un-busy. 920 */ 921 SMC_SELECT_BANK(sc, 2); 922 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 923 ; 924 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 925 926 /* 927 * Attempt to queue more transmits. 928 */ 929 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 930 snstart_locked(ifp); 931 } 932 /* 933 * Transmit underrun. We use this opportunity to update transmit 934 * statistics from the card. 935 */ 936 if (status & IM_TX_EMPTY_INT) { 937 938 /* 939 * Acknowlege Interrupt 940 */ 941 SMC_SELECT_BANK(sc, 2); 942 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 943 944 /* 945 * Disable this interrupt. 946 */ 947 mask &= ~IM_TX_EMPTY_INT; 948 949 SMC_SELECT_BANK(sc, 0); 950 card_stats = CSR_READ_2(sc, COUNTER_REG_W); 951 952 /* 953 * Single collisions 954 */ 955 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, card_stats & ECR_COLN_MASK); 956 957 /* 958 * Multiple collisions 959 */ 960 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (card_stats & ECR_MCOLN_MASK) >> 4); 961 962 SMC_SELECT_BANK(sc, 2); 963 964 /* 965 * Attempt to enqueue some more stuff. 966 */ 967 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 968 snstart_locked(ifp); 969 } 970 /* 971 * Some other error. Try to fix it by resetting the adapter. 972 */ 973 if (status & IM_EPH_INT) { 974 snstop(sc); 975 sninit_locked(sc); 976 } 977 978out: 979 /* 980 * Handled all interrupt sources. 981 */ 982 983 SMC_SELECT_BANK(sc, 2); 984 985 /* 986 * Reestablish interrupts from mask which have not been deselected 987 * during this interrupt. Note that the hardware mask, which was set 988 * to 0x00 at the start of this service routine, may have been 989 * updated by one or more of the interrupt handers and we must let 990 * those new interrupts stay enabled here. 991 */ 992 mask |= CSR_READ_1(sc, INTR_MASK_REG_B); 993 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 994 sc->intr_mask = mask; 995} 996 997static void 998snread(struct ifnet *ifp) 999{ 1000 struct sn_softc *sc = ifp->if_softc; 1001 struct ether_header *eh; 1002 struct mbuf *m; 1003 short status; 1004 int packet_number; 1005 uint16_t packet_length; 1006 uint8_t *data; 1007 1008 SMC_SELECT_BANK(sc, 2); 1009#if 0 1010 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1011 1012 if (packet_number & FIFO_REMPTY) { 1013 1014 /* 1015 * we got called , but nothing was on the FIFO 1016 */ 1017 printf("sn: Receive interrupt with nothing on FIFO\n"); 1018 return; 1019 } 1020#endif 1021read_another: 1022 1023 /* 1024 * Start reading from the start of the packet. Since PTR_RCV is set, 1025 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1026 */ 1027 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000); 1028 1029 /* 1030 * First two words are status and packet_length 1031 */ 1032 status = CSR_READ_2(sc, DATA_REG_W); 1033 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK; 1034 1035 /* 1036 * The packet length contains 3 extra words: status, length, and a 1037 * extra word with the control byte. 1038 */ 1039 packet_length -= 6; 1040 1041 /* 1042 * Account for receive errors and discard. 1043 */ 1044 if (status & RS_ERRORS) { 1045 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1046 goto out; 1047 } 1048 /* 1049 * A packet is received. 1050 */ 1051 1052 /* 1053 * Adjust for odd-length packet. 1054 */ 1055 if (status & RS_ODDFRAME) 1056 packet_length++; 1057 1058 /* 1059 * Allocate a header mbuf from the kernel. 1060 */ 1061 MGETHDR(m, M_NOWAIT, MT_DATA); 1062 if (m == NULL) 1063 goto out; 1064 1065 m->m_pkthdr.rcvif = ifp; 1066 m->m_pkthdr.len = m->m_len = packet_length; 1067 1068 /* 1069 * Attach an mbuf cluster. 1070 */ 1071 if (!(MCLGET(m, M_NOWAIT))) { 1072 m_freem(m); 1073 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1074 printf("sn: snread() kernel memory allocation problem\n"); 1075 goto out; 1076 } 1077 eh = mtod(m, struct ether_header *); 1078 1079 /* 1080 * Get packet, including link layer address, from interface. 1081 */ 1082 data = (uint8_t *) eh; 1083 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1); 1084 if (packet_length & 1) { 1085 data += packet_length & ~1; 1086 *data = CSR_READ_1(sc, DATA_REG_B); 1087 } 1088 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1089 1090 /* 1091 * Remove link layer addresses and whatnot. 1092 */ 1093 m->m_pkthdr.len = m->m_len = packet_length; 1094 1095 /* 1096 * Drop locks before calling if_input() since it may re-enter 1097 * snstart() in the netisr case. This would result in a 1098 * lock reversal. Better performance might be obtained by 1099 * chaining all packets received, dropping the lock, and then 1100 * calling if_input() on each one. 1101 */ 1102 SN_UNLOCK(sc); 1103 (*ifp->if_input)(ifp, m); 1104 SN_LOCK(sc); 1105 1106out: 1107 1108 /* 1109 * Error or good, tell the card to get rid of this packet Wait for 1110 * the MMU to be un-busy. 1111 */ 1112 SMC_SELECT_BANK(sc, 2); 1113 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 1114 ; 1115 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE); 1116 1117 /* 1118 * Check whether another packet is ready 1119 */ 1120 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1121 if (packet_number & FIFO_REMPTY) { 1122 return; 1123 } 1124 goto read_another; 1125} 1126 1127 1128/* 1129 * Handle IOCTLS. This function is completely stolen from if_ep.c 1130 * As with its progenitor, it does not handle hardware address 1131 * changes. 1132 */ 1133static int 1134snioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1135{ 1136 struct sn_softc *sc = ifp->if_softc; 1137 int error = 0; 1138 1139 switch (cmd) { 1140 case SIOCSIFFLAGS: 1141 SN_LOCK(sc); 1142 if ((ifp->if_flags & IFF_UP) == 0 && 1143 ifp->if_drv_flags & IFF_DRV_RUNNING) { 1144 snstop(sc); 1145 } else { 1146 /* reinitialize card on any parameter change */ 1147 sninit_locked(sc); 1148 } 1149 SN_UNLOCK(sc); 1150 break; 1151 1152 case SIOCADDMULTI: 1153 case SIOCDELMULTI: 1154 /* update multicast filter list. */ 1155 SN_LOCK(sc); 1156 sn_setmcast(sc); 1157 error = 0; 1158 SN_UNLOCK(sc); 1159 break; 1160 default: 1161 error = ether_ioctl(ifp, cmd, data); 1162 break; 1163 } 1164 return (error); 1165} 1166 1167static void 1168snwatchdog(void *arg) 1169{ 1170 struct sn_softc *sc; 1171 1172 sc = arg; 1173 SN_ASSERT_LOCKED(sc); 1174 callout_reset(&sc->watchdog, hz, snwatchdog, sc); 1175 if (sc->timer == 0 || --sc->timer > 0) 1176 return; 1177 snintr_locked(sc); 1178} 1179 1180 1181/* 1. zero the interrupt mask 1182 * 2. clear the enable receive flag 1183 * 3. clear the enable xmit flags 1184 */ 1185static void 1186snstop(struct sn_softc *sc) 1187{ 1188 1189 struct ifnet *ifp = sc->ifp; 1190 1191 /* 1192 * Clear interrupt mask; disable all interrupts. 1193 */ 1194 SMC_SELECT_BANK(sc, 2); 1195 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 1196 1197 /* 1198 * Disable transmitter and Receiver 1199 */ 1200 SMC_SELECT_BANK(sc, 0); 1201 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 1202 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 1203 1204 /* 1205 * Cancel watchdog. 1206 */ 1207 sc->timer = 0; 1208 callout_stop(&sc->watchdog); 1209 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1210} 1211 1212 1213int 1214sn_activate(device_t dev) 1215{ 1216 struct sn_softc *sc = device_get_softc(dev); 1217 1218 sc->port_rid = 0; 1219 sc->port_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, 1220 &sc->port_rid, SMC_IO_EXTENT, RF_ACTIVE); 1221 if (!sc->port_res) { 1222 if (bootverbose) 1223 device_printf(dev, "Cannot allocate ioport\n"); 1224 return ENOMEM; 1225 } 1226 1227 sc->irq_rid = 0; 1228 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 1229 RF_ACTIVE); 1230 if (!sc->irq_res) { 1231 if (bootverbose) 1232 device_printf(dev, "Cannot allocate irq\n"); 1233 sn_deactivate(dev); 1234 return ENOMEM; 1235 } 1236 return (0); 1237} 1238 1239void 1240sn_deactivate(device_t dev) 1241{ 1242 struct sn_softc *sc = device_get_softc(dev); 1243 1244 if (sc->intrhand) 1245 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1246 sc->intrhand = 0; 1247 if (sc->port_res) 1248 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid, 1249 sc->port_res); 1250 sc->port_res = 0; 1251 if (sc->modem_res) 1252 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid, 1253 sc->modem_res); 1254 sc->modem_res = 0; 1255 if (sc->irq_res) 1256 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 1257 sc->irq_res); 1258 sc->irq_res = 0; 1259 return; 1260} 1261 1262/* 1263 * Function: sn_probe(device_t dev) 1264 * 1265 * Purpose: 1266 * Tests to see if a given ioaddr points to an SMC9xxx chip. 1267 * Tries to cause as little damage as possible if it's not a SMC chip. 1268 * Returns a 0 on success 1269 * 1270 * Algorithm: 1271 * (1) see if the high byte of BANK_SELECT is 0x33 1272 * (2) compare the ioaddr with the base register's address 1273 * (3) see if I recognize the chip ID in the appropriate register 1274 * 1275 * 1276 */ 1277int 1278sn_probe(device_t dev) 1279{ 1280 struct sn_softc *sc = device_get_softc(dev); 1281 uint16_t bank; 1282 uint16_t revision_register; 1283 uint16_t base_address_register; 1284 int err; 1285 1286 if ((err = sn_activate(dev)) != 0) 1287 return err; 1288 1289 /* 1290 * First, see if the high byte is 0x33 1291 */ 1292 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1293 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1294#ifdef SN_DEBUG 1295 device_printf(dev, "test1 failed\n"); 1296#endif 1297 goto error; 1298 } 1299 /* 1300 * The above MIGHT indicate a device, but I need to write to further 1301 * test this. Go to bank 0, then test that the register still 1302 * reports the high byte is 0x33. 1303 */ 1304 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000); 1305 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1306 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1307#ifdef SN_DEBUG 1308 device_printf(dev, "test2 failed\n"); 1309#endif 1310 goto error; 1311 } 1312 /* 1313 * well, we've already written once, so hopefully another time won't 1314 * hurt. This time, I need to switch the bank register to bank 1, so 1315 * I can access the base address register. The contents of the 1316 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected 1317 * to match the I/O port address where the adapter is being probed. 1318 */ 1319 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001); 1320 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0; 1321 1322 if (rman_get_start(sc->port_res) != base_address_register) { 1323 1324 /* 1325 * Well, the base address register didn't match. Must not 1326 * have been a SMC chip after all. 1327 */ 1328#ifdef SN_DEBUG 1329 device_printf(dev, "test3 failed ioaddr = 0x%x, " 1330 "base_address_register = 0x%x\n", 1331 rman_get_start(sc->port_res), base_address_register); 1332#endif 1333 goto error; 1334 } 1335 1336 /* 1337 * Check if the revision register is something that I recognize. 1338 * These might need to be added to later, as future revisions could 1339 * be added. 1340 */ 1341 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3); 1342 revision_register = CSR_READ_2(sc, REVISION_REG_W); 1343 if (!chip_ids[(revision_register >> 4) & 0xF]) { 1344 1345 /* 1346 * I don't regonize this chip, so... 1347 */ 1348#ifdef SN_DEBUG 1349 device_printf(dev, "test4 failed\n"); 1350#endif 1351 goto error; 1352 } 1353 1354 /* 1355 * at this point I'll assume that the chip is an SMC9xxx. It might be 1356 * prudent to check a listing of MAC addresses against the hardware 1357 * address, or do some other tests. 1358 */ 1359 sn_deactivate(dev); 1360 return 0; 1361 error: 1362 sn_deactivate(dev); 1363 return ENXIO; 1364} 1365 1366#define MCFSZ 8 1367 1368static void 1369sn_setmcast(struct sn_softc *sc) 1370{ 1371 struct ifnet *ifp = sc->ifp; 1372 int flags; 1373 uint8_t mcf[MCFSZ]; 1374 1375 SN_ASSERT_LOCKED(sc); 1376 1377 /* 1378 * Set the receiver filter. We want receive enabled and auto strip 1379 * of CRC from received packet. If we are promiscuous then set that 1380 * bit too. 1381 */ 1382 flags = RCR_ENABLE | RCR_STRIP_CRC; 1383 1384 if (ifp->if_flags & IFF_PROMISC) { 1385 flags |= RCR_PROMISC | RCR_ALMUL; 1386 } else if (ifp->if_flags & IFF_ALLMULTI) { 1387 flags |= RCR_ALMUL; 1388 } else { 1389 if (sn_getmcf(ifp, mcf)) { 1390 /* set filter */ 1391 SMC_SELECT_BANK(sc, 3); 1392 CSR_WRITE_2(sc, MULTICAST1_REG_W, 1393 ((uint16_t)mcf[1] << 8) | mcf[0]); 1394 CSR_WRITE_2(sc, MULTICAST2_REG_W, 1395 ((uint16_t)mcf[3] << 8) | mcf[2]); 1396 CSR_WRITE_2(sc, MULTICAST3_REG_W, 1397 ((uint16_t)mcf[5] << 8) | mcf[4]); 1398 CSR_WRITE_2(sc, MULTICAST4_REG_W, 1399 ((uint16_t)mcf[7] << 8) | mcf[6]); 1400 } else { 1401 flags |= RCR_ALMUL; 1402 } 1403 } 1404 SMC_SELECT_BANK(sc, 0); 1405 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags); 1406} 1407 1408static int 1409sn_getmcf(struct ifnet *ifp, uint8_t *mcf) 1410{ 1411 int i; 1412 uint32_t index, index2; 1413 uint8_t *af = mcf; 1414 struct ifmultiaddr *ifma; 1415 1416 bzero(mcf, MCFSZ); 1417 1418 if_maddr_rlock(ifp); 1419 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1420 if (ifma->ifma_addr->sa_family != AF_LINK) { 1421 if_maddr_runlock(ifp); 1422 return 0; 1423 } 1424 index = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1425 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f; 1426 index2 = 0; 1427 for (i = 0; i < 6; i++) { 1428 index2 <<= 1; 1429 index2 |= (index & 0x01); 1430 index >>= 1; 1431 } 1432 af[index2 >> 3] |= 1 << (index2 & 7); 1433 } 1434 if_maddr_runlock(ifp); 1435 return 1; /* use multicast filter */ 1436} 1437