siena_impl.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009-2016 Solarflare Communications Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 *    this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 *    this list of conditions and the following disclaimer in the documentation
14 *    and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * The views and conclusions contained in the software and documentation are
29 * those of the authors and should not be interpreted as representing official
30 * policies, either expressed or implied, of the FreeBSD Project.
31 *
32 * $FreeBSD: stable/11/sys/dev/sfxge/common/siena_impl.h 330897 2018-03-14 03:19:51Z eadler $
33 */
34
35#ifndef _SYS_SIENA_IMPL_H
36#define	_SYS_SIENA_IMPL_H
37
38#include "efx.h"
39#include "efx_regs.h"
40#include "efx_mcdi.h"
41#include "siena_flash.h"
42
43#ifdef	__cplusplus
44extern "C" {
45#endif
46
47#define	SIENA_NVRAM_CHUNK 0x80
48
49extern	__checkReturn	efx_rc_t
50siena_nic_probe(
51	__in		efx_nic_t *enp);
52
53extern	__checkReturn	efx_rc_t
54siena_nic_reset(
55	__in		efx_nic_t *enp);
56
57extern	__checkReturn	efx_rc_t
58siena_nic_init(
59	__in		efx_nic_t *enp);
60
61#if EFSYS_OPT_DIAG
62
63extern	__checkReturn	efx_rc_t
64siena_nic_register_test(
65	__in		efx_nic_t *enp);
66
67#endif	/* EFSYS_OPT_DIAG */
68
69extern			void
70siena_nic_fini(
71	__in		efx_nic_t *enp);
72
73extern			void
74siena_nic_unprobe(
75	__in		efx_nic_t *enp);
76
77#define	SIENA_SRAM_ROWS	0x12000
78
79extern			void
80siena_sram_init(
81	__in		efx_nic_t *enp);
82
83#if EFSYS_OPT_DIAG
84
85extern	__checkReturn	efx_rc_t
86siena_sram_test(
87	__in		efx_nic_t *enp,
88	__in		efx_sram_pattern_fn_t func);
89
90#endif	/* EFSYS_OPT_DIAG */
91
92#if EFSYS_OPT_MCDI
93
94extern	__checkReturn	efx_rc_t
95siena_mcdi_init(
96	__in		efx_nic_t *enp,
97	__in		const efx_mcdi_transport_t *mtp);
98
99extern			void
100siena_mcdi_send_request(
101	__in			efx_nic_t *enp,
102	__in_bcount(hdr_len)	void *hdrp,
103	__in			size_t hdr_len,
104	__in_bcount(sdu_len)	void *sdup,
105	__in			size_t sdu_len);
106
107extern	__checkReturn	boolean_t
108siena_mcdi_poll_response(
109	__in		efx_nic_t *enp);
110
111extern			void
112siena_mcdi_read_response(
113	__in			efx_nic_t *enp,
114	__out_bcount(length)	void *bufferp,
115	__in			size_t offset,
116	__in			size_t length);
117
118extern			efx_rc_t
119siena_mcdi_poll_reboot(
120	__in		efx_nic_t *enp);
121
122extern			void
123siena_mcdi_fini(
124	__in		efx_nic_t *enp);
125
126extern	__checkReturn	efx_rc_t
127siena_mcdi_feature_supported(
128	__in		efx_nic_t *enp,
129	__in		efx_mcdi_feature_id_t id,
130	__out		boolean_t *supportedp);
131
132extern			void
133siena_mcdi_get_timeout(
134	__in		efx_nic_t *enp,
135	__in		efx_mcdi_req_t *emrp,
136	__out		uint32_t *timeoutp);
137
138#endif /* EFSYS_OPT_MCDI */
139
140#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
141
142extern	__checkReturn		efx_rc_t
143siena_nvram_partn_lock(
144	__in			efx_nic_t *enp,
145	__in			uint32_t partn);
146
147extern	__checkReturn		efx_rc_t
148siena_nvram_partn_unlock(
149	__in			efx_nic_t *enp,
150	__in			uint32_t partn);
151
152extern	__checkReturn		efx_rc_t
153siena_nvram_get_dynamic_cfg(
154	__in			efx_nic_t *enp,
155	__in			uint32_t partn,
156	__in			boolean_t vpd,
157	__out			siena_mc_dynamic_config_hdr_t **dcfgp,
158	__out			size_t *sizep);
159
160#endif	/* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
161
162#if EFSYS_OPT_NVRAM
163
164#if EFSYS_OPT_DIAG
165
166extern	__checkReturn		efx_rc_t
167siena_nvram_test(
168	__in			efx_nic_t *enp);
169
170#endif	/* EFSYS_OPT_DIAG */
171
172extern	__checkReturn		efx_rc_t
173siena_nvram_get_subtype(
174	__in			efx_nic_t *enp,
175	__in			uint32_t partn,
176	__out			uint32_t *subtypep);
177
178extern	__checkReturn		efx_rc_t
179siena_nvram_type_to_partn(
180	__in			efx_nic_t *enp,
181	__in			efx_nvram_type_t type,
182	__out			uint32_t *partnp);
183
184extern	__checkReturn		efx_rc_t
185siena_nvram_partn_size(
186	__in			efx_nic_t *enp,
187	__in			uint32_t partn,
188	__out			size_t *sizep);
189
190extern	__checkReturn		efx_rc_t
191siena_nvram_partn_rw_start(
192	__in			efx_nic_t *enp,
193	__in			uint32_t partn,
194	__out			size_t *chunk_sizep);
195
196extern	__checkReturn		efx_rc_t
197siena_nvram_partn_read(
198	__in			efx_nic_t *enp,
199	__in			uint32_t partn,
200	__in			unsigned int offset,
201	__out_bcount(size)	caddr_t data,
202	__in			size_t size);
203
204extern	__checkReturn		efx_rc_t
205siena_nvram_partn_erase(
206	__in			efx_nic_t *enp,
207	__in			uint32_t partn,
208	__in			unsigned int offset,
209	__in			size_t size);
210
211extern	__checkReturn		efx_rc_t
212siena_nvram_partn_write(
213	__in			efx_nic_t *enp,
214	__in			uint32_t partn,
215	__in			unsigned int offset,
216	__out_bcount(size)	caddr_t data,
217	__in			size_t size);
218
219extern	__checkReturn		efx_rc_t
220siena_nvram_partn_rw_finish(
221	__in			efx_nic_t *enp,
222	__in			uint32_t partn);
223
224extern	__checkReturn		efx_rc_t
225siena_nvram_partn_get_version(
226	__in			efx_nic_t *enp,
227	__in			uint32_t partn,
228	__out			uint32_t *subtypep,
229	__out_ecount(4)		uint16_t version[4]);
230
231extern	__checkReturn		efx_rc_t
232siena_nvram_partn_set_version(
233	__in			efx_nic_t *enp,
234	__in			uint32_t partn,
235	__in_ecount(4)		uint16_t version[4]);
236
237#endif	/* EFSYS_OPT_NVRAM */
238
239#if EFSYS_OPT_VPD
240
241extern	__checkReturn		efx_rc_t
242siena_vpd_init(
243	__in			efx_nic_t *enp);
244
245extern	__checkReturn		efx_rc_t
246siena_vpd_size(
247	__in			efx_nic_t *enp,
248	__out			size_t *sizep);
249
250extern	__checkReturn		efx_rc_t
251siena_vpd_read(
252	__in			efx_nic_t *enp,
253	__out_bcount(size)	caddr_t data,
254	__in			size_t size);
255
256extern	__checkReturn		efx_rc_t
257siena_vpd_verify(
258	__in			efx_nic_t *enp,
259	__in_bcount(size)	caddr_t data,
260	__in			size_t size);
261
262extern	__checkReturn		efx_rc_t
263siena_vpd_reinit(
264	__in			efx_nic_t *enp,
265	__in_bcount(size)	caddr_t data,
266	__in			size_t size);
267
268extern	__checkReturn		efx_rc_t
269siena_vpd_get(
270	__in			efx_nic_t *enp,
271	__in_bcount(size)	caddr_t data,
272	__in			size_t size,
273	__inout			efx_vpd_value_t *evvp);
274
275extern	__checkReturn		efx_rc_t
276siena_vpd_set(
277	__in			efx_nic_t *enp,
278	__in_bcount(size)	caddr_t data,
279	__in			size_t size,
280	__in			efx_vpd_value_t *evvp);
281
282extern	__checkReturn		efx_rc_t
283siena_vpd_next(
284	__in			efx_nic_t *enp,
285	__in_bcount(size)	caddr_t data,
286	__in			size_t size,
287	__out			efx_vpd_value_t *evvp,
288	__inout			unsigned int *contp);
289
290extern __checkReturn		efx_rc_t
291siena_vpd_write(
292	__in			efx_nic_t *enp,
293	__in_bcount(size)	caddr_t data,
294	__in			size_t size);
295
296extern				void
297siena_vpd_fini(
298	__in			efx_nic_t *enp);
299
300#endif	/* EFSYS_OPT_VPD */
301
302typedef struct siena_link_state_s {
303	uint32_t		sls_adv_cap_mask;
304	uint32_t		sls_lp_cap_mask;
305	unsigned int		sls_fcntl;
306	efx_link_mode_t		sls_link_mode;
307#if EFSYS_OPT_LOOPBACK
308	efx_loopback_type_t	sls_loopback;
309#endif
310	boolean_t		sls_mac_up;
311} siena_link_state_t;
312
313extern			void
314siena_phy_link_ev(
315	__in		efx_nic_t *enp,
316	__in		efx_qword_t *eqp,
317	__out		efx_link_mode_t *link_modep);
318
319extern	__checkReturn	efx_rc_t
320siena_phy_get_link(
321	__in		efx_nic_t *enp,
322	__out		siena_link_state_t *slsp);
323
324extern	__checkReturn	efx_rc_t
325siena_phy_power(
326	__in		efx_nic_t *enp,
327	__in		boolean_t on);
328
329extern	__checkReturn	efx_rc_t
330siena_phy_reconfigure(
331	__in		efx_nic_t *enp);
332
333extern	__checkReturn	efx_rc_t
334siena_phy_verify(
335	__in		efx_nic_t *enp);
336
337extern	__checkReturn	efx_rc_t
338siena_phy_oui_get(
339	__in		efx_nic_t *enp,
340	__out		uint32_t *ouip);
341
342#if EFSYS_OPT_PHY_STATS
343
344extern						void
345siena_phy_decode_stats(
346	__in					efx_nic_t *enp,
347	__in					uint32_t vmask,
348	__in_opt				efsys_mem_t *esmp,
349	__out_opt				uint64_t *smaskp,
350	__inout_ecount_opt(EFX_PHY_NSTATS)	uint32_t *stat);
351
352extern	__checkReturn			efx_rc_t
353siena_phy_stats_update(
354	__in				efx_nic_t *enp,
355	__in				efsys_mem_t *esmp,
356	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
357
358#endif	/* EFSYS_OPT_PHY_STATS */
359
360#if EFSYS_OPT_BIST
361
362extern	__checkReturn		efx_rc_t
363siena_phy_bist_start(
364	__in			efx_nic_t *enp,
365	__in			efx_bist_type_t type);
366
367extern	__checkReturn		efx_rc_t
368siena_phy_bist_poll(
369	__in			efx_nic_t *enp,
370	__in			efx_bist_type_t type,
371	__out			efx_bist_result_t *resultp,
372	__out_opt __drv_when(count > 0, __notnull)
373	uint32_t	*value_maskp,
374	__out_ecount_opt(count)	__drv_when(count > 0, __notnull)
375	unsigned long	*valuesp,
376	__in			size_t count);
377
378extern				void
379siena_phy_bist_stop(
380	__in			efx_nic_t *enp,
381	__in			efx_bist_type_t type);
382
383#endif	/* EFSYS_OPT_BIST */
384
385extern	__checkReturn	efx_rc_t
386siena_mac_poll(
387	__in		efx_nic_t *enp,
388	__out		efx_link_mode_t *link_modep);
389
390extern	__checkReturn	efx_rc_t
391siena_mac_up(
392	__in		efx_nic_t *enp,
393	__out		boolean_t *mac_upp);
394
395extern	__checkReturn	efx_rc_t
396siena_mac_reconfigure(
397	__in	efx_nic_t *enp);
398
399extern	__checkReturn	efx_rc_t
400siena_mac_pdu_get(
401	__in	efx_nic_t *enp,
402	__out	size_t *pdu);
403
404#if EFSYS_OPT_LOOPBACK
405
406extern	__checkReturn	efx_rc_t
407siena_mac_loopback_set(
408	__in		efx_nic_t *enp,
409	__in		efx_link_mode_t link_mode,
410	__in		efx_loopback_type_t loopback_type);
411
412#endif	/* EFSYS_OPT_LOOPBACK */
413
414#if EFSYS_OPT_MAC_STATS
415
416extern	__checkReturn			efx_rc_t
417siena_mac_stats_get_mask(
418	__in				efx_nic_t *enp,
419	__inout_bcount(mask_size)	uint32_t *maskp,
420	__in				size_t mask_size);
421
422extern	__checkReturn			efx_rc_t
423siena_mac_stats_update(
424	__in				efx_nic_t *enp,
425	__in				efsys_mem_t *esmp,
426	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
427	__inout_opt			uint32_t *generationp);
428
429#endif	/* EFSYS_OPT_MAC_STATS */
430
431#ifdef	__cplusplus
432}
433#endif
434
435#endif	/* _SYS_SIENA_IMPL_H */
436