sdhci_pci.c revision 343504
1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/11/sys/dev/sdhci/sdhci_pci.c 343504 2019-01-27 19:04:28Z marius $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/kernel.h> 33#include <sys/lock.h> 34#include <sys/module.h> 35#include <sys/mutex.h> 36#include <sys/resource.h> 37#include <sys/rman.h> 38#include <sys/sysctl.h> 39#include <sys/taskqueue.h> 40 41#include <dev/pci/pcireg.h> 42#include <dev/pci/pcivar.h> 43 44#include <machine/bus.h> 45#include <machine/resource.h> 46 47#include <dev/mmc/bridge.h> 48 49#include <dev/sdhci/sdhci.h> 50 51#include "mmcbr_if.h" 52#include "sdhci_if.h" 53 54/* 55 * PCI registers 56 */ 57#define PCI_SDHCI_IFPIO 0x00 58#define PCI_SDHCI_IFDMA 0x01 59#define PCI_SDHCI_IFVENDOR 0x02 60 61#define PCI_SLOT_INFO 0x40 /* 8 bits */ 62#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 63#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 64 65/* 66 * RICOH specific PCI registers 67 */ 68#define SDHC_PCI_MODE_KEY 0xf9 69#define SDHC_PCI_MODE 0x150 70#define SDHC_PCI_MODE_SD20 0x10 71#define SDHC_PCI_BASE_FREQ_KEY 0xfc 72#define SDHC_PCI_BASE_FREQ 0xe1 73 74static const struct sdhci_device { 75 uint32_t model; 76 uint16_t subvendor; 77 const char *desc; 78 u_int quirks; 79} sdhci_devices[] = { 80 { 0x08221180, 0xffff, "RICOH R5C822 SD", 81 SDHCI_QUIRK_FORCE_DMA }, 82 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 83 SDHCI_QUIRK_FORCE_DMA | 84 SDHCI_QUIRK_LOWER_FREQUENCY }, 85 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 86 SDHCI_QUIRK_LOWER_FREQUENCY }, 87 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 88 SDHCI_QUIRK_FORCE_DMA }, 89 { 0x05501524, 0xffff, "ENE CB712 SD", 90 SDHCI_QUIRK_BROKEN_TIMINGS }, 91 { 0x05511524, 0xffff, "ENE CB712 SD 2", 92 SDHCI_QUIRK_BROKEN_TIMINGS }, 93 { 0x07501524, 0xffff, "ENE CB714 SD", 94 SDHCI_QUIRK_RESET_ON_IOS | 95 SDHCI_QUIRK_BROKEN_TIMINGS }, 96 { 0x07511524, 0xffff, "ENE CB714 SD 2", 97 SDHCI_QUIRK_RESET_ON_IOS | 98 SDHCI_QUIRK_BROKEN_TIMINGS }, 99 { 0x410111ab, 0xffff, "Marvell CaFe SD", 100 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 101 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 102 SDHCI_QUIRK_32BIT_DMA_SIZE | 103 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 104 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 105 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 106 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 107 /* DDR52 is supported but affected by the VLI54 erratum */ 108 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 109 SDHCI_QUIRK_WAIT_WHILE_BUSY | 110 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 111 SDHCI_QUIRK_PRESET_VALUE_BROKEN}, 112 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 113 SDHCI_QUIRK_WAIT_WHILE_BUSY | 114 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 115 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 116 /* DDR52 is supported but affected by the VLI54 erratum */ 117 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 118 SDHCI_QUIRK_WAIT_WHILE_BUSY | 119 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 120 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 121 { 0x19db8086, 0xffff, "Intel Denverton eMMC 5.0 Controller", 122 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 123 SDHCI_QUIRK_WAIT_WHILE_BUSY | 124 SDHCI_QUIRK_MMC_DDR52 | 125 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 126 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 127 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 128 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | 129 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 130 SDHCI_QUIRK_WAIT_WHILE_BUSY | 131 SDHCI_QUIRK_MMC_DDR52 | 132 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 133 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 134 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 135 SDHCI_QUIRK_WAIT_WHILE_BUSY | 136 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 137 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 138 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 139 SDHCI_QUIRK_WAIT_WHILE_BUSY | 140 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 141 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 142 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 143 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 144 SDHCI_QUIRK_WAIT_WHILE_BUSY | 145 SDHCI_QUIRK_MMC_DDR52 | 146 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 147 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 148 { 0, 0xffff, NULL, 149 0 } 150}; 151 152struct sdhci_pci_softc { 153 u_int quirks; /* Chip specific quirks */ 154 struct resource *irq_res; /* IRQ resource */ 155 void *intrhand; /* Interrupt handle */ 156 157 int num_slots; /* Number of slots on this controller */ 158 struct sdhci_slot slots[6]; 159 struct resource *mem_res[6]; /* Memory resource */ 160 uint8_t cfg_freq; /* Saved frequency */ 161 uint8_t cfg_mode; /* Saved mode */ 162}; 163 164static int sdhci_enable_msi = 1; 165SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 166 0, "Enable MSI interrupts"); 167 168static uint8_t 169sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 170{ 171 struct sdhci_pci_softc *sc = device_get_softc(dev); 172 173 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 174 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 175 return bus_read_1(sc->mem_res[slot->num], off); 176} 177 178static void 179sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, 180 bus_size_t off, uint8_t val) 181{ 182 struct sdhci_pci_softc *sc = device_get_softc(dev); 183 184 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 185 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 186 bus_write_1(sc->mem_res[slot->num], off, val); 187} 188 189static uint16_t 190sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 191{ 192 struct sdhci_pci_softc *sc = device_get_softc(dev); 193 194 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 195 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 196 return bus_read_2(sc->mem_res[slot->num], off); 197} 198 199static void 200sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, 201 bus_size_t off, uint16_t val) 202{ 203 struct sdhci_pci_softc *sc = device_get_softc(dev); 204 205 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 206 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 207 bus_write_2(sc->mem_res[slot->num], off, val); 208} 209 210static uint32_t 211sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 212{ 213 struct sdhci_pci_softc *sc = device_get_softc(dev); 214 215 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 216 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 217 return bus_read_4(sc->mem_res[slot->num], off); 218} 219 220static void 221sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, 222 bus_size_t off, uint32_t val) 223{ 224 struct sdhci_pci_softc *sc = device_get_softc(dev); 225 226 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 227 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 228 bus_write_4(sc->mem_res[slot->num], off, val); 229} 230 231static void 232sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 233 bus_size_t off, uint32_t *data, bus_size_t count) 234{ 235 struct sdhci_pci_softc *sc = device_get_softc(dev); 236 237 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 238} 239 240static void 241sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 242 bus_size_t off, uint32_t *data, bus_size_t count) 243{ 244 struct sdhci_pci_softc *sc = device_get_softc(dev); 245 246 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 247} 248 249static void sdhci_pci_intr(void *arg); 250 251static void 252sdhci_lower_frequency(device_t dev) 253{ 254 struct sdhci_pci_softc *sc = device_get_softc(dev); 255 256 /* 257 * Enable SD2.0 mode. 258 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 259 */ 260 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 261 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 262 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 263 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 264 265 /* 266 * Some SD/MMC cards don't work with the default base 267 * clock frequency of 200 MHz. Lower it to 50 MHz. 268 */ 269 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 270 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 271 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 272 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 273} 274 275static void 276sdhci_restore_frequency(device_t dev) 277{ 278 struct sdhci_pci_softc *sc = device_get_softc(dev); 279 280 /* Restore mode. */ 281 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 282 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 283 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 284 285 /* Restore frequency. */ 286 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 287 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 288 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 289} 290 291static int 292sdhci_pci_probe(device_t dev) 293{ 294 uint32_t model; 295 uint16_t subvendor; 296 uint8_t class, subclass; 297 int i, result; 298 299 model = (uint32_t)pci_get_device(dev) << 16; 300 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 301 subvendor = pci_get_subvendor(dev); 302 class = pci_get_class(dev); 303 subclass = pci_get_subclass(dev); 304 305 result = ENXIO; 306 for (i = 0; sdhci_devices[i].model != 0; i++) { 307 if (sdhci_devices[i].model == model && 308 (sdhci_devices[i].subvendor == 0xffff || 309 sdhci_devices[i].subvendor == subvendor)) { 310 device_set_desc(dev, sdhci_devices[i].desc); 311 result = BUS_PROBE_DEFAULT; 312 break; 313 } 314 } 315 if (result == ENXIO && class == PCIC_BASEPERIPH && 316 subclass == PCIS_BASEPERIPH_SDHC) { 317 device_set_desc(dev, "Generic SD HCI"); 318 result = BUS_PROBE_GENERIC; 319 } 320 321 return (result); 322} 323 324static int 325sdhci_pci_attach(device_t dev) 326{ 327 struct sdhci_pci_softc *sc = device_get_softc(dev); 328 struct sdhci_slot *slot; 329 uint32_t model; 330 uint16_t subvendor; 331 int bar, err, rid, slots, i; 332 333 model = (uint32_t)pci_get_device(dev) << 16; 334 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 335 subvendor = pci_get_subvendor(dev); 336 /* Apply chip specific quirks. */ 337 for (i = 0; sdhci_devices[i].model != 0; i++) { 338 if (sdhci_devices[i].model == model && 339 (sdhci_devices[i].subvendor == 0xffff || 340 sdhci_devices[i].subvendor == subvendor)) { 341 sc->quirks = sdhci_devices[i].quirks; 342 break; 343 } 344 } 345 sc->quirks &= ~sdhci_quirk_clear; 346 sc->quirks |= sdhci_quirk_set; 347 348 /* Some controllers need to be bumped into the right mode. */ 349 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 350 sdhci_lower_frequency(dev); 351 /* Read slots info from PCI registers. */ 352 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 353 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 354 slots = PCI_SLOT_INFO_SLOTS(slots); 355 if (slots > 6 || bar > 5) { 356 device_printf(dev, "Incorrect slots information (%d, %d).\n", 357 slots, bar); 358 return (EINVAL); 359 } 360 /* Allocate IRQ. */ 361 i = 1; 362 rid = 0; 363 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 364 rid = 1; 365 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 366 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 367 if (sc->irq_res == NULL) { 368 device_printf(dev, "Can't allocate IRQ\n"); 369 pci_release_msi(dev); 370 return (ENOMEM); 371 } 372 /* Scan all slots. */ 373 for (i = 0; i < slots; i++) { 374 slot = &sc->slots[sc->num_slots]; 375 376 /* Allocate memory. */ 377 rid = PCIR_BAR(bar + i); 378 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 379 &rid, RF_ACTIVE); 380 if (sc->mem_res[i] == NULL) { 381 device_printf(dev, 382 "Can't allocate memory for slot %d\n", i); 383 continue; 384 } 385 386 slot->quirks = sc->quirks; 387 388 if (sdhci_init_slot(dev, slot, i) != 0) 389 continue; 390 391 sc->num_slots++; 392 } 393 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 394 /* Activate the interrupt */ 395 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 396 NULL, sdhci_pci_intr, sc, &sc->intrhand); 397 if (err) 398 device_printf(dev, "Can't setup IRQ\n"); 399 pci_enable_busmaster(dev); 400 /* Process cards detection. */ 401 for (i = 0; i < sc->num_slots; i++) 402 sdhci_start_slot(&sc->slots[i]); 403 404 return (0); 405} 406 407static int 408sdhci_pci_detach(device_t dev) 409{ 410 struct sdhci_pci_softc *sc = device_get_softc(dev); 411 int i; 412 413 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 414 bus_release_resource(dev, SYS_RES_IRQ, 415 rman_get_rid(sc->irq_res), sc->irq_res); 416 pci_release_msi(dev); 417 418 for (i = 0; i < sc->num_slots; i++) { 419 sdhci_cleanup_slot(&sc->slots[i]); 420 bus_release_resource(dev, SYS_RES_MEMORY, 421 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 422 } 423 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 424 sdhci_restore_frequency(dev); 425 return (0); 426} 427 428static int 429sdhci_pci_shutdown(device_t dev) 430{ 431 struct sdhci_pci_softc *sc = device_get_softc(dev); 432 433 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 434 sdhci_restore_frequency(dev); 435 return (0); 436} 437 438static int 439sdhci_pci_suspend(device_t dev) 440{ 441 struct sdhci_pci_softc *sc = device_get_softc(dev); 442 int i, err; 443 444 err = bus_generic_suspend(dev); 445 if (err) 446 return (err); 447 for (i = 0; i < sc->num_slots; i++) 448 sdhci_generic_suspend(&sc->slots[i]); 449 return (0); 450} 451 452static int 453sdhci_pci_resume(device_t dev) 454{ 455 struct sdhci_pci_softc *sc = device_get_softc(dev); 456 int i, err; 457 458 for (i = 0; i < sc->num_slots; i++) 459 sdhci_generic_resume(&sc->slots[i]); 460 err = bus_generic_resume(dev); 461 if (err) 462 return (err); 463 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 464 sdhci_lower_frequency(dev); 465 return (0); 466} 467 468static void 469sdhci_pci_intr(void *arg) 470{ 471 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 472 int i; 473 474 for (i = 0; i < sc->num_slots; i++) 475 sdhci_generic_intr(&sc->slots[i]); 476} 477 478static device_method_t sdhci_methods[] = { 479 /* device_if */ 480 DEVMETHOD(device_probe, sdhci_pci_probe), 481 DEVMETHOD(device_attach, sdhci_pci_attach), 482 DEVMETHOD(device_detach, sdhci_pci_detach), 483 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 484 DEVMETHOD(device_suspend, sdhci_pci_suspend), 485 DEVMETHOD(device_resume, sdhci_pci_resume), 486 487 /* Bus interface */ 488 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 489 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 490 491 /* mmcbr_if */ 492 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 493 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), 494 DEVMETHOD(mmcbr_tune, sdhci_generic_tune), 495 DEVMETHOD(mmcbr_retune, sdhci_generic_retune), 496 DEVMETHOD(mmcbr_request, sdhci_generic_request), 497 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 498 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 499 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 500 501 /* SDHCI accessors */ 502 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 503 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 504 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 505 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 506 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 507 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 508 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 509 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 510 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing), 511 512 DEVMETHOD_END 513}; 514 515static driver_t sdhci_pci_driver = { 516 "sdhci_pci", 517 sdhci_methods, 518 sizeof(struct sdhci_pci_softc), 519}; 520static devclass_t sdhci_pci_devclass; 521 522DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 523 NULL); 524SDHCI_DEPEND(sdhci_pci); 525MMC_DECLARE_BRIDGE(sdhci_pci); 526