fsl_sdhci.c revision 331501
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/dev/sdhci/fsl_sdhci.c 331501 2018-03-24 22:39:38Z ian $"); 29 30/* 31 * SDHCI driver glue for Freescale i.MX SoC and QorIQ families. 32 * 33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). 34 */ 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/types.h> 39#include <sys/bus.h> 40#include <sys/callout.h> 41#include <sys/kernel.h> 42#include <sys/libkern.h> 43#include <sys/lock.h> 44#include <sys/malloc.h> 45#include <sys/module.h> 46#include <sys/mutex.h> 47#include <sys/resource.h> 48#include <sys/rman.h> 49#include <sys/sysctl.h> 50#include <sys/taskqueue.h> 51#include <sys/time.h> 52 53#include <machine/bus.h> 54#include <machine/resource.h> 55#ifdef __arm__ 56#include <machine/intr.h> 57 58#include <arm/freescale/imx/imx_ccmvar.h> 59#endif 60 61#include <dev/gpio/gpiobusvar.h> 62 63#include <dev/ofw/ofw_bus.h> 64#include <dev/ofw/ofw_bus_subr.h> 65 66#include <dev/mmc/bridge.h> 67 68#include <dev/sdhci/sdhci.h> 69#include <dev/sdhci/sdhci_fdt_gpio.h> 70 71#include "mmcbr_if.h" 72#include "sdhci_if.h" 73 74struct fsl_sdhci_softc { 75 device_t dev; 76 struct resource * mem_res; 77 struct resource * irq_res; 78 void * intr_cookie; 79 struct sdhci_slot slot; 80 struct callout r1bfix_callout; 81 sbintime_t r1bfix_timeout_at; 82 struct sdhci_fdt_gpio * gpio; 83 uint32_t baseclk_hz; 84 uint32_t cmd_and_mode; 85 uint32_t r1bfix_intmask; 86 uint16_t sdclockreg_freq_bits; 87 uint8_t r1bfix_type; 88 uint8_t hwtype; 89 bool slot_init_done; 90}; 91 92#define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ 93#define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ 94#define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ 95 96#define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ 97#define HWTYPE_ESDHC 1 /* fsl5x and earlier. */ 98#define HWTYPE_USDHC 2 /* fsl6. */ 99 100/* 101 * Freescale-specific registers, or in some cases the layout of bits within the 102 * sdhci-defined register is different on Freescale. These names all begin with 103 * SDHC_ (not SDHCI_). 104 */ 105 106#define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ 107#define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ 108#define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ 109#define SDHC_VEND_FRC_SDCLK_ON (1 << 8) 110#define SDHC_VEND_IPGEN (1 << 11) 111#define SDHC_VEND_HCKEN (1 << 12) 112#define SDHC_VEND_PEREN (1 << 13) 113 114#define SDHC_PRES_STATE 0x24 115#define SDHC_PRES_CIHB (1 << 0) 116#define SDHC_PRES_CDIHB (1 << 1) 117#define SDHC_PRES_DLA (1 << 2) 118#define SDHC_PRES_SDSTB (1 << 3) 119#define SDHC_PRES_IPGOFF (1 << 4) 120#define SDHC_PRES_HCKOFF (1 << 5) 121#define SDHC_PRES_PEROFF (1 << 6) 122#define SDHC_PRES_SDOFF (1 << 7) 123#define SDHC_PRES_WTA (1 << 8) 124#define SDHC_PRES_RTA (1 << 9) 125#define SDHC_PRES_BWEN (1 << 10) 126#define SDHC_PRES_BREN (1 << 11) 127#define SDHC_PRES_RTR (1 << 12) 128#define SDHC_PRES_CINST (1 << 16) 129#define SDHC_PRES_CDPL (1 << 18) 130#define SDHC_PRES_WPSPL (1 << 19) 131#define SDHC_PRES_CLSL (1 << 23) 132#define SDHC_PRES_DLSL_SHIFT 24 133#define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT) 134 135#define SDHC_PROT_CTRL 0x28 136#define SDHC_PROT_LED (1 << 0) 137#define SDHC_PROT_WIDTH_1BIT (0 << 1) 138#define SDHC_PROT_WIDTH_4BIT (1 << 1) 139#define SDHC_PROT_WIDTH_8BIT (2 << 1) 140#define SDHC_PROT_WIDTH_MASK (3 << 1) 141#define SDHC_PROT_D3CD (1 << 3) 142#define SDHC_PROT_EMODE_BIG (0 << 4) 143#define SDHC_PROT_EMODE_HALF (1 << 4) 144#define SDHC_PROT_EMODE_LITTLE (2 << 4) 145#define SDHC_PROT_EMODE_MASK (3 << 4) 146#define SDHC_PROT_SDMA (0 << 8) 147#define SDHC_PROT_ADMA1 (1 << 8) 148#define SDHC_PROT_ADMA2 (2 << 8) 149#define SDHC_PROT_ADMA264 (3 << 8) 150#define SDHC_PROT_DMA_MASK (3 << 8) 151#define SDHC_PROT_CDTL (1 << 6) 152#define SDHC_PROT_CDSS (1 << 7) 153 154#define SDHC_SYS_CTRL 0x2c 155 156/* 157 * The clock enable bits exist in different registers for ESDHC vs USDHC, but 158 * they are the same bits in both cases. The divisor values go into the 159 * standard sdhci clock register, but in different bit positions and meanings 160 than the sdhci spec values. 161 */ 162#define SDHC_CLK_IPGEN (1 << 0) 163#define SDHC_CLK_HCKEN (1 << 1) 164#define SDHC_CLK_PEREN (1 << 2) 165#define SDHC_CLK_SDCLKEN (1 << 3) 166#define SDHC_CLK_ENABLE_MASK 0x0000000f 167#define SDHC_CLK_DIVISOR_MASK 0x000000f0 168#define SDHC_CLK_DIVISOR_SHIFT 4 169#define SDHC_CLK_PRESCALE_MASK 0x0000ff00 170#define SDHC_CLK_PRESCALE_SHIFT 8 171 172static struct ofw_compat_data compat_data[] = { 173 {"fsl,imx6q-usdhc", HWTYPE_USDHC}, 174 {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, 175 {"fsl,imx53-esdhc", HWTYPE_ESDHC}, 176 {"fsl,imx51-esdhc", HWTYPE_ESDHC}, 177 {"fsl,esdhc", HWTYPE_ESDHC}, 178 {NULL, HWTYPE_NONE}, 179}; 180 181static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc); 182static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val); 183static void fsl_sdhci_r1bfix_func(void *arg); 184 185static inline uint32_t 186RD4(struct fsl_sdhci_softc *sc, bus_size_t off) 187{ 188 189 return (bus_read_4(sc->mem_res, off)); 190} 191 192static inline void 193WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) 194{ 195 196 bus_write_4(sc->mem_res, off, val); 197} 198 199static uint8_t 200fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 201{ 202 struct fsl_sdhci_softc *sc = device_get_softc(dev); 203 uint32_t val32, wrk32; 204 205 /* 206 * Most of the things in the standard host control register are in the 207 * hardware's wider protocol control register, but some of the bits are 208 * moved around. 209 */ 210 if (off == SDHCI_HOST_CONTROL) { 211 wrk32 = RD4(sc, SDHC_PROT_CTRL); 212 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 213 SDHCI_CTRL_FORCE_CARD); 214 switch (wrk32 & SDHC_PROT_WIDTH_MASK) { 215 case SDHC_PROT_WIDTH_1BIT: 216 /* Value is already 0. */ 217 break; 218 case SDHC_PROT_WIDTH_4BIT: 219 val32 |= SDHCI_CTRL_4BITBUS; 220 break; 221 case SDHC_PROT_WIDTH_8BIT: 222 val32 |= SDHCI_CTRL_8BITBUS; 223 break; 224 } 225 switch (wrk32 & SDHC_PROT_DMA_MASK) { 226 case SDHC_PROT_SDMA: 227 /* Value is already 0. */ 228 break; 229 case SDHC_PROT_ADMA1: 230 /* This value is deprecated, should never appear. */ 231 break; 232 case SDHC_PROT_ADMA2: 233 val32 |= SDHCI_CTRL_ADMA2; 234 break; 235 case SDHC_PROT_ADMA264: 236 val32 |= SDHCI_CTRL_ADMA264; 237 break; 238 } 239 return val32; 240 } 241 242 /* 243 * XXX can't find the bus power on/off knob. For now we have to say the 244 * power is always on and always set to the same voltage. 245 */ 246 if (off == SDHCI_POWER_CONTROL) { 247 return (SDHCI_POWER_ON | SDHCI_POWER_300); 248 } 249 250 251 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 252} 253 254static uint16_t 255fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 256{ 257 struct fsl_sdhci_softc *sc = device_get_softc(dev); 258 uint32_t val32; 259 260 if (sc->hwtype == HWTYPE_USDHC) { 261 /* 262 * The USDHC hardware has nothing in the version register, but 263 * it's v3 compatible with all our translation code. 264 */ 265 if (off == SDHCI_HOST_VERSION) { 266 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); 267 } 268 /* 269 * The USDHC hardware moved the transfer mode bits to the mixed 270 * control register, fetch them from there. 271 */ 272 if (off == SDHCI_TRANSFER_MODE) 273 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); 274 275 } else if (sc->hwtype == HWTYPE_ESDHC) { 276 277 /* 278 * The ESDHC hardware has the typical 32-bit combined "command 279 * and mode" register that we have to cache so that command 280 * isn't written until after mode. On a read, just retrieve the 281 * cached values last written. 282 */ 283 if (off == SDHCI_TRANSFER_MODE) { 284 return (sc->cmd_and_mode & 0x0000ffff); 285 } else if (off == SDHCI_COMMAND_FLAGS) { 286 return (sc->cmd_and_mode >> 16); 287 } 288 } 289 290 /* 291 * This hardware only manages one slot. Synthesize a slot interrupt 292 * status register... if there are any enabled interrupts active they 293 * must be coming from our one and only slot. 294 */ 295 if (off == SDHCI_SLOT_INT_STATUS) { 296 val32 = RD4(sc, SDHCI_INT_STATUS); 297 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 298 return (val32 ? 1 : 0); 299 } 300 301 /* 302 * Clock bits are scattered into various registers which differ by 303 * hardware type, complex enough to have their own function. 304 */ 305 if (off == SDHCI_CLOCK_CONTROL) { 306 return (fsl_sdhc_get_clock(sc)); 307 } 308 309 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 310} 311 312static uint32_t 313fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 314{ 315 struct fsl_sdhci_softc *sc = device_get_softc(dev); 316 uint32_t val32, wrk32; 317 318 val32 = RD4(sc, off); 319 320 /* 321 * The hardware leaves the base clock frequency out of the capabilities 322 * register, but we filled it in by setting slot->max_clk at attach time 323 * rather than here, because we can't represent frequencies above 63MHz 324 * in an sdhci 2.0 capabliities register. The timeout clock is the same 325 * as the active output sdclock; we indicate that with a quirk setting 326 * so don't populate the timeout frequency bits. 327 * 328 * XXX Turn off (for now) features the hardware can do but this driver 329 * doesn't yet handle (1.8v, suspend/resume, etc). 330 */ 331 if (off == SDHCI_CAPABILITIES) { 332 val32 &= ~SDHCI_CAN_VDD_180; 333 val32 &= ~SDHCI_CAN_DO_SUSPEND; 334 val32 |= SDHCI_CAN_DO_8BITBUS; 335 return (val32); 336 } 337 338 /* 339 * The hardware moves bits around in the present state register to make 340 * room for all 8 data line state bits. To translate, mask out all the 341 * bits which are not in the same position in both registers (this also 342 * masks out some Freescale-specific bits in locations defined as 343 * reserved by sdhci), then shift the data line and retune request bits 344 * down to their standard locations. 345 */ 346 if (off == SDHCI_PRESENT_STATE) { 347 wrk32 = val32; 348 val32 &= 0x000F0F07; 349 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 350 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST; 351 return (val32); 352 } 353 354 /* 355 * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a 356 * command with an R1B response, mix it into the hardware status. 357 */ 358 if (off == SDHCI_INT_STATUS) { 359 return (val32 | sc->r1bfix_intmask); 360 } 361 362 return val32; 363} 364 365static void 366fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 367 uint32_t *data, bus_size_t count) 368{ 369 struct fsl_sdhci_softc *sc = device_get_softc(dev); 370 371 bus_read_multi_4(sc->mem_res, off, data, count); 372} 373 374static void 375fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 376{ 377 struct fsl_sdhci_softc *sc = device_get_softc(dev); 378 uint32_t val32; 379 380 /* 381 * Most of the things in the standard host control register are in the 382 * hardware's wider protocol control register, but some of the bits are 383 * moved around. 384 */ 385 if (off == SDHCI_HOST_CONTROL) { 386 val32 = RD4(sc, SDHC_PROT_CTRL); 387 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | 388 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); 389 val32 |= (val & SDHCI_CTRL_LED); 390 if (val & SDHCI_CTRL_8BITBUS) 391 val32 |= SDHC_PROT_WIDTH_8BIT; 392 else 393 val32 |= (val & SDHCI_CTRL_4BITBUS); 394 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; 395 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); 396 WR4(sc, SDHC_PROT_CTRL, val32); 397 return; 398 } 399 400 /* XXX I can't find the bus power on/off knob; do nothing. */ 401 if (off == SDHCI_POWER_CONTROL) { 402 return; 403 } 404#ifdef __powerpc__ 405 /* XXX Reset doesn't seem to work as expected. Do nothing for now. */ 406 if (off == SDHCI_SOFTWARE_RESET) 407 return; 408#endif 409 410 val32 = RD4(sc, off & ~3); 411 val32 &= ~(0xff << (off & 3) * 8); 412 val32 |= (val << (off & 3) * 8); 413 414 WR4(sc, off & ~3, val32); 415} 416 417static void 418fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 419{ 420 struct fsl_sdhci_softc *sc = device_get_softc(dev); 421 uint32_t val32; 422 423 /* 424 * The clock control stuff is complex enough to have its own function 425 * that can handle the ESDHC versus USDHC differences. 426 */ 427 if (off == SDHCI_CLOCK_CONTROL) { 428 fsl_sdhc_set_clock(sc, val); 429 return; 430 } 431 432 /* 433 * Figure out whether we need to check the DAT0 line for busy status at 434 * interrupt time. The controller should be doing this, but for some 435 * reason it doesn't. There are two cases: 436 * - R1B response with no data transfer should generate a DATA_END (aka 437 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if 438 * there's no data transfer there's no DATA_END interrupt. This is 439 * documented; they seem to think it's a feature. 440 * - R1B response after Auto-CMD12 appears to not work, even though 441 * there's a control bit for it (bit 3) in the vendor register. 442 * When we're starting a command that needs a manual DAT0 line check at 443 * interrupt time, we leave ourselves a note in r1bfix_type so that we 444 * can do the extra work in fsl_sdhci_intr(). 445 */ 446 if (off == SDHCI_COMMAND_FLAGS) { 447 if (val & SDHCI_CMD_DATA) { 448 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; 449 val32 = RD4(sc, USDHC_MIX_CONTROL); 450 if ((val32 & MBAUTOCMD) == MBAUTOCMD) 451 sc->r1bfix_type = R1BFIX_AC12; 452 } else { 453 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { 454 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 455 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 456 sc->r1bfix_type = R1BFIX_NODATA; 457 } 458 } 459 } 460 461 /* 462 * The USDHC hardware moved the transfer mode bits to mixed control; we 463 * just write them there and we're done. The ESDHC hardware has the 464 * typical combined cmd-and-mode register that allows only 32-bit 465 * access, so when writing the mode bits just save them, then later when 466 * writing the command bits, add in the saved mode bits. 467 */ 468 if (sc->hwtype == HWTYPE_USDHC) { 469 if (off == SDHCI_TRANSFER_MODE) { 470 val32 = RD4(sc, USDHC_MIX_CONTROL); 471 val32 &= ~0x3f; 472 val32 |= val & 0x37; 473 // XXX acmd23 not supported here (or by sdhci driver) 474 WR4(sc, USDHC_MIX_CONTROL, val32); 475 return; 476 } 477 } else if (sc->hwtype == HWTYPE_ESDHC) { 478 if (off == SDHCI_TRANSFER_MODE) { 479 sc->cmd_and_mode = 480 (sc->cmd_and_mode & 0xffff0000) | val; 481 return; 482 } else if (off == SDHCI_COMMAND_FLAGS) { 483 sc->cmd_and_mode = 484 (sc->cmd_and_mode & 0xffff) | (val << 16); 485 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 486 return; 487 } 488 } 489 490 val32 = RD4(sc, off & ~3); 491 val32 &= ~(0xffff << (off & 3) * 8); 492 val32 |= ((val & 0xffff) << (off & 3) * 8); 493 WR4(sc, off & ~3, val32); 494} 495 496static void 497fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 498{ 499 struct fsl_sdhci_softc *sc = device_get_softc(dev); 500 501 /* Clear synthesized interrupts, then pass the value to the hardware. */ 502 if (off == SDHCI_INT_STATUS) { 503 sc->r1bfix_intmask &= ~val; 504 } 505 506 WR4(sc, off, val); 507} 508 509static void 510fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 511 uint32_t *data, bus_size_t count) 512{ 513 struct fsl_sdhci_softc *sc = device_get_softc(dev); 514 515 bus_write_multi_4(sc->mem_res, off, data, count); 516} 517 518static uint16_t 519fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc) 520{ 521 uint16_t val; 522 523 /* 524 * Whenever the sdhci driver writes the clock register we save a 525 * snapshot of just the frequency bits, so that we can play them back 526 * here on a register read without recalculating the frequency from the 527 * prescalar and divisor bits in the real register. We'll start with 528 * those bits, and mix in the clock status and enable bits that come 529 * from different places depending on which hardware we've got. 530 */ 531 val = sc->sdclockreg_freq_bits; 532 533 /* 534 * The internal clock is always enabled (actually, the hardware manages 535 * it). Whether the internal clock is stable yet after a frequency 536 * change comes from the present-state register on both hardware types. 537 */ 538 val |= SDHCI_CLOCK_INT_EN; 539 if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB) 540 val |= SDHCI_CLOCK_INT_STABLE; 541 542 /* 543 * On i.MX ESDHC hardware the card bus clock enable is in the usual 544 * sdhci register but it's a different bit, so transcribe it (note the 545 * difference between standard SDHCI_ and Freescale SDHC_ prefixes 546 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but 547 * no force-off for the card bus clock (the hardware runs the clock when 548 * transfers are active no matter what), so we always say the clock is 549 * on. 550 * XXX Maybe we should say it's in whatever state the sdhci driver last 551 * set it to. 552 */ 553 if (sc->hwtype == HWTYPE_ESDHC) { 554#ifdef __arm__ 555 if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN) 556#endif 557 val |= SDHCI_CLOCK_CARD_EN; 558 } else { 559 val |= SDHCI_CLOCK_CARD_EN; 560 } 561 562 return (val); 563} 564 565static void 566fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val) 567{ 568 uint32_t divisor, freq, prescale, val32; 569 570 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 571 572 /* 573 * Save the frequency-setting bits in SDHCI format so that we can play 574 * them back in get_clock without complex decoding of hardware regs, 575 * then deal with the freqency part of the value based on hardware type. 576 */ 577 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK; 578 if (sc->hwtype == HWTYPE_ESDHC) { 579 /* 580 * The i.MX5 ESDHC hardware requires the driver to manually 581 * start and stop the sd bus clock. If the enable bit is not 582 * set, turn off the clock in hardware and we're done, otherwise 583 * decode the requested frequency. ESDHC hardware is sdhci 2.0; 584 * the sdhci driver will use the original 8-bit divisor field 585 * and the "base / 2^N" divisor scheme. 586 */ 587 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 588#ifdef __arm__ 589 /* On QorIQ, this is a reserved bit. */ 590 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN); 591#endif 592 return; 593 594 } 595 divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 596 freq = sc->baseclk_hz >> ffs(divisor); 597 } else { 598 /* 599 * The USDHC hardware provides only "force always on" control 600 * over the sd bus clock, but no way to turn it off. (If a cmd 601 * or data transfer is in progress the clock is on, otherwise it 602 * is off.) If the clock is being disabled, we can just return 603 * now, otherwise we decode the requested frequency. USDHC 604 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit 605 * divisor using the "base / 2*N" divisor scheme. 606 */ 607 if ((val & SDHCI_CLOCK_CARD_EN) == 0) 608 return; 609 divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) | 610 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << 611 SDHCI_DIVIDER_MASK_LEN; 612 if (divisor == 0) 613 freq = sc->baseclk_hz; 614 else 615 freq = sc->baseclk_hz / (2 * divisor); 616 } 617 618 /* 619 * Get a prescaler and final divisor to achieve the desired frequency. 620 */ 621 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) 622 prescale <<= 1; 623 624 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) 625 ++divisor; 626 627#ifdef DEBUG 628 device_printf(sc->dev, 629 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n", 630 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, 631 prescale, divisor); 632#endif 633 634 /* 635 * Adjust to zero-based values, and store them to the hardware. 636 */ 637 prescale >>= 1; 638 divisor -= 1; 639 640 val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK); 641 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; 642 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; 643 val32 |= SDHC_CLK_IPGEN; 644 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 645} 646 647static boolean_t 648fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc) 649{ 650 uint32_t inhibit; 651 652 mtx_assert(&sc->slot.mtx, MA_OWNED); 653 654 /* 655 * Check the DAT0 line status using both the DLA (data line active) and 656 * CDIHB (data inhibit) bits in the present state register. In theory 657 * just DLA should do the trick, but in practice it takes both. If the 658 * DAT0 line is still being held and we're not yet beyond the timeout 659 * point, just schedule another callout to check again later. 660 */ 661 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB); 662 663 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { 664 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, 665 fsl_sdhci_r1bfix_func, sc, 0); 666 return (false); 667 } 668 669 /* 670 * If we reach this point with the inhibit bits still set, we've got a 671 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0 672 * line has been released, and we synthesize a DATA_END, and if the type 673 * of fix needed was on a command-without-data we also now add in the 674 * original INT_RESPONSE that we suppressed earlier. 675 */ 676 if (inhibit) 677 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; 678 else { 679 sc->r1bfix_intmask |= SDHCI_INT_DATA_END; 680 if (sc->r1bfix_type == R1BFIX_NODATA) 681 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; 682 } 683 684 sc->r1bfix_type = R1BFIX_NONE; 685 return (true); 686} 687 688static void 689fsl_sdhci_r1bfix_func(void * arg) 690{ 691 struct fsl_sdhci_softc *sc = arg; 692 boolean_t r1bwait_done; 693 694 mtx_lock(&sc->slot.mtx); 695 r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc); 696 mtx_unlock(&sc->slot.mtx); 697 if (r1bwait_done) 698 sdhci_generic_intr(&sc->slot); 699} 700 701static void 702fsl_sdhci_intr(void *arg) 703{ 704 struct fsl_sdhci_softc *sc = arg; 705 uint32_t intmask; 706 707 mtx_lock(&sc->slot.mtx); 708 709 /* 710 * Manually check the DAT0 line for R1B response types that the 711 * controller fails to handle properly. The controller asserts the done 712 * interrupt while the card is still asserting busy with the DAT0 line. 713 * 714 * We check DAT0 immediately because most of the time, especially on a 715 * read, the card will actually be done by time we get here. If it's 716 * not, then the wait_done routine will schedule a callout to re-check 717 * periodically until it is done. In that case we clear the interrupt 718 * out of the hardware now so that we can present it later when the DAT0 719 * line is released. 720 * 721 * If we need to wait for the DAT0 line to be released, we set up a 722 * timeout point 250ms in the future. This number comes from the SD 723 * spec, which allows a command to take that long. In the real world, 724 * cards tend to take 10-20ms for a long-running command such as a write 725 * or erase that spans two pages. 726 */ 727 switch (sc->r1bfix_type) { 728 case R1BFIX_NODATA: 729 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE; 730 break; 731 case R1BFIX_AC12: 732 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END; 733 break; 734 default: 735 intmask = 0; 736 break; 737 } 738 if (intmask) { 739 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; 740 if (!fsl_sdhci_r1bfix_is_wait_done(sc)) { 741 WR4(sc, SDHCI_INT_STATUS, intmask); 742 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4, 743 BUS_SPACE_BARRIER_WRITE); 744 } 745 } 746 747 mtx_unlock(&sc->slot.mtx); 748 sdhci_generic_intr(&sc->slot); 749} 750 751static int 752fsl_sdhci_get_ro(device_t bus, device_t child) 753{ 754 struct fsl_sdhci_softc *sc = device_get_softc(bus); 755 756 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 757} 758 759static bool 760fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) 761{ 762 struct fsl_sdhci_softc *sc = device_get_softc(dev); 763 764 return (sdhci_fdt_gpio_get_present(sc->gpio)); 765} 766 767#ifdef __powerpc__ 768static uint32_t 769fsl_sdhci_get_platform_clock(device_t dev) 770{ 771 device_t parent; 772 phandle_t node; 773 uint32_t clock; 774 775 node = ofw_bus_get_node(dev); 776 777 /* Get sdhci node properties */ 778 if((OF_getprop(node, "clock-frequency", (void *)&clock, 779 sizeof(clock)) <= 0) || (clock == 0)) { 780 781 /* 782 * Trying to get clock from parent device (soc) if correct 783 * clock cannot be acquired from sdhci node. 784 */ 785 parent = device_get_parent(dev); 786 node = ofw_bus_get_node(parent); 787 788 /* Get soc properties */ 789 if ((OF_getprop(node, "bus-frequency", (void *)&clock, 790 sizeof(clock)) <= 0) || (clock == 0)) { 791 device_printf(dev,"Cannot acquire correct sdhci " 792 "frequency from DTS.\n"); 793 794 return (0); 795 } 796 /* eSDHC clock is 1/2 platform clock. */ 797 clock /= 2; 798 } 799 800 if (bootverbose) 801 device_printf(dev, "Acquired clock: %d from DTS\n", clock); 802 803 return (clock); 804} 805#endif 806 807 808static int 809fsl_sdhci_detach(device_t dev) 810{ 811 struct fsl_sdhci_softc *sc = device_get_softc(dev); 812 813 if (sc->gpio != NULL) 814 sdhci_fdt_gpio_teardown(sc->gpio); 815 816 callout_drain(&sc->r1bfix_callout); 817 818 if (sc->slot_init_done) 819 sdhci_cleanup_slot(&sc->slot); 820 821 if (sc->intr_cookie != NULL) 822 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 823 if (sc->irq_res != NULL) 824 bus_release_resource(dev, SYS_RES_IRQ, 825 rman_get_rid(sc->irq_res), sc->irq_res); 826 827 if (sc->mem_res != NULL) { 828 bus_release_resource(dev, SYS_RES_MEMORY, 829 rman_get_rid(sc->mem_res), sc->mem_res); 830 } 831 832 return (0); 833} 834 835static int 836fsl_sdhci_attach(device_t dev) 837{ 838 struct fsl_sdhci_softc *sc = device_get_softc(dev); 839 int rid, err; 840#ifdef __powerpc__ 841 phandle_t node; 842 uint32_t protctl; 843#endif 844 845 sc->dev = dev; 846 847 callout_init(&sc->r1bfix_callout, 1); 848 849 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 850 if (sc->hwtype == HWTYPE_NONE) 851 panic("Impossible: not compatible in fsl_sdhci_attach()"); 852 853 rid = 0; 854 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 855 RF_ACTIVE); 856 if (!sc->mem_res) { 857 device_printf(dev, "cannot allocate memory window\n"); 858 err = ENXIO; 859 goto fail; 860 } 861 862 rid = 0; 863 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 864 RF_ACTIVE); 865 if (!sc->irq_res) { 866 device_printf(dev, "cannot allocate interrupt\n"); 867 err = ENXIO; 868 goto fail; 869 } 870 871 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 872 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) { 873 device_printf(dev, "cannot setup interrupt handler\n"); 874 err = ENXIO; 875 goto fail; 876 } 877 878 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 879 880 /* 881 * DMA is not really broken, I just haven't implemented it yet. 882 */ 883 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 884 885 /* 886 * Set the buffer watermark level to 128 words (512 bytes) for both read 887 * and write. The hardware has a restriction that when the read or 888 * write ready status is asserted, that means you can read exactly the 889 * number of words set in the watermark register before you have to 890 * re-check the status and potentially wait for more data. The main 891 * sdhci driver provides no hook for doing status checking on less than 892 * a full block boundary, so we set the watermark level to be a full 893 * block. Reads and writes where the block size is less than the 894 * watermark size will work correctly too, no need to change the 895 * watermark for different size blocks. However, 128 is the maximum 896 * allowed for the watermark, so PIO is limitted to 512 byte blocks 897 * (which works fine for SD cards, may be a problem for SDIO some day). 898 * 899 * XXX need named constants for this stuff. 900 */ 901 /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */ 902 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc")) 903 WR4(sc, SDHC_WTMK_LVL, 0x10801080); 904 else 905 WR4(sc, SDHC_WTMK_LVL, 0x08800880); 906 907 /* 908 * We read in native byte order in the main driver, but the register 909 * defaults to little endian. 910 */ 911#ifdef __powerpc__ 912 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev); 913#else 914 sc->baseclk_hz = imx_ccm_sdhci_hz(); 915#endif 916 sc->slot.max_clk = sc->baseclk_hz; 917 918 /* 919 * Set up any gpio pin handling described in the FDT data. This cannot 920 * fail; see comments in sdhci_fdt_gpio.h for details. 921 */ 922 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 923 924#ifdef __powerpc__ 925 node = ofw_bus_get_node(dev); 926 /* Default to big-endian on powerpc */ 927 protctl = RD4(sc, SDHC_PROT_CTRL); 928 protctl &= ~SDHC_PROT_EMODE_MASK; 929 if (OF_hasprop(node, "little-endian")) 930 protctl |= SDHC_PROT_EMODE_LITTLE; 931 else 932 protctl |= SDHC_PROT_EMODE_BIG; 933 WR4(sc, SDHC_PROT_CTRL, protctl); 934#endif 935 936 sdhci_init_slot(dev, &sc->slot, 0); 937 sc->slot_init_done = true; 938 939 bus_generic_probe(dev); 940 bus_generic_attach(dev); 941 942 sdhci_start_slot(&sc->slot); 943 944 return (0); 945 946fail: 947 fsl_sdhci_detach(dev); 948 return (err); 949} 950 951static int 952fsl_sdhci_probe(device_t dev) 953{ 954 955 if (!ofw_bus_status_okay(dev)) 956 return (ENXIO); 957 958 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 959 case HWTYPE_ESDHC: 960 device_set_desc(dev, "Freescale eSDHC controller"); 961 return (BUS_PROBE_DEFAULT); 962 case HWTYPE_USDHC: 963 device_set_desc(dev, "Freescale uSDHC controller"); 964 return (BUS_PROBE_DEFAULT); 965 default: 966 break; 967 } 968 return (ENXIO); 969} 970 971static device_method_t fsl_sdhci_methods[] = { 972 /* Device interface */ 973 DEVMETHOD(device_probe, fsl_sdhci_probe), 974 DEVMETHOD(device_attach, fsl_sdhci_attach), 975 DEVMETHOD(device_detach, fsl_sdhci_detach), 976 977 /* Bus interface */ 978 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 979 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 980 981 /* MMC bridge interface */ 982 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 983 DEVMETHOD(mmcbr_request, sdhci_generic_request), 984 DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro), 985 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 986 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 987 988 /* SDHCI accessors */ 989 DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1), 990 DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2), 991 DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4), 992 DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4), 993 DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1), 994 DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2), 995 DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4), 996 DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4), 997 DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present), 998 999 DEVMETHOD_END 1000}; 1001 1002static devclass_t fsl_sdhci_devclass; 1003 1004static driver_t fsl_sdhci_driver = { 1005 "sdhci_fsl", 1006 fsl_sdhci_methods, 1007 sizeof(struct fsl_sdhci_softc), 1008}; 1009 1010DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, fsl_sdhci_devclass, 1011 NULL, NULL); 1012MODULE_DEPEND(sdhci_fsl, sdhci, 1, 1, 1); 1013MMC_DECLARE_BRIDGE(sdhci_fsl); 1014