rp_pci.c revision 356020 
1/*-
2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
3 * All rights reserved.
4 *
5 * PCI-specific part separated from:
6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted prodived that the follwoing conditions
10 * are met.
11 * 1. Redistributions of source code must retain the above copyright
12 *    notive, this list of conditions and the following disclainer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials prodided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *       This product includes software developed by Comtrol Corporation.
19 * 4. The name of Comtrol Corporation may not be used to endorse or
20 *    promote products derived from this software without specific
21 *    prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36#include <sys/cdefs.h>
37__FBSDID("$FreeBSD: stable/11/sys/dev/rp/rp_pci.c 356020 2019-12-22 19:06:45Z kevans $");
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/fcntl.h>
42#include <sys/malloc.h>
43#include <sys/conf.h>
44#include <sys/kernel.h>
45#include <sys/lock.h>
46#include <sys/module.h>
47#include <sys/mutex.h>
48#include <machine/resource.h>
49#include <machine/bus.h>
50#include <sys/bus.h>
51#include <sys/rman.h>
52
53#define ROCKET_C
54#include <dev/rp/rpreg.h>
55#include <dev/rp/rpvar.h>
56
57#include <dev/pci/pcireg.h>
58#include <dev/pci/pcivar.h>
59
60/* PCI IDs  */
61#define RP_VENDOR_ID		0x11FE
62#define RP_DEVICE_ID_32I	0x0001
63#define RP_DEVICE_ID_8I		0x0002
64#define RP_DEVICE_ID_16I	0x0003
65#define RP_DEVICE_ID_4Q		0x0004
66#define RP_DEVICE_ID_8O		0x0005
67#define RP_DEVICE_ID_8J		0x0006
68#define RP_DEVICE_ID_4J		0x0007
69#define RP_DEVICE_ID_6M		0x000C
70#define RP_DEVICE_ID_4M		0x000D
71#define RP_DEVICE_ID_UPCI_32	0x0801
72#define RP_DEVICE_ID_UPCI_16	0x0803
73#define RP_DEVICE_ID_UPCI_8O	0x0805
74
75/**************************************************************************
76  MUDBAC remapped for PCI
77**************************************************************************/
78
79#define _CFG_INT_PCI	0x40
80#define _PCI_INT_FUNC	0x3A
81
82#define PCI_STROB	0x2000
83#define INTR_EN_PCI	0x0010
84
85/***************************************************************************
86Function: sPCIControllerEOI
87Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
88Call:	  sPCIControllerEOI(CtlP)
89	  CONTROLLER_T *CtlP; Ptr to controller structure
90*/
91#define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
92
93/***************************************************************************
94Function: sPCIGetControllerIntStatus
95Purpose:  Get the controller interrupt status
96Call:	  sPCIGetControllerIntStatus(CtlP)
97	  CONTROLLER_T *CtlP; Ptr to controller structure
98Return:   Byte_t: The controller interrupt status in the lower 4
99			 bits.	Bits 0 through 3 represent AIOP's 0
100			 through 3 respectively.  If a bit is set that
101			 AIOP is interrupting.	Bits 4 through 7 will
102			 always be cleared.
103*/
104#define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
105
106static devclass_t rp_devclass;
107
108static int rp_pciprobe(device_t dev);
109static int rp_pciattach(device_t dev);
110#ifdef notdef
111static int rp_pcidetach(device_t dev);
112static int rp_pcishutdown(device_t dev);
113#endif /* notdef */
114static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
115static int sPCIInitController( CONTROLLER_t *CtlP,
116			       int AiopNum,
117			       int IRQNum,
118			       Byte_t Frequency,
119			       int PeriodicOnly,
120			       int VendorDevice);
121static rp_aiop2rid_t rp_pci_aiop2rid;
122static rp_aiop2off_t rp_pci_aiop2off;
123static rp_ctlmask_t rp_pci_ctlmask;
124
125/*
126 * The following functions are the pci-specific part
127 * of rp driver.
128 */
129
130static int
131rp_pciprobe(device_t dev)
132{
133	char *s;
134
135	s = NULL;
136	if (pci_get_vendor(dev) == RP_VENDOR_ID)
137		s = "RocketPort PCI";
138
139	if (s != NULL) {
140		device_set_desc(dev, s);
141		return (BUS_PROBE_DEFAULT);
142	}
143
144	return (ENXIO);
145}
146
147static int
148rp_pciattach(device_t dev)
149{
150	int	num_ports, num_aiops;
151	int	aiop;
152	CONTROLLER_t	*ctlp;
153	int	unit;
154	int	retval;
155
156	ctlp = device_get_softc(dev);
157	bzero(ctlp, sizeof(*ctlp));
158	ctlp->dev = dev;
159	unit = device_get_unit(dev);
160	ctlp->aiop2rid = rp_pci_aiop2rid;
161	ctlp->aiop2off = rp_pci_aiop2off;
162	ctlp->ctlmask = rp_pci_ctlmask;
163
164	/* The IO ports of AIOPs for a PCI controller are continuous. */
165	ctlp->io_num = 1;
166	ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
167	ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
168	if (ctlp->io_rid == NULL || ctlp->io == NULL) {
169		device_printf(dev, "rp_pciattach: Out of memory.\n");
170		retval = ENOMEM;
171		goto nogo;
172	}
173
174	ctlp->bus_ctlp = NULL;
175
176	switch (pci_get_device(dev)) {
177	case RP_DEVICE_ID_UPCI_16:
178	case RP_DEVICE_ID_UPCI_32:
179	case RP_DEVICE_ID_UPCI_8O:
180		ctlp->io_rid[0] = PCIR_BAR(2);
181		break;
182	default:
183		ctlp->io_rid[0] = PCIR_BAR(0);
184		break;
185	}
186	ctlp->io[0] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
187		&ctlp->io_rid[0], RF_ACTIVE);
188	if(ctlp->io[0] == NULL) {
189		device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
190		retval = ENXIO;
191		goto nogo;
192	}
193
194	num_aiops = sPCIInitController(ctlp,
195				       MAX_AIOPS_PER_BOARD, 0,
196				       FREQ_DIS, 0, pci_get_device(dev));
197
198	num_ports = 0;
199	for(aiop=0; aiop < num_aiops; aiop++) {
200		sResetAiopByNum(ctlp, aiop);
201		num_ports += sGetAiopNumChan(ctlp, aiop);
202	}
203
204	retval = rp_attachcommon(ctlp, num_aiops, num_ports);
205	if (retval != 0)
206		goto nogo;
207
208	return (0);
209
210nogo:
211	rp_pcireleaseresource(ctlp);
212
213	return (retval);
214}
215
216static int
217rp_pcidetach(device_t dev)
218{
219	CONTROLLER_t	*ctlp;
220
221	ctlp = device_get_softc(dev);
222	rp_pcireleaseresource(ctlp);
223
224	return (0);
225}
226
227static int
228rp_pcishutdown(device_t dev)
229{
230	CONTROLLER_t	*ctlp;
231
232	ctlp = device_get_softc(dev);
233	rp_pcireleaseresource(ctlp);
234
235	return (0);
236}
237
238static void
239rp_pcireleaseresource(CONTROLLER_t *ctlp)
240{
241	rp_releaseresource(ctlp);
242	if (ctlp->io != NULL) {
243		if (ctlp->io[0] != NULL)
244			bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
245		free(ctlp->io, M_DEVBUF);
246		ctlp->io = NULL;
247	}
248	if (ctlp->io_rid != NULL) {
249		free(ctlp->io_rid, M_DEVBUF);
250		ctlp->io = NULL;
251	}
252}
253
254static int
255sPCIInitController( CONTROLLER_t *CtlP,
256		    int AiopNum,
257		    int IRQNum,
258		    Byte_t Frequency,
259		    int PeriodicOnly,
260		    int VendorDevice)
261{
262	int		i;
263
264	CtlP->CtlID = CTLID_0001;	/* controller release 1 */
265
266	sPCIControllerEOI(CtlP);
267
268	/* Init AIOPs */
269	CtlP->NumAiop = 0;
270	for(i=0; i < AiopNum; i++)
271	{
272		/*device_printf(CtlP->dev, "aiop %d.\n", i);*/
273		CtlP->AiopID[i] = sReadAiopID(CtlP, i);	/* read AIOP ID */
274		/*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
275		if(CtlP->AiopID[i] == AIOPID_NULL)	/* if AIOP does not exist */
276		{
277			break;				/* done looking for AIOPs */
278		}
279
280		switch( VendorDevice ) {
281		case RP_DEVICE_ID_4Q:
282		case RP_DEVICE_ID_4J:
283		case RP_DEVICE_ID_4M:
284      			CtlP->AiopNumChan[i] = 4;
285			break;
286		case RP_DEVICE_ID_6M:
287      			CtlP->AiopNumChan[i] = 6;
288			break;
289		case RP_DEVICE_ID_8O:
290		case RP_DEVICE_ID_8J:
291		case RP_DEVICE_ID_8I:
292		case RP_DEVICE_ID_16I:
293		case RP_DEVICE_ID_32I:
294      			CtlP->AiopNumChan[i] = 8;
295			break;
296		default:
297#ifdef notdef
298      			CtlP->AiopNumChan[i] = 8;
299#else
300      			CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
301#endif /* notdef */
302			break;
303		}
304		/*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
305		rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE);	/* clock prescaler */
306		/*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
307		rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
308		/*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
309		CtlP->NumAiop++;				/* bump count of AIOPs */
310	}
311
312	if(CtlP->NumAiop == 0)
313		return(-1);
314	else
315		return(CtlP->NumAiop);
316}
317
318/*
319 * ARGSUSED
320 * Maps (aiop, offset) to rid.
321 */
322static int
323rp_pci_aiop2rid(int aiop, int offset)
324{
325	/* Always return zero for a PCI controller. */
326	return 0;
327}
328
329/*
330 * ARGSUSED
331 * Maps (aiop, offset) to the offset of resource.
332 */
333static int
334rp_pci_aiop2off(int aiop, int offset)
335{
336	/* Each AIOP reserves 0x40 bytes. */
337	return aiop * 0x40 + offset;
338}
339
340/* Read the int status for a PCI controller. */
341static unsigned char
342rp_pci_ctlmask(CONTROLLER_t *ctlp)
343{
344	return sPCIGetControllerIntStatus(ctlp);
345}
346
347static device_method_t rp_pcimethods[] = {
348	/* Device interface */
349	DEVMETHOD(device_probe,		rp_pciprobe),
350	DEVMETHOD(device_attach,	rp_pciattach),
351	DEVMETHOD(device_detach,	rp_pcidetach),
352	DEVMETHOD(device_shutdown,	rp_pcishutdown),
353
354	{ 0, 0 }
355};
356
357static driver_t rp_pcidriver = {
358	"rp",
359	rp_pcimethods,
360	sizeof(CONTROLLER_t),
361};
362
363/*
364 * rp can be attached to a pci bus.
365 */
366DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);
367