if_pcnreg.h revision 331722
1/*- 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: stable/11/sys/dev/pcn/if_pcnreg.h 331722 2018-03-29 02:50:57Z eadler $ 34 */ 35 36/* 37 * I/O map in 16-bit mode. To switch to 32-bit mode, 38 * you need to perform a 32-bit write to the RDP register 39 * (writing a 0 is recommended). 40 */ 41#define PCN_IO16_APROM00 0x00 42#define PCN_IO16_APROM01 0x02 43#define PCN_IO16_APROM02 0x04 44#define PCN_IO16_APROM03 0x06 45#define PCN_IO16_APROM04 0x08 46#define PCN_IO16_APROM05 0x0A 47#define PCN_IO16_APROM06 0x0C 48#define PCN_IO16_APROM07 0x0E 49#define PCN_IO16_RDP 0x10 50#define PCN_IO16_RAP 0x12 51#define PCN_IO16_RESET 0x14 52#define PCN_IO16_BDP 0x16 53 54/* 55 * I/O map in 32-bit mode. 56 */ 57#define PCN_IO32_APROM00 0x00 58#define PCN_IO32_APROM01 0x04 59#define PCN_IO32_APROM02 0x08 60#define PCN_IO32_APROM03 0x0C 61#define PCN_IO32_RDP 0x10 62#define PCN_IO32_RAP 0x14 63#define PCN_IO32_RESET 0x18 64#define PCN_IO32_BDP 0x1C 65 66/* 67 * CSR registers 68 */ 69#define PCN_CSR_CSR 0x00 70#define PCN_CSR_IAB0 0x01 71#define PCN_CSR_IAB1 0x02 72#define PCN_CSR_IMR 0x03 73#define PCN_CSR_TFEAT 0x04 74#define PCN_CSR_EXTCTL1 0x05 75#define PCN_CSR_DTBLLEN 0x06 76#define PCN_CSR_EXTCTL2 0x07 77#define PCN_CSR_MAR0 0x08 78#define PCN_CSR_MAR1 0x09 79#define PCN_CSR_MAR2 0x0A 80#define PCN_CSR_MAR3 0x0B 81#define PCN_CSR_PAR0 0x0C 82#define PCN_CSR_PAR1 0x0D 83#define PCN_CSR_PAR2 0x0E 84#define PCN_CSR_MODE 0x0F 85#define PCN_CSR_RXADDR0 0x18 86#define PCN_CSR_RXADDR1 0x19 87#define PCN_CSR_TXADDR0 0x1E 88#define PCN_CSR_TXADDR1 0x1F 89#define PCN_CSR_TXPOLL 0x2F 90#define PCN_CSR_RXPOLL 0x31 91#define PCN_CSR_RXRINGLEN 0x4C 92#define PCN_CSR_TXRINGLEN 0x4E 93#define PCN_CSR_DMACTL 0x50 94#define PCN_CSR_BUSTIMER 0x52 95#define PCN_CSR_MEMERRTIMEO 0x64 96#define PCN_CSR_ONNOWMISC 0x74 97#define PCN_CSR_ADVFEAT 0x7A 98#define PCN_CSR_MACCFG 0x7D 99#define PCN_CSR_CHIPID0 0x58 100#define PCN_CSR_CHIPID1 0x59 101 102/* 103 * Control and status register (CSR0) 104 */ 105#define PCN_CSR_INIT 0x0001 106#define PCN_CSR_START 0x0002 107#define PCN_CSR_STOP 0x0004 108#define PCN_CSR_TX 0x0008 109#define PCN_CSR_TXON 0x0010 110#define PCN_CSR_RXON 0x0020 111#define PCN_CSR_INTEN 0x0040 112#define PCN_CSR_INTR 0x0080 113#define PCN_CSR_IDONE 0x0100 114#define PCN_CSR_TINT 0x0200 115#define PCN_CSR_RINT 0x0400 116#define PCN_CSR_MERR 0x0800 117#define PCN_CSR_MISS 0x1000 118#define PCN_CSR_CERR 0x2000 119#define PCN_CSR_ERR 0x8000 120 121/* 122 * Interrupt masks and deferral control (CSR3) 123 */ 124#define PCN_IMR_BSWAP 0x0004 125#define PCN_IMR_ENMBA 0x0008 /* enable modified backoff alg */ 126#define PCN_IMR_DXMT2PD 0x0010 127#define PCN_IMR_LAPPEN 0x0020 /* lookahead packet processing enb */ 128#define PCN_IMR_DXSUFLO 0x0040 /* disable TX stop on underflow */ 129#define PCN_IMR_IDONE 0x0100 130#define PCN_IMR_TINT 0x0200 131#define PCN_IMR_RINT 0x0400 132#define PCN_IMR_MERR 0x0800 133#define PCN_IMR_MISS 0x1000 134 135/* 136 * Test and features control (CSR4) 137 */ 138#define PCN_TFEAT_TXSTRTMASK 0x0004 139#define PCN_TFEAT_TXSTRT 0x0008 140#define PCN_TFEAT_RXCCOFLOWM 0x0010 /* Rx collision counter oflow */ 141#define PCN_TFEAT_RXCCOFLOW 0x0020 142#define PCN_TFEAT_UINT 0x0040 143#define PCN_TFEAT_UINTREQ 0x0080 144#define PCN_TFEAT_MISSOFLOWM 0x0100 145#define PCN_TFEAT_MISSOFLOW 0x0200 146#define PCN_TFEAT_STRIP_FCS 0x0400 147#define PCN_TFEAT_PAD_TX 0x0800 148#define PCN_TFEAT_TXDPOLL 0x1000 149#define PCN_TFEAT_DMAPLUS 0x4000 150 151/* 152 * Extended control and interrupt 1 (CSR5) 153 */ 154#define PCN_EXTCTL1_SPND 0x0001 /* suspend */ 155#define PCN_EXTCTL1_MPMODE 0x0002 /* magic packet mode */ 156#define PCN_EXTCTL1_MPENB 0x0004 /* magic packet enable */ 157#define PCN_EXTCTL1_MPINTEN 0x0008 /* magic packet interrupt enable */ 158#define PCN_EXTCTL1_MPINT 0x0010 /* magic packet interrupt */ 159#define PCN_EXTCTL1_MPPLBA 0x0020 /* magic packet phys. logical bcast */ 160#define PCN_EXTCTL1_EXDEFEN 0x0040 /* excessive deferral interrupt enb. */ 161#define PCN_EXTCTL1_EXDEF 0x0080 /* excessive deferral interrupt */ 162#define PCN_EXTCTL1_SINTEN 0x0400 /* system interrupt enable */ 163#define PCN_EXTCTL1_SINT 0x0800 /* system interrupt */ 164#define PCN_EXTCTL1_LTINTEN 0x4000 /* last TX interrupt enb */ 165#define PCN_EXTCTL1_TXOKINTD 0x8000 /* TX OK interrupt disable */ 166 167/* 168 * RX/TX descriptor len (CSR6) 169 */ 170#define PCN_DTBLLEN_RLEN 0x0F00 171#define PCN_DTBLLEN_TLEN 0xF000 172 173/* 174 * Extended control and interrupt 2 (CSR7) 175 */ 176#define PCN_EXTCTL2_MIIPDTINTE 0x0001 177#define PCN_EXTCTL2_MIIPDTINT 0x0002 178#define PCN_EXTCTL2_MCCIINTE 0x0004 179#define PCN_EXTCTL2_MCCIINT 0x0008 180#define PCN_EXTCTL2_MCCINTE 0x0010 181#define PCN_EXTCTL2_MCCINT 0x0020 182#define PCN_EXTCTL2_MAPINTE 0x0040 183#define PCN_EXTCTL2_MAPINT 0x0080 184#define PCN_EXTCTL2_MREINTE 0x0100 185#define PCN_EXTCTL2_MREINT 0x0200 186#define PCN_EXTCTL2_STINTE 0x0400 187#define PCN_EXTCTL2_STINT 0x0800 188#define PCN_EXTCTL2_RXDPOLL 0x1000 189#define PCN_EXTCTL2_RDMD 0x2000 190#define PCN_EXTCTL2_RXFRTG 0x4000 191#define PCN_EXTCTL2_FASTSPNDE 0x8000 192 193 194/* 195 * Mode (CSR15) 196 */ 197#define PCN_MODE_RXD 0x0001 /* RX disable */ 198#define PCN_MODE_TXD 0x0002 /* TX disable */ 199#define PCN_MODE_LOOP 0x0004 /* loopback enable */ 200#define PCN_MODE_TXCRCD 0x0008 201#define PCN_MODE_FORCECOLL 0x0010 202#define PCN_MODE_RETRYD 0x0020 203#define PCN_MODE_INTLOOP 0x0040 204#define PCN_MODE_PORTSEL 0x0180 205#define PCN_MODE_RXVPAD 0x2000 206#define PCN_MODE_RXNOBROAD 0x4000 207#define PCN_MODE_PROMISC 0x8000 208 209/* Settings for PCN_MODE_PORTSEL when ASEL (BCR2[1]) is 0 */ 210#define PCN_PORT_AUI 0x0000 211#define PCN_PORT_10BASET 0x0080 212#define PCN_PORT_GPSI 0x0100 213#define PCN_PORT_MII 0x0180 214 215/* 216 * Chip ID values. 217 */ 218/* CSR88-89: Chip ID masks */ 219#define AMD_MASK 0x003 220#define PART_MASK 0xffff 221#define Am79C971 0x2623 222#define Am79C972 0x2624 223#define Am79C973 0x2625 224#define Am79C978 0x2626 225#define Am79C975 0x2627 226#define Am79C976 0x2628 227 228/* 229 * Advanced feature control (CSR122) 230 */ 231#define PCN_AFC_RXALIGN 0x0001 232 233/* 234 * BCR (bus control) registers 235 */ 236#define PCN_BCR_MMRA 0x00 /* Master Mode Read Active */ 237#define PCN_BCR_MMW 0x01 /* Master Mode Write Active */ 238#define PCN_BCR_MISCCFG 0x02 239#define PCN_BCR_LED0 0x04 240#define PCN_BCR_LED1 0x05 241#define PCN_BCR_LED2 0x06 242#define PCN_BCR_LED3 0x07 243#define PCN_BCR_DUPLEX 0x09 244#define PCN_BCR_BUSCTL 0x12 245#define PCN_BCR_EECTL 0x13 246#define PCN_BCR_SSTYLE 0x14 247#define PCN_BCR_PCILAT 0x16 248#define PCN_BCR_PCISUBVENID 0x17 249#define PCN_BCR_PCISUBSYSID 0x18 250#define PCN_BCR_SRAMSIZE 0x19 251#define PCN_BCR_SRAMBOUND 0x1A 252#define PCN_BCR_SRAMCTL 0x1B 253#define PCN_BCR_MIICTL 0x20 254#define PCN_BCR_MIIADDR 0x21 255#define PCN_BCR_MIIDATA 0x22 256#define PCN_BCR_PCIVENID 0x23 257#define PCN_BCR_PCIPCAP 0x24 258#define PCN_BCR_DATA0 0x25 259#define PCN_BCR_DATA1 0x26 260#define PCN_BCR_DATA2 0x27 261#define PCN_BCR_DATA3 0x28 262#define PCN_BCR_DATA4 0x29 263#define PCN_BCR_DATA5 0x2A 264#define PCN_BCR_DATA6 0x2B 265#define PCN_BCR_DATA7 0x2C 266#define PCN_BCR_ONNOWPAT0 0x2D 267#define PCN_BCR_ONNOWPAT1 0x2E 268#define PCN_BCR_ONNOWPAT2 0x2F 269#define PCN_BCR_PHYSEL 0x31 270 271/* 272 * Miscellaneous Configuration (BCR2) 273 */ 274#define PCN_MISC_TMAULOOP 1<<14 /* T-MAU Loopback packet enable. */ 275#define PCN_MISC_LEDPE 1<<12 /* LED Program Enable */ 276#define PCN_MISC_APROMWE 1<<8 /* Address PROM Write Enable */ 277#define PCN_MISC_INTLEVEL 1<<7 /* Interrupt level */ 278#define PCN_MISC_EADISEL 1<<3 /* EADI Select */ 279#define PCN_MISC_AWAKE 1<<2 /* Power saving mode select */ 280#define PCN_MISC_ASEL 1<<1 /* Auto Select */ 281#define PCN_MISC_XMAUSEL 1<<0 /* Reserved. */ 282 283/* 284 * Full duplex control (BCR9) 285 */ 286#define PCN_DUPLEX_FDEN 0x0001 /* Full-duplex enable */ 287#define PCN_DUPLEX_AUI 0x0002 /* AUI full-duplex */ 288#define PCN_DUPLEX_FDRPAD 0x0004 /* Full-duplex runt pkt accept dis. */ 289 290/* 291 * Burst and bus control register (BCR18) 292 */ 293#define PCN_BUSCTL_BWRITE 0x0020 294#define PCN_BUSCTL_BREAD 0x0040 295#define PCN_BUSCTL_DWIO 0x0080 296#define PCN_BUSCTL_EXTREQ 0x0100 297#define PCN_BUSCTL_MEMCMD 0x0200 298#define PCN_BUSCTL_NOUFLOW 0x0800 299#define PCN_BUSCTL_ROMTMG 0xF000 300 301/* 302 * EEPROM control (BCR19) 303 */ 304#define PCN_EECTL_EDATA 0x0001 305#define PCN_EECTL_ECLK 0x0002 306#define PCN_EECTL_EECS 0x0004 307#define PCN_EECTL_EEN 0x0100 308#define PCN_EECTL_EEDET 0x2000 309#define PCN_EECTL_PREAD 0x4000 310#define PCN_EECTL_PVALID 0x8000 311 312/* 313 * Software style (BCR20) 314 */ 315#define PCN_SSTYLE_APERREN 0x0400 /* advanced parity error checking */ 316#define PCN_SSTYLE_SSIZE32 0x0100 317#define PCN_SSTYLE_SWSTYLE 0x00FF 318 319#define PCN_SWSTYLE_LANCE 0x0000 320#define PCN_SWSTYLE_PCNETPCI 0x0102 321#define PCN_SWSTYLE_PCNETPCI_BURST 0x0103 322 323/* 324 * MII control and status (BCR32) 325 */ 326#define PCN_MIICTL_MIILP 0x0002 /* MII internal loopback */ 327#define PCN_MIICTL_XPHYSP 0x0008 /* external PHY speed */ 328#define PCN_MIICTL_XPHYFD 0x0010 /* external PHY full duplex */ 329#define PCN_MIICTL_XPHYANE 0x0020 /* external phy auto-neg enable */ 330#define PCN_MIICTL_XPHYRST 0x0040 /* external PHY reset */ 331#define PCN_MIICTL_DANAS 0x0080 /* disable auto-neg auto-setup */ 332#define PCN_MIICTL_APDW 0x0700 /* auto-poll dwell time */ 333#define PCN_MIICTL_APEP 0x0100 /* auto-poll external PHY */ 334#define PCN_MIICTL_FMDC 0x3000 /* data clock speed */ 335#define PCN_MIICTL_MIIPD 0x4000 /* PHY detect */ 336#define PCN_MIICTL_ANTST 0x8000 /* Manufacturing test */ 337 338/* 339 * MII address register (BCR33) 340 */ 341#define PCN_MIIADDR_REGAD 0x001F 342#define PCN_MIIADDR_PHYAD 0x03E0 343 344/* addresses of internal PHYs */ 345#define PCN_PHYAD_100BTX 30 346#define PCN_PHYAD_10BT 31 347 348/* 349 * MII data register (BCR34) 350 */ 351#define PCN_MIIDATA_MIIMD 0xFFFF 352 353/* 354 * PHY selection (BCR49) (HomePNA NIC only) 355 */ 356#define PCN_PHYSEL_PHYSEL 0x0003 357#define PCN_PHYSEL_DEFAULT 0x0300 358#define PCN_PHYSEL_PCNET 0x8000 359 360#define PCN_PHY_10BT 0x0000 361#define PCN_PHY_HOMEPNA 0x0001 362#define PCN_PHY_EXTERNAL 0x0002 363 364struct pcn_rx_desc { 365 u_int16_t pcn_rxlen; 366 u_int16_t pcn_rsvd0; 367 u_int16_t pcn_bufsz; 368 u_int16_t pcn_rxstat; 369 u_int32_t pcn_rbaddr; 370 u_int32_t pcn_uspace; 371}; 372 373#define PCN_RXSTAT_BPE 0x0080 /* bus parity error */ 374#define PCN_RXSTAT_ENP 0x0100 /* end of packet */ 375#define PCN_RXSTAT_STP 0x0200 /* start of packet */ 376#define PCN_RXSTAT_BUFF 0x0400 /* buffer error */ 377#define PCN_RXSTAT_CRC 0x0800 /* CRC error */ 378#define PCN_RXSTAT_OFLOW 0x1000 /* rx overrun */ 379#define PCN_RXSTAT_FRAM 0x2000 /* framing error */ 380#define PCN_RXSTAT_ERR 0x4000 /* error summary */ 381#define PCN_RXSTAT_OWN 0x8000 382 383#define PCN_RXLEN_MBO 0xF000 384#define PCN_RXLEN_BUFSZ 0x0FFF 385 386#define PCN_OWN_RXDESC(x) (((x)->pcn_rxstat & PCN_RXSTAT_OWN) == 0) 387 388struct pcn_tx_desc { 389 u_int32_t pcn_txstat; 390 u_int32_t pcn_txctl; 391 u_int32_t pcn_tbaddr; 392 u_int32_t pcn_uspace; 393}; 394 395#define PCN_TXSTAT_TRC 0x0000000F /* transmit retries */ 396#define PCN_TXSTAT_RTRY 0x04000000 /* retry */ 397#define PCN_TXSTAT_LCAR 0x08000000 /* lost carrier */ 398#define PCN_TXSTAT_LCOL 0x10000000 /* late collision */ 399#define PCN_TXSTAT_EXDEF 0x20000000 /* excessive deferrals */ 400#define PCN_TXSTAT_UFLOW 0x40000000 /* transmit underrun */ 401#define PCN_TXSTAT_BUFF 0x80000000 /* buffer error */ 402 403#define PCN_TXCTL_OWN 0x80000000 404#define PCN_TXCTL_ERR 0x40000000 /* error summary */ 405#define PCN_TXCTL_ADD_FCS 0x20000000 /* add FCS to pkt */ 406#define PCN_TXCTL_MORE_LTINT 0x10000000 407#define PCN_TXCTL_ONE 0x08000000 408#define PCN_TXCTL_DEF 0x04000000 409#define PCN_TXCTL_STP 0x02000000 410#define PCN_TXCTL_ENP 0x01000000 411#define PCN_TXCTL_BPE 0x00800000 412#define PCN_TXCTL_MBO 0x0000F000 413#define PCN_TXCTL_BUFSZ 0x00000FFF 414 415#define PCN_OWN_TXDESC(x) (((x)->pcn_txctl & PCN_TXCTL_OWN) == 0) 416 417#define PCN_RX_LIST_CNT 64 418#define PCN_TX_LIST_CNT 256 419 420struct pcn_list_data { 421 struct pcn_rx_desc pcn_rx_list[PCN_RX_LIST_CNT]; 422 struct pcn_tx_desc pcn_tx_list[PCN_TX_LIST_CNT]; 423}; 424 425struct pcn_ring_data { 426 struct mbuf *pcn_rx_chain[PCN_RX_LIST_CNT]; 427 struct mbuf *pcn_tx_chain[PCN_TX_LIST_CNT]; 428 int pcn_rx_prod; 429 int pcn_tx_prod; 430 int pcn_tx_cons; 431 int pcn_tx_cnt; 432}; 433 434/* 435 * AMD PCI vendor ID. 436 */ 437#define PCN_VENDORID 0x1022 438 439/* 440 * AMD PCnet/PCI device IDs 441 */ 442#define PCN_DEVICEID_PCNET 0x2000 443#define PCN_DEVICEID_HOME 0x2001 444 445struct pcn_type { 446 u_int16_t pcn_vid; 447 u_int16_t pcn_did; 448 const char *pcn_name; 449}; 450 451struct pcn_softc { 452 struct ifnet *pcn_ifp; 453 bus_space_handle_t pcn_bhandle; 454 bus_space_tag_t pcn_btag; 455 struct resource *pcn_res; 456 struct resource *pcn_irq; 457 void *pcn_intrhand; 458 device_t pcn_miibus; 459 u_int8_t pcn_link; 460 int8_t pcn_extphyaddr; 461 int8_t pcn_inst_10bt; 462 int pcn_if_flags; 463 int pcn_type; 464 struct pcn_list_data *pcn_ldata; 465 struct pcn_ring_data pcn_cdata; 466 struct callout pcn_stat_callout; 467 struct mtx pcn_mtx; 468 int pcn_timer; 469}; 470 471#define PCN_LOCK(_sc) mtx_lock(&(_sc)->pcn_mtx) 472#define PCN_UNLOCK(_sc) mtx_unlock(&(_sc)->pcn_mtx) 473#define PCN_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->pcn_mtx, MA_OWNED) 474 475/* 476 * register space access macros 477 */ 478#define CSR_WRITE_4(sc, reg, val) \ 479 bus_space_write_4(sc->pcn_btag, sc->pcn_bhandle, reg, val) 480 481#define CSR_READ_4(sc, reg) \ 482 bus_space_read_4(sc->pcn_btag, sc->pcn_bhandle, reg) 483 484#define CSR_WRITE_2(sc, reg, val) \ 485 bus_space_write_2(sc->pcn_btag, sc->pcn_bhandle, reg, val) 486 487#define CSR_READ_2(sc, reg) \ 488 bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg) 489 490#define PCN_TIMEOUT 1000 491#define ETHER_ALIGN 2 492#define PCN_RXLEN 1536 493#define PCN_MIN_FRAMELEN 60 494#define PCN_INC(x, y) (x) = (x + 1) % y 495/* 496 * PCI low memory base and low I/O base register, and 497 * other PCI registers. 498 */ 499 500#define PCN_PCI_VENDOR_ID 0x00 501#define PCN_PCI_DEVICE_ID 0x02 502#define PCN_PCI_COMMAND 0x04 503#define PCN_PCI_STATUS 0x06 504#define PCN_PCI_REVID 0x08 505#define PCN_PCI_CLASSCODE 0x09 506#define PCN_PCI_CACHELEN 0x0C 507#define PCN_PCI_LATENCY_TIMER 0x0D 508#define PCN_PCI_HEADER_TYPE 0x0E 509#define PCN_PCI_LOIO 0x10 510#define PCN_PCI_LOMEM 0x14 511#define PCN_PCI_BIOSROM 0x30 512#define PCN_PCI_INTLINE 0x3C 513#define PCN_PCI_INTPIN 0x3D 514#define PCN_PCI_MINGNT 0x3E 515#define PCN_PCI_MINLAT 0x3F 516#define PCN_PCI_RESETOPT 0x48 517#define PCN_PCI_EEPROM_DATA 0x4C 518 519/* power management registers */ 520#define PCN_PCI_CAPID 0x50 /* 8 bits */ 521#define PCN_PCI_NEXTPTR 0x51 /* 8 bits */ 522#define PCN_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 523#define PCN_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 524 525#define PCN_PSTATE_MASK 0x0003 526#define PCN_PSTATE_D0 0x0000 527#define PCN_PSTATE_D1 0x0001 528#define PCN_PSTATE_D2 0x0002 529#define PCN_PSTATE_D3 0x0003 530#define PCN_PME_EN 0x0010 531#define PCN_PME_STATUS 0x8000 532