xgehal-ring.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2007 Neterion, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/11/sys/dev/nxge/include/xgehal-ring.h 330897 2018-03-14 03:19:51Z eadler $ 29 */ 30 31#ifndef XGE_HAL_RING_H 32#define XGE_HAL_RING_H 33 34#include <dev/nxge/include/xgehal-channel.h> 35#include <dev/nxge/include/xgehal-config.h> 36#include <dev/nxge/include/xgehal-mm.h> 37 38__EXTERN_BEGIN_DECLS 39 40/* HW ring configuration */ 41#define XGE_HAL_RING_RXDBLOCK_SIZE 0x1000 42 43#define XGE_HAL_RXD_T_CODE_OK 0x0 44#define XGE_HAL_RXD_T_CODE_PARITY 0x1 45#define XGE_HAL_RXD_T_CODE_ABORT 0x2 46#define XGE_HAL_RXD_T_CODE_PARITY_ABORT 0x3 47#define XGE_HAL_RXD_T_CODE_RDA_FAILURE 0x4 48#define XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO 0x5 49#define XGE_HAL_RXD_T_CODE_BAD_FCS 0x6 50#define XGE_HAL_RXD_T_CODE_BUFF_SIZE 0x7 51#define XGE_HAL_RXD_T_CODE_BAD_ECC 0x8 52#define XGE_HAL_RXD_T_CODE_UNUSED_C 0xC 53#define XGE_HAL_RXD_T_CODE_UNKNOWN 0xF 54 55#define XGE_HAL_RING_USE_MTU -1 56 57/* control_1 and control_2 formatting - same for all buffer modes */ 58#define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF) 59#define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF)) 60 61#define XGE_HAL_RXD_MASK_VLAN_TAG vBIT(0xFFFF,48,16) 62#define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val 63#define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF)) 64 65#define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */ 66#define XGE_HAL_RXD_NOT_COMPLETED BIT(0) /* control_2 */ 67#define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 68#define XGE_HAL_RXD_GET_T_CODE(control_1) \ 69 ((control_1 & XGE_HAL_RXD_T_CODE)>>48) 70#define XGE_HAL_RXD_SET_T_CODE(control_1, val) \ 71 (control_1 |= (((u64)val & 0xF) << 48)) 72 73#define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2) 74#define XGE_HAL_RXD_MASK_FRAME_PROTO vBIT(0xFFFF,24,8) 75#define XGE_HAL_RXD_GET_FRAME_TYPE(control_1) \ 76 (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37)) 77#define XGE_HAL_RXD_GET_FRAME_PROTO(control_1) \ 78 (u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32) 79#define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24) 80#define XGE_HAL_RXD_FRAME_PROTO_IPV4 BIT(27) 81#define XGE_HAL_RXD_FRAME_PROTO_IPV6 BIT(28) 82#define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED BIT(29) 83#define XGE_HAL_RXD_FRAME_PROTO_TCP BIT(30) 84#define XGE_HAL_RXD_FRAME_PROTO_UDP BIT(31) 85#define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \ 86 XGE_HAL_RXD_FRAME_PROTO_UDP) 87 88/** 89 * enum xge_hal_frame_type_e - Ethernet frame format. 90 * @XGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format. 91 * @XGE_HAL_FRAME_TYPE_LLC: LLC format. 92 * @XGE_HAL_FRAME_TYPE_SNAP: SNAP format. 93 * @XGE_HAL_FRAME_TYPE_IPX: IPX format. 94 * 95 * Ethernet frame format. 96 */ 97typedef enum xge_hal_frame_type_e { 98 XGE_HAL_FRAME_TYPE_DIX = 0x0, 99 XGE_HAL_FRAME_TYPE_LLC = 0x1, 100 XGE_HAL_FRAME_TYPE_SNAP = 0x2, 101 XGE_HAL_FRAME_TYPE_IPX = 0x3, 102} xge_hal_frame_type_e; 103 104/** 105 * enum xge_hal_frame_proto_e - Higher-layer ethernet protocols. 106 * @XGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN. 107 * @XGE_HAL_FRAME_PROTO_IPV4: IPv4. 108 * @XGE_HAL_FRAME_PROTO_IPV6: IPv6. 109 * @XGE_HAL_FRAME_PROTO_IP_FRAGMENTED: IP fragmented. 110 * @XGE_HAL_FRAME_PROTO_TCP: TCP. 111 * @XGE_HAL_FRAME_PROTO_UDP: UDP. 112 * @XGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP. 113 * 114 * Higher layer ethernet protocols and options. 115 */ 116typedef enum xge_hal_frame_proto_e { 117 XGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80, 118 XGE_HAL_FRAME_PROTO_IPV4 = 0x10, 119 XGE_HAL_FRAME_PROTO_IPV6 = 0x08, 120 XGE_HAL_FRAME_PROTO_IP_FRAGMENTED = 0x04, 121 XGE_HAL_FRAME_PROTO_TCP = 0x02, 122 XGE_HAL_FRAME_PROTO_UDP = 0x01, 123 XGE_HAL_FRAME_PROTO_TCP_OR_UDP = (XGE_HAL_FRAME_PROTO_TCP | \ 124 XGE_HAL_FRAME_PROTO_UDP) 125} xge_hal_frame_proto_e; 126 127/* 128 * xge_hal_ring_rxd_1_t 129 */ 130typedef struct { 131 u64 host_control; 132 u64 control_1; 133 u64 control_2; 134#define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 135#define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16) 136#define XGE_HAL_RXD_1_GET_BUFFER0_SIZE(Control_2) \ 137 (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) 138#define XGE_HAL_RXD_1_GET_RTH_VALUE(Control_2) \ 139 (u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16) 140 u64 buffer0_ptr; 141} xge_hal_ring_rxd_1_t; 142 143/* 144 * xge_hal_ring_rxd_3_t 145 */ 146typedef struct { 147 u64 host_control; 148 u64 control_1; 149 150 u64 control_2; 151#define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE vBIT(0xFF,8,8) 152#define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8) 153#define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 154#define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16) 155#define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 156#define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16) 157 158 159#define XGE_HAL_RXD_3_GET_BUFFER0_SIZE(Control_2) \ 160 (int)((Control_2 & vBIT(0xFF,8,8))>>48) 161#define XGE_HAL_RXD_3_GET_BUFFER1_SIZE(Control_2) \ 162 (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) 163#define XGE_HAL_RXD_3_GET_BUFFER2_SIZE(Control_2) \ 164 (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) 165 166 u64 buffer0_ptr; 167 u64 buffer1_ptr; 168 u64 buffer2_ptr; 169} xge_hal_ring_rxd_3_t; 170 171/* 172 * xge_hal_ring_rxd_5_t 173 */ 174typedef struct { 175#ifdef XGE_OS_HOST_BIG_ENDIAN 176 u32 host_control; 177 u32 control_3; 178#else 179 u32 control_3; 180 u32 host_control; 181#endif 182 183 184#define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE vBIT(0xFFFF,32,16) 185#define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16) 186#define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE vBIT(0xFFFF,48,16) 187#define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16) 188 189#define XGE_HAL_RXD_5_GET_BUFFER3_SIZE(Control_3) \ 190 (int)((Control_3 & vBIT(0xFFFF,32,16))>>16) 191#define XGE_HAL_RXD_5_GET_BUFFER4_SIZE(Control_3) \ 192 (int)((Control_3 & vBIT(0xFFFF,48,16))) 193 194 u64 control_1; 195 u64 control_2; 196 197#define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 198#define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16) 199#define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 200#define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16) 201#define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 202#define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16) 203 204 205#define XGE_HAL_RXD_5_GET_BUFFER0_SIZE(Control_2) \ 206 (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) 207#define XGE_HAL_RXD_5_GET_BUFFER1_SIZE(Control_2) \ 208 (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) 209#define XGE_HAL_RXD_5_GET_BUFFER2_SIZE(Control_2) \ 210 (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) 211 u64 buffer0_ptr; 212 u64 buffer1_ptr; 213 u64 buffer2_ptr; 214 u64 buffer3_ptr; 215 u64 buffer4_ptr; 216} xge_hal_ring_rxd_5_t; 217 218#define XGE_HAL_RXD_GET_RTH_SPDM_HIT(Control_1) \ 219 (u8)((Control_1 & BIT(18))>>45) 220#define XGE_HAL_RXD_GET_RTH_IT_HIT(Control_1) \ 221 (u8)((Control_1 & BIT(19))>>44) 222#define XGE_HAL_RXD_GET_RTH_HASH_TYPE(Control_1) \ 223 (u8)((Control_1 & vBIT(0xF,20,4))>>40) 224 225#define XGE_HAL_RXD_HASH_TYPE_NONE 0x0 226#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4 0x1 227#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4 0x2 228#define XGE_HAL_RXD_HASH_TYPE_IPV4 0x3 229#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6 0x4 230#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6 0x5 231#define XGE_HAL_RXD_HASH_TYPE_IPV6 0x6 232#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX 0x7 233#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX 0x8 234#define XGE_HAL_RXD_HASH_TYPE_IPV6_EX 0x9 235 236typedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE]; 237 238#define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET 0xFF8 239#define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET 0xFF0 240 241#define XGE_HAL_RING_RXD_SIZEOF(n) \ 242 (n==1 ? sizeof(xge_hal_ring_rxd_1_t) : \ 243 (n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \ 244 sizeof(xge_hal_ring_rxd_5_t))) 245 246#define XGE_HAL_RING_RXDS_PER_BLOCK(n) \ 247 (n==1 ? 127 : (n==3 ? 85 : 63)) 248 249/** 250 * struct xge_hal_ring_rxd_priv_t - Receive descriptor HAL-private data. 251 * @dma_addr: DMA (mapped) address of _this_ descriptor. 252 * @dma_handle: DMA handle used to map the descriptor onto device. 253 * @dma_offset: Descriptor's offset in the memory block. HAL allocates 254 * descriptors in memory blocks of 255 * %XGE_HAL_RING_RXDBLOCK_SIZE 256 * bytes. Each memblock is contiguous DMA-able memory. Each 257 * memblock contains 1 or more 4KB RxD blocks visible to the 258 * Xframe hardware. 259 * @dma_object: DMA address and handle of the memory block that contains 260 * the descriptor. This member is used only in the "checked" 261 * version of the HAL (to enforce certain assertions); 262 * otherwise it gets compiled out. 263 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 264 * 265 * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA 266 * information associated with the descriptor. Note that ULD can ask HAL 267 * to allocate additional per-descriptor space for its own (ULD-specific) 268 * purposes. 269 */ 270typedef struct xge_hal_ring_rxd_priv_t { 271 dma_addr_t dma_addr; 272 pci_dma_h dma_handle; 273 ptrdiff_t dma_offset; 274#ifdef XGE_DEBUG_ASSERT 275 xge_hal_mempool_dma_t *dma_object; 276#endif 277#ifdef XGE_OS_MEMORY_CHECK 278 int allocated; 279#endif 280} xge_hal_ring_rxd_priv_t; 281 282/** 283 * struct xge_hal_ring_t - Ring channel. 284 * @channel: Channel "base" of this ring, the common part of all HAL 285 * channels. 286 * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode, 287 * as per Xframe User Guide. 288 * @indicate_max_pkts: Maximum number of packets processed within a single 289 * interrupt. Can be used to limit the time spent inside hw 290 * interrupt. 291 * @config: Ring configuration, part of device configuration 292 * (see xge_hal_device_config_t{}). 293 * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Xframe spec, 294 * 1-buffer mode descriptor is 32 byte long, etc. 295 * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor 296 * data (e.g., DMA handle for Solaris) 297 * @rxds_per_block: Number of descriptors per hardware-defined RxD 298 * block. Depends on the (1-,3-,5-) buffer mode. 299 * @mempool: Memory pool, the pool from which descriptors get allocated. 300 * (See xge_hal_mm.h). 301 * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal 302 * usage. Not to confuse with @rxd_priv_size. 303 * @reserved_rxds_arr: Array of RxD pointers. At any point in time each 304 * entry in this array is available for allocation 305 * (via xge_hal_ring_dtr_reserve()) and posting. 306 * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR. 307 * Used in conjunction with @indicate_max_pkts. 308 * Ring channel. 309 * 310 * Note: The structure is cache line aligned to better utilize 311 * CPU cache performance. 312 */ 313typedef struct xge_hal_ring_t { 314 xge_hal_channel_t channel; 315 int buffer_mode; 316 int indicate_max_pkts; 317 xge_hal_ring_config_t *config; 318 int rxd_size; 319 int rxd_priv_size; 320 int rxds_per_block; 321 xge_hal_mempool_t *mempool; 322 int rxdblock_priv_size; 323 void **reserved_rxds_arr; 324 int cmpl_cnt; 325} __xge_os_attr_cacheline_aligned xge_hal_ring_t; 326 327/** 328 * struct xge_hal_dtr_info_t - Extended information associated with a 329 * completed ring descriptor. 330 * @l3_cksum: Result of IP checksum check (by Xframe hardware). 331 * This field containing XGE_HAL_L3_CKSUM_OK would mean that 332 * the checksum is correct, otherwise - the datagram is 333 * corrupted. 334 * @l4_cksum: Result of TCP/UDP checksum check (by Xframe hardware). 335 * This field containing XGE_HAL_L4_CKSUM_OK would mean that 336 * the checksum is correct. Otherwise - the packet is 337 * corrupted. 338 * @frame: See xge_hal_frame_type_e{}. 339 * @proto: Reporting bits for various higher-layer protocols, including (but 340 * note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}. 341 * @vlan: VLAN tag extracted from the received frame. 342 * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II 343 * hardware if RTH is enabled. 344 * @rth_it_hit: Set, If RTH hash value calculated by the Xframe II hardware 345 * has a matching entry in the Indirection table. 346 * @rth_spdm_hit: Set, If RTH hash value calculated by the Xframe II hardware 347 * has a matching entry in the Socket Pair Direct Match table. 348 * @rth_hash_type: RTH hash code of the function used to calculate the hash. 349 * @reserved_pad: Unused byte. 350 */ 351typedef struct xge_hal_dtr_info_t { 352 int l3_cksum; 353 int l4_cksum; 354 int frame; /* zero or more of xge_hal_frame_type_e flags */ 355 int proto; /* zero or more of xge_hal_frame_proto_e flags */ 356 int vlan; 357 u32 rth_value; 358 u8 rth_it_hit; 359 u8 rth_spdm_hit; 360 u8 rth_hash_type; 361 u8 reserved_pad; 362} xge_hal_dtr_info_t; 363 364/* ========================== RING PRIVATE API ============================ */ 365 366xge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh, 367 xge_hal_channel_attr_t *attr); 368 369void __hal_ring_close(xge_hal_channel_h channelh); 370 371void __hal_ring_hw_initialize(xge_hal_device_h devh); 372 373void __hal_ring_mtu_set(xge_hal_device_h devh, int new_mtu); 374 375void __hal_ring_prc_enable(xge_hal_channel_h channelh); 376 377void __hal_ring_prc_disable(xge_hal_channel_h channelh); 378 379xge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel, 380 xge_hal_channel_reopen_e reopen); 381 382#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING) 383#define __HAL_STATIC_RING 384#define __HAL_INLINE_RING 385 386__HAL_STATIC_RING __HAL_INLINE_RING int 387__hal_ring_block_memblock_idx(xge_hal_ring_block_t *block); 388 389__HAL_STATIC_RING __HAL_INLINE_RING void 390__hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx); 391 392__HAL_STATIC_RING __HAL_INLINE_RING dma_addr_t 393__hal_ring_block_next_pointer(xge_hal_ring_block_t *block); 394 395__HAL_STATIC_RING __HAL_INLINE_RING void 396__hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block, 397 dma_addr_t dma_next); 398 399__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t* 400__hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh); 401 402/* =========================== RING PUBLIC API ============================ */ 403 404__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 405xge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); 406 407__HAL_STATIC_RING __HAL_INLINE_RING void* 408xge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 409 410__HAL_STATIC_RING __HAL_INLINE_RING void 411xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size); 412 413__HAL_STATIC_RING __HAL_INLINE_RING void 414xge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 415 xge_hal_dtr_info_t *ext_info); 416 417__HAL_STATIC_RING __HAL_INLINE_RING void 418xge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 419 dma_addr_t *dma_pointer, int *pkt_length); 420 421__HAL_STATIC_RING __HAL_INLINE_RING void 422xge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], 423 int sizes[]); 424 425__HAL_STATIC_RING __HAL_INLINE_RING void 426xge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 427 dma_addr_t dma_pointers[], int sizes[]); 428 429__HAL_STATIC_RING __HAL_INLINE_RING void 430xge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], 431 int sizes[]); 432 433__HAL_STATIC_RING __HAL_INLINE_RING void 434xge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 435 dma_addr_t dma_pointer[], int sizes[]); 436 437__HAL_STATIC_RING __HAL_INLINE_RING void 438xge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 439 440__HAL_STATIC_RING __HAL_INLINE_RING void 441xge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 442 443__HAL_STATIC_RING __HAL_INLINE_RING void 444xge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 445 446__HAL_STATIC_RING __HAL_INLINE_RING void 447xge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 448 449__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 450xge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, 451 u8 *t_code); 452 453__HAL_STATIC_RING __HAL_INLINE_RING void 454xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 455 456__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 457xge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh); 458 459#else /* XGE_FASTPATH_EXTERN */ 460#define __HAL_STATIC_RING static 461#define __HAL_INLINE_RING inline 462#include <dev/nxge/xgehal/xgehal-ring-fp.c> 463#endif /* XGE_FASTPATH_INLINE */ 464 465__EXTERN_END_DECLS 466 467#endif /* XGE_HAL_RING_H */ 468