nfc_fsl.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012 Juniper Networks, Inc. 5 * Copyright (C) 2009-2012 Semihalf 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/dev/nand/nfc_fsl.h 330897 2018-03-14 03:19:51Z eadler $ 30 */ 31 32#ifndef _NAND_NFC_FSL_H_ 33#define _NAND_NFC_FSL_H_ 34 35/* LBC BR/OR Registers layout definitions */ 36#define BR_V 0x00000001 37#define BR_V_SHIFT 0 38#define BR_MSEL 0x000000E0 39#define BR_MSEL_SHIFT 5 40#define BR_DECC_CHECK_MODE 0x00000600 41#define BR_DECC_CHECK_GEN 0x00000400 42 43#define OR_FCM_PAGESIZE 0x00000400 44 45/* Options definitions */ 46#define NAND_OPT_ECC_MODE_HW 1 47#define NAND_OPT_ECC_MODE_SOFT (1 << 1) 48 49/* FMR - Flash Mode Register */ 50#define FMR_CWTO 0xF000 51#define FMR_CWTO_SHIFT 12 52#define FMR_BOOT 0x0800 53#define FMR_ECCM 0x0100 54#define FMR_AL 0x0030 55#define FMR_AL_SHIFT 4 56#define FMR_OP 0x0003 57#define FMR_OP_SHIFT 0 58 59#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 60#define FIR_OP_CA 0x1 /* Issue current column address */ 61#define FIR_OP_PA 0x2 /* Issue current block+page address */ 62#define FIR_OP_UA 0x3 /* Issue user defined address */ 63#define FIR_OP_CM(x) (4 + (x)) /* Issue command from FCR[CMD(x)] */ 64#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 65#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 66#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 67#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 68#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 69#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 70#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 71#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 72 73/* LTESR - Transfer Error Status Register */ 74#define LTESR_BM 0x80000000 75#define LTESR_FCT 0x40000000 76#define LTESR_PAR 0x20000000 77#define LTESR_WP 0x04000000 78#define LTESR_ATMW 0x00800000 79#define LTESR_ATMR 0x00400000 80#define LTESR_CS 0x00080000 81#define LTESR_CC 0x00000001 82 83#define LTESR_NAND_MASK (LTESR_FCT | LTESR_CC | LTESR_CS) 84 85/* FPAR - Flash Page Address Register */ 86#define FPAR_SP_PI 0x00007C00 87#define FPAR_SP_PI_SHIFT 10 88#define FPAR_SP_MS 0x00000200 89#define FPAR_SP_CI 0x000001FF 90#define FPAR_SP_CI_SHIFT 0 91#define FPAR_LP_PI 0x0003F000 92#define FPAR_LP_PI_SHIFT 12 93#define FPAR_LP_MS 0x00000800 94#define FPAR_LP_CI 0x000007FF 95#define FPAR_LP_CI_SHIFT 0 96 97#define FSL_FCM_WAIT_TIMEOUT 10 98 99#endif /* _NAND_NFC_FSL_H_ */ 100