nxprtc.c revision 323467
1/*- 2 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/dev/iicbus/nxprtc.c 323467 2017-09-11 22:21:15Z ian $"); 29 30/* 31 * Driver for NXP real-time clock/calendar chips: 32 * - PCF8563 = low power, countdown timer 33 * - PCA8565 = like PCF8563, automotive temperature range 34 * - PCF8523 = low power, countdown timer, oscillator freq tuning, 2 timers 35 * - PCF2127 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, 512B ram 36 * - PCA2129 = like PCF8523, automotive, tcxo, tamper/ts, i2c & spi, no timer 37 * - PCF2129 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, no timer 38 * 39 * Most chips have a countdown timer, ostensibly intended to generate periodic 40 * interrupt signals on an output pin. The timer is driven from the same 41 * divider chain that clocks the time of day registers, and they start counting 42 * in sync when the STOP bit is cleared after the time and timer registers are 43 * set. The timer register can also be read on the fly, so we use it to count 44 * fractional seconds and get a resolution of ~15ms. 45 */ 46 47#include "opt_platform.h" 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/clock.h> 53#include <sys/kernel.h> 54#include <sys/libkern.h> 55#include <sys/module.h> 56 57#include <dev/iicbus/iicbus.h> 58#include <dev/iicbus/iiconf.h> 59#ifdef FDT 60#include <dev/ofw/openfirm.h> 61#include <dev/ofw/ofw_bus.h> 62#include <dev/ofw/ofw_bus_subr.h> 63#endif 64 65#include "clock_if.h" 66#include "iicbus_if.h" 67 68/* 69 * I2C address 1010 001x : PCA2129 PCF2127 PCF2129 PCF8563 PCF8565 70 * I2C address 1101 000x : PCF8523 71 */ 72#define PCF8563_ADDR 0xa2 73#define PCF8523_ADDR 0xd0 74 75/* 76 * Registers, bits within them, and masks that are common to all chip types. 77 */ 78#define PCF85xx_R_CS1 0x00 /* CS1 and CS2 control regs are in */ 79#define PCF85xx_R_CS2 0x01 /* the same location on all chips. */ 80 81#define PCF85xx_B_CS1_STOP 0x20 /* Stop time incrementing bit */ 82#define PCF85xx_B_SECOND_OS 0x80 /* Oscillator Stopped bit */ 83 84#define PCF85xx_M_SECOND 0x7f /* Masks for all BCD time regs... */ 85#define PCF85xx_M_MINUTE 0x7f 86#define PCF85xx_M_12HOUR 0x1f 87#define PCF85xx_M_24HOUR 0x3f 88#define PCF85xx_M_DAY 0x3f 89#define PCF85xx_M_MONTH 0x1f 90#define PCF85xx_M_YEAR 0xff 91 92/* 93 * PCF2127-specific registers, bits, and masks. 94 */ 95#define PCF2127_R_TMR_CTL 0x10 /* Timer/watchdog control */ 96 97#define PCF2127_M_TMR_CTRL 0xe3 /* Mask off undef bits */ 98 99#define PCF2127_B_TMR_CD 0x40 /* Run in countdown mode */ 100#define PCF2127_B_TMR_64HZ 0x01 /* Timer frequency 64Hz */ 101 102/* 103 * PCA/PCF2129-specific registers, bits, and masks. 104 */ 105#define PCF2129_B_CS1_12HR 0x04 /* Use 12-hour (AM/PM) mode bit */ 106#define PCF2129_B_CLKOUT_OTPR 0x20 /* OTP refresh command */ 107#define PCF2129_B_CLKOUT_HIGHZ 0x07 /* Clock Out Freq = disable */ 108 109/* 110 * PCF8523-specific registers, bits, and masks. 111 */ 112#define PCF8523_R_CS3 0x02 /* Control and status reg 3 */ 113#define PCF8523_R_SECOND 0x03 /* Seconds */ 114#define PCF8523_R_TMR_CLKOUT 0x0F /* Timer and clockout control */ 115#define PCF8523_R_TMR_A_FREQ 0x10 /* Timer A frequency control */ 116#define PCF8523_R_TMR_A_COUNT 0x11 /* Timer A count */ 117 118#define PCF8523_M_TMR_A_FREQ 0x07 /* Mask off undef bits */ 119 120#define PCF8523_B_HOUR_PM 0x20 /* PM bit */ 121#define PCF8523_B_CS1_SOFTRESET 0x58 /* Initiate Soft Reset bits */ 122#define PCF8523_B_CS1_12HR 0x08 /* Use 12-hour (AM/PM) mode bit */ 123#define PCF8523_B_CLKOUT_TACD 0x02 /* TimerA runs in CountDown mode */ 124#define PCF8523_B_CLKOUT_HIGHZ 0x38 /* Clock Out Freq = disable */ 125#define PCF8523_B_TMR_A_64HZ 0x01 /* Timer A freq 64Hz */ 126 127#define PCF8523_M_CS3_PM 0xE0 /* Power mode mask */ 128#define PCF8523_B_CS3_PM_NOBAT 0xE0 /* PM bits: no battery usage */ 129#define PCF8523_B_CS3_PM_STD 0x00 /* PM bits: standard */ 130#define PCF8523_B_CS3_BLF 0x04 /* Battery Low Flag bit */ 131 132/* 133 * PCF8563-specific registers, bits, and masks. 134 */ 135#define PCF8563_R_SECOND 0x02 /* Seconds */ 136#define PCF8563_R_TMR_CTRL 0x0e /* Timer control */ 137#define PCF8563_R_TMR_COUNT 0x0f /* Timer count */ 138 139#define PCF8563_M_TMR_CTRL 0x93 /* Mask off undef bits */ 140 141#define PCF8563_B_TMR_ENABLE 0x80 /* Enable countdown timer */ 142#define PCF8563_B_TMR_64HZ 0x01 /* Timer frequency 64Hz */ 143 144#define PCF8563_B_MONTH_C 0x80 /* Century bit */ 145 146/* 147 * We use the countdown timer for fractional seconds. We program it for 64 Hz, 148 * the fastest available rate that doesn't roll over in less than a second. 149 */ 150#define TMR_TICKS_SEC 64 151#define TMR_TICKS_HALFSEC 32 152 153/* 154 * The chip types we support. 155 */ 156enum { 157 TYPE_NONE, 158 TYPE_PCA2129, 159 TYPE_PCA8565, 160 TYPE_PCF2127, 161 TYPE_PCF2129, 162 TYPE_PCF8523, 163 TYPE_PCF8563, 164 165 TYPE_COUNT 166}; 167static const char *desc_strings[] = { 168 "", 169 "NXP PCA2129 RTC", 170 "NXP PCA8565 RTC", 171 "NXP PCF2127 RTC", 172 "NXP PCF2129 RTC", 173 "NXP PCF8523 RTC", 174 "NXP PCF8563 RTC", 175}; 176CTASSERT(nitems(desc_strings) == TYPE_COUNT); 177 178/* 179 * The time registers in the order they are laid out in hardware. 180 */ 181struct time_regs { 182 uint8_t sec, min, hour, day, wday, month, year; 183}; 184 185struct nxprtc_softc { 186 device_t dev; 187 device_t busdev; 188 struct intr_config_hook 189 config_hook; 190 u_int flags; /* SC_F_* flags */ 191 u_int chiptype; /* Type of PCF85xx chip */ 192 uint8_t secaddr; /* Address of seconds register */ 193 uint8_t tmcaddr; /* Address of timer count register */ 194 bool use_timer; /* Use timer for fractional sec */ 195}; 196 197#define SC_F_CPOL (1 << 0) /* Century bit means 19xx */ 198#define SC_F_AMPM (1 << 1) /* Use PM flag in hours reg */ 199 200/* 201 * We use the compat_data table to look up hint strings in the non-FDT case, so 202 * define the struct locally when we don't get it from ofw_bus_subr.h. 203 */ 204#ifdef FDT 205typedef struct ofw_compat_data nxprtc_compat_data; 206#else 207typedef struct { 208 const char *ocd_str; 209 uintptr_t ocd_data; 210} nxprtc_compat_data; 211#endif 212 213static nxprtc_compat_data compat_data[] = { 214 {"nxp,pca2129", TYPE_PCA2129}, 215 {"nxp,pca8565", TYPE_PCA8565}, 216 {"nxp,pcf2127", TYPE_PCF2127}, 217 {"nxp,pcf2129", TYPE_PCF2129}, 218 {"nxp,pcf8523", TYPE_PCF8523}, 219 {"nxp,pcf8563", TYPE_PCF8563}, 220 221 /* Undocumented compat strings known to exist in the wild... */ 222 {"pcf8563", TYPE_PCF8563}, 223 {"phg,pcf8563", TYPE_PCF8563}, 224 {"philips,pcf8563", TYPE_PCF8563}, 225 226 {NULL, TYPE_NONE}, 227}; 228 229static int 230read_reg(struct nxprtc_softc *sc, uint8_t reg, uint8_t *val) 231{ 232 233 return (iicdev_readfrom(sc->dev, reg, val, sizeof(*val), IIC_WAIT)); 234} 235 236static int 237write_reg(struct nxprtc_softc *sc, uint8_t reg, uint8_t val) 238{ 239 240 return (iicdev_writeto(sc->dev, reg, &val, sizeof(val), IIC_WAIT)); 241} 242 243static int 244read_timeregs(struct nxprtc_softc *sc, struct time_regs *tregs, uint8_t *tmr) 245{ 246 int err; 247 uint8_t sec, tmr1, tmr2; 248 249 /* 250 * The datasheet says loop to read the same timer value twice because it 251 * does not freeze while reading. To that we add our own logic that 252 * the seconds register must be the same before and after reading the 253 * timer, ensuring the fractional part is from the same second as tregs. 254 */ 255 do { 256 if (sc->use_timer) { 257 if ((err = read_reg(sc, sc->secaddr, &sec)) != 0) 258 break; 259 if ((err = read_reg(sc, sc->tmcaddr, &tmr1)) != 0) 260 break; 261 if ((err = read_reg(sc, sc->tmcaddr, &tmr2)) != 0) 262 break; 263 if (tmr1 != tmr2) 264 continue; 265 } 266 if ((err = iicdev_readfrom(sc->dev, sc->secaddr, tregs, 267 sizeof(*tregs), IIC_WAIT)) != 0) 268 break; 269 } while (sc->use_timer && tregs->sec != sec); 270 271 /* 272 * If the timer value is greater than our hz rate (or is zero), 273 * something is wrong. Maybe some other OS used the timer differently? 274 * Just set it to zero. Likewise if we're not using the timer. After 275 * the offset calc below, the zero turns into 32, the mid-second point, 276 * which in effect performs 4/5 rounding, which is just the right thing 277 * to do if we don't have fine-grained time. 278 */ 279 if (!sc->use_timer || tmr1 > TMR_TICKS_SEC) 280 tmr1 = 0; 281 282 /* 283 * Turn the downcounter into an upcounter. The timer starts counting at 284 * and rolls over at mid-second, so add half a second worth of ticks to 285 * get its zero point back in sync with the tregs.sec rollover. 286 */ 287 *tmr = (TMR_TICKS_SEC - tmr1 + TMR_TICKS_HALFSEC) % TMR_TICKS_SEC; 288 289 return (err); 290} 291 292static int 293write_timeregs(struct nxprtc_softc *sc, struct time_regs *tregs) 294{ 295 296 return (iicdev_writeto(sc->dev, sc->secaddr, tregs, 297 sizeof(*tregs), IIC_WAIT)); 298} 299 300static int 301pcf8523_start(struct nxprtc_softc *sc) 302{ 303 int err; 304 uint8_t cs1, cs3, clkout; 305 bool is2129; 306 307 is2129 = (sc->chiptype == TYPE_PCA2129 || sc->chiptype == TYPE_PCF2129); 308 309 /* Read and sanity-check the control registers. */ 310 if ((err = read_reg(sc, PCF85xx_R_CS1, &cs1)) != 0) { 311 device_printf(sc->dev, "cannot read RTC CS1 control\n"); 312 return (err); 313 } 314 if ((err = read_reg(sc, PCF8523_R_CS3, &cs3)) != 0) { 315 device_printf(sc->dev, "cannot read RTC CS3 control\n"); 316 return (err); 317 } 318 319 /* 320 * Do a full init (soft-reset) if... 321 * - The chip is in battery-disable mode (fresh from the factory). 322 * - The clock-increment STOP flag is set (this is just insane). 323 * After reset, battery disable mode has to be overridden to "standard" 324 * mode. Also, turn off clock output to save battery power. 325 */ 326 if ((cs3 & PCF8523_M_CS3_PM) == PCF8523_B_CS3_PM_NOBAT || 327 (cs1 & PCF85xx_B_CS1_STOP)) { 328 cs1 = PCF8523_B_CS1_SOFTRESET; 329 if ((err = write_reg(sc, PCF85xx_R_CS1, cs1)) != 0) { 330 device_printf(sc->dev, "cannot write CS1 control\n"); 331 return (err); 332 } 333 cs3 = PCF8523_B_CS3_PM_STD; 334 if ((err = write_reg(sc, PCF8523_R_CS3, cs3)) != 0) { 335 device_printf(sc->dev, "cannot write CS3 control\n"); 336 return (err); 337 } 338 /* 339 * For 2129 series, trigger OTP refresh by forcing the OTPR bit 340 * to zero then back to 1, then wait 100ms for the refresh, and 341 * finally set the bit back to zero with the COF_HIGHZ write. 342 */ 343 if (is2129) { 344 clkout = PCF2129_B_CLKOUT_HIGHZ; 345 if ((err = write_reg(sc, PCF8523_R_TMR_CLKOUT, 346 clkout)) != 0) { 347 device_printf(sc->dev, 348 "cannot write CLKOUT control\n"); 349 return (err); 350 } 351 if ((err = write_reg(sc, PCF8523_R_TMR_CLKOUT, 352 clkout | PCF2129_B_CLKOUT_OTPR)) != 0) { 353 device_printf(sc->dev, 354 "cannot write CLKOUT control\n"); 355 return (err); 356 } 357 pause_sbt("nxpotp", mstosbt(100), mstosbt(10), 0); 358 } else 359 clkout = PCF8523_B_CLKOUT_HIGHZ; 360 if ((err = write_reg(sc, PCF8523_R_TMR_CLKOUT, clkout)) != 0) { 361 device_printf(sc->dev, "cannot write CLKOUT control\n"); 362 return (err); 363 } 364 device_printf(sc->dev, 365 "first time startup, enabled RTC battery operation\n"); 366 367 /* 368 * Sleep briefly so the battery monitor can make a measurement, 369 * then re-read CS3 so battery-low status can be reported below. 370 */ 371 pause_sbt("nxpbat", mstosbt(100), 0, 0); 372 if ((err = read_reg(sc, PCF8523_R_CS3, &cs3)) != 0) { 373 device_printf(sc->dev, "cannot read RTC CS3 control\n"); 374 return (err); 375 } 376 } 377 378 /* Let someone know if the battery is weak. */ 379 if (cs3 & PCF8523_B_CS3_BLF) 380 device_printf(sc->dev, "WARNING: RTC battery is low\n"); 381 382 /* Remember whether we're running in AM/PM mode. */ 383 if (is2129) { 384 if (cs1 & PCF2129_B_CS1_12HR) 385 sc->flags |= SC_F_AMPM; 386 } else { 387 if (cs1 & PCF8523_B_CS1_12HR) 388 sc->flags |= SC_F_AMPM; 389 } 390 391 return (0); 392} 393 394static int 395pcf8523_start_timer(struct nxprtc_softc *sc) 396{ 397 int err; 398 uint8_t clkout, stdclk, stdfreq, tmrfreq; 399 400 /* 401 * Read the timer control and frequency regs. If they don't have the 402 * values we normally program into them then the timer count doesn't 403 * contain a valid fractional second, so zero it to prevent using a bad 404 * value. Then program the normal timer values so that on the first 405 * settime call we'll begin to use fractional time. 406 */ 407 if ((err = read_reg(sc, PCF8523_R_TMR_A_FREQ, &tmrfreq)) != 0) 408 return (err); 409 if ((err = read_reg(sc, PCF8523_R_TMR_CLKOUT, &clkout)) != 0) 410 return (err); 411 412 stdfreq = PCF8523_B_TMR_A_64HZ; 413 stdclk = PCF8523_B_CLKOUT_TACD | PCF8523_B_CLKOUT_HIGHZ; 414 415 if (clkout != stdclk || (tmrfreq & PCF8523_M_TMR_A_FREQ) != stdfreq) { 416 if ((err = write_reg(sc, sc->tmcaddr, 0)) != 0) 417 return (err); 418 if ((err = write_reg(sc, PCF8523_R_TMR_A_FREQ, stdfreq)) != 0) 419 return (err); 420 if ((err = write_reg(sc, PCF8523_R_TMR_CLKOUT, stdclk)) != 0) 421 return (err); 422 } 423 return (0); 424} 425 426static int 427pcf2127_start_timer(struct nxprtc_softc *sc) 428{ 429 int err; 430 uint8_t stdctl, tmrctl; 431 432 /* See comment in pcf8523_start_timer(). */ 433 if ((err = read_reg(sc, PCF2127_R_TMR_CTL, &tmrctl)) != 0) 434 return (err); 435 436 stdctl = PCF2127_B_TMR_CD | PCF8523_B_TMR_A_64HZ; 437 438 if ((tmrctl & PCF2127_M_TMR_CTRL) != stdctl) { 439 if ((err = write_reg(sc, sc->tmcaddr, 0)) != 0) 440 return (err); 441 if ((err = write_reg(sc, PCF2127_R_TMR_CTL, stdctl)) != 0) 442 return (err); 443 } 444 return (0); 445} 446 447static int 448pcf8563_start_timer(struct nxprtc_softc *sc) 449{ 450 int err; 451 uint8_t stdctl, tmrctl; 452 453 /* See comment in pcf8523_start_timer(). */ 454 if ((err = read_reg(sc, PCF8563_R_TMR_CTRL, &tmrctl)) != 0) 455 return (err); 456 457 stdctl = PCF8563_B_TMR_ENABLE | PCF8563_B_TMR_64HZ; 458 459 if ((tmrctl & PCF8563_M_TMR_CTRL) != stdctl) { 460 if ((err = write_reg(sc, sc->tmcaddr, 0)) != 0) 461 return (err); 462 if ((err = write_reg(sc, PCF8563_R_TMR_CTRL, stdctl)) != 0) 463 return (err); 464 } 465 return (0); 466} 467 468static void 469nxprtc_start(void *dev) 470{ 471 struct nxprtc_softc *sc; 472 int clockflags, resolution; 473 uint8_t sec; 474 475 sc = device_get_softc((device_t)dev); 476 config_intrhook_disestablish(&sc->config_hook); 477 478 /* First do chip-specific inits. */ 479 switch (sc->chiptype) { 480 case TYPE_PCA2129: 481 case TYPE_PCF2129: 482 if (pcf8523_start(sc) != 0) 483 return; 484 /* No timer to start */ 485 break; 486 case TYPE_PCF2127: 487 if (pcf8523_start(sc) != 0) 488 return; 489 if (pcf2127_start_timer(sc) != 0) { 490 device_printf(sc->dev, "cannot set up timer\n"); 491 return; 492 } 493 break; 494 case TYPE_PCF8523: 495 if (pcf8523_start(sc) != 0) 496 return; 497 if (pcf8523_start_timer(sc) != 0) { 498 device_printf(sc->dev, "cannot set up timer\n"); 499 return; 500 } 501 break; 502 case TYPE_PCA8565: 503 case TYPE_PCF8563: 504 if (pcf8563_start_timer(sc) != 0) { 505 device_printf(sc->dev, "cannot set up timer\n"); 506 return; 507 } 508 break; 509 default: 510 device_printf(sc->dev, "missing init code for this chiptype\n"); 511 return; 512 } 513 514 /* 515 * Common init. Read the seconds register so we can check the 516 * oscillator-stopped status bit in it. 517 */ 518 if (read_reg(sc, sc->secaddr, &sec) != 0) { 519 device_printf(sc->dev, "cannot read RTC seconds\n"); 520 return; 521 } 522 if ((sec & PCF85xx_B_SECOND_OS) != 0) { 523 device_printf(sc->dev, 524 "WARNING: RTC battery failed; time is invalid\n"); 525 } 526 527 /* 528 * Everything looks good if we make it to here; register as an RTC. If 529 * we're using the timer to count fractional seconds, our resolution is 530 * 1e6/64, about 15.6ms. Without the timer we still align the RTC clock 531 * when setting it so our error is an average .5s when reading it. 532 * Schedule our clock_settime() method to be called at a .495ms offset 533 * into the second, because the clock hardware resets the divider chain 534 * to the mid-second point when you set the time and it takes about 5ms 535 * of i2c bus activity to set the clock. 536 */ 537 resolution = sc->use_timer ? 1000000 / TMR_TICKS_SEC : 1000000 / 2; 538 clockflags = CLOCKF_GETTIME_NO_ADJ | CLOCKF_SETTIME_NO_TS; 539 clock_register_flags(sc->dev, resolution, clockflags); 540 clock_schedule(sc->dev, 495000000); 541} 542 543static int 544nxprtc_gettime(device_t dev, struct timespec *ts) 545{ 546 struct clocktime ct; 547 struct time_regs tregs; 548 struct nxprtc_softc *sc; 549 int err; 550 uint8_t cs1, hourmask, tmrcount; 551 552 sc = device_get_softc(dev); 553 554 /* 555 * Read the time, but before using it, validate that the oscillator- 556 * stopped/power-fail bit is not set, and that the time-increment STOP 557 * bit is not set in the control reg. The latter can happen if there 558 * was an error when setting the time. 559 */ 560 if ((err = read_timeregs(sc, &tregs, &tmrcount)) != 0) { 561 device_printf(dev, "cannot read RTC time\n"); 562 return (err); 563 } 564 if ((err = read_reg(sc, PCF85xx_R_CS1, &cs1)) != 0) { 565 device_printf(dev, "cannot read RTC time\n"); 566 return (err); 567 } 568 if ((tregs.sec & PCF85xx_B_SECOND_OS) || (cs1 & PCF85xx_B_CS1_STOP)) { 569 device_printf(dev, "RTC clock not running\n"); 570 return (EINVAL); /* hardware is good, time is not. */ 571 } 572 573 if (sc->flags & SC_F_AMPM) 574 hourmask = PCF85xx_M_12HOUR; 575 else 576 hourmask = PCF85xx_M_24HOUR; 577 578 ct.nsec = ((uint64_t)tmrcount * 1000000000) / TMR_TICKS_SEC; 579 ct.sec = FROMBCD(tregs.sec & PCF85xx_M_SECOND); 580 ct.min = FROMBCD(tregs.min & PCF85xx_M_MINUTE); 581 ct.hour = FROMBCD(tregs.hour & hourmask); 582 ct.day = FROMBCD(tregs.day & PCF85xx_M_DAY); 583 ct.mon = FROMBCD(tregs.month & PCF85xx_M_MONTH); 584 ct.year = FROMBCD(tregs.year & PCF85xx_M_YEAR); 585 ct.year += 1900; 586 if (ct.year < POSIX_BASE_YEAR) 587 ct.year += 100; /* assume [1970, 2069] */ 588 589 /* 590 * Old PCF8563 datasheets recommended that the C bit be 1 for 19xx and 0 591 * for 20xx; newer datasheets don't recommend that. We don't care, 592 * but we may co-exist with other OSes sharing the hardware. Determine 593 * existing polarity on a read so that we can preserve it on a write. 594 */ 595 if (sc->chiptype == TYPE_PCF8563) { 596 if (tregs.month & PCF8563_B_MONTH_C) { 597 if (ct.year >= 2000) 598 sc->flags |= SC_F_CPOL; 599 } else if (ct.year < 2000) 600 sc->flags |= SC_F_CPOL; 601 } 602 603 /* If this chip is running in 12-hour/AMPM mode, deal with it. */ 604 if (sc->flags & SC_F_AMPM) { 605 if (ct.hour == 12) 606 ct.hour = 0; 607 if (tregs.hour & PCF8523_B_HOUR_PM) 608 ct.hour += 12; 609 } 610 611 err = clock_ct_to_ts(&ct, ts); 612 ts->tv_sec += utc_offset(); 613 614 return (err); 615} 616 617static int 618nxprtc_settime(device_t dev, struct timespec *ts) 619{ 620 struct clocktime ct; 621 struct time_regs tregs; 622 struct nxprtc_softc *sc; 623 int err; 624 uint8_t cflag, cs1, pmflag; 625 626 sc = device_get_softc(dev); 627 628 /* 629 * We stop the clock, set the time, then restart the clock. Half a 630 * second after restarting the clock it ticks over to the next second. 631 * So to align the RTC, we schedule this function to be called when 632 * system time is roughly halfway (.495) through the current second. 633 * 634 * Reserve use of the i2c bus and stop the RTC clock. Note that if 635 * anything goes wrong from this point on, we leave the clock stopped, 636 * because we don't really know what state it's in. 637 */ 638 if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) != 0) 639 return (err); 640 if ((err = read_reg(sc, PCF85xx_R_CS1, &cs1)) != 0) 641 goto errout; 642 cs1 |= PCF85xx_B_CS1_STOP; 643 if ((err = write_reg(sc, PCF85xx_R_CS1, cs1)) != 0) 644 goto errout; 645 646 /* Grab a fresh post-sleep idea of what time it is. */ 647 getnanotime(ts); 648 ts->tv_sec -= utc_offset(); 649 ts->tv_nsec = 0; 650 clock_ts_to_ct(ts, &ct); 651 652 /* If the chip is in AMPM mode deal with the PM flag. */ 653 pmflag = 0; 654 if (sc->flags & SC_F_AMPM) { 655 if (ct.hour >= 12) { 656 ct.hour -= 12; 657 pmflag = PCF8523_B_HOUR_PM; 658 } 659 if (ct.hour == 0) 660 ct.hour = 12; 661 } 662 663 /* On 8563 set the century based on the polarity seen when reading. */ 664 cflag = 0; 665 if (sc->chiptype == TYPE_PCF8563) { 666 if ((sc->flags & SC_F_CPOL) != 0) { 667 if (ct.year >= 2000) 668 cflag = PCF8563_B_MONTH_C; 669 } else if (ct.year < 2000) 670 cflag = PCF8563_B_MONTH_C; 671 } 672 673 tregs.sec = TOBCD(ct.sec); 674 tregs.min = TOBCD(ct.min); 675 tregs.hour = TOBCD(ct.hour) | pmflag; 676 tregs.day = TOBCD(ct.day); 677 tregs.month = TOBCD(ct.mon); 678 tregs.year = TOBCD(ct.year % 100) | cflag; 679 tregs.wday = ct.dow; 680 681 /* 682 * Set the time, reset the timer count register, then start the clocks. 683 */ 684 if ((err = write_timeregs(sc, &tregs)) != 0) 685 goto errout; 686 687 if ((err = write_reg(sc, sc->tmcaddr, TMR_TICKS_SEC)) != 0) 688 return (err); 689 690 cs1 &= ~PCF85xx_B_CS1_STOP; 691 err = write_reg(sc, PCF85xx_R_CS1, cs1); 692 693errout: 694 695 iicbus_release_bus(sc->busdev, sc->dev); 696 697 if (err != 0) 698 device_printf(dev, "cannot write RTC time\n"); 699 700 return (err); 701} 702 703static int 704nxprtc_get_chiptype(device_t dev) 705{ 706#ifdef FDT 707 708 return (ofw_bus_search_compatible(dev, compat_data)->ocd_data); 709#else 710 nxprtc_compat_data *cdata; 711 const char *htype; 712 int chiptype; 713 714 /* 715 * If given a chiptype hint string, loop through the ofw compat data 716 * comparing the hinted chip type to the compat strings. The table end 717 * marker ocd_data is TYPE_NONE. 718 */ 719 if (resource_string_value(device_get_name(dev), 720 device_get_unit(dev), "compatible", &htype) == 0) { 721 for (cdata = compat_data; cdata->ocd_str != NULL; ++cdata) { 722 if (strcmp(htype, cdata->ocd_str) == 0) 723 break; 724 } 725 chiptype = cdata->ocd_data; 726 } else 727 chiptype = TYPE_NONE; 728 729 /* 730 * On non-FDT systems the historical behavior of this driver was to 731 * assume a PCF8563; keep doing that for compatibility. 732 */ 733 if (chiptype == TYPE_NONE) 734 return (TYPE_PCF8563); 735 else 736 return (chiptype); 737#endif 738} 739 740static int 741nxprtc_probe(device_t dev) 742{ 743 int chiptype, rv; 744 745#ifdef FDT 746 if (!ofw_bus_status_okay(dev)) 747 return (ENXIO); 748 rv = BUS_PROBE_GENERIC; 749#else 750 rv = BUS_PROBE_NOWILDCARD; 751#endif 752 if ((chiptype = nxprtc_get_chiptype(dev)) == TYPE_NONE) 753 return (ENXIO); 754 755 device_set_desc(dev, desc_strings[chiptype]); 756 return (rv); 757} 758 759static int 760nxprtc_attach(device_t dev) 761{ 762 struct nxprtc_softc *sc; 763 764 sc = device_get_softc(dev); 765 sc->dev = dev; 766 sc->busdev = device_get_parent(dev); 767 768 /* We need to know what kind of chip we're driving. */ 769 sc->chiptype = nxprtc_get_chiptype(dev); 770 771 /* The features and some register addresses vary by chip type. */ 772 switch (sc->chiptype) { 773 case TYPE_PCA2129: 774 case TYPE_PCF2129: 775 sc->secaddr = PCF8523_R_SECOND; 776 sc->tmcaddr = 0; 777 sc->use_timer = false; 778 break; 779 case TYPE_PCF2127: 780 case TYPE_PCF8523: 781 sc->secaddr = PCF8523_R_SECOND; 782 sc->tmcaddr = PCF8523_R_TMR_A_COUNT; 783 sc->use_timer = true; 784 break; 785 case TYPE_PCA8565: 786 case TYPE_PCF8563: 787 sc->secaddr = PCF8563_R_SECOND; 788 sc->tmcaddr = PCF8563_R_TMR_COUNT; 789 sc->use_timer = true; 790 break; 791 default: 792 device_printf(dev, "impossible: cannot determine chip type\n"); 793 return (ENXIO); 794 } 795 796 /* 797 * We have to wait until interrupts are enabled. Sometimes I2C read 798 * and write only works when the interrupts are available. 799 */ 800 sc->config_hook.ich_func = nxprtc_start; 801 sc->config_hook.ich_arg = dev; 802 if (config_intrhook_establish(&sc->config_hook) != 0) 803 return (ENOMEM); 804 805 return (0); 806} 807 808static int 809nxprtc_detach(device_t dev) 810{ 811 812 clock_unregister(dev); 813 return (0); 814} 815 816static device_method_t nxprtc_methods[] = { 817 DEVMETHOD(device_probe, nxprtc_probe), 818 DEVMETHOD(device_attach, nxprtc_attach), 819 DEVMETHOD(device_detach, nxprtc_detach), 820 821 DEVMETHOD(clock_gettime, nxprtc_gettime), 822 DEVMETHOD(clock_settime, nxprtc_settime), 823 824 DEVMETHOD_END 825}; 826 827static driver_t nxprtc_driver = { 828 "nxprtc", 829 nxprtc_methods, 830 sizeof(struct nxprtc_softc), 831}; 832 833static devclass_t nxprtc_devclass; 834 835DRIVER_MODULE(nxprtc, iicbus, nxprtc_driver, nxprtc_devclass, NULL, NULL); 836MODULE_VERSION(nxprtc, 1); 837MODULE_DEPEND(nxprtc, iicbus, IICBB_MINVER, IICBB_PREFVER, IICBB_MAXVER); 838