1235783Skib/* 2235783Skib * Copyright �� 2008 Intel Corporation 3235783Skib * 4235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 5235783Skib * copy of this software and associated documentation files (the "Software"), 6235783Skib * to deal in the Software without restriction, including without limitation 7235783Skib * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8235783Skib * and/or sell copies of the Software, and to permit persons to whom the 9235783Skib * Software is furnished to do so, subject to the following conditions: 10235783Skib * 11235783Skib * The above copyright notice and this permission notice (including the next 12235783Skib * paragraph) shall be included in all copies or substantial portions of the 13235783Skib * Software. 14235783Skib * 15235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16235783Skib * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17235783Skib * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18235783Skib * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19235783Skib * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20235783Skib * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21235783Skib * IN THE SOFTWARE. 22235783Skib * 23235783Skib * Authors: 24235783Skib * Eric Anholt <eric@anholt.net> 25235783Skib * Keith Packard <keithp@keithp.com> 26235783Skib * 27235783Skib */ 28235783Skib 29235783Skib#include <sys/cdefs.h> 30235783Skib__FBSDID("$FreeBSD$"); 31235783Skib 32235783Skib#include <dev/drm2/drmP.h> 33235783Skib#include <dev/drm2/drm.h> 34235783Skib#include <dev/drm2/i915/i915_drm.h> 35235783Skib#include <dev/drm2/i915/i915_drv.h> 36235783Skib#include <dev/drm2/i915/intel_drv.h> 37235783Skib#include <dev/drm2/i915/intel_ringbuffer.h> 38235783Skib 39235783Skib#include <sys/sysctl.h> 40235783Skib 41296548Sdumbbell#define seq_printf(m, fmt, ...) sbuf_printf((m), (fmt), ##__VA_ARGS__) 42296548Sdumbbell 43296548Sdumbbell//#if defined(CONFIG_DEBUG_FS) 44296548Sdumbbell 45235783Skibenum { 46235783Skib ACTIVE_LIST, 47235783Skib INACTIVE_LIST, 48235783Skib PINNED_LIST, 49235783Skib}; 50235783Skib 51280183Sdumbbellstatic const char *yesno(int v) 52235783Skib{ 53280183Sdumbbell return v ? "yes" : "no"; 54235783Skib} 55235783Skib 56280183Sdumbbellstatic int i915_capabilities(struct drm_device *dev, struct sbuf *m, void *data) 57235783Skib{ 58235783Skib const struct intel_device_info *info = INTEL_INFO(dev); 59235783Skib 60296548Sdumbbell seq_printf(m, "gen: %d\n", info->gen); 61296548Sdumbbell seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); 62296548Sdumbbell#define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) 63296548Sdumbbell#define DEV_INFO_SEP ; 64296548Sdumbbell DEV_INFO_FLAGS; 65296548Sdumbbell#undef DEV_INFO_FLAG 66296548Sdumbbell#undef DEV_INFO_SEP 67235783Skib 68280183Sdumbbell return 0; 69235783Skib} 70235783Skib 71280183Sdumbbellstatic const char *get_pin_flag(struct drm_i915_gem_object *obj) 72235783Skib{ 73235783Skib if (obj->user_pin_count > 0) 74235783Skib return "P"; 75235783Skib else if (obj->pin_count > 0) 76235783Skib return "p"; 77235783Skib else 78235783Skib return " "; 79235783Skib} 80235783Skib 81280183Sdumbbellstatic const char *get_tiling_flag(struct drm_i915_gem_object *obj) 82235783Skib{ 83235783Skib switch (obj->tiling_mode) { 84235783Skib default: 85280183Sdumbbell case I915_TILING_NONE: return " "; 86280183Sdumbbell case I915_TILING_X: return "X"; 87280183Sdumbbell case I915_TILING_Y: return "Y"; 88235783Skib } 89235783Skib} 90235783Skib 91280183Sdumbbellstatic const char *cache_level_str(int type) 92235783Skib{ 93235783Skib switch (type) { 94235783Skib case I915_CACHE_NONE: return " uncached"; 95235783Skib case I915_CACHE_LLC: return " snooped (LLC)"; 96235783Skib case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; 97280183Sdumbbell default: return ""; 98235783Skib } 99235783Skib} 100235783Skib 101235783Skibstatic void 102235783Skibdescribe_obj(struct sbuf *m, struct drm_i915_gem_object *obj) 103235783Skib{ 104296548Sdumbbell seq_printf(m, "%pK: %s%s %8zdKiB %04x %04x %d %d %d%s%s%s", 105235783Skib &obj->base, 106235783Skib get_pin_flag(obj), 107235783Skib get_tiling_flag(obj), 108235783Skib obj->base.size / 1024, 109235783Skib obj->base.read_domains, 110235783Skib obj->base.write_domain, 111296548Sdumbbell obj->last_read_seqno, 112296548Sdumbbell obj->last_write_seqno, 113235783Skib obj->last_fenced_seqno, 114235783Skib cache_level_str(obj->cache_level), 115235783Skib obj->dirty ? " dirty" : "", 116235783Skib obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); 117235783Skib if (obj->base.name) 118296548Sdumbbell seq_printf(m, " (name: %d)", obj->base.name); 119296548Sdumbbell if (obj->pin_count) 120296548Sdumbbell seq_printf(m, " (pinned x %d)", obj->pin_count); 121277487Skib if (obj->pin_display) 122296548Sdumbbell seq_printf(m, " (display)"); 123235783Skib if (obj->fence_reg != I915_FENCE_REG_NONE) 124296548Sdumbbell seq_printf(m, " (fence: %d)", obj->fence_reg); 125235783Skib if (obj->gtt_space != NULL) 126296548Sdumbbell seq_printf(m, " (gtt offset: %08x, size: %08x)", 127235783Skib obj->gtt_offset, (unsigned int)obj->gtt_space->size); 128235783Skib if (obj->pin_mappable || obj->fault_mappable) { 129235783Skib char s[3], *t = s; 130235783Skib if (obj->pin_mappable) 131235783Skib *t++ = 'p'; 132235783Skib if (obj->fault_mappable) 133235783Skib *t++ = 'f'; 134235783Skib *t = '\0'; 135296548Sdumbbell seq_printf(m, " (%s mappable)", s); 136235783Skib } 137235783Skib if (obj->ring != NULL) 138296548Sdumbbell seq_printf(m, " (%s)", obj->ring->name); 139235783Skib} 140235783Skib 141280183Sdumbbellstatic int i915_gem_object_list_info(struct drm_device *dev, struct sbuf *m, void *data) 142235783Skib{ 143235783Skib uintptr_t list = (uintptr_t)data; 144235783Skib struct list_head *head; 145235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 146235783Skib struct drm_i915_gem_object *obj; 147235783Skib size_t total_obj_size, total_gtt_size; 148235783Skib int count; 149235783Skib 150235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 151280183Sdumbbell return -EINTR; 152235783Skib 153235783Skib switch (list) { 154235783Skib case ACTIVE_LIST: 155296548Sdumbbell seq_printf(m, "Active:\n"); 156235783Skib head = &dev_priv->mm.active_list; 157235783Skib break; 158235783Skib case INACTIVE_LIST: 159296548Sdumbbell seq_printf(m, "Inactive:\n"); 160235783Skib head = &dev_priv->mm.inactive_list; 161235783Skib break; 162235783Skib default: 163235783Skib DRM_UNLOCK(dev); 164280183Sdumbbell return -EINVAL; 165235783Skib } 166235783Skib 167235783Skib total_obj_size = total_gtt_size = count = 0; 168235783Skib list_for_each_entry(obj, head, mm_list) { 169296548Sdumbbell seq_printf(m, " "); 170235783Skib describe_obj(m, obj); 171296548Sdumbbell seq_printf(m, "\n"); 172235783Skib total_obj_size += obj->base.size; 173235783Skib total_gtt_size += obj->gtt_space->size; 174235783Skib count++; 175235783Skib } 176235783Skib DRM_UNLOCK(dev); 177235783Skib 178296548Sdumbbell seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", 179235783Skib count, total_obj_size, total_gtt_size); 180280183Sdumbbell return 0; 181235783Skib} 182235783Skib 183235783Skib#define count_objects(list, member) do { \ 184235783Skib list_for_each_entry(obj, list, member) { \ 185235783Skib size += obj->gtt_space->size; \ 186235783Skib ++count; \ 187235783Skib if (obj->map_and_fenceable) { \ 188235783Skib mappable_size += obj->gtt_space->size; \ 189235783Skib ++mappable_count; \ 190235783Skib } \ 191235783Skib } \ 192235783Skib} while (0) 193235783Skib 194280183Sdumbbellstatic int i915_gem_object_info(struct drm_device *dev, struct sbuf *m, void *data) 195235783Skib{ 196235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 197296548Sdumbbell u32 count, mappable_count, purgeable_count; 198296548Sdumbbell size_t size, mappable_size, purgeable_size; 199235783Skib struct drm_i915_gem_object *obj; 200235783Skib 201235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 202280183Sdumbbell return -EINTR; 203296548Sdumbbell 204296548Sdumbbell seq_printf(m, "%u objects, %zu bytes\n", 205235783Skib dev_priv->mm.object_count, 206235783Skib dev_priv->mm.object_memory); 207235783Skib 208235783Skib size = count = mappable_size = mappable_count = 0; 209296548Sdumbbell count_objects(&dev_priv->mm.bound_list, gtt_list); 210296548Sdumbbell seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", 211235783Skib count, mappable_count, size, mappable_size); 212235783Skib 213235783Skib size = count = mappable_size = mappable_count = 0; 214235783Skib count_objects(&dev_priv->mm.active_list, mm_list); 215296548Sdumbbell seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", 216235783Skib count, mappable_count, size, mappable_size); 217235783Skib 218235783Skib size = count = mappable_size = mappable_count = 0; 219235783Skib count_objects(&dev_priv->mm.inactive_list, mm_list); 220296548Sdumbbell seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", 221235783Skib count, mappable_count, size, mappable_size); 222235783Skib 223296548Sdumbbell size = count = purgeable_size = purgeable_count = 0; 224296548Sdumbbell list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) { 225296548Sdumbbell size += obj->base.size, ++count; 226296548Sdumbbell if (obj->madv == I915_MADV_DONTNEED) 227296548Sdumbbell purgeable_size += obj->base.size, ++purgeable_count; 228296548Sdumbbell } 229296548Sdumbbell seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); 230296548Sdumbbell 231235783Skib size = count = mappable_size = mappable_count = 0; 232296548Sdumbbell list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { 233235783Skib if (obj->fault_mappable) { 234235783Skib size += obj->gtt_space->size; 235235783Skib ++count; 236235783Skib } 237235783Skib if (obj->pin_mappable) { 238235783Skib mappable_size += obj->gtt_space->size; 239235783Skib ++mappable_count; 240235783Skib } 241296548Sdumbbell if (obj->madv == I915_MADV_DONTNEED) { 242296548Sdumbbell purgeable_size += obj->base.size; 243296548Sdumbbell ++purgeable_count; 244296548Sdumbbell } 245235783Skib } 246296548Sdumbbell seq_printf(m, "%u purgeable objects, %zu bytes\n", 247296548Sdumbbell purgeable_count, purgeable_size); 248296548Sdumbbell seq_printf(m, "%u pinned mappable objects, %zu bytes\n", 249235783Skib mappable_count, mappable_size); 250296548Sdumbbell seq_printf(m, "%u fault mappable objects, %zu bytes\n", 251235783Skib count, size); 252235783Skib 253296548Sdumbbell seq_printf(m, "%zu [%zu] gtt total\n", 254235783Skib dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); 255280183Sdumbbell 256235783Skib DRM_UNLOCK(dev); 257235783Skib 258280183Sdumbbell return 0; 259235783Skib} 260235783Skib 261280183Sdumbbellstatic int i915_gem_gtt_info(struct drm_device *dev, struct sbuf *m, void *data) 262235783Skib{ 263235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 264277487Skib uintptr_t list = (uintptr_t)data; 265235783Skib struct drm_i915_gem_object *obj; 266235783Skib size_t total_obj_size, total_gtt_size; 267235783Skib int count; 268235783Skib 269235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 270280183Sdumbbell return -EINTR; 271235783Skib 272235783Skib total_obj_size = total_gtt_size = count = 0; 273296548Sdumbbell list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { 274277487Skib if (list == PINNED_LIST && obj->pin_count == 0) 275277487Skib continue; 276277487Skib 277296548Sdumbbell seq_printf(m, " "); 278235783Skib describe_obj(m, obj); 279296548Sdumbbell seq_printf(m, "\n"); 280235783Skib total_obj_size += obj->base.size; 281235783Skib total_gtt_size += obj->gtt_space->size; 282235783Skib count++; 283235783Skib } 284235783Skib 285235783Skib DRM_UNLOCK(dev); 286235783Skib 287296548Sdumbbell seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", 288235783Skib count, total_obj_size, total_gtt_size); 289235783Skib 290280183Sdumbbell return 0; 291235783Skib} 292235783Skib 293280183Sdumbbellstatic int i915_gem_pageflip_info(struct drm_device *dev, struct sbuf *m, void *data) 294235783Skib{ 295235783Skib struct intel_crtc *crtc; 296235783Skib 297235783Skib list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 298291428Sdumbbell const char pipe = pipe_name(crtc->pipe); 299291428Sdumbbell const char plane = plane_name(crtc->plane); 300291428Sdumbbell struct intel_unpin_work *work; 301235783Skib 302235783Skib mtx_lock(&dev->event_lock); 303235783Skib work = crtc->unpin_work; 304235783Skib if (work == NULL) { 305296548Sdumbbell seq_printf(m, "No flip due on pipe %c (plane %c)\n", 306235783Skib pipe, plane); 307235783Skib } else { 308296548Sdumbbell if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { 309296548Sdumbbell seq_printf(m, "Flip queued on pipe %c (plane %c)\n", 310235783Skib pipe, plane); 311235783Skib } else { 312296548Sdumbbell seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", 313235783Skib pipe, plane); 314235783Skib } 315235783Skib if (work->enable_stall_check) 316296548Sdumbbell seq_printf(m, "Stall check enabled, "); 317235783Skib else 318296548Sdumbbell seq_printf(m, "Stall check waiting for page flip ioctl, "); 319296548Sdumbbell seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); 320235783Skib 321235783Skib if (work->old_fb_obj) { 322291428Sdumbbell struct drm_i915_gem_object *obj = work->old_fb_obj; 323235783Skib if (obj) 324296548Sdumbbell seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); 325235783Skib } 326235783Skib if (work->pending_flip_obj) { 327291428Sdumbbell struct drm_i915_gem_object *obj = work->pending_flip_obj; 328235783Skib if (obj) 329296548Sdumbbell seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); 330235783Skib } 331235783Skib } 332235783Skib mtx_unlock(&dev->event_lock); 333235783Skib } 334235783Skib 335280183Sdumbbell return 0; 336235783Skib} 337235783Skib 338280183Sdumbbellstatic int i915_gem_request_info(struct drm_device *dev, struct sbuf *m, void *data) 339235783Skib{ 340235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 341296548Sdumbbell struct intel_ring_buffer *ring; 342235783Skib struct drm_i915_gem_request *gem_request; 343296548Sdumbbell int count, i; 344235783Skib 345235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 346280183Sdumbbell return -EINTR; 347235783Skib 348235783Skib count = 0; 349296548Sdumbbell for_each_ring(ring, dev_priv, i) { 350296548Sdumbbell if (list_empty(&ring->request_list)) 351296548Sdumbbell continue; 352296548Sdumbbell 353296548Sdumbbell seq_printf(m, "%s requests:\n", ring->name); 354235783Skib list_for_each_entry(gem_request, 355296548Sdumbbell &ring->request_list, 356235783Skib list) { 357296548Sdumbbell seq_printf(m, " %d @ %d\n", 358235783Skib gem_request->seqno, 359235783Skib (int) (jiffies - gem_request->emitted_jiffies)); 360235783Skib } 361235783Skib count++; 362235783Skib } 363235783Skib DRM_UNLOCK(dev); 364235783Skib 365235783Skib if (count == 0) 366296548Sdumbbell seq_printf(m, "No requests\n"); 367235783Skib 368235783Skib return 0; 369235783Skib} 370235783Skib 371291428Sdumbbellstatic void i915_ring_seqno_info(struct sbuf *m, 372291428Sdumbbell struct intel_ring_buffer *ring) 373235783Skib{ 374235783Skib if (ring->get_seqno) { 375296548Sdumbbell seq_printf(m, "Current sequence (%s): %d\n", 376296548Sdumbbell ring->name, ring->get_seqno(ring, false)); 377235783Skib } 378235783Skib} 379235783Skib 380280183Sdumbbellstatic int i915_gem_seqno_info(struct drm_device *dev, struct sbuf *m, void *data) 381235783Skib{ 382235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 383296548Sdumbbell struct intel_ring_buffer *ring; 384235783Skib int i; 385235783Skib 386235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 387280183Sdumbbell return -EINTR; 388280183Sdumbbell 389296548Sdumbbell for_each_ring(ring, dev_priv, i) 390296548Sdumbbell i915_ring_seqno_info(m, ring); 391280183Sdumbbell 392235783Skib DRM_UNLOCK(dev); 393280183Sdumbbell 394280183Sdumbbell return 0; 395235783Skib} 396235783Skib 397235783Skib 398280183Sdumbbellstatic int i915_interrupt_info(struct drm_device *dev, struct sbuf *m, void *data) 399235783Skib{ 400235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 401296548Sdumbbell struct intel_ring_buffer *ring; 402235783Skib int i, pipe; 403235783Skib 404235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 405280183Sdumbbell return -EINTR; 406235783Skib 407277487Skib if (IS_VALLEYVIEW(dev)) { 408296548Sdumbbell seq_printf(m, "Display IER:\t%08x\n", 409277487Skib I915_READ(VLV_IER)); 410296548Sdumbbell seq_printf(m, "Display IIR:\t%08x\n", 411277487Skib I915_READ(VLV_IIR)); 412296548Sdumbbell seq_printf(m, "Display IIR_RW:\t%08x\n", 413277487Skib I915_READ(VLV_IIR_RW)); 414296548Sdumbbell seq_printf(m, "Display IMR:\t%08x\n", 415277487Skib I915_READ(VLV_IMR)); 416277487Skib for_each_pipe(pipe) 417296548Sdumbbell seq_printf(m, "Pipe %c stat:\t%08x\n", 418277487Skib pipe_name(pipe), 419277487Skib I915_READ(PIPESTAT(pipe))); 420277487Skib 421296548Sdumbbell seq_printf(m, "Master IER:\t%08x\n", 422277487Skib I915_READ(VLV_MASTER_IER)); 423277487Skib 424296548Sdumbbell seq_printf(m, "Render IER:\t%08x\n", 425277487Skib I915_READ(GTIER)); 426296548Sdumbbell seq_printf(m, "Render IIR:\t%08x\n", 427277487Skib I915_READ(GTIIR)); 428296548Sdumbbell seq_printf(m, "Render IMR:\t%08x\n", 429277487Skib I915_READ(GTIMR)); 430277487Skib 431296548Sdumbbell seq_printf(m, "PM IER:\t\t%08x\n", 432277487Skib I915_READ(GEN6_PMIER)); 433296548Sdumbbell seq_printf(m, "PM IIR:\t\t%08x\n", 434277487Skib I915_READ(GEN6_PMIIR)); 435296548Sdumbbell seq_printf(m, "PM IMR:\t\t%08x\n", 436277487Skib I915_READ(GEN6_PMIMR)); 437277487Skib 438296548Sdumbbell seq_printf(m, "Port hotplug:\t%08x\n", 439277487Skib I915_READ(PORT_HOTPLUG_EN)); 440296548Sdumbbell seq_printf(m, "DPFLIPSTAT:\t%08x\n", 441277487Skib I915_READ(VLV_DPFLIPSTAT)); 442296548Sdumbbell seq_printf(m, "DPINVGTT:\t%08x\n", 443277487Skib I915_READ(DPINVGTT)); 444277487Skib 445277487Skib } else if (!HAS_PCH_SPLIT(dev)) { 446296548Sdumbbell seq_printf(m, "Interrupt enable: %08x\n", 447235783Skib I915_READ(IER)); 448296548Sdumbbell seq_printf(m, "Interrupt identity: %08x\n", 449235783Skib I915_READ(IIR)); 450296548Sdumbbell seq_printf(m, "Interrupt mask: %08x\n", 451235783Skib I915_READ(IMR)); 452235783Skib for_each_pipe(pipe) 453296548Sdumbbell seq_printf(m, "Pipe %c stat: %08x\n", 454235783Skib pipe_name(pipe), 455235783Skib I915_READ(PIPESTAT(pipe))); 456235783Skib } else { 457296548Sdumbbell seq_printf(m, "North Display Interrupt enable: %08x\n", 458235783Skib I915_READ(DEIER)); 459296548Sdumbbell seq_printf(m, "North Display Interrupt identity: %08x\n", 460235783Skib I915_READ(DEIIR)); 461296548Sdumbbell seq_printf(m, "North Display Interrupt mask: %08x\n", 462235783Skib I915_READ(DEIMR)); 463296548Sdumbbell seq_printf(m, "South Display Interrupt enable: %08x\n", 464235783Skib I915_READ(SDEIER)); 465296548Sdumbbell seq_printf(m, "South Display Interrupt identity: %08x\n", 466235783Skib I915_READ(SDEIIR)); 467296548Sdumbbell seq_printf(m, "South Display Interrupt mask: %08x\n", 468235783Skib I915_READ(SDEIMR)); 469296548Sdumbbell seq_printf(m, "Graphics Interrupt enable: %08x\n", 470235783Skib I915_READ(GTIER)); 471296548Sdumbbell seq_printf(m, "Graphics Interrupt identity: %08x\n", 472235783Skib I915_READ(GTIIR)); 473296548Sdumbbell seq_printf(m, "Graphics Interrupt mask: %08x\n", 474235783Skib I915_READ(GTIMR)); 475235783Skib } 476296548Sdumbbell seq_printf(m, "Interrupts received: %d\n", 477235783Skib atomic_read(&dev_priv->irq_received)); 478296548Sdumbbell for_each_ring(ring, dev_priv, i) { 479235783Skib if (IS_GEN6(dev) || IS_GEN7(dev)) { 480296548Sdumbbell seq_printf(m, 481291428Sdumbbell "Graphics Interrupt mask (%s): %08x\n", 482296548Sdumbbell ring->name, I915_READ_IMR(ring)); 483235783Skib } 484296548Sdumbbell i915_ring_seqno_info(m, ring); 485235783Skib } 486235783Skib DRM_UNLOCK(dev); 487235783Skib 488280183Sdumbbell return 0; 489235783Skib} 490235783Skib 491280183Sdumbbellstatic int i915_gem_fence_regs_info(struct drm_device *dev, struct sbuf *m, void *data) 492235783Skib{ 493235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 494235783Skib int i; 495235783Skib 496235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 497280183Sdumbbell return -EINTR; 498235783Skib 499296548Sdumbbell seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); 500296548Sdumbbell seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); 501235783Skib for (i = 0; i < dev_priv->num_fence_regs; i++) { 502235783Skib struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; 503235783Skib 504296548Sdumbbell seq_printf(m, "Fence %d, pin count = %d, object = ", 505296548Sdumbbell i, dev_priv->fence_regs[i].pin_count); 506235783Skib if (obj == NULL) 507296548Sdumbbell seq_printf(m, "unused"); 508235783Skib else 509235783Skib describe_obj(m, obj); 510296548Sdumbbell seq_printf(m, "\n"); 511235783Skib } 512235783Skib 513235783Skib DRM_UNLOCK(dev); 514280183Sdumbbell return 0; 515235783Skib} 516235783Skib 517280183Sdumbbellstatic int i915_hws_info(struct drm_device *dev, struct sbuf *m, void *data) 518235783Skib{ 519235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 520235783Skib struct intel_ring_buffer *ring; 521280183Sdumbbell const volatile u32 __iomem *hws; 522235783Skib int i; 523235783Skib 524296548Sdumbbell ring = &dev_priv->ring[(uintptr_t)data]; 525296548Sdumbbell hws = (volatile u32 __iomem *)ring->status_page.page_addr; 526235783Skib if (hws == NULL) 527280183Sdumbbell return 0; 528235783Skib 529235783Skib for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { 530296548Sdumbbell seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", 531235783Skib i * 4, 532235783Skib hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); 533235783Skib } 534280183Sdumbbell return 0; 535235783Skib} 536235783Skib 537280183Sdumbbellstatic const char *ring_str(int ring) 538235783Skib{ 539235783Skib switch (ring) { 540296548Sdumbbell case RCS: return "render"; 541296548Sdumbbell case VCS: return "bsd"; 542296548Sdumbbell case BCS: return "blt"; 543280183Sdumbbell default: return ""; 544235783Skib } 545235783Skib} 546235783Skib 547280183Sdumbbellstatic const char *pin_flag(int pinned) 548235783Skib{ 549235783Skib if (pinned > 0) 550280183Sdumbbell return " P"; 551235783Skib else if (pinned < 0) 552280183Sdumbbell return " p"; 553235783Skib else 554280183Sdumbbell return ""; 555235783Skib} 556235783Skib 557235783Skibstatic const char *tiling_flag(int tiling) 558235783Skib{ 559235783Skib switch (tiling) { 560235783Skib default: 561235783Skib case I915_TILING_NONE: return ""; 562235783Skib case I915_TILING_X: return " X"; 563235783Skib case I915_TILING_Y: return " Y"; 564235783Skib } 565235783Skib} 566235783Skib 567235783Skibstatic const char *dirty_flag(int dirty) 568235783Skib{ 569235783Skib return dirty ? " dirty" : ""; 570235783Skib} 571235783Skib 572235783Skibstatic const char *purgeable_flag(int purgeable) 573235783Skib{ 574235783Skib return purgeable ? " purgeable" : ""; 575235783Skib} 576235783Skib 577280183Sdumbbellstatic void print_error_buffers(struct sbuf *m, 578280183Sdumbbell const char *name, 579280183Sdumbbell struct drm_i915_error_buffer *err, 580280183Sdumbbell int count) 581235783Skib{ 582235783Skib 583296548Sdumbbell seq_printf(m, "%s [%d]:\n", name, count); 584235783Skib 585235783Skib while (count--) { 586296548Sdumbbell seq_printf(m, " %08x %8u %04x %04x %x %x%s%s%s%s%s%s%s", 587235783Skib err->gtt_offset, 588235783Skib err->size, 589235783Skib err->read_domains, 590235783Skib err->write_domain, 591296548Sdumbbell err->rseqno, err->wseqno, 592235783Skib pin_flag(err->pinned), 593235783Skib tiling_flag(err->tiling), 594235783Skib dirty_flag(err->dirty), 595235783Skib purgeable_flag(err->purgeable), 596235783Skib err->ring != -1 ? " " : "", 597235783Skib ring_str(err->ring), 598235783Skib cache_level_str(err->cache_level)); 599235783Skib 600235783Skib if (err->name) 601296548Sdumbbell seq_printf(m, " (name: %d)", err->name); 602235783Skib if (err->fence_reg != I915_FENCE_REG_NONE) 603296548Sdumbbell seq_printf(m, " (fence: %d)", err->fence_reg); 604235783Skib 605296548Sdumbbell seq_printf(m, "\n"); 606235783Skib err++; 607235783Skib } 608235783Skib} 609235783Skib 610280183Sdumbbellstatic void i915_ring_error_state(struct sbuf *m, 611280183Sdumbbell struct drm_device *dev, 612280183Sdumbbell struct drm_i915_error_state *error, 613280183Sdumbbell unsigned ring) 614235783Skib{ 615296548Sdumbbell MPASS((ring < I915_NUM_RINGS)); /* shut up confused gcc */ 616296548Sdumbbell seq_printf(m, "%s command stream:\n", ring_str(ring)); 617296548Sdumbbell seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]); 618296548Sdumbbell seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); 619296548Sdumbbell seq_printf(m, " CTL: 0x%08x\n", error->ctl[ring]); 620296548Sdumbbell seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); 621296548Sdumbbell seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); 622296548Sdumbbell seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); 623296548Sdumbbell seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); 624296548Sdumbbell if (ring == RCS && INTEL_INFO(dev)->gen >= 4) 625296548Sdumbbell seq_printf(m, " BBADDR: 0x%08jx\n", error->bbaddr); 626235783Skib 627235783Skib if (INTEL_INFO(dev)->gen >= 4) 628296548Sdumbbell seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); 629296548Sdumbbell seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); 630296548Sdumbbell seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); 631235783Skib if (INTEL_INFO(dev)->gen >= 6) { 632296548Sdumbbell seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]); 633296548Sdumbbell seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); 634296548Sdumbbell seq_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 635296548Sdumbbell error->semaphore_mboxes[ring][0], 636296548Sdumbbell error->semaphore_seqno[ring][0]); 637296548Sdumbbell seq_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 638296548Sdumbbell error->semaphore_mboxes[ring][1], 639296548Sdumbbell error->semaphore_seqno[ring][1]); 640235783Skib } 641296548Sdumbbell seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); 642296548Sdumbbell seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring])); 643296548Sdumbbell seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); 644296548Sdumbbell seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); 645235783Skib} 646235783Skib 647280183Sdumbbellstatic int i915_error_state(struct drm_device *dev, struct sbuf *m, 648235783Skib void *unused) 649235783Skib{ 650235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 651235783Skib struct drm_i915_error_state *error; 652277487Skib struct intel_ring_buffer *ring; 653235783Skib int i, j, page, offset, elt; 654235783Skib 655235783Skib mtx_lock(&dev_priv->error_lock); 656277487Skib error = dev_priv->first_error; 657277487Skib if (error != NULL) 658277487Skib refcount_acquire(&error->ref); 659277487Skib mtx_unlock(&dev_priv->error_lock); 660296548Sdumbbell 661280183Sdumbbell if (!error) { 662296548Sdumbbell seq_printf(m, "no error state collected\n"); 663280183Sdumbbell return 0; 664235783Skib } 665235783Skib 666296548Sdumbbell seq_printf(m, "Time: %jd s %jd us\n", (intmax_t)error->time.tv_sec, 667235783Skib (intmax_t)error->time.tv_usec); 668296548Sdumbbell seq_printf(m, "Kernel: %s\n", version); 669296548Sdumbbell seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); 670296548Sdumbbell seq_printf(m, "EIR: 0x%08x\n", error->eir); 671296548Sdumbbell seq_printf(m, "IER: 0x%08x\n", error->ier); 672296548Sdumbbell seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 673296548Sdumbbell seq_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 674296548Sdumbbell seq_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 675296548Sdumbbell seq_printf(m, "CCID: 0x%08x\n", error->ccid); 676235783Skib 677235783Skib for (i = 0; i < dev_priv->num_fence_regs; i++) 678296548Sdumbbell seq_printf(m, " fence[%d] = %08jx\n", i, 679235783Skib (uintmax_t)error->fence[i]); 680235783Skib 681296548Sdumbbell for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 682296548Sdumbbell seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]); 683296548Sdumbbell 684235783Skib if (INTEL_INFO(dev)->gen >= 6) { 685296548Sdumbbell seq_printf(m, "ERROR: 0x%08x\n", error->error); 686296548Sdumbbell seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 687235783Skib } 688235783Skib 689296548Sdumbbell if (INTEL_INFO(dev)->gen == 7) 690296548Sdumbbell seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 691296548Sdumbbell 692277487Skib for_each_ring(ring, dev_priv, i) 693277487Skib i915_ring_error_state(m, dev, error, i); 694235783Skib 695235783Skib if (error->active_bo) 696235783Skib print_error_buffers(m, "Active", 697235783Skib error->active_bo, 698235783Skib error->active_bo_count); 699235783Skib 700235783Skib if (error->pinned_bo) 701235783Skib print_error_buffers(m, "Pinned", 702235783Skib error->pinned_bo, 703235783Skib error->pinned_bo_count); 704235783Skib 705280183Sdumbbell for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 706235783Skib struct drm_i915_error_object *obj; 707280183Sdumbbell 708235783Skib if ((obj = error->ring[i].batchbuffer)) { 709296548Sdumbbell seq_printf(m, "%s --- gtt_offset = 0x%08x\n", 710296548Sdumbbell dev_priv->ring[i].name, 711235783Skib obj->gtt_offset); 712235783Skib offset = 0; 713235783Skib for (page = 0; page < obj->page_count; page++) { 714235783Skib for (elt = 0; elt < PAGE_SIZE/4; elt++) { 715296548Sdumbbell seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); 716235783Skib offset += 4; 717235783Skib } 718235783Skib } 719235783Skib } 720235783Skib 721235783Skib if (error->ring[i].num_requests) { 722296548Sdumbbell seq_printf(m, "%s --- %d requests\n", 723296548Sdumbbell dev_priv->ring[i].name, 724235783Skib error->ring[i].num_requests); 725235783Skib for (j = 0; j < error->ring[i].num_requests; j++) { 726296548Sdumbbell seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 727235783Skib error->ring[i].requests[j].seqno, 728235783Skib error->ring[i].requests[j].jiffies, 729235783Skib error->ring[i].requests[j].tail); 730235783Skib } 731235783Skib } 732235783Skib 733235783Skib if ((obj = error->ring[i].ringbuffer)) { 734296548Sdumbbell seq_printf(m, "%s --- ringbuffer = 0x%08x\n", 735296548Sdumbbell dev_priv->ring[i].name, 736235783Skib obj->gtt_offset); 737235783Skib offset = 0; 738235783Skib for (page = 0; page < obj->page_count; page++) { 739235783Skib for (elt = 0; elt < PAGE_SIZE/4; elt++) { 740296548Sdumbbell seq_printf(m, "%08x : %08x\n", 741235783Skib offset, 742235783Skib obj->pages[page][elt]); 743235783Skib offset += 4; 744235783Skib } 745235783Skib } 746235783Skib } 747235783Skib } 748235783Skib 749235783Skib if (error->overlay) 750235783Skib intel_overlay_print_error_state(m, error->overlay); 751235783Skib 752235783Skib if (error->display) 753235783Skib intel_display_print_error_state(m, dev, error->display); 754235783Skib 755277487Skib if (refcount_release(&error->ref)) 756277487Skib i915_error_state_free(error); 757235783Skib 758280183Sdumbbell return 0; 759235783Skib} 760235783Skib 761235783Skibstatic int 762291428Sdumbbelli915_error_state_write(struct drm_device *dev, const char *str, void *unused) 763277487Skib{ 764277487Skib 765277487Skib DRM_DEBUG_DRIVER("Resetting error state\n"); 766296548Sdumbbell 767296548Sdumbbell DRM_LOCK(dev); 768296548Sdumbbell i915_destroy_error_state(dev); 769296548Sdumbbell DRM_UNLOCK(dev); 770296548Sdumbbell 771277487Skib return (0); 772277487Skib} 773277487Skib 774291428Sdumbbellstatic int i915_rstdby_delays(struct drm_device *dev, struct sbuf *m, void *unused) 775235783Skib{ 776235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 777235783Skib u16 crstanddelay; 778235783Skib 779235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 780280183Sdumbbell return -EINTR; 781280183Sdumbbell 782235783Skib crstanddelay = I915_READ16(CRSTANDVID); 783280183Sdumbbell 784235783Skib DRM_UNLOCK(dev); 785235783Skib 786296548Sdumbbell seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); 787235783Skib 788235783Skib return 0; 789235783Skib} 790235783Skib 791280183Sdumbbellstatic int i915_cur_delayinfo(struct drm_device *dev, struct sbuf *m, void *unused) 792235783Skib{ 793235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 794235783Skib 795235783Skib if (IS_GEN5(dev)) { 796235783Skib u16 rgvswctl = I915_READ16(MEMSWCTL); 797235783Skib u16 rgvstat = I915_READ16(MEMSTAT_ILK); 798235783Skib 799296548Sdumbbell seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 800296548Sdumbbell seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); 801296548Sdumbbell seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 802235783Skib MEMSTAT_VID_SHIFT); 803296548Sdumbbell seq_printf(m, "Current P-state: %d\n", 804235783Skib (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 805296548Sdumbbell } else if (IS_GEN6(dev) || IS_GEN7(dev)) { 806235783Skib u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 807235783Skib u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); 808235783Skib u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 809296548Sdumbbell u32 rpstat, cagf; 810235783Skib u32 rpupei, rpcurup, rpprevup; 811235783Skib u32 rpdownei, rpcurdown, rpprevdown; 812235783Skib int max_freq; 813235783Skib 814235783Skib /* RPSTAT1 is in the GT power well */ 815235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 816280183Sdumbbell return -EINTR; 817235783Skib gen6_gt_force_wake_get(dev_priv); 818235783Skib 819235783Skib rpstat = I915_READ(GEN6_RPSTAT1); 820235783Skib rpupei = I915_READ(GEN6_RP_CUR_UP_EI); 821235783Skib rpcurup = I915_READ(GEN6_RP_CUR_UP); 822235783Skib rpprevup = I915_READ(GEN6_RP_PREV_UP); 823235783Skib rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); 824235783Skib rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); 825235783Skib rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); 826296548Sdumbbell if (IS_HASWELL(dev)) 827296548Sdumbbell cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 828296548Sdumbbell else 829296548Sdumbbell cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 830296548Sdumbbell cagf *= GT_FREQUENCY_MULTIPLIER; 831235783Skib 832235783Skib gen6_gt_force_wake_put(dev_priv); 833235783Skib DRM_UNLOCK(dev); 834235783Skib 835296548Sdumbbell seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 836296548Sdumbbell seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); 837296548Sdumbbell seq_printf(m, "Render p-state ratio: %d\n", 838235783Skib (gt_perf_status & 0xff00) >> 8); 839296548Sdumbbell seq_printf(m, "Render p-state VID: %d\n", 840235783Skib gt_perf_status & 0xff); 841296548Sdumbbell seq_printf(m, "Render p-state limit: %d\n", 842235783Skib rp_state_limits & 0xff); 843296548Sdumbbell seq_printf(m, "CAGF: %dMHz\n", cagf); 844296548Sdumbbell seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & 845235783Skib GEN6_CURICONT_MASK); 846296548Sdumbbell seq_printf(m, "RP CUR UP: %dus\n", rpcurup & 847235783Skib GEN6_CURBSYTAVG_MASK); 848296548Sdumbbell seq_printf(m, "RP PREV UP: %dus\n", rpprevup & 849235783Skib GEN6_CURBSYTAVG_MASK); 850296548Sdumbbell seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & 851235783Skib GEN6_CURIAVG_MASK); 852296548Sdumbbell seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & 853235783Skib GEN6_CURBSYTAVG_MASK); 854296548Sdumbbell seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & 855235783Skib GEN6_CURBSYTAVG_MASK); 856235783Skib 857235783Skib max_freq = (rp_state_cap & 0xff0000) >> 16; 858296548Sdumbbell seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 859296548Sdumbbell max_freq * GT_FREQUENCY_MULTIPLIER); 860235783Skib 861235783Skib max_freq = (rp_state_cap & 0xff00) >> 8; 862296548Sdumbbell seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 863296548Sdumbbell max_freq * GT_FREQUENCY_MULTIPLIER); 864235783Skib 865235783Skib max_freq = rp_state_cap & 0xff; 866296548Sdumbbell seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 867296548Sdumbbell max_freq * GT_FREQUENCY_MULTIPLIER); 868235783Skib } else { 869296548Sdumbbell seq_printf(m, "no P-state info available\n"); 870235783Skib } 871235783Skib 872235783Skib return 0; 873235783Skib} 874235783Skib 875280183Sdumbbellstatic int i915_delayfreq_table(struct drm_device *dev, struct sbuf *m, void *unused) 876235783Skib{ 877235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 878235783Skib u32 delayfreq; 879235783Skib int i; 880235783Skib 881235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 882280183Sdumbbell return -EINTR; 883280183Sdumbbell 884235783Skib for (i = 0; i < 16; i++) { 885235783Skib delayfreq = I915_READ(PXVFREQ_BASE + i * 4); 886296548Sdumbbell seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, 887235783Skib (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); 888235783Skib } 889280183Sdumbbell 890235783Skib DRM_UNLOCK(dev); 891280183Sdumbbell 892280183Sdumbbell return 0; 893235783Skib} 894235783Skib 895280183Sdumbbellstatic inline int MAP_TO_MV(int map) 896235783Skib{ 897235783Skib return 1250 - (map * 25); 898235783Skib} 899235783Skib 900280183Sdumbbellstatic int i915_inttoext_table(struct drm_device *dev, struct sbuf *m, void *unused) 901235783Skib{ 902235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 903235783Skib u32 inttoext; 904235783Skib int i; 905235783Skib 906235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 907280183Sdumbbell return -EINTR; 908280183Sdumbbell 909235783Skib for (i = 1; i <= 32; i++) { 910235783Skib inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); 911296548Sdumbbell seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); 912235783Skib } 913280183Sdumbbell 914235783Skib DRM_UNLOCK(dev); 915235783Skib 916280183Sdumbbell return 0; 917235783Skib} 918235783Skib 919280183Sdumbbellstatic int ironlake_drpc_info(struct drm_device *dev, struct sbuf *m) 920235783Skib{ 921235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 922291428Sdumbbell u32 rgvmodectl, rstdbyctl; 923235783Skib u16 crstandvid; 924235783Skib 925235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 926280183Sdumbbell return -EINTR; 927280183Sdumbbell 928235783Skib rgvmodectl = I915_READ(MEMMODECTL); 929235783Skib rstdbyctl = I915_READ(RSTDBYCTL); 930235783Skib crstandvid = I915_READ16(CRSTANDVID); 931280183Sdumbbell 932235783Skib DRM_UNLOCK(dev); 933235783Skib 934296548Sdumbbell seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? 935235783Skib "yes" : "no"); 936296548Sdumbbell seq_printf(m, "Boost freq: %d\n", 937235783Skib (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 938235783Skib MEMMODE_BOOST_FREQ_SHIFT); 939296548Sdumbbell seq_printf(m, "HW control enabled: %s\n", 940235783Skib rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); 941296548Sdumbbell seq_printf(m, "SW control enabled: %s\n", 942235783Skib rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); 943296548Sdumbbell seq_printf(m, "Gated voltage change: %s\n", 944235783Skib rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); 945296548Sdumbbell seq_printf(m, "Starting frequency: P%d\n", 946235783Skib (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 947296548Sdumbbell seq_printf(m, "Max P-state: P%d\n", 948235783Skib (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 949296548Sdumbbell seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 950296548Sdumbbell seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 951296548Sdumbbell seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 952296548Sdumbbell seq_printf(m, "Render standby enabled: %s\n", 953235783Skib (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); 954296548Sdumbbell seq_printf(m, "Current RS state: "); 955235783Skib switch (rstdbyctl & RSX_STATUS_MASK) { 956235783Skib case RSX_STATUS_ON: 957296548Sdumbbell seq_printf(m, "on\n"); 958235783Skib break; 959235783Skib case RSX_STATUS_RC1: 960296548Sdumbbell seq_printf(m, "RC1\n"); 961235783Skib break; 962235783Skib case RSX_STATUS_RC1E: 963296548Sdumbbell seq_printf(m, "RC1E\n"); 964235783Skib break; 965235783Skib case RSX_STATUS_RS1: 966296548Sdumbbell seq_printf(m, "RS1\n"); 967235783Skib break; 968235783Skib case RSX_STATUS_RS2: 969296548Sdumbbell seq_printf(m, "RS2 (RC6)\n"); 970235783Skib break; 971235783Skib case RSX_STATUS_RS3: 972296548Sdumbbell seq_printf(m, "RC3 (RC6+)\n"); 973235783Skib break; 974235783Skib default: 975296548Sdumbbell seq_printf(m, "unknown\n"); 976235783Skib break; 977235783Skib } 978235783Skib 979235783Skib return 0; 980235783Skib} 981235783Skib 982280183Sdumbbellstatic int gen6_drpc_info(struct drm_device *dev, struct sbuf *m) 983235783Skib{ 984296548Sdumbbell struct drm_i915_private *dev_priv = dev->dev_private; 985296548Sdumbbell u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; 986235783Skib unsigned forcewake_count; 987235783Skib int count=0; 988235783Skib 989280183Sdumbbell 990235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 991280183Sdumbbell return -EINTR; 992235783Skib 993235783Skib mtx_lock(&dev_priv->gt_lock); 994235783Skib forcewake_count = dev_priv->forcewake_count; 995235783Skib mtx_unlock(&dev_priv->gt_lock); 996235783Skib 997235783Skib if (forcewake_count) { 998296548Sdumbbell seq_printf(m, "RC information inaccurate because somebody " 999296548Sdumbbell "holds a forcewake reference \n"); 1000235783Skib } else { 1001235783Skib /* NB: we cannot use forcewake, else we read the wrong values */ 1002235783Skib while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) 1003280183Sdumbbell udelay(10); 1004296548Sdumbbell seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); 1005235783Skib } 1006235783Skib 1007235783Skib gt_core_status = DRM_READ32(dev_priv->mmio_map, GEN6_GT_CORE_STATUS); 1008235783Skib trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); 1009235783Skib 1010235783Skib rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1011235783Skib rcctl1 = I915_READ(GEN6_RC_CONTROL); 1012235783Skib DRM_UNLOCK(dev); 1013296548Sdumbbell sx_xlock(&dev_priv->rps.hw_lock); 1014296548Sdumbbell sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 1015296548Sdumbbell sx_xunlock(&dev_priv->rps.hw_lock); 1016235783Skib 1017296548Sdumbbell seq_printf(m, "Video Turbo Mode: %s\n", 1018235783Skib yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1019296548Sdumbbell seq_printf(m, "HW control enabled: %s\n", 1020235783Skib yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1021296548Sdumbbell seq_printf(m, "SW control enabled: %s\n", 1022235783Skib yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1023235783Skib GEN6_RP_MEDIA_SW_MODE)); 1024296548Sdumbbell seq_printf(m, "RC1e Enabled: %s\n", 1025235783Skib yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 1026296548Sdumbbell seq_printf(m, "RC6 Enabled: %s\n", 1027235783Skib yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 1028296548Sdumbbell seq_printf(m, "Deep RC6 Enabled: %s\n", 1029235783Skib yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 1030296548Sdumbbell seq_printf(m, "Deepest RC6 Enabled: %s\n", 1031235783Skib yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 1032296548Sdumbbell seq_printf(m, "Current RC state: "); 1033235783Skib switch (gt_core_status & GEN6_RCn_MASK) { 1034235783Skib case GEN6_RC0: 1035235783Skib if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 1036296548Sdumbbell seq_printf(m, "Core Power Down\n"); 1037235783Skib else 1038296548Sdumbbell seq_printf(m, "on\n"); 1039235783Skib break; 1040235783Skib case GEN6_RC3: 1041296548Sdumbbell seq_printf(m, "RC3\n"); 1042235783Skib break; 1043235783Skib case GEN6_RC6: 1044296548Sdumbbell seq_printf(m, "RC6\n"); 1045235783Skib break; 1046235783Skib case GEN6_RC7: 1047296548Sdumbbell seq_printf(m, "RC7\n"); 1048235783Skib break; 1049235783Skib default: 1050296548Sdumbbell seq_printf(m, "Unknown\n"); 1051235783Skib break; 1052235783Skib } 1053235783Skib 1054296548Sdumbbell seq_printf(m, "Core Power Down: %s\n", 1055235783Skib yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 1056277487Skib 1057277487Skib /* Not exactly sure what this is */ 1058296548Sdumbbell seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", 1059277487Skib I915_READ(GEN6_GT_GFX_RC6_LOCKED)); 1060296548Sdumbbell seq_printf(m, "RC6 residency since boot: %u\n", 1061277487Skib I915_READ(GEN6_GT_GFX_RC6)); 1062296548Sdumbbell seq_printf(m, "RC6+ residency since boot: %u\n", 1063277487Skib I915_READ(GEN6_GT_GFX_RC6p)); 1064296548Sdumbbell seq_printf(m, "RC6++ residency since boot: %u\n", 1065277487Skib I915_READ(GEN6_GT_GFX_RC6pp)); 1066277487Skib 1067296548Sdumbbell seq_printf(m, "RC6 voltage: %dmV\n", 1068296548Sdumbbell GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 1069296548Sdumbbell seq_printf(m, "RC6+ voltage: %dmV\n", 1070296548Sdumbbell GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 1071296548Sdumbbell seq_printf(m, "RC6++ voltage: %dmV\n", 1072296548Sdumbbell GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 1073235783Skib return 0; 1074235783Skib} 1075235783Skib 1076235783Skibstatic int i915_drpc_info(struct drm_device *dev, struct sbuf *m, void *unused) 1077235783Skib{ 1078235783Skib 1079235783Skib if (IS_GEN6(dev) || IS_GEN7(dev)) 1080280183Sdumbbell return gen6_drpc_info(dev, m); 1081235783Skib else 1082280183Sdumbbell return ironlake_drpc_info(dev, m); 1083235783Skib} 1084280183Sdumbbell 1085280183Sdumbbellstatic int i915_fbc_status(struct drm_device *dev, struct sbuf *m, void *unused) 1086235783Skib{ 1087235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 1088235783Skib 1089235783Skib if (!I915_HAS_FBC(dev)) { 1090296548Sdumbbell seq_printf(m, "FBC unsupported on this chipset\n"); 1091235783Skib return 0; 1092235783Skib } 1093235783Skib 1094235783Skib if (intel_fbc_enabled(dev)) { 1095296548Sdumbbell seq_printf(m, "FBC enabled\n"); 1096235783Skib } else { 1097296548Sdumbbell seq_printf(m, "FBC disabled: "); 1098235783Skib switch (dev_priv->no_fbc_reason) { 1099235783Skib case FBC_NO_OUTPUT: 1100296548Sdumbbell seq_printf(m, "no outputs"); 1101235783Skib break; 1102235783Skib case FBC_STOLEN_TOO_SMALL: 1103296548Sdumbbell seq_printf(m, "not enough stolen memory"); 1104235783Skib break; 1105235783Skib case FBC_UNSUPPORTED_MODE: 1106296548Sdumbbell seq_printf(m, "mode not supported"); 1107235783Skib break; 1108235783Skib case FBC_MODE_TOO_LARGE: 1109296548Sdumbbell seq_printf(m, "mode too large"); 1110235783Skib break; 1111235783Skib case FBC_BAD_PLANE: 1112296548Sdumbbell seq_printf(m, "FBC unsupported on plane"); 1113235783Skib break; 1114235783Skib case FBC_NOT_TILED: 1115296548Sdumbbell seq_printf(m, "scanout buffer not tiled"); 1116235783Skib break; 1117235783Skib case FBC_MULTIPLE_PIPES: 1118296548Sdumbbell seq_printf(m, "multiple pipes are enabled"); 1119235783Skib break; 1120296548Sdumbbell case FBC_MODULE_PARAM: 1121296548Sdumbbell seq_printf(m, "disabled per module param (default off)"); 1122296548Sdumbbell break; 1123235783Skib default: 1124296548Sdumbbell seq_printf(m, "unknown reason"); 1125235783Skib } 1126296548Sdumbbell seq_printf(m, "\n"); 1127235783Skib } 1128235783Skib return 0; 1129235783Skib} 1130235783Skib 1131280183Sdumbbellstatic int i915_sr_status(struct drm_device *dev, struct sbuf *m, void *unused) 1132235783Skib{ 1133235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 1134235783Skib bool sr_enabled = false; 1135235783Skib 1136235783Skib if (HAS_PCH_SPLIT(dev)) 1137235783Skib sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; 1138235783Skib else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) 1139235783Skib sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; 1140235783Skib else if (IS_I915GM(dev)) 1141235783Skib sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; 1142235783Skib else if (IS_PINEVIEW(dev)) 1143235783Skib sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 1144235783Skib 1145296548Sdumbbell seq_printf(m, "self-refresh: %s\n", 1146235783Skib sr_enabled ? "enabled" : "disabled"); 1147235783Skib 1148280183Sdumbbell return 0; 1149235783Skib} 1150235783Skib 1151280183Sdumbbellstatic int i915_emon_status(struct drm_device *dev, struct sbuf *m, void *unused) 1152280183Sdumbbell{ 1153280183Sdumbbell drm_i915_private_t *dev_priv = dev->dev_private; 1154280183Sdumbbell unsigned long temp, chipset, gfx; 1155280183Sdumbbell 1156280183Sdumbbell if (!IS_GEN5(dev)) 1157280183Sdumbbell return -ENODEV; 1158280183Sdumbbell 1159280183Sdumbbell if (sx_xlock_sig(&dev->dev_struct_lock)) 1160280183Sdumbbell return -EINTR; 1161280183Sdumbbell 1162280183Sdumbbell temp = i915_mch_val(dev_priv); 1163280183Sdumbbell chipset = i915_chipset_val(dev_priv); 1164280183Sdumbbell gfx = i915_gfx_val(dev_priv); 1165280183Sdumbbell DRM_UNLOCK(dev); 1166280183Sdumbbell 1167296548Sdumbbell seq_printf(m, "GMCH temp: %ld\n", temp); 1168296548Sdumbbell seq_printf(m, "Chipset power: %ld\n", chipset); 1169296548Sdumbbell seq_printf(m, "GFX power: %ld\n", gfx); 1170296548Sdumbbell seq_printf(m, "Total power: %ld\n", chipset + gfx); 1171280183Sdumbbell 1172280183Sdumbbell return 0; 1173280183Sdumbbell} 1174280183Sdumbbell 1175235783Skibstatic int i915_ring_freq_table(struct drm_device *dev, struct sbuf *m, 1176235783Skib void *unused) 1177235783Skib{ 1178235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 1179235783Skib int gpu_freq, ia_freq; 1180235783Skib 1181235783Skib if (!(IS_GEN6(dev) || IS_GEN7(dev))) { 1182296548Sdumbbell seq_printf(m, "unsupported on this chipset\n"); 1183280183Sdumbbell return 0; 1184235783Skib } 1185235783Skib 1186296548Sdumbbell sx_xlock(&dev_priv->rps.hw_lock); 1187235783Skib 1188296548Sdumbbell seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); 1189235783Skib 1190296548Sdumbbell for (gpu_freq = dev_priv->rps.min_delay; 1191296548Sdumbbell gpu_freq <= dev_priv->rps.max_delay; 1192235783Skib gpu_freq++) { 1193296548Sdumbbell ia_freq = gpu_freq; 1194296548Sdumbbell sandybridge_pcode_read(dev_priv, 1195296548Sdumbbell GEN6_PCODE_READ_MIN_FREQ_TABLE, 1196296548Sdumbbell &ia_freq); 1197296548Sdumbbell seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100); 1198235783Skib } 1199235783Skib 1200296548Sdumbbell sx_xunlock(&dev_priv->rps.hw_lock); 1201235783Skib 1202280183Sdumbbell return 0; 1203235783Skib} 1204235783Skib 1205280183Sdumbbellstatic int i915_gfxec(struct drm_device *dev, struct sbuf *m, void *unused) 1206235783Skib{ 1207235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 1208235783Skib 1209235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 1210280183Sdumbbell return -EINTR; 1211235783Skib 1212296548Sdumbbell seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); 1213235783Skib 1214235783Skib DRM_UNLOCK(dev); 1215235783Skib 1216280183Sdumbbell return 0; 1217235783Skib} 1218235783Skib 1219235783Skib#if 0 1220280183Sdumbbellstatic int i915_opregion(struct drm_device *dev, struct sbuf *m, void *unused) 1221235783Skib{ 1222235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 1223235783Skib struct intel_opregion *opregion = &dev_priv->opregion; 1224235783Skib 1225235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 1226280183Sdumbbell return -EINTR; 1227280183Sdumbbell 1228235783Skib if (opregion->header) 1229235783Skib seq_write(m, opregion->header, OPREGION_SIZE); 1230280183Sdumbbell 1231235783Skib DRM_UNLOCK(dev); 1232235783Skib 1233235783Skib return 0; 1234235783Skib} 1235235783Skib#endif 1236235783Skib 1237280183Sdumbbellstatic int i915_gem_framebuffer_info(struct drm_device *dev, struct sbuf *m, void *data) 1238235783Skib{ 1239235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 1240235783Skib struct intel_fbdev *ifbdev; 1241235783Skib struct intel_framebuffer *fb; 1242235783Skib 1243235783Skib if (sx_xlock_sig(&dev->dev_struct_lock)) 1244280183Sdumbbell return -EINTR; 1245235783Skib 1246235783Skib ifbdev = dev_priv->fbdev; 1247235783Skib if (ifbdev == NULL) { 1248235783Skib DRM_UNLOCK(dev); 1249280183Sdumbbell return 0; 1250235783Skib } 1251235783Skib fb = to_intel_framebuffer(ifbdev->helper.fb); 1252235783Skib 1253296548Sdumbbell seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", 1254235783Skib fb->base.width, 1255235783Skib fb->base.height, 1256235783Skib fb->base.depth, 1257235783Skib fb->base.bits_per_pixel); 1258235783Skib describe_obj(m, fb->obj); 1259296548Sdumbbell seq_printf(m, "\n"); 1260235783Skib 1261235783Skib list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { 1262235783Skib if (&fb->base == ifbdev->helper.fb) 1263235783Skib continue; 1264235783Skib 1265296548Sdumbbell seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", 1266235783Skib fb->base.width, 1267235783Skib fb->base.height, 1268235783Skib fb->base.depth, 1269235783Skib fb->base.bits_per_pixel); 1270235783Skib describe_obj(m, fb->obj); 1271296548Sdumbbell seq_printf(m, "\n"); 1272235783Skib } 1273235783Skib 1274235783Skib DRM_UNLOCK(dev); 1275235783Skib 1276280183Sdumbbell return 0; 1277235783Skib} 1278235783Skib 1279280183Sdumbbellstatic int i915_context_status(struct drm_device *dev, struct sbuf *m, void *data) 1280235783Skib{ 1281296548Sdumbbell drm_i915_private_t *dev_priv = dev->dev_private; 1282235783Skib int ret; 1283235783Skib 1284235783Skib ret = sx_xlock_sig(&dev->mode_config.mutex); 1285235783Skib if (ret != 0) 1286280183Sdumbbell return -EINTR; 1287235783Skib 1288296548Sdumbbell if (dev_priv->ips.pwrctx) { 1289296548Sdumbbell seq_printf(m, "power context "); 1290296548Sdumbbell describe_obj(m, dev_priv->ips.pwrctx); 1291296548Sdumbbell seq_printf(m, "\n"); 1292235783Skib } 1293235783Skib 1294296548Sdumbbell if (dev_priv->ips.renderctx) { 1295296548Sdumbbell seq_printf(m, "render context "); 1296296548Sdumbbell describe_obj(m, dev_priv->ips.renderctx); 1297296548Sdumbbell seq_printf(m, "\n"); 1298235783Skib } 1299235783Skib 1300235783Skib sx_xunlock(&dev->mode_config.mutex); 1301235783Skib 1302280183Sdumbbell return 0; 1303235783Skib} 1304235783Skib 1305280183Sdumbbellstatic int i915_gen6_forcewake_count_info(struct drm_device *dev, struct sbuf *m, 1306235783Skib void *data) 1307235783Skib{ 1308291428Sdumbbell struct drm_i915_private *dev_priv = dev->dev_private; 1309235783Skib unsigned forcewake_count; 1310235783Skib 1311235783Skib mtx_lock(&dev_priv->gt_lock); 1312235783Skib forcewake_count = dev_priv->forcewake_count; 1313235783Skib mtx_unlock(&dev_priv->gt_lock); 1314235783Skib 1315296548Sdumbbell seq_printf(m, "forcewake count = %u\n", forcewake_count); 1316235783Skib 1317280183Sdumbbell return 0; 1318235783Skib} 1319235783Skib 1320280183Sdumbbellstatic const char *swizzle_string(unsigned swizzle) 1321235783Skib{ 1322235783Skib 1323235783Skib switch(swizzle) { 1324235783Skib case I915_BIT_6_SWIZZLE_NONE: 1325235783Skib return "none"; 1326235783Skib case I915_BIT_6_SWIZZLE_9: 1327235783Skib return "bit9"; 1328235783Skib case I915_BIT_6_SWIZZLE_9_10: 1329235783Skib return "bit9/bit10"; 1330235783Skib case I915_BIT_6_SWIZZLE_9_11: 1331235783Skib return "bit9/bit11"; 1332235783Skib case I915_BIT_6_SWIZZLE_9_10_11: 1333235783Skib return "bit9/bit10/bit11"; 1334235783Skib case I915_BIT_6_SWIZZLE_9_17: 1335235783Skib return "bit9/bit17"; 1336235783Skib case I915_BIT_6_SWIZZLE_9_10_17: 1337235783Skib return "bit9/bit10/bit17"; 1338235783Skib case I915_BIT_6_SWIZZLE_UNKNOWN: 1339235783Skib return "unknown"; 1340235783Skib } 1341235783Skib 1342235783Skib return "bug"; 1343235783Skib} 1344235783Skib 1345280183Sdumbbellstatic int i915_swizzle_info(struct drm_device *dev, struct sbuf *m, void *data) 1346235783Skib{ 1347291428Sdumbbell struct drm_i915_private *dev_priv = dev->dev_private; 1348235783Skib int ret; 1349235783Skib 1350235783Skib ret = sx_xlock_sig(&dev->dev_struct_lock); 1351291428Sdumbbell if (ret) 1352280183Sdumbbell return -EINTR; 1353235783Skib 1354296548Sdumbbell seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 1355235783Skib swizzle_string(dev_priv->mm.bit_6_swizzle_x)); 1356296548Sdumbbell seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 1357235783Skib swizzle_string(dev_priv->mm.bit_6_swizzle_y)); 1358235783Skib 1359235783Skib if (IS_GEN3(dev) || IS_GEN4(dev)) { 1360296548Sdumbbell seq_printf(m, "DDC = 0x%08x\n", 1361235783Skib I915_READ(DCC)); 1362296548Sdumbbell seq_printf(m, "C0DRB3 = 0x%04x\n", 1363235783Skib I915_READ16(C0DRB3)); 1364296548Sdumbbell seq_printf(m, "C1DRB3 = 0x%04x\n", 1365235783Skib I915_READ16(C1DRB3)); 1366235783Skib } else if (IS_GEN6(dev) || IS_GEN7(dev)) { 1367296548Sdumbbell seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 1368235783Skib I915_READ(MAD_DIMM_C0)); 1369296548Sdumbbell seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 1370235783Skib I915_READ(MAD_DIMM_C1)); 1371296548Sdumbbell seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 1372235783Skib I915_READ(MAD_DIMM_C2)); 1373296548Sdumbbell seq_printf(m, "TILECTL = 0x%08x\n", 1374235783Skib I915_READ(TILECTL)); 1375296548Sdumbbell seq_printf(m, "ARB_MODE = 0x%08x\n", 1376235783Skib I915_READ(ARB_MODE)); 1377296548Sdumbbell seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 1378235783Skib I915_READ(DISP_ARB_CTL)); 1379280183Sdumbbell } 1380235783Skib DRM_UNLOCK(dev); 1381235783Skib 1382280183Sdumbbell return 0; 1383235783Skib} 1384235783Skib 1385280183Sdumbbellstatic int i915_ppgtt_info(struct drm_device *dev, struct sbuf *m, void *data) 1386235783Skib{ 1387291428Sdumbbell struct drm_i915_private *dev_priv = dev->dev_private; 1388235783Skib struct intel_ring_buffer *ring; 1389235783Skib int i, ret; 1390235783Skib 1391235783Skib 1392235783Skib ret = sx_xlock_sig(&dev->dev_struct_lock); 1393291428Sdumbbell if (ret) 1394280183Sdumbbell return -EINTR; 1395235783Skib if (INTEL_INFO(dev)->gen == 6) 1396296548Sdumbbell seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); 1397235783Skib 1398296548Sdumbbell for_each_ring(ring, dev_priv, i) { 1399296548Sdumbbell seq_printf(m, "%s\n", ring->name); 1400235783Skib if (INTEL_INFO(dev)->gen == 7) 1401296548Sdumbbell seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); 1402296548Sdumbbell seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); 1403296548Sdumbbell seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); 1404296548Sdumbbell seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); 1405235783Skib } 1406235783Skib if (dev_priv->mm.aliasing_ppgtt) { 1407235783Skib struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 1408235783Skib 1409296548Sdumbbell seq_printf(m, "aliasing PPGTT:\n"); 1410296548Sdumbbell seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); 1411235783Skib } 1412296548Sdumbbell seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); 1413235783Skib DRM_UNLOCK(dev); 1414235783Skib 1415280183Sdumbbell return 0; 1416235783Skib} 1417235783Skib 1418277487Skibstatic int i915_dpio_info(struct drm_device *dev, struct sbuf *m, void *data) 1419277487Skib{ 1420291428Sdumbbell struct drm_i915_private *dev_priv = dev->dev_private; 1421277487Skib int ret; 1422277487Skib 1423291428Sdumbbell 1424277487Skib if (!IS_VALLEYVIEW(dev)) { 1425296548Sdumbbell seq_printf(m, "unsupported\n"); 1426277487Skib return 0; 1427277487Skib } 1428277487Skib 1429277487Skib ret = sx_xlock_sig(&dev->mode_config.mutex); 1430291428Sdumbbell if (ret) 1431280183Sdumbbell return -EINTR; 1432277487Skib 1433296548Sdumbbell seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); 1434277487Skib 1435296548Sdumbbell seq_printf(m, "DPIO_DIV_A: 0x%08x\n", 1436277487Skib intel_dpio_read(dev_priv, _DPIO_DIV_A)); 1437296548Sdumbbell seq_printf(m, "DPIO_DIV_B: 0x%08x\n", 1438277487Skib intel_dpio_read(dev_priv, _DPIO_DIV_B)); 1439277487Skib 1440296548Sdumbbell seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", 1441277487Skib intel_dpio_read(dev_priv, _DPIO_REFSFR_A)); 1442296548Sdumbbell seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", 1443277487Skib intel_dpio_read(dev_priv, _DPIO_REFSFR_B)); 1444277487Skib 1445296548Sdumbbell seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", 1446277487Skib intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); 1447296548Sdumbbell seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", 1448277487Skib intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); 1449277487Skib 1450296548Sdumbbell seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", 1451277487Skib intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); 1452296548Sdumbbell seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", 1453277487Skib intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); 1454277487Skib 1455296548Sdumbbell seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", 1456277487Skib intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); 1457277487Skib 1458277487Skib sx_xunlock(&dev->mode_config.mutex); 1459277487Skib 1460277487Skib return 0; 1461277487Skib} 1462277487Skib 1463235783Skibstatic int 1464296548Sdumbbelli915_wedged(SYSCTL_HANDLER_ARGS) 1465235783Skib{ 1466291428Sdumbbell struct drm_device *dev = arg1; 1467291428Sdumbbell drm_i915_private_t *dev_priv = dev->dev_private; 1468296548Sdumbbell int val = 1, ret; 1469235783Skib 1470235783Skib if (dev_priv == NULL) 1471235783Skib return (EBUSY); 1472296548Sdumbbell 1473296548Sdumbbell val = atomic_read(&dev_priv->mm.wedged); 1474296548Sdumbbell ret = sysctl_handle_int(oidp, &val, 0, req); 1475296548Sdumbbell if (ret != 0 || !req->newptr) 1476296548Sdumbbell return (ret); 1477296548Sdumbbell 1478296548Sdumbbell DRM_INFO("Manually setting wedged to %d\n", val); 1479296548Sdumbbell i915_handle_error(dev, val); 1480296548Sdumbbell 1481296548Sdumbbell return (ret); 1482235783Skib} 1483235783Skib 1484235783Skibstatic int 1485296548Sdumbbelli915_ring_stop(SYSCTL_HANDLER_ARGS) 1486296548Sdumbbell{ 1487296548Sdumbbell struct drm_device *dev = arg1; 1488296548Sdumbbell drm_i915_private_t *dev_priv = dev->dev_private; 1489296548Sdumbbell int val = 0, ret; 1490296548Sdumbbell 1491296548Sdumbbell if (dev_priv == NULL) 1492296548Sdumbbell return (EBUSY); 1493296548Sdumbbell 1494296548Sdumbbell val = dev_priv->stop_rings; 1495296548Sdumbbell ret = sysctl_handle_int(oidp, &val, 0, req); 1496296548Sdumbbell if (ret != 0 || !req->newptr) 1497296548Sdumbbell return (ret); 1498296548Sdumbbell 1499296548Sdumbbell DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val); 1500296548Sdumbbell 1501296548Sdumbbell sx_xlock(&dev_priv->rps.hw_lock); 1502296548Sdumbbell dev_priv->stop_rings = val; 1503296548Sdumbbell sx_xunlock(&dev_priv->rps.hw_lock); 1504296548Sdumbbell 1505296548Sdumbbell return (0); 1506296548Sdumbbell} 1507296548Sdumbbell 1508296548Sdumbbellstatic int 1509235783Skibi915_max_freq(SYSCTL_HANDLER_ARGS) 1510235783Skib{ 1511291428Sdumbbell struct drm_device *dev = arg1; 1512291428Sdumbbell drm_i915_private_t *dev_priv = dev->dev_private; 1513296548Sdumbbell int val = 1, ret; 1514235783Skib 1515235783Skib if (dev_priv == NULL) 1516235783Skib return (EBUSY); 1517296548Sdumbbell if (!(IS_GEN6(dev) || IS_GEN7(dev))) 1518296548Sdumbbell return (ENODEV); 1519296548Sdumbbell 1520296548Sdumbbell sx_xlock(&dev_priv->rps.hw_lock); 1521296548Sdumbbell 1522296548Sdumbbell val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; 1523296548Sdumbbell ret = sysctl_handle_int(oidp, &val, 0, req); 1524296548Sdumbbell if (ret != 0 || !req->newptr) { 1525296548Sdumbbell sx_xunlock(&dev_priv->rps.hw_lock); 1526296548Sdumbbell return (ret); 1527296548Sdumbbell } 1528296548Sdumbbell 1529296548Sdumbbell DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); 1530296548Sdumbbell 1531235783Skib /* 1532235783Skib * Turbo will still be enabled, but won't go above the set value. 1533235783Skib */ 1534296548Sdumbbell dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER; 1535296548Sdumbbell 1536296548Sdumbbell gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER); 1537296548Sdumbbell sx_xunlock(&dev_priv->rps.hw_lock); 1538296548Sdumbbell 1539296548Sdumbbell return (ret); 1540235783Skib} 1541235783Skib 1542235783Skibstatic int 1543296548Sdumbbelli915_min_freq(SYSCTL_HANDLER_ARGS) 1544235783Skib{ 1545291428Sdumbbell struct drm_device *dev = arg1; 1546291428Sdumbbell drm_i915_private_t *dev_priv = dev->dev_private; 1547296548Sdumbbell int val = 1, ret; 1548235783Skib 1549235783Skib if (dev_priv == NULL) 1550235783Skib return (EBUSY); 1551296548Sdumbbell if (!(IS_GEN6(dev) || IS_GEN7(dev))) 1552296548Sdumbbell return (ENODEV); 1553235783Skib 1554296548Sdumbbell sx_xlock(&dev_priv->rps.hw_lock); 1555296548Sdumbbell 1556296548Sdumbbell val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; 1557296548Sdumbbell ret = sysctl_handle_int(oidp, &val, 0, req); 1558296548Sdumbbell if (ret != 0 || !req->newptr) { 1559296548Sdumbbell sx_xunlock(&dev_priv->rps.hw_lock); 1560296548Sdumbbell return (ret); 1561296548Sdumbbell } 1562296548Sdumbbell 1563296548Sdumbbell DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val); 1564296548Sdumbbell 1565296548Sdumbbell /* 1566296548Sdumbbell * Turbo will still be enabled, but won't go above the set value. 1567296548Sdumbbell */ 1568296548Sdumbbell dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER; 1569296548Sdumbbell 1570296548Sdumbbell gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER); 1571296548Sdumbbell sx_xunlock(&dev_priv->rps.hw_lock); 1572296548Sdumbbell 1573296548Sdumbbell return (ret); 1574235783Skib} 1575235783Skib 1576277487Skibstatic int 1577296548Sdumbbelli915_cache_sharing(SYSCTL_HANDLER_ARGS) 1578277487Skib{ 1579291428Sdumbbell struct drm_device *dev = arg1; 1580291428Sdumbbell drm_i915_private_t *dev_priv = dev->dev_private; 1581296548Sdumbbell u32 snpcr; 1582296548Sdumbbell int val = 1, ret; 1583277487Skib 1584277487Skib if (dev_priv == NULL) 1585277487Skib return (EBUSY); 1586296548Sdumbbell if (!(IS_GEN6(dev) || IS_GEN7(dev))) 1587296548Sdumbbell return (ENODEV); 1588277487Skib 1589296548Sdumbbell sx_xlock(&dev_priv->rps.hw_lock); 1590296548Sdumbbell snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 1591296548Sdumbbell sx_xunlock(&dev_priv->rps.hw_lock); 1592296548Sdumbbell 1593296548Sdumbbell val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; 1594296548Sdumbbell ret = sysctl_handle_int(oidp, &val, 0, req); 1595296548Sdumbbell if (ret != 0 || !req->newptr) 1596296548Sdumbbell return (ret); 1597296548Sdumbbell 1598296548Sdumbbell if (val < 0 || val > 3) 1599296548Sdumbbell return (EINVAL); 1600296548Sdumbbell 1601296548Sdumbbell DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); 1602296548Sdumbbell 1603296548Sdumbbell /* Update the cache sharing policy here as well */ 1604296548Sdumbbell snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 1605296548Sdumbbell snpcr &= ~GEN6_MBC_SNPCR_MASK; 1606296548Sdumbbell snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); 1607296548Sdumbbell I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 1608296548Sdumbbell 1609277487Skib return (0); 1610277487Skib} 1611277487Skib 1612235783Skibstatic struct i915_info_sysctl_list { 1613235783Skib const char *name; 1614235783Skib int (*ptr)(struct drm_device *dev, struct sbuf *m, void *data); 1615277487Skib int (*ptr_w)(struct drm_device *dev, const char *str, void *data); 1616235783Skib int flags; 1617235783Skib void *data; 1618235783Skib} i915_info_sysctl_list[] = { 1619277487Skib {"i915_capabilities", i915_capabilities, NULL, 0}, 1620277487Skib {"i915_gem_objects", i915_gem_object_info, NULL, 0}, 1621277487Skib {"i915_gem_gtt", i915_gem_gtt_info, NULL, 0}, 1622277487Skib {"i915_gem_pinned", i915_gem_gtt_info, NULL, 0, (void *)PINNED_LIST}, 1623291428Sdumbbell {"i915_gem_active", i915_gem_object_list_info, NULL, 0, (void *)ACTIVE_LIST}, 1624291428Sdumbbell {"i915_gem_inactive", i915_gem_object_list_info, NULL, 0, (void *)INACTIVE_LIST}, 1625277487Skib {"i915_gem_pageflip", i915_gem_pageflip_info, NULL, 0}, 1626277487Skib {"i915_gem_request", i915_gem_request_info, NULL, 0}, 1627277487Skib {"i915_gem_seqno", i915_gem_seqno_info, NULL, 0}, 1628277487Skib {"i915_gem_fence_regs", i915_gem_fence_regs_info, NULL, 0}, 1629277487Skib {"i915_gem_interrupt", i915_interrupt_info, NULL, 0}, 1630277487Skib {"i915_gem_hws", i915_hws_info, NULL, 0, (void *)RCS}, 1631277487Skib {"i915_gem_hws_blt", i915_hws_info, NULL, 0, (void *)BCS}, 1632277487Skib {"i915_gem_hws_bsd", i915_hws_info, NULL, 0, (void *)VCS}, 1633291428Sdumbbell {"i915_error_state", i915_error_state, i915_error_state_write, 0}, 1634277487Skib {"i915_rstdby_delays", i915_rstdby_delays, NULL, 0}, 1635277487Skib {"i915_cur_delayinfo", i915_cur_delayinfo, NULL, 0}, 1636277487Skib {"i915_delayfreq_table", i915_delayfreq_table, NULL, 0}, 1637277487Skib {"i915_inttoext_table", i915_inttoext_table, NULL, 0}, 1638277487Skib {"i915_drpc_info", i915_drpc_info, NULL, 0}, 1639277487Skib {"i915_emon_status", i915_emon_status, NULL, 0}, 1640277487Skib {"i915_ring_freq_table", i915_ring_freq_table, NULL, 0}, 1641277487Skib {"i915_gfxec", i915_gfxec, NULL, 0}, 1642277487Skib {"i915_fbc_status", i915_fbc_status, NULL, 0}, 1643277487Skib {"i915_sr_status", i915_sr_status, NULL, 0}, 1644235783Skib#if 0 1645277487Skib {"i915_opregion", i915_opregion, NULL, 0}, 1646235783Skib#endif 1647277487Skib {"i915_gem_framebuffer", i915_gem_framebuffer_info, NULL, 0}, 1648277487Skib {"i915_context_status", i915_context_status, NULL, 0}, 1649277487Skib {"i915_gen6_forcewake_count_info", i915_gen6_forcewake_count_info, 1650277487Skib NULL, 0}, 1651277487Skib {"i915_swizzle_info", i915_swizzle_info, NULL, 0}, 1652277487Skib {"i915_ppgtt_info", i915_ppgtt_info, NULL, 0}, 1653277487Skib {"i915_dpio", i915_dpio_info, NULL, 0}, 1654235783Skib}; 1655235783Skib 1656235783Skibstruct i915_info_sysctl_thunk { 1657235783Skib struct drm_device *dev; 1658235783Skib int idx; 1659235783Skib void *arg; 1660235783Skib}; 1661235783Skib 1662235783Skibstatic int 1663235783Skibi915_info_sysctl_handler(SYSCTL_HANDLER_ARGS) 1664235783Skib{ 1665235783Skib struct sbuf m; 1666235783Skib struct i915_info_sysctl_thunk *thunk; 1667235783Skib struct drm_device *dev; 1668235783Skib drm_i915_private_t *dev_priv; 1669277487Skib char *p; 1670235783Skib int error; 1671235783Skib 1672235783Skib thunk = arg1; 1673235783Skib dev = thunk->dev; 1674235783Skib dev_priv = dev->dev_private; 1675235783Skib if (dev_priv == NULL) 1676235783Skib return (EBUSY); 1677235783Skib error = sysctl_wire_old_buffer(req, 0); 1678235783Skib if (error != 0) 1679235783Skib return (error); 1680235783Skib sbuf_new_for_sysctl(&m, NULL, 128, req); 1681280183Sdumbbell error = -i915_info_sysctl_list[thunk->idx].ptr(dev, &m, 1682235783Skib thunk->arg); 1683235783Skib if (error == 0) 1684235783Skib error = sbuf_finish(&m); 1685235783Skib sbuf_delete(&m); 1686277487Skib if (error != 0 || req->newptr == NULL) 1687277487Skib return (error); 1688277487Skib if (req->newlen > 2048) 1689277487Skib return (E2BIG); 1690277487Skib p = malloc(req->newlen + 1, M_TEMP, M_WAITOK); 1691277487Skib error = SYSCTL_IN(req, p, req->newlen); 1692277487Skib if (error != 0) 1693277487Skib goto out; 1694277487Skib p[req->newlen] = '\0'; 1695277487Skib error = i915_info_sysctl_list[thunk->idx].ptr_w(dev, p, 1696277487Skib thunk->arg); 1697277487Skibout: 1698277487Skib free(p, M_TEMP); 1699235783Skib return (error); 1700235783Skib} 1701235783Skib 1702235783Skibextern int i915_intr_pf; 1703235783Skibextern long i915_gem_wired_pages_cnt; 1704235783Skib 1705235783Skibint 1706235783Skibi915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1707235783Skib struct sysctl_oid *top) 1708235783Skib{ 1709235783Skib struct sysctl_oid *oid, *info; 1710235783Skib struct i915_info_sysctl_thunk *thunks; 1711235783Skib int i, error; 1712235783Skib 1713280183Sdumbbell thunks = malloc(sizeof(*thunks) * ARRAY_SIZE(i915_info_sysctl_list), 1714235783Skib DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1715280183Sdumbbell for (i = 0; i < ARRAY_SIZE(i915_info_sysctl_list); i++) { 1716235783Skib thunks[i].dev = dev; 1717235783Skib thunks[i].idx = i; 1718235783Skib thunks[i].arg = i915_info_sysctl_list[i].data; 1719235783Skib } 1720235783Skib dev->sysctl_private = thunks; 1721235783Skib info = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "info", 1722235783Skib CTLFLAG_RW, NULL, NULL); 1723235783Skib if (info == NULL) 1724280183Sdumbbell return (-ENOMEM); 1725280183Sdumbbell for (i = 0; i < ARRAY_SIZE(i915_info_sysctl_list); i++) { 1726235783Skib oid = SYSCTL_ADD_OID(ctx, SYSCTL_CHILDREN(info), OID_AUTO, 1727277487Skib i915_info_sysctl_list[i].name, CTLTYPE_STRING | 1728277487Skib (i915_info_sysctl_list[i].ptr_w != NULL ? CTLFLAG_RW : 1729277487Skib CTLFLAG_RD), 1730235783Skib &thunks[i], 0, i915_info_sysctl_handler, "A", NULL); 1731235783Skib if (oid == NULL) 1732280183Sdumbbell return (-ENOMEM); 1733235783Skib } 1734235783Skib oid = SYSCTL_ADD_LONG(ctx, SYSCTL_CHILDREN(info), OID_AUTO, 1735235783Skib "i915_gem_wired_pages", CTLFLAG_RD, &i915_gem_wired_pages_cnt, 1736235783Skib NULL); 1737235783Skib oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "wedged", 1738235783Skib CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0, 1739296548Sdumbbell i915_wedged, "I", NULL); 1740235783Skib if (oid == NULL) 1741280183Sdumbbell return (-ENOMEM); 1742235783Skib oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "max_freq", 1743235783Skib CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0, i915_max_freq, 1744235783Skib "I", NULL); 1745235783Skib if (oid == NULL) 1746280183Sdumbbell return (-ENOMEM); 1747296548Sdumbbell oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "min_freq", 1748296548Sdumbbell CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0, i915_min_freq, 1749296548Sdumbbell "I", NULL); 1750296548Sdumbbell if (oid == NULL) 1751296548Sdumbbell return (-ENOMEM); 1752235783Skib oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, 1753235783Skib "cache_sharing", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 1754235783Skib 0, i915_cache_sharing, "I", NULL); 1755235783Skib if (oid == NULL) 1756280183Sdumbbell return (-ENOMEM); 1757277487Skib oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, 1758296548Sdumbbell "ring_stop", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 1759296548Sdumbbell 0, i915_ring_stop, "I", NULL); 1760277487Skib if (oid == NULL) 1761280183Sdumbbell return (-ENOMEM); 1762235783Skib oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "intr_pf", 1763235783Skib CTLFLAG_RW, &i915_intr_pf, 0, NULL); 1764235783Skib if (oid == NULL) 1765280183Sdumbbell return (-ENOMEM); 1766235783Skib 1767235783Skib error = drm_add_busid_modesetting(dev, ctx, top); 1768235783Skib if (error != 0) 1769235783Skib return (error); 1770235783Skib 1771235783Skib return (0); 1772235783Skib} 1773235783Skib 1774235783Skibvoid 1775235783Skibi915_sysctl_cleanup(struct drm_device *dev) 1776235783Skib{ 1777235783Skib 1778235783Skib free(dev->sysctl_private, DRM_MEM_DRIVER); 1779235783Skib} 1780296548Sdumbbell 1781296548Sdumbbell//#endif /* CONFIG_DEBUG_FS */ 1782