t4_ioctl.h revision 309569
1139749Simp/*- 2138755Simp * Copyright (c) 2011 Chelsio Communications, Inc. 3138755Simp * All rights reserved. 4138755Simp * Written by: Navdeep Parhar <np@FreeBSD.org> 5138755Simp * 6138755Simp * Redistribution and use in source and binary forms, with or without 7138755Simp * modification, are permitted provided that the following conditions 8138755Simp * are met: 9140040Simp * 1. Redistributions of source code must retain the above copyright 10138755Simp * notice, this list of conditions and the following disclaimer. 11140040Simp * 2. Redistributions in binary form must reproduce the above copyright 12140040Simp * notice, this list of conditions and the following disclaimer in the 13138755Simp * documentation and/or other materials provided with the distribution. 14138755Simp * 15138755Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16138755Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17140040Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18140040Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19138755Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20138755Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21138755Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22138755Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23138755Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24138755Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25138755Simp * SUCH DAMAGE. 26138755Simp * 27138755Simp * $FreeBSD: stable/11/sys/dev/cxgbe/t4_ioctl.h 309569 2016-12-05 23:02:26Z jhb $ 28138755Simp * 29140040Simp */ 30138755Simp 31138755Simp#ifndef __T4_IOCTL_H__ 32138755Simp#define __T4_IOCTL_H__ 33138755Simp 34138755Simp#include <sys/types.h> 35138755Simp#include <net/ethernet.h> 36138755Simp 37138755Simp/* 38138755Simp * Ioctl commands specific to this driver. 39138755Simp */ 40138755Simpenum { 41138755Simp T4_GETREG = 0x40, /* read register */ 42138755Simp T4_SETREG, /* write register */ 43138755Simp T4_REGDUMP, /* dump of all registers */ 44138755Simp T4_GET_FILTER_MODE, /* get global filter mode */ 45138755Simp T4_SET_FILTER_MODE, /* set global filter mode */ 46138755Simp T4_GET_FILTER, /* get information about a filter */ 47138755Simp T4_SET_FILTER, /* program a filter */ 48138755Simp T4_DEL_FILTER, /* delete a filter */ 49138755Simp T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 50138755Simp T4_LOAD_FW, /* flash firmware */ 51138755Simp T4_GET_MEM, /* read memory */ 52138755Simp T4_GET_I2C, /* read from i2c addressible device */ 53138755Simp T4_CLEAR_STATS, /* clear a port's MAC statistics */ 54138755Simp T4_SET_OFLD_POLICY, /* Set offload policy */ 55138755Simp T4_SET_SCHED_CLASS, /* set sched class */ 56138755Simp T4_SET_SCHED_QUEUE, /* set queue class */ 57138755Simp T4_GET_TRACER, /* get information about a tracer */ 58138755Simp T4_SET_TRACER, /* program a tracer */ 59138755Simp T4_LOAD_CFG, /* copy a config file to card's flash */ 60138755Simp}; 61138755Simp 62138755Simpstruct t4_reg { 63138755Simp uint32_t addr; 64138755Simp uint32_t size; 65138755Simp uint64_t val; 66138755Simp}; 67138755Simp 68138755Simp#define T4_REGDUMP_SIZE (160 * 1024) 69138755Simp#define T5_REGDUMP_SIZE (332 * 1024) 70138755Simpstruct t4_regdump { 71138755Simp uint32_t version; 72138755Simp uint32_t len; /* bytes */ 73138755Simp uint32_t *data; 74138755Simp}; 75138755Simp 76138755Simpstruct t4_data { 77138755Simp uint32_t len; 78138755Simp uint8_t *data; 79138755Simp}; 80138755Simp 81138755Simpstruct t4_i2c_data { 82138755Simp uint8_t port_id; 83138755Simp uint8_t dev_addr; 84138755Simp uint8_t offset; 85138755Simp uint8_t len; 86138755Simp uint8_t data[8]; 87138755Simp}; 88138755Simp 89138755Simp/* 90138755Simp * A hardware filter is some valid combination of these. 91138755Simp */ 92144783Simp#define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 93144783Simp#define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 94138755Simp#define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 95138755Simp#define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 96144783Simp#define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 97144783Simp#define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 98272956Sjhb#define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 99138755Simp#define T4_FILTER_PORT 0x80 /* Physical ingress port */ 100138755Simp#define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 101138755Simp#define T4_FILTER_VLAN 0x200 /* VLAN ID */ 102138755Simp#define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 103138755Simp#define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 104138755Simp#define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 105138755Simp#define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 106138755Simp#define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 107138755Simp#define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 108138755Simp 109138755Simp#define T4_FILTER_IC_VNIC 0x80000000 /* TP Ingress Config's F_VNIC 110138755Simp bit. It indicates whether 111138755Simp T4_FILTER_VNIC bit means VNIC 112138755Simp id (PF/VF) or outer VLAN. 113138755Simp 0 = oVLAN, 1 = VNIC */ 114138755Simp 115138755Simp/* Filter action */ 116138755Simpenum { 117138755Simp FILTER_PASS = 0, /* default */ 118138755Simp FILTER_DROP, 119138755Simp FILTER_SWITCH 120138755Simp}; 121138755Simp 122138755Simp/* 802.1q manipulation on FILTER_SWITCH */ 123138755Simpenum { 124138755Simp VLAN_NOCHANGE = 0, /* default */ 125138755Simp VLAN_REMOVE, 126138755Simp VLAN_INSERT, 127138755Simp VLAN_REWRITE 128138755Simp}; 129138755Simp 130138755Simp/* MPS match type */ 131138755Simpenum { 132138755Simp UCAST_EXACT = 0, /* exact unicast match */ 133138755Simp UCAST_HASH = 1, /* inexact (hashed) unicast match */ 134138755Simp MCAST_EXACT = 2, /* exact multicast match */ 135138755Simp MCAST_HASH = 3, /* inexact (hashed) multicast match */ 136138755Simp PROMISC = 4, /* no match but port is promiscuous */ 137138755Simp HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 138138755Simp BCAST = 6, /* broadcast packet */ 139138755Simp}; 140138755Simp 141138755Simp/* Rx steering */ 142138755Simpenum { 143138755Simp DST_MODE_QUEUE, /* queue is directly specified by filter */ 144138755Simp DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 145138755Simp DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 146138755Simp DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 147138755Simp RSS subtable */ 148138755Simp}; 149138755Simp 150138755Simpstruct t4_filter_tuple { 151138755Simp /* 152138755Simp * These are always available. 153138755Simp */ 154138755Simp uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 155138755Simp uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 156138755Simp uint16_t sport; /* source port */ 157138755Simp uint16_t dport; /* destination port */ 158272956Sjhb 159272956Sjhb /* 160272956Sjhb * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP 161272956Sjhb * is used to select the global mode and all filters are limited to the 162138755Simp * set of fields allowed by the global mode. 163138755Simp */ 164138755Simp uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */ 165138755Simp uint16_t vlan; /* VLAN tag */ 166138755Simp uint16_t ethtype; /* Ethernet type */ 167138755Simp uint8_t tos; /* TOS/Traffic Type */ 168138755Simp uint8_t proto; /* protocol type */ 169138755Simp uint32_t fcoe:1; /* FCoE packet */ 170138755Simp uint32_t iport:3; /* ingress port */ 171138755Simp uint32_t matchtype:3; /* MPS match type */ 172138755Simp uint32_t frag:1; /* fragmentation extension header */ 173138755Simp uint32_t macidx:9; /* exact match MAC index */ 174138755Simp uint32_t vlan_vld:1; /* VLAN valid */ 175272956Sjhb uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */ 176272956Sjhb uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */ 177272956Sjhb}; 178272956Sjhb 179138755Simpstruct t4_filter_specification { 180138755Simp uint32_t hitcnts:1; /* count filter hits in TCB */ 181138755Simp uint32_t prio:1; /* filter has priority over active/server */ 182138755Simp uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 183138755Simp uint32_t action:2; /* drop, pass, switch */ 184138755Simp uint32_t rpttid:1; /* report TID in RSS hash field */ 185138755Simp uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 186138755Simp uint32_t iq:10; /* ingress queue */ 187138755Simp uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 188138755Simp uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 189138755Simp /* 1 => TCB contains IQ ID */ 190138755Simp 191138755Simp /* 192138755Simp * Switch proxy/rewrite fields. An ingress packet which matches a 193138755Simp * filter with "switch" set will be looped back out as an egress 194138755Simp * packet -- potentially with some Ethernet header rewriting. 195144783Simp */ 196138755Simp uint32_t eport:2; /* egress port to switch packet out */ 197138755Simp uint32_t newdmac:1; /* rewrite destination MAC address */ 198138755Simp uint32_t newsmac:1; /* rewrite source MAC address */ 199138755Simp uint32_t newvlan:2; /* rewrite VLAN Tag */ 200138755Simp uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 201138755Simp uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 202138755Simp uint16_t vlan; /* VLAN Tag to insert */ 203138755Simp 204138755Simp /* 205138755Simp * Filter rule value/mask pairs. 206138755Simp */ 207138755Simp struct t4_filter_tuple val; 208138755Simp struct t4_filter_tuple mask; 209296137Sjhibbits}; 210296137Sjhibbits 211138755Simpstruct t4_filter { 212138755Simp uint32_t idx; 213138755Simp uint16_t l2tidx; 214138755Simp uint16_t smtidx; 215138755Simp uint64_t hits; 216138755Simp struct t4_filter_specification fs; 217138755Simp}; 218138755Simp 219138755Simp/* Tx Scheduling Class parameters */ 220138755Simpstruct t4_sched_class_params { 221138755Simp int8_t level; /* scheduler hierarchy level */ 222138755Simp int8_t mode; /* per-class or per-flow */ 223138755Simp int8_t rateunit; /* bit or packet rate */ 224138755Simp int8_t ratemode; /* %port relative or kbps absolute */ 225138755Simp int8_t channel; /* scheduler channel [0..N] */ 226138755Simp int8_t cl; /* scheduler class [0..N] */ 227138755Simp int32_t minrate; /* minimum rate */ 228138755Simp int32_t maxrate; /* maximum rate */ 229138755Simp int16_t weight; /* percent weight */ 230138755Simp int16_t pktsize; /* average packet size */ 231138755Simp}; 232138755Simp 233138755Simp/* 234138755Simp * Support for "sched-class" command to allow a TX Scheduling Class to be 235138755Simp * programmed with various parameters. 236138755Simp */ 237138755Simpstruct t4_sched_params { 238144783Simp int8_t subcmd; /* sub-command */ 239138755Simp int8_t type; /* packet or flow */ 240138755Simp union { 241138755Simp struct { /* sub-command SCHED_CLASS_CONFIG */ 242138755Simp int8_t minmax; /* minmax enable */ 243138755Simp } config; 244138755Simp struct t4_sched_class_params params; 245138755Simp uint8_t reserved[6 + 8 * 8]; 246296137Sjhibbits } u; 247296137Sjhibbits}; 248138755Simp 249138755Simpenum { 250138755Simp SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */ 251138755Simp SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */ 252138755Simp}; 253138755Simp 254138755Simpenum { 255138755Simp SCHED_CLASS_TYPE_PACKET, 256138755Simp}; 257138755Simp 258138755Simpenum { 259138755Simp SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */ 260138755Simp SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */ 261138755Simp SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */ 262138755Simp}; 263144783Simp 264138755Simpenum { 265138755Simp SCHED_CLASS_MODE_CLASS, /* per-class scheduling */ 266138755Simp SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 267138755Simp}; 268272956Sjhb 269138755Simpenum { 270272956Sjhb SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */ 271138755Simp SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */ 272138755Simp}; 273272956Sjhb 274138755Simpenum { 275272956Sjhb SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */ 276138755Simp SCHED_CLASS_RATEMODE_ABS, /* Kb/s */ 277138755Simp}; 278138755Simp 279138755Simp/* 280138755Simp * Support for "sched_queue" command to allow one or more NIC TX Queues to be 281138755Simp * bound to a TX Scheduling Class. 282138755Simp */ 283138755Simpstruct t4_sched_queue { 284138755Simp uint8_t port; 285138755Simp int8_t queue; /* queue index; -1 => all queues */ 286138755Simp int8_t cl; /* class index; -1 => unbind */ 287138755Simp}; 288272956Sjhb 289138755Simp#define T4_SGE_CONTEXT_SIZE 24 290138755Simpenum { 291138755Simp SGE_CONTEXT_EGRESS, 292272956Sjhb SGE_CONTEXT_INGRESS, 293272956Sjhb SGE_CONTEXT_FLM, 294138755Simp SGE_CONTEXT_CNM 295138755Simp}; 296138755Simp 297138755Simpstruct t4_sge_context { 298138755Simp uint32_t mem_id; 299138755Simp uint32_t cid; 300272956Sjhb uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 301138755Simp}; 302138755Simp 303272956Sjhbstruct t4_mem_range { 304138755Simp uint32_t addr; 305138755Simp uint32_t len; 306138755Simp uint32_t *data; 307138755Simp}; 308138755Simp 309138755Simp#define T4_TRACE_LEN 112 310272956Sjhbstruct t4_trace_params { 311138755Simp uint32_t data[T4_TRACE_LEN / 4]; 312138755Simp uint32_t mask[T4_TRACE_LEN / 4]; 313138755Simp uint16_t snap_len; 314272956Sjhb uint16_t min_len; 315272956Sjhb uint8_t skip_ofst; 316138755Simp uint8_t skip_len; 317138755Simp uint8_t invert; 318272956Sjhb uint8_t port; 319272956Sjhb}; 320272956Sjhb 321272956Sjhbstruct t4_tracer { 322272956Sjhb uint8_t idx; 323272956Sjhb uint8_t enabled; 324138755Simp uint8_t valid; 325138755Simp struct t4_trace_params tp; 326272956Sjhb}; 327138755Simp 328138755Simp#define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 329138755Simp#define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 330138755Simp#define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 331138755Simp#define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 332138755Simp#define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 333138755Simp#define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 334138755Simp#define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 335138755Simp#define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 336138755Simp#define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 337144783Simp struct t4_sge_context) 338138755Simp#define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 339138755Simp#define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 340138755Simp#define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 341138755Simp#define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 342272956Sjhb#define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \ 343138755Simp struct t4_sched_params) 344138755Simp#define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \ 345138755Simp struct t4_sched_queue) 346138755Simp#define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 347138755Simp#define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 348138755Simp#define CHELSIO_T4_LOAD_CFG _IOW('f', T4_LOAD_CFG, struct t4_data) 349138755Simp#endif 350138755Simp