iw_cxgbe.h revision 331722 
1/*
2 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *	  copyright notice, this list of conditions and the following
16 *	  disclaimer.
17 *      - Redistributions in binary form must reproduce the above
18 *	  copyright notice, this list of conditions and the following
19 *	  disclaimer in the documentation and/or other materials
20 *	  provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 *
31 * $FreeBSD: stable/11/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h 331722 2018-03-29 02:50:57Z eadler $
32 */
33#ifndef __IW_CXGB4_H__
34#define __IW_CXGB4_H__
35
36#include <linux/list.h>
37#include <linux/spinlock.h>
38#include <linux/idr.h>
39#include <linux/completion.h>
40#include <linux/netdevice.h>
41#include <linux/sched.h>
42#include <linux/pci.h>
43#include <linux/dma-mapping.h>
44#include <linux/wait.h>
45#include <linux/kref.h>
46#include <linux/timer.h>
47#include <linux/io.h>
48#include <sys/vmem.h>
49
50#include <asm/byteorder.h>
51
52#include <netinet/in.h>
53#include <netinet/toecore.h>
54
55#include <rdma/ib_verbs.h>
56#include <rdma/iw_cm.h>
57
58#undef prefetch
59
60#include "common/common.h"
61#include "common/t4_msg.h"
62#include "common/t4_regs.h"
63#include "common/t4_tcb.h"
64#include "t4_l2t.h"
65
66#define DRV_NAME "iw_cxgbe"
67#define MOD DRV_NAME ":"
68#define KTR_IW_CXGBE	KTR_SPARE3
69
70extern int c4iw_debug;
71#define PDBG(fmt, args...) \
72do { \
73	if (c4iw_debug) \
74		printf(MOD fmt, ## args); \
75} while (0)
76
77#include "t4.h"
78
79static inline void *cplhdr(struct mbuf *m)
80{
81	return mtod(m, void*);
82}
83
84#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
85#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
86
87#define C4IW_ID_TABLE_F_RANDOM 1       /* Pseudo-randomize the id's returned */
88#define C4IW_ID_TABLE_F_EMPTY  2       /* Table is initially empty */
89
90struct c4iw_id_table {
91	u32 flags;
92	u32 start;              /* logical minimal id */
93	u32 last;               /* hint for find */
94	u32 max;
95	spinlock_t lock;
96	unsigned long *table;
97};
98
99struct c4iw_resource {
100	struct c4iw_id_table tpt_table;
101	struct c4iw_id_table qid_table;
102	struct c4iw_id_table pdid_table;
103};
104
105struct c4iw_qid_list {
106	struct list_head entry;
107	u32 qid;
108};
109
110struct c4iw_dev_ucontext {
111	struct list_head qpids;
112	struct list_head cqids;
113	struct mutex lock;
114};
115
116enum c4iw_rdev_flags {
117	T4_FATAL_ERROR = (1<<0),
118};
119
120struct c4iw_stat {
121	u64 total;
122	u64 cur;
123	u64 max;
124	u64 fail;
125};
126
127struct c4iw_stats {
128	struct mutex lock;
129	struct c4iw_stat qid;
130	struct c4iw_stat pd;
131	struct c4iw_stat stag;
132	struct c4iw_stat pbl;
133	struct c4iw_stat rqt;
134};
135
136struct c4iw_rdev {
137	struct adapter *adap;
138	struct c4iw_resource resource;
139	unsigned long qpshift;
140	u32 qpmask;
141	unsigned long cqshift;
142	u32 cqmask;
143	struct c4iw_dev_ucontext uctx;
144	vmem_t          *rqt_arena;
145	vmem_t          *pbl_arena;
146	u32 flags;
147	struct c4iw_stats stats;
148};
149
150static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
151{
152	return rdev->flags & T4_FATAL_ERROR;
153}
154
155static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
156{
157	return (int)(rdev->adap->vres.stag.size >> 5);
158}
159
160#define C4IW_WR_TO (60*HZ)
161
162struct c4iw_wr_wait {
163	int ret;
164	struct completion completion;
165};
166
167static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
168{
169	wr_waitp->ret = 0;
170	init_completion(&wr_waitp->completion);
171}
172
173static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
174{
175	wr_waitp->ret = ret;
176	complete(&wr_waitp->completion);
177}
178
179static inline int
180c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
181					u32 hwtid, u32 qpid, const char *func)
182{
183	struct adapter *sc = rdev->adap;
184	unsigned to = C4IW_WR_TO;
185	int ret;
186	int timedout = 0;
187	struct timeval t1, t2;
188
189	if (c4iw_fatal_error(rdev)) {
190		wr_waitp->ret = -EIO;
191		goto out;
192	}
193
194	getmicrotime(&t1);
195	do {
196		ret = wait_for_completion_timeout(&wr_waitp->completion, to);
197		if (!ret) {
198			getmicrotime(&t2);
199			timevalsub(&t2, &t1);
200			printf("%s - Device %s not responding after %ld.%06ld "
201			    "seconds - tid %u qpid %u\n", func,
202			    device_get_nameunit(sc->dev), t2.tv_sec, t2.tv_usec,
203			    hwtid, qpid);
204			if (c4iw_fatal_error(rdev)) {
205				wr_waitp->ret = -EIO;
206				break;
207			}
208			to = to << 2;
209			timedout = 1;
210		}
211	} while (!ret);
212
213out:
214	if (timedout) {
215		getmicrotime(&t2);
216		timevalsub(&t2, &t1);
217		printf("%s - Device %s reply after %ld.%06ld seconds - "
218		    "tid %u qpid %u\n", func, device_get_nameunit(sc->dev),
219		    t2.tv_sec, t2.tv_usec, hwtid, qpid);
220	}
221	if (wr_waitp->ret)
222		CTR4(KTR_IW_CXGBE, "%p: FW reply %d tid %u qpid %u", sc,
223		    wr_waitp->ret, hwtid, qpid);
224	return (wr_waitp->ret);
225}
226
227struct c4iw_dev {
228	struct ib_device ibdev;
229	struct c4iw_rdev rdev;
230	u32 device_cap_flags;
231	struct idr cqidr;
232	struct idr qpidr;
233	struct idr mmidr;
234	spinlock_t lock;
235	struct dentry *debugfs_root;
236};
237
238static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
239{
240	return container_of(ibdev, struct c4iw_dev, ibdev);
241}
242
243static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
244{
245	return container_of(rdev, struct c4iw_dev, rdev);
246}
247
248static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
249{
250	return idr_find(&rhp->cqidr, cqid);
251}
252
253static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
254{
255	return idr_find(&rhp->qpidr, qpid);
256}
257
258static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
259{
260	return idr_find(&rhp->mmidr, mmid);
261}
262
263static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
264				 void *handle, u32 id, int lock)
265{
266	int ret;
267	int newid;
268
269	do {
270		if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
271			return -ENOMEM;
272		if (lock)
273			spin_lock_irq(&rhp->lock);
274		ret = idr_get_new_above(idr, handle, id, &newid);
275		BUG_ON(!ret && newid != id);
276		if (lock)
277			spin_unlock_irq(&rhp->lock);
278	} while (ret == -EAGAIN);
279
280	return ret;
281}
282
283static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
284				void *handle, u32 id)
285{
286	return _insert_handle(rhp, idr, handle, id, 1);
287}
288
289static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
290				       void *handle, u32 id)
291{
292	return _insert_handle(rhp, idr, handle, id, 0);
293}
294
295static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
296				   u32 id, int lock)
297{
298	if (lock)
299		spin_lock_irq(&rhp->lock);
300	idr_remove(idr, id);
301	if (lock)
302		spin_unlock_irq(&rhp->lock);
303}
304
305static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
306{
307	_remove_handle(rhp, idr, id, 1);
308}
309
310static inline void remove_handle_nolock(struct c4iw_dev *rhp,
311					 struct idr *idr, u32 id)
312{
313	_remove_handle(rhp, idr, id, 0);
314}
315
316struct c4iw_pd {
317	struct ib_pd ibpd;
318	u32 pdid;
319	struct c4iw_dev *rhp;
320};
321
322static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
323{
324	return container_of(ibpd, struct c4iw_pd, ibpd);
325}
326
327struct tpt_attributes {
328	u64 len;
329	u64 va_fbo;
330	enum fw_ri_mem_perms perms;
331	u32 stag;
332	u32 pdid;
333	u32 qpid;
334	u32 pbl_addr;
335	u32 pbl_size;
336	u32 state:1;
337	u32 type:2;
338	u32 rsvd:1;
339	u32 remote_invaliate_disable:1;
340	u32 zbva:1;
341	u32 mw_bind_enable:1;
342	u32 page_size:5;
343};
344
345struct c4iw_mr {
346	struct ib_mr ibmr;
347	struct ib_umem *umem;
348	struct c4iw_dev *rhp;
349	u64 kva;
350	struct tpt_attributes attr;
351};
352
353static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
354{
355	return container_of(ibmr, struct c4iw_mr, ibmr);
356}
357
358struct c4iw_mw {
359	struct ib_mw ibmw;
360	struct c4iw_dev *rhp;
361	u64 kva;
362	struct tpt_attributes attr;
363};
364
365static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
366{
367	return container_of(ibmw, struct c4iw_mw, ibmw);
368}
369
370struct c4iw_fr_page_list {
371	struct ib_fast_reg_page_list ibpl;
372	DECLARE_PCI_UNMAP_ADDR(mapping);
373	dma_addr_t dma_addr;
374	struct c4iw_dev *dev;
375	int size;
376};
377
378static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
379					struct ib_fast_reg_page_list *ibpl)
380{
381	return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
382}
383
384struct c4iw_cq {
385	struct ib_cq ibcq;
386	struct c4iw_dev *rhp;
387	struct t4_cq cq;
388	spinlock_t lock;
389	spinlock_t comp_handler_lock;
390	atomic_t refcnt;
391	wait_queue_head_t wait;
392};
393
394static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
395{
396	return container_of(ibcq, struct c4iw_cq, ibcq);
397}
398
399struct c4iw_mpa_attributes {
400	u8 initiator;
401	u8 recv_marker_enabled;
402	u8 xmit_marker_enabled;
403	u8 crc_enabled;
404	u8 enhanced_rdma_conn;
405	u8 version;
406	u8 p2p_type;
407};
408
409struct c4iw_qp_attributes {
410	u32 scq;
411	u32 rcq;
412	u32 sq_num_entries;
413	u32 rq_num_entries;
414	u32 sq_max_sges;
415	u32 sq_max_sges_rdma_write;
416	u32 rq_max_sges;
417	u32 state;
418	u8 enable_rdma_read;
419	u8 enable_rdma_write;
420	u8 enable_bind;
421	u8 enable_mmid0_fastreg;
422	u32 max_ord;
423	u32 max_ird;
424	u32 pd;
425	u32 next_state;
426	char terminate_buffer[52];
427	u32 terminate_msg_len;
428	u8 is_terminate_local;
429	struct c4iw_mpa_attributes mpa_attr;
430	struct c4iw_ep *llp_stream_handle;
431	u8 layer_etype;
432	u8 ecode;
433	u16 sq_db_inc;
434	u16 rq_db_inc;
435};
436
437struct c4iw_qp {
438	struct ib_qp ibqp;
439	struct c4iw_dev *rhp;
440	struct c4iw_ep *ep;
441	struct c4iw_qp_attributes attr;
442	struct t4_wq wq;
443	spinlock_t lock;
444	struct mutex mutex;
445	atomic_t refcnt;
446	wait_queue_head_t wait;
447	struct timer_list timer;
448	int sq_sig_all;
449};
450
451static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
452{
453	return container_of(ibqp, struct c4iw_qp, ibqp);
454}
455
456struct c4iw_ucontext {
457	struct ib_ucontext ibucontext;
458	struct c4iw_dev_ucontext uctx;
459	u32 key;
460	spinlock_t mmap_lock;
461	struct list_head mmaps;
462};
463
464static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
465{
466	return container_of(c, struct c4iw_ucontext, ibucontext);
467}
468
469struct c4iw_mm_entry {
470	struct list_head entry;
471	u64 addr;
472	u32 key;
473	unsigned len;
474};
475
476static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
477						u32 key, unsigned len)
478{
479	struct list_head *pos, *nxt;
480	struct c4iw_mm_entry *mm;
481
482	spin_lock(&ucontext->mmap_lock);
483	list_for_each_safe(pos, nxt, &ucontext->mmaps) {
484
485		mm = list_entry(pos, struct c4iw_mm_entry, entry);
486		if (mm->key == key && mm->len == len) {
487			list_del_init(&mm->entry);
488			spin_unlock(&ucontext->mmap_lock);
489			CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
490			     __func__, key, (unsigned long long) mm->addr,
491			     mm->len);
492			return mm;
493		}
494	}
495	spin_unlock(&ucontext->mmap_lock);
496	return NULL;
497}
498
499static inline void insert_mmap(struct c4iw_ucontext *ucontext,
500			       struct c4iw_mm_entry *mm)
501{
502	spin_lock(&ucontext->mmap_lock);
503	CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
504	    (unsigned long long) mm->addr, mm->len);
505	list_add_tail(&mm->entry, &ucontext->mmaps);
506	spin_unlock(&ucontext->mmap_lock);
507}
508
509enum c4iw_qp_attr_mask {
510	C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
511	C4IW_QP_ATTR_SQ_DB = 1<<1,
512	C4IW_QP_ATTR_RQ_DB = 1<<2,
513	C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
514	C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
515	C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
516	C4IW_QP_ATTR_MAX_ORD = 1 << 11,
517	C4IW_QP_ATTR_MAX_IRD = 1 << 12,
518	C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
519	C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
520	C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
521	C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
522	C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
523				     C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
524				     C4IW_QP_ATTR_MAX_ORD |
525				     C4IW_QP_ATTR_MAX_IRD |
526				     C4IW_QP_ATTR_LLP_STREAM_HANDLE |
527				     C4IW_QP_ATTR_STREAM_MSG_BUFFER |
528				     C4IW_QP_ATTR_MPA_ATTR |
529				     C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
530};
531
532int c4iw_modify_qp(struct c4iw_dev *rhp,
533				struct c4iw_qp *qhp,
534				enum c4iw_qp_attr_mask mask,
535				struct c4iw_qp_attributes *attrs,
536				int internal);
537
538enum c4iw_qp_state {
539	C4IW_QP_STATE_IDLE,
540	C4IW_QP_STATE_RTS,
541	C4IW_QP_STATE_ERROR,
542	C4IW_QP_STATE_TERMINATE,
543	C4IW_QP_STATE_CLOSING,
544	C4IW_QP_STATE_TOT
545};
546
547/*
548 * IW_CXGBE event bits.
549 * These bits are used for handling all events for a particular 'ep' serially.
550 */
551#define	C4IW_EVENT_SOCKET	0x0001
552#define	C4IW_EVENT_TIMEOUT	0x0002
553#define	C4IW_EVENT_TERM		0x0004
554
555static inline int c4iw_convert_state(enum ib_qp_state ib_state)
556{
557	switch (ib_state) {
558	case IB_QPS_RESET:
559	case IB_QPS_INIT:
560		return C4IW_QP_STATE_IDLE;
561	case IB_QPS_RTS:
562		return C4IW_QP_STATE_RTS;
563	case IB_QPS_SQD:
564		return C4IW_QP_STATE_CLOSING;
565	case IB_QPS_SQE:
566		return C4IW_QP_STATE_TERMINATE;
567	case IB_QPS_ERR:
568		return C4IW_QP_STATE_ERROR;
569	default:
570		return -1;
571	}
572}
573
574static inline int to_ib_qp_state(int c4iw_qp_state)
575{
576	switch (c4iw_qp_state) {
577	case C4IW_QP_STATE_IDLE:
578		return IB_QPS_INIT;
579	case C4IW_QP_STATE_RTS:
580		return IB_QPS_RTS;
581	case C4IW_QP_STATE_CLOSING:
582		return IB_QPS_SQD;
583	case C4IW_QP_STATE_TERMINATE:
584		return IB_QPS_SQE;
585	case C4IW_QP_STATE_ERROR:
586		return IB_QPS_ERR;
587	}
588	return IB_QPS_ERR;
589}
590
591#define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
592
593static inline u32 c4iw_ib_to_tpt_access(int a)
594{
595	return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
596	       (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
597	       (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
598	       FW_RI_MEM_ACCESS_LOCAL_READ;
599}
600
601static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
602{
603	return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
604	       (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
605}
606
607enum c4iw_mmid_state {
608	C4IW_STAG_STATE_VALID,
609	C4IW_STAG_STATE_INVALID
610};
611
612#define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
613
614#define MPA_KEY_REQ "MPA ID Req Frame"
615#define MPA_KEY_REP "MPA ID Rep Frame"
616
617#define MPA_MAX_PRIVATE_DATA	256
618#define MPA_ENHANCED_RDMA_CONN	0x10
619#define MPA_REJECT		0x20
620#define MPA_CRC			0x40
621#define MPA_MARKERS		0x80
622#define MPA_FLAGS_MASK		0xE0
623
624#define MPA_V2_PEER2PEER_MODEL          0x8000
625#define MPA_V2_ZERO_LEN_FPDU_RTR        0x4000
626#define MPA_V2_RDMA_WRITE_RTR           0x8000
627#define MPA_V2_RDMA_READ_RTR            0x4000
628#define MPA_V2_IRD_ORD_MASK             0x3FFF
629
630#define c4iw_put_ep(ep) { \
631	CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
632	     __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
633	WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \
634        kref_put(&((ep)->kref), _c4iw_free_ep); \
635}
636
637#define c4iw_get_ep(ep) { \
638	CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
639	      __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
640        kref_get(&((ep)->kref));  \
641}
642
643void _c4iw_free_ep(struct kref *kref);
644
645struct mpa_message {
646	u8 key[16];
647	u8 flags;
648	u8 revision;
649	__be16 private_data_size;
650	u8 private_data[0];
651};
652
653struct mpa_v2_conn_params {
654	__be16 ird;
655	__be16 ord;
656};
657
658struct terminate_message {
659	u8 layer_etype;
660	u8 ecode;
661	__be16 hdrct_rsvd;
662	u8 len_hdrs[0];
663};
664
665#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
666
667enum c4iw_layers_types {
668	LAYER_RDMAP		= 0x00,
669	LAYER_DDP		= 0x10,
670	LAYER_MPA		= 0x20,
671	RDMAP_LOCAL_CATA	= 0x00,
672	RDMAP_REMOTE_PROT	= 0x01,
673	RDMAP_REMOTE_OP		= 0x02,
674	DDP_LOCAL_CATA		= 0x00,
675	DDP_TAGGED_ERR		= 0x01,
676	DDP_UNTAGGED_ERR	= 0x02,
677	DDP_LLP			= 0x03
678};
679
680enum c4iw_rdma_ecodes {
681	RDMAP_INV_STAG		= 0x00,
682	RDMAP_BASE_BOUNDS	= 0x01,
683	RDMAP_ACC_VIOL		= 0x02,
684	RDMAP_STAG_NOT_ASSOC	= 0x03,
685	RDMAP_TO_WRAP		= 0x04,
686	RDMAP_INV_VERS		= 0x05,
687	RDMAP_INV_OPCODE	= 0x06,
688	RDMAP_STREAM_CATA	= 0x07,
689	RDMAP_GLOBAL_CATA	= 0x08,
690	RDMAP_CANT_INV_STAG	= 0x09,
691	RDMAP_UNSPECIFIED	= 0xff
692};
693
694enum c4iw_ddp_ecodes {
695	DDPT_INV_STAG		= 0x00,
696	DDPT_BASE_BOUNDS	= 0x01,
697	DDPT_STAG_NOT_ASSOC	= 0x02,
698	DDPT_TO_WRAP		= 0x03,
699	DDPT_INV_VERS		= 0x04,
700	DDPU_INV_QN		= 0x01,
701	DDPU_INV_MSN_NOBUF	= 0x02,
702	DDPU_INV_MSN_RANGE	= 0x03,
703	DDPU_INV_MO		= 0x04,
704	DDPU_MSG_TOOBIG		= 0x05,
705	DDPU_INV_VERS		= 0x06
706};
707
708enum c4iw_mpa_ecodes {
709	MPA_CRC_ERR		= 0x02,
710	MPA_MARKER_ERR		= 0x03,
711	MPA_LOCAL_CATA          = 0x05,
712	MPA_INSUFF_IRD          = 0x06,
713	MPA_NOMATCH_RTR         = 0x07,
714};
715
716enum c4iw_ep_state {
717	IDLE = 0,
718	LISTEN,
719	CONNECTING,
720	MPA_REQ_WAIT,
721	MPA_REQ_SENT,
722	MPA_REQ_RCVD,
723	MPA_REP_SENT,
724	FPDU_MODE,
725	ABORTING,
726	CLOSING,
727	MORIBUND,
728	DEAD,
729};
730
731enum c4iw_ep_flags {
732	PEER_ABORT_IN_PROGRESS	= 0,
733	ABORT_REQ_IN_PROGRESS	= 1,
734	RELEASE_RESOURCES	= 2,
735	CLOSE_SENT		= 3,
736	TIMEOUT                 = 4,
737	QP_REFERENCED		= 5
738};
739
740enum c4iw_ep_history {
741        ACT_OPEN_REQ            = 0,
742        ACT_OFLD_CONN           = 1,
743        ACT_OPEN_RPL            = 2,
744        ACT_ESTAB               = 3,
745        PASS_ACCEPT_REQ         = 4,
746        PASS_ESTAB              = 5,
747        ABORT_UPCALL            = 6,
748        ESTAB_UPCALL            = 7,
749        CLOSE_UPCALL            = 8,
750        ULP_ACCEPT              = 9,
751        ULP_REJECT              = 10,
752        TIMEDOUT                = 11,
753        PEER_ABORT              = 12,
754        PEER_CLOSE              = 13,
755        CONNREQ_UPCALL          = 14,
756        ABORT_CONN              = 15,
757        DISCONN_UPCALL          = 16,
758        EP_DISC_CLOSE           = 17,
759        EP_DISC_ABORT           = 18,
760        CONN_RPL_UPCALL         = 19,
761        ACT_RETRY_NOMEM         = 20,
762        ACT_RETRY_INUSE         = 21,
763        CLOSE_CON_RPL           = 22,
764        EP_DISC_FAIL            = 24,
765        QP_REFED                = 25,
766        QP_DEREFED              = 26,
767        CM_ID_REFED             = 27,
768        CM_ID_DEREFED           = 28
769};
770
771struct c4iw_ep_common {
772	TAILQ_ENTRY(c4iw_ep_common) entry;	/* Work queue attachment */
773	struct iw_cm_id *cm_id;
774	struct c4iw_qp *qp;
775	struct c4iw_dev *dev;
776	enum c4iw_ep_state state;
777	struct kref kref;
778	struct mutex mutex;
779	struct sockaddr_in local_addr;
780	struct sockaddr_in remote_addr;
781	struct c4iw_wr_wait wr_wait;
782	unsigned long flags;
783	unsigned long history;
784        int rpl_err;
785        int rpl_done;
786        struct thread *thread;
787        struct socket *so;
788	int ep_events;
789};
790
791struct c4iw_listen_ep {
792	struct c4iw_ep_common com;
793	unsigned int stid;
794	int backlog;
795};
796
797struct c4iw_ep {
798	struct c4iw_ep_common com;
799	struct c4iw_ep *parent_ep;
800	struct timer_list timer;
801	unsigned int atid;
802	u32 hwtid;
803	u32 snd_seq;
804	u32 rcv_seq;
805	struct l2t_entry *l2t;
806	struct dst_entry *dst;
807	struct c4iw_mpa_attributes mpa_attr;
808	u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
809	unsigned int mpa_pkt_len;
810	u32 ird;
811	u32 ord;
812	u32 smac_idx;
813	u32 tx_chan;
814	u32 mtu;
815	u16 mss;
816	u16 emss;
817	u16 plen;
818	u16 rss_qid;
819	u16 txq_idx;
820	u16 ctrlq_idx;
821	u8 tos;
822	u8 retry_with_mpa_v1;
823	u8 tried_with_mpa_v1;
824};
825
826static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
827{
828	return cm_id->provider_data;
829}
830
831static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
832{
833	return cm_id->provider_data;
834}
835
836static inline int compute_wscale(int win)
837{
838	int wscale = 0;
839
840	while (wscale < 14 && (65535<<wscale) < win)
841		wscale++;
842	return wscale;
843}
844
845u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
846void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
847int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
848			u32 reserved, u32 flags);
849void c4iw_id_table_free(struct c4iw_id_table *alloc);
850
851typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
852
853int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
854		     struct l2t_entry *l2t);
855u32 c4iw_get_resource(struct c4iw_id_table *id_table);
856void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
857int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
858int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
859int c4iw_pblpool_create(struct c4iw_rdev *rdev);
860int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
861void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
862void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
863void c4iw_destroy_resource(struct c4iw_resource *rscp);
864int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
865int c4iw_register_device(struct c4iw_dev *dev);
866void c4iw_unregister_device(struct c4iw_dev *dev);
867int __init c4iw_cm_init(void);
868void __exit c4iw_cm_term(void);
869void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
870			       struct c4iw_dev_ucontext *uctx);
871void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
872			    struct c4iw_dev_ucontext *uctx);
873int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
874int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
875		      struct ib_send_wr **bad_wr);
876int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
877		      struct ib_recv_wr **bad_wr);
878int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
879		 struct ib_mw_bind *mw_bind);
880int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
881int c4iw_create_listen_ep(struct iw_cm_id *cm_id, int backlog);
882void c4iw_destroy_listen_ep(struct iw_cm_id *cm_id);
883int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
884int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
885void c4iw_qp_add_ref(struct ib_qp *qp);
886void c4iw_qp_rem_ref(struct ib_qp *qp);
887void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
888struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
889					struct ib_device *device,
890					int page_list_len);
891struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
892int c4iw_dealloc_mw(struct ib_mw *mw);
893struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
894struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
895    virt, int acc, struct ib_udata *udata, int mr_id);
896struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
897struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
898					struct ib_phys_buf *buffer_list,
899					int num_phys_buf,
900					int acc,
901					u64 *iova_start);
902int c4iw_reregister_phys_mem(struct ib_mr *mr,
903				     int mr_rereg_mask,
904				     struct ib_pd *pd,
905				     struct ib_phys_buf *buffer_list,
906				     int num_phys_buf,
907				     int acc, u64 *iova_start);
908int c4iw_dereg_mr(struct ib_mr *ib_mr);
909int c4iw_destroy_cq(struct ib_cq *ib_cq);
910struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, struct ib_cq_init_attr *attr,
911					struct ib_ucontext *ib_context,
912					struct ib_udata *udata);
913int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
914int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
915int c4iw_destroy_qp(struct ib_qp *ib_qp);
916struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
917			     struct ib_qp_init_attr *attrs,
918			     struct ib_udata *udata);
919int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
920				 int attr_mask, struct ib_udata *udata);
921int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
922		     int attr_mask, struct ib_qp_init_attr *init_attr);
923struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
924u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
925void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
926u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
927void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
928int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
929void c4iw_flush_hw_cq(struct c4iw_cq *chp);
930void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
931int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
932int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
933int c4iw_flush_sq(struct c4iw_qp *qhp);
934int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
935u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
936int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
937u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
938void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
939		struct c4iw_dev_ucontext *uctx);
940u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
941void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
942		struct c4iw_dev_ucontext *uctx);
943void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
944void process_newconn(struct iw_cm_id *parent_cm_id,
945		struct socket *child_so);
946
947extern struct cxgb4_client t4c_client;
948extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
949extern int c4iw_max_read_depth;
950
951#if defined(__i386__) || defined(__amd64__)
952#define L1_CACHE_BYTES 128
953#else
954#define L1_CACHE_BYTES 32
955#endif
956
957void your_reg_device(struct c4iw_dev *dev);
958
959#define SGE_CTRLQ_NUM	0
960
961#endif
962