t4_hw.c revision 306664 
1/*-
2 * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/common/t4_hw.c 306664 2016-10-03 23:49:05Z jhb $");
29
30#include "opt_inet.h"
31
32#include <sys/param.h>
33#include <sys/eventhandler.h>
34
35#include "common.h"
36#include "t4_regs.h"
37#include "t4_regs_values.h"
38#include "firmware/t4fw_interface.h"
39
40#undef msleep
41#define msleep(x) do { \
42	if (cold) \
43		DELAY((x) * 1000); \
44	else \
45		pause("t4hw", (x) * hz / 1000); \
46} while (0)
47
48/**
49 *	t4_wait_op_done_val - wait until an operation is completed
50 *	@adapter: the adapter performing the operation
51 *	@reg: the register to check for completion
52 *	@mask: a single-bit field within @reg that indicates completion
53 *	@polarity: the value of the field when the operation is completed
54 *	@attempts: number of check iterations
55 *	@delay: delay in usecs between iterations
56 *	@valp: where to store the value of the register at completion time
57 *
58 *	Wait until an operation is completed by checking a bit in a register
59 *	up to @attempts times.  If @valp is not NULL the value of the register
60 *	at the time it indicated completion is stored there.  Returns 0 if the
61 *	operation completes and	-EAGAIN	otherwise.
62 */
63static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
64			       int polarity, int attempts, int delay, u32 *valp)
65{
66	while (1) {
67		u32 val = t4_read_reg(adapter, reg);
68
69		if (!!(val & mask) == polarity) {
70			if (valp)
71				*valp = val;
72			return 0;
73		}
74		if (--attempts == 0)
75			return -EAGAIN;
76		if (delay)
77			udelay(delay);
78	}
79}
80
81static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
82				  int polarity, int attempts, int delay)
83{
84	return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
85				   delay, NULL);
86}
87
88/**
89 *	t4_set_reg_field - set a register field to a value
90 *	@adapter: the adapter to program
91 *	@addr: the register address
92 *	@mask: specifies the portion of the register to modify
93 *	@val: the new value for the register field
94 *
95 *	Sets a register field specified by the supplied mask to the
96 *	given value.
97 */
98void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
99		      u32 val)
100{
101	u32 v = t4_read_reg(adapter, addr) & ~mask;
102
103	t4_write_reg(adapter, addr, v | val);
104	(void) t4_read_reg(adapter, addr);      /* flush */
105}
106
107/**
108 *	t4_read_indirect - read indirectly addressed registers
109 *	@adap: the adapter
110 *	@addr_reg: register holding the indirect address
111 *	@data_reg: register holding the value of the indirect register
112 *	@vals: where the read register values are stored
113 *	@nregs: how many indirect registers to read
114 *	@start_idx: index of first indirect register to read
115 *
116 *	Reads registers that are accessed indirectly through an address/data
117 *	register pair.
118 */
119void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
120			     unsigned int data_reg, u32 *vals,
121			     unsigned int nregs, unsigned int start_idx)
122{
123	while (nregs--) {
124		t4_write_reg(adap, addr_reg, start_idx);
125		*vals++ = t4_read_reg(adap, data_reg);
126		start_idx++;
127	}
128}
129
130/**
131 *	t4_write_indirect - write indirectly addressed registers
132 *	@adap: the adapter
133 *	@addr_reg: register holding the indirect addresses
134 *	@data_reg: register holding the value for the indirect registers
135 *	@vals: values to write
136 *	@nregs: how many indirect registers to write
137 *	@start_idx: address of first indirect register to write
138 *
139 *	Writes a sequential block of registers that are accessed indirectly
140 *	through an address/data register pair.
141 */
142void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
143		       unsigned int data_reg, const u32 *vals,
144		       unsigned int nregs, unsigned int start_idx)
145{
146	while (nregs--) {
147		t4_write_reg(adap, addr_reg, start_idx++);
148		t4_write_reg(adap, data_reg, *vals++);
149	}
150}
151
152/*
153 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
154 * mechanism.  This guarantees that we get the real value even if we're
155 * operating within a Virtual Machine and the Hypervisor is trapping our
156 * Configuration Space accesses.
157 *
158 * N.B. This routine should only be used as a last resort: the firmware uses
159 *      the backdoor registers on a regular basis and we can end up
160 *      conflicting with it's uses!
161 */
162u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
163{
164	u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
165	u32 val;
166
167	if (chip_id(adap) <= CHELSIO_T5)
168		req |= F_ENABLE;
169	else
170		req |= F_T6_ENABLE;
171
172	if (is_t4(adap))
173		req |= F_LOCALCFG;
174
175	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
176	val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
177
178	/*
179	 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
180	 * Configuration Space read.  (None of the other fields matter when
181	 * F_ENABLE is 0 so a simple register write is easier than a
182	 * read-modify-write via t4_set_reg_field().)
183	 */
184	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
185
186	return val;
187}
188
189/*
190 * t4_report_fw_error - report firmware error
191 * @adap: the adapter
192 *
193 * The adapter firmware can indicate error conditions to the host.
194 * If the firmware has indicated an error, print out the reason for
195 * the firmware error.
196 */
197static void t4_report_fw_error(struct adapter *adap)
198{
199	static const char *const reason[] = {
200		"Crash",			/* PCIE_FW_EVAL_CRASH */
201		"During Device Preparation",	/* PCIE_FW_EVAL_PREP */
202		"During Device Configuration",	/* PCIE_FW_EVAL_CONF */
203		"During Device Initialization",	/* PCIE_FW_EVAL_INIT */
204		"Unexpected Event",		/* PCIE_FW_EVAL_UNEXPECTEDEVENT */
205		"Insufficient Airflow",		/* PCIE_FW_EVAL_OVERHEAT */
206		"Device Shutdown",		/* PCIE_FW_EVAL_DEVICESHUTDOWN */
207		"Reserved",			/* reserved */
208	};
209	u32 pcie_fw;
210
211	pcie_fw = t4_read_reg(adap, A_PCIE_FW);
212	if (pcie_fw & F_PCIE_FW_ERR)
213		CH_ERR(adap, "Firmware reports adapter error: %s\n",
214			reason[G_PCIE_FW_EVAL(pcie_fw)]);
215}
216
217/*
218 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
219 */
220static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
221			 u32 mbox_addr)
222{
223	for ( ; nflit; nflit--, mbox_addr += 8)
224		*rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
225}
226
227/*
228 * Handle a FW assertion reported in a mailbox.
229 */
230static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
231{
232	CH_ALERT(adap,
233		  "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
234		  asrt->u.assert.filename_0_7,
235		  be32_to_cpu(asrt->u.assert.line),
236		  be32_to_cpu(asrt->u.assert.x),
237		  be32_to_cpu(asrt->u.assert.y));
238}
239
240#define X_CIM_PF_NOACCESS 0xeeeeeeee
241/**
242 *	t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
243 *	@adap: the adapter
244 *	@mbox: index of the mailbox to use
245 *	@cmd: the command to write
246 *	@size: command length in bytes
247 *	@rpl: where to optionally store the reply
248 *	@sleep_ok: if true we may sleep while awaiting command completion
249 *	@timeout: time to wait for command to finish before timing out
250 *		(negative implies @sleep_ok=false)
251 *
252 *	Sends the given command to FW through the selected mailbox and waits
253 *	for the FW to execute the command.  If @rpl is not %NULL it is used to
254 *	store the FW's reply to the command.  The command and its optional
255 *	reply are of the same length.  Some FW commands like RESET and
256 *	INITIALIZE can take a considerable amount of time to execute.
257 *	@sleep_ok determines whether we may sleep while awaiting the response.
258 *	If sleeping is allowed we use progressive backoff otherwise we spin.
259 *	Note that passing in a negative @timeout is an alternate mechanism
260 *	for specifying @sleep_ok=false.  This is useful when a higher level
261 *	interface allows for specification of @timeout but not @sleep_ok ...
262 *
263 *	The return value is 0 on success or a negative errno on failure.  A
264 *	failure can happen either because we are not able to execute the
265 *	command or FW executes it but signals an error.  In the latter case
266 *	the return value is the error code indicated by FW (negated).
267 */
268int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
269			    int size, void *rpl, bool sleep_ok, int timeout)
270{
271	/*
272	 * We delay in small increments at first in an effort to maintain
273	 * responsiveness for simple, fast executing commands but then back
274	 * off to larger delays to a maximum retry delay.
275	 */
276	static const int delay[] = {
277		1, 1, 3, 5, 10, 10, 20, 50, 100
278	};
279	u32 v;
280	u64 res;
281	int i, ms, delay_idx, ret;
282	const __be64 *p = cmd;
283	u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
284	u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
285	u32 ctl;
286	__be64 cmd_rpl[MBOX_LEN/8];
287	u32 pcie_fw;
288
289	if ((size & 15) || size > MBOX_LEN)
290		return -EINVAL;
291
292	if (adap->flags & IS_VF) {
293		if (is_t6(adap))
294			data_reg = FW_T6VF_MBDATA_BASE_ADDR;
295		else
296			data_reg = FW_T4VF_MBDATA_BASE_ADDR;
297		ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
298	}
299
300	/*
301	 * If we have a negative timeout, that implies that we can't sleep.
302	 */
303	if (timeout < 0) {
304		sleep_ok = false;
305		timeout = -timeout;
306	}
307
308	/*
309	 * Attempt to gain access to the mailbox.
310	 */
311	for (i = 0; i < 4; i++) {
312		ctl = t4_read_reg(adap, ctl_reg);
313		v = G_MBOWNER(ctl);
314		if (v != X_MBOWNER_NONE)
315			break;
316	}
317
318	/*
319	 * If we were unable to gain access, dequeue ourselves from the
320	 * mailbox atomic access list and report the error to our caller.
321	 */
322	if (v != X_MBOWNER_PL) {
323		t4_report_fw_error(adap);
324		ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
325		return ret;
326	}
327
328	/*
329	 * If we gain ownership of the mailbox and there's a "valid" message
330	 * in it, this is likely an asynchronous error message from the
331	 * firmware.  So we'll report that and then proceed on with attempting
332	 * to issue our own command ... which may well fail if the error
333	 * presaged the firmware crashing ...
334	 */
335	if (ctl & F_MBMSGVALID) {
336		CH_ERR(adap, "found VALID command in mbox %u: "
337		       "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
338		       (unsigned long long)t4_read_reg64(adap, data_reg),
339		       (unsigned long long)t4_read_reg64(adap, data_reg + 8),
340		       (unsigned long long)t4_read_reg64(adap, data_reg + 16),
341		       (unsigned long long)t4_read_reg64(adap, data_reg + 24),
342		       (unsigned long long)t4_read_reg64(adap, data_reg + 32),
343		       (unsigned long long)t4_read_reg64(adap, data_reg + 40),
344		       (unsigned long long)t4_read_reg64(adap, data_reg + 48),
345		       (unsigned long long)t4_read_reg64(adap, data_reg + 56));
346	}
347
348	/*
349	 * Copy in the new mailbox command and send it on its way ...
350	 */
351	for (i = 0; i < size; i += 8, p++)
352		t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
353
354	if (adap->flags & IS_VF) {
355		/*
356		 * For the VFs, the Mailbox Data "registers" are
357		 * actually backed by T4's "MA" interface rather than
358		 * PL Registers (as is the case for the PFs).  Because
359		 * these are in different coherency domains, the write
360		 * to the VF's PL-register-backed Mailbox Control can
361		 * race in front of the writes to the MA-backed VF
362		 * Mailbox Data "registers".  So we need to do a
363		 * read-back on at least one byte of the VF Mailbox
364		 * Data registers before doing the write to the VF
365		 * Mailbox Control register.
366		 */
367		t4_read_reg(adap, data_reg);
368	}
369
370	CH_DUMP_MBOX(adap, mbox, data_reg);
371
372	t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
373	t4_read_reg(adap, ctl_reg);	/* flush write */
374
375	delay_idx = 0;
376	ms = delay[0];
377
378	/*
379	 * Loop waiting for the reply; bail out if we time out or the firmware
380	 * reports an error.
381	 */
382	pcie_fw = 0;
383	for (i = 0; i < timeout; i += ms) {
384		if (!(adap->flags & IS_VF)) {
385			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
386			if (pcie_fw & F_PCIE_FW_ERR)
387				break;
388		}
389		if (sleep_ok) {
390			ms = delay[delay_idx];  /* last element may repeat */
391			if (delay_idx < ARRAY_SIZE(delay) - 1)
392				delay_idx++;
393			msleep(ms);
394		} else {
395			mdelay(ms);
396		}
397
398		v = t4_read_reg(adap, ctl_reg);
399		if (v == X_CIM_PF_NOACCESS)
400			continue;
401		if (G_MBOWNER(v) == X_MBOWNER_PL) {
402			if (!(v & F_MBMSGVALID)) {
403				t4_write_reg(adap, ctl_reg,
404					     V_MBOWNER(X_MBOWNER_NONE));
405				continue;
406			}
407
408			/*
409			 * Retrieve the command reply and release the mailbox.
410			 */
411			get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
412			t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
413
414			CH_DUMP_MBOX(adap, mbox, data_reg);
415
416			res = be64_to_cpu(cmd_rpl[0]);
417			if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
418				fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
419				res = V_FW_CMD_RETVAL(EIO);
420			} else if (rpl)
421				memcpy(rpl, cmd_rpl, size);
422			return -G_FW_CMD_RETVAL((int)res);
423		}
424	}
425
426	/*
427	 * We timed out waiting for a reply to our mailbox command.  Report
428	 * the error and also check to see if the firmware reported any
429	 * errors ...
430	 */
431	ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
432	CH_ERR(adap, "command %#x in mailbox %d timed out\n",
433	       *(const u8 *)cmd, mbox);
434
435	t4_report_fw_error(adap);
436	t4_fatal_err(adap);
437	return ret;
438}
439
440int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
441		    void *rpl, bool sleep_ok)
442{
443		return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
444					       sleep_ok, FW_CMD_MAX_TIMEOUT);
445
446}
447
448static int t4_edc_err_read(struct adapter *adap, int idx)
449{
450	u32 edc_ecc_err_addr_reg;
451	u32 edc_bist_status_rdata_reg;
452
453	if (is_t4(adap)) {
454		CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
455		return 0;
456	}
457	if (idx != 0 && idx != 1) {
458		CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
459		return 0;
460	}
461
462	edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
463	edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
464
465	CH_WARN(adap,
466		"edc%d err addr 0x%x: 0x%x.\n",
467		idx, edc_ecc_err_addr_reg,
468		t4_read_reg(adap, edc_ecc_err_addr_reg));
469	CH_WARN(adap,
470	 	"bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
471		edc_bist_status_rdata_reg,
472		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
473		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
474		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
475		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
476		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
477		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
478		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
479		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
480		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
481
482	return 0;
483}
484
485/**
486 *	t4_mc_read - read from MC through backdoor accesses
487 *	@adap: the adapter
488 *	@idx: which MC to access
489 *	@addr: address of first byte requested
490 *	@data: 64 bytes of data containing the requested address
491 *	@ecc: where to store the corresponding 64-bit ECC word
492 *
493 *	Read 64 bytes of data from MC starting at a 64-byte-aligned address
494 *	that covers the requested address @addr.  If @parity is not %NULL it
495 *	is assigned the 64-bit ECC word for the read data.
496 */
497int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
498{
499	int i;
500	u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
501	u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
502
503	if (is_t4(adap)) {
504		mc_bist_cmd_reg = A_MC_BIST_CMD;
505		mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
506		mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
507		mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
508		mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
509	} else {
510		mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
511		mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
512		mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
513		mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
514						  idx);
515		mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
516						  idx);
517	}
518
519	if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
520		return -EBUSY;
521	t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
522	t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
523	t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
524	t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
525		     F_START_BIST | V_BIST_CMD_GAP(1));
526	i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
527	if (i)
528		return i;
529
530#define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
531
532	for (i = 15; i >= 0; i--)
533		*data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
534	if (ecc)
535		*ecc = t4_read_reg64(adap, MC_DATA(16));
536#undef MC_DATA
537	return 0;
538}
539
540/**
541 *	t4_edc_read - read from EDC through backdoor accesses
542 *	@adap: the adapter
543 *	@idx: which EDC to access
544 *	@addr: address of first byte requested
545 *	@data: 64 bytes of data containing the requested address
546 *	@ecc: where to store the corresponding 64-bit ECC word
547 *
548 *	Read 64 bytes of data from EDC starting at a 64-byte-aligned address
549 *	that covers the requested address @addr.  If @parity is not %NULL it
550 *	is assigned the 64-bit ECC word for the read data.
551 */
552int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
553{
554	int i;
555	u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
556	u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
557
558	if (is_t4(adap)) {
559		edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
560		edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
561		edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
562		edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
563						    idx);
564		edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
565						    idx);
566	} else {
567/*
568 * These macro are missing in t4_regs.h file.
569 * Added temporarily for testing.
570 */
571#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
572#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
573		edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
574		edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
575		edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
576		edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
577						    idx);
578		edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
579						    idx);
580#undef EDC_REG_T5
581#undef EDC_STRIDE_T5
582	}
583
584	if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
585		return -EBUSY;
586	t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
587	t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
588	t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
589	t4_write_reg(adap, edc_bist_cmd_reg,
590		     V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
591	i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
592	if (i)
593		return i;
594
595#define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
596
597	for (i = 15; i >= 0; i--)
598		*data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
599	if (ecc)
600		*ecc = t4_read_reg64(adap, EDC_DATA(16));
601#undef EDC_DATA
602	return 0;
603}
604
605/**
606 *	t4_mem_read - read EDC 0, EDC 1 or MC into buffer
607 *	@adap: the adapter
608 *	@mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
609 *	@addr: address within indicated memory type
610 *	@len: amount of memory to read
611 *	@buf: host memory buffer
612 *
613 *	Reads an [almost] arbitrary memory region in the firmware: the
614 *	firmware memory address, length and host buffer must be aligned on
615 *	32-bit boudaries.  The memory is returned as a raw byte sequence from
616 *	the firmware's memory.  If this memory contains data structures which
617 *	contain multi-byte integers, it's the callers responsibility to
618 *	perform appropriate byte order conversions.
619 */
620int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
621		__be32 *buf)
622{
623	u32 pos, start, end, offset;
624	int ret;
625
626	/*
627	 * Argument sanity checks ...
628	 */
629	if ((addr & 0x3) || (len & 0x3))
630		return -EINVAL;
631
632	/*
633	 * The underlaying EDC/MC read routines read 64 bytes at a time so we
634	 * need to round down the start and round up the end.  We'll start
635	 * copying out of the first line at (addr - start) a word at a time.
636	 */
637	start = rounddown2(addr, 64);
638	end = roundup2(addr + len, 64);
639	offset = (addr - start)/sizeof(__be32);
640
641	for (pos = start; pos < end; pos += 64, offset = 0) {
642		__be32 data[16];
643
644		/*
645		 * Read the chip's memory block and bail if there's an error.
646		 */
647		if ((mtype == MEM_MC) || (mtype == MEM_MC1))
648			ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
649		else
650			ret = t4_edc_read(adap, mtype, pos, data, NULL);
651		if (ret)
652			return ret;
653
654		/*
655		 * Copy the data into the caller's memory buffer.
656		 */
657		while (offset < 16 && len > 0) {
658			*buf++ = data[offset++];
659			len -= sizeof(__be32);
660		}
661	}
662
663	return 0;
664}
665
666/*
667 * Return the specified PCI-E Configuration Space register from our Physical
668 * Function.  We try first via a Firmware LDST Command (if fw_attach != 0)
669 * since we prefer to let the firmware own all of these registers, but if that
670 * fails we go for it directly ourselves.
671 */
672u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
673{
674
675	/*
676	 * If fw_attach != 0, construct and send the Firmware LDST Command to
677	 * retrieve the specified PCI-E Configuration Space register.
678	 */
679	if (drv_fw_attach != 0) {
680		struct fw_ldst_cmd ldst_cmd;
681		int ret;
682
683		memset(&ldst_cmd, 0, sizeof(ldst_cmd));
684		ldst_cmd.op_to_addrspace =
685			cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
686				    F_FW_CMD_REQUEST |
687				    F_FW_CMD_READ |
688				    V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
689		ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
690		ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
691		ldst_cmd.u.pcie.ctrl_to_fn =
692			(F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
693		ldst_cmd.u.pcie.r = reg;
694
695		/*
696		 * If the LDST Command succeeds, return the result, otherwise
697		 * fall through to reading it directly ourselves ...
698		 */
699		ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
700				 &ldst_cmd);
701		if (ret == 0)
702			return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
703
704		CH_WARN(adap, "Firmware failed to return "
705			"Configuration Space register %d, err = %d\n",
706			reg, -ret);
707	}
708
709	/*
710	 * Read the desired Configuration Space register via the PCI-E
711	 * Backdoor mechanism.
712	 */
713	return t4_hw_pci_read_cfg4(adap, reg);
714}
715
716/**
717 *	t4_get_regs_len - return the size of the chips register set
718 *	@adapter: the adapter
719 *
720 *	Returns the size of the chip's BAR0 register space.
721 */
722unsigned int t4_get_regs_len(struct adapter *adapter)
723{
724	unsigned int chip_version = chip_id(adapter);
725
726	switch (chip_version) {
727	case CHELSIO_T4:
728		if (adapter->flags & IS_VF)
729			return FW_T4VF_REGMAP_SIZE;
730		return T4_REGMAP_SIZE;
731
732	case CHELSIO_T5:
733	case CHELSIO_T6:
734		if (adapter->flags & IS_VF)
735			return FW_T4VF_REGMAP_SIZE;
736		return T5_REGMAP_SIZE;
737	}
738
739	CH_ERR(adapter,
740		"Unsupported chip version %d\n", chip_version);
741	return 0;
742}
743
744/**
745 *	t4_get_regs - read chip registers into provided buffer
746 *	@adap: the adapter
747 *	@buf: register buffer
748 *	@buf_size: size (in bytes) of register buffer
749 *
750 *	If the provided register buffer isn't large enough for the chip's
751 *	full register range, the register dump will be truncated to the
752 *	register buffer's size.
753 */
754void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
755{
756	static const unsigned int t4_reg_ranges[] = {
757		0x1008, 0x1108,
758		0x1180, 0x1184,
759		0x1190, 0x1194,
760		0x11a0, 0x11a4,
761		0x11b0, 0x11b4,
762		0x11fc, 0x123c,
763		0x1300, 0x173c,
764		0x1800, 0x18fc,
765		0x3000, 0x30d8,
766		0x30e0, 0x30e4,
767		0x30ec, 0x5910,
768		0x5920, 0x5924,
769		0x5960, 0x5960,
770		0x5968, 0x5968,
771		0x5970, 0x5970,
772		0x5978, 0x5978,
773		0x5980, 0x5980,
774		0x5988, 0x5988,
775		0x5990, 0x5990,
776		0x5998, 0x5998,
777		0x59a0, 0x59d4,
778		0x5a00, 0x5ae0,
779		0x5ae8, 0x5ae8,
780		0x5af0, 0x5af0,
781		0x5af8, 0x5af8,
782		0x6000, 0x6098,
783		0x6100, 0x6150,
784		0x6200, 0x6208,
785		0x6240, 0x6248,
786		0x6280, 0x62b0,
787		0x62c0, 0x6338,
788		0x6370, 0x638c,
789		0x6400, 0x643c,
790		0x6500, 0x6524,
791		0x6a00, 0x6a04,
792		0x6a14, 0x6a38,
793		0x6a60, 0x6a70,
794		0x6a78, 0x6a78,
795		0x6b00, 0x6b0c,
796		0x6b1c, 0x6b84,
797		0x6bf0, 0x6bf8,
798		0x6c00, 0x6c0c,
799		0x6c1c, 0x6c84,
800		0x6cf0, 0x6cf8,
801		0x6d00, 0x6d0c,
802		0x6d1c, 0x6d84,
803		0x6df0, 0x6df8,
804		0x6e00, 0x6e0c,
805		0x6e1c, 0x6e84,
806		0x6ef0, 0x6ef8,
807		0x6f00, 0x6f0c,
808		0x6f1c, 0x6f84,
809		0x6ff0, 0x6ff8,
810		0x7000, 0x700c,
811		0x701c, 0x7084,
812		0x70f0, 0x70f8,
813		0x7100, 0x710c,
814		0x711c, 0x7184,
815		0x71f0, 0x71f8,
816		0x7200, 0x720c,
817		0x721c, 0x7284,
818		0x72f0, 0x72f8,
819		0x7300, 0x730c,
820		0x731c, 0x7384,
821		0x73f0, 0x73f8,
822		0x7400, 0x7450,
823		0x7500, 0x7530,
824		0x7600, 0x760c,
825		0x7614, 0x761c,
826		0x7680, 0x76cc,
827		0x7700, 0x7798,
828		0x77c0, 0x77fc,
829		0x7900, 0x79fc,
830		0x7b00, 0x7b58,
831		0x7b60, 0x7b84,
832		0x7b8c, 0x7c38,
833		0x7d00, 0x7d38,
834		0x7d40, 0x7d80,
835		0x7d8c, 0x7ddc,
836		0x7de4, 0x7e04,
837		0x7e10, 0x7e1c,
838		0x7e24, 0x7e38,
839		0x7e40, 0x7e44,
840		0x7e4c, 0x7e78,
841		0x7e80, 0x7ea4,
842		0x7eac, 0x7edc,
843		0x7ee8, 0x7efc,
844		0x8dc0, 0x8e04,
845		0x8e10, 0x8e1c,
846		0x8e30, 0x8e78,
847		0x8ea0, 0x8eb8,
848		0x8ec0, 0x8f6c,
849		0x8fc0, 0x9008,
850		0x9010, 0x9058,
851		0x9060, 0x9060,
852		0x9068, 0x9074,
853		0x90fc, 0x90fc,
854		0x9400, 0x9408,
855		0x9410, 0x9458,
856		0x9600, 0x9600,
857		0x9608, 0x9638,
858		0x9640, 0x96bc,
859		0x9800, 0x9808,
860		0x9820, 0x983c,
861		0x9850, 0x9864,
862		0x9c00, 0x9c6c,
863		0x9c80, 0x9cec,
864		0x9d00, 0x9d6c,
865		0x9d80, 0x9dec,
866		0x9e00, 0x9e6c,
867		0x9e80, 0x9eec,
868		0x9f00, 0x9f6c,
869		0x9f80, 0x9fec,
870		0xd004, 0xd004,
871		0xd010, 0xd03c,
872		0xdfc0, 0xdfe0,
873		0xe000, 0xea7c,
874		0xf000, 0x11190,
875		0x19040, 0x1906c,
876		0x19078, 0x19080,
877		0x1908c, 0x190e4,
878		0x190f0, 0x190f8,
879		0x19100, 0x19110,
880		0x19120, 0x19124,
881		0x19150, 0x19194,
882		0x1919c, 0x191b0,
883		0x191d0, 0x191e8,
884		0x19238, 0x1924c,
885		0x193f8, 0x1943c,
886		0x1944c, 0x19474,
887		0x19490, 0x194e0,
888		0x194f0, 0x194f8,
889		0x19800, 0x19c08,
890		0x19c10, 0x19c90,
891		0x19ca0, 0x19ce4,
892		0x19cf0, 0x19d40,
893		0x19d50, 0x19d94,
894		0x19da0, 0x19de8,
895		0x19df0, 0x19e40,
896		0x19e50, 0x19e90,
897		0x19ea0, 0x19f4c,
898		0x1a000, 0x1a004,
899		0x1a010, 0x1a06c,
900		0x1a0b0, 0x1a0e4,
901		0x1a0ec, 0x1a0f4,
902		0x1a100, 0x1a108,
903		0x1a114, 0x1a120,
904		0x1a128, 0x1a130,
905		0x1a138, 0x1a138,
906		0x1a190, 0x1a1c4,
907		0x1a1fc, 0x1a1fc,
908		0x1e040, 0x1e04c,
909		0x1e284, 0x1e28c,
910		0x1e2c0, 0x1e2c0,
911		0x1e2e0, 0x1e2e0,
912		0x1e300, 0x1e384,
913		0x1e3c0, 0x1e3c8,
914		0x1e440, 0x1e44c,
915		0x1e684, 0x1e68c,
916		0x1e6c0, 0x1e6c0,
917		0x1e6e0, 0x1e6e0,
918		0x1e700, 0x1e784,
919		0x1e7c0, 0x1e7c8,
920		0x1e840, 0x1e84c,
921		0x1ea84, 0x1ea8c,
922		0x1eac0, 0x1eac0,
923		0x1eae0, 0x1eae0,
924		0x1eb00, 0x1eb84,
925		0x1ebc0, 0x1ebc8,
926		0x1ec40, 0x1ec4c,
927		0x1ee84, 0x1ee8c,
928		0x1eec0, 0x1eec0,
929		0x1eee0, 0x1eee0,
930		0x1ef00, 0x1ef84,
931		0x1efc0, 0x1efc8,
932		0x1f040, 0x1f04c,
933		0x1f284, 0x1f28c,
934		0x1f2c0, 0x1f2c0,
935		0x1f2e0, 0x1f2e0,
936		0x1f300, 0x1f384,
937		0x1f3c0, 0x1f3c8,
938		0x1f440, 0x1f44c,
939		0x1f684, 0x1f68c,
940		0x1f6c0, 0x1f6c0,
941		0x1f6e0, 0x1f6e0,
942		0x1f700, 0x1f784,
943		0x1f7c0, 0x1f7c8,
944		0x1f840, 0x1f84c,
945		0x1fa84, 0x1fa8c,
946		0x1fac0, 0x1fac0,
947		0x1fae0, 0x1fae0,
948		0x1fb00, 0x1fb84,
949		0x1fbc0, 0x1fbc8,
950		0x1fc40, 0x1fc4c,
951		0x1fe84, 0x1fe8c,
952		0x1fec0, 0x1fec0,
953		0x1fee0, 0x1fee0,
954		0x1ff00, 0x1ff84,
955		0x1ffc0, 0x1ffc8,
956		0x20000, 0x2002c,
957		0x20100, 0x2013c,
958		0x20190, 0x201a0,
959		0x201a8, 0x201b8,
960		0x201c4, 0x201c8,
961		0x20200, 0x20318,
962		0x20400, 0x204b4,
963		0x204c0, 0x20528,
964		0x20540, 0x20614,
965		0x21000, 0x21040,
966		0x2104c, 0x21060,
967		0x210c0, 0x210ec,
968		0x21200, 0x21268,
969		0x21270, 0x21284,
970		0x212fc, 0x21388,
971		0x21400, 0x21404,
972		0x21500, 0x21500,
973		0x21510, 0x21518,
974		0x2152c, 0x21530,
975		0x2153c, 0x2153c,
976		0x21550, 0x21554,
977		0x21600, 0x21600,
978		0x21608, 0x2161c,
979		0x21624, 0x21628,
980		0x21630, 0x21634,
981		0x2163c, 0x2163c,
982		0x21700, 0x2171c,
983		0x21780, 0x2178c,
984		0x21800, 0x21818,
985		0x21820, 0x21828,
986		0x21830, 0x21848,
987		0x21850, 0x21854,
988		0x21860, 0x21868,
989		0x21870, 0x21870,
990		0x21878, 0x21898,
991		0x218a0, 0x218a8,
992		0x218b0, 0x218c8,
993		0x218d0, 0x218d4,
994		0x218e0, 0x218e8,
995		0x218f0, 0x218f0,
996		0x218f8, 0x21a18,
997		0x21a20, 0x21a28,
998		0x21a30, 0x21a48,
999		0x21a50, 0x21a54,
1000		0x21a60, 0x21a68,
1001		0x21a70, 0x21a70,
1002		0x21a78, 0x21a98,
1003		0x21aa0, 0x21aa8,
1004		0x21ab0, 0x21ac8,
1005		0x21ad0, 0x21ad4,
1006		0x21ae0, 0x21ae8,
1007		0x21af0, 0x21af0,
1008		0x21af8, 0x21c18,
1009		0x21c20, 0x21c20,
1010		0x21c28, 0x21c30,
1011		0x21c38, 0x21c38,
1012		0x21c80, 0x21c98,
1013		0x21ca0, 0x21ca8,
1014		0x21cb0, 0x21cc8,
1015		0x21cd0, 0x21cd4,
1016		0x21ce0, 0x21ce8,
1017		0x21cf0, 0x21cf0,
1018		0x21cf8, 0x21d7c,
1019		0x21e00, 0x21e04,
1020		0x22000, 0x2202c,
1021		0x22100, 0x2213c,
1022		0x22190, 0x221a0,
1023		0x221a8, 0x221b8,
1024		0x221c4, 0x221c8,
1025		0x22200, 0x22318,
1026		0x22400, 0x224b4,
1027		0x224c0, 0x22528,
1028		0x22540, 0x22614,
1029		0x23000, 0x23040,
1030		0x2304c, 0x23060,
1031		0x230c0, 0x230ec,
1032		0x23200, 0x23268,
1033		0x23270, 0x23284,
1034		0x232fc, 0x23388,
1035		0x23400, 0x23404,
1036		0x23500, 0x23500,
1037		0x23510, 0x23518,
1038		0x2352c, 0x23530,
1039		0x2353c, 0x2353c,
1040		0x23550, 0x23554,
1041		0x23600, 0x23600,
1042		0x23608, 0x2361c,
1043		0x23624, 0x23628,
1044		0x23630, 0x23634,
1045		0x2363c, 0x2363c,
1046		0x23700, 0x2371c,
1047		0x23780, 0x2378c,
1048		0x23800, 0x23818,
1049		0x23820, 0x23828,
1050		0x23830, 0x23848,
1051		0x23850, 0x23854,
1052		0x23860, 0x23868,
1053		0x23870, 0x23870,
1054		0x23878, 0x23898,
1055		0x238a0, 0x238a8,
1056		0x238b0, 0x238c8,
1057		0x238d0, 0x238d4,
1058		0x238e0, 0x238e8,
1059		0x238f0, 0x238f0,
1060		0x238f8, 0x23a18,
1061		0x23a20, 0x23a28,
1062		0x23a30, 0x23a48,
1063		0x23a50, 0x23a54,
1064		0x23a60, 0x23a68,
1065		0x23a70, 0x23a70,
1066		0x23a78, 0x23a98,
1067		0x23aa0, 0x23aa8,
1068		0x23ab0, 0x23ac8,
1069		0x23ad0, 0x23ad4,
1070		0x23ae0, 0x23ae8,
1071		0x23af0, 0x23af0,
1072		0x23af8, 0x23c18,
1073		0x23c20, 0x23c20,
1074		0x23c28, 0x23c30,
1075		0x23c38, 0x23c38,
1076		0x23c80, 0x23c98,
1077		0x23ca0, 0x23ca8,
1078		0x23cb0, 0x23cc8,
1079		0x23cd0, 0x23cd4,
1080		0x23ce0, 0x23ce8,
1081		0x23cf0, 0x23cf0,
1082		0x23cf8, 0x23d7c,
1083		0x23e00, 0x23e04,
1084		0x24000, 0x2402c,
1085		0x24100, 0x2413c,
1086		0x24190, 0x241a0,
1087		0x241a8, 0x241b8,
1088		0x241c4, 0x241c8,
1089		0x24200, 0x24318,
1090		0x24400, 0x244b4,
1091		0x244c0, 0x24528,
1092		0x24540, 0x24614,
1093		0x25000, 0x25040,
1094		0x2504c, 0x25060,
1095		0x250c0, 0x250ec,
1096		0x25200, 0x25268,
1097		0x25270, 0x25284,
1098		0x252fc, 0x25388,
1099		0x25400, 0x25404,
1100		0x25500, 0x25500,
1101		0x25510, 0x25518,
1102		0x2552c, 0x25530,
1103		0x2553c, 0x2553c,
1104		0x25550, 0x25554,
1105		0x25600, 0x25600,
1106		0x25608, 0x2561c,
1107		0x25624, 0x25628,
1108		0x25630, 0x25634,
1109		0x2563c, 0x2563c,
1110		0x25700, 0x2571c,
1111		0x25780, 0x2578c,
1112		0x25800, 0x25818,
1113		0x25820, 0x25828,
1114		0x25830, 0x25848,
1115		0x25850, 0x25854,
1116		0x25860, 0x25868,
1117		0x25870, 0x25870,
1118		0x25878, 0x25898,
1119		0x258a0, 0x258a8,
1120		0x258b0, 0x258c8,
1121		0x258d0, 0x258d4,
1122		0x258e0, 0x258e8,
1123		0x258f0, 0x258f0,
1124		0x258f8, 0x25a18,
1125		0x25a20, 0x25a28,
1126		0x25a30, 0x25a48,
1127		0x25a50, 0x25a54,
1128		0x25a60, 0x25a68,
1129		0x25a70, 0x25a70,
1130		0x25a78, 0x25a98,
1131		0x25aa0, 0x25aa8,
1132		0x25ab0, 0x25ac8,
1133		0x25ad0, 0x25ad4,
1134		0x25ae0, 0x25ae8,
1135		0x25af0, 0x25af0,
1136		0x25af8, 0x25c18,
1137		0x25c20, 0x25c20,
1138		0x25c28, 0x25c30,
1139		0x25c38, 0x25c38,
1140		0x25c80, 0x25c98,
1141		0x25ca0, 0x25ca8,
1142		0x25cb0, 0x25cc8,
1143		0x25cd0, 0x25cd4,
1144		0x25ce0, 0x25ce8,
1145		0x25cf0, 0x25cf0,
1146		0x25cf8, 0x25d7c,
1147		0x25e00, 0x25e04,
1148		0x26000, 0x2602c,
1149		0x26100, 0x2613c,
1150		0x26190, 0x261a0,
1151		0x261a8, 0x261b8,
1152		0x261c4, 0x261c8,
1153		0x26200, 0x26318,
1154		0x26400, 0x264b4,
1155		0x264c0, 0x26528,
1156		0x26540, 0x26614,
1157		0x27000, 0x27040,
1158		0x2704c, 0x27060,
1159		0x270c0, 0x270ec,
1160		0x27200, 0x27268,
1161		0x27270, 0x27284,
1162		0x272fc, 0x27388,
1163		0x27400, 0x27404,
1164		0x27500, 0x27500,
1165		0x27510, 0x27518,
1166		0x2752c, 0x27530,
1167		0x2753c, 0x2753c,
1168		0x27550, 0x27554,
1169		0x27600, 0x27600,
1170		0x27608, 0x2761c,
1171		0x27624, 0x27628,
1172		0x27630, 0x27634,
1173		0x2763c, 0x2763c,
1174		0x27700, 0x2771c,
1175		0x27780, 0x2778c,
1176		0x27800, 0x27818,
1177		0x27820, 0x27828,
1178		0x27830, 0x27848,
1179		0x27850, 0x27854,
1180		0x27860, 0x27868,
1181		0x27870, 0x27870,
1182		0x27878, 0x27898,
1183		0x278a0, 0x278a8,
1184		0x278b0, 0x278c8,
1185		0x278d0, 0x278d4,
1186		0x278e0, 0x278e8,
1187		0x278f0, 0x278f0,
1188		0x278f8, 0x27a18,
1189		0x27a20, 0x27a28,
1190		0x27a30, 0x27a48,
1191		0x27a50, 0x27a54,
1192		0x27a60, 0x27a68,
1193		0x27a70, 0x27a70,
1194		0x27a78, 0x27a98,
1195		0x27aa0, 0x27aa8,
1196		0x27ab0, 0x27ac8,
1197		0x27ad0, 0x27ad4,
1198		0x27ae0, 0x27ae8,
1199		0x27af0, 0x27af0,
1200		0x27af8, 0x27c18,
1201		0x27c20, 0x27c20,
1202		0x27c28, 0x27c30,
1203		0x27c38, 0x27c38,
1204		0x27c80, 0x27c98,
1205		0x27ca0, 0x27ca8,
1206		0x27cb0, 0x27cc8,
1207		0x27cd0, 0x27cd4,
1208		0x27ce0, 0x27ce8,
1209		0x27cf0, 0x27cf0,
1210		0x27cf8, 0x27d7c,
1211		0x27e00, 0x27e04,
1212	};
1213
1214	static const unsigned int t4vf_reg_ranges[] = {
1215		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1216		VF_MPS_REG(A_MPS_VF_CTL),
1217		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1218		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1219		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1220		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1221		FW_T4VF_MBDATA_BASE_ADDR,
1222		FW_T4VF_MBDATA_BASE_ADDR +
1223		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1224	};
1225
1226	static const unsigned int t5_reg_ranges[] = {
1227		0x1008, 0x10c0,
1228		0x10cc, 0x10f8,
1229		0x1100, 0x1100,
1230		0x110c, 0x1148,
1231		0x1180, 0x1184,
1232		0x1190, 0x1194,
1233		0x11a0, 0x11a4,
1234		0x11b0, 0x11b4,
1235		0x11fc, 0x123c,
1236		0x1280, 0x173c,
1237		0x1800, 0x18fc,
1238		0x3000, 0x3028,
1239		0x3060, 0x30b0,
1240		0x30b8, 0x30d8,
1241		0x30e0, 0x30fc,
1242		0x3140, 0x357c,
1243		0x35a8, 0x35cc,
1244		0x35ec, 0x35ec,
1245		0x3600, 0x5624,
1246		0x56cc, 0x56ec,
1247		0x56f4, 0x5720,
1248		0x5728, 0x575c,
1249		0x580c, 0x5814,
1250		0x5890, 0x589c,
1251		0x58a4, 0x58ac,
1252		0x58b8, 0x58bc,
1253		0x5940, 0x59c8,
1254		0x59d0, 0x59dc,
1255		0x59fc, 0x5a18,
1256		0x5a60, 0x5a70,
1257		0x5a80, 0x5a9c,
1258		0x5b94, 0x5bfc,
1259		0x6000, 0x6020,
1260		0x6028, 0x6040,
1261		0x6058, 0x609c,
1262		0x60a8, 0x614c,
1263		0x7700, 0x7798,
1264		0x77c0, 0x78fc,
1265		0x7b00, 0x7b58,
1266		0x7b60, 0x7b84,
1267		0x7b8c, 0x7c54,
1268		0x7d00, 0x7d38,
1269		0x7d40, 0x7d80,
1270		0x7d8c, 0x7ddc,
1271		0x7de4, 0x7e04,
1272		0x7e10, 0x7e1c,
1273		0x7e24, 0x7e38,
1274		0x7e40, 0x7e44,
1275		0x7e4c, 0x7e78,
1276		0x7e80, 0x7edc,
1277		0x7ee8, 0x7efc,
1278		0x8dc0, 0x8de0,
1279		0x8df8, 0x8e04,
1280		0x8e10, 0x8e84,
1281		0x8ea0, 0x8f84,
1282		0x8fc0, 0x9058,
1283		0x9060, 0x9060,
1284		0x9068, 0x90f8,
1285		0x9400, 0x9408,
1286		0x9410, 0x9470,
1287		0x9600, 0x9600,
1288		0x9608, 0x9638,
1289		0x9640, 0x96f4,
1290		0x9800, 0x9808,
1291		0x9820, 0x983c,
1292		0x9850, 0x9864,
1293		0x9c00, 0x9c6c,
1294		0x9c80, 0x9cec,
1295		0x9d00, 0x9d6c,
1296		0x9d80, 0x9dec,
1297		0x9e00, 0x9e6c,
1298		0x9e80, 0x9eec,
1299		0x9f00, 0x9f6c,
1300		0x9f80, 0xa020,
1301		0xd004, 0xd004,
1302		0xd010, 0xd03c,
1303		0xdfc0, 0xdfe0,
1304		0xe000, 0x1106c,
1305		0x11074, 0x11088,
1306		0x1109c, 0x1117c,
1307		0x11190, 0x11204,
1308		0x19040, 0x1906c,
1309		0x19078, 0x19080,
1310		0x1908c, 0x190e8,
1311		0x190f0, 0x190f8,
1312		0x19100, 0x19110,
1313		0x19120, 0x19124,
1314		0x19150, 0x19194,
1315		0x1919c, 0x191b0,
1316		0x191d0, 0x191e8,
1317		0x19238, 0x19290,
1318		0x193f8, 0x19428,
1319		0x19430, 0x19444,
1320		0x1944c, 0x1946c,
1321		0x19474, 0x19474,
1322		0x19490, 0x194cc,
1323		0x194f0, 0x194f8,
1324		0x19c00, 0x19c08,
1325		0x19c10, 0x19c60,
1326		0x19c94, 0x19ce4,
1327		0x19cf0, 0x19d40,
1328		0x19d50, 0x19d94,
1329		0x19da0, 0x19de8,
1330		0x19df0, 0x19e10,
1331		0x19e50, 0x19e90,
1332		0x19ea0, 0x19f24,
1333		0x19f34, 0x19f34,
1334		0x19f40, 0x19f50,
1335		0x19f90, 0x19fb4,
1336		0x19fc4, 0x19fe4,
1337		0x1a000, 0x1a004,
1338		0x1a010, 0x1a06c,
1339		0x1a0b0, 0x1a0e4,
1340		0x1a0ec, 0x1a0f8,
1341		0x1a100, 0x1a108,
1342		0x1a114, 0x1a120,
1343		0x1a128, 0x1a130,
1344		0x1a138, 0x1a138,
1345		0x1a190, 0x1a1c4,
1346		0x1a1fc, 0x1a1fc,
1347		0x1e008, 0x1e00c,
1348		0x1e040, 0x1e044,
1349		0x1e04c, 0x1e04c,
1350		0x1e284, 0x1e290,
1351		0x1e2c0, 0x1e2c0,
1352		0x1e2e0, 0x1e2e0,
1353		0x1e300, 0x1e384,
1354		0x1e3c0, 0x1e3c8,
1355		0x1e408, 0x1e40c,
1356		0x1e440, 0x1e444,
1357		0x1e44c, 0x1e44c,
1358		0x1e684, 0x1e690,
1359		0x1e6c0, 0x1e6c0,
1360		0x1e6e0, 0x1e6e0,
1361		0x1e700, 0x1e784,
1362		0x1e7c0, 0x1e7c8,
1363		0x1e808, 0x1e80c,
1364		0x1e840, 0x1e844,
1365		0x1e84c, 0x1e84c,
1366		0x1ea84, 0x1ea90,
1367		0x1eac0, 0x1eac0,
1368		0x1eae0, 0x1eae0,
1369		0x1eb00, 0x1eb84,
1370		0x1ebc0, 0x1ebc8,
1371		0x1ec08, 0x1ec0c,
1372		0x1ec40, 0x1ec44,
1373		0x1ec4c, 0x1ec4c,
1374		0x1ee84, 0x1ee90,
1375		0x1eec0, 0x1eec0,
1376		0x1eee0, 0x1eee0,
1377		0x1ef00, 0x1ef84,
1378		0x1efc0, 0x1efc8,
1379		0x1f008, 0x1f00c,
1380		0x1f040, 0x1f044,
1381		0x1f04c, 0x1f04c,
1382		0x1f284, 0x1f290,
1383		0x1f2c0, 0x1f2c0,
1384		0x1f2e0, 0x1f2e0,
1385		0x1f300, 0x1f384,
1386		0x1f3c0, 0x1f3c8,
1387		0x1f408, 0x1f40c,
1388		0x1f440, 0x1f444,
1389		0x1f44c, 0x1f44c,
1390		0x1f684, 0x1f690,
1391		0x1f6c0, 0x1f6c0,
1392		0x1f6e0, 0x1f6e0,
1393		0x1f700, 0x1f784,
1394		0x1f7c0, 0x1f7c8,
1395		0x1f808, 0x1f80c,
1396		0x1f840, 0x1f844,
1397		0x1f84c, 0x1f84c,
1398		0x1fa84, 0x1fa90,
1399		0x1fac0, 0x1fac0,
1400		0x1fae0, 0x1fae0,
1401		0x1fb00, 0x1fb84,
1402		0x1fbc0, 0x1fbc8,
1403		0x1fc08, 0x1fc0c,
1404		0x1fc40, 0x1fc44,
1405		0x1fc4c, 0x1fc4c,
1406		0x1fe84, 0x1fe90,
1407		0x1fec0, 0x1fec0,
1408		0x1fee0, 0x1fee0,
1409		0x1ff00, 0x1ff84,
1410		0x1ffc0, 0x1ffc8,
1411		0x30000, 0x30030,
1412		0x30038, 0x30038,
1413		0x30040, 0x30040,
1414		0x30100, 0x30144,
1415		0x30190, 0x301a0,
1416		0x301a8, 0x301b8,
1417		0x301c4, 0x301c8,
1418		0x301d0, 0x301d0,
1419		0x30200, 0x30318,
1420		0x30400, 0x304b4,
1421		0x304c0, 0x3052c,
1422		0x30540, 0x3061c,
1423		0x30800, 0x30828,
1424		0x30834, 0x30834,
1425		0x308c0, 0x30908,
1426		0x30910, 0x309ac,
1427		0x30a00, 0x30a14,
1428		0x30a1c, 0x30a2c,
1429		0x30a44, 0x30a50,
1430		0x30a74, 0x30a74,
1431		0x30a7c, 0x30afc,
1432		0x30b08, 0x30c24,
1433		0x30d00, 0x30d00,
1434		0x30d08, 0x30d14,
1435		0x30d1c, 0x30d20,
1436		0x30d3c, 0x30d3c,
1437		0x30d48, 0x30d50,
1438		0x31200, 0x3120c,
1439		0x31220, 0x31220,
1440		0x31240, 0x31240,
1441		0x31600, 0x3160c,
1442		0x31a00, 0x31a1c,
1443		0x31e00, 0x31e20,
1444		0x31e38, 0x31e3c,
1445		0x31e80, 0x31e80,
1446		0x31e88, 0x31ea8,
1447		0x31eb0, 0x31eb4,
1448		0x31ec8, 0x31ed4,
1449		0x31fb8, 0x32004,
1450		0x32200, 0x32200,
1451		0x32208, 0x32240,
1452		0x32248, 0x32280,
1453		0x32288, 0x322c0,
1454		0x322c8, 0x322fc,
1455		0x32600, 0x32630,
1456		0x32a00, 0x32abc,
1457		0x32b00, 0x32b10,
1458		0x32b20, 0x32b30,
1459		0x32b40, 0x32b50,
1460		0x32b60, 0x32b70,
1461		0x33000, 0x33028,
1462		0x33030, 0x33048,
1463		0x33060, 0x33068,
1464		0x33070, 0x3309c,
1465		0x330f0, 0x33128,
1466		0x33130, 0x33148,
1467		0x33160, 0x33168,
1468		0x33170, 0x3319c,
1469		0x331f0, 0x33238,
1470		0x33240, 0x33240,
1471		0x33248, 0x33250,
1472		0x3325c, 0x33264,
1473		0x33270, 0x332b8,
1474		0x332c0, 0x332e4,
1475		0x332f8, 0x33338,
1476		0x33340, 0x33340,
1477		0x33348, 0x33350,
1478		0x3335c, 0x33364,
1479		0x33370, 0x333b8,
1480		0x333c0, 0x333e4,
1481		0x333f8, 0x33428,
1482		0x33430, 0x33448,
1483		0x33460, 0x33468,
1484		0x33470, 0x3349c,
1485		0x334f0, 0x33528,
1486		0x33530, 0x33548,
1487		0x33560, 0x33568,
1488		0x33570, 0x3359c,
1489		0x335f0, 0x33638,
1490		0x33640, 0x33640,
1491		0x33648, 0x33650,
1492		0x3365c, 0x33664,
1493		0x33670, 0x336b8,
1494		0x336c0, 0x336e4,
1495		0x336f8, 0x33738,
1496		0x33740, 0x33740,
1497		0x33748, 0x33750,
1498		0x3375c, 0x33764,
1499		0x33770, 0x337b8,
1500		0x337c0, 0x337e4,
1501		0x337f8, 0x337fc,
1502		0x33814, 0x33814,
1503		0x3382c, 0x3382c,
1504		0x33880, 0x3388c,
1505		0x338e8, 0x338ec,
1506		0x33900, 0x33928,
1507		0x33930, 0x33948,
1508		0x33960, 0x33968,
1509		0x33970, 0x3399c,
1510		0x339f0, 0x33a38,
1511		0x33a40, 0x33a40,
1512		0x33a48, 0x33a50,
1513		0x33a5c, 0x33a64,
1514		0x33a70, 0x33ab8,
1515		0x33ac0, 0x33ae4,
1516		0x33af8, 0x33b10,
1517		0x33b28, 0x33b28,
1518		0x33b3c, 0x33b50,
1519		0x33bf0, 0x33c10,
1520		0x33c28, 0x33c28,
1521		0x33c3c, 0x33c50,
1522		0x33cf0, 0x33cfc,
1523		0x34000, 0x34030,
1524		0x34038, 0x34038,
1525		0x34040, 0x34040,
1526		0x34100, 0x34144,
1527		0x34190, 0x341a0,
1528		0x341a8, 0x341b8,
1529		0x341c4, 0x341c8,
1530		0x341d0, 0x341d0,
1531		0x34200, 0x34318,
1532		0x34400, 0x344b4,
1533		0x344c0, 0x3452c,
1534		0x34540, 0x3461c,
1535		0x34800, 0x34828,
1536		0x34834, 0x34834,
1537		0x348c0, 0x34908,
1538		0x34910, 0x349ac,
1539		0x34a00, 0x34a14,
1540		0x34a1c, 0x34a2c,
1541		0x34a44, 0x34a50,
1542		0x34a74, 0x34a74,
1543		0x34a7c, 0x34afc,
1544		0x34b08, 0x34c24,
1545		0x34d00, 0x34d00,
1546		0x34d08, 0x34d14,
1547		0x34d1c, 0x34d20,
1548		0x34d3c, 0x34d3c,
1549		0x34d48, 0x34d50,
1550		0x35200, 0x3520c,
1551		0x35220, 0x35220,
1552		0x35240, 0x35240,
1553		0x35600, 0x3560c,
1554		0x35a00, 0x35a1c,
1555		0x35e00, 0x35e20,
1556		0x35e38, 0x35e3c,
1557		0x35e80, 0x35e80,
1558		0x35e88, 0x35ea8,
1559		0x35eb0, 0x35eb4,
1560		0x35ec8, 0x35ed4,
1561		0x35fb8, 0x36004,
1562		0x36200, 0x36200,
1563		0x36208, 0x36240,
1564		0x36248, 0x36280,
1565		0x36288, 0x362c0,
1566		0x362c8, 0x362fc,
1567		0x36600, 0x36630,
1568		0x36a00, 0x36abc,
1569		0x36b00, 0x36b10,
1570		0x36b20, 0x36b30,
1571		0x36b40, 0x36b50,
1572		0x36b60, 0x36b70,
1573		0x37000, 0x37028,
1574		0x37030, 0x37048,
1575		0x37060, 0x37068,
1576		0x37070, 0x3709c,
1577		0x370f0, 0x37128,
1578		0x37130, 0x37148,
1579		0x37160, 0x37168,
1580		0x37170, 0x3719c,
1581		0x371f0, 0x37238,
1582		0x37240, 0x37240,
1583		0x37248, 0x37250,
1584		0x3725c, 0x37264,
1585		0x37270, 0x372b8,
1586		0x372c0, 0x372e4,
1587		0x372f8, 0x37338,
1588		0x37340, 0x37340,
1589		0x37348, 0x37350,
1590		0x3735c, 0x37364,
1591		0x37370, 0x373b8,
1592		0x373c0, 0x373e4,
1593		0x373f8, 0x37428,
1594		0x37430, 0x37448,
1595		0x37460, 0x37468,
1596		0x37470, 0x3749c,
1597		0x374f0, 0x37528,
1598		0x37530, 0x37548,
1599		0x37560, 0x37568,
1600		0x37570, 0x3759c,
1601		0x375f0, 0x37638,
1602		0x37640, 0x37640,
1603		0x37648, 0x37650,
1604		0x3765c, 0x37664,
1605		0x37670, 0x376b8,
1606		0x376c0, 0x376e4,
1607		0x376f8, 0x37738,
1608		0x37740, 0x37740,
1609		0x37748, 0x37750,
1610		0x3775c, 0x37764,
1611		0x37770, 0x377b8,
1612		0x377c0, 0x377e4,
1613		0x377f8, 0x377fc,
1614		0x37814, 0x37814,
1615		0x3782c, 0x3782c,
1616		0x37880, 0x3788c,
1617		0x378e8, 0x378ec,
1618		0x37900, 0x37928,
1619		0x37930, 0x37948,
1620		0x37960, 0x37968,
1621		0x37970, 0x3799c,
1622		0x379f0, 0x37a38,
1623		0x37a40, 0x37a40,
1624		0x37a48, 0x37a50,
1625		0x37a5c, 0x37a64,
1626		0x37a70, 0x37ab8,
1627		0x37ac0, 0x37ae4,
1628		0x37af8, 0x37b10,
1629		0x37b28, 0x37b28,
1630		0x37b3c, 0x37b50,
1631		0x37bf0, 0x37c10,
1632		0x37c28, 0x37c28,
1633		0x37c3c, 0x37c50,
1634		0x37cf0, 0x37cfc,
1635		0x38000, 0x38030,
1636		0x38038, 0x38038,
1637		0x38040, 0x38040,
1638		0x38100, 0x38144,
1639		0x38190, 0x381a0,
1640		0x381a8, 0x381b8,
1641		0x381c4, 0x381c8,
1642		0x381d0, 0x381d0,
1643		0x38200, 0x38318,
1644		0x38400, 0x384b4,
1645		0x384c0, 0x3852c,
1646		0x38540, 0x3861c,
1647		0x38800, 0x38828,
1648		0x38834, 0x38834,
1649		0x388c0, 0x38908,
1650		0x38910, 0x389ac,
1651		0x38a00, 0x38a14,
1652		0x38a1c, 0x38a2c,
1653		0x38a44, 0x38a50,
1654		0x38a74, 0x38a74,
1655		0x38a7c, 0x38afc,
1656		0x38b08, 0x38c24,
1657		0x38d00, 0x38d00,
1658		0x38d08, 0x38d14,
1659		0x38d1c, 0x38d20,
1660		0x38d3c, 0x38d3c,
1661		0x38d48, 0x38d50,
1662		0x39200, 0x3920c,
1663		0x39220, 0x39220,
1664		0x39240, 0x39240,
1665		0x39600, 0x3960c,
1666		0x39a00, 0x39a1c,
1667		0x39e00, 0x39e20,
1668		0x39e38, 0x39e3c,
1669		0x39e80, 0x39e80,
1670		0x39e88, 0x39ea8,
1671		0x39eb0, 0x39eb4,
1672		0x39ec8, 0x39ed4,
1673		0x39fb8, 0x3a004,
1674		0x3a200, 0x3a200,
1675		0x3a208, 0x3a240,
1676		0x3a248, 0x3a280,
1677		0x3a288, 0x3a2c0,
1678		0x3a2c8, 0x3a2fc,
1679		0x3a600, 0x3a630,
1680		0x3aa00, 0x3aabc,
1681		0x3ab00, 0x3ab10,
1682		0x3ab20, 0x3ab30,
1683		0x3ab40, 0x3ab50,
1684		0x3ab60, 0x3ab70,
1685		0x3b000, 0x3b028,
1686		0x3b030, 0x3b048,
1687		0x3b060, 0x3b068,
1688		0x3b070, 0x3b09c,
1689		0x3b0f0, 0x3b128,
1690		0x3b130, 0x3b148,
1691		0x3b160, 0x3b168,
1692		0x3b170, 0x3b19c,
1693		0x3b1f0, 0x3b238,
1694		0x3b240, 0x3b240,
1695		0x3b248, 0x3b250,
1696		0x3b25c, 0x3b264,
1697		0x3b270, 0x3b2b8,
1698		0x3b2c0, 0x3b2e4,
1699		0x3b2f8, 0x3b338,
1700		0x3b340, 0x3b340,
1701		0x3b348, 0x3b350,
1702		0x3b35c, 0x3b364,
1703		0x3b370, 0x3b3b8,
1704		0x3b3c0, 0x3b3e4,
1705		0x3b3f8, 0x3b428,
1706		0x3b430, 0x3b448,
1707		0x3b460, 0x3b468,
1708		0x3b470, 0x3b49c,
1709		0x3b4f0, 0x3b528,
1710		0x3b530, 0x3b548,
1711		0x3b560, 0x3b568,
1712		0x3b570, 0x3b59c,
1713		0x3b5f0, 0x3b638,
1714		0x3b640, 0x3b640,
1715		0x3b648, 0x3b650,
1716		0x3b65c, 0x3b664,
1717		0x3b670, 0x3b6b8,
1718		0x3b6c0, 0x3b6e4,
1719		0x3b6f8, 0x3b738,
1720		0x3b740, 0x3b740,
1721		0x3b748, 0x3b750,
1722		0x3b75c, 0x3b764,
1723		0x3b770, 0x3b7b8,
1724		0x3b7c0, 0x3b7e4,
1725		0x3b7f8, 0x3b7fc,
1726		0x3b814, 0x3b814,
1727		0x3b82c, 0x3b82c,
1728		0x3b880, 0x3b88c,
1729		0x3b8e8, 0x3b8ec,
1730		0x3b900, 0x3b928,
1731		0x3b930, 0x3b948,
1732		0x3b960, 0x3b968,
1733		0x3b970, 0x3b99c,
1734		0x3b9f0, 0x3ba38,
1735		0x3ba40, 0x3ba40,
1736		0x3ba48, 0x3ba50,
1737		0x3ba5c, 0x3ba64,
1738		0x3ba70, 0x3bab8,
1739		0x3bac0, 0x3bae4,
1740		0x3baf8, 0x3bb10,
1741		0x3bb28, 0x3bb28,
1742		0x3bb3c, 0x3bb50,
1743		0x3bbf0, 0x3bc10,
1744		0x3bc28, 0x3bc28,
1745		0x3bc3c, 0x3bc50,
1746		0x3bcf0, 0x3bcfc,
1747		0x3c000, 0x3c030,
1748		0x3c038, 0x3c038,
1749		0x3c040, 0x3c040,
1750		0x3c100, 0x3c144,
1751		0x3c190, 0x3c1a0,
1752		0x3c1a8, 0x3c1b8,
1753		0x3c1c4, 0x3c1c8,
1754		0x3c1d0, 0x3c1d0,
1755		0x3c200, 0x3c318,
1756		0x3c400, 0x3c4b4,
1757		0x3c4c0, 0x3c52c,
1758		0x3c540, 0x3c61c,
1759		0x3c800, 0x3c828,
1760		0x3c834, 0x3c834,
1761		0x3c8c0, 0x3c908,
1762		0x3c910, 0x3c9ac,
1763		0x3ca00, 0x3ca14,
1764		0x3ca1c, 0x3ca2c,
1765		0x3ca44, 0x3ca50,
1766		0x3ca74, 0x3ca74,
1767		0x3ca7c, 0x3cafc,
1768		0x3cb08, 0x3cc24,
1769		0x3cd00, 0x3cd00,
1770		0x3cd08, 0x3cd14,
1771		0x3cd1c, 0x3cd20,
1772		0x3cd3c, 0x3cd3c,
1773		0x3cd48, 0x3cd50,
1774		0x3d200, 0x3d20c,
1775		0x3d220, 0x3d220,
1776		0x3d240, 0x3d240,
1777		0x3d600, 0x3d60c,
1778		0x3da00, 0x3da1c,
1779		0x3de00, 0x3de20,
1780		0x3de38, 0x3de3c,
1781		0x3de80, 0x3de80,
1782		0x3de88, 0x3dea8,
1783		0x3deb0, 0x3deb4,
1784		0x3dec8, 0x3ded4,
1785		0x3dfb8, 0x3e004,
1786		0x3e200, 0x3e200,
1787		0x3e208, 0x3e240,
1788		0x3e248, 0x3e280,
1789		0x3e288, 0x3e2c0,
1790		0x3e2c8, 0x3e2fc,
1791		0x3e600, 0x3e630,
1792		0x3ea00, 0x3eabc,
1793		0x3eb00, 0x3eb10,
1794		0x3eb20, 0x3eb30,
1795		0x3eb40, 0x3eb50,
1796		0x3eb60, 0x3eb70,
1797		0x3f000, 0x3f028,
1798		0x3f030, 0x3f048,
1799		0x3f060, 0x3f068,
1800		0x3f070, 0x3f09c,
1801		0x3f0f0, 0x3f128,
1802		0x3f130, 0x3f148,
1803		0x3f160, 0x3f168,
1804		0x3f170, 0x3f19c,
1805		0x3f1f0, 0x3f238,
1806		0x3f240, 0x3f240,
1807		0x3f248, 0x3f250,
1808		0x3f25c, 0x3f264,
1809		0x3f270, 0x3f2b8,
1810		0x3f2c0, 0x3f2e4,
1811		0x3f2f8, 0x3f338,
1812		0x3f340, 0x3f340,
1813		0x3f348, 0x3f350,
1814		0x3f35c, 0x3f364,
1815		0x3f370, 0x3f3b8,
1816		0x3f3c0, 0x3f3e4,
1817		0x3f3f8, 0x3f428,
1818		0x3f430, 0x3f448,
1819		0x3f460, 0x3f468,
1820		0x3f470, 0x3f49c,
1821		0x3f4f0, 0x3f528,
1822		0x3f530, 0x3f548,
1823		0x3f560, 0x3f568,
1824		0x3f570, 0x3f59c,
1825		0x3f5f0, 0x3f638,
1826		0x3f640, 0x3f640,
1827		0x3f648, 0x3f650,
1828		0x3f65c, 0x3f664,
1829		0x3f670, 0x3f6b8,
1830		0x3f6c0, 0x3f6e4,
1831		0x3f6f8, 0x3f738,
1832		0x3f740, 0x3f740,
1833		0x3f748, 0x3f750,
1834		0x3f75c, 0x3f764,
1835		0x3f770, 0x3f7b8,
1836		0x3f7c0, 0x3f7e4,
1837		0x3f7f8, 0x3f7fc,
1838		0x3f814, 0x3f814,
1839		0x3f82c, 0x3f82c,
1840		0x3f880, 0x3f88c,
1841		0x3f8e8, 0x3f8ec,
1842		0x3f900, 0x3f928,
1843		0x3f930, 0x3f948,
1844		0x3f960, 0x3f968,
1845		0x3f970, 0x3f99c,
1846		0x3f9f0, 0x3fa38,
1847		0x3fa40, 0x3fa40,
1848		0x3fa48, 0x3fa50,
1849		0x3fa5c, 0x3fa64,
1850		0x3fa70, 0x3fab8,
1851		0x3fac0, 0x3fae4,
1852		0x3faf8, 0x3fb10,
1853		0x3fb28, 0x3fb28,
1854		0x3fb3c, 0x3fb50,
1855		0x3fbf0, 0x3fc10,
1856		0x3fc28, 0x3fc28,
1857		0x3fc3c, 0x3fc50,
1858		0x3fcf0, 0x3fcfc,
1859		0x40000, 0x4000c,
1860		0x40040, 0x40050,
1861		0x40060, 0x40068,
1862		0x4007c, 0x4008c,
1863		0x40094, 0x400b0,
1864		0x400c0, 0x40144,
1865		0x40180, 0x4018c,
1866		0x40200, 0x40254,
1867		0x40260, 0x40264,
1868		0x40270, 0x40288,
1869		0x40290, 0x40298,
1870		0x402ac, 0x402c8,
1871		0x402d0, 0x402e0,
1872		0x402f0, 0x402f0,
1873		0x40300, 0x4033c,
1874		0x403f8, 0x403fc,
1875		0x41304, 0x413c4,
1876		0x41400, 0x4140c,
1877		0x41414, 0x4141c,
1878		0x41480, 0x414d0,
1879		0x44000, 0x44054,
1880		0x4405c, 0x44078,
1881		0x440c0, 0x44174,
1882		0x44180, 0x441ac,
1883		0x441b4, 0x441b8,
1884		0x441c0, 0x44254,
1885		0x4425c, 0x44278,
1886		0x442c0, 0x44374,
1887		0x44380, 0x443ac,
1888		0x443b4, 0x443b8,
1889		0x443c0, 0x44454,
1890		0x4445c, 0x44478,
1891		0x444c0, 0x44574,
1892		0x44580, 0x445ac,
1893		0x445b4, 0x445b8,
1894		0x445c0, 0x44654,
1895		0x4465c, 0x44678,
1896		0x446c0, 0x44774,
1897		0x44780, 0x447ac,
1898		0x447b4, 0x447b8,
1899		0x447c0, 0x44854,
1900		0x4485c, 0x44878,
1901		0x448c0, 0x44974,
1902		0x44980, 0x449ac,
1903		0x449b4, 0x449b8,
1904		0x449c0, 0x449fc,
1905		0x45000, 0x45004,
1906		0x45010, 0x45030,
1907		0x45040, 0x45060,
1908		0x45068, 0x45068,
1909		0x45080, 0x45084,
1910		0x450a0, 0x450b0,
1911		0x45200, 0x45204,
1912		0x45210, 0x45230,
1913		0x45240, 0x45260,
1914		0x45268, 0x45268,
1915		0x45280, 0x45284,
1916		0x452a0, 0x452b0,
1917		0x460c0, 0x460e4,
1918		0x47000, 0x4703c,
1919		0x47044, 0x4708c,
1920		0x47200, 0x47250,
1921		0x47400, 0x47408,
1922		0x47414, 0x47420,
1923		0x47600, 0x47618,
1924		0x47800, 0x47814,
1925		0x48000, 0x4800c,
1926		0x48040, 0x48050,
1927		0x48060, 0x48068,
1928		0x4807c, 0x4808c,
1929		0x48094, 0x480b0,
1930		0x480c0, 0x48144,
1931		0x48180, 0x4818c,
1932		0x48200, 0x48254,
1933		0x48260, 0x48264,
1934		0x48270, 0x48288,
1935		0x48290, 0x48298,
1936		0x482ac, 0x482c8,
1937		0x482d0, 0x482e0,
1938		0x482f0, 0x482f0,
1939		0x48300, 0x4833c,
1940		0x483f8, 0x483fc,
1941		0x49304, 0x493c4,
1942		0x49400, 0x4940c,
1943		0x49414, 0x4941c,
1944		0x49480, 0x494d0,
1945		0x4c000, 0x4c054,
1946		0x4c05c, 0x4c078,
1947		0x4c0c0, 0x4c174,
1948		0x4c180, 0x4c1ac,
1949		0x4c1b4, 0x4c1b8,
1950		0x4c1c0, 0x4c254,
1951		0x4c25c, 0x4c278,
1952		0x4c2c0, 0x4c374,
1953		0x4c380, 0x4c3ac,
1954		0x4c3b4, 0x4c3b8,
1955		0x4c3c0, 0x4c454,
1956		0x4c45c, 0x4c478,
1957		0x4c4c0, 0x4c574,
1958		0x4c580, 0x4c5ac,
1959		0x4c5b4, 0x4c5b8,
1960		0x4c5c0, 0x4c654,
1961		0x4c65c, 0x4c678,
1962		0x4c6c0, 0x4c774,
1963		0x4c780, 0x4c7ac,
1964		0x4c7b4, 0x4c7b8,
1965		0x4c7c0, 0x4c854,
1966		0x4c85c, 0x4c878,
1967		0x4c8c0, 0x4c974,
1968		0x4c980, 0x4c9ac,
1969		0x4c9b4, 0x4c9b8,
1970		0x4c9c0, 0x4c9fc,
1971		0x4d000, 0x4d004,
1972		0x4d010, 0x4d030,
1973		0x4d040, 0x4d060,
1974		0x4d068, 0x4d068,
1975		0x4d080, 0x4d084,
1976		0x4d0a0, 0x4d0b0,
1977		0x4d200, 0x4d204,
1978		0x4d210, 0x4d230,
1979		0x4d240, 0x4d260,
1980		0x4d268, 0x4d268,
1981		0x4d280, 0x4d284,
1982		0x4d2a0, 0x4d2b0,
1983		0x4e0c0, 0x4e0e4,
1984		0x4f000, 0x4f03c,
1985		0x4f044, 0x4f08c,
1986		0x4f200, 0x4f250,
1987		0x4f400, 0x4f408,
1988		0x4f414, 0x4f420,
1989		0x4f600, 0x4f618,
1990		0x4f800, 0x4f814,
1991		0x50000, 0x50084,
1992		0x50090, 0x500cc,
1993		0x50400, 0x50400,
1994		0x50800, 0x50884,
1995		0x50890, 0x508cc,
1996		0x50c00, 0x50c00,
1997		0x51000, 0x5101c,
1998		0x51300, 0x51308,
1999	};
2000
2001	static const unsigned int t5vf_reg_ranges[] = {
2002		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2003		VF_MPS_REG(A_MPS_VF_CTL),
2004		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2005		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2006		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2007		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2008		FW_T4VF_MBDATA_BASE_ADDR,
2009		FW_T4VF_MBDATA_BASE_ADDR +
2010		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2011	};
2012
2013	static const unsigned int t6_reg_ranges[] = {
2014		0x1008, 0x101c,
2015		0x1024, 0x10a8,
2016		0x10b4, 0x10f8,
2017		0x1100, 0x1114,
2018		0x111c, 0x112c,
2019		0x1138, 0x113c,
2020		0x1144, 0x114c,
2021		0x1180, 0x1184,
2022		0x1190, 0x1194,
2023		0x11a0, 0x11a4,
2024		0x11b0, 0x11b4,
2025		0x11fc, 0x1274,
2026		0x1280, 0x133c,
2027		0x1800, 0x18fc,
2028		0x3000, 0x302c,
2029		0x3060, 0x30b0,
2030		0x30b8, 0x30d8,
2031		0x30e0, 0x30fc,
2032		0x3140, 0x357c,
2033		0x35a8, 0x35cc,
2034		0x35ec, 0x35ec,
2035		0x3600, 0x5624,
2036		0x56cc, 0x56ec,
2037		0x56f4, 0x5720,
2038		0x5728, 0x575c,
2039		0x580c, 0x5814,
2040		0x5890, 0x589c,
2041		0x58a4, 0x58ac,
2042		0x58b8, 0x58bc,
2043		0x5940, 0x595c,
2044		0x5980, 0x598c,
2045		0x59b0, 0x59c8,
2046		0x59d0, 0x59dc,
2047		0x59fc, 0x5a18,
2048		0x5a60, 0x5a6c,
2049		0x5a80, 0x5a8c,
2050		0x5a94, 0x5a9c,
2051		0x5b94, 0x5bfc,
2052		0x5c10, 0x5e48,
2053		0x5e50, 0x5e94,
2054		0x5ea0, 0x5eb0,
2055		0x5ec0, 0x5ec0,
2056		0x5ec8, 0x5ed0,
2057		0x5ee0, 0x5ee0,
2058		0x5ef0, 0x5ef0,
2059		0x5f00, 0x5f00,
2060		0x6000, 0x6020,
2061		0x6028, 0x6040,
2062		0x6058, 0x609c,
2063		0x60a8, 0x619c,
2064		0x7700, 0x7798,
2065		0x77c0, 0x7880,
2066		0x78cc, 0x78fc,
2067		0x7b00, 0x7b58,
2068		0x7b60, 0x7b84,
2069		0x7b8c, 0x7c54,
2070		0x7d00, 0x7d38,
2071		0x7d40, 0x7d84,
2072		0x7d8c, 0x7ddc,
2073		0x7de4, 0x7e04,
2074		0x7e10, 0x7e1c,
2075		0x7e24, 0x7e38,
2076		0x7e40, 0x7e44,
2077		0x7e4c, 0x7e78,
2078		0x7e80, 0x7edc,
2079		0x7ee8, 0x7efc,
2080		0x8dc0, 0x8de4,
2081		0x8df8, 0x8e04,
2082		0x8e10, 0x8e84,
2083		0x8ea0, 0x8f88,
2084		0x8fb8, 0x9058,
2085		0x9060, 0x9060,
2086		0x9068, 0x90f8,
2087		0x9100, 0x9124,
2088		0x9400, 0x9470,
2089		0x9600, 0x9600,
2090		0x9608, 0x9638,
2091		0x9640, 0x9704,
2092		0x9710, 0x971c,
2093		0x9800, 0x9808,
2094		0x9820, 0x983c,
2095		0x9850, 0x9864,
2096		0x9c00, 0x9c6c,
2097		0x9c80, 0x9cec,
2098		0x9d00, 0x9d6c,
2099		0x9d80, 0x9dec,
2100		0x9e00, 0x9e6c,
2101		0x9e80, 0x9eec,
2102		0x9f00, 0x9f6c,
2103		0x9f80, 0xa020,
2104		0xd004, 0xd03c,
2105		0xd100, 0xd118,
2106		0xd200, 0xd214,
2107		0xd220, 0xd234,
2108		0xd240, 0xd254,
2109		0xd260, 0xd274,
2110		0xd280, 0xd294,
2111		0xd2a0, 0xd2b4,
2112		0xd2c0, 0xd2d4,
2113		0xd2e0, 0xd2f4,
2114		0xd300, 0xd31c,
2115		0xdfc0, 0xdfe0,
2116		0xe000, 0xf008,
2117		0xf010, 0xf018,
2118		0xf020, 0xf028,
2119		0x11000, 0x11014,
2120		0x11048, 0x1106c,
2121		0x11074, 0x11088,
2122		0x11098, 0x11120,
2123		0x1112c, 0x1117c,
2124		0x11190, 0x112e0,
2125		0x11300, 0x1130c,
2126		0x12000, 0x1206c,
2127		0x19040, 0x1906c,
2128		0x19078, 0x19080,
2129		0x1908c, 0x190e8,
2130		0x190f0, 0x190f8,
2131		0x19100, 0x19110,
2132		0x19120, 0x19124,
2133		0x19150, 0x19194,
2134		0x1919c, 0x191b0,
2135		0x191d0, 0x191e8,
2136		0x19238, 0x19290,
2137		0x192a4, 0x192b0,
2138		0x192bc, 0x192bc,
2139		0x19348, 0x1934c,
2140		0x193f8, 0x19418,
2141		0x19420, 0x19428,
2142		0x19430, 0x19444,
2143		0x1944c, 0x1946c,
2144		0x19474, 0x19474,
2145		0x19490, 0x194cc,
2146		0x194f0, 0x194f8,
2147		0x19c00, 0x19c48,
2148		0x19c50, 0x19c80,
2149		0x19c94, 0x19c98,
2150		0x19ca0, 0x19cbc,
2151		0x19ce4, 0x19ce4,
2152		0x19cf0, 0x19cf8,
2153		0x19d00, 0x19d28,
2154		0x19d50, 0x19d78,
2155		0x19d94, 0x19d98,
2156		0x19da0, 0x19dc8,
2157		0x19df0, 0x19e10,
2158		0x19e50, 0x19e6c,
2159		0x19ea0, 0x19ebc,
2160		0x19ec4, 0x19ef4,
2161		0x19f04, 0x19f2c,
2162		0x19f34, 0x19f34,
2163		0x19f40, 0x19f50,
2164		0x19f90, 0x19fac,
2165		0x19fc4, 0x19fc8,
2166		0x19fd0, 0x19fe4,
2167		0x1a000, 0x1a004,
2168		0x1a010, 0x1a06c,
2169		0x1a0b0, 0x1a0e4,
2170		0x1a0ec, 0x1a0f8,
2171		0x1a100, 0x1a108,
2172		0x1a114, 0x1a120,
2173		0x1a128, 0x1a130,
2174		0x1a138, 0x1a138,
2175		0x1a190, 0x1a1c4,
2176		0x1a1fc, 0x1a1fc,
2177		0x1e008, 0x1e00c,
2178		0x1e040, 0x1e044,
2179		0x1e04c, 0x1e04c,
2180		0x1e284, 0x1e290,
2181		0x1e2c0, 0x1e2c0,
2182		0x1e2e0, 0x1e2e0,
2183		0x1e300, 0x1e384,
2184		0x1e3c0, 0x1e3c8,
2185		0x1e408, 0x1e40c,
2186		0x1e440, 0x1e444,
2187		0x1e44c, 0x1e44c,
2188		0x1e684, 0x1e690,
2189		0x1e6c0, 0x1e6c0,
2190		0x1e6e0, 0x1e6e0,
2191		0x1e700, 0x1e784,
2192		0x1e7c0, 0x1e7c8,
2193		0x1e808, 0x1e80c,
2194		0x1e840, 0x1e844,
2195		0x1e84c, 0x1e84c,
2196		0x1ea84, 0x1ea90,
2197		0x1eac0, 0x1eac0,
2198		0x1eae0, 0x1eae0,
2199		0x1eb00, 0x1eb84,
2200		0x1ebc0, 0x1ebc8,
2201		0x1ec08, 0x1ec0c,
2202		0x1ec40, 0x1ec44,
2203		0x1ec4c, 0x1ec4c,
2204		0x1ee84, 0x1ee90,
2205		0x1eec0, 0x1eec0,
2206		0x1eee0, 0x1eee0,
2207		0x1ef00, 0x1ef84,
2208		0x1efc0, 0x1efc8,
2209		0x1f008, 0x1f00c,
2210		0x1f040, 0x1f044,
2211		0x1f04c, 0x1f04c,
2212		0x1f284, 0x1f290,
2213		0x1f2c0, 0x1f2c0,
2214		0x1f2e0, 0x1f2e0,
2215		0x1f300, 0x1f384,
2216		0x1f3c0, 0x1f3c8,
2217		0x1f408, 0x1f40c,
2218		0x1f440, 0x1f444,
2219		0x1f44c, 0x1f44c,
2220		0x1f684, 0x1f690,
2221		0x1f6c0, 0x1f6c0,
2222		0x1f6e0, 0x1f6e0,
2223		0x1f700, 0x1f784,
2224		0x1f7c0, 0x1f7c8,
2225		0x1f808, 0x1f80c,
2226		0x1f840, 0x1f844,
2227		0x1f84c, 0x1f84c,
2228		0x1fa84, 0x1fa90,
2229		0x1fac0, 0x1fac0,
2230		0x1fae0, 0x1fae0,
2231		0x1fb00, 0x1fb84,
2232		0x1fbc0, 0x1fbc8,
2233		0x1fc08, 0x1fc0c,
2234		0x1fc40, 0x1fc44,
2235		0x1fc4c, 0x1fc4c,
2236		0x1fe84, 0x1fe90,
2237		0x1fec0, 0x1fec0,
2238		0x1fee0, 0x1fee0,
2239		0x1ff00, 0x1ff84,
2240		0x1ffc0, 0x1ffc8,
2241		0x30000, 0x30030,
2242		0x30038, 0x30038,
2243		0x30040, 0x30040,
2244		0x30048, 0x30048,
2245		0x30050, 0x30050,
2246		0x3005c, 0x30060,
2247		0x30068, 0x30068,
2248		0x30070, 0x30070,
2249		0x30100, 0x30168,
2250		0x30190, 0x301a0,
2251		0x301a8, 0x301b8,
2252		0x301c4, 0x301c8,
2253		0x301d0, 0x301d0,
2254		0x30200, 0x30320,
2255		0x30400, 0x304b4,
2256		0x304c0, 0x3052c,
2257		0x30540, 0x3061c,
2258		0x30800, 0x308a0,
2259		0x308c0, 0x30908,
2260		0x30910, 0x309b8,
2261		0x30a00, 0x30a04,
2262		0x30a0c, 0x30a14,
2263		0x30a1c, 0x30a2c,
2264		0x30a44, 0x30a50,
2265		0x30a74, 0x30a74,
2266		0x30a7c, 0x30afc,
2267		0x30b08, 0x30c24,
2268		0x30d00, 0x30d14,
2269		0x30d1c, 0x30d3c,
2270		0x30d44, 0x30d4c,
2271		0x30d54, 0x30d74,
2272		0x30d7c, 0x30d7c,
2273		0x30de0, 0x30de0,
2274		0x30e00, 0x30ed4,
2275		0x30f00, 0x30fa4,
2276		0x30fc0, 0x30fc4,
2277		0x31000, 0x31004,
2278		0x31080, 0x310fc,
2279		0x31208, 0x31220,
2280		0x3123c, 0x31254,
2281		0x31300, 0x31300,
2282		0x31308, 0x3131c,
2283		0x31338, 0x3133c,
2284		0x31380, 0x31380,
2285		0x31388, 0x313a8,
2286		0x313b4, 0x313b4,
2287		0x31400, 0x31420,
2288		0x31438, 0x3143c,
2289		0x31480, 0x31480,
2290		0x314a8, 0x314a8,
2291		0x314b0, 0x314b4,
2292		0x314c8, 0x314d4,
2293		0x31a40, 0x31a4c,
2294		0x31af0, 0x31b20,
2295		0x31b38, 0x31b3c,
2296		0x31b80, 0x31b80,
2297		0x31ba8, 0x31ba8,
2298		0x31bb0, 0x31bb4,
2299		0x31bc8, 0x31bd4,
2300		0x32140, 0x3218c,
2301		0x321f0, 0x321f4,
2302		0x32200, 0x32200,
2303		0x32218, 0x32218,
2304		0x32400, 0x32400,
2305		0x32408, 0x3241c,
2306		0x32618, 0x32620,
2307		0x32664, 0x32664,
2308		0x326a8, 0x326a8,
2309		0x326ec, 0x326ec,
2310		0x32a00, 0x32abc,
2311		0x32b00, 0x32b38,
2312		0x32b40, 0x32b58,
2313		0x32b60, 0x32b78,
2314		0x32c00, 0x32c00,
2315		0x32c08, 0x32c3c,
2316		0x32e00, 0x32e2c,
2317		0x32f00, 0x32f2c,
2318		0x33000, 0x3302c,
2319		0x33034, 0x33050,
2320		0x33058, 0x33058,
2321		0x33060, 0x3308c,
2322		0x3309c, 0x330ac,
2323		0x330c0, 0x330c0,
2324		0x330c8, 0x330d0,
2325		0x330d8, 0x330e0,
2326		0x330ec, 0x3312c,
2327		0x33134, 0x33150,
2328		0x33158, 0x33158,
2329		0x33160, 0x3318c,
2330		0x3319c, 0x331ac,
2331		0x331c0, 0x331c0,
2332		0x331c8, 0x331d0,
2333		0x331d8, 0x331e0,
2334		0x331ec, 0x33290,
2335		0x33298, 0x332c4,
2336		0x332e4, 0x33390,
2337		0x33398, 0x333c4,
2338		0x333e4, 0x3342c,
2339		0x33434, 0x33450,
2340		0x33458, 0x33458,
2341		0x33460, 0x3348c,
2342		0x3349c, 0x334ac,
2343		0x334c0, 0x334c0,
2344		0x334c8, 0x334d0,
2345		0x334d8, 0x334e0,
2346		0x334ec, 0x3352c,
2347		0x33534, 0x33550,
2348		0x33558, 0x33558,
2349		0x33560, 0x3358c,
2350		0x3359c, 0x335ac,
2351		0x335c0, 0x335c0,
2352		0x335c8, 0x335d0,
2353		0x335d8, 0x335e0,
2354		0x335ec, 0x33690,
2355		0x33698, 0x336c4,
2356		0x336e4, 0x33790,
2357		0x33798, 0x337c4,
2358		0x337e4, 0x337fc,
2359		0x33814, 0x33814,
2360		0x33854, 0x33868,
2361		0x33880, 0x3388c,
2362		0x338c0, 0x338d0,
2363		0x338e8, 0x338ec,
2364		0x33900, 0x3392c,
2365		0x33934, 0x33950,
2366		0x33958, 0x33958,
2367		0x33960, 0x3398c,
2368		0x3399c, 0x339ac,
2369		0x339c0, 0x339c0,
2370		0x339c8, 0x339d0,
2371		0x339d8, 0x339e0,
2372		0x339ec, 0x33a90,
2373		0x33a98, 0x33ac4,
2374		0x33ae4, 0x33b10,
2375		0x33b24, 0x33b28,
2376		0x33b38, 0x33b50,
2377		0x33bf0, 0x33c10,
2378		0x33c24, 0x33c28,
2379		0x33c38, 0x33c50,
2380		0x33cf0, 0x33cfc,
2381		0x34000, 0x34030,
2382		0x34038, 0x34038,
2383		0x34040, 0x34040,
2384		0x34048, 0x34048,
2385		0x34050, 0x34050,
2386		0x3405c, 0x34060,
2387		0x34068, 0x34068,
2388		0x34070, 0x34070,
2389		0x34100, 0x34168,
2390		0x34190, 0x341a0,
2391		0x341a8, 0x341b8,
2392		0x341c4, 0x341c8,
2393		0x341d0, 0x341d0,
2394		0x34200, 0x34320,
2395		0x34400, 0x344b4,
2396		0x344c0, 0x3452c,
2397		0x34540, 0x3461c,
2398		0x34800, 0x348a0,
2399		0x348c0, 0x34908,
2400		0x34910, 0x349b8,
2401		0x34a00, 0x34a04,
2402		0x34a0c, 0x34a14,
2403		0x34a1c, 0x34a2c,
2404		0x34a44, 0x34a50,
2405		0x34a74, 0x34a74,
2406		0x34a7c, 0x34afc,
2407		0x34b08, 0x34c24,
2408		0x34d00, 0x34d14,
2409		0x34d1c, 0x34d3c,
2410		0x34d44, 0x34d4c,
2411		0x34d54, 0x34d74,
2412		0x34d7c, 0x34d7c,
2413		0x34de0, 0x34de0,
2414		0x34e00, 0x34ed4,
2415		0x34f00, 0x34fa4,
2416		0x34fc0, 0x34fc4,
2417		0x35000, 0x35004,
2418		0x35080, 0x350fc,
2419		0x35208, 0x35220,
2420		0x3523c, 0x35254,
2421		0x35300, 0x35300,
2422		0x35308, 0x3531c,
2423		0x35338, 0x3533c,
2424		0x35380, 0x35380,
2425		0x35388, 0x353a8,
2426		0x353b4, 0x353b4,
2427		0x35400, 0x35420,
2428		0x35438, 0x3543c,
2429		0x35480, 0x35480,
2430		0x354a8, 0x354a8,
2431		0x354b0, 0x354b4,
2432		0x354c8, 0x354d4,
2433		0x35a40, 0x35a4c,
2434		0x35af0, 0x35b20,
2435		0x35b38, 0x35b3c,
2436		0x35b80, 0x35b80,
2437		0x35ba8, 0x35ba8,
2438		0x35bb0, 0x35bb4,
2439		0x35bc8, 0x35bd4,
2440		0x36140, 0x3618c,
2441		0x361f0, 0x361f4,
2442		0x36200, 0x36200,
2443		0x36218, 0x36218,
2444		0x36400, 0x36400,
2445		0x36408, 0x3641c,
2446		0x36618, 0x36620,
2447		0x36664, 0x36664,
2448		0x366a8, 0x366a8,
2449		0x366ec, 0x366ec,
2450		0x36a00, 0x36abc,
2451		0x36b00, 0x36b38,
2452		0x36b40, 0x36b58,
2453		0x36b60, 0x36b78,
2454		0x36c00, 0x36c00,
2455		0x36c08, 0x36c3c,
2456		0x36e00, 0x36e2c,
2457		0x36f00, 0x36f2c,
2458		0x37000, 0x3702c,
2459		0x37034, 0x37050,
2460		0x37058, 0x37058,
2461		0x37060, 0x3708c,
2462		0x3709c, 0x370ac,
2463		0x370c0, 0x370c0,
2464		0x370c8, 0x370d0,
2465		0x370d8, 0x370e0,
2466		0x370ec, 0x3712c,
2467		0x37134, 0x37150,
2468		0x37158, 0x37158,
2469		0x37160, 0x3718c,
2470		0x3719c, 0x371ac,
2471		0x371c0, 0x371c0,
2472		0x371c8, 0x371d0,
2473		0x371d8, 0x371e0,
2474		0x371ec, 0x37290,
2475		0x37298, 0x372c4,
2476		0x372e4, 0x37390,
2477		0x37398, 0x373c4,
2478		0x373e4, 0x3742c,
2479		0x37434, 0x37450,
2480		0x37458, 0x37458,
2481		0x37460, 0x3748c,
2482		0x3749c, 0x374ac,
2483		0x374c0, 0x374c0,
2484		0x374c8, 0x374d0,
2485		0x374d8, 0x374e0,
2486		0x374ec, 0x3752c,
2487		0x37534, 0x37550,
2488		0x37558, 0x37558,
2489		0x37560, 0x3758c,
2490		0x3759c, 0x375ac,
2491		0x375c0, 0x375c0,
2492		0x375c8, 0x375d0,
2493		0x375d8, 0x375e0,
2494		0x375ec, 0x37690,
2495		0x37698, 0x376c4,
2496		0x376e4, 0x37790,
2497		0x37798, 0x377c4,
2498		0x377e4, 0x377fc,
2499		0x37814, 0x37814,
2500		0x37854, 0x37868,
2501		0x37880, 0x3788c,
2502		0x378c0, 0x378d0,
2503		0x378e8, 0x378ec,
2504		0x37900, 0x3792c,
2505		0x37934, 0x37950,
2506		0x37958, 0x37958,
2507		0x37960, 0x3798c,
2508		0x3799c, 0x379ac,
2509		0x379c0, 0x379c0,
2510		0x379c8, 0x379d0,
2511		0x379d8, 0x379e0,
2512		0x379ec, 0x37a90,
2513		0x37a98, 0x37ac4,
2514		0x37ae4, 0x37b10,
2515		0x37b24, 0x37b28,
2516		0x37b38, 0x37b50,
2517		0x37bf0, 0x37c10,
2518		0x37c24, 0x37c28,
2519		0x37c38, 0x37c50,
2520		0x37cf0, 0x37cfc,
2521		0x40040, 0x40040,
2522		0x40080, 0x40084,
2523		0x40100, 0x40100,
2524		0x40140, 0x401bc,
2525		0x40200, 0x40214,
2526		0x40228, 0x40228,
2527		0x40240, 0x40258,
2528		0x40280, 0x40280,
2529		0x40304, 0x40304,
2530		0x40330, 0x4033c,
2531		0x41304, 0x413c8,
2532		0x413d0, 0x413dc,
2533		0x413f0, 0x413f0,
2534		0x41400, 0x4140c,
2535		0x41414, 0x4141c,
2536		0x41480, 0x414d0,
2537		0x44000, 0x4407c,
2538		0x440c0, 0x441ac,
2539		0x441b4, 0x4427c,
2540		0x442c0, 0x443ac,
2541		0x443b4, 0x4447c,
2542		0x444c0, 0x445ac,
2543		0x445b4, 0x4467c,
2544		0x446c0, 0x447ac,
2545		0x447b4, 0x4487c,
2546		0x448c0, 0x449ac,
2547		0x449b4, 0x44a7c,
2548		0x44ac0, 0x44bac,
2549		0x44bb4, 0x44c7c,
2550		0x44cc0, 0x44dac,
2551		0x44db4, 0x44e7c,
2552		0x44ec0, 0x44fac,
2553		0x44fb4, 0x4507c,
2554		0x450c0, 0x451ac,
2555		0x451b4, 0x451fc,
2556		0x45800, 0x45804,
2557		0x45810, 0x45830,
2558		0x45840, 0x45860,
2559		0x45868, 0x45868,
2560		0x45880, 0x45884,
2561		0x458a0, 0x458b0,
2562		0x45a00, 0x45a04,
2563		0x45a10, 0x45a30,
2564		0x45a40, 0x45a60,
2565		0x45a68, 0x45a68,
2566		0x45a80, 0x45a84,
2567		0x45aa0, 0x45ab0,
2568		0x460c0, 0x460e4,
2569		0x47000, 0x4703c,
2570		0x47044, 0x4708c,
2571		0x47200, 0x47250,
2572		0x47400, 0x47408,
2573		0x47414, 0x47420,
2574		0x47600, 0x47618,
2575		0x47800, 0x47814,
2576		0x47820, 0x4782c,
2577		0x50000, 0x50084,
2578		0x50090, 0x500cc,
2579		0x50300, 0x50384,
2580		0x50400, 0x50400,
2581		0x50800, 0x50884,
2582		0x50890, 0x508cc,
2583		0x50b00, 0x50b84,
2584		0x50c00, 0x50c00,
2585		0x51000, 0x51020,
2586		0x51028, 0x510b0,
2587		0x51300, 0x51324,
2588	};
2589
2590	static const unsigned int t6vf_reg_ranges[] = {
2591		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2592		VF_MPS_REG(A_MPS_VF_CTL),
2593		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2594		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2595		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2596		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2597		FW_T6VF_MBDATA_BASE_ADDR,
2598		FW_T6VF_MBDATA_BASE_ADDR +
2599		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2600	};
2601
2602	u32 *buf_end = (u32 *)(buf + buf_size);
2603	const unsigned int *reg_ranges;
2604	int reg_ranges_size, range;
2605	unsigned int chip_version = chip_id(adap);
2606
2607	/*
2608	 * Select the right set of register ranges to dump depending on the
2609	 * adapter chip type.
2610	 */
2611	switch (chip_version) {
2612	case CHELSIO_T4:
2613		if (adap->flags & IS_VF) {
2614			reg_ranges = t4vf_reg_ranges;
2615			reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2616		} else {
2617			reg_ranges = t4_reg_ranges;
2618			reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2619		}
2620		break;
2621
2622	case CHELSIO_T5:
2623		if (adap->flags & IS_VF) {
2624			reg_ranges = t5vf_reg_ranges;
2625			reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2626		} else {
2627			reg_ranges = t5_reg_ranges;
2628			reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2629		}
2630		break;
2631
2632	case CHELSIO_T6:
2633		if (adap->flags & IS_VF) {
2634			reg_ranges = t6vf_reg_ranges;
2635			reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2636		} else {
2637			reg_ranges = t6_reg_ranges;
2638			reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2639		}
2640		break;
2641
2642	default:
2643		CH_ERR(adap,
2644			"Unsupported chip version %d\n", chip_version);
2645		return;
2646	}
2647
2648	/*
2649	 * Clear the register buffer and insert the appropriate register
2650	 * values selected by the above register ranges.
2651	 */
2652	memset(buf, 0, buf_size);
2653	for (range = 0; range < reg_ranges_size; range += 2) {
2654		unsigned int reg = reg_ranges[range];
2655		unsigned int last_reg = reg_ranges[range + 1];
2656		u32 *bufp = (u32 *)(buf + reg);
2657
2658		/*
2659		 * Iterate across the register range filling in the register
2660		 * buffer but don't write past the end of the register buffer.
2661		 */
2662		while (reg <= last_reg && bufp < buf_end) {
2663			*bufp++ = t4_read_reg(adap, reg);
2664			reg += sizeof(u32);
2665		}
2666	}
2667}
2668
2669/*
2670 * Partial EEPROM Vital Product Data structure.  Includes only the ID and
2671 * VPD-R sections.
2672 */
2673struct t4_vpd_hdr {
2674	u8  id_tag;
2675	u8  id_len[2];
2676	u8  id_data[ID_LEN];
2677	u8  vpdr_tag;
2678	u8  vpdr_len[2];
2679};
2680
2681/*
2682 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2683 */
2684#define EEPROM_DELAY		10		/* 10us per poll spin */
2685#define EEPROM_MAX_POLL		5000		/* x 5000 == 50ms */
2686
2687#define EEPROM_STAT_ADDR	0x7bfc
2688#define VPD_BASE		0x400
2689#define VPD_BASE_OLD		0
2690#define VPD_LEN			1024
2691#define VPD_INFO_FLD_HDR_SIZE	3
2692#define CHELSIO_VPD_UNIQUE_ID	0x82
2693
2694/*
2695 * Small utility function to wait till any outstanding VPD Access is complete.
2696 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2697 * VPD Access in flight.  This allows us to handle the problem of having a
2698 * previous VPD Access time out and prevent an attempt to inject a new VPD
2699 * Request before any in-flight VPD reguest has completed.
2700 */
2701static int t4_seeprom_wait(struct adapter *adapter)
2702{
2703	unsigned int base = adapter->params.pci.vpd_cap_addr;
2704	int max_poll;
2705
2706	/*
2707	 * If no VPD Access is in flight, we can just return success right
2708	 * away.
2709	 */
2710	if (!adapter->vpd_busy)
2711		return 0;
2712
2713	/*
2714	 * Poll the VPD Capability Address/Flag register waiting for it
2715	 * to indicate that the operation is complete.
2716	 */
2717	max_poll = EEPROM_MAX_POLL;
2718	do {
2719		u16 val;
2720
2721		udelay(EEPROM_DELAY);
2722		t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2723
2724		/*
2725		 * If the operation is complete, mark the VPD as no longer
2726		 * busy and return success.
2727		 */
2728		if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2729			adapter->vpd_busy = 0;
2730			return 0;
2731		}
2732	} while (--max_poll);
2733
2734	/*
2735	 * Failure!  Note that we leave the VPD Busy status set in order to
2736	 * avoid pushing a new VPD Access request into the VPD Capability till
2737	 * the current operation eventually succeeds.  It's a bug to issue a
2738	 * new request when an existing request is in flight and will result
2739	 * in corrupt hardware state.
2740	 */
2741	return -ETIMEDOUT;
2742}
2743
2744/**
2745 *	t4_seeprom_read - read a serial EEPROM location
2746 *	@adapter: adapter to read
2747 *	@addr: EEPROM virtual address
2748 *	@data: where to store the read data
2749 *
2750 *	Read a 32-bit word from a location in serial EEPROM using the card's PCI
2751 *	VPD capability.  Note that this function must be called with a virtual
2752 *	address.
2753 */
2754int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2755{
2756	unsigned int base = adapter->params.pci.vpd_cap_addr;
2757	int ret;
2758
2759	/*
2760	 * VPD Accesses must alway be 4-byte aligned!
2761	 */
2762	if (addr >= EEPROMVSIZE || (addr & 3))
2763		return -EINVAL;
2764
2765	/*
2766	 * Wait for any previous operation which may still be in flight to
2767	 * complete.
2768	 */
2769	ret = t4_seeprom_wait(adapter);
2770	if (ret) {
2771		CH_ERR(adapter, "VPD still busy from previous operation\n");
2772		return ret;
2773	}
2774
2775	/*
2776	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2777	 * for our request to complete.  If it doesn't complete, note the
2778	 * error and return it to our caller.  Note that we do not reset the
2779	 * VPD Busy status!
2780	 */
2781	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2782	adapter->vpd_busy = 1;
2783	adapter->vpd_flag = PCI_VPD_ADDR_F;
2784	ret = t4_seeprom_wait(adapter);
2785	if (ret) {
2786		CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2787		return ret;
2788	}
2789
2790	/*
2791	 * Grab the returned data, swizzle it into our endianness and
2792	 * return success.
2793	 */
2794	t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2795	*data = le32_to_cpu(*data);
2796	return 0;
2797}
2798
2799/**
2800 *	t4_seeprom_write - write a serial EEPROM location
2801 *	@adapter: adapter to write
2802 *	@addr: virtual EEPROM address
2803 *	@data: value to write
2804 *
2805 *	Write a 32-bit word to a location in serial EEPROM using the card's PCI
2806 *	VPD capability.  Note that this function must be called with a virtual
2807 *	address.
2808 */
2809int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2810{
2811	unsigned int base = adapter->params.pci.vpd_cap_addr;
2812	int ret;
2813	u32 stats_reg;
2814	int max_poll;
2815
2816	/*
2817	 * VPD Accesses must alway be 4-byte aligned!
2818	 */
2819	if (addr >= EEPROMVSIZE || (addr & 3))
2820		return -EINVAL;
2821
2822	/*
2823	 * Wait for any previous operation which may still be in flight to
2824	 * complete.
2825	 */
2826	ret = t4_seeprom_wait(adapter);
2827	if (ret) {
2828		CH_ERR(adapter, "VPD still busy from previous operation\n");
2829		return ret;
2830	}
2831
2832	/*
2833	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2834	 * for our request to complete.  If it doesn't complete, note the
2835	 * error and return it to our caller.  Note that we do not reset the
2836	 * VPD Busy status!
2837	 */
2838	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2839				 cpu_to_le32(data));
2840	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2841				 (u16)addr | PCI_VPD_ADDR_F);
2842	adapter->vpd_busy = 1;
2843	adapter->vpd_flag = 0;
2844	ret = t4_seeprom_wait(adapter);
2845	if (ret) {
2846		CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2847		return ret;
2848	}
2849
2850	/*
2851	 * Reset PCI_VPD_DATA register after a transaction and wait for our
2852	 * request to complete. If it doesn't complete, return error.
2853	 */
2854	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2855	max_poll = EEPROM_MAX_POLL;
2856	do {
2857		udelay(EEPROM_DELAY);
2858		t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2859	} while ((stats_reg & 0x1) && --max_poll);
2860	if (!max_poll)
2861		return -ETIMEDOUT;
2862
2863	/* Return success! */
2864	return 0;
2865}
2866
2867/**
2868 *	t4_eeprom_ptov - translate a physical EEPROM address to virtual
2869 *	@phys_addr: the physical EEPROM address
2870 *	@fn: the PCI function number
2871 *	@sz: size of function-specific area
2872 *
2873 *	Translate a physical EEPROM address to virtual.  The first 1K is
2874 *	accessed through virtual addresses starting at 31K, the rest is
2875 *	accessed through virtual addresses starting at 0.
2876 *
2877 *	The mapping is as follows:
2878 *	[0..1K) -> [31K..32K)
2879 *	[1K..1K+A) -> [ES-A..ES)
2880 *	[1K+A..ES) -> [0..ES-A-1K)
2881 *
2882 *	where A = @fn * @sz, and ES = EEPROM size.
2883 */
2884int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2885{
2886	fn *= sz;
2887	if (phys_addr < 1024)
2888		return phys_addr + (31 << 10);
2889	if (phys_addr < 1024 + fn)
2890		return EEPROMSIZE - fn + phys_addr - 1024;
2891	if (phys_addr < EEPROMSIZE)
2892		return phys_addr - 1024 - fn;
2893	return -EINVAL;
2894}
2895
2896/**
2897 *	t4_seeprom_wp - enable/disable EEPROM write protection
2898 *	@adapter: the adapter
2899 *	@enable: whether to enable or disable write protection
2900 *
2901 *	Enables or disables write protection on the serial EEPROM.
2902 */
2903int t4_seeprom_wp(struct adapter *adapter, int enable)
2904{
2905	return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2906}
2907
2908/**
2909 *	get_vpd_keyword_val - Locates an information field keyword in the VPD
2910 *	@v: Pointer to buffered vpd data structure
2911 *	@kw: The keyword to search for
2912 *
2913 *	Returns the value of the information field keyword or
2914 *	-ENOENT otherwise.
2915 */
2916static int get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw)
2917{
2918	int i;
2919	unsigned int offset , len;
2920	const u8 *buf = (const u8 *)v;
2921	const u8 *vpdr_len = &v->vpdr_len[0];
2922	offset = sizeof(struct t4_vpd_hdr);
2923	len =  (u16)vpdr_len[0] + ((u16)vpdr_len[1] << 8);
2924
2925	if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) {
2926		return -ENOENT;
2927	}
2928
2929	for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2930		if(memcmp(buf + i , kw , 2) == 0){
2931			i += VPD_INFO_FLD_HDR_SIZE;
2932			return i;
2933		}
2934
2935		i += VPD_INFO_FLD_HDR_SIZE + buf[i+2];
2936	}
2937
2938	return -ENOENT;
2939}
2940
2941
2942/**
2943 *	get_vpd_params - read VPD parameters from VPD EEPROM
2944 *	@adapter: adapter to read
2945 *	@p: where to store the parameters
2946 *	@vpd: caller provided temporary space to read the VPD into
2947 *
2948 *	Reads card parameters stored in VPD EEPROM.
2949 */
2950static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
2951    u8 *vpd)
2952{
2953	int i, ret, addr;
2954	int ec, sn, pn, na;
2955	u8 csum;
2956	const struct t4_vpd_hdr *v;
2957
2958	/*
2959	 * Card information normally starts at VPD_BASE but early cards had
2960	 * it at 0.
2961	 */
2962	ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd));
2963	if (ret)
2964		return (ret);
2965
2966	/*
2967	 * The VPD shall have a unique identifier specified by the PCI SIG.
2968	 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2969	 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2970	 * is expected to automatically put this entry at the
2971	 * beginning of the VPD.
2972	 */
2973	addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2974
2975	for (i = 0; i < VPD_LEN; i += 4) {
2976		ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i));
2977		if (ret)
2978			return ret;
2979	}
2980 	v = (const struct t4_vpd_hdr *)vpd;
2981
2982#define FIND_VPD_KW(var,name) do { \
2983	var = get_vpd_keyword_val(v , name); \
2984	if (var < 0) { \
2985		CH_ERR(adapter, "missing VPD keyword " name "\n"); \
2986		return -EINVAL; \
2987	} \
2988} while (0)
2989
2990	FIND_VPD_KW(i, "RV");
2991	for (csum = 0; i >= 0; i--)
2992		csum += vpd[i];
2993
2994	if (csum) {
2995		CH_ERR(adapter,
2996			"corrupted VPD EEPROM, actual csum %u\n", csum);
2997		return -EINVAL;
2998	}
2999
3000	FIND_VPD_KW(ec, "EC");
3001	FIND_VPD_KW(sn, "SN");
3002	FIND_VPD_KW(pn, "PN");
3003	FIND_VPD_KW(na, "NA");
3004#undef FIND_VPD_KW
3005
3006	memcpy(p->id, v->id_data, ID_LEN);
3007	strstrip(p->id);
3008	memcpy(p->ec, vpd + ec, EC_LEN);
3009	strstrip(p->ec);
3010	i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3011	memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3012	strstrip(p->sn);
3013	i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3014	memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3015	strstrip((char *)p->pn);
3016	i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3017	memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3018	strstrip((char *)p->na);
3019
3020	return 0;
3021}
3022
3023/* serial flash and firmware constants and flash config file constants */
3024enum {
3025	SF_ATTEMPTS = 10,	/* max retries for SF operations */
3026
3027	/* flash command opcodes */
3028	SF_PROG_PAGE    = 2,	/* program page */
3029	SF_WR_DISABLE   = 4,	/* disable writes */
3030	SF_RD_STATUS    = 5,	/* read status register */
3031	SF_WR_ENABLE    = 6,	/* enable writes */
3032	SF_RD_DATA_FAST = 0xb,	/* read flash */
3033	SF_RD_ID	= 0x9f,	/* read ID */
3034	SF_ERASE_SECTOR = 0xd8,	/* erase sector */
3035};
3036
3037/**
3038 *	sf1_read - read data from the serial flash
3039 *	@adapter: the adapter
3040 *	@byte_cnt: number of bytes to read
3041 *	@cont: whether another operation will be chained
3042 *	@lock: whether to lock SF for PL access only
3043 *	@valp: where to store the read data
3044 *
3045 *	Reads up to 4 bytes of data from the serial flash.  The location of
3046 *	the read needs to be specified prior to calling this by issuing the
3047 *	appropriate commands to the serial flash.
3048 */
3049static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3050		    int lock, u32 *valp)
3051{
3052	int ret;
3053
3054	if (!byte_cnt || byte_cnt > 4)
3055		return -EINVAL;
3056	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3057		return -EBUSY;
3058	t4_write_reg(adapter, A_SF_OP,
3059		     V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3060	ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3061	if (!ret)
3062		*valp = t4_read_reg(adapter, A_SF_DATA);
3063	return ret;
3064}
3065
3066/**
3067 *	sf1_write - write data to the serial flash
3068 *	@adapter: the adapter
3069 *	@byte_cnt: number of bytes to write
3070 *	@cont: whether another operation will be chained
3071 *	@lock: whether to lock SF for PL access only
3072 *	@val: value to write
3073 *
3074 *	Writes up to 4 bytes of data to the serial flash.  The location of
3075 *	the write needs to be specified prior to calling this by issuing the
3076 *	appropriate commands to the serial flash.
3077 */
3078static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3079		     int lock, u32 val)
3080{
3081	if (!byte_cnt || byte_cnt > 4)
3082		return -EINVAL;
3083	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3084		return -EBUSY;
3085	t4_write_reg(adapter, A_SF_DATA, val);
3086	t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3087		     V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3088	return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3089}
3090
3091/**
3092 *	flash_wait_op - wait for a flash operation to complete
3093 *	@adapter: the adapter
3094 *	@attempts: max number of polls of the status register
3095 *	@delay: delay between polls in ms
3096 *
3097 *	Wait for a flash operation to complete by polling the status register.
3098 */
3099static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3100{
3101	int ret;
3102	u32 status;
3103
3104	while (1) {
3105		if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3106		    (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3107			return ret;
3108		if (!(status & 1))
3109			return 0;
3110		if (--attempts == 0)
3111			return -EAGAIN;
3112		if (delay)
3113			msleep(delay);
3114	}
3115}
3116
3117/**
3118 *	t4_read_flash - read words from serial flash
3119 *	@adapter: the adapter
3120 *	@addr: the start address for the read
3121 *	@nwords: how many 32-bit words to read
3122 *	@data: where to store the read data
3123 *	@byte_oriented: whether to store data as bytes or as words
3124 *
3125 *	Read the specified number of 32-bit words from the serial flash.
3126 *	If @byte_oriented is set the read data is stored as a byte array
3127 *	(i.e., big-endian), otherwise as 32-bit words in the platform's
3128 *	natural endianness.
3129 */
3130int t4_read_flash(struct adapter *adapter, unsigned int addr,
3131		  unsigned int nwords, u32 *data, int byte_oriented)
3132{
3133	int ret;
3134
3135	if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3136		return -EINVAL;
3137
3138	addr = swab32(addr) | SF_RD_DATA_FAST;
3139
3140	if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3141	    (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3142		return ret;
3143
3144	for ( ; nwords; nwords--, data++) {
3145		ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3146		if (nwords == 1)
3147			t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3148		if (ret)
3149			return ret;
3150		if (byte_oriented)
3151			*data = (__force __u32)(cpu_to_be32(*data));
3152	}
3153	return 0;
3154}
3155
3156/**
3157 *	t4_write_flash - write up to a page of data to the serial flash
3158 *	@adapter: the adapter
3159 *	@addr: the start address to write
3160 *	@n: length of data to write in bytes
3161 *	@data: the data to write
3162 *	@byte_oriented: whether to store data as bytes or as words
3163 *
3164 *	Writes up to a page of data (256 bytes) to the serial flash starting
3165 *	at the given address.  All the data must be written to the same page.
3166 *	If @byte_oriented is set the write data is stored as byte stream
3167 *	(i.e. matches what on disk), otherwise in big-endian.
3168 */
3169int t4_write_flash(struct adapter *adapter, unsigned int addr,
3170			  unsigned int n, const u8 *data, int byte_oriented)
3171{
3172	int ret;
3173	u32 buf[SF_PAGE_SIZE / 4];
3174	unsigned int i, c, left, val, offset = addr & 0xff;
3175
3176	if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3177		return -EINVAL;
3178
3179	val = swab32(addr) | SF_PROG_PAGE;
3180
3181	if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3182	    (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3183		goto unlock;
3184
3185	for (left = n; left; left -= c) {
3186		c = min(left, 4U);
3187		for (val = 0, i = 0; i < c; ++i)
3188			val = (val << 8) + *data++;
3189
3190		if (!byte_oriented)
3191			val = cpu_to_be32(val);
3192
3193		ret = sf1_write(adapter, c, c != left, 1, val);
3194		if (ret)
3195			goto unlock;
3196	}
3197	ret = flash_wait_op(adapter, 8, 1);
3198	if (ret)
3199		goto unlock;
3200
3201	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3202
3203	/* Read the page to verify the write succeeded */
3204	ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3205			    byte_oriented);
3206	if (ret)
3207		return ret;
3208
3209	if (memcmp(data - n, (u8 *)buf + offset, n)) {
3210		CH_ERR(adapter,
3211			"failed to correctly write the flash page at %#x\n",
3212			addr);
3213		return -EIO;
3214	}
3215	return 0;
3216
3217unlock:
3218	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3219	return ret;
3220}
3221
3222/**
3223 *	t4_get_fw_version - read the firmware version
3224 *	@adapter: the adapter
3225 *	@vers: where to place the version
3226 *
3227 *	Reads the FW version from flash.
3228 */
3229int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3230{
3231	return t4_read_flash(adapter, FLASH_FW_START +
3232			     offsetof(struct fw_hdr, fw_ver), 1,
3233			     vers, 0);
3234}
3235
3236/**
3237 *	t4_get_tp_version - read the TP microcode version
3238 *	@adapter: the adapter
3239 *	@vers: where to place the version
3240 *
3241 *	Reads the TP microcode version from flash.
3242 */
3243int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3244{
3245	return t4_read_flash(adapter, FLASH_FW_START +
3246			     offsetof(struct fw_hdr, tp_microcode_ver),
3247			     1, vers, 0);
3248}
3249
3250/**
3251 *	t4_get_exprom_version - return the Expansion ROM version (if any)
3252 *	@adapter: the adapter
3253 *	@vers: where to place the version
3254 *
3255 *	Reads the Expansion ROM header from FLASH and returns the version
3256 *	number (if present) through the @vers return value pointer.  We return
3257 *	this in the Firmware Version Format since it's convenient.  Return
3258 *	0 on success, -ENOENT if no Expansion ROM is present.
3259 */
3260int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3261{
3262	struct exprom_header {
3263		unsigned char hdr_arr[16];	/* must start with 0x55aa */
3264		unsigned char hdr_ver[4];	/* Expansion ROM version */
3265	} *hdr;
3266	u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3267					   sizeof(u32))];
3268	int ret;
3269
3270	ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3271			    ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3272			    0);
3273	if (ret)
3274		return ret;
3275
3276	hdr = (struct exprom_header *)exprom_header_buf;
3277	if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3278		return -ENOENT;
3279
3280	*vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3281		 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3282		 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3283		 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3284	return 0;
3285}
3286
3287/**
3288 *	t4_flash_erase_sectors - erase a range of flash sectors
3289 *	@adapter: the adapter
3290 *	@start: the first sector to erase
3291 *	@end: the last sector to erase
3292 *
3293 *	Erases the sectors in the given inclusive range.
3294 */
3295int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3296{
3297	int ret = 0;
3298
3299	if (end >= adapter->params.sf_nsec)
3300		return -EINVAL;
3301
3302	while (start <= end) {
3303		if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3304		    (ret = sf1_write(adapter, 4, 0, 1,
3305				     SF_ERASE_SECTOR | (start << 8))) != 0 ||
3306		    (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3307			CH_ERR(adapter,
3308				"erase of flash sector %d failed, error %d\n",
3309				start, ret);
3310			break;
3311		}
3312		start++;
3313	}
3314	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3315	return ret;
3316}
3317
3318/**
3319 *	t4_flash_cfg_addr - return the address of the flash configuration file
3320 *	@adapter: the adapter
3321 *
3322 *	Return the address within the flash where the Firmware Configuration
3323 *	File is stored, or an error if the device FLASH is too small to contain
3324 *	a Firmware Configuration File.
3325 */
3326int t4_flash_cfg_addr(struct adapter *adapter)
3327{
3328	/*
3329	 * If the device FLASH isn't large enough to hold a Firmware
3330	 * Configuration File, return an error.
3331	 */
3332	if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3333		return -ENOSPC;
3334
3335	return FLASH_CFG_START;
3336}
3337
3338/*
3339 * Return TRUE if the specified firmware matches the adapter.  I.e. T4
3340 * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3341 * and emit an error message for mismatched firmware to save our caller the
3342 * effort ...
3343 */
3344static int t4_fw_matches_chip(struct adapter *adap,
3345			      const struct fw_hdr *hdr)
3346{
3347	/*
3348	 * The expression below will return FALSE for any unsupported adapter
3349	 * which will keep us "honest" in the future ...
3350	 */
3351	if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3352	    (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3353	    (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3354		return 1;
3355
3356	CH_ERR(adap,
3357		"FW image (%d) is not suitable for this adapter (%d)\n",
3358		hdr->chip, chip_id(adap));
3359	return 0;
3360}
3361
3362/**
3363 *	t4_load_fw - download firmware
3364 *	@adap: the adapter
3365 *	@fw_data: the firmware image to write
3366 *	@size: image size
3367 *
3368 *	Write the supplied firmware image to the card's serial flash.
3369 */
3370int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3371{
3372	u32 csum;
3373	int ret, addr;
3374	unsigned int i;
3375	u8 first_page[SF_PAGE_SIZE];
3376	const u32 *p = (const u32 *)fw_data;
3377	const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3378	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3379	unsigned int fw_start_sec;
3380	unsigned int fw_start;
3381	unsigned int fw_size;
3382
3383	if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3384		fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3385		fw_start = FLASH_FWBOOTSTRAP_START;
3386		fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3387	} else {
3388		fw_start_sec = FLASH_FW_START_SEC;
3389 		fw_start = FLASH_FW_START;
3390		fw_size = FLASH_FW_MAX_SIZE;
3391	}
3392
3393	if (!size) {
3394		CH_ERR(adap, "FW image has no data\n");
3395		return -EINVAL;
3396	}
3397	if (size & 511) {
3398		CH_ERR(adap,
3399			"FW image size not multiple of 512 bytes\n");
3400		return -EINVAL;
3401	}
3402	if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3403		CH_ERR(adap,
3404			"FW image size differs from size in FW header\n");
3405		return -EINVAL;
3406	}
3407	if (size > fw_size) {
3408		CH_ERR(adap, "FW image too large, max is %u bytes\n",
3409			fw_size);
3410		return -EFBIG;
3411	}
3412	if (!t4_fw_matches_chip(adap, hdr))
3413		return -EINVAL;
3414
3415	for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3416		csum += be32_to_cpu(p[i]);
3417
3418	if (csum != 0xffffffff) {
3419		CH_ERR(adap,
3420			"corrupted firmware image, checksum %#x\n", csum);
3421		return -EINVAL;
3422	}
3423
3424	i = DIV_ROUND_UP(size, sf_sec_size);	/* # of sectors spanned */
3425	ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3426	if (ret)
3427		goto out;
3428
3429	/*
3430	 * We write the correct version at the end so the driver can see a bad
3431	 * version if the FW write fails.  Start by writing a copy of the
3432	 * first page with a bad version.
3433	 */
3434	memcpy(first_page, fw_data, SF_PAGE_SIZE);
3435	((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3436	ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3437	if (ret)
3438		goto out;
3439
3440	addr = fw_start;
3441	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3442		addr += SF_PAGE_SIZE;
3443		fw_data += SF_PAGE_SIZE;
3444		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3445		if (ret)
3446			goto out;
3447	}
3448
3449	ret = t4_write_flash(adap,
3450			     fw_start + offsetof(struct fw_hdr, fw_ver),
3451			     sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3452out:
3453	if (ret)
3454		CH_ERR(adap, "firmware download failed, error %d\n",
3455			ret);
3456	return ret;
3457}
3458
3459/**
3460 *	t4_fwcache - firmware cache operation
3461 *	@adap: the adapter
3462 *	@op  : the operation (flush or flush and invalidate)
3463 */
3464int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3465{
3466	struct fw_params_cmd c;
3467
3468	memset(&c, 0, sizeof(c));
3469	c.op_to_vfn =
3470	    cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3471			    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3472				V_FW_PARAMS_CMD_PFN(adap->pf) |
3473				V_FW_PARAMS_CMD_VFN(0));
3474	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3475	c.param[0].mnem =
3476	    cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3477			    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3478	c.param[0].val = (__force __be32)op;
3479
3480	return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3481}
3482
3483void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3484			unsigned int *pif_req_wrptr,
3485			unsigned int *pif_rsp_wrptr)
3486{
3487	int i, j;
3488	u32 cfg, val, req, rsp;
3489
3490	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3491	if (cfg & F_LADBGEN)
3492		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3493
3494	val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3495	req = G_POLADBGWRPTR(val);
3496	rsp = G_PILADBGWRPTR(val);
3497	if (pif_req_wrptr)
3498		*pif_req_wrptr = req;
3499	if (pif_rsp_wrptr)
3500		*pif_rsp_wrptr = rsp;
3501
3502	for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3503		for (j = 0; j < 6; j++) {
3504			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3505				     V_PILADBGRDPTR(rsp));
3506			*pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3507			*pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3508			req++;
3509			rsp++;
3510		}
3511		req = (req + 2) & M_POLADBGRDPTR;
3512		rsp = (rsp + 2) & M_PILADBGRDPTR;
3513	}
3514	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3515}
3516
3517void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3518{
3519	u32 cfg;
3520	int i, j, idx;
3521
3522	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3523	if (cfg & F_LADBGEN)
3524		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3525
3526	for (i = 0; i < CIM_MALA_SIZE; i++) {
3527		for (j = 0; j < 5; j++) {
3528			idx = 8 * i + j;
3529			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3530				     V_PILADBGRDPTR(idx));
3531			*ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3532			*ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3533		}
3534	}
3535	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3536}
3537
3538void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3539{
3540	unsigned int i, j;
3541
3542	for (i = 0; i < 8; i++) {
3543		u32 *p = la_buf + i;
3544
3545		t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3546		j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3547		t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3548		for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3549			*p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3550	}
3551}
3552
3553#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3554		     FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3555		     FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)
3556
3557/**
3558 *	t4_link_l1cfg - apply link configuration to MAC/PHY
3559 *	@phy: the PHY to setup
3560 *	@mac: the MAC to setup
3561 *	@lc: the requested link configuration
3562 *
3563 *	Set up a port's MAC and PHY according to a desired link configuration.
3564 *	- If the PHY can auto-negotiate first decide what to advertise, then
3565 *	  enable/disable auto-negotiation as desired, and reset.
3566 *	- If the PHY does not auto-negotiate just reset it.
3567 *	- If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3568 *	  otherwise do it later based on the outcome of auto-negotiation.
3569 */
3570int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3571		  struct link_config *lc)
3572{
3573	struct fw_port_cmd c;
3574	unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
3575
3576	lc->link_ok = 0;
3577	if (lc->requested_fc & PAUSE_RX)
3578		fc |= FW_PORT_CAP_FC_RX;
3579	if (lc->requested_fc & PAUSE_TX)
3580		fc |= FW_PORT_CAP_FC_TX;
3581
3582	memset(&c, 0, sizeof(c));
3583	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3584				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3585				     V_FW_PORT_CMD_PORTID(port));
3586	c.action_to_len16 =
3587		cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3588			    FW_LEN16(c));
3589
3590	if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3591		c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3592					     fc);
3593		lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3594	} else if (lc->autoneg == AUTONEG_DISABLE) {
3595		c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3596		lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3597	} else
3598		c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3599
3600	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3601}
3602
3603/**
3604 *	t4_restart_aneg - restart autonegotiation
3605 *	@adap: the adapter
3606 *	@mbox: mbox to use for the FW command
3607 *	@port: the port id
3608 *
3609 *	Restarts autonegotiation for the selected port.
3610 */
3611int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3612{
3613	struct fw_port_cmd c;
3614
3615	memset(&c, 0, sizeof(c));
3616	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3617				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3618				     V_FW_PORT_CMD_PORTID(port));
3619	c.action_to_len16 =
3620		cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3621			    FW_LEN16(c));
3622	c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3623	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3624}
3625
3626typedef void (*int_handler_t)(struct adapter *adap);
3627
3628struct intr_info {
3629	unsigned int mask;	/* bits to check in interrupt status */
3630	const char *msg;	/* message to print or NULL */
3631	short stat_idx;		/* stat counter to increment or -1 */
3632	unsigned short fatal;	/* whether the condition reported is fatal */
3633	int_handler_t int_handler;	/* platform-specific int handler */
3634};
3635
3636/**
3637 *	t4_handle_intr_status - table driven interrupt handler
3638 *	@adapter: the adapter that generated the interrupt
3639 *	@reg: the interrupt status register to process
3640 *	@acts: table of interrupt actions
3641 *
3642 *	A table driven interrupt handler that applies a set of masks to an
3643 *	interrupt status word and performs the corresponding actions if the
3644 *	interrupts described by the mask have occurred.  The actions include
3645 *	optionally emitting a warning or alert message.  The table is terminated
3646 *	by an entry specifying mask 0.  Returns the number of fatal interrupt
3647 *	conditions.
3648 */
3649static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3650				 const struct intr_info *acts)
3651{
3652	int fatal = 0;
3653	unsigned int mask = 0;
3654	unsigned int status = t4_read_reg(adapter, reg);
3655
3656	for ( ; acts->mask; ++acts) {
3657		if (!(status & acts->mask))
3658			continue;
3659		if (acts->fatal) {
3660			fatal++;
3661			CH_ALERT(adapter, "%s (0x%x)\n", acts->msg,
3662				  status & acts->mask);
3663		} else if (acts->msg)
3664			CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg,
3665				 status & acts->mask);
3666		if (acts->int_handler)
3667			acts->int_handler(adapter);
3668		mask |= acts->mask;
3669	}
3670	status &= mask;
3671	if (status)	/* clear processed interrupts */
3672		t4_write_reg(adapter, reg, status);
3673	return fatal;
3674}
3675
3676/*
3677 * Interrupt handler for the PCIE module.
3678 */
3679static void pcie_intr_handler(struct adapter *adapter)
3680{
3681	static const struct intr_info sysbus_intr_info[] = {
3682		{ F_RNPP, "RXNP array parity error", -1, 1 },
3683		{ F_RPCP, "RXPC array parity error", -1, 1 },
3684		{ F_RCIP, "RXCIF array parity error", -1, 1 },
3685		{ F_RCCP, "Rx completions control array parity error", -1, 1 },
3686		{ F_RFTP, "RXFT array parity error", -1, 1 },
3687		{ 0 }
3688	};
3689	static const struct intr_info pcie_port_intr_info[] = {
3690		{ F_TPCP, "TXPC array parity error", -1, 1 },
3691		{ F_TNPP, "TXNP array parity error", -1, 1 },
3692		{ F_TFTP, "TXFT array parity error", -1, 1 },
3693		{ F_TCAP, "TXCA array parity error", -1, 1 },
3694		{ F_TCIP, "TXCIF array parity error", -1, 1 },
3695		{ F_RCAP, "RXCA array parity error", -1, 1 },
3696		{ F_OTDD, "outbound request TLP discarded", -1, 1 },
3697		{ F_RDPE, "Rx data parity error", -1, 1 },
3698		{ F_TDUE, "Tx uncorrectable data error", -1, 1 },
3699		{ 0 }
3700	};
3701	static const struct intr_info pcie_intr_info[] = {
3702		{ F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
3703		{ F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
3704		{ F_MSIDATAPERR, "MSI data parity error", -1, 1 },
3705		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3706		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3707		{ F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3708		{ F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3709		{ F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
3710		{ F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
3711		{ F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3712		{ F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
3713		{ F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3714		{ F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3715		{ F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
3716		{ F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3717		{ F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3718		{ F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
3719		{ F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3720		{ F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3721		{ F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3722		{ F_FIDPERR, "PCI FID parity error", -1, 1 },
3723		{ F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
3724		{ F_MATAGPERR, "PCI MA tag parity error", -1, 1 },
3725		{ F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3726		{ F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
3727		{ F_RXWRPERR, "PCI Rx write parity error", -1, 1 },
3728		{ F_RPLPERR, "PCI replay buffer parity error", -1, 1 },
3729		{ F_PCIESINT, "PCI core secondary fault", -1, 1 },
3730		{ F_PCIEPINT, "PCI core primary fault", -1, 1 },
3731		{ F_UNXSPLCPLERR, "PCI unexpected split completion error", -1,
3732		  0 },
3733		{ 0 }
3734	};
3735
3736	static const struct intr_info t5_pcie_intr_info[] = {
3737		{ F_MSTGRPPERR, "Master Response Read Queue parity error",
3738		  -1, 1 },
3739		{ F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
3740		{ F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
3741		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3742		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3743		{ F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3744		{ F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3745		{ F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
3746		  -1, 1 },
3747		{ F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
3748		  -1, 1 },
3749		{ F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3750		{ F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
3751		{ F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3752		{ F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3753		{ F_DREQWRPERR, "PCI DMA channel write request parity error",
3754		  -1, 1 },
3755		{ F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3756		{ F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3757		{ F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
3758		{ F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3759		{ F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3760		{ F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3761		{ F_FIDPERR, "PCI FID parity error", -1, 1 },
3762		{ F_VFIDPERR, "PCI INTx clear parity error", -1, 1 },
3763		{ F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
3764		{ F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3765		{ F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
3766		  -1, 1 },
3767		{ F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
3768		  -1, 1 },
3769		{ F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
3770		{ F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
3771		{ F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3772		{ F_READRSPERR, "Outbound read error", -1,
3773		  0 },
3774		{ 0 }
3775	};
3776
3777	int fat;
3778
3779	if (is_t4(adapter))
3780		fat = t4_handle_intr_status(adapter,
3781				A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
3782				sysbus_intr_info) +
3783			t4_handle_intr_status(adapter,
3784					A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
3785					pcie_port_intr_info) +
3786			t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3787					      pcie_intr_info);
3788	else
3789		fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3790					    t5_pcie_intr_info);
3791	if (fat)
3792		t4_fatal_err(adapter);
3793}
3794
3795/*
3796 * TP interrupt handler.
3797 */
3798static void tp_intr_handler(struct adapter *adapter)
3799{
3800	static const struct intr_info tp_intr_info[] = {
3801		{ 0x3fffffff, "TP parity error", -1, 1 },
3802		{ F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
3803		{ 0 }
3804	};
3805
3806	if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info))
3807		t4_fatal_err(adapter);
3808}
3809
3810/*
3811 * SGE interrupt handler.
3812 */
3813static void sge_intr_handler(struct adapter *adapter)
3814{
3815	u64 v;
3816	u32 err;
3817
3818	static const struct intr_info sge_intr_info[] = {
3819		{ F_ERR_CPL_EXCEED_IQE_SIZE,
3820		  "SGE received CPL exceeding IQE size", -1, 1 },
3821		{ F_ERR_INVALID_CIDX_INC,
3822		  "SGE GTS CIDX increment too large", -1, 0 },
3823		{ F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
3824		{ F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
3825		{ F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
3826		  "SGE IQID > 1023 received CPL for FL", -1, 0 },
3827		{ F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
3828		  0 },
3829		{ F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
3830		  0 },
3831		{ F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
3832		  0 },
3833		{ F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
3834		  0 },
3835		{ F_ERR_ING_CTXT_PRIO,
3836		  "SGE too many priority ingress contexts", -1, 0 },
3837		{ F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
3838		{ F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
3839		{ 0 }
3840	};
3841
3842	static const struct intr_info t4t5_sge_intr_info[] = {
3843		{ F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
3844		{ F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
3845		{ F_ERR_EGR_CTXT_PRIO,
3846		  "SGE too many priority egress contexts", -1, 0 },
3847		{ 0 }
3848	};
3849
3850	/*
3851 	* For now, treat below interrupts as fatal so that we disable SGE and
3852 	* get better debug */
3853	static const struct intr_info t6_sge_intr_info[] = {
3854		{ F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1,
3855		  "SGE PCIe error for a DBP thread", -1, 1 },
3856		{ F_FATAL_WRE_LEN,
3857		  "SGE Actual WRE packet is less than advertized length",
3858		  -1, 1 },
3859		{ 0 }
3860	};
3861
3862	v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) |
3863		((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32);
3864	if (v) {
3865		CH_ALERT(adapter, "SGE parity error (%#llx)\n",
3866				(unsigned long long)v);
3867		t4_write_reg(adapter, A_SGE_INT_CAUSE1, v);
3868		t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32);
3869	}
3870
3871	v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info);
3872	if (chip_id(adapter) <= CHELSIO_T5)
3873		v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
3874					   t4t5_sge_intr_info);
3875	else
3876		v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
3877					   t6_sge_intr_info);
3878
3879	err = t4_read_reg(adapter, A_SGE_ERROR_STATS);
3880	if (err & F_ERROR_QID_VALID) {
3881		CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err));
3882		if (err & F_UNCAPTURED_ERROR)
3883			CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n");
3884		t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID |
3885			     F_UNCAPTURED_ERROR);
3886	}
3887
3888	if (v != 0)
3889		t4_fatal_err(adapter);
3890}
3891
3892#define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\
3893		      F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR)
3894#define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\
3895		      F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR)
3896
3897/*
3898 * CIM interrupt handler.
3899 */
3900static void cim_intr_handler(struct adapter *adapter)
3901{
3902	static const struct intr_info cim_intr_info[] = {
3903		{ F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
3904		{ CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3905		{ CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3906		{ F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
3907		{ F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
3908		{ F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
3909		{ F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
3910		{ 0 }
3911	};
3912	static const struct intr_info cim_upintr_info[] = {
3913		{ F_RSVDSPACEINT, "CIM reserved space access", -1, 1 },
3914		{ F_ILLTRANSINT, "CIM illegal transaction", -1, 1 },
3915		{ F_ILLWRINT, "CIM illegal write", -1, 1 },
3916		{ F_ILLRDINT, "CIM illegal read", -1, 1 },
3917		{ F_ILLRDBEINT, "CIM illegal read BE", -1, 1 },
3918		{ F_ILLWRBEINT, "CIM illegal write BE", -1, 1 },
3919		{ F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
3920		{ F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
3921		{ F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
3922		{ F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
3923		{ F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
3924		{ F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
3925		{ F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
3926		{ F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
3927		{ F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
3928		{ F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
3929		{ F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
3930		{ F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
3931		{ F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
3932		{ F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
3933		{ F_SGLRDPLINT , "CIM single read from PL space", -1, 1 },
3934		{ F_SGLWRPLINT , "CIM single write to PL space", -1, 1 },
3935		{ F_BLKRDPLINT , "CIM block read from PL space", -1, 1 },
3936		{ F_BLKWRPLINT , "CIM block write to PL space", -1, 1 },
3937		{ F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
3938		{ F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
3939		{ F_TIMEOUTINT , "CIM PIF timeout", -1, 1 },
3940		{ F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
3941		{ 0 }
3942	};
3943	int fat;
3944
3945	if (t4_read_reg(adapter, A_PCIE_FW) & F_PCIE_FW_ERR)
3946		t4_report_fw_error(adapter);
3947
3948	fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE,
3949				    cim_intr_info) +
3950	      t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE,
3951				    cim_upintr_info);
3952	if (fat)
3953		t4_fatal_err(adapter);
3954}
3955
3956/*
3957 * ULP RX interrupt handler.
3958 */
3959static void ulprx_intr_handler(struct adapter *adapter)
3960{
3961	static const struct intr_info ulprx_intr_info[] = {
3962		{ F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 },
3963		{ F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 },
3964		{ 0x7fffff, "ULPRX parity error", -1, 1 },
3965		{ 0 }
3966	};
3967
3968	if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info))
3969		t4_fatal_err(adapter);
3970}
3971
3972/*
3973 * ULP TX interrupt handler.
3974 */
3975static void ulptx_intr_handler(struct adapter *adapter)
3976{
3977	static const struct intr_info ulptx_intr_info[] = {
3978		{ F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
3979		  0 },
3980		{ F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
3981		  0 },
3982		{ F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
3983		  0 },
3984		{ F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
3985		  0 },
3986		{ 0xfffffff, "ULPTX parity error", -1, 1 },
3987		{ 0 }
3988	};
3989
3990	if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info))
3991		t4_fatal_err(adapter);
3992}
3993
3994/*
3995 * PM TX interrupt handler.
3996 */
3997static void pmtx_intr_handler(struct adapter *adapter)
3998{
3999	static const struct intr_info pmtx_intr_info[] = {
4000		{ F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
4001		{ F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
4002		{ F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
4003		{ F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
4004		{ 0xffffff0, "PMTX framing error", -1, 1 },
4005		{ F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
4006		{ F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1,
4007		  1 },
4008		{ F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
4009		{ F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
4010		{ 0 }
4011	};
4012
4013	if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info))
4014		t4_fatal_err(adapter);
4015}
4016
4017/*
4018 * PM RX interrupt handler.
4019 */
4020static void pmrx_intr_handler(struct adapter *adapter)
4021{
4022	static const struct intr_info pmrx_intr_info[] = {
4023		{ F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
4024		{ 0x3ffff0, "PMRX framing error", -1, 1 },
4025		{ F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
4026		{ F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1,
4027		  1 },
4028		{ F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
4029		{ F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
4030		{ 0 }
4031	};
4032
4033	if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info))
4034		t4_fatal_err(adapter);
4035}
4036
4037/*
4038 * CPL switch interrupt handler.
4039 */
4040static void cplsw_intr_handler(struct adapter *adapter)
4041{
4042	static const struct intr_info cplsw_intr_info[] = {
4043		{ F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
4044		{ F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
4045		{ F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
4046		{ F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
4047		{ F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
4048		{ F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
4049		{ 0 }
4050	};
4051
4052	if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info))
4053		t4_fatal_err(adapter);
4054}
4055
4056/*
4057 * LE interrupt handler.
4058 */
4059static void le_intr_handler(struct adapter *adap)
4060{
4061	unsigned int chip_ver = chip_id(adap);
4062	static const struct intr_info le_intr_info[] = {
4063		{ F_LIPMISS, "LE LIP miss", -1, 0 },
4064		{ F_LIP0, "LE 0 LIP error", -1, 0 },
4065		{ F_PARITYERR, "LE parity error", -1, 1 },
4066		{ F_UNKNOWNCMD, "LE unknown command", -1, 1 },
4067		{ F_REQQPARERR, "LE request queue parity error", -1, 1 },
4068		{ 0 }
4069	};
4070
4071	static const struct intr_info t6_le_intr_info[] = {
4072		{ F_T6_LIPMISS, "LE LIP miss", -1, 0 },
4073		{ F_T6_LIP0, "LE 0 LIP error", -1, 0 },
4074		{ F_TCAMINTPERR, "LE parity error", -1, 1 },
4075		{ F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 },
4076		{ F_SSRAMINTPERR, "LE request queue parity error", -1, 1 },
4077		{ 0 }
4078	};
4079
4080	if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE,
4081				  (chip_ver <= CHELSIO_T5) ?
4082				  le_intr_info : t6_le_intr_info))
4083		t4_fatal_err(adap);
4084}
4085
4086/*
4087 * MPS interrupt handler.
4088 */
4089static void mps_intr_handler(struct adapter *adapter)
4090{
4091	static const struct intr_info mps_rx_intr_info[] = {
4092		{ 0xffffff, "MPS Rx parity error", -1, 1 },
4093		{ 0 }
4094	};
4095	static const struct intr_info mps_tx_intr_info[] = {
4096		{ V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 },
4097		{ F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4098		{ V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error",
4099		  -1, 1 },
4100		{ V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error",
4101		  -1, 1 },
4102		{ F_BUBBLE, "MPS Tx underflow", -1, 1 },
4103		{ F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
4104		{ F_FRMERR, "MPS Tx framing error", -1, 1 },
4105		{ 0 }
4106	};
4107	static const struct intr_info mps_trc_intr_info[] = {
4108		{ V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 },
4109		{ V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1,
4110		  1 },
4111		{ F_MISCPERR, "MPS TRC misc parity error", -1, 1 },
4112		{ 0 }
4113	};
4114	static const struct intr_info mps_stat_sram_intr_info[] = {
4115		{ 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4116		{ 0 }
4117	};
4118	static const struct intr_info mps_stat_tx_intr_info[] = {
4119		{ 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4120		{ 0 }
4121	};
4122	static const struct intr_info mps_stat_rx_intr_info[] = {
4123		{ 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4124		{ 0 }
4125	};
4126	static const struct intr_info mps_cls_intr_info[] = {
4127		{ F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
4128		{ F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
4129		{ F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
4130		{ 0 }
4131	};
4132
4133	int fat;
4134
4135	fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE,
4136				    mps_rx_intr_info) +
4137	      t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE,
4138				    mps_tx_intr_info) +
4139	      t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE,
4140				    mps_trc_intr_info) +
4141	      t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4142				    mps_stat_sram_intr_info) +
4143	      t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4144				    mps_stat_tx_intr_info) +
4145	      t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4146				    mps_stat_rx_intr_info) +
4147	      t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE,
4148				    mps_cls_intr_info);
4149
4150	t4_write_reg(adapter, A_MPS_INT_CAUSE, 0);
4151	t4_read_reg(adapter, A_MPS_INT_CAUSE);	/* flush */
4152	if (fat)
4153		t4_fatal_err(adapter);
4154}
4155
4156#define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \
4157		      F_ECC_UE_INT_CAUSE)
4158
4159/*
4160 * EDC/MC interrupt handler.
4161 */
4162static void mem_intr_handler(struct adapter *adapter, int idx)
4163{
4164	static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4165
4166	unsigned int addr, cnt_addr, v;
4167
4168	if (idx <= MEM_EDC1) {
4169		addr = EDC_REG(A_EDC_INT_CAUSE, idx);
4170		cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx);
4171	} else if (idx == MEM_MC) {
4172		if (is_t4(adapter)) {
4173			addr = A_MC_INT_CAUSE;
4174			cnt_addr = A_MC_ECC_STATUS;
4175		} else {
4176			addr = A_MC_P_INT_CAUSE;
4177			cnt_addr = A_MC_P_ECC_STATUS;
4178		}
4179	} else {
4180		addr = MC_REG(A_MC_P_INT_CAUSE, 1);
4181		cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1);
4182	}
4183
4184	v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4185	if (v & F_PERR_INT_CAUSE)
4186		CH_ALERT(adapter, "%s FIFO parity error\n",
4187			  name[idx]);
4188	if (v & F_ECC_CE_INT_CAUSE) {
4189		u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr));
4190
4191		t4_edc_err_read(adapter, idx);
4192
4193		t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT));
4194		CH_WARN_RATELIMIT(adapter,
4195				  "%u %s correctable ECC data error%s\n",
4196				  cnt, name[idx], cnt > 1 ? "s" : "");
4197	}
4198	if (v & F_ECC_UE_INT_CAUSE)
4199		CH_ALERT(adapter,
4200			 "%s uncorrectable ECC data error\n", name[idx]);
4201
4202	t4_write_reg(adapter, addr, v);
4203	if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE))
4204		t4_fatal_err(adapter);
4205}
4206
4207/*
4208 * MA interrupt handler.
4209 */
4210static void ma_intr_handler(struct adapter *adapter)
4211{
4212	u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE);
4213
4214	if (status & F_MEM_PERR_INT_CAUSE) {
4215		CH_ALERT(adapter,
4216			  "MA parity error, parity status %#x\n",
4217			  t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1));
4218		if (is_t5(adapter))
4219			CH_ALERT(adapter,
4220				  "MA parity error, parity status %#x\n",
4221				  t4_read_reg(adapter,
4222					      A_MA_PARITY_ERROR_STATUS2));
4223	}
4224	if (status & F_MEM_WRAP_INT_CAUSE) {
4225		v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS);
4226		CH_ALERT(adapter, "MA address wrap-around error by "
4227			  "client %u to address %#x\n",
4228			  G_MEM_WRAP_CLIENT_NUM(v),
4229			  G_MEM_WRAP_ADDRESS(v) << 4);
4230	}
4231	t4_write_reg(adapter, A_MA_INT_CAUSE, status);
4232	t4_fatal_err(adapter);
4233}
4234
4235/*
4236 * SMB interrupt handler.
4237 */
4238static void smb_intr_handler(struct adapter *adap)
4239{
4240	static const struct intr_info smb_intr_info[] = {
4241		{ F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
4242		{ F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
4243		{ F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
4244		{ 0 }
4245	};
4246
4247	if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info))
4248		t4_fatal_err(adap);
4249}
4250
4251/*
4252 * NC-SI interrupt handler.
4253 */
4254static void ncsi_intr_handler(struct adapter *adap)
4255{
4256	static const struct intr_info ncsi_intr_info[] = {
4257		{ F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
4258		{ F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
4259		{ F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
4260		{ F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
4261		{ 0 }
4262	};
4263
4264	if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info))
4265		t4_fatal_err(adap);
4266}
4267
4268/*
4269 * XGMAC interrupt handler.
4270 */
4271static void xgmac_intr_handler(struct adapter *adap, int port)
4272{
4273	u32 v, int_cause_reg;
4274
4275	if (is_t4(adap))
4276		int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
4277	else
4278		int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
4279
4280	v = t4_read_reg(adap, int_cause_reg);
4281
4282	v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR);
4283	if (!v)
4284		return;
4285
4286	if (v & F_TXFIFO_PRTY_ERR)
4287		CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n",
4288			  port);
4289	if (v & F_RXFIFO_PRTY_ERR)
4290		CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n",
4291			  port);
4292	t4_write_reg(adap, int_cause_reg, v);
4293	t4_fatal_err(adap);
4294}
4295
4296/*
4297 * PL interrupt handler.
4298 */
4299static void pl_intr_handler(struct adapter *adap)
4300{
4301	static const struct intr_info pl_intr_info[] = {
4302		{ F_FATALPERR, "Fatal parity error", -1, 1 },
4303		{ F_PERRVFID, "PL VFID_MAP parity error", -1, 1 },
4304		{ 0 }
4305	};
4306
4307	static const struct intr_info t5_pl_intr_info[] = {
4308		{ F_FATALPERR, "Fatal parity error", -1, 1 },
4309		{ 0 }
4310	};
4311
4312	if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE,
4313				  is_t4(adap) ?
4314				  pl_intr_info : t5_pl_intr_info))
4315		t4_fatal_err(adap);
4316}
4317
4318#define PF_INTR_MASK (F_PFSW | F_PFCIM)
4319
4320/**
4321 *	t4_slow_intr_handler - control path interrupt handler
4322 *	@adapter: the adapter
4323 *
4324 *	T4 interrupt handler for non-data global interrupt events, e.g., errors.
4325 *	The designation 'slow' is because it involves register reads, while
4326 *	data interrupts typically don't involve any MMIOs.
4327 */
4328int t4_slow_intr_handler(struct adapter *adapter)
4329{
4330	u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE);
4331
4332	if (!(cause & GLBL_INTR_MASK))
4333		return 0;
4334	if (cause & F_CIM)
4335		cim_intr_handler(adapter);
4336	if (cause & F_MPS)
4337		mps_intr_handler(adapter);
4338	if (cause & F_NCSI)
4339		ncsi_intr_handler(adapter);
4340	if (cause & F_PL)
4341		pl_intr_handler(adapter);
4342	if (cause & F_SMB)
4343		smb_intr_handler(adapter);
4344	if (cause & F_MAC0)
4345		xgmac_intr_handler(adapter, 0);
4346	if (cause & F_MAC1)
4347		xgmac_intr_handler(adapter, 1);
4348	if (cause & F_MAC2)
4349		xgmac_intr_handler(adapter, 2);
4350	if (cause & F_MAC3)
4351		xgmac_intr_handler(adapter, 3);
4352	if (cause & F_PCIE)
4353		pcie_intr_handler(adapter);
4354	if (cause & F_MC0)
4355		mem_intr_handler(adapter, MEM_MC);
4356	if (is_t5(adapter) && (cause & F_MC1))
4357		mem_intr_handler(adapter, MEM_MC1);
4358	if (cause & F_EDC0)
4359		mem_intr_handler(adapter, MEM_EDC0);
4360	if (cause & F_EDC1)
4361		mem_intr_handler(adapter, MEM_EDC1);
4362	if (cause & F_LE)
4363		le_intr_handler(adapter);
4364	if (cause & F_TP)
4365		tp_intr_handler(adapter);
4366	if (cause & F_MA)
4367		ma_intr_handler(adapter);
4368	if (cause & F_PM_TX)
4369		pmtx_intr_handler(adapter);
4370	if (cause & F_PM_RX)
4371		pmrx_intr_handler(adapter);
4372	if (cause & F_ULP_RX)
4373		ulprx_intr_handler(adapter);
4374	if (cause & F_CPL_SWITCH)
4375		cplsw_intr_handler(adapter);
4376	if (cause & F_SGE)
4377		sge_intr_handler(adapter);
4378	if (cause & F_ULP_TX)
4379		ulptx_intr_handler(adapter);
4380
4381	/* Clear the interrupts just processed for which we are the master. */
4382	t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK);
4383	(void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */
4384	return 1;
4385}
4386
4387/**
4388 *	t4_intr_enable - enable interrupts
4389 *	@adapter: the adapter whose interrupts should be enabled
4390 *
4391 *	Enable PF-specific interrupts for the calling function and the top-level
4392 *	interrupt concentrator for global interrupts.  Interrupts are already
4393 *	enabled at each module,	here we just enable the roots of the interrupt
4394 *	hierarchies.
4395 *
4396 *	Note: this function should be called only when the driver manages
4397 *	non PF-specific interrupts from the various HW modules.  Only one PCI
4398 *	function at a time should be doing this.
4399 */
4400void t4_intr_enable(struct adapter *adapter)
4401{
4402	u32 val = 0;
4403	u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4404	u32 pf = (chip_id(adapter) <= CHELSIO_T5
4405		  ? G_SOURCEPF(whoami)
4406		  : G_T6_SOURCEPF(whoami));
4407
4408	if (chip_id(adapter) <= CHELSIO_T5)
4409		val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
4410	else
4411		val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
4412	t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
4413		     F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
4414		     F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
4415		     F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
4416		     F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4417		     F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
4418		     F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
4419	t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
4420	t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
4421}
4422
4423/**
4424 *	t4_intr_disable - disable interrupts
4425 *	@adapter: the adapter whose interrupts should be disabled
4426 *
4427 *	Disable interrupts.  We only disable the top-level interrupt
4428 *	concentrators.  The caller must be a PCI function managing global
4429 *	interrupts.
4430 */
4431void t4_intr_disable(struct adapter *adapter)
4432{
4433	u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4434	u32 pf = (chip_id(adapter) <= CHELSIO_T5
4435		  ? G_SOURCEPF(whoami)
4436		  : G_T6_SOURCEPF(whoami));
4437
4438	t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
4439	t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
4440}
4441
4442/**
4443 *	t4_intr_clear - clear all interrupts
4444 *	@adapter: the adapter whose interrupts should be cleared
4445 *
4446 *	Clears all interrupts.  The caller must be a PCI function managing
4447 *	global interrupts.
4448 */
4449void t4_intr_clear(struct adapter *adapter)
4450{
4451	static const unsigned int cause_reg[] = {
4452		A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3,
4453		A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE,
4454		A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE,
4455		A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1),
4456		A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE,
4457		MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4458		A_TP_INT_CAUSE,
4459		A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE,
4460		A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE,
4461		A_MPS_RX_PERR_INT_CAUSE,
4462		A_CPL_INTR_CAUSE,
4463		MYPF_REG(A_PL_PF_INT_CAUSE),
4464		A_PL_PL_INT_CAUSE,
4465		A_LE_DB_INT_CAUSE,
4466	};
4467
4468	unsigned int i;
4469
4470	for (i = 0; i < ARRAY_SIZE(cause_reg); ++i)
4471		t4_write_reg(adapter, cause_reg[i], 0xffffffff);
4472
4473	t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE :
4474				A_MC_P_INT_CAUSE, 0xffffffff);
4475
4476	if (is_t4(adapter)) {
4477		t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4478				0xffffffff);
4479		t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4480				0xffffffff);
4481	} else
4482		t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
4483
4484	t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK);
4485	(void) t4_read_reg(adapter, A_PL_INT_CAUSE);          /* flush */
4486}
4487
4488/**
4489 *	hash_mac_addr - return the hash value of a MAC address
4490 *	@addr: the 48-bit Ethernet MAC address
4491 *
4492 *	Hashes a MAC address according to the hash function used by HW inexact
4493 *	(hash) address matching.
4494 */
4495static int hash_mac_addr(const u8 *addr)
4496{
4497	u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
4498	u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
4499	a ^= b;
4500	a ^= (a >> 12);
4501	a ^= (a >> 6);
4502	return a & 0x3f;
4503}
4504
4505/**
4506 *	t4_config_rss_range - configure a portion of the RSS mapping table
4507 *	@adapter: the adapter
4508 *	@mbox: mbox to use for the FW command
4509 *	@viid: virtual interface whose RSS subtable is to be written
4510 *	@start: start entry in the table to write
4511 *	@n: how many table entries to write
4512 *	@rspq: values for the "response queue" (Ingress Queue) lookup table
4513 *	@nrspq: number of values in @rspq
4514 *
4515 *	Programs the selected part of the VI's RSS mapping table with the
4516 *	provided values.  If @nrspq < @n the supplied values are used repeatedly
4517 *	until the full table range is populated.
4518 *
4519 *	The caller must ensure the values in @rspq are in the range allowed for
4520 *	@viid.
4521 */
4522int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4523			int start, int n, const u16 *rspq, unsigned int nrspq)
4524{
4525	int ret;
4526	const u16 *rsp = rspq;
4527	const u16 *rsp_end = rspq + nrspq;
4528	struct fw_rss_ind_tbl_cmd cmd;
4529
4530	memset(&cmd, 0, sizeof(cmd));
4531	cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
4532				     F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4533				     V_FW_RSS_IND_TBL_CMD_VIID(viid));
4534	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4535
4536	/*
4537	 * Each firmware RSS command can accommodate up to 32 RSS Ingress
4538	 * Queue Identifiers.  These Ingress Queue IDs are packed three to
4539	 * a 32-bit word as 10-bit values with the upper remaining 2 bits
4540	 * reserved.
4541	 */
4542	while (n > 0) {
4543		int nq = min(n, 32);
4544		int nq_packed = 0;
4545		__be32 *qp = &cmd.iq0_to_iq2;
4546
4547		/*
4548		 * Set up the firmware RSS command header to send the next
4549		 * "nq" Ingress Queue IDs to the firmware.
4550		 */
4551		cmd.niqid = cpu_to_be16(nq);
4552		cmd.startidx = cpu_to_be16(start);
4553
4554		/*
4555		 * "nq" more done for the start of the next loop.
4556		 */
4557		start += nq;
4558		n -= nq;
4559
4560		/*
4561		 * While there are still Ingress Queue IDs to stuff into the
4562		 * current firmware RSS command, retrieve them from the
4563		 * Ingress Queue ID array and insert them into the command.
4564		 */
4565		while (nq > 0) {
4566			/*
4567			 * Grab up to the next 3 Ingress Queue IDs (wrapping
4568			 * around the Ingress Queue ID array if necessary) and
4569			 * insert them into the firmware RSS command at the
4570			 * current 3-tuple position within the commad.
4571			 */
4572			u16 qbuf[3];
4573			u16 *qbp = qbuf;
4574			int nqbuf = min(3, nq);
4575
4576			nq -= nqbuf;
4577			qbuf[0] = qbuf[1] = qbuf[2] = 0;
4578			while (nqbuf && nq_packed < 32) {
4579				nqbuf--;
4580				nq_packed++;
4581				*qbp++ = *rsp++;
4582				if (rsp >= rsp_end)
4583					rsp = rspq;
4584			}
4585			*qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
4586					    V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
4587					    V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
4588		}
4589
4590		/*
4591		 * Send this portion of the RRS table update to the firmware;
4592		 * bail out on any errors.
4593		 */
4594		ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4595		if (ret)
4596			return ret;
4597	}
4598	return 0;
4599}
4600
4601/**
4602 *	t4_config_glbl_rss - configure the global RSS mode
4603 *	@adapter: the adapter
4604 *	@mbox: mbox to use for the FW command
4605 *	@mode: global RSS mode
4606 *	@flags: mode-specific flags
4607 *
4608 *	Sets the global RSS mode.
4609 */
4610int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4611		       unsigned int flags)
4612{
4613	struct fw_rss_glb_config_cmd c;
4614
4615	memset(&c, 0, sizeof(c));
4616	c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
4617				    F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
4618	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4619	if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4620		c.u.manual.mode_pkd =
4621			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4622	} else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4623		c.u.basicvirtual.mode_pkd =
4624			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4625		c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4626	} else
4627		return -EINVAL;
4628	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4629}
4630
4631/**
4632 *	t4_config_vi_rss - configure per VI RSS settings
4633 *	@adapter: the adapter
4634 *	@mbox: mbox to use for the FW command
4635 *	@viid: the VI id
4636 *	@flags: RSS flags
4637 *	@defq: id of the default RSS queue for the VI.
4638 *
4639 *	Configures VI-specific RSS properties.
4640 */
4641int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4642		     unsigned int flags, unsigned int defq)
4643{
4644	struct fw_rss_vi_config_cmd c;
4645
4646	memset(&c, 0, sizeof(c));
4647	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4648				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4649				   V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
4650	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4651	c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4652					V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
4653	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4654}
4655
4656/* Read an RSS table row */
4657static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4658{
4659	t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
4660	return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
4661				   5, 0, val);
4662}
4663
4664/**
4665 *	t4_read_rss - read the contents of the RSS mapping table
4666 *	@adapter: the adapter
4667 *	@map: holds the contents of the RSS mapping table
4668 *
4669 *	Reads the contents of the RSS hash->queue mapping table.
4670 */
4671int t4_read_rss(struct adapter *adapter, u16 *map)
4672{
4673	u32 val;
4674	int i, ret;
4675
4676	for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4677		ret = rd_rss_row(adapter, i, &val);
4678		if (ret)
4679			return ret;
4680		*map++ = G_LKPTBLQUEUE0(val);
4681		*map++ = G_LKPTBLQUEUE1(val);
4682	}
4683	return 0;
4684}
4685
4686/**
4687 *	t4_fw_tp_pio_rw - Access TP PIO through LDST
4688 *	@adap: the adapter
4689 *	@vals: where the indirect register values are stored/written
4690 *	@nregs: how many indirect registers to read/write
4691 *	@start_idx: index of first indirect register to read/write
4692 *	@rw: Read (1) or Write (0)
4693 *
4694 *	Access TP PIO registers through LDST
4695 */
4696void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4697		     unsigned int start_index, unsigned int rw)
4698{
4699	int ret, i;
4700	int cmd = FW_LDST_ADDRSPC_TP_PIO;
4701	struct fw_ldst_cmd c;
4702
4703	for (i = 0 ; i < nregs; i++) {
4704		memset(&c, 0, sizeof(c));
4705		c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
4706						F_FW_CMD_REQUEST |
4707						(rw ? F_FW_CMD_READ :
4708						     F_FW_CMD_WRITE) |
4709						V_FW_LDST_CMD_ADDRSPACE(cmd));
4710		c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4711
4712		c.u.addrval.addr = cpu_to_be32(start_index + i);
4713		c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
4714		ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4715		if (ret == 0) {
4716			if (rw)
4717				vals[i] = be32_to_cpu(c.u.addrval.val);
4718		}
4719	}
4720}
4721
4722/**
4723 *	t4_read_rss_key - read the global RSS key
4724 *	@adap: the adapter
4725 *	@key: 10-entry array holding the 320-bit RSS key
4726 *
4727 *	Reads the global 320-bit RSS key.
4728 */
4729void t4_read_rss_key(struct adapter *adap, u32 *key)
4730{
4731	if (t4_use_ldst(adap))
4732		t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1);
4733	else
4734		t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
4735				 A_TP_RSS_SECRET_KEY0);
4736}
4737
4738/**
4739 *	t4_write_rss_key - program one of the RSS keys
4740 *	@adap: the adapter
4741 *	@key: 10-entry array holding the 320-bit RSS key
4742 *	@idx: which RSS key to write
4743 *
4744 *	Writes one of the RSS keys with the given 320-bit value.  If @idx is
4745 *	0..15 the corresponding entry in the RSS key table is written,
4746 *	otherwise the global RSS key is written.
4747 */
4748void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
4749{
4750	u8 rss_key_addr_cnt = 16;
4751	u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
4752
4753	/*
4754	 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4755	 * allows access to key addresses 16-63 by using KeyWrAddrX
4756	 * as index[5:4](upper 2) into key table
4757	 */
4758	if ((chip_id(adap) > CHELSIO_T5) &&
4759	    (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
4760		rss_key_addr_cnt = 32;
4761
4762	if (t4_use_ldst(adap))
4763		t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
4764	else
4765		t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
4766				  A_TP_RSS_SECRET_KEY0);
4767
4768	if (idx >= 0 && idx < rss_key_addr_cnt) {
4769		if (rss_key_addr_cnt > 16)
4770			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
4771				     V_KEYWRADDRX(idx >> 4) |
4772				     V_T6_VFWRADDR(idx) | F_KEYWREN);
4773		else
4774			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
4775				     V_KEYWRADDR(idx) | F_KEYWREN);
4776	}
4777}
4778
4779/**
4780 *	t4_read_rss_pf_config - read PF RSS Configuration Table
4781 *	@adapter: the adapter
4782 *	@index: the entry in the PF RSS table to read
4783 *	@valp: where to store the returned value
4784 *
4785 *	Reads the PF RSS Configuration Table at the specified index and returns
4786 *	the value found there.
4787 */
4788void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4789			   u32 *valp)
4790{
4791	if (t4_use_ldst(adapter))
4792		t4_fw_tp_pio_rw(adapter, valp, 1,
4793				A_TP_RSS_PF0_CONFIG + index, 1);
4794	else
4795		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4796				 valp, 1, A_TP_RSS_PF0_CONFIG + index);
4797}
4798
4799/**
4800 *	t4_write_rss_pf_config - write PF RSS Configuration Table
4801 *	@adapter: the adapter
4802 *	@index: the entry in the VF RSS table to read
4803 *	@val: the value to store
4804 *
4805 *	Writes the PF RSS Configuration Table at the specified index with the
4806 *	specified value.
4807 */
4808void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
4809			    u32 val)
4810{
4811	if (t4_use_ldst(adapter))
4812		t4_fw_tp_pio_rw(adapter, &val, 1,
4813				A_TP_RSS_PF0_CONFIG + index, 0);
4814	else
4815		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4816				  &val, 1, A_TP_RSS_PF0_CONFIG + index);
4817}
4818
4819/**
4820 *	t4_read_rss_vf_config - read VF RSS Configuration Table
4821 *	@adapter: the adapter
4822 *	@index: the entry in the VF RSS table to read
4823 *	@vfl: where to store the returned VFL
4824 *	@vfh: where to store the returned VFH
4825 *
4826 *	Reads the VF RSS Configuration Table at the specified index and returns
4827 *	the (VFL, VFH) values found there.
4828 */
4829void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4830			   u32 *vfl, u32 *vfh)
4831{
4832	u32 vrt, mask, data;
4833
4834	if (chip_id(adapter) <= CHELSIO_T5) {
4835		mask = V_VFWRADDR(M_VFWRADDR);
4836		data = V_VFWRADDR(index);
4837	} else {
4838		 mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
4839		 data = V_T6_VFWRADDR(index);
4840	}
4841	/*
4842	 * Request that the index'th VF Table values be read into VFL/VFH.
4843	 */
4844	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
4845	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
4846	vrt |= data | F_VFRDEN;
4847	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
4848
4849	/*
4850	 * Grab the VFL/VFH values ...
4851	 */
4852	if (t4_use_ldst(adapter)) {
4853		t4_fw_tp_pio_rw(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, 1);
4854		t4_fw_tp_pio_rw(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, 1);
4855	} else {
4856		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4857				 vfl, 1, A_TP_RSS_VFL_CONFIG);
4858		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4859				 vfh, 1, A_TP_RSS_VFH_CONFIG);
4860	}
4861}
4862
4863/**
4864 *	t4_write_rss_vf_config - write VF RSS Configuration Table
4865 *
4866 *	@adapter: the adapter
4867 *	@index: the entry in the VF RSS table to write
4868 *	@vfl: the VFL to store
4869 *	@vfh: the VFH to store
4870 *
4871 *	Writes the VF RSS Configuration Table at the specified index with the
4872 *	specified (VFL, VFH) values.
4873 */
4874void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
4875			    u32 vfl, u32 vfh)
4876{
4877	u32 vrt, mask, data;
4878
4879	if (chip_id(adapter) <= CHELSIO_T5) {
4880		mask = V_VFWRADDR(M_VFWRADDR);
4881		data = V_VFWRADDR(index);
4882	} else {
4883		mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
4884		data = V_T6_VFWRADDR(index);
4885	}
4886
4887	/*
4888	 * Load up VFL/VFH with the values to be written ...
4889	 */
4890	if (t4_use_ldst(adapter)) {
4891		t4_fw_tp_pio_rw(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, 0);
4892		t4_fw_tp_pio_rw(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, 0);
4893	} else {
4894		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4895				  &vfl, 1, A_TP_RSS_VFL_CONFIG);
4896		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4897				  &vfh, 1, A_TP_RSS_VFH_CONFIG);
4898	}
4899
4900	/*
4901	 * Write the VFL/VFH into the VF Table at index'th location.
4902	 */
4903	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
4904	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
4905	vrt |= data | F_VFRDEN;
4906	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
4907}
4908
4909/**
4910 *	t4_read_rss_pf_map - read PF RSS Map
4911 *	@adapter: the adapter
4912 *
4913 *	Reads the PF RSS Map register and returns its value.
4914 */
4915u32 t4_read_rss_pf_map(struct adapter *adapter)
4916{
4917	u32 pfmap;
4918
4919	if (t4_use_ldst(adapter))
4920		t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 1);
4921	else
4922		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4923				 &pfmap, 1, A_TP_RSS_PF_MAP);
4924	return pfmap;
4925}
4926
4927/**
4928 *	t4_write_rss_pf_map - write PF RSS Map
4929 *	@adapter: the adapter
4930 *	@pfmap: PF RSS Map value
4931 *
4932 *	Writes the specified value to the PF RSS Map register.
4933 */
4934void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap)
4935{
4936	if (t4_use_ldst(adapter))
4937		t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 0);
4938	else
4939		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4940				  &pfmap, 1, A_TP_RSS_PF_MAP);
4941}
4942
4943/**
4944 *	t4_read_rss_pf_mask - read PF RSS Mask
4945 *	@adapter: the adapter
4946 *
4947 *	Reads the PF RSS Mask register and returns its value.
4948 */
4949u32 t4_read_rss_pf_mask(struct adapter *adapter)
4950{
4951	u32 pfmask;
4952
4953	if (t4_use_ldst(adapter))
4954		t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 1);
4955	else
4956		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4957				 &pfmask, 1, A_TP_RSS_PF_MSK);
4958	return pfmask;
4959}
4960
4961/**
4962 *	t4_write_rss_pf_mask - write PF RSS Mask
4963 *	@adapter: the adapter
4964 *	@pfmask: PF RSS Mask value
4965 *
4966 *	Writes the specified value to the PF RSS Mask register.
4967 */
4968void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask)
4969{
4970	if (t4_use_ldst(adapter))
4971		t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 0);
4972	else
4973		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4974				  &pfmask, 1, A_TP_RSS_PF_MSK);
4975}
4976
4977/**
4978 *	t4_tp_get_tcp_stats - read TP's TCP MIB counters
4979 *	@adap: the adapter
4980 *	@v4: holds the TCP/IP counter values
4981 *	@v6: holds the TCP/IPv6 counter values
4982 *
4983 *	Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4984 *	Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4985 */
4986void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4987			 struct tp_tcp_stats *v6)
4988{
4989	u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
4990
4991#define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
4992#define STAT(x)     val[STAT_IDX(x)]
4993#define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4994
4995	if (v4) {
4996		t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
4997				 ARRAY_SIZE(val), A_TP_MIB_TCP_OUT_RST);
4998		v4->tcp_out_rsts = STAT(OUT_RST);
4999		v4->tcp_in_segs  = STAT64(IN_SEG);
5000		v4->tcp_out_segs = STAT64(OUT_SEG);
5001		v4->tcp_retrans_segs = STAT64(RXT_SEG);
5002	}
5003	if (v6) {
5004		t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
5005				 ARRAY_SIZE(val), A_TP_MIB_TCP_V6OUT_RST);
5006		v6->tcp_out_rsts = STAT(OUT_RST);
5007		v6->tcp_in_segs  = STAT64(IN_SEG);
5008		v6->tcp_out_segs = STAT64(OUT_SEG);
5009		v6->tcp_retrans_segs = STAT64(RXT_SEG);
5010	}
5011#undef STAT64
5012#undef STAT
5013#undef STAT_IDX
5014}
5015
5016/**
5017 *	t4_tp_get_err_stats - read TP's error MIB counters
5018 *	@adap: the adapter
5019 *	@st: holds the counter values
5020 *
5021 *	Returns the values of TP's error counters.
5022 */
5023void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
5024{
5025	int nchan = adap->chip_params->nchan;
5026
5027	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5028			st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0);
5029	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5030			st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0);
5031	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5032			st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0);
5033	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5034			st->tnl_cong_drops, nchan, A_TP_MIB_TNL_CNG_DROP_0);
5035	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5036			st->ofld_chan_drops, nchan, A_TP_MIB_OFD_CHN_DROP_0);
5037	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5038			st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0);
5039	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5040			st->ofld_vlan_drops, nchan, A_TP_MIB_OFD_VLN_DROP_0);
5041	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5042			st->tcp6_in_errs, nchan, A_TP_MIB_TCP_V6IN_ERR_0);
5043
5044	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5045			 &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP);
5046}
5047
5048/**
5049 *	t4_tp_get_proxy_stats - read TP's proxy MIB counters
5050 *	@adap: the adapter
5051 *	@st: holds the counter values
5052 *
5053 *	Returns the values of TP's proxy counters.
5054 */
5055void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st)
5056{
5057	int nchan = adap->chip_params->nchan;
5058
5059	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->proxy,
5060			 nchan, A_TP_MIB_TNL_LPBK_0);
5061}
5062
5063/**
5064 *	t4_tp_get_cpl_stats - read TP's CPL MIB counters
5065 *	@adap: the adapter
5066 *	@st: holds the counter values
5067 *
5068 *	Returns the values of TP's CPL counters.
5069 */
5070void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
5071{
5072	int nchan = adap->chip_params->nchan;
5073
5074	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->req,
5075			 nchan, A_TP_MIB_CPL_IN_REQ_0);
5076	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->rsp,
5077			 nchan, A_TP_MIB_CPL_OUT_RSP_0);
5078}
5079
5080/**
5081 *	t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5082 *	@adap: the adapter
5083 *	@st: holds the counter values
5084 *
5085 *	Returns the values of TP's RDMA counters.
5086 */
5087void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5088{
5089	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->rqe_dfr_pkt,
5090			 2, A_TP_MIB_RQE_DFR_PKT);
5091}
5092
5093/**
5094 *	t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5095 *	@adap: the adapter
5096 *	@idx: the port index
5097 *	@st: holds the counter values
5098 *
5099 *	Returns the values of TP's FCoE counters for the selected port.
5100 */
5101void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5102		       struct tp_fcoe_stats *st)
5103{
5104	u32 val[2];
5105
5106	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_ddp,
5107			 1, A_TP_MIB_FCOE_DDP_0 + idx);
5108	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_drop,
5109			 1, A_TP_MIB_FCOE_DROP_0 + idx);
5110	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
5111			 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx);
5112	st->octets_ddp = ((u64)val[0] << 32) | val[1];
5113}
5114
5115/**
5116 *	t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5117 *	@adap: the adapter
5118 *	@st: holds the counter values
5119 *
5120 *	Returns the values of TP's counters for non-TCP directly-placed packets.
5121 */
5122void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5123{
5124	u32 val[4];
5125
5126	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 4,
5127			 A_TP_MIB_USM_PKTS);
5128	st->frames = val[0];
5129	st->drops = val[1];
5130	st->octets = ((u64)val[2] << 32) | val[3];
5131}
5132
5133/**
5134 *	t4_read_mtu_tbl - returns the values in the HW path MTU table
5135 *	@adap: the adapter
5136 *	@mtus: where to store the MTU values
5137 *	@mtu_log: where to store the MTU base-2 log (may be %NULL)
5138 *
5139 *	Reads the HW path MTU table.
5140 */
5141void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5142{
5143	u32 v;
5144	int i;
5145
5146	for (i = 0; i < NMTUS; ++i) {
5147		t4_write_reg(adap, A_TP_MTU_TABLE,
5148			     V_MTUINDEX(0xff) | V_MTUVALUE(i));
5149		v = t4_read_reg(adap, A_TP_MTU_TABLE);
5150		mtus[i] = G_MTUVALUE(v);
5151		if (mtu_log)
5152			mtu_log[i] = G_MTUWIDTH(v);
5153	}
5154}
5155
5156/**
5157 *	t4_read_cong_tbl - reads the congestion control table
5158 *	@adap: the adapter
5159 *	@incr: where to store the alpha values
5160 *
5161 *	Reads the additive increments programmed into the HW congestion
5162 *	control table.
5163 */
5164void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5165{
5166	unsigned int mtu, w;
5167
5168	for (mtu = 0; mtu < NMTUS; ++mtu)
5169		for (w = 0; w < NCCTRL_WIN; ++w) {
5170			t4_write_reg(adap, A_TP_CCTRL_TABLE,
5171				     V_ROWINDEX(0xffff) | (mtu << 5) | w);
5172			incr[mtu][w] = (u16)t4_read_reg(adap,
5173						A_TP_CCTRL_TABLE) & 0x1fff;
5174		}
5175}
5176
5177/**
5178 *	t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5179 *	@adap: the adapter
5180 *	@addr: the indirect TP register address
5181 *	@mask: specifies the field within the register to modify
5182 *	@val: new value for the field
5183 *
5184 *	Sets a field of an indirect TP register to the given value.
5185 */
5186void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5187			    unsigned int mask, unsigned int val)
5188{
5189	t4_write_reg(adap, A_TP_PIO_ADDR, addr);
5190	val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
5191	t4_write_reg(adap, A_TP_PIO_DATA, val);
5192}
5193
5194/**
5195 *	init_cong_ctrl - initialize congestion control parameters
5196 *	@a: the alpha values for congestion control
5197 *	@b: the beta values for congestion control
5198 *
5199 *	Initialize the congestion control parameters.
5200 */
5201static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5202{
5203	a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5204	a[9] = 2;
5205	a[10] = 3;
5206	a[11] = 4;
5207	a[12] = 5;
5208	a[13] = 6;
5209	a[14] = 7;
5210	a[15] = 8;
5211	a[16] = 9;
5212	a[17] = 10;
5213	a[18] = 14;
5214	a[19] = 17;
5215	a[20] = 21;
5216	a[21] = 25;
5217	a[22] = 30;
5218	a[23] = 35;
5219	a[24] = 45;
5220	a[25] = 60;
5221	a[26] = 80;
5222	a[27] = 100;
5223	a[28] = 200;
5224	a[29] = 300;
5225	a[30] = 400;
5226	a[31] = 500;
5227
5228	b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5229	b[9] = b[10] = 1;
5230	b[11] = b[12] = 2;
5231	b[13] = b[14] = b[15] = b[16] = 3;
5232	b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5233	b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5234	b[28] = b[29] = 6;
5235	b[30] = b[31] = 7;
5236}
5237
5238/* The minimum additive increment value for the congestion control table */
5239#define CC_MIN_INCR 2U
5240
5241/**
5242 *	t4_load_mtus - write the MTU and congestion control HW tables
5243 *	@adap: the adapter
5244 *	@mtus: the values for the MTU table
5245 *	@alpha: the values for the congestion control alpha parameter
5246 *	@beta: the values for the congestion control beta parameter
5247 *
5248 *	Write the HW MTU table with the supplied MTUs and the high-speed
5249 *	congestion control table with the supplied alpha, beta, and MTUs.
5250 *	We write the two tables together because the additive increments
5251 *	depend on the MTUs.
5252 */
5253void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5254		  const unsigned short *alpha, const unsigned short *beta)
5255{
5256	static const unsigned int avg_pkts[NCCTRL_WIN] = {
5257		2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5258		896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5259		28672, 40960, 57344, 81920, 114688, 163840, 229376
5260	};
5261
5262	unsigned int i, w;
5263
5264	for (i = 0; i < NMTUS; ++i) {
5265		unsigned int mtu = mtus[i];
5266		unsigned int log2 = fls(mtu);
5267
5268		if (!(mtu & ((1 << log2) >> 2)))     /* round */
5269			log2--;
5270		t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
5271			     V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
5272
5273		for (w = 0; w < NCCTRL_WIN; ++w) {
5274			unsigned int inc;
5275
5276			inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5277				  CC_MIN_INCR);
5278
5279			t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
5280				     (w << 16) | (beta[w] << 13) | inc);
5281		}
5282	}
5283}
5284
5285/**
5286 *	t4_set_pace_tbl - set the pace table
5287 *	@adap: the adapter
5288 *	@pace_vals: the pace values in microseconds
5289 *	@start: index of the first entry in the HW pace table to set
5290 *	@n: how many entries to set
5291 *
5292 *	Sets (a subset of the) HW pace table.
5293 */
5294int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
5295		     unsigned int start, unsigned int n)
5296{
5297	unsigned int vals[NTX_SCHED], i;
5298	unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
5299
5300	if (n > NTX_SCHED)
5301	    return -ERANGE;
5302
5303	/* convert values from us to dack ticks, rounding to closest value */
5304	for (i = 0; i < n; i++, pace_vals++) {
5305		vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
5306		if (vals[i] > 0x7ff)
5307			return -ERANGE;
5308		if (*pace_vals && vals[i] == 0)
5309			return -ERANGE;
5310	}
5311	for (i = 0; i < n; i++, start++)
5312		t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
5313	return 0;
5314}
5315
5316/**
5317 *	t4_set_sched_bps - set the bit rate for a HW traffic scheduler
5318 *	@adap: the adapter
5319 *	@kbps: target rate in Kbps
5320 *	@sched: the scheduler index
5321 *
5322 *	Configure a Tx HW scheduler for the target rate.
5323 */
5324int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
5325{
5326	unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
5327	unsigned int clk = adap->params.vpd.cclk * 1000;
5328	unsigned int selected_cpt = 0, selected_bpt = 0;
5329
5330	if (kbps > 0) {
5331		kbps *= 125;     /* -> bytes */
5332		for (cpt = 1; cpt <= 255; cpt++) {
5333			tps = clk / cpt;
5334			bpt = (kbps + tps / 2) / tps;
5335			if (bpt > 0 && bpt <= 255) {
5336				v = bpt * tps;
5337				delta = v >= kbps ? v - kbps : kbps - v;
5338				if (delta < mindelta) {
5339					mindelta = delta;
5340					selected_cpt = cpt;
5341					selected_bpt = bpt;
5342				}
5343			} else if (selected_cpt)
5344				break;
5345		}
5346		if (!selected_cpt)
5347			return -EINVAL;
5348	}
5349	t4_write_reg(adap, A_TP_TM_PIO_ADDR,
5350		     A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
5351	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5352	if (sched & 1)
5353		v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
5354	else
5355		v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
5356	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5357	return 0;
5358}
5359
5360/**
5361 *	t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
5362 *	@adap: the adapter
5363 *	@sched: the scheduler index
5364 *	@ipg: the interpacket delay in tenths of nanoseconds
5365 *
5366 *	Set the interpacket delay for a HW packet rate scheduler.
5367 */
5368int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
5369{
5370	unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
5371
5372	/* convert ipg to nearest number of core clocks */
5373	ipg *= core_ticks_per_usec(adap);
5374	ipg = (ipg + 5000) / 10000;
5375	if (ipg > M_TXTIMERSEPQ0)
5376		return -EINVAL;
5377
5378	t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
5379	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5380	if (sched & 1)
5381		v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
5382	else
5383		v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
5384	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5385	t4_read_reg(adap, A_TP_TM_PIO_DATA);
5386	return 0;
5387}
5388
5389/*
5390 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5391 * clocks.  The formula is
5392 *
5393 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5394 *
5395 * which is equivalent to
5396 *
5397 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5398 */
5399static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5400{
5401	u64 v = bytes256 * adap->params.vpd.cclk;
5402
5403	return v * 62 + v / 2;
5404}
5405
5406/**
5407 *	t4_get_chan_txrate - get the current per channel Tx rates
5408 *	@adap: the adapter
5409 *	@nic_rate: rates for NIC traffic
5410 *	@ofld_rate: rates for offloaded traffic
5411 *
5412 *	Return the current Tx rates in bytes/s for NIC and offloaded traffic
5413 *	for each channel.
5414 */
5415void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5416{
5417	u32 v;
5418
5419	v = t4_read_reg(adap, A_TP_TX_TRATE);
5420	nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
5421	nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
5422	if (adap->chip_params->nchan > 2) {
5423		nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
5424		nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
5425	}
5426
5427	v = t4_read_reg(adap, A_TP_TX_ORATE);
5428	ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
5429	ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
5430	if (adap->chip_params->nchan > 2) {
5431		ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
5432		ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
5433	}
5434}
5435
5436/**
5437 *	t4_set_trace_filter - configure one of the tracing filters
5438 *	@adap: the adapter
5439 *	@tp: the desired trace filter parameters
5440 *	@idx: which filter to configure
5441 *	@enable: whether to enable or disable the filter
5442 *
5443 *	Configures one of the tracing filters available in HW.  If @tp is %NULL
5444 *	it indicates that the filter is already written in the register and it
5445 *	just needs to be enabled or disabled.
5446 */
5447int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5448    int idx, int enable)
5449{
5450	int i, ofst = idx * 4;
5451	u32 data_reg, mask_reg, cfg;
5452	u32 multitrc = F_TRCMULTIFILTER;
5453	u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
5454
5455	if (idx < 0 || idx >= NTRACE)
5456		return -EINVAL;
5457
5458	if (tp == NULL || !enable) {
5459		t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
5460		    enable ? en : 0);
5461		return 0;
5462	}
5463
5464	/*
5465	 * TODO - After T4 data book is updated, specify the exact
5466	 * section below.
5467	 *
5468	 * See T4 data book - MPS section for a complete description
5469	 * of the below if..else handling of A_MPS_TRC_CFG register
5470	 * value.
5471	 */
5472	cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
5473	if (cfg & F_TRCMULTIFILTER) {
5474		/*
5475		 * If multiple tracers are enabled, then maximum
5476		 * capture size is 2.5KB (FIFO size of a single channel)
5477		 * minus 2 flits for CPL_TRACE_PKT header.
5478		 */
5479		if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5480			return -EINVAL;
5481	} else {
5482		/*
5483		 * If multiple tracers are disabled, to avoid deadlocks
5484		 * maximum packet capture size of 9600 bytes is recommended.
5485		 * Also in this mode, only trace0 can be enabled and running.
5486		 */
5487		multitrc = 0;
5488		if (tp->snap_len > 9600 || idx)
5489			return -EINVAL;
5490	}
5491
5492	if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
5493	    tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
5494	    tp->min_len > M_TFMINPKTSIZE)
5495		return -EINVAL;
5496
5497	/* stop the tracer we'll be changing */
5498	t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
5499
5500	idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
5501	data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
5502	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
5503
5504	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5505		t4_write_reg(adap, data_reg, tp->data[i]);
5506		t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5507	}
5508	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
5509		     V_TFCAPTUREMAX(tp->snap_len) |
5510		     V_TFMINPKTSIZE(tp->min_len));
5511	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
5512		     V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
5513		     (is_t4(adap) ?
5514		     V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
5515		     V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
5516
5517	return 0;
5518}
5519
5520/**
5521 *	t4_get_trace_filter - query one of the tracing filters
5522 *	@adap: the adapter
5523 *	@tp: the current trace filter parameters
5524 *	@idx: which trace filter to query
5525 *	@enabled: non-zero if the filter is enabled
5526 *
5527 *	Returns the current settings of one of the HW tracing filters.
5528 */
5529void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5530			 int *enabled)
5531{
5532	u32 ctla, ctlb;
5533	int i, ofst = idx * 4;
5534	u32 data_reg, mask_reg;
5535
5536	ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
5537	ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
5538
5539	if (is_t4(adap)) {
5540		*enabled = !!(ctla & F_TFEN);
5541		tp->port =  G_TFPORT(ctla);
5542		tp->invert = !!(ctla & F_TFINVERTMATCH);
5543	} else {
5544		*enabled = !!(ctla & F_T5_TFEN);
5545		tp->port = G_T5_TFPORT(ctla);
5546		tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
5547	}
5548	tp->snap_len = G_TFCAPTUREMAX(ctlb);
5549	tp->min_len = G_TFMINPKTSIZE(ctlb);
5550	tp->skip_ofst = G_TFOFFSET(ctla);
5551	tp->skip_len = G_TFLENGTH(ctla);
5552
5553	ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
5554	data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
5555	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
5556
5557	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5558		tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5559		tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5560	}
5561}
5562
5563/**
5564 *	t4_pmtx_get_stats - returns the HW stats from PMTX
5565 *	@adap: the adapter
5566 *	@cnt: where to store the count statistics
5567 *	@cycles: where to store the cycle statistics
5568 *
5569 *	Returns performance statistics from PMTX.
5570 */
5571void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5572{
5573	int i;
5574	u32 data[2];
5575
5576	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5577		t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
5578		cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
5579		if (is_t4(adap))
5580			cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
5581		else {
5582			t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
5583					 A_PM_TX_DBG_DATA, data, 2,
5584					 A_PM_TX_DBG_STAT_MSB);
5585			cycles[i] = (((u64)data[0] << 32) | data[1]);
5586		}
5587	}
5588}
5589
5590/**
5591 *	t4_pmrx_get_stats - returns the HW stats from PMRX
5592 *	@adap: the adapter
5593 *	@cnt: where to store the count statistics
5594 *	@cycles: where to store the cycle statistics
5595 *
5596 *	Returns performance statistics from PMRX.
5597 */
5598void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5599{
5600	int i;
5601	u32 data[2];
5602
5603	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5604		t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
5605		cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
5606		if (is_t4(adap)) {
5607			cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
5608		} else {
5609			t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
5610					 A_PM_RX_DBG_DATA, data, 2,
5611					 A_PM_RX_DBG_STAT_MSB);
5612			cycles[i] = (((u64)data[0] << 32) | data[1]);
5613		}
5614	}
5615}
5616
5617/**
5618 *	t4_get_mps_bg_map - return the buffer groups associated with a port
5619 *	@adap: the adapter
5620 *	@idx: the port index
5621 *
5622 *	Returns a bitmap indicating which MPS buffer groups are associated
5623 *	with the given port.  Bit i is set if buffer group i is used by the
5624 *	port.
5625 */
5626static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5627{
5628	u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
5629
5630	if (n == 0)
5631		return idx == 0 ? 0xf : 0;
5632	if (n == 1 && chip_id(adap) <= CHELSIO_T5)
5633		return idx < 2 ? (3 << (2 * idx)) : 0;
5634	return 1 << idx;
5635}
5636
5637/**
5638 *      t4_get_port_type_description - return Port Type string description
5639 *      @port_type: firmware Port Type enumeration
5640 */
5641const char *t4_get_port_type_description(enum fw_port_type port_type)
5642{
5643	static const char *const port_type_description[] = {
5644		"Fiber_XFI",
5645		"Fiber_XAUI",
5646		"BT_SGMII",
5647		"BT_XFI",
5648		"BT_XAUI",
5649		"KX4",
5650		"CX4",
5651		"KX",
5652		"KR",
5653		"SFP",
5654		"BP_AP",
5655		"BP4_AP",
5656		"QSFP_10G",
5657		"QSA",
5658		"QSFP",
5659		"BP40_BA",
5660	};
5661
5662	if (port_type < ARRAY_SIZE(port_type_description))
5663		return port_type_description[port_type];
5664	return "UNKNOWN";
5665}
5666
5667/**
5668 *      t4_get_port_stats_offset - collect port stats relative to a previous
5669 *				   snapshot
5670 *      @adap: The adapter
5671 *      @idx: The port
5672 *      @stats: Current stats to fill
5673 *      @offset: Previous stats snapshot
5674 */
5675void t4_get_port_stats_offset(struct adapter *adap, int idx,
5676		struct port_stats *stats,
5677		struct port_stats *offset)
5678{
5679	u64 *s, *o;
5680	int i;
5681
5682	t4_get_port_stats(adap, idx, stats);
5683	for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
5684			i < (sizeof(struct port_stats)/sizeof(u64)) ;
5685			i++, s++, o++)
5686		*s -= *o;
5687}
5688
5689/**
5690 *	t4_get_port_stats - collect port statistics
5691 *	@adap: the adapter
5692 *	@idx: the port index
5693 *	@p: the stats structure to fill
5694 *
5695 *	Collect statistics related to the given port from HW.
5696 */
5697void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5698{
5699	u32 bgmap = t4_get_mps_bg_map(adap, idx);
5700	u32 stat_ctl;
5701
5702#define GET_STAT(name) \
5703	t4_read_reg64(adap, \
5704	(is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
5705	T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
5706#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
5707
5708	stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
5709
5710	p->tx_pause		= GET_STAT(TX_PORT_PAUSE);
5711	p->tx_octets		= GET_STAT(TX_PORT_BYTES);
5712	p->tx_frames		= GET_STAT(TX_PORT_FRAMES);
5713	p->tx_bcast_frames	= GET_STAT(TX_PORT_BCAST);
5714	p->tx_mcast_frames	= GET_STAT(TX_PORT_MCAST);
5715	p->tx_ucast_frames	= GET_STAT(TX_PORT_UCAST);
5716	p->tx_error_frames	= GET_STAT(TX_PORT_ERROR);
5717	p->tx_frames_64		= GET_STAT(TX_PORT_64B);
5718	p->tx_frames_65_127	= GET_STAT(TX_PORT_65B_127B);
5719	p->tx_frames_128_255	= GET_STAT(TX_PORT_128B_255B);
5720	p->tx_frames_256_511	= GET_STAT(TX_PORT_256B_511B);
5721	p->tx_frames_512_1023	= GET_STAT(TX_PORT_512B_1023B);
5722	p->tx_frames_1024_1518	= GET_STAT(TX_PORT_1024B_1518B);
5723	p->tx_frames_1519_max	= GET_STAT(TX_PORT_1519B_MAX);
5724	p->tx_drop		= GET_STAT(TX_PORT_DROP);
5725	p->tx_ppp0		= GET_STAT(TX_PORT_PPP0);
5726	p->tx_ppp1		= GET_STAT(TX_PORT_PPP1);
5727	p->tx_ppp2		= GET_STAT(TX_PORT_PPP2);
5728	p->tx_ppp3		= GET_STAT(TX_PORT_PPP3);
5729	p->tx_ppp4		= GET_STAT(TX_PORT_PPP4);
5730	p->tx_ppp5		= GET_STAT(TX_PORT_PPP5);
5731	p->tx_ppp6		= GET_STAT(TX_PORT_PPP6);
5732	p->tx_ppp7		= GET_STAT(TX_PORT_PPP7);
5733
5734	if (stat_ctl & F_COUNTPAUSESTATTX) {
5735		p->tx_frames -= p->tx_pause;
5736		p->tx_octets -= p->tx_pause * 64;
5737		p->tx_mcast_frames -= p->tx_pause;
5738	}
5739
5740	p->rx_pause		= GET_STAT(RX_PORT_PAUSE);
5741	p->rx_octets		= GET_STAT(RX_PORT_BYTES);
5742	p->rx_frames		= GET_STAT(RX_PORT_FRAMES);
5743	p->rx_bcast_frames	= GET_STAT(RX_PORT_BCAST);
5744	p->rx_mcast_frames	= GET_STAT(RX_PORT_MCAST);
5745	p->rx_ucast_frames	= GET_STAT(RX_PORT_UCAST);
5746	p->rx_too_long		= GET_STAT(RX_PORT_MTU_ERROR);
5747	p->rx_jabber		= GET_STAT(RX_PORT_MTU_CRC_ERROR);
5748	p->rx_fcs_err		= GET_STAT(RX_PORT_CRC_ERROR);
5749	p->rx_len_err		= GET_STAT(RX_PORT_LEN_ERROR);
5750	p->rx_symbol_err	= GET_STAT(RX_PORT_SYM_ERROR);
5751	p->rx_runt		= GET_STAT(RX_PORT_LESS_64B);
5752	p->rx_frames_64		= GET_STAT(RX_PORT_64B);
5753	p->rx_frames_65_127	= GET_STAT(RX_PORT_65B_127B);
5754	p->rx_frames_128_255	= GET_STAT(RX_PORT_128B_255B);
5755	p->rx_frames_256_511	= GET_STAT(RX_PORT_256B_511B);
5756	p->rx_frames_512_1023	= GET_STAT(RX_PORT_512B_1023B);
5757	p->rx_frames_1024_1518	= GET_STAT(RX_PORT_1024B_1518B);
5758	p->rx_frames_1519_max	= GET_STAT(RX_PORT_1519B_MAX);
5759	p->rx_ppp0		= GET_STAT(RX_PORT_PPP0);
5760	p->rx_ppp1		= GET_STAT(RX_PORT_PPP1);
5761	p->rx_ppp2		= GET_STAT(RX_PORT_PPP2);
5762	p->rx_ppp3		= GET_STAT(RX_PORT_PPP3);
5763	p->rx_ppp4		= GET_STAT(RX_PORT_PPP4);
5764	p->rx_ppp5		= GET_STAT(RX_PORT_PPP5);
5765	p->rx_ppp6		= GET_STAT(RX_PORT_PPP6);
5766	p->rx_ppp7		= GET_STAT(RX_PORT_PPP7);
5767
5768	if (stat_ctl & F_COUNTPAUSESTATRX) {
5769		p->rx_frames -= p->rx_pause;
5770		p->rx_octets -= p->rx_pause * 64;
5771		p->rx_mcast_frames -= p->rx_pause;
5772	}
5773
5774	p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5775	p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5776	p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5777	p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5778	p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5779	p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5780	p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5781	p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5782
5783#undef GET_STAT
5784#undef GET_STAT_COM
5785}
5786
5787/**
5788 *	t4_get_lb_stats - collect loopback port statistics
5789 *	@adap: the adapter
5790 *	@idx: the loopback port index
5791 *	@p: the stats structure to fill
5792 *
5793 *	Return HW statistics for the given loopback port.
5794 */
5795void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5796{
5797	u32 bgmap = t4_get_mps_bg_map(adap, idx);
5798
5799#define GET_STAT(name) \
5800	t4_read_reg64(adap, \
5801	(is_t4(adap) ? \
5802	PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
5803	T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
5804#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
5805
5806	p->octets	= GET_STAT(BYTES);
5807	p->frames	= GET_STAT(FRAMES);
5808	p->bcast_frames	= GET_STAT(BCAST);
5809	p->mcast_frames	= GET_STAT(MCAST);
5810	p->ucast_frames	= GET_STAT(UCAST);
5811	p->error_frames	= GET_STAT(ERROR);
5812
5813	p->frames_64		= GET_STAT(64B);
5814	p->frames_65_127	= GET_STAT(65B_127B);
5815	p->frames_128_255	= GET_STAT(128B_255B);
5816	p->frames_256_511	= GET_STAT(256B_511B);
5817	p->frames_512_1023	= GET_STAT(512B_1023B);
5818	p->frames_1024_1518	= GET_STAT(1024B_1518B);
5819	p->frames_1519_max	= GET_STAT(1519B_MAX);
5820	p->drop			= GET_STAT(DROP_FRAMES);
5821
5822	p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5823	p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5824	p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5825	p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5826	p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5827	p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5828	p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5829	p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5830
5831#undef GET_STAT
5832#undef GET_STAT_COM
5833}
5834
5835/**
5836 *	t4_wol_magic_enable - enable/disable magic packet WoL
5837 *	@adap: the adapter
5838 *	@port: the physical port index
5839 *	@addr: MAC address expected in magic packets, %NULL to disable
5840 *
5841 *	Enables/disables magic packet wake-on-LAN for the selected port.
5842 */
5843void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
5844			 const u8 *addr)
5845{
5846	u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
5847
5848	if (is_t4(adap)) {
5849		mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
5850		mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
5851		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
5852	} else {
5853		mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
5854		mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
5855		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
5856	}
5857
5858	if (addr) {
5859		t4_write_reg(adap, mag_id_reg_l,
5860			     (addr[2] << 24) | (addr[3] << 16) |
5861			     (addr[4] << 8) | addr[5]);
5862		t4_write_reg(adap, mag_id_reg_h,
5863			     (addr[0] << 8) | addr[1]);
5864	}
5865	t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
5866			 V_MAGICEN(addr != NULL));
5867}
5868
5869/**
5870 *	t4_wol_pat_enable - enable/disable pattern-based WoL
5871 *	@adap: the adapter
5872 *	@port: the physical port index
5873 *	@map: bitmap of which HW pattern filters to set
5874 *	@mask0: byte mask for bytes 0-63 of a packet
5875 *	@mask1: byte mask for bytes 64-127 of a packet
5876 *	@crc: Ethernet CRC for selected bytes
5877 *	@enable: enable/disable switch
5878 *
5879 *	Sets the pattern filters indicated in @map to mask out the bytes
5880 *	specified in @mask0/@mask1 in received packets and compare the CRC of
5881 *	the resulting packet against @crc.  If @enable is %true pattern-based
5882 *	WoL is enabled, otherwise disabled.
5883 */
5884int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
5885		      u64 mask0, u64 mask1, unsigned int crc, bool enable)
5886{
5887	int i;
5888	u32 port_cfg_reg;
5889
5890	if (is_t4(adap))
5891		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
5892	else
5893		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
5894
5895	if (!enable) {
5896		t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
5897		return 0;
5898	}
5899	if (map > 0xff)
5900		return -EINVAL;
5901
5902#define EPIO_REG(name) \
5903	(is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
5904	T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
5905
5906	t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
5907	t4_write_reg(adap, EPIO_REG(DATA2), mask1);
5908	t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
5909
5910	for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
5911		if (!(map & 1))
5912			continue;
5913
5914		/* write byte masks */
5915		t4_write_reg(adap, EPIO_REG(DATA0), mask0);
5916		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
5917		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
5918		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
5919			return -ETIMEDOUT;
5920
5921		/* write CRC */
5922		t4_write_reg(adap, EPIO_REG(DATA0), crc);
5923		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
5924		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
5925		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
5926			return -ETIMEDOUT;
5927	}
5928#undef EPIO_REG
5929
5930	t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
5931	return 0;
5932}
5933
5934/*     t4_mk_filtdelwr - create a delete filter WR
5935 *     @ftid: the filter ID
5936 *     @wr: the filter work request to populate
5937 *     @qid: ingress queue to receive the delete notification
5938 *
5939 *     Creates a filter work request to delete the supplied filter.  If @qid is
5940 *     negative the delete notification is suppressed.
5941 */
5942void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5943{
5944	memset(wr, 0, sizeof(*wr));
5945	wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
5946	wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
5947	wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
5948				    V_FW_FILTER_WR_NOREPLY(qid < 0));
5949	wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
5950	if (qid >= 0)
5951		wr->rx_chan_rx_rpl_iq =
5952				cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
5953}
5954
5955#define INIT_CMD(var, cmd, rd_wr) do { \
5956	(var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
5957					F_FW_CMD_REQUEST | \
5958					F_FW_CMD_##rd_wr); \
5959	(var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5960} while (0)
5961
5962int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5963			  u32 addr, u32 val)
5964{
5965	u32 ldst_addrspace;
5966	struct fw_ldst_cmd c;
5967
5968	memset(&c, 0, sizeof(c));
5969	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
5970	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5971					F_FW_CMD_REQUEST |
5972					F_FW_CMD_WRITE |
5973					ldst_addrspace);
5974	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5975	c.u.addrval.addr = cpu_to_be32(addr);
5976	c.u.addrval.val = cpu_to_be32(val);
5977
5978	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5979}
5980
5981/**
5982 *	t4_mdio_rd - read a PHY register through MDIO
5983 *	@adap: the adapter
5984 *	@mbox: mailbox to use for the FW command
5985 *	@phy_addr: the PHY address
5986 *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
5987 *	@reg: the register to read
5988 *	@valp: where to store the value
5989 *
5990 *	Issues a FW command through the given mailbox to read a PHY register.
5991 */
5992int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5993	       unsigned int mmd, unsigned int reg, unsigned int *valp)
5994{
5995	int ret;
5996	u32 ldst_addrspace;
5997	struct fw_ldst_cmd c;
5998
5999	memset(&c, 0, sizeof(c));
6000	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
6001	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6002					F_FW_CMD_REQUEST | F_FW_CMD_READ |
6003					ldst_addrspace);
6004	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6005	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
6006					 V_FW_LDST_CMD_MMD(mmd));
6007	c.u.mdio.raddr = cpu_to_be16(reg);
6008
6009	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6010	if (ret == 0)
6011		*valp = be16_to_cpu(c.u.mdio.rval);
6012	return ret;
6013}
6014
6015/**
6016 *	t4_mdio_wr - write a PHY register through MDIO
6017 *	@adap: the adapter
6018 *	@mbox: mailbox to use for the FW command
6019 *	@phy_addr: the PHY address
6020 *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
6021 *	@reg: the register to write
6022 *	@valp: value to write
6023 *
6024 *	Issues a FW command through the given mailbox to write a PHY register.
6025 */
6026int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6027	       unsigned int mmd, unsigned int reg, unsigned int val)
6028{
6029	u32 ldst_addrspace;
6030	struct fw_ldst_cmd c;
6031
6032	memset(&c, 0, sizeof(c));
6033	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
6034	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6035					F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6036					ldst_addrspace);
6037	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6038	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
6039					 V_FW_LDST_CMD_MMD(mmd));
6040	c.u.mdio.raddr = cpu_to_be16(reg);
6041	c.u.mdio.rval = cpu_to_be16(val);
6042
6043	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6044}
6045
6046/**
6047 *
6048 *	t4_sge_decode_idma_state - decode the idma state
6049 *	@adap: the adapter
6050 *	@state: the state idma is stuck in
6051 */
6052void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6053{
6054	static const char * const t4_decode[] = {
6055		"IDMA_IDLE",
6056		"IDMA_PUSH_MORE_CPL_FIFO",
6057		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6058		"Not used",
6059		"IDMA_PHYSADDR_SEND_PCIEHDR",
6060		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6061		"IDMA_PHYSADDR_SEND_PAYLOAD",
6062		"IDMA_SEND_FIFO_TO_IMSG",
6063		"IDMA_FL_REQ_DATA_FL_PREP",
6064		"IDMA_FL_REQ_DATA_FL",
6065		"IDMA_FL_DROP",
6066		"IDMA_FL_H_REQ_HEADER_FL",
6067		"IDMA_FL_H_SEND_PCIEHDR",
6068		"IDMA_FL_H_PUSH_CPL_FIFO",
6069		"IDMA_FL_H_SEND_CPL",
6070		"IDMA_FL_H_SEND_IP_HDR_FIRST",
6071		"IDMA_FL_H_SEND_IP_HDR",
6072		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
6073		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
6074		"IDMA_FL_H_SEND_IP_HDR_PADDING",
6075		"IDMA_FL_D_SEND_PCIEHDR",
6076		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6077		"IDMA_FL_D_REQ_NEXT_DATA_FL",
6078		"IDMA_FL_SEND_PCIEHDR",
6079		"IDMA_FL_PUSH_CPL_FIFO",
6080		"IDMA_FL_SEND_CPL",
6081		"IDMA_FL_SEND_PAYLOAD_FIRST",
6082		"IDMA_FL_SEND_PAYLOAD",
6083		"IDMA_FL_REQ_NEXT_DATA_FL",
6084		"IDMA_FL_SEND_NEXT_PCIEHDR",
6085		"IDMA_FL_SEND_PADDING",
6086		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
6087		"IDMA_FL_SEND_FIFO_TO_IMSG",
6088		"IDMA_FL_REQ_DATAFL_DONE",
6089		"IDMA_FL_REQ_HEADERFL_DONE",
6090	};
6091	static const char * const t5_decode[] = {
6092		"IDMA_IDLE",
6093		"IDMA_ALMOST_IDLE",
6094		"IDMA_PUSH_MORE_CPL_FIFO",
6095		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6096		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6097		"IDMA_PHYSADDR_SEND_PCIEHDR",
6098		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6099		"IDMA_PHYSADDR_SEND_PAYLOAD",
6100		"IDMA_SEND_FIFO_TO_IMSG",
6101		"IDMA_FL_REQ_DATA_FL",
6102		"IDMA_FL_DROP",
6103		"IDMA_FL_DROP_SEND_INC",
6104		"IDMA_FL_H_REQ_HEADER_FL",
6105		"IDMA_FL_H_SEND_PCIEHDR",
6106		"IDMA_FL_H_PUSH_CPL_FIFO",
6107		"IDMA_FL_H_SEND_CPL",
6108		"IDMA_FL_H_SEND_IP_HDR_FIRST",
6109		"IDMA_FL_H_SEND_IP_HDR",
6110		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
6111		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
6112		"IDMA_FL_H_SEND_IP_HDR_PADDING",
6113		"IDMA_FL_D_SEND_PCIEHDR",
6114		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6115		"IDMA_FL_D_REQ_NEXT_DATA_FL",
6116		"IDMA_FL_SEND_PCIEHDR",
6117		"IDMA_FL_PUSH_CPL_FIFO",
6118		"IDMA_FL_SEND_CPL",
6119		"IDMA_FL_SEND_PAYLOAD_FIRST",
6120		"IDMA_FL_SEND_PAYLOAD",
6121		"IDMA_FL_REQ_NEXT_DATA_FL",
6122		"IDMA_FL_SEND_NEXT_PCIEHDR",
6123		"IDMA_FL_SEND_PADDING",
6124		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
6125	};
6126	static const char * const t6_decode[] = {
6127		"IDMA_IDLE",
6128		"IDMA_PUSH_MORE_CPL_FIFO",
6129		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6130		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6131		"IDMA_PHYSADDR_SEND_PCIEHDR",
6132		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6133		"IDMA_PHYSADDR_SEND_PAYLOAD",
6134		"IDMA_FL_REQ_DATA_FL",
6135		"IDMA_FL_DROP",
6136		"IDMA_FL_DROP_SEND_INC",
6137		"IDMA_FL_H_REQ_HEADER_FL",
6138		"IDMA_FL_H_SEND_PCIEHDR",
6139		"IDMA_FL_H_PUSH_CPL_FIFO",
6140		"IDMA_FL_H_SEND_CPL",
6141		"IDMA_FL_H_SEND_IP_HDR_FIRST",
6142		"IDMA_FL_H_SEND_IP_HDR",
6143		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
6144		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
6145		"IDMA_FL_H_SEND_IP_HDR_PADDING",
6146		"IDMA_FL_D_SEND_PCIEHDR",
6147		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6148		"IDMA_FL_D_REQ_NEXT_DATA_FL",
6149		"IDMA_FL_SEND_PCIEHDR",
6150		"IDMA_FL_PUSH_CPL_FIFO",
6151		"IDMA_FL_SEND_CPL",
6152		"IDMA_FL_SEND_PAYLOAD_FIRST",
6153		"IDMA_FL_SEND_PAYLOAD",
6154		"IDMA_FL_REQ_NEXT_DATA_FL",
6155		"IDMA_FL_SEND_NEXT_PCIEHDR",
6156		"IDMA_FL_SEND_PADDING",
6157		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
6158	};
6159	static const u32 sge_regs[] = {
6160		A_SGE_DEBUG_DATA_LOW_INDEX_2,
6161		A_SGE_DEBUG_DATA_LOW_INDEX_3,
6162		A_SGE_DEBUG_DATA_HIGH_INDEX_10,
6163	};
6164	const char * const *sge_idma_decode;
6165	int sge_idma_decode_nstates;
6166	int i;
6167	unsigned int chip_version = chip_id(adapter);
6168
6169	/* Select the right set of decode strings to dump depending on the
6170	 * adapter chip type.
6171	 */
6172	switch (chip_version) {
6173	case CHELSIO_T4:
6174		sge_idma_decode = (const char * const *)t4_decode;
6175		sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6176		break;
6177
6178	case CHELSIO_T5:
6179		sge_idma_decode = (const char * const *)t5_decode;
6180		sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6181		break;
6182
6183	case CHELSIO_T6:
6184		sge_idma_decode = (const char * const *)t6_decode;
6185		sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6186		break;
6187
6188	default:
6189		CH_ERR(adapter,	"Unsupported chip version %d\n", chip_version);
6190		return;
6191	}
6192
6193	if (state < sge_idma_decode_nstates)
6194		CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6195	else
6196		CH_WARN(adapter, "idma state %d unknown\n", state);
6197
6198	for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6199		CH_WARN(adapter, "SGE register %#x value %#x\n",
6200			sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6201}
6202
6203/**
6204 *      t4_sge_ctxt_flush - flush the SGE context cache
6205 *      @adap: the adapter
6206 *      @mbox: mailbox to use for the FW command
6207 *
6208 *      Issues a FW command through the given mailbox to flush the
6209 *      SGE context cache.
6210 */
6211int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6212{
6213	int ret;
6214	u32 ldst_addrspace;
6215	struct fw_ldst_cmd c;
6216
6217	memset(&c, 0, sizeof(c));
6218	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC);
6219	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6220					F_FW_CMD_REQUEST | F_FW_CMD_READ |
6221					ldst_addrspace);
6222	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6223	c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
6224
6225	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6226	return ret;
6227}
6228
6229/**
6230 *      t4_fw_hello - establish communication with FW
6231 *      @adap: the adapter
6232 *      @mbox: mailbox to use for the FW command
6233 *      @evt_mbox: mailbox to receive async FW events
6234 *      @master: specifies the caller's willingness to be the device master
6235 *	@state: returns the current device state (if non-NULL)
6236 *
6237 *	Issues a command to establish communication with FW.  Returns either
6238 *	an error (negative integer) or the mailbox of the Master PF.
6239 */
6240int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6241		enum dev_master master, enum dev_state *state)
6242{
6243	int ret;
6244	struct fw_hello_cmd c;
6245	u32 v;
6246	unsigned int master_mbox;
6247	int retries = FW_CMD_HELLO_RETRIES;
6248
6249retry:
6250	memset(&c, 0, sizeof(c));
6251	INIT_CMD(c, HELLO, WRITE);
6252	c.err_to_clearinit = cpu_to_be32(
6253		V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
6254		V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
6255		V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
6256					mbox : M_FW_HELLO_CMD_MBMASTER) |
6257		V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
6258		V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
6259		F_FW_HELLO_CMD_CLEARINIT);
6260
6261	/*
6262	 * Issue the HELLO command to the firmware.  If it's not successful
6263	 * but indicates that we got a "busy" or "timeout" condition, retry
6264	 * the HELLO until we exhaust our retry limit.  If we do exceed our
6265	 * retry limit, check to see if the firmware left us any error
6266	 * information and report that if so ...
6267	 */
6268	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6269	if (ret != FW_SUCCESS) {
6270		if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6271			goto retry;
6272		if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
6273			t4_report_fw_error(adap);
6274		return ret;
6275	}
6276
6277	v = be32_to_cpu(c.err_to_clearinit);
6278	master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
6279	if (state) {
6280		if (v & F_FW_HELLO_CMD_ERR)
6281			*state = DEV_STATE_ERR;
6282		else if (v & F_FW_HELLO_CMD_INIT)
6283			*state = DEV_STATE_INIT;
6284		else
6285			*state = DEV_STATE_UNINIT;
6286	}
6287
6288	/*
6289	 * If we're not the Master PF then we need to wait around for the
6290	 * Master PF Driver to finish setting up the adapter.
6291	 *
6292	 * Note that we also do this wait if we're a non-Master-capable PF and
6293	 * there is no current Master PF; a Master PF may show up momentarily
6294	 * and we wouldn't want to fail pointlessly.  (This can happen when an
6295	 * OS loads lots of different drivers rapidly at the same time).  In
6296	 * this case, the Master PF returned by the firmware will be
6297	 * M_PCIE_FW_MASTER so the test below will work ...
6298	 */
6299	if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
6300	    master_mbox != mbox) {
6301		int waiting = FW_CMD_HELLO_TIMEOUT;
6302
6303		/*
6304		 * Wait for the firmware to either indicate an error or
6305		 * initialized state.  If we see either of these we bail out
6306		 * and report the issue to the caller.  If we exhaust the
6307		 * "hello timeout" and we haven't exhausted our retries, try
6308		 * again.  Otherwise bail with a timeout error.
6309		 */
6310		for (;;) {
6311			u32 pcie_fw;
6312
6313			msleep(50);
6314			waiting -= 50;
6315
6316			/*
6317			 * If neither Error nor Initialialized are indicated
6318			 * by the firmware keep waiting till we exhaust our
6319			 * timeout ... and then retry if we haven't exhausted
6320			 * our retries ...
6321			 */
6322			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
6323			if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
6324				if (waiting <= 0) {
6325					if (retries-- > 0)
6326						goto retry;
6327
6328					return -ETIMEDOUT;
6329				}
6330				continue;
6331			}
6332
6333			/*
6334			 * We either have an Error or Initialized condition
6335			 * report errors preferentially.
6336			 */
6337			if (state) {
6338				if (pcie_fw & F_PCIE_FW_ERR)
6339					*state = DEV_STATE_ERR;
6340				else if (pcie_fw & F_PCIE_FW_INIT)
6341					*state = DEV_STATE_INIT;
6342			}
6343
6344			/*
6345			 * If we arrived before a Master PF was selected and
6346			 * there's not a valid Master PF, grab its identity
6347			 * for our caller.
6348			 */
6349			if (master_mbox == M_PCIE_FW_MASTER &&
6350			    (pcie_fw & F_PCIE_FW_MASTER_VLD))
6351				master_mbox = G_PCIE_FW_MASTER(pcie_fw);
6352			break;
6353		}
6354	}
6355
6356	return master_mbox;
6357}
6358
6359/**
6360 *	t4_fw_bye - end communication with FW
6361 *	@adap: the adapter
6362 *	@mbox: mailbox to use for the FW command
6363 *
6364 *	Issues a command to terminate communication with FW.
6365 */
6366int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6367{
6368	struct fw_bye_cmd c;
6369
6370	memset(&c, 0, sizeof(c));
6371	INIT_CMD(c, BYE, WRITE);
6372	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6373}
6374
6375/**
6376 *	t4_fw_reset - issue a reset to FW
6377 *	@adap: the adapter
6378 *	@mbox: mailbox to use for the FW command
6379 *	@reset: specifies the type of reset to perform
6380 *
6381 *	Issues a reset command of the specified type to FW.
6382 */
6383int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6384{
6385	struct fw_reset_cmd c;
6386
6387	memset(&c, 0, sizeof(c));
6388	INIT_CMD(c, RESET, WRITE);
6389	c.val = cpu_to_be32(reset);
6390	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6391}
6392
6393/**
6394 *	t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6395 *	@adap: the adapter
6396 *	@mbox: mailbox to use for the FW RESET command (if desired)
6397 *	@force: force uP into RESET even if FW RESET command fails
6398 *
6399 *	Issues a RESET command to firmware (if desired) with a HALT indication
6400 *	and then puts the microprocessor into RESET state.  The RESET command
6401 *	will only be issued if a legitimate mailbox is provided (mbox <=
6402 *	M_PCIE_FW_MASTER).
6403 *
6404 *	This is generally used in order for the host to safely manipulate the
6405 *	adapter without fear of conflicting with whatever the firmware might
6406 *	be doing.  The only way out of this state is to RESTART the firmware
6407 *	...
6408 */
6409int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6410{
6411	int ret = 0;
6412
6413	/*
6414	 * If a legitimate mailbox is provided, issue a RESET command
6415	 * with a HALT indication.
6416	 */
6417	if (mbox <= M_PCIE_FW_MASTER) {
6418		struct fw_reset_cmd c;
6419
6420		memset(&c, 0, sizeof(c));
6421		INIT_CMD(c, RESET, WRITE);
6422		c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
6423		c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
6424		ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6425	}
6426
6427	/*
6428	 * Normally we won't complete the operation if the firmware RESET
6429	 * command fails but if our caller insists we'll go ahead and put the
6430	 * uP into RESET.  This can be useful if the firmware is hung or even
6431	 * missing ...  We'll have to take the risk of putting the uP into
6432	 * RESET without the cooperation of firmware in that case.
6433	 *
6434	 * We also force the firmware's HALT flag to be on in case we bypassed
6435	 * the firmware RESET command above or we're dealing with old firmware
6436	 * which doesn't have the HALT capability.  This will serve as a flag
6437	 * for the incoming firmware to know that it's coming out of a HALT
6438	 * rather than a RESET ... if it's new enough to understand that ...
6439	 */
6440	if (ret == 0 || force) {
6441		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
6442		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
6443				 F_PCIE_FW_HALT);
6444	}
6445
6446	/*
6447	 * And we always return the result of the firmware RESET command
6448	 * even when we force the uP into RESET ...
6449	 */
6450	return ret;
6451}
6452
6453/**
6454 *	t4_fw_restart - restart the firmware by taking the uP out of RESET
6455 *	@adap: the adapter
6456 *	@reset: if we want to do a RESET to restart things
6457 *
6458 *	Restart firmware previously halted by t4_fw_halt().  On successful
6459 *	return the previous PF Master remains as the new PF Master and there
6460 *	is no need to issue a new HELLO command, etc.
6461 *
6462 *	We do this in two ways:
6463 *
6464 *	 1. If we're dealing with newer firmware we'll simply want to take
6465 *	    the chip's microprocessor out of RESET.  This will cause the
6466 *	    firmware to start up from its start vector.  And then we'll loop
6467 *	    until the firmware indicates it's started again (PCIE_FW.HALT
6468 *	    reset to 0) or we timeout.
6469 *
6470 *	 2. If we're dealing with older firmware then we'll need to RESET
6471 *	    the chip since older firmware won't recognize the PCIE_FW.HALT
6472 *	    flag and automatically RESET itself on startup.
6473 */
6474int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6475{
6476	if (reset) {
6477		/*
6478		 * Since we're directing the RESET instead of the firmware
6479		 * doing it automatically, we need to clear the PCIE_FW.HALT
6480		 * bit.
6481		 */
6482		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
6483
6484		/*
6485		 * If we've been given a valid mailbox, first try to get the
6486		 * firmware to do the RESET.  If that works, great and we can
6487		 * return success.  Otherwise, if we haven't been given a
6488		 * valid mailbox or the RESET command failed, fall back to
6489		 * hitting the chip with a hammer.
6490		 */
6491		if (mbox <= M_PCIE_FW_MASTER) {
6492			t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6493			msleep(100);
6494			if (t4_fw_reset(adap, mbox,
6495					F_PIORST | F_PIORSTMODE) == 0)
6496				return 0;
6497		}
6498
6499		t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
6500		msleep(2000);
6501	} else {
6502		int ms;
6503
6504		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6505		for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6506			if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
6507				return FW_SUCCESS;
6508			msleep(100);
6509			ms += 100;
6510		}
6511		return -ETIMEDOUT;
6512	}
6513	return 0;
6514}
6515
6516/**
6517 *	t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6518 *	@adap: the adapter
6519 *	@mbox: mailbox to use for the FW RESET command (if desired)
6520 *	@fw_data: the firmware image to write
6521 *	@size: image size
6522 *	@force: force upgrade even if firmware doesn't cooperate
6523 *
6524 *	Perform all of the steps necessary for upgrading an adapter's
6525 *	firmware image.  Normally this requires the cooperation of the
6526 *	existing firmware in order to halt all existing activities
6527 *	but if an invalid mailbox token is passed in we skip that step
6528 *	(though we'll still put the adapter microprocessor into RESET in
6529 *	that case).
6530 *
6531 *	On successful return the new firmware will have been loaded and
6532 *	the adapter will have been fully RESET losing all previous setup
6533 *	state.  On unsuccessful return the adapter may be completely hosed ...
6534 *	positive errno indicates that the adapter is ~probably~ intact, a
6535 *	negative errno indicates that things are looking bad ...
6536 */
6537int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6538		  const u8 *fw_data, unsigned int size, int force)
6539{
6540	const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6541	unsigned int bootstrap =
6542	    be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
6543	int reset, ret;
6544
6545	if (!t4_fw_matches_chip(adap, fw_hdr))
6546		return -EINVAL;
6547
6548	if (!bootstrap) {
6549		ret = t4_fw_halt(adap, mbox, force);
6550		if (ret < 0 && !force)
6551			return ret;
6552	}
6553
6554	ret = t4_load_fw(adap, fw_data, size);
6555	if (ret < 0 || bootstrap)
6556		return ret;
6557
6558	/*
6559	 * Older versions of the firmware don't understand the new
6560	 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6561	 * restart.  So for newly loaded older firmware we'll have to do the
6562	 * RESET for it so it starts up on a clean slate.  We can tell if
6563	 * the newly loaded firmware will handle this right by checking
6564	 * its header flags to see if it advertises the capability.
6565	 */
6566	reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6567	return t4_fw_restart(adap, mbox, reset);
6568}
6569
6570/**
6571 *	t4_fw_initialize - ask FW to initialize the device
6572 *	@adap: the adapter
6573 *	@mbox: mailbox to use for the FW command
6574 *
6575 *	Issues a command to FW to partially initialize the device.  This
6576 *	performs initialization that generally doesn't depend on user input.
6577 */
6578int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6579{
6580	struct fw_initialize_cmd c;
6581
6582	memset(&c, 0, sizeof(c));
6583	INIT_CMD(c, INITIALIZE, WRITE);
6584	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6585}
6586
6587/**
6588 *	t4_query_params_rw - query FW or device parameters
6589 *	@adap: the adapter
6590 *	@mbox: mailbox to use for the FW command
6591 *	@pf: the PF
6592 *	@vf: the VF
6593 *	@nparams: the number of parameters
6594 *	@params: the parameter names
6595 *	@val: the parameter values
6596 *	@rw: Write and read flag
6597 *
6598 *	Reads the value of FW or device parameters.  Up to 7 parameters can be
6599 *	queried at once.
6600 */
6601int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6602		       unsigned int vf, unsigned int nparams, const u32 *params,
6603		       u32 *val, int rw)
6604{
6605	int i, ret;
6606	struct fw_params_cmd c;
6607	__be32 *p = &c.param[0].mnem;
6608
6609	if (nparams > 7)
6610		return -EINVAL;
6611
6612	memset(&c, 0, sizeof(c));
6613	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6614				  F_FW_CMD_REQUEST | F_FW_CMD_READ |
6615				  V_FW_PARAMS_CMD_PFN(pf) |
6616				  V_FW_PARAMS_CMD_VFN(vf));
6617	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6618
6619	for (i = 0; i < nparams; i++) {
6620		*p++ = cpu_to_be32(*params++);
6621		if (rw)
6622			*p = cpu_to_be32(*(val + i));
6623		p++;
6624	}
6625
6626	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6627	if (ret == 0)
6628		for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6629			*val++ = be32_to_cpu(*p);
6630	return ret;
6631}
6632
6633int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6634		    unsigned int vf, unsigned int nparams, const u32 *params,
6635		    u32 *val)
6636{
6637	return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6638}
6639
6640/**
6641 *      t4_set_params_timeout - sets FW or device parameters
6642 *      @adap: the adapter
6643 *      @mbox: mailbox to use for the FW command
6644 *      @pf: the PF
6645 *      @vf: the VF
6646 *      @nparams: the number of parameters
6647 *      @params: the parameter names
6648 *      @val: the parameter values
6649 *      @timeout: the timeout time
6650 *
6651 *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6652 *      specified at once.
6653 */
6654int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6655			  unsigned int pf, unsigned int vf,
6656			  unsigned int nparams, const u32 *params,
6657			  const u32 *val, int timeout)
6658{
6659	struct fw_params_cmd c;
6660	__be32 *p = &c.param[0].mnem;
6661
6662	if (nparams > 7)
6663		return -EINVAL;
6664
6665	memset(&c, 0, sizeof(c));
6666	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6667				  F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6668				  V_FW_PARAMS_CMD_PFN(pf) |
6669				  V_FW_PARAMS_CMD_VFN(vf));
6670	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6671
6672	while (nparams--) {
6673		*p++ = cpu_to_be32(*params++);
6674		*p++ = cpu_to_be32(*val++);
6675	}
6676
6677	return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6678}
6679
6680/**
6681 *	t4_set_params - sets FW or device parameters
6682 *	@adap: the adapter
6683 *	@mbox: mailbox to use for the FW command
6684 *	@pf: the PF
6685 *	@vf: the VF
6686 *	@nparams: the number of parameters
6687 *	@params: the parameter names
6688 *	@val: the parameter values
6689 *
6690 *	Sets the value of FW or device parameters.  Up to 7 parameters can be
6691 *	specified at once.
6692 */
6693int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6694		  unsigned int vf, unsigned int nparams, const u32 *params,
6695		  const u32 *val)
6696{
6697	return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6698				     FW_CMD_MAX_TIMEOUT);
6699}
6700
6701/**
6702 *	t4_cfg_pfvf - configure PF/VF resource limits
6703 *	@adap: the adapter
6704 *	@mbox: mailbox to use for the FW command
6705 *	@pf: the PF being configured
6706 *	@vf: the VF being configured
6707 *	@txq: the max number of egress queues
6708 *	@txq_eth_ctrl: the max number of egress Ethernet or control queues
6709 *	@rxqi: the max number of interrupt-capable ingress queues
6710 *	@rxq: the max number of interruptless ingress queues
6711 *	@tc: the PCI traffic class
6712 *	@vi: the max number of virtual interfaces
6713 *	@cmask: the channel access rights mask for the PF/VF
6714 *	@pmask: the port access rights mask for the PF/VF
6715 *	@nexact: the maximum number of exact MPS filters
6716 *	@rcaps: read capabilities
6717 *	@wxcaps: write/execute capabilities
6718 *
6719 *	Configures resource limits and capabilities for a physical or virtual
6720 *	function.
6721 */
6722int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6723		unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6724		unsigned int rxqi, unsigned int rxq, unsigned int tc,
6725		unsigned int vi, unsigned int cmask, unsigned int pmask,
6726		unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6727{
6728	struct fw_pfvf_cmd c;
6729
6730	memset(&c, 0, sizeof(c));
6731	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
6732				  F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
6733				  V_FW_PFVF_CMD_VFN(vf));
6734	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6735	c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
6736				     V_FW_PFVF_CMD_NIQ(rxq));
6737	c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
6738				    V_FW_PFVF_CMD_PMASK(pmask) |
6739				    V_FW_PFVF_CMD_NEQ(txq));
6740	c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
6741				      V_FW_PFVF_CMD_NVI(vi) |
6742				      V_FW_PFVF_CMD_NEXACTF(nexact));
6743	c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
6744				     V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
6745				     V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
6746	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6747}
6748
6749/**
6750 *	t4_alloc_vi_func - allocate a virtual interface
6751 *	@adap: the adapter
6752 *	@mbox: mailbox to use for the FW command
6753 *	@port: physical port associated with the VI
6754 *	@pf: the PF owning the VI
6755 *	@vf: the VF owning the VI
6756 *	@nmac: number of MAC addresses needed (1 to 5)
6757 *	@mac: the MAC addresses of the VI
6758 *	@rss_size: size of RSS table slice associated with this VI
6759 *	@portfunc: which Port Application Function MAC Address is desired
6760 *	@idstype: Intrusion Detection Type
6761 *
6762 *	Allocates a virtual interface for the given physical port.  If @mac is
6763 *	not %NULL it contains the MAC addresses of the VI as assigned by FW.
6764 *	If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
6765 *	@mac should be large enough to hold @nmac Ethernet addresses, they are
6766 *	stored consecutively so the space needed is @nmac * 6 bytes.
6767 *	Returns a negative error number or the non-negative VI id.
6768 */
6769int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
6770		     unsigned int port, unsigned int pf, unsigned int vf,
6771		     unsigned int nmac, u8 *mac, u16 *rss_size,
6772		     unsigned int portfunc, unsigned int idstype)
6773{
6774	int ret;
6775	struct fw_vi_cmd c;
6776
6777	memset(&c, 0, sizeof(c));
6778	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
6779				  F_FW_CMD_WRITE | F_FW_CMD_EXEC |
6780				  V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
6781	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
6782	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
6783				     V_FW_VI_CMD_FUNC(portfunc));
6784	c.portid_pkd = V_FW_VI_CMD_PORTID(port);
6785	c.nmac = nmac - 1;
6786	if(!rss_size)
6787		c.norss_rsssize = F_FW_VI_CMD_NORSS;
6788
6789	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6790	if (ret)
6791		return ret;
6792
6793	if (mac) {
6794		memcpy(mac, c.mac, sizeof(c.mac));
6795		switch (nmac) {
6796		case 5:
6797			memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6798		case 4:
6799			memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6800		case 3:
6801			memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6802		case 2:
6803			memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
6804		}
6805	}
6806	if (rss_size)
6807		*rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
6808	return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
6809}
6810
6811/**
6812 *      t4_alloc_vi - allocate an [Ethernet Function] virtual interface
6813 *      @adap: the adapter
6814 *      @mbox: mailbox to use for the FW command
6815 *      @port: physical port associated with the VI
6816 *      @pf: the PF owning the VI
6817 *      @vf: the VF owning the VI
6818 *      @nmac: number of MAC addresses needed (1 to 5)
6819 *      @mac: the MAC addresses of the VI
6820 *      @rss_size: size of RSS table slice associated with this VI
6821 *
6822 *	backwards compatible and convieniance routine to allocate a Virtual
6823 *	Interface with a Ethernet Port Application Function and Intrustion
6824 *	Detection System disabled.
6825 */
6826int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6827		unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6828		u16 *rss_size)
6829{
6830	return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
6831				FW_VI_FUNC_ETH, 0);
6832}
6833
6834/**
6835 * 	t4_free_vi - free a virtual interface
6836 * 	@adap: the adapter
6837 * 	@mbox: mailbox to use for the FW command
6838 * 	@pf: the PF owning the VI
6839 * 	@vf: the VF owning the VI
6840 * 	@viid: virtual interface identifiler
6841 *
6842 * 	Free a previously allocated virtual interface.
6843 */
6844int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6845	       unsigned int vf, unsigned int viid)
6846{
6847	struct fw_vi_cmd c;
6848
6849	memset(&c, 0, sizeof(c));
6850	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
6851				  F_FW_CMD_REQUEST |
6852				  F_FW_CMD_EXEC |
6853				  V_FW_VI_CMD_PFN(pf) |
6854				  V_FW_VI_CMD_VFN(vf));
6855	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
6856	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
6857
6858	return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6859}
6860
6861/**
6862 *	t4_set_rxmode - set Rx properties of a virtual interface
6863 *	@adap: the adapter
6864 *	@mbox: mailbox to use for the FW command
6865 *	@viid: the VI id
6866 *	@mtu: the new MTU or -1
6867 *	@promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6868 *	@all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6869 *	@bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6870 *	@vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6871 *	@sleep_ok: if true we may sleep while awaiting command completion
6872 *
6873 *	Sets Rx properties of a virtual interface.
6874 */
6875int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6876		  int mtu, int promisc, int all_multi, int bcast, int vlanex,
6877		  bool sleep_ok)
6878{
6879	struct fw_vi_rxmode_cmd c;
6880
6881	/* convert to FW values */
6882	if (mtu < 0)
6883		mtu = M_FW_VI_RXMODE_CMD_MTU;
6884	if (promisc < 0)
6885		promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
6886	if (all_multi < 0)
6887		all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
6888	if (bcast < 0)
6889		bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
6890	if (vlanex < 0)
6891		vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
6892
6893	memset(&c, 0, sizeof(c));
6894	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
6895				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6896				   V_FW_VI_RXMODE_CMD_VIID(viid));
6897	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6898	c.mtu_to_vlanexen =
6899		cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
6900			    V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
6901			    V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
6902			    V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
6903			    V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
6904	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6905}
6906
6907/**
6908 *	t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6909 *	@adap: the adapter
6910 *	@mbox: mailbox to use for the FW command
6911 *	@viid: the VI id
6912 *	@free: if true any existing filters for this VI id are first removed
6913 *	@naddr: the number of MAC addresses to allocate filters for (up to 7)
6914 *	@addr: the MAC address(es)
6915 *	@idx: where to store the index of each allocated filter
6916 *	@hash: pointer to hash address filter bitmap
6917 *	@sleep_ok: call is allowed to sleep
6918 *
6919 *	Allocates an exact-match filter for each of the supplied addresses and
6920 *	sets it to the corresponding address.  If @idx is not %NULL it should
6921 *	have at least @naddr entries, each of which will be set to the index of
6922 *	the filter allocated for the corresponding MAC address.  If a filter
6923 *	could not be allocated for an address its index is set to 0xffff.
6924 *	If @hash is not %NULL addresses that fail to allocate an exact filter
6925 *	are hashed and update the hash filter bitmap pointed at by @hash.
6926 *
6927 *	Returns a negative error number or the number of filters allocated.
6928 */
6929int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6930		      unsigned int viid, bool free, unsigned int naddr,
6931		      const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6932{
6933	int offset, ret = 0;
6934	struct fw_vi_mac_cmd c;
6935	unsigned int nfilters = 0;
6936	unsigned int max_naddr = adap->chip_params->mps_tcam_size;
6937	unsigned int rem = naddr;
6938
6939	if (naddr > max_naddr)
6940		return -EINVAL;
6941
6942	for (offset = 0; offset < naddr ; /**/) {
6943		unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6944					 ? rem
6945					 : ARRAY_SIZE(c.u.exact));
6946		size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6947						     u.exact[fw_naddr]), 16);
6948		struct fw_vi_mac_exact *p;
6949		int i;
6950
6951		memset(&c, 0, sizeof(c));
6952		c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
6953					   F_FW_CMD_REQUEST |
6954					   F_FW_CMD_WRITE |
6955					   V_FW_CMD_EXEC(free) |
6956					   V_FW_VI_MAC_CMD_VIID(viid));
6957		c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
6958						  V_FW_CMD_LEN16(len16));
6959
6960		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6961			p->valid_to_idx =
6962				cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
6963					    V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
6964			memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6965		}
6966
6967		/*
6968		 * It's okay if we run out of space in our MAC address arena.
6969		 * Some of the addresses we submit may get stored so we need
6970		 * to run through the reply to see what the results were ...
6971		 */
6972		ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6973		if (ret && ret != -FW_ENOMEM)
6974			break;
6975
6976		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6977			u16 index = G_FW_VI_MAC_CMD_IDX(
6978						be16_to_cpu(p->valid_to_idx));
6979
6980			if (idx)
6981				idx[offset+i] = (index >=  max_naddr
6982						 ? 0xffff
6983						 : index);
6984			if (index < max_naddr)
6985				nfilters++;
6986			else if (hash)
6987				*hash |= (1ULL << hash_mac_addr(addr[offset+i]));
6988		}
6989
6990		free = false;
6991		offset += fw_naddr;
6992		rem -= fw_naddr;
6993	}
6994
6995	if (ret == 0 || ret == -FW_ENOMEM)
6996		ret = nfilters;
6997	return ret;
6998}
6999
7000/**
7001 *	t4_change_mac - modifies the exact-match filter for a MAC address
7002 *	@adap: the adapter
7003 *	@mbox: mailbox to use for the FW command
7004 *	@viid: the VI id
7005 *	@idx: index of existing filter for old value of MAC address, or -1
7006 *	@addr: the new MAC address value
7007 *	@persist: whether a new MAC allocation should be persistent
7008 *	@add_smt: if true also add the address to the HW SMT
7009 *
7010 *	Modifies an exact-match filter and sets it to the new MAC address if
7011 *	@idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
7012 *	latter case the address is added persistently if @persist is %true.
7013 *
7014 *	Note that in general it is not possible to modify the value of a given
7015 *	filter so the generic way to modify an address filter is to free the one
7016 *	being used by the old address value and allocate a new filter for the
7017 *	new address value.
7018 *
7019 *	Returns a negative error number or the index of the filter with the new
7020 *	MAC value.  Note that this index may differ from @idx.
7021 */
7022int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7023		  int idx, const u8 *addr, bool persist, bool add_smt)
7024{
7025	int ret, mode;
7026	struct fw_vi_mac_cmd c;
7027	struct fw_vi_mac_exact *p = c.u.exact;
7028	unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
7029
7030	if (idx < 0)		/* new allocation */
7031		idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7032	mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7033
7034	memset(&c, 0, sizeof(c));
7035	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7036				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7037				   V_FW_VI_MAC_CMD_VIID(viid));
7038	c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
7039	p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
7040				      V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
7041				      V_FW_VI_MAC_CMD_IDX(idx));
7042	memcpy(p->macaddr, addr, sizeof(p->macaddr));
7043
7044	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7045	if (ret == 0) {
7046		ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
7047		if (ret >= max_mac_addr)
7048			ret = -ENOMEM;
7049	}
7050	return ret;
7051}
7052
7053/**
7054 *	t4_set_addr_hash - program the MAC inexact-match hash filter
7055 *	@adap: the adapter
7056 *	@mbox: mailbox to use for the FW command
7057 *	@viid: the VI id
7058 *	@ucast: whether the hash filter should also match unicast addresses
7059 *	@vec: the value to be written to the hash filter
7060 *	@sleep_ok: call is allowed to sleep
7061 *
7062 *	Sets the 64-bit inexact-match hash filter for a virtual interface.
7063 */
7064int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7065		     bool ucast, u64 vec, bool sleep_ok)
7066{
7067	struct fw_vi_mac_cmd c;
7068	u32 val;
7069
7070	memset(&c, 0, sizeof(c));
7071	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7072				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7073				   V_FW_VI_ENABLE_CMD_VIID(viid));
7074	val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
7075	      V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
7076	c.freemacs_to_len16 = cpu_to_be32(val);
7077	c.u.hash.hashvec = cpu_to_be64(vec);
7078	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7079}
7080
7081/**
7082 *      t4_enable_vi_params - enable/disable a virtual interface
7083 *      @adap: the adapter
7084 *      @mbox: mailbox to use for the FW command
7085 *      @viid: the VI id
7086 *      @rx_en: 1=enable Rx, 0=disable Rx
7087 *      @tx_en: 1=enable Tx, 0=disable Tx
7088 *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7089 *
7090 *      Enables/disables a virtual interface.  Note that setting DCB Enable
7091 *      only makes sense when enabling a Virtual Interface ...
7092 */
7093int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7094			unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7095{
7096	struct fw_vi_enable_cmd c;
7097
7098	memset(&c, 0, sizeof(c));
7099	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7100				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7101				   V_FW_VI_ENABLE_CMD_VIID(viid));
7102	c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
7103				     V_FW_VI_ENABLE_CMD_EEN(tx_en) |
7104				     V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
7105				     FW_LEN16(c));
7106	return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7107}
7108
7109/**
7110 *	t4_enable_vi - enable/disable a virtual interface
7111 *	@adap: the adapter
7112 *	@mbox: mailbox to use for the FW command
7113 *	@viid: the VI id
7114 *	@rx_en: 1=enable Rx, 0=disable Rx
7115 *	@tx_en: 1=enable Tx, 0=disable Tx
7116 *
7117 *	Enables/disables a virtual interface.  Note that setting DCB Enable
7118 *	only makes sense when enabling a Virtual Interface ...
7119 */
7120int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7121		 bool rx_en, bool tx_en)
7122{
7123	return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7124}
7125
7126/**
7127 *	t4_identify_port - identify a VI's port by blinking its LED
7128 *	@adap: the adapter
7129 *	@mbox: mailbox to use for the FW command
7130 *	@viid: the VI id
7131 *	@nblinks: how many times to blink LED at 2.5 Hz
7132 *
7133 *	Identifies a VI's port by blinking its LED.
7134 */
7135int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7136		     unsigned int nblinks)
7137{
7138	struct fw_vi_enable_cmd c;
7139
7140	memset(&c, 0, sizeof(c));
7141	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7142				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7143				   V_FW_VI_ENABLE_CMD_VIID(viid));
7144	c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
7145	c.blinkdur = cpu_to_be16(nblinks);
7146	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7147}
7148
7149/**
7150 *	t4_iq_stop - stop an ingress queue and its FLs
7151 *	@adap: the adapter
7152 *	@mbox: mailbox to use for the FW command
7153 *	@pf: the PF owning the queues
7154 *	@vf: the VF owning the queues
7155 *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7156 *	@iqid: ingress queue id
7157 *	@fl0id: FL0 queue id or 0xffff if no attached FL0
7158 *	@fl1id: FL1 queue id or 0xffff if no attached FL1
7159 *
7160 *	Stops an ingress queue and its associated FLs, if any.  This causes
7161 *	any current or future data/messages destined for these queues to be
7162 *	tossed.
7163 */
7164int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7165	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
7166	       unsigned int fl0id, unsigned int fl1id)
7167{
7168	struct fw_iq_cmd c;
7169
7170	memset(&c, 0, sizeof(c));
7171	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7172				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7173				  V_FW_IQ_CMD_VFN(vf));
7174	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
7175	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7176	c.iqid = cpu_to_be16(iqid);
7177	c.fl0id = cpu_to_be16(fl0id);
7178	c.fl1id = cpu_to_be16(fl1id);
7179	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7180}
7181
7182/**
7183 *	t4_iq_free - free an ingress queue and its FLs
7184 *	@adap: the adapter
7185 *	@mbox: mailbox to use for the FW command
7186 *	@pf: the PF owning the queues
7187 *	@vf: the VF owning the queues
7188 *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7189 *	@iqid: ingress queue id
7190 *	@fl0id: FL0 queue id or 0xffff if no attached FL0
7191 *	@fl1id: FL1 queue id or 0xffff if no attached FL1
7192 *
7193 *	Frees an ingress queue and its associated FLs, if any.
7194 */
7195int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7196	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
7197	       unsigned int fl0id, unsigned int fl1id)
7198{
7199	struct fw_iq_cmd c;
7200
7201	memset(&c, 0, sizeof(c));
7202	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7203				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7204				  V_FW_IQ_CMD_VFN(vf));
7205	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
7206	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7207	c.iqid = cpu_to_be16(iqid);
7208	c.fl0id = cpu_to_be16(fl0id);
7209	c.fl1id = cpu_to_be16(fl1id);
7210	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7211}
7212
7213/**
7214 *	t4_eth_eq_free - free an Ethernet egress queue
7215 *	@adap: the adapter
7216 *	@mbox: mailbox to use for the FW command
7217 *	@pf: the PF owning the queue
7218 *	@vf: the VF owning the queue
7219 *	@eqid: egress queue id
7220 *
7221 *	Frees an Ethernet egress queue.
7222 */
7223int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7224		   unsigned int vf, unsigned int eqid)
7225{
7226	struct fw_eq_eth_cmd c;
7227
7228	memset(&c, 0, sizeof(c));
7229	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
7230				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7231				  V_FW_EQ_ETH_CMD_PFN(pf) |
7232				  V_FW_EQ_ETH_CMD_VFN(vf));
7233	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
7234	c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
7235	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7236}
7237
7238/**
7239 *	t4_ctrl_eq_free - free a control egress queue
7240 *	@adap: the adapter
7241 *	@mbox: mailbox to use for the FW command
7242 *	@pf: the PF owning the queue
7243 *	@vf: the VF owning the queue
7244 *	@eqid: egress queue id
7245 *
7246 *	Frees a control egress queue.
7247 */
7248int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7249		    unsigned int vf, unsigned int eqid)
7250{
7251	struct fw_eq_ctrl_cmd c;
7252
7253	memset(&c, 0, sizeof(c));
7254	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
7255				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7256				  V_FW_EQ_CTRL_CMD_PFN(pf) |
7257				  V_FW_EQ_CTRL_CMD_VFN(vf));
7258	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
7259	c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
7260	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7261}
7262
7263/**
7264 *	t4_ofld_eq_free - free an offload egress queue
7265 *	@adap: the adapter
7266 *	@mbox: mailbox to use for the FW command
7267 *	@pf: the PF owning the queue
7268 *	@vf: the VF owning the queue
7269 *	@eqid: egress queue id
7270 *
7271 *	Frees a control egress queue.
7272 */
7273int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7274		    unsigned int vf, unsigned int eqid)
7275{
7276	struct fw_eq_ofld_cmd c;
7277
7278	memset(&c, 0, sizeof(c));
7279	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
7280				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7281				  V_FW_EQ_OFLD_CMD_PFN(pf) |
7282				  V_FW_EQ_OFLD_CMD_VFN(vf));
7283	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
7284	c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
7285	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7286}
7287
7288/**
7289 *	t4_link_down_rc_str - return a string for a Link Down Reason Code
7290 *	@link_down_rc: Link Down Reason Code
7291 *
7292 *	Returns a string representation of the Link Down Reason Code.
7293 */
7294const char *t4_link_down_rc_str(unsigned char link_down_rc)
7295{
7296	static const char *reason[] = {
7297		"Link Down",
7298		"Remote Fault",
7299		"Auto-negotiation Failure",
7300		"Reserved3",
7301		"Insufficient Airflow",
7302		"Unable To Determine Reason",
7303		"No RX Signal Detected",
7304		"Reserved7",
7305	};
7306
7307	if (link_down_rc >= ARRAY_SIZE(reason))
7308		return "Bad Reason Code";
7309
7310	return reason[link_down_rc];
7311}
7312
7313/**
7314 *	t4_handle_fw_rpl - process a FW reply message
7315 *	@adap: the adapter
7316 *	@rpl: start of the FW message
7317 *
7318 *	Processes a FW message, such as link state change messages.
7319 */
7320int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7321{
7322	u8 opcode = *(const u8 *)rpl;
7323	const struct fw_port_cmd *p = (const void *)rpl;
7324	unsigned int action =
7325			G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
7326
7327	if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7328		/* link/module state change message */
7329		int speed = 0, fc = 0, i;
7330		int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
7331		struct port_info *pi = NULL;
7332		struct link_config *lc;
7333		u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7334		int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
7335		u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
7336
7337		if (stat & F_FW_PORT_CMD_RXPAUSE)
7338			fc |= PAUSE_RX;
7339		if (stat & F_FW_PORT_CMD_TXPAUSE)
7340			fc |= PAUSE_TX;
7341		if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
7342			speed = 100;
7343		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
7344			speed = 1000;
7345		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
7346			speed = 10000;
7347		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
7348			speed = 40000;
7349
7350		for_each_port(adap, i) {
7351			pi = adap2pinfo(adap, i);
7352			if (pi->tx_chan == chan)
7353				break;
7354		}
7355		lc = &pi->link_cfg;
7356
7357		if (mod != pi->mod_type) {
7358			pi->mod_type = mod;
7359			t4_os_portmod_changed(adap, i);
7360		}
7361		if (link_ok != lc->link_ok || speed != lc->speed ||
7362		    fc != lc->fc) {                    /* something changed */
7363			int reason;
7364
7365			if (!link_ok && lc->link_ok)
7366				reason = G_FW_PORT_CMD_LINKDNRC(stat);
7367			else
7368				reason = -1;
7369
7370			lc->link_ok = link_ok;
7371			lc->speed = speed;
7372			lc->fc = fc;
7373			lc->supported = be16_to_cpu(p->u.info.pcap);
7374			t4_os_link_changed(adap, i, link_ok, reason);
7375		}
7376	} else {
7377		CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
7378		return -EINVAL;
7379	}
7380	return 0;
7381}
7382
7383/**
7384 *	get_pci_mode - determine a card's PCI mode
7385 *	@adapter: the adapter
7386 *	@p: where to store the PCI settings
7387 *
7388 *	Determines a card's PCI mode and associated parameters, such as speed
7389 *	and width.
7390 */
7391static void get_pci_mode(struct adapter *adapter,
7392				   struct pci_params *p)
7393{
7394	u16 val;
7395	u32 pcie_cap;
7396
7397	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7398	if (pcie_cap) {
7399		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
7400		p->speed = val & PCI_EXP_LNKSTA_CLS;
7401		p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7402	}
7403}
7404
7405/**
7406 *	init_link_config - initialize a link's SW state
7407 *	@lc: structure holding the link state
7408 *	@caps: link capabilities
7409 *
7410 *	Initializes the SW state maintained for each link, including the link's
7411 *	capabilities and default speed/flow-control/autonegotiation settings.
7412 */
7413static void init_link_config(struct link_config *lc, unsigned int caps)
7414{
7415	lc->supported = caps;
7416	lc->requested_speed = 0;
7417	lc->speed = 0;
7418	lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7419	if (lc->supported & FW_PORT_CAP_ANEG) {
7420		lc->advertising = lc->supported & ADVERT_MASK;
7421		lc->autoneg = AUTONEG_ENABLE;
7422		lc->requested_fc |= PAUSE_AUTONEG;
7423	} else {
7424		lc->advertising = 0;
7425		lc->autoneg = AUTONEG_DISABLE;
7426	}
7427}
7428
7429struct flash_desc {
7430	u32 vendor_and_model_id;
7431	u32 size_mb;
7432};
7433
7434int t4_get_flash_params(struct adapter *adapter)
7435{
7436	/*
7437	 * Table for non-Numonix supported flash parts.  Numonix parts are left
7438	 * to the preexisting well-tested code.  All flash parts have 64KB
7439	 * sectors.
7440	 */
7441	static struct flash_desc supported_flash[] = {
7442		{ 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
7443	};
7444
7445	int ret;
7446	u32 info = 0;
7447
7448	ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
7449	if (!ret)
7450		ret = sf1_read(adapter, 3, 0, 1, &info);
7451	t4_write_reg(adapter, A_SF_OP, 0);	/* unlock SF */
7452	if (ret < 0)
7453		return ret;
7454
7455	for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7456		if (supported_flash[ret].vendor_and_model_id == info) {
7457			adapter->params.sf_size = supported_flash[ret].size_mb;
7458			adapter->params.sf_nsec =
7459				adapter->params.sf_size / SF_SEC_SIZE;
7460			return 0;
7461		}
7462
7463	if ((info & 0xff) != 0x20)		/* not a Numonix flash */
7464		return -EINVAL;
7465	info >>= 16;				/* log2 of size */
7466	if (info >= 0x14 && info < 0x18)
7467		adapter->params.sf_nsec = 1 << (info - 16);
7468	else if (info == 0x18)
7469		adapter->params.sf_nsec = 64;
7470	else
7471		return -EINVAL;
7472	adapter->params.sf_size = 1 << info;
7473
7474	/*
7475	 * We should ~probably~ reject adapters with FLASHes which are too
7476	 * small but we have some legacy FPGAs with small FLASHes that we'd
7477	 * still like to use.  So instead we emit a scary message ...
7478	 */
7479	if (adapter->params.sf_size < FLASH_MIN_SIZE)
7480		CH_WARN(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n",
7481			adapter->params.sf_size, FLASH_MIN_SIZE);
7482
7483	return 0;
7484}
7485
7486static void set_pcie_completion_timeout(struct adapter *adapter,
7487						  u8 range)
7488{
7489	u16 val;
7490	u32 pcie_cap;
7491
7492	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7493	if (pcie_cap) {
7494		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
7495		val &= 0xfff0;
7496		val |= range ;
7497		t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
7498	}
7499}
7500
7501const struct chip_params *t4_get_chip_params(int chipid)
7502{
7503	static const struct chip_params chip_params[] = {
7504		{
7505			/* T4 */
7506			.nchan = NCHAN,
7507			.pm_stats_cnt = PM_NSTATS,
7508			.cng_ch_bits_log = 2,
7509			.nsched_cls = 15,
7510			.cim_num_obq = CIM_NUM_OBQ,
7511			.mps_rplc_size = 128,
7512			.vfcount = 128,
7513			.sge_fl_db = F_DBPRIO,
7514			.mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
7515		},
7516		{
7517			/* T5 */
7518			.nchan = NCHAN,
7519			.pm_stats_cnt = PM_NSTATS,
7520			.cng_ch_bits_log = 2,
7521			.nsched_cls = 16,
7522			.cim_num_obq = CIM_NUM_OBQ_T5,
7523			.mps_rplc_size = 128,
7524			.vfcount = 128,
7525			.sge_fl_db = F_DBPRIO | F_DBTYPE,
7526			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7527		},
7528		{
7529			/* T6 */
7530			.nchan = T6_NCHAN,
7531			.pm_stats_cnt = T6_PM_NSTATS,
7532			.cng_ch_bits_log = 3,
7533			.nsched_cls = 16,
7534			.cim_num_obq = CIM_NUM_OBQ_T5,
7535			.mps_rplc_size = 256,
7536			.vfcount = 256,
7537			.sge_fl_db = 0,
7538			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7539		},
7540	};
7541
7542	chipid -= CHELSIO_T4;
7543	if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
7544		return NULL;
7545
7546	return &chip_params[chipid];
7547}
7548
7549/**
7550 *	t4_prep_adapter - prepare SW and HW for operation
7551 *	@adapter: the adapter
7552 *	@buf: temporary space of at least VPD_LEN size provided by the caller.
7553 *
7554 *	Initialize adapter SW state for the various HW modules, set initial
7555 *	values for some adapter tunables, take PHYs out of reset, and
7556 *	initialize the MDIO interface.
7557 */
7558int t4_prep_adapter(struct adapter *adapter, u8 *buf)
7559{
7560	int ret;
7561	uint16_t device_id;
7562	uint32_t pl_rev;
7563
7564	get_pci_mode(adapter, &adapter->params.pci);
7565
7566	pl_rev = t4_read_reg(adapter, A_PL_REV);
7567	adapter->params.chipid = G_CHIPID(pl_rev);
7568	adapter->params.rev = G_REV(pl_rev);
7569	if (adapter->params.chipid == 0) {
7570		/* T4 did not have chipid in PL_REV (T5 onwards do) */
7571		adapter->params.chipid = CHELSIO_T4;
7572
7573		/* T4A1 chip is not supported */
7574		if (adapter->params.rev == 1) {
7575			CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
7576			return -EINVAL;
7577		}
7578	}
7579
7580	adapter->chip_params = t4_get_chip_params(chip_id(adapter));
7581	if (adapter->chip_params == NULL)
7582		return -EINVAL;
7583
7584	adapter->params.pci.vpd_cap_addr =
7585	    t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
7586
7587	ret = t4_get_flash_params(adapter);
7588	if (ret < 0)
7589		return ret;
7590
7591	ret = get_vpd_params(adapter, &adapter->params.vpd, buf);
7592	if (ret < 0)
7593		return ret;
7594
7595	/* Cards with real ASICs have the chipid in the PCIe device id */
7596	t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
7597	if (device_id >> 12 == chip_id(adapter))
7598		adapter->params.cim_la_size = CIMLA_SIZE;
7599	else {
7600		/* FPGA */
7601		adapter->params.fpga = 1;
7602		adapter->params.cim_la_size = 2 * CIMLA_SIZE;
7603	}
7604
7605	init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7606
7607	/*
7608	 * Default port and clock for debugging in case we can't reach FW.
7609	 */
7610	adapter->params.nports = 1;
7611	adapter->params.portvec = 1;
7612	adapter->params.vpd.cclk = 50000;
7613
7614	/* Set pci completion timeout value to 4 seconds. */
7615	set_pcie_completion_timeout(adapter, 0xd);
7616	return 0;
7617}
7618
7619/**
7620 *	t4_shutdown_adapter - shut down adapter, host & wire
7621 *	@adapter: the adapter
7622 *
7623 *	Perform an emergency shutdown of the adapter and stop it from
7624 *	continuing any further communication on the ports or DMA to the
7625 *	host.  This is typically used when the adapter and/or firmware
7626 *	have crashed and we want to prevent any further accidental
7627 *	communication with the rest of the world.  This will also force
7628 *	the port Link Status to go down -- if register writes work --
7629 *	which should help our peers figure out that we're down.
7630 */
7631int t4_shutdown_adapter(struct adapter *adapter)
7632{
7633	int port;
7634
7635	t4_intr_disable(adapter);
7636	t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
7637	for_each_port(adapter, port) {
7638		u32 a_port_cfg = PORT_REG(port,
7639					  is_t4(adapter)
7640					  ? A_XGMAC_PORT_CFG
7641					  : A_MAC_PORT_CFG);
7642
7643		t4_write_reg(adapter, a_port_cfg,
7644			     t4_read_reg(adapter, a_port_cfg)
7645			     & ~V_SIGNAL_DET(1));
7646	}
7647	t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
7648
7649	return 0;
7650}
7651
7652/**
7653 *	t4_init_devlog_params - initialize adapter->params.devlog
7654 *	@adap: the adapter
7655 *	@fw_attach: whether we can talk to the firmware
7656 *
7657 *	Initialize various fields of the adapter's Firmware Device Log
7658 *	Parameters structure.
7659 */
7660int t4_init_devlog_params(struct adapter *adap, int fw_attach)
7661{
7662	struct devlog_params *dparams = &adap->params.devlog;
7663	u32 pf_dparams;
7664	unsigned int devlog_meminfo;
7665	struct fw_devlog_cmd devlog_cmd;
7666	int ret;
7667
7668	/* If we're dealing with newer firmware, the Device Log Paramerters
7669	 * are stored in a designated register which allows us to access the
7670	 * Device Log even if we can't talk to the firmware.
7671	 */
7672	pf_dparams =
7673		t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
7674	if (pf_dparams) {
7675		unsigned int nentries, nentries128;
7676
7677		dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
7678		dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
7679
7680		nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
7681		nentries = (nentries128 + 1) * 128;
7682		dparams->size = nentries * sizeof(struct fw_devlog_e);
7683
7684		return 0;
7685	}
7686
7687	/*
7688	 * For any failing returns ...
7689	 */
7690	memset(dparams, 0, sizeof *dparams);
7691
7692	/*
7693	 * If we can't talk to the firmware, there's really nothing we can do
7694	 * at this point.
7695	 */
7696	if (!fw_attach)
7697		return -ENXIO;
7698
7699	/* Otherwise, ask the firmware for it's Device Log Parameters.
7700	 */
7701	memset(&devlog_cmd, 0, sizeof devlog_cmd);
7702	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
7703					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
7704	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7705	ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7706			 &devlog_cmd);
7707	if (ret)
7708		return ret;
7709
7710	devlog_meminfo =
7711		be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7712	dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
7713	dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
7714	dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7715
7716	return 0;
7717}
7718
7719/**
7720 *	t4_init_sge_params - initialize adap->params.sge
7721 *	@adapter: the adapter
7722 *
7723 *	Initialize various fields of the adapter's SGE Parameters structure.
7724 */
7725int t4_init_sge_params(struct adapter *adapter)
7726{
7727	u32 r;
7728	struct sge_params *sp = &adapter->params.sge;
7729	unsigned i;
7730
7731	r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
7732	sp->counter_val[0] = G_THRESHOLD_0(r);
7733	sp->counter_val[1] = G_THRESHOLD_1(r);
7734	sp->counter_val[2] = G_THRESHOLD_2(r);
7735	sp->counter_val[3] = G_THRESHOLD_3(r);
7736
7737	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
7738	sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r));
7739	sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r));
7740	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
7741	sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r));
7742	sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r));
7743	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
7744	sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r));
7745	sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r));
7746
7747	r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
7748	sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
7749	if (is_t4(adapter))
7750		sp->fl_starve_threshold2 = sp->fl_starve_threshold;
7751	else
7752		sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
7753
7754	/* egress queues: log2 of # of doorbells per BAR2 page */
7755	r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
7756	r >>= S_QUEUESPERPAGEPF0 +
7757	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
7758	sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
7759
7760	/* ingress queues: log2 of # of doorbells per BAR2 page */
7761	r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
7762	r >>= S_QUEUESPERPAGEPF0 +
7763	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
7764	sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
7765
7766	r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
7767	r >>= S_HOSTPAGESIZEPF0 +
7768	    (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
7769	sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
7770
7771	r = t4_read_reg(adapter, A_SGE_CONTROL);
7772	sp->sge_control = r;
7773	sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
7774	sp->fl_pktshift = G_PKTSHIFT(r);
7775	sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 5);
7776	if (is_t4(adapter))
7777		sp->pack_boundary = sp->pad_boundary;
7778	else {
7779		r = t4_read_reg(adapter, A_SGE_CONTROL2);
7780		if (G_INGPACKBOUNDARY(r) == 0)
7781			sp->pack_boundary = 16;
7782		else
7783			sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
7784	}
7785	for (i = 0; i < SGE_FLBUF_SIZES; i++)
7786		sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
7787		    A_SGE_FL_BUFFER_SIZE0 + (4 * i));
7788
7789	return 0;
7790}
7791
7792/*
7793 * Read and cache the adapter's compressed filter mode and ingress config.
7794 */
7795static void read_filter_mode_and_ingress_config(struct adapter *adap)
7796{
7797	struct tp_params *tpp = &adap->params.tp;
7798
7799	if (t4_use_ldst(adap)) {
7800		t4_fw_tp_pio_rw(adap, &tpp->vlan_pri_map, 1,
7801				A_TP_VLAN_PRI_MAP, 1);
7802		t4_fw_tp_pio_rw(adap, &tpp->ingress_config, 1,
7803				A_TP_INGRESS_CONFIG, 1);
7804	} else {
7805		t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
7806				 &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
7807		t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
7808				 &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG);
7809	}
7810
7811	/*
7812	 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7813	 * shift positions of several elements of the Compressed Filter Tuple
7814	 * for this adapter which we need frequently ...
7815	 */
7816	tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
7817	tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
7818	tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
7819	tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
7820	tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
7821	tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
7822	tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
7823	tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
7824	tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
7825	tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
7826
7827	/*
7828	 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7829	 * represents the presence of an Outer VLAN instead of a VNIC ID.
7830	 */
7831	if ((tpp->ingress_config & F_VNIC) == 0)
7832		tpp->vnic_shift = -1;
7833}
7834
7835/**
7836 *      t4_init_tp_params - initialize adap->params.tp
7837 *      @adap: the adapter
7838 *
7839 *      Initialize various fields of the adapter's TP Parameters structure.
7840 */
7841int t4_init_tp_params(struct adapter *adap)
7842{
7843	int chan;
7844	u32 v;
7845	struct tp_params *tpp = &adap->params.tp;
7846
7847	v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
7848	tpp->tre = G_TIMERRESOLUTION(v);
7849	tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
7850
7851	/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7852	for (chan = 0; chan < MAX_NCHAN; chan++)
7853		tpp->tx_modq[chan] = chan;
7854
7855	read_filter_mode_and_ingress_config(adap);
7856
7857	/*
7858	 * For T6, cache the adapter's compressed error vector
7859	 * and passing outer header info for encapsulated packets.
7860	 */
7861	if (chip_id(adap) > CHELSIO_T5) {
7862		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
7863		tpp->rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
7864	}
7865
7866	return 0;
7867}
7868
7869/**
7870 *      t4_filter_field_shift - calculate filter field shift
7871 *      @adap: the adapter
7872 *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7873 *
7874 *      Return the shift position of a filter field within the Compressed
7875 *      Filter Tuple.  The filter field is specified via its selection bit
7876 *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
7877 */
7878int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7879{
7880	unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7881	unsigned int sel;
7882	int field_shift;
7883
7884	if ((filter_mode & filter_sel) == 0)
7885		return -1;
7886
7887	for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7888		switch (filter_mode & sel) {
7889		case F_FCOE:
7890			field_shift += W_FT_FCOE;
7891			break;
7892		case F_PORT:
7893			field_shift += W_FT_PORT;
7894			break;
7895		case F_VNIC_ID:
7896			field_shift += W_FT_VNIC_ID;
7897			break;
7898		case F_VLAN:
7899			field_shift += W_FT_VLAN;
7900			break;
7901		case F_TOS:
7902			field_shift += W_FT_TOS;
7903			break;
7904		case F_PROTOCOL:
7905			field_shift += W_FT_PROTOCOL;
7906			break;
7907		case F_ETHERTYPE:
7908			field_shift += W_FT_ETHERTYPE;
7909			break;
7910		case F_MACMATCH:
7911			field_shift += W_FT_MACMATCH;
7912			break;
7913		case F_MPSHITTYPE:
7914			field_shift += W_FT_MPSHITTYPE;
7915			break;
7916		case F_FRAGMENTATION:
7917			field_shift += W_FT_FRAGMENTATION;
7918			break;
7919		}
7920	}
7921	return field_shift;
7922}
7923
7924int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
7925{
7926	u8 addr[6];
7927	int ret, i, j;
7928	struct fw_port_cmd c;
7929	u16 rss_size;
7930	struct port_info *p = adap2pinfo(adap, port_id);
7931	u32 param, val;
7932
7933	memset(&c, 0, sizeof(c));
7934
7935	for (i = 0, j = -1; i <= p->port_id; i++) {
7936		do {
7937			j++;
7938		} while ((adap->params.portvec & (1 << j)) == 0);
7939	}
7940
7941	c.op_to_portid = htonl(V_FW_CMD_OP(FW_PORT_CMD) |
7942			       F_FW_CMD_REQUEST | F_FW_CMD_READ |
7943			       V_FW_PORT_CMD_PORTID(j));
7944	c.action_to_len16 = htonl(
7945		V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
7946		FW_LEN16(c));
7947	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7948	if (ret)
7949		return ret;
7950
7951	ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
7952	if (ret < 0)
7953		return ret;
7954
7955	p->vi[0].viid = ret;
7956	p->tx_chan = j;
7957	p->rx_chan_map = t4_get_mps_bg_map(adap, j);
7958	p->lport = j;
7959	p->vi[0].rss_size = rss_size;
7960	t4_os_set_hw_addr(adap, p->port_id, addr);
7961
7962	ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7963	p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
7964		G_FW_PORT_CMD_MDIOADDR(ret) : -1;
7965	p->port_type = G_FW_PORT_CMD_PTYPE(ret);
7966	p->mod_type = G_FW_PORT_CMD_MODTYPE(ret);
7967
7968	init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
7969
7970	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7971	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
7972	    V_FW_PARAMS_PARAM_YZ(p->vi[0].viid);
7973	ret = t4_query_params(adap, mbox, pf, vf, 1, &param, &val);
7974	if (ret)
7975		p->vi[0].rss_base = 0xffff;
7976	else {
7977		/* MPASS((val >> 16) == rss_size); */
7978		p->vi[0].rss_base = val & 0xffff;
7979	}
7980
7981	return 0;
7982}
7983
7984/**
7985 *	t4_read_cimq_cfg - read CIM queue configuration
7986 *	@adap: the adapter
7987 *	@base: holds the queue base addresses in bytes
7988 *	@size: holds the queue sizes in bytes
7989 *	@thres: holds the queue full thresholds in bytes
7990 *
7991 *	Returns the current configuration of the CIM queues, starting with
7992 *	the IBQs, then the OBQs.
7993 */
7994void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7995{
7996	unsigned int i, v;
7997	int cim_num_obq = adap->chip_params->cim_num_obq;
7998
7999	for (i = 0; i < CIM_NUM_IBQ; i++) {
8000		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
8001			     V_QUENUMSELECT(i));
8002		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8003		/* value is in 256-byte units */
8004		*base++ = G_CIMQBASE(v) * 256;
8005		*size++ = G_CIMQSIZE(v) * 256;
8006		*thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
8007	}
8008	for (i = 0; i < cim_num_obq; i++) {
8009		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
8010			     V_QUENUMSELECT(i));
8011		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8012		/* value is in 256-byte units */
8013		*base++ = G_CIMQBASE(v) * 256;
8014		*size++ = G_CIMQSIZE(v) * 256;
8015	}
8016}
8017
8018/**
8019 *	t4_read_cim_ibq - read the contents of a CIM inbound queue
8020 *	@adap: the adapter
8021 *	@qid: the queue index
8022 *	@data: where to store the queue contents
8023 *	@n: capacity of @data in 32-bit words
8024 *
8025 *	Reads the contents of the selected CIM queue starting at address 0 up
8026 *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8027 *	error and the number of 32-bit words actually read on success.
8028 */
8029int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8030{
8031	int i, err, attempts;
8032	unsigned int addr;
8033	const unsigned int nwords = CIM_IBQ_SIZE * 4;
8034
8035	if (qid > 5 || (n & 3))
8036		return -EINVAL;
8037
8038	addr = qid * nwords;
8039	if (n > nwords)
8040		n = nwords;
8041
8042	/* It might take 3-10ms before the IBQ debug read access is allowed.
8043	 * Wait for 1 Sec with a delay of 1 usec.
8044	 */
8045	attempts = 1000000;
8046
8047	for (i = 0; i < n; i++, addr++) {
8048		t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
8049			     F_IBQDBGEN);
8050		err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
8051				      attempts, 1);
8052		if (err)
8053			return err;
8054		*data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
8055	}
8056	t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
8057	return i;
8058}
8059
8060/**
8061 *	t4_read_cim_obq - read the contents of a CIM outbound queue
8062 *	@adap: the adapter
8063 *	@qid: the queue index
8064 *	@data: where to store the queue contents
8065 *	@n: capacity of @data in 32-bit words
8066 *
8067 *	Reads the contents of the selected CIM queue starting at address 0 up
8068 *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8069 *	error and the number of 32-bit words actually read on success.
8070 */
8071int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8072{
8073	int i, err;
8074	unsigned int addr, v, nwords;
8075	int cim_num_obq = adap->chip_params->cim_num_obq;
8076
8077	if ((qid > (cim_num_obq - 1)) || (n & 3))
8078		return -EINVAL;
8079
8080	t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
8081		     V_QUENUMSELECT(qid));
8082	v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8083
8084	addr = G_CIMQBASE(v) * 64;    /* muliple of 256 -> muliple of 4 */
8085	nwords = G_CIMQSIZE(v) * 64;  /* same */
8086	if (n > nwords)
8087		n = nwords;
8088
8089	for (i = 0; i < n; i++, addr++) {
8090		t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
8091			     F_OBQDBGEN);
8092		err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
8093				      2, 1);
8094		if (err)
8095			return err;
8096		*data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
8097	}
8098	t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
8099	return i;
8100}
8101
8102enum {
8103	CIM_QCTL_BASE     = 0,
8104	CIM_CTL_BASE      = 0x2000,
8105	CIM_PBT_ADDR_BASE = 0x2800,
8106	CIM_PBT_LRF_BASE  = 0x3000,
8107	CIM_PBT_DATA_BASE = 0x3800
8108};
8109
8110/**
8111 *	t4_cim_read - read a block from CIM internal address space
8112 *	@adap: the adapter
8113 *	@addr: the start address within the CIM address space
8114 *	@n: number of words to read
8115 *	@valp: where to store the result
8116 *
8117 *	Reads a block of 4-byte words from the CIM intenal address space.
8118 */
8119int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8120		unsigned int *valp)
8121{
8122	int ret = 0;
8123
8124	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8125		return -EBUSY;
8126
8127	for ( ; !ret && n--; addr += 4) {
8128		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
8129		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8130				      0, 5, 2);
8131		if (!ret)
8132			*valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
8133	}
8134	return ret;
8135}
8136
8137/**
8138 *	t4_cim_write - write a block into CIM internal address space
8139 *	@adap: the adapter
8140 *	@addr: the start address within the CIM address space
8141 *	@n: number of words to write
8142 *	@valp: set of values to write
8143 *
8144 *	Writes a block of 4-byte words into the CIM intenal address space.
8145 */
8146int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8147		 const unsigned int *valp)
8148{
8149	int ret = 0;
8150
8151	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8152		return -EBUSY;
8153
8154	for ( ; !ret && n--; addr += 4) {
8155		t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
8156		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
8157		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8158				      0, 5, 2);
8159	}
8160	return ret;
8161}
8162
8163static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8164			 unsigned int val)
8165{
8166	return t4_cim_write(adap, addr, 1, &val);
8167}
8168
8169/**
8170 *	t4_cim_ctl_read - read a block from CIM control region
8171 *	@adap: the adapter
8172 *	@addr: the start address within the CIM control region
8173 *	@n: number of words to read
8174 *	@valp: where to store the result
8175 *
8176 *	Reads a block of 4-byte words from the CIM control region.
8177 */
8178int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
8179		    unsigned int *valp)
8180{
8181	return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
8182}
8183
8184/**
8185 *	t4_cim_read_la - read CIM LA capture buffer
8186 *	@adap: the adapter
8187 *	@la_buf: where to store the LA data
8188 *	@wrptr: the HW write pointer within the capture buffer
8189 *
8190 *	Reads the contents of the CIM LA buffer with the most recent entry at
8191 *	the end	of the returned data and with the entry at @wrptr first.
8192 *	We try to leave the LA in the running state we find it in.
8193 */
8194int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8195{
8196	int i, ret;
8197	unsigned int cfg, val, idx;
8198
8199	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
8200	if (ret)
8201		return ret;
8202
8203	if (cfg & F_UPDBGLAEN) {	/* LA is running, freeze it */
8204		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
8205		if (ret)
8206			return ret;
8207	}
8208
8209	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8210	if (ret)
8211		goto restart;
8212
8213	idx = G_UPDBGLAWRPTR(val);
8214	if (wrptr)
8215		*wrptr = idx;
8216
8217	for (i = 0; i < adap->params.cim_la_size; i++) {
8218		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8219				    V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
8220		if (ret)
8221			break;
8222		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8223		if (ret)
8224			break;
8225		if (val & F_UPDBGLARDEN) {
8226			ret = -ETIMEDOUT;
8227			break;
8228		}
8229		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
8230		if (ret)
8231			break;
8232
8233		/* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */
8234		idx = (idx + 1) & M_UPDBGLARDPTR;
8235		/*
8236		 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
8237		 * identify the 32-bit portion of the full 312-bit data
8238		 */
8239		if (is_t6(adap))
8240			while ((idx & 0xf) > 9)
8241				idx = (idx + 1) % M_UPDBGLARDPTR;
8242	}
8243restart:
8244	if (cfg & F_UPDBGLAEN) {
8245		int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8246				      cfg & ~F_UPDBGLARDEN);
8247		if (!ret)
8248			ret = r;
8249	}
8250	return ret;
8251}
8252
8253/**
8254 *	t4_tp_read_la - read TP LA capture buffer
8255 *	@adap: the adapter
8256 *	@la_buf: where to store the LA data
8257 *	@wrptr: the HW write pointer within the capture buffer
8258 *
8259 *	Reads the contents of the TP LA buffer with the most recent entry at
8260 *	the end	of the returned data and with the entry at @wrptr first.
8261 *	We leave the LA in the running state we find it in.
8262 */
8263void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8264{
8265	bool last_incomplete;
8266	unsigned int i, cfg, val, idx;
8267
8268	cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
8269	if (cfg & F_DBGLAENABLE)			/* freeze LA */
8270		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8271			     adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
8272
8273	val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
8274	idx = G_DBGLAWPTR(val);
8275	last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
8276	if (last_incomplete)
8277		idx = (idx + 1) & M_DBGLARPTR;
8278	if (wrptr)
8279		*wrptr = idx;
8280
8281	val &= 0xffff;
8282	val &= ~V_DBGLARPTR(M_DBGLARPTR);
8283	val |= adap->params.tp.la_mask;
8284
8285	for (i = 0; i < TPLA_SIZE; i++) {
8286		t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
8287		la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
8288		idx = (idx + 1) & M_DBGLARPTR;
8289	}
8290
8291	/* Wipe out last entry if it isn't valid */
8292	if (last_incomplete)
8293		la_buf[TPLA_SIZE - 1] = ~0ULL;
8294
8295	if (cfg & F_DBGLAENABLE)		/* restore running state */
8296		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8297			     cfg | adap->params.tp.la_mask);
8298}
8299
8300/*
8301 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8302 * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
8303 * state for more than the Warning Threshold then we'll issue a warning about
8304 * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
8305 * appears to be hung every Warning Repeat second till the situation clears.
8306 * If the situation clears, we'll note that as well.
8307 */
8308#define SGE_IDMA_WARN_THRESH 1
8309#define SGE_IDMA_WARN_REPEAT 300
8310
8311/**
8312 *	t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8313 *	@adapter: the adapter
8314 *	@idma: the adapter IDMA Monitor state
8315 *
8316 *	Initialize the state of an SGE Ingress DMA Monitor.
8317 */
8318void t4_idma_monitor_init(struct adapter *adapter,
8319			  struct sge_idma_monitor_state *idma)
8320{
8321	/* Initialize the state variables for detecting an SGE Ingress DMA
8322	 * hang.  The SGE has internal counters which count up on each clock
8323	 * tick whenever the SGE finds its Ingress DMA State Engines in the
8324	 * same state they were on the previous clock tick.  The clock used is
8325	 * the Core Clock so we have a limit on the maximum "time" they can
8326	 * record; typically a very small number of seconds.  For instance,
8327	 * with a 600MHz Core Clock, we can only count up to a bit more than
8328	 * 7s.  So we'll synthesize a larger counter in order to not run the
8329	 * risk of having the "timers" overflow and give us the flexibility to
8330	 * maintain a Hung SGE State Machine of our own which operates across
8331	 * a longer time frame.
8332	 */
8333	idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8334	idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
8335}
8336
8337/**
8338 *	t4_idma_monitor - monitor SGE Ingress DMA state
8339 *	@adapter: the adapter
8340 *	@idma: the adapter IDMA Monitor state
8341 *	@hz: number of ticks/second
8342 *	@ticks: number of ticks since the last IDMA Monitor call
8343 */
8344void t4_idma_monitor(struct adapter *adapter,
8345		     struct sge_idma_monitor_state *idma,
8346		     int hz, int ticks)
8347{
8348	int i, idma_same_state_cnt[2];
8349
8350	 /* Read the SGE Debug Ingress DMA Same State Count registers.  These
8351	  * are counters inside the SGE which count up on each clock when the
8352	  * SGE finds its Ingress DMA State Engines in the same states they
8353	  * were in the previous clock.  The counters will peg out at
8354	  * 0xffffffff without wrapping around so once they pass the 1s
8355	  * threshold they'll stay above that till the IDMA state changes.
8356	  */
8357	t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
8358	idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
8359	idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8360
8361	for (i = 0; i < 2; i++) {
8362		u32 debug0, debug11;
8363
8364		/* If the Ingress DMA Same State Counter ("timer") is less
8365		 * than 1s, then we can reset our synthesized Stall Timer and
8366		 * continue.  If we have previously emitted warnings about a
8367		 * potential stalled Ingress Queue, issue a note indicating
8368		 * that the Ingress Queue has resumed forward progress.
8369		 */
8370		if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8371			if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
8372				CH_WARN(adapter, "SGE idma%d, queue %u, "
8373					"resumed after %d seconds\n",
8374					i, idma->idma_qid[i],
8375					idma->idma_stalled[i]/hz);
8376			idma->idma_stalled[i] = 0;
8377			continue;
8378		}
8379
8380		/* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8381		 * domain.  The first time we get here it'll be because we
8382		 * passed the 1s Threshold; each additional time it'll be
8383		 * because the RX Timer Callback is being fired on its regular
8384		 * schedule.
8385		 *
8386		 * If the stall is below our Potential Hung Ingress Queue
8387		 * Warning Threshold, continue.
8388		 */
8389		if (idma->idma_stalled[i] == 0) {
8390			idma->idma_stalled[i] = hz;
8391			idma->idma_warn[i] = 0;
8392		} else {
8393			idma->idma_stalled[i] += ticks;
8394			idma->idma_warn[i] -= ticks;
8395		}
8396
8397		if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
8398			continue;
8399
8400		/* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8401		 */
8402		if (idma->idma_warn[i] > 0)
8403			continue;
8404		idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
8405
8406		/* Read and save the SGE IDMA State and Queue ID information.
8407		 * We do this every time in case it changes across time ...
8408		 * can't be too careful ...
8409		 */
8410		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
8411		debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8412		idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8413
8414		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
8415		debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8416		idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8417
8418		CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
8419			" state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8420			i, idma->idma_qid[i], idma->idma_state[i],
8421			idma->idma_stalled[i]/hz,
8422			debug0, debug11);
8423		t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8424	}
8425}
8426
8427/**
8428 *	t4_read_pace_tbl - read the pace table
8429 *	@adap: the adapter
8430 *	@pace_vals: holds the returned values
8431 *
8432 *	Returns the values of TP's pace table in microseconds.
8433 */
8434void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
8435{
8436	unsigned int i, v;
8437
8438	for (i = 0; i < NTX_SCHED; i++) {
8439		t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
8440		v = t4_read_reg(adap, A_TP_PACE_TABLE);
8441		pace_vals[i] = dack_ticks_to_usec(adap, v);
8442	}
8443}
8444
8445/**
8446 *	t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
8447 *	@adap: the adapter
8448 *	@sched: the scheduler index
8449 *	@kbps: the byte rate in Kbps
8450 *	@ipg: the interpacket delay in tenths of nanoseconds
8451 *
8452 *	Return the current configuration of a HW Tx scheduler.
8453 */
8454void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
8455		     unsigned int *ipg)
8456{
8457	unsigned int v, addr, bpt, cpt;
8458
8459	if (kbps) {
8460		addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
8461		t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
8462		v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8463		if (sched & 1)
8464			v >>= 16;
8465		bpt = (v >> 8) & 0xff;
8466		cpt = v & 0xff;
8467		if (!cpt)
8468			*kbps = 0;	/* scheduler disabled */
8469		else {
8470			v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
8471			*kbps = (v * bpt) / 125;
8472		}
8473	}
8474	if (ipg) {
8475		addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
8476		t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
8477		v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8478		if (sched & 1)
8479			v >>= 16;
8480		v &= 0xffff;
8481		*ipg = (10000 * v) / core_ticks_per_usec(adap);
8482	}
8483}
8484
8485/**
8486 *	t4_load_cfg - download config file
8487 *	@adap: the adapter
8488 *	@cfg_data: the cfg text file to write
8489 *	@size: text file size
8490 *
8491 *	Write the supplied config text file to the card's serial flash.
8492 */
8493int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
8494{
8495	int ret, i, n, cfg_addr;
8496	unsigned int addr;
8497	unsigned int flash_cfg_start_sec;
8498	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8499
8500	cfg_addr = t4_flash_cfg_addr(adap);
8501	if (cfg_addr < 0)
8502		return cfg_addr;
8503
8504	addr = cfg_addr;
8505	flash_cfg_start_sec = addr / SF_SEC_SIZE;
8506
8507	if (size > FLASH_CFG_MAX_SIZE) {
8508		CH_ERR(adap, "cfg file too large, max is %u bytes\n",
8509		       FLASH_CFG_MAX_SIZE);
8510		return -EFBIG;
8511	}
8512
8513	i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,	/* # of sectors spanned */
8514			 sf_sec_size);
8515	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
8516				     flash_cfg_start_sec + i - 1);
8517	/*
8518	 * If size == 0 then we're simply erasing the FLASH sectors associated
8519	 * with the on-adapter Firmware Configuration File.
8520	 */
8521	if (ret || size == 0)
8522		goto out;
8523
8524	/* this will write to the flash up to SF_PAGE_SIZE at a time */
8525	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
8526		if ( (size - i) <  SF_PAGE_SIZE)
8527			n = size - i;
8528		else
8529			n = SF_PAGE_SIZE;
8530		ret = t4_write_flash(adap, addr, n, cfg_data, 1);
8531		if (ret)
8532			goto out;
8533
8534		addr += SF_PAGE_SIZE;
8535		cfg_data += SF_PAGE_SIZE;
8536	}
8537
8538out:
8539	if (ret)
8540		CH_ERR(adap, "config file %s failed %d\n",
8541		       (size == 0 ? "clear" : "download"), ret);
8542	return ret;
8543}
8544
8545/**
8546 *	t5_fw_init_extern_mem - initialize the external memory
8547 *	@adap: the adapter
8548 *
8549 *	Initializes the external memory on T5.
8550 */
8551int t5_fw_init_extern_mem(struct adapter *adap)
8552{
8553	u32 params[1], val[1];
8554	int ret;
8555
8556	if (!is_t5(adap))
8557		return 0;
8558
8559	val[0] = 0xff; /* Initialize all MCs */
8560	params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8561			V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
8562	ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
8563			FW_CMD_MAX_TIMEOUT);
8564
8565	return ret;
8566}
8567
8568/* BIOS boot headers */
8569typedef struct pci_expansion_rom_header {
8570	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
8571	u8	reserved[22]; /* Reserved per processor Architecture data */
8572	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
8573} pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
8574
8575/* Legacy PCI Expansion ROM Header */
8576typedef struct legacy_pci_expansion_rom_header {
8577	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
8578	u8	size512; /* Current Image Size in units of 512 bytes */
8579	u8	initentry_point[4];
8580	u8	cksum; /* Checksum computed on the entire Image */
8581	u8	reserved[16]; /* Reserved */
8582	u8	pcir_offset[2]; /* Offset to PCI Data Struture */
8583} legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
8584
8585/* EFI PCI Expansion ROM Header */
8586typedef struct efi_pci_expansion_rom_header {
8587	u8	signature[2]; // ROM signature. The value 0xaa55
8588	u8	initialization_size[2]; /* Units 512. Includes this header */
8589	u8	efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
8590	u8	efi_subsystem[2]; /* Subsystem value for EFI image header */
8591	u8	efi_machine_type[2]; /* Machine type from EFI image header */
8592	u8	compression_type[2]; /* Compression type. */
8593		/*
8594		 * Compression type definition
8595		 * 0x0: uncompressed
8596		 * 0x1: Compressed
8597		 * 0x2-0xFFFF: Reserved
8598		 */
8599	u8	reserved[8]; /* Reserved */
8600	u8	efi_image_header_offset[2]; /* Offset to EFI Image */
8601	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
8602} efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
8603
8604/* PCI Data Structure Format */
8605typedef struct pcir_data_structure { /* PCI Data Structure */
8606	u8	signature[4]; /* Signature. The string "PCIR" */
8607	u8	vendor_id[2]; /* Vendor Identification */
8608	u8	device_id[2]; /* Device Identification */
8609	u8	vital_product[2]; /* Pointer to Vital Product Data */
8610	u8	length[2]; /* PCIR Data Structure Length */
8611	u8	revision; /* PCIR Data Structure Revision */
8612	u8	class_code[3]; /* Class Code */
8613	u8	image_length[2]; /* Image Length. Multiple of 512B */
8614	u8	code_revision[2]; /* Revision Level of Code/Data */
8615	u8	code_type; /* Code Type. */
8616		/*
8617		 * PCI Expansion ROM Code Types
8618		 * 0x00: Intel IA-32, PC-AT compatible. Legacy
8619		 * 0x01: Open Firmware standard for PCI. FCODE
8620		 * 0x02: Hewlett-Packard PA RISC. HP reserved
8621		 * 0x03: EFI Image. EFI
8622		 * 0x04-0xFF: Reserved.
8623		 */
8624	u8	indicator; /* Indicator. Identifies the last image in the ROM */
8625	u8	reserved[2]; /* Reserved */
8626} pcir_data_t; /* PCI__DATA_STRUCTURE */
8627
8628/* BOOT constants */
8629enum {
8630	BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
8631	BOOT_SIGNATURE = 0xaa55,   /* signature of BIOS boot ROM */
8632	BOOT_SIZE_INC = 512,       /* image size measured in 512B chunks */
8633	BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
8634	BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment  */
8635	VENDOR_ID = 0x1425, /* Vendor ID */
8636	PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
8637};
8638
8639/*
8640 *	modify_device_id - Modifies the device ID of the Boot BIOS image
8641 *	@adatper: the device ID to write.
8642 *	@boot_data: the boot image to modify.
8643 *
8644 *	Write the supplied device ID to the boot BIOS image.
8645 */
8646static void modify_device_id(int device_id, u8 *boot_data)
8647{
8648	legacy_pci_exp_rom_header_t *header;
8649	pcir_data_t *pcir_header;
8650	u32 cur_header = 0;
8651
8652	/*
8653	 * Loop through all chained images and change the device ID's
8654	 */
8655	while (1) {
8656		header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
8657		pcir_header = (pcir_data_t *) &boot_data[cur_header +
8658			      le16_to_cpu(*(u16*)header->pcir_offset)];
8659
8660		/*
8661		 * Only modify the Device ID if code type is Legacy or HP.
8662		 * 0x00: Okay to modify
8663		 * 0x01: FCODE. Do not be modify
8664		 * 0x03: Okay to modify
8665		 * 0x04-0xFF: Do not modify
8666		 */
8667		if (pcir_header->code_type == 0x00) {
8668			u8 csum = 0;
8669			int i;
8670
8671			/*
8672			 * Modify Device ID to match current adatper
8673			 */
8674			*(u16*) pcir_header->device_id = device_id;
8675
8676			/*
8677			 * Set checksum temporarily to 0.
8678			 * We will recalculate it later.
8679			 */
8680			header->cksum = 0x0;
8681
8682			/*
8683			 * Calculate and update checksum
8684			 */
8685			for (i = 0; i < (header->size512 * 512); i++)
8686				csum += (u8)boot_data[cur_header + i];
8687
8688			/*
8689			 * Invert summed value to create the checksum
8690			 * Writing new checksum value directly to the boot data
8691			 */
8692			boot_data[cur_header + 7] = -csum;
8693
8694		} else if (pcir_header->code_type == 0x03) {
8695
8696			/*
8697			 * Modify Device ID to match current adatper
8698			 */
8699			*(u16*) pcir_header->device_id = device_id;
8700
8701		}
8702
8703
8704		/*
8705		 * Check indicator element to identify if this is the last
8706		 * image in the ROM.
8707		 */
8708		if (pcir_header->indicator & 0x80)
8709			break;
8710
8711		/*
8712		 * Move header pointer up to the next image in the ROM.
8713		 */
8714		cur_header += header->size512 * 512;
8715	}
8716}
8717
8718/*
8719 *	t4_load_boot - download boot flash
8720 *	@adapter: the adapter
8721 *	@boot_data: the boot image to write
8722 *	@boot_addr: offset in flash to write boot_data
8723 *	@size: image size
8724 *
8725 *	Write the supplied boot image to the card's serial flash.
8726 *	The boot image has the following sections: a 28-byte header and the
8727 *	boot image.
8728 */
8729int t4_load_boot(struct adapter *adap, u8 *boot_data,
8730		 unsigned int boot_addr, unsigned int size)
8731{
8732	pci_exp_rom_header_t *header;
8733	int pcir_offset ;
8734	pcir_data_t *pcir_header;
8735	int ret, addr;
8736	uint16_t device_id;
8737	unsigned int i;
8738	unsigned int boot_sector = (boot_addr * 1024 );
8739	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8740
8741	/*
8742	 * Make sure the boot image does not encroach on the firmware region
8743	 */
8744	if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
8745		CH_ERR(adap, "boot image encroaching on firmware region\n");
8746		return -EFBIG;
8747	}
8748
8749	/*
8750	 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
8751	 * and Boot configuration data sections. These 3 boot sections span
8752	 * sectors 0 to 7 in flash and live right before the FW image location.
8753	 */
8754	i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
8755			sf_sec_size);
8756	ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
8757				     (boot_sector >> 16) + i - 1);
8758
8759	/*
8760	 * If size == 0 then we're simply erasing the FLASH sectors associated
8761	 * with the on-adapter option ROM file
8762	 */
8763	if (ret || (size == 0))
8764		goto out;
8765
8766	/* Get boot header */
8767	header = (pci_exp_rom_header_t *)boot_data;
8768	pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
8769	/* PCIR Data Structure */
8770	pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
8771
8772	/*
8773	 * Perform some primitive sanity testing to avoid accidentally
8774	 * writing garbage over the boot sectors.  We ought to check for
8775	 * more but it's not worth it for now ...
8776	 */
8777	if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
8778		CH_ERR(adap, "boot image too small/large\n");
8779		return -EFBIG;
8780	}
8781
8782#ifndef CHELSIO_T4_DIAGS
8783	/*
8784	 * Check BOOT ROM header signature
8785	 */
8786	if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
8787		CH_ERR(adap, "Boot image missing signature\n");
8788		return -EINVAL;
8789	}
8790
8791	/*
8792	 * Check PCI header signature
8793	 */
8794	if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
8795		CH_ERR(adap, "PCI header missing signature\n");
8796		return -EINVAL;
8797	}
8798
8799	/*
8800	 * Check Vendor ID matches Chelsio ID
8801	 */
8802	if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
8803		CH_ERR(adap, "Vendor ID missing signature\n");
8804		return -EINVAL;
8805	}
8806#endif
8807
8808	/*
8809	 * Retrieve adapter's device ID
8810	 */
8811	t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
8812	/* Want to deal with PF 0 so I strip off PF 4 indicator */
8813	device_id = device_id & 0xf0ff;
8814
8815	/*
8816	 * Check PCIE Device ID
8817	 */
8818	if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
8819		/*
8820		 * Change the device ID in the Boot BIOS image to match
8821		 * the Device ID of the current adapter.
8822		 */
8823		modify_device_id(device_id, boot_data);
8824	}
8825
8826	/*
8827	 * Skip over the first SF_PAGE_SIZE worth of data and write it after
8828	 * we finish copying the rest of the boot image. This will ensure
8829	 * that the BIOS boot header will only be written if the boot image
8830	 * was written in full.
8831	 */
8832	addr = boot_sector;
8833	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
8834		addr += SF_PAGE_SIZE;
8835		boot_data += SF_PAGE_SIZE;
8836		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
8837		if (ret)
8838			goto out;
8839	}
8840
8841	ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
8842			     (const u8 *)header, 0);
8843
8844out:
8845	if (ret)
8846		CH_ERR(adap, "boot image download failed, error %d\n", ret);
8847	return ret;
8848}
8849
8850/*
8851 *	t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
8852 *	@adapter: the adapter
8853 *
8854 *	Return the address within the flash where the OptionROM Configuration
8855 *	is stored, or an error if the device FLASH is too small to contain
8856 *	a OptionROM Configuration.
8857 */
8858static int t4_flash_bootcfg_addr(struct adapter *adapter)
8859{
8860	/*
8861	 * If the device FLASH isn't large enough to hold a Firmware
8862	 * Configuration File, return an error.
8863	 */
8864	if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
8865		return -ENOSPC;
8866
8867	return FLASH_BOOTCFG_START;
8868}
8869
8870int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
8871{
8872	int ret, i, n, cfg_addr;
8873	unsigned int addr;
8874	unsigned int flash_cfg_start_sec;
8875	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8876
8877	cfg_addr = t4_flash_bootcfg_addr(adap);
8878	if (cfg_addr < 0)
8879		return cfg_addr;
8880
8881	addr = cfg_addr;
8882	flash_cfg_start_sec = addr / SF_SEC_SIZE;
8883
8884	if (size > FLASH_BOOTCFG_MAX_SIZE) {
8885		CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
8886			FLASH_BOOTCFG_MAX_SIZE);
8887		return -EFBIG;
8888	}
8889
8890	i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
8891			 sf_sec_size);
8892	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
8893					flash_cfg_start_sec + i - 1);
8894
8895	/*
8896	 * If size == 0 then we're simply erasing the FLASH sectors associated
8897	 * with the on-adapter OptionROM Configuration File.
8898	 */
8899	if (ret || size == 0)
8900		goto out;
8901
8902	/* this will write to the flash up to SF_PAGE_SIZE at a time */
8903	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
8904		if ( (size - i) <  SF_PAGE_SIZE)
8905			n = size - i;
8906		else
8907			n = SF_PAGE_SIZE;
8908		ret = t4_write_flash(adap, addr, n, cfg_data, 0);
8909		if (ret)
8910			goto out;
8911
8912		addr += SF_PAGE_SIZE;
8913		cfg_data += SF_PAGE_SIZE;
8914	}
8915
8916out:
8917	if (ret)
8918		CH_ERR(adap, "boot config data %s failed %d\n",
8919				(size == 0 ? "clear" : "download"), ret);
8920	return ret;
8921}
8922
8923/**
8924 *	t4_set_filter_mode - configure the optional components of filter tuples
8925 *	@adap: the adapter
8926 *	@mode_map: a bitmap selcting which optional filter components to enable
8927 *
8928 *	Sets the filter mode by selecting the optional components to enable
8929 *	in filter tuples.  Returns 0 on success and a negative error if the
8930 *	requested mode needs more bits than are available for optional
8931 *	components.
8932 */
8933int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map)
8934{
8935	static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 };
8936
8937	int i, nbits = 0;
8938
8939	for (i = S_FCOE; i <= S_FRAGMENTATION; i++)
8940		if (mode_map & (1 << i))
8941			nbits += width[i];
8942	if (nbits > FILTER_OPT_LEN)
8943		return -EINVAL;
8944	if (t4_use_ldst(adap))
8945		t4_fw_tp_pio_rw(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, 0);
8946	else
8947		t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, &mode_map,
8948				  1, A_TP_VLAN_PRI_MAP);
8949	read_filter_mode_and_ingress_config(adap);
8950
8951	return 0;
8952}
8953
8954/**
8955 *	t4_clr_port_stats - clear port statistics
8956 *	@adap: the adapter
8957 *	@idx: the port index
8958 *
8959 *	Clear HW statistics for the given port.
8960 */
8961void t4_clr_port_stats(struct adapter *adap, int idx)
8962{
8963	unsigned int i;
8964	u32 bgmap = t4_get_mps_bg_map(adap, idx);
8965	u32 port_base_addr;
8966
8967	if (is_t4(adap))
8968		port_base_addr = PORT_BASE(idx);
8969	else
8970		port_base_addr = T5_PORT_BASE(idx);
8971
8972	for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
8973			i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
8974		t4_write_reg(adap, port_base_addr + i, 0);
8975	for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
8976			i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
8977		t4_write_reg(adap, port_base_addr + i, 0);
8978	for (i = 0; i < 4; i++)
8979		if (bgmap & (1 << i)) {
8980			t4_write_reg(adap,
8981			A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
8982			t4_write_reg(adap,
8983			A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
8984		}
8985}
8986
8987/**
8988 *	t4_i2c_rd - read I2C data from adapter
8989 *	@adap: the adapter
8990 *	@port: Port number if per-port device; <0 if not
8991 *	@devid: per-port device ID or absolute device ID
8992 *	@offset: byte offset into device I2C space
8993 *	@len: byte length of I2C space data
8994 *	@buf: buffer in which to return I2C data
8995 *
8996 *	Reads the I2C data from the indicated device and location.
8997 */
8998int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
8999	      int port, unsigned int devid,
9000	      unsigned int offset, unsigned int len,
9001	      u8 *buf)
9002{
9003	u32 ldst_addrspace;
9004	struct fw_ldst_cmd ldst;
9005	int ret;
9006
9007	if (port >= 4 ||
9008	    devid >= 256 ||
9009	    offset >= 256 ||
9010	    len > sizeof ldst.u.i2c.data)
9011		return -EINVAL;
9012
9013	memset(&ldst, 0, sizeof ldst);
9014	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
9015	ldst.op_to_addrspace =
9016		cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9017			    F_FW_CMD_REQUEST |
9018			    F_FW_CMD_READ |
9019			    ldst_addrspace);
9020	ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
9021	ldst.u.i2c.pid = (port < 0 ? 0xff : port);
9022	ldst.u.i2c.did = devid;
9023	ldst.u.i2c.boffset = offset;
9024	ldst.u.i2c.blen = len;
9025	ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
9026	if (!ret)
9027		memcpy(buf, ldst.u.i2c.data, len);
9028	return ret;
9029}
9030
9031/**
9032 *	t4_i2c_wr - write I2C data to adapter
9033 *	@adap: the adapter
9034 *	@port: Port number if per-port device; <0 if not
9035 *	@devid: per-port device ID or absolute device ID
9036 *	@offset: byte offset into device I2C space
9037 *	@len: byte length of I2C space data
9038 *	@buf: buffer containing new I2C data
9039 *
9040 *	Write the I2C data to the indicated device and location.
9041 */
9042int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
9043	      int port, unsigned int devid,
9044	      unsigned int offset, unsigned int len,
9045	      u8 *buf)
9046{
9047	u32 ldst_addrspace;
9048	struct fw_ldst_cmd ldst;
9049
9050	if (port >= 4 ||
9051	    devid >= 256 ||
9052	    offset >= 256 ||
9053	    len > sizeof ldst.u.i2c.data)
9054		return -EINVAL;
9055
9056	memset(&ldst, 0, sizeof ldst);
9057	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
9058	ldst.op_to_addrspace =
9059		cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9060			    F_FW_CMD_REQUEST |
9061			    F_FW_CMD_WRITE |
9062			    ldst_addrspace);
9063	ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
9064	ldst.u.i2c.pid = (port < 0 ? 0xff : port);
9065	ldst.u.i2c.did = devid;
9066	ldst.u.i2c.boffset = offset;
9067	ldst.u.i2c.blen = len;
9068	memcpy(ldst.u.i2c.data, buf, len);
9069	return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
9070}
9071
9072/**
9073 * 	t4_sge_ctxt_rd - read an SGE context through FW
9074 * 	@adap: the adapter
9075 * 	@mbox: mailbox to use for the FW command
9076 * 	@cid: the context id
9077 * 	@ctype: the context type
9078 * 	@data: where to store the context data
9079 *
9080 * 	Issues a FW command through the given mailbox to read an SGE context.
9081 */
9082int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
9083		   enum ctxt_type ctype, u32 *data)
9084{
9085	int ret;
9086	struct fw_ldst_cmd c;
9087
9088	if (ctype == CTXT_EGRESS)
9089		ret = FW_LDST_ADDRSPC_SGE_EGRC;
9090	else if (ctype == CTXT_INGRESS)
9091		ret = FW_LDST_ADDRSPC_SGE_INGC;
9092	else if (ctype == CTXT_FLM)
9093		ret = FW_LDST_ADDRSPC_SGE_FLMC;
9094	else
9095		ret = FW_LDST_ADDRSPC_SGE_CONMC;
9096
9097	memset(&c, 0, sizeof(c));
9098	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9099					F_FW_CMD_REQUEST | F_FW_CMD_READ |
9100					V_FW_LDST_CMD_ADDRSPACE(ret));
9101	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9102	c.u.idctxt.physid = cpu_to_be32(cid);
9103
9104	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9105	if (ret == 0) {
9106		data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
9107		data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
9108		data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
9109		data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
9110		data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
9111		data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
9112	}
9113	return ret;
9114}
9115
9116/**
9117 * 	t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9118 * 	@adap: the adapter
9119 * 	@cid: the context id
9120 * 	@ctype: the context type
9121 * 	@data: where to store the context data
9122 *
9123 * 	Reads an SGE context directly, bypassing FW.  This is only for
9124 * 	debugging when FW is unavailable.
9125 */
9126int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
9127		      u32 *data)
9128{
9129	int i, ret;
9130
9131	t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
9132	ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
9133	if (!ret)
9134		for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
9135			*data++ = t4_read_reg(adap, i);
9136	return ret;
9137}
9138
9139int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
9140    		    int sleep_ok)
9141{
9142	struct fw_sched_cmd cmd;
9143
9144	memset(&cmd, 0, sizeof(cmd));
9145	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9146				      F_FW_CMD_REQUEST |
9147				      F_FW_CMD_WRITE);
9148	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9149
9150	cmd.u.config.sc = FW_SCHED_SC_CONFIG;
9151	cmd.u.config.type = type;
9152	cmd.u.config.minmaxen = minmaxen;
9153
9154	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9155			       NULL, sleep_ok);
9156}
9157
9158int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9159		    int rateunit, int ratemode, int channel, int cl,
9160		    int minrate, int maxrate, int weight, int pktsize,
9161		    int sleep_ok)
9162{
9163	struct fw_sched_cmd cmd;
9164
9165	memset(&cmd, 0, sizeof(cmd));
9166	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9167				      F_FW_CMD_REQUEST |
9168				      F_FW_CMD_WRITE);
9169	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9170
9171	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9172	cmd.u.params.type = type;
9173	cmd.u.params.level = level;
9174	cmd.u.params.mode = mode;
9175	cmd.u.params.ch = channel;
9176	cmd.u.params.cl = cl;
9177	cmd.u.params.unit = rateunit;
9178	cmd.u.params.rate = ratemode;
9179	cmd.u.params.min = cpu_to_be32(minrate);
9180	cmd.u.params.max = cpu_to_be32(maxrate);
9181	cmd.u.params.weight = cpu_to_be16(weight);
9182	cmd.u.params.pktsize = cpu_to_be16(pktsize);
9183
9184	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9185			       NULL, sleep_ok);
9186}
9187
9188/*
9189 *	t4_config_watchdog - configure (enable/disable) a watchdog timer
9190 *	@adapter: the adapter
9191 * 	@mbox: mailbox to use for the FW command
9192 * 	@pf: the PF owning the queue
9193 * 	@vf: the VF owning the queue
9194 *	@timeout: watchdog timeout in ms
9195 *	@action: watchdog timer / action
9196 *
9197 *	There are separate watchdog timers for each possible watchdog
9198 *	action.  Configure one of the watchdog timers by setting a non-zero
9199 *	timeout.  Disable a watchdog timer by using a timeout of zero.
9200 */
9201int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
9202		       unsigned int pf, unsigned int vf,
9203		       unsigned int timeout, unsigned int action)
9204{
9205	struct fw_watchdog_cmd wdog;
9206	unsigned int ticks;
9207
9208	/*
9209	 * The watchdog command expects a timeout in units of 10ms so we need
9210	 * to convert it here (via rounding) and force a minimum of one 10ms
9211	 * "tick" if the timeout is non-zero but the conversion results in 0
9212	 * ticks.
9213	 */
9214	ticks = (timeout + 5)/10;
9215	if (timeout && !ticks)
9216		ticks = 1;
9217
9218	memset(&wdog, 0, sizeof wdog);
9219	wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
9220				     F_FW_CMD_REQUEST |
9221				     F_FW_CMD_WRITE |
9222				     V_FW_PARAMS_CMD_PFN(pf) |
9223				     V_FW_PARAMS_CMD_VFN(vf));
9224	wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
9225	wdog.timeout = cpu_to_be32(ticks);
9226	wdog.action = cpu_to_be32(action);
9227
9228	return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
9229}
9230
9231int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
9232{
9233	struct fw_devlog_cmd devlog_cmd;
9234	int ret;
9235
9236	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9237	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9238					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
9239	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9240	ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9241			 sizeof(devlog_cmd), &devlog_cmd);
9242	if (ret)
9243		return ret;
9244
9245	*level = devlog_cmd.level;
9246	return 0;
9247}
9248
9249int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
9250{
9251	struct fw_devlog_cmd devlog_cmd;
9252
9253	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9254	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9255					     F_FW_CMD_REQUEST |
9256					     F_FW_CMD_WRITE);
9257	devlog_cmd.level = level;
9258	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9259	return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9260			  sizeof(devlog_cmd), &devlog_cmd);
9261}
9262