cxgb_common.h revision 331722
1/************************************************************************** 2 3Copyright (c) 2007-2009, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28$FreeBSD: stable/11/sys/dev/cxgb/common/cxgb_common.h 331722 2018-03-29 02:50:57Z eadler $ 29 30***************************************************************************/ 31#ifndef __CHELSIO_COMMON_H 32#define __CHELSIO_COMMON_H 33 34#include <cxgb_osdep.h> 35 36enum { 37 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ 38 EEPROMSIZE = 8192, /* Serial EEPROM size */ 39 SERNUM_LEN = 16, /* Serial # length */ 40 ECNUM_LEN = 16, /* EC # length */ 41 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 42 TCB_SIZE = 128, /* TCB size */ 43 NMTUS = 16, /* size of MTU table */ 44 NCCTRL_WIN = 32, /* # of congestion control windows */ 45 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 46 PROTO_SRAM_LINES = 128, /* size of protocol sram */ 47 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ 48}; 49 50#define MAX_RX_COALESCING_LEN 12288U 51 52enum { 53 PAUSE_RX = 1 << 0, 54 PAUSE_TX = 1 << 1, 55 PAUSE_AUTONEG = 1 << 2 56}; 57 58enum { 59 SUPPORTED_LINK_IRQ = 1 << 24, 60 /* skip 25 */ 61 SUPPORTED_MISC_IRQ = 1 << 26, 62 SUPPORTED_IRQ = (SUPPORTED_LINK_IRQ | SUPPORTED_MISC_IRQ), 63}; 64 65enum { /* adapter interrupt-maintained statistics */ 66 STAT_ULP_CH0_PBL_OOB, 67 STAT_ULP_CH1_PBL_OOB, 68 STAT_PCI_CORR_ECC, 69 70 IRQ_NUM_STATS /* keep last */ 71}; 72 73enum { 74 TP_VERSION_MAJOR = 1, 75 TP_VERSION_MINOR = 1, 76 TP_VERSION_MICRO = 0 77}; 78 79#define S_TP_VERSION_MAJOR 16 80#define M_TP_VERSION_MAJOR 0xFF 81#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 82#define G_TP_VERSION_MAJOR(x) \ 83 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 84 85#define S_TP_VERSION_MINOR 8 86#define M_TP_VERSION_MINOR 0xFF 87#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 88#define G_TP_VERSION_MINOR(x) \ 89 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 90 91#define S_TP_VERSION_MICRO 0 92#define M_TP_VERSION_MICRO 0xFF 93#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 94#define G_TP_VERSION_MICRO(x) \ 95 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 96 97enum { 98 FW_VERSION_MAJOR = 7, 99 FW_VERSION_MINOR = 11, 100 FW_VERSION_MICRO = 0 101}; 102 103enum { 104 LA_CTRL = 0x80, 105 LA_DATA = 0x84, 106 LA_ENTRIES = 512 107}; 108 109enum { 110 IOQ_ENTRIES = 7 111}; 112 113enum { 114 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 115 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 116 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 117}; 118 119enum sge_context_type { /* SGE egress context types */ 120 SGE_CNTXT_RDMA = 0, 121 SGE_CNTXT_ETH = 2, 122 SGE_CNTXT_OFLD = 4, 123 SGE_CNTXT_CTRL = 5 124}; 125 126enum { 127 AN_PKT_SIZE = 32, /* async notification packet size */ 128 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 129}; 130 131struct sg_ent { /* SGE scatter/gather entry */ 132 __be32 len[2]; 133 __be64 addr[2]; 134}; 135 136#ifndef SGE_NUM_GENBITS 137/* Must be 1 or 2 */ 138# define SGE_NUM_GENBITS 2 139#endif 140 141#define TX_DESC_FLITS 16U 142#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 143 144#define MAX_PHYINTRS 4 145 146struct cphy; 147 148struct mdio_ops { 149 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 150 int reg_addr, unsigned int *val); 151 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 152 int reg_addr, unsigned int val); 153}; 154 155struct adapter_info { 156 unsigned char nports0; /* # of ports on channel 0 */ 157 unsigned char nports1; /* # of ports on channel 1 */ 158 unsigned char phy_base_addr; /* MDIO PHY base address */ 159 unsigned int gpio_out; /* GPIO output settings */ 160 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */ 161 unsigned long caps; /* adapter capabilities */ 162 const struct mdio_ops *mdio_ops; /* MDIO operations */ 163 const char *desc; /* product description */ 164}; 165 166struct mc5_stats { 167 unsigned long parity_err; 168 unsigned long active_rgn_full; 169 unsigned long nfa_srch_err; 170 unsigned long unknown_cmd; 171 unsigned long reqq_parity_err; 172 unsigned long dispq_parity_err; 173 unsigned long del_act_empty; 174}; 175 176struct mc7_stats { 177 unsigned long corr_err; 178 unsigned long uncorr_err; 179 unsigned long parity_err; 180 unsigned long addr_err; 181}; 182 183struct mac_stats { 184 u64 tx_octets; /* total # of octets in good frames */ 185 u64 tx_octets_bad; /* total # of octets in error frames */ 186 u64 tx_frames; /* all good frames */ 187 u64 tx_mcast_frames; /* good multicast frames */ 188 u64 tx_bcast_frames; /* good broadcast frames */ 189 u64 tx_pause; /* # of transmitted pause frames */ 190 u64 tx_deferred; /* frames with deferred transmissions */ 191 u64 tx_late_collisions; /* # of late collisions */ 192 u64 tx_total_collisions; /* # of total collisions */ 193 u64 tx_excess_collisions; /* frame errors from excessive collissions */ 194 u64 tx_underrun; /* # of Tx FIFO underruns */ 195 u64 tx_len_errs; /* # of Tx length errors */ 196 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 197 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 198 u64 tx_fcs_errs; /* # of frames with bad FCS */ 199 200 u64 tx_frames_64; /* # of Tx frames in a particular range */ 201 u64 tx_frames_65_127; 202 u64 tx_frames_128_255; 203 u64 tx_frames_256_511; 204 u64 tx_frames_512_1023; 205 u64 tx_frames_1024_1518; 206 u64 tx_frames_1519_max; 207 208 u64 rx_octets; /* total # of octets in good frames */ 209 u64 rx_octets_bad; /* total # of octets in error frames */ 210 u64 rx_frames; /* all good frames */ 211 u64 rx_mcast_frames; /* good multicast frames */ 212 u64 rx_bcast_frames; /* good broadcast frames */ 213 u64 rx_pause; /* # of received pause frames */ 214 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 215 u64 rx_align_errs; /* alignment errors */ 216 u64 rx_symbol_errs; /* symbol errors */ 217 u64 rx_data_errs; /* data errors */ 218 u64 rx_sequence_errs; /* sequence errors */ 219 u64 rx_runt; /* # of runt frames */ 220 u64 rx_jabber; /* # of jabber frames */ 221 u64 rx_short; /* # of short frames */ 222 u64 rx_too_long; /* # of oversized frames */ 223 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 224 225 u64 rx_frames_64; /* # of Rx frames in a particular range */ 226 u64 rx_frames_65_127; 227 u64 rx_frames_128_255; 228 u64 rx_frames_256_511; 229 u64 rx_frames_512_1023; 230 u64 rx_frames_1024_1518; 231 u64 rx_frames_1519_max; 232 233 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 234 235 unsigned long tx_fifo_parity_err; 236 unsigned long rx_fifo_parity_err; 237 unsigned long tx_fifo_urun; 238 unsigned long rx_fifo_ovfl; 239 unsigned long serdes_signal_loss; 240 unsigned long xaui_pcs_ctc_err; 241 unsigned long xaui_pcs_align_change; 242 243 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 244 unsigned long num_resets; /* # times reset due to stuck TX */ 245 246 unsigned long link_faults; /* # detected link faults */ 247}; 248 249struct tp_mib_stats { 250 u32 ipInReceive_hi; 251 u32 ipInReceive_lo; 252 u32 ipInHdrErrors_hi; 253 u32 ipInHdrErrors_lo; 254 u32 ipInAddrErrors_hi; 255 u32 ipInAddrErrors_lo; 256 u32 ipInUnknownProtos_hi; 257 u32 ipInUnknownProtos_lo; 258 u32 ipInDiscards_hi; 259 u32 ipInDiscards_lo; 260 u32 ipInDelivers_hi; 261 u32 ipInDelivers_lo; 262 u32 ipOutRequests_hi; 263 u32 ipOutRequests_lo; 264 u32 ipOutDiscards_hi; 265 u32 ipOutDiscards_lo; 266 u32 ipOutNoRoutes_hi; 267 u32 ipOutNoRoutes_lo; 268 u32 ipReasmTimeout; 269 u32 ipReasmReqds; 270 u32 ipReasmOKs; 271 u32 ipReasmFails; 272 273 u32 reserved[8]; 274 275 u32 tcpActiveOpens; 276 u32 tcpPassiveOpens; 277 u32 tcpAttemptFails; 278 u32 tcpEstabResets; 279 u32 tcpOutRsts; 280 u32 tcpCurrEstab; 281 u32 tcpInSegs_hi; 282 u32 tcpInSegs_lo; 283 u32 tcpOutSegs_hi; 284 u32 tcpOutSegs_lo; 285 u32 tcpRetransSeg_hi; 286 u32 tcpRetransSeg_lo; 287 u32 tcpInErrs_hi; 288 u32 tcpInErrs_lo; 289 u32 tcpRtoMin; 290 u32 tcpRtoMax; 291}; 292 293struct tp_params { 294 unsigned int nchan; /* # of channels */ 295 unsigned int pmrx_size; /* total PMRX capacity */ 296 unsigned int pmtx_size; /* total PMTX capacity */ 297 unsigned int cm_size; /* total CM capacity */ 298 unsigned int chan_rx_size; /* per channel Rx size */ 299 unsigned int chan_tx_size; /* per channel Tx size */ 300 unsigned int rx_pg_size; /* Rx page size */ 301 unsigned int tx_pg_size; /* Tx page size */ 302 unsigned int rx_num_pgs; /* # of Rx pages */ 303 unsigned int tx_num_pgs; /* # of Tx pages */ 304 unsigned int ntimer_qs; /* # of timer queues */ 305 unsigned int tre; /* log2 of core clocks per TP tick */ 306 unsigned int dack_re; /* DACK timer resolution */ 307}; 308 309struct qset_params { /* SGE queue set parameters */ 310 unsigned int polling; /* polling/interrupt service for rspq */ 311 unsigned int lro; /* large receive offload */ 312 unsigned int coalesce_usecs; /* irq coalescing timer */ 313 unsigned int rspq_size; /* # of entries in response queue */ 314 unsigned int fl_size; /* # of entries in regular free list */ 315 unsigned int jumbo_size; /* # of entries in jumbo free list */ 316 unsigned int jumbo_buf_size; /* buffer size of jumbo entry */ 317 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 318 unsigned int cong_thres; /* FL congestion threshold */ 319 unsigned int vector; /* Interrupt (line or vector) number */ 320}; 321 322struct sge_params { 323 unsigned int max_pkt_size; /* max offload pkt size */ 324 struct qset_params qset[SGE_QSETS]; 325}; 326 327struct mc5_params { 328 unsigned int mode; /* selects MC5 width */ 329 unsigned int nservers; /* size of server region */ 330 unsigned int nfilters; /* size of filter region */ 331 unsigned int nroutes; /* size of routing region */ 332}; 333 334/* Default MC5 region sizes */ 335enum { 336 DEFAULT_NSERVERS = 512, 337 DEFAULT_NFILTERS = 128 338}; 339 340/* MC5 modes, these must be non-0 */ 341enum { 342 MC5_MODE_144_BIT = 1, 343 MC5_MODE_72_BIT = 2 344}; 345 346/* MC5 min active region size */ 347enum { MC5_MIN_TIDS = 16 }; 348 349struct vpd_params { 350 unsigned int cclk; 351 unsigned int mclk; 352 unsigned int uclk; 353 unsigned int mdc; 354 unsigned int mem_timing; 355 u8 sn[SERNUM_LEN + 1]; 356 u8 ec[ECNUM_LEN + 1]; 357 u8 eth_base[6]; 358 u8 port_type[MAX_NPORTS]; 359 unsigned short xauicfg[2]; 360}; 361 362struct generic_vpd { 363 u32 offset; 364 u32 len; 365 u8 *data; 366}; 367 368enum { MAX_VPD_BYTES = 32000 }; 369 370struct pci_params { 371 unsigned int vpd_cap_addr; 372 unsigned int pcie_cap_addr; 373 unsigned short speed; 374 unsigned char width; 375 unsigned char variant; 376}; 377 378enum { 379 PCI_VARIANT_PCI, 380 PCI_VARIANT_PCIX_MODE1_PARITY, 381 PCI_VARIANT_PCIX_MODE1_ECC, 382 PCI_VARIANT_PCIX_266_MODE2, 383 PCI_VARIANT_PCIE 384}; 385 386struct adapter_params { 387 struct sge_params sge; 388 struct mc5_params mc5; 389 struct tp_params tp; 390 struct vpd_params vpd; 391 struct pci_params pci; 392 393 const struct adapter_info *info; 394 395 unsigned short mtus[NMTUS]; 396 unsigned short a_wnd[NCCTRL_WIN]; 397 unsigned short b_wnd[NCCTRL_WIN]; 398 unsigned int nports; /* # of ethernet ports */ 399 unsigned int chan_map; /* bitmap of in-use Tx channels */ 400 unsigned int stats_update_period; /* MAC stats accumulation period */ 401 unsigned int linkpoll_period; /* link poll period in 0.1s */ 402 unsigned int rev; /* chip revision */ 403 unsigned int offload; 404}; 405 406enum { /* chip revisions */ 407 T3_REV_A = 0, 408 T3_REV_B = 2, 409 T3_REV_B2 = 3, 410 T3_REV_C = 4, 411}; 412 413struct trace_params { 414 u32 sip; 415 u32 sip_mask; 416 u32 dip; 417 u32 dip_mask; 418 u16 sport; 419 u16 sport_mask; 420 u16 dport; 421 u16 dport_mask; 422 u32 vlan:12; 423 u32 vlan_mask:12; 424 u32 intf:4; 425 u32 intf_mask:4; 426 u8 proto; 427 u8 proto_mask; 428}; 429 430struct link_config { 431 unsigned int supported; /* link capabilities */ 432 unsigned int advertising; /* advertised capabilities */ 433 unsigned short requested_speed; /* speed user has requested */ 434 unsigned short speed; /* actual link speed */ 435 unsigned char requested_duplex; /* duplex user has requested */ 436 unsigned char duplex; /* actual link duplex */ 437 unsigned char requested_fc; /* flow control user has requested */ 438 unsigned char fc; /* actual link flow control */ 439 unsigned char autoneg; /* autonegotiating? */ 440 unsigned int link_ok; /* link up? */ 441}; 442 443#define SPEED_INVALID 0xffff 444#define DUPLEX_INVALID 0xff 445 446struct mc5 { 447 adapter_t *adapter; 448 unsigned int tcam_size; 449 unsigned char part_type; 450 unsigned char parity_enabled; 451 unsigned char mode; 452 struct mc5_stats stats; 453}; 454 455static inline unsigned int t3_mc5_size(const struct mc5 *p) 456{ 457 return p->tcam_size; 458} 459 460struct mc7 { 461 adapter_t *adapter; /* backpointer to adapter */ 462 unsigned int size; /* memory size in bytes */ 463 unsigned int width; /* MC7 interface width */ 464 unsigned int offset; /* register address offset for MC7 instance */ 465 const char *name; /* name of MC7 instance */ 466 struct mc7_stats stats; /* MC7 statistics */ 467}; 468 469static inline unsigned int t3_mc7_size(const struct mc7 *p) 470{ 471 return p->size; 472} 473 474struct cmac { 475 adapter_t *adapter; 476 unsigned int offset; 477 unsigned char nucast; /* # of address filters for unicast MACs */ 478 unsigned char multiport; /* multiple ports connected to this MAC */ 479 unsigned char ext_port; /* external MAC port */ 480 unsigned char promisc_map; /* which external ports are promiscuous */ 481 unsigned int tx_tcnt; 482 unsigned int tx_xcnt; 483 u64 tx_mcnt; 484 unsigned int rx_xcnt; 485 unsigned int rx_ocnt; 486 u64 rx_mcnt; 487 unsigned int toggle_cnt; 488 unsigned int txen; 489 unsigned int was_reset; 490 u64 rx_pause; 491 struct mac_stats stats; 492}; 493 494enum { 495 MAC_DIRECTION_RX = 1, 496 MAC_DIRECTION_TX = 2, 497 MAC_RXFIFO_SIZE = 32768 498}; 499 500/* IEEE 802.3 specified MDIO devices */ 501enum { 502 MDIO_DEV_PMA_PMD = 1, 503 MDIO_DEV_WIS = 2, 504 MDIO_DEV_PCS = 3, 505 MDIO_DEV_XGXS = 4, 506 MDIO_DEV_ANEG = 7, 507 MDIO_DEV_VEND1 = 30, 508 MDIO_DEV_VEND2 = 31 509}; 510 511/* LASI control and status registers */ 512enum { 513 RX_ALARM_CTRL = 0x9000, 514 TX_ALARM_CTRL = 0x9001, 515 LASI_CTRL = 0x9002, 516 RX_ALARM_STAT = 0x9003, 517 TX_ALARM_STAT = 0x9004, 518 LASI_STAT = 0x9005 519}; 520 521/* PHY loopback direction */ 522enum { 523 PHY_LOOPBACK_TX = 1, 524 PHY_LOOPBACK_RX = 2 525}; 526 527/* PHY interrupt types */ 528enum { 529 cphy_cause_link_change = 1, 530 cphy_cause_fifo_error = 2, 531 cphy_cause_module_change = 4, 532 cphy_cause_alarm = 8, 533}; 534 535/* PHY module types */ 536enum { 537 phy_modtype_none, 538 phy_modtype_sr, 539 phy_modtype_lr, 540 phy_modtype_lrm, 541 phy_modtype_twinax, 542 phy_modtype_twinax_long, 543 phy_modtype_unknown 544}; 545 546enum { 547 PHY_LINK_DOWN = 0, 548 PHY_LINK_UP, 549 PHY_LINK_PARTIAL 550}; 551 552/* PHY operations */ 553struct cphy_ops { 554 int (*reset)(struct cphy *phy, int wait); 555 556 int (*intr_enable)(struct cphy *phy); 557 int (*intr_disable)(struct cphy *phy); 558 int (*intr_clear)(struct cphy *phy); 559 int (*intr_handler)(struct cphy *phy); 560 561 int (*autoneg_enable)(struct cphy *phy); 562 int (*autoneg_restart)(struct cphy *phy); 563 564 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 565 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 566 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 567 int (*get_link_status)(struct cphy *phy, int *link_state, int *speed, 568 int *duplex, int *fc); 569 int (*power_down)(struct cphy *phy, int enable); 570}; 571 572/* A PHY instance */ 573struct cphy { 574 u8 addr; /* PHY address */ 575 u8 modtype; /* PHY module type */ 576 u8 rst; 577 unsigned int priv; /* scratch pad */ 578 unsigned int caps; /* PHY capabilities */ 579 adapter_t *adapter; /* associated adapter */ 580 pinfo_t *pinfo; /* associated port */ 581 const char *desc; /* PHY description */ 582 unsigned long fifo_errors; /* FIFO over/under-flows */ 583 const struct cphy_ops *ops; /* PHY operations */ 584 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 585 int reg_addr, unsigned int *val); 586 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 587 int reg_addr, unsigned int val); 588}; 589 590/* Convenience MDIO read/write wrappers */ 591static inline int mdio_read(struct cphy *phy, int mmd, int reg, 592 unsigned int *valp) 593{ 594 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 595} 596 597static inline int mdio_write(struct cphy *phy, int mmd, int reg, 598 unsigned int val) 599{ 600 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 601} 602 603/* Convenience initializer */ 604static inline void cphy_init(struct cphy *phy, adapter_t *adapter, pinfo_t *pinfo, 605 int phy_addr, struct cphy_ops *phy_ops, 606 const struct mdio_ops *mdio_ops, unsigned int caps, 607 const char *desc) 608{ 609 phy->addr = (u8)phy_addr; 610 phy->caps = caps; 611 phy->adapter = adapter; 612 phy->pinfo = pinfo; 613 phy->desc = desc; 614 phy->ops = phy_ops; 615 if (mdio_ops) { 616 phy->mdio_read = mdio_ops->read; 617 phy->mdio_write = mdio_ops->write; 618 } 619} 620 621/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 622#define MAC_STATS_ACCUM_SECS 180 623 624/* The external MAC needs accumulation every 30 seconds */ 625#define VSC_STATS_ACCUM_SECS 30 626 627#define XGM_REG(reg_addr, idx) \ 628 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 629 630struct addr_val_pair { 631 unsigned int reg_addr; 632 unsigned int val; 633}; 634 635#include <cxgb_adapter.h> 636 637#ifndef PCI_VENDOR_ID_CHELSIO 638# define PCI_VENDOR_ID_CHELSIO 0x1425 639#endif 640 641#define for_each_port(adapter, iter) \ 642 for (iter = 0; iter < (adapter)->params.nports; ++iter) 643 644#define adapter_info(adap) ((adap)->params.info) 645 646static inline int uses_xaui(const adapter_t *adap) 647{ 648 return adapter_info(adap)->caps & SUPPORTED_AUI; 649} 650 651static inline int is_10G(const adapter_t *adap) 652{ 653 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 654} 655 656static inline int is_offload(const adapter_t *adap) 657{ 658 return adap->params.offload; 659} 660 661static inline unsigned int core_ticks_per_usec(const adapter_t *adap) 662{ 663 return adap->params.vpd.cclk / 1000; 664} 665 666static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, 667 unsigned int ticks) 668{ 669 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 670} 671 672static inline unsigned int is_pcie(const adapter_t *adap) 673{ 674 return adap->params.pci.variant == PCI_VARIANT_PCIE; 675} 676 677void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); 678void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, 679 unsigned int offset); 680int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, 681 int attempts, int delay, u32 *valp); 682 683static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, 684 int polarity, int attempts, int delay) 685{ 686 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 687 delay, NULL); 688} 689 690int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 691 unsigned int set); 692int t3_phy_reset(struct cphy *phy, int mmd, int wait); 693int t3_phy_advertise(struct cphy *phy, unsigned int advert); 694int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 695int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 696int t3_phy_lasi_intr_enable(struct cphy *phy); 697int t3_phy_lasi_intr_disable(struct cphy *phy); 698int t3_phy_lasi_intr_clear(struct cphy *phy); 699int t3_phy_lasi_intr_handler(struct cphy *phy); 700 701void t3_intr_enable(adapter_t *adapter); 702void t3_intr_disable(adapter_t *adapter); 703void t3_intr_clear(adapter_t *adapter); 704void t3_xgm_intr_enable(adapter_t *adapter, int idx); 705void t3_xgm_intr_disable(adapter_t *adapter, int idx); 706void t3_port_intr_enable(adapter_t *adapter, int idx); 707void t3_port_intr_disable(adapter_t *adapter, int idx); 708void t3_port_intr_clear(adapter_t *adapter, int idx); 709int t3_slow_intr_handler(adapter_t *adapter); 710 711void t3_link_changed(adapter_t *adapter, int port_id); 712int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 713const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 714int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 715int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); 716int t3_seeprom_wp(adapter_t *adapter, int enable); 717int t3_get_vpd_len(adapter_t *adapter, struct generic_vpd *vpd); 718int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd); 719int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, 720 u32 *data, int byte_oriented); 721int t3_get_tp_version(adapter_t *adapter, u32 *vers); 722int t3_check_tpsram_version(adapter_t *adapter); 723int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); 724int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); 725int t3_get_fw_version(adapter_t *adapter, u32 *vers); 726int t3_check_fw_version(adapter_t *adapter); 727int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size); 728int t3_init_hw(adapter_t *adapter, u32 fw_params); 729void mac_prep(struct cmac *mac, adapter_t *adapter, int index); 730void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); 731int t3_reset_adapter(adapter_t *adapter); 732int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); 733int t3_reinit_adapter(adapter_t *adap); 734void t3_led_ready(adapter_t *adapter); 735void t3_fatal_err(adapter_t *adapter); 736void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); 737void t3_enable_filters(adapter_t *adap); 738void t3_disable_filters(adapter_t *adap); 739void t3_tp_set_offload_mode(adapter_t *adap, int enable); 740void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, 741 const u16 *rspq); 742int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); 743int t3_set_proto_sram(adapter_t *adap, const u8 *data); 744int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); 745void t3_port_failover(adapter_t *adapter, int port); 746void t3_failover_done(adapter_t *adapter, int port); 747void t3_failover_clear(adapter_t *adapter); 748int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, 749 unsigned int *valp); 750int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 751 u64 *buf); 752 753int t3_mac_init(struct cmac *mac); 754void t3b_pcs_reset(struct cmac *mac); 755void t3c_pcs_force_los(struct cmac *mac); 756void t3_mac_disable_exact_filters(struct cmac *mac); 757void t3_mac_enable_exact_filters(struct cmac *mac); 758int t3_mac_enable(struct cmac *mac, int which); 759int t3_mac_disable(struct cmac *mac, int which); 760int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 761int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 762int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 763int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); 764const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 765int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 766 int fc); 767int t3b2_mac_watchdog_task(struct cmac *mac); 768 769void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); 770int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 771 unsigned int nroutes); 772void t3_mc5_intr_handler(struct mc5 *mc5); 773int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 774 u32 *buf); 775 776int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); 777void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); 778void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); 779void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], 780 unsigned short alpha[NCCTRL_WIN], 781 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 782void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); 783void t3_get_cong_cntl_tab(adapter_t *adap, 784 unsigned short incr[NMTUS][NCCTRL_WIN]); 785void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, 786 int filter_index, int invert, int enable); 787void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, 788 int filter_index, int *inverted, int *enabled); 789int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); 790int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); 791void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, 792 unsigned int *ipg); 793void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); 794void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, 795 unsigned int start, unsigned int n); 796 797int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, 798 u32 *size, void *data); 799int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data); 800 801void t3_sge_prep(adapter_t *adap, struct sge_params *p); 802void t3_sge_init(adapter_t *adap, struct sge_params *p); 803int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, 804 enum sge_context_type type, int respq, u64 base_addr, 805 unsigned int size, unsigned int token, int gen, 806 unsigned int cidx); 807int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, 808 u64 base_addr, unsigned int size, unsigned int esize, 809 unsigned int cong_thres, int gen, unsigned int cidx); 810int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, 811 u64 base_addr, unsigned int size, 812 unsigned int fl_thres, int gen, unsigned int cidx); 813int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, 814 unsigned int size, int rspq, int ovfl_mode, 815 unsigned int credits, unsigned int credit_thres); 816int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); 817int t3_sge_disable_fl(adapter_t *adapter, unsigned int id); 818int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); 819int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); 820int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); 821int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); 822int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); 823int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); 824int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, 825 unsigned int credits); 826 827int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); 828int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); 829int t3_vsc7323_init(adapter_t *adap, int nports); 830int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); 831int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); 832int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); 833int t3_vsc7323_enable(adapter_t *adap, int port, int which); 834int t3_vsc7323_disable(adapter_t *adap, int port, int which); 835const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); 836 837int t3_i2c_read8(adapter_t *adapter, int chained, u8 *valp); 838int t3_i2c_write8(adapter_t *adapter, int chained, u8 val); 839 840int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 841 unsigned int *valp); 842int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 843 unsigned int val); 844 845int t3_mv88e1xxx_phy_prep(pinfo_t *pinfo, int phy_addr, 846 const struct mdio_ops *mdio_ops); 847int t3_vsc8211_phy_prep(pinfo_t *pinfo, int phy_addr, 848 const struct mdio_ops *mdio_ops); 849int t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port); 850int t3_ael1002_phy_prep(pinfo_t *pinfo, int phy_addr, 851 const struct mdio_ops *mdio_ops); 852int t3_ael1006_phy_prep(pinfo_t *pinfo, int phy_addr, 853 const struct mdio_ops *mdio_ops); 854int t3_ael2005_phy_prep(pinfo_t *pinfo, int phy_addr, 855 const struct mdio_ops *mdio_ops); 856int t3_ael2020_phy_prep(pinfo_t *pinfo, int phy_addr, 857 const struct mdio_ops *mdio_ops); 858int t3_qt2045_phy_prep(pinfo_t *pinfo, int phy_addr, 859 const struct mdio_ops *mdio_ops); 860int t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr, 861 const struct mdio_ops *mdio_ops); 862int t3_xaui_direct_phy_prep(pinfo_t *pinfo, int phy_addr, 863 const struct mdio_ops *mdio_ops); 864int t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr, 865 const struct mdio_ops *mdio_ops); 866#endif /* __CHELSIO_COMMON_H */ 867