ecore_hsi.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/11/sys/dev/bxe/ecore_hsi.h 330897 2018-03-14 03:19:51Z eadler $"); 31 32#ifndef ECORE_HSI_H 33#define ECORE_HSI_H 34 35#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 36 37struct license_key { 38 uint32_t reserved[6]; 39 40 uint32_t max_iscsi_conn; 41#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 42#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0 43#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 44#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16 45 46 uint32_t reserved_a; 47 48 uint32_t max_fcoe_conn; 49#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 50#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0 51#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 52#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16 53 54 uint32_t reserved_b[4]; 55}; 56 57typedef struct license_key license_key_t; 58 59 60/**************************************************************************** 61 * Shared HW configuration * 62 ****************************************************************************/ 63#define PIN_CFG_NA 0x00000000 64#define PIN_CFG_GPIO0_P0 0x00000001 65#define PIN_CFG_GPIO1_P0 0x00000002 66#define PIN_CFG_GPIO2_P0 0x00000003 67#define PIN_CFG_GPIO3_P0 0x00000004 68#define PIN_CFG_GPIO0_P1 0x00000005 69#define PIN_CFG_GPIO1_P1 0x00000006 70#define PIN_CFG_GPIO2_P1 0x00000007 71#define PIN_CFG_GPIO3_P1 0x00000008 72#define PIN_CFG_EPIO0 0x00000009 73#define PIN_CFG_EPIO1 0x0000000a 74#define PIN_CFG_EPIO2 0x0000000b 75#define PIN_CFG_EPIO3 0x0000000c 76#define PIN_CFG_EPIO4 0x0000000d 77#define PIN_CFG_EPIO5 0x0000000e 78#define PIN_CFG_EPIO6 0x0000000f 79#define PIN_CFG_EPIO7 0x00000010 80#define PIN_CFG_EPIO8 0x00000011 81#define PIN_CFG_EPIO9 0x00000012 82#define PIN_CFG_EPIO10 0x00000013 83#define PIN_CFG_EPIO11 0x00000014 84#define PIN_CFG_EPIO12 0x00000015 85#define PIN_CFG_EPIO13 0x00000016 86#define PIN_CFG_EPIO14 0x00000017 87#define PIN_CFG_EPIO15 0x00000018 88#define PIN_CFG_EPIO16 0x00000019 89#define PIN_CFG_EPIO17 0x0000001a 90#define PIN_CFG_EPIO18 0x0000001b 91#define PIN_CFG_EPIO19 0x0000001c 92#define PIN_CFG_EPIO20 0x0000001d 93#define PIN_CFG_EPIO21 0x0000001e 94#define PIN_CFG_EPIO22 0x0000001f 95#define PIN_CFG_EPIO23 0x00000020 96#define PIN_CFG_EPIO24 0x00000021 97#define PIN_CFG_EPIO25 0x00000022 98#define PIN_CFG_EPIO26 0x00000023 99#define PIN_CFG_EPIO27 0x00000024 100#define PIN_CFG_EPIO28 0x00000025 101#define PIN_CFG_EPIO29 0x00000026 102#define PIN_CFG_EPIO30 0x00000027 103#define PIN_CFG_EPIO31 0x00000028 104 105/* EPIO definition */ 106#define EPIO_CFG_NA 0x00000000 107#define EPIO_CFG_EPIO0 0x00000001 108#define EPIO_CFG_EPIO1 0x00000002 109#define EPIO_CFG_EPIO2 0x00000003 110#define EPIO_CFG_EPIO3 0x00000004 111#define EPIO_CFG_EPIO4 0x00000005 112#define EPIO_CFG_EPIO5 0x00000006 113#define EPIO_CFG_EPIO6 0x00000007 114#define EPIO_CFG_EPIO7 0x00000008 115#define EPIO_CFG_EPIO8 0x00000009 116#define EPIO_CFG_EPIO9 0x0000000a 117#define EPIO_CFG_EPIO10 0x0000000b 118#define EPIO_CFG_EPIO11 0x0000000c 119#define EPIO_CFG_EPIO12 0x0000000d 120#define EPIO_CFG_EPIO13 0x0000000e 121#define EPIO_CFG_EPIO14 0x0000000f 122#define EPIO_CFG_EPIO15 0x00000010 123#define EPIO_CFG_EPIO16 0x00000011 124#define EPIO_CFG_EPIO17 0x00000012 125#define EPIO_CFG_EPIO18 0x00000013 126#define EPIO_CFG_EPIO19 0x00000014 127#define EPIO_CFG_EPIO20 0x00000015 128#define EPIO_CFG_EPIO21 0x00000016 129#define EPIO_CFG_EPIO22 0x00000017 130#define EPIO_CFG_EPIO23 0x00000018 131#define EPIO_CFG_EPIO24 0x00000019 132#define EPIO_CFG_EPIO25 0x0000001a 133#define EPIO_CFG_EPIO26 0x0000001b 134#define EPIO_CFG_EPIO27 0x0000001c 135#define EPIO_CFG_EPIO28 0x0000001d 136#define EPIO_CFG_EPIO29 0x0000001e 137#define EPIO_CFG_EPIO30 0x0000001f 138#define EPIO_CFG_EPIO31 0x00000020 139 140struct mac_addr { 141 uint32_t upper; 142 uint32_t lower; 143}; 144 145 146struct shared_hw_cfg { /* NVRAM Offset */ 147 /* Up to 16 bytes of NULL-terminated string */ 148 uint8_t part_num[16]; /* 0x104 */ 149 150 uint32_t config; /* 0x114 */ 151 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 152 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 153 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 154 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 155 156 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 157 158 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 159 160 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 161 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 162 163 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 164 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 165 /* Whatever MFW found in NVM 166 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 167 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 168 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 169 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 170 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 171 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 172 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 173 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 174 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 175 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 176 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 177 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 178 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 179 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 180 181 /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For 182 backwards compatibility, value of 0 is disabling this feature. 183 That means that though 0 is a valid value, it cannot be 184 configured. */ 185 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 186 #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 187 188 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 189 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 190 #define SHARED_HW_CFG_LED_MAC1 0x00000000 191 #define SHARED_HW_CFG_LED_PHY1 0x00010000 192 #define SHARED_HW_CFG_LED_PHY2 0x00020000 193 #define SHARED_HW_CFG_LED_PHY3 0x00030000 194 #define SHARED_HW_CFG_LED_MAC2 0x00040000 195 #define SHARED_HW_CFG_LED_PHY4 0x00050000 196 #define SHARED_HW_CFG_LED_PHY5 0x00060000 197 #define SHARED_HW_CFG_LED_PHY6 0x00070000 198 #define SHARED_HW_CFG_LED_MAC3 0x00080000 199 #define SHARED_HW_CFG_LED_PHY7 0x00090000 200 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 201 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 202 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 203 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 204 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 205 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 206 207 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 208 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 209 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 210 211 #define SHARED_HW_CFG_ATC_MASK 0x80000000 212 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 213 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 214 215 uint32_t config2; /* 0x118 */ 216 217 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 218 #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 219 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 220 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 221 222 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 223 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 224 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 225 226 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 227 228 229 /* Output low when PERST is asserted */ 230 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 231 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 232 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 233 234 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 235 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 236 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 237 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 238 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 239 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 240 241 /* The fan failure mechanism is usually related to the PHY type 242 since the power consumption of the board is determined by the PHY. 243 Currently, fan is required for most designs with SFX7101, BCM8727 244 and BCM8481. If a fan is not required for a board which uses one 245 of those PHYs, this field should be set to "Disabled". If a fan is 246 required for a different PHY type, this option should be set to 247 "Enabled". The fan failure indication is expected on SPIO5 */ 248 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 249 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 250 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 251 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 252 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 253 254 /* ASPM Power Management support */ 255 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 256 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 257 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 258 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 259 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 260 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 261 262 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 263 tl_control_0 (register 0x2800) */ 264 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 265 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 266 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 267 268 269 /* Set the MDC/MDIO access for the first external phy */ 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 277 278 /* Set the MDC/MDIO access for the second external phy */ 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 282 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 283 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 284 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 285 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 286 287 /* Max number of PF MSIX vectors */ 288 uint32_t config_3; /* 0x11C */ 289 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F 290 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 291 292 /* This field extends the mf mode chosen in nvm cfg #73 (as we ran 293 out of bits) */ 294 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00 295 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8 296 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000 297 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100 298 299 uint32_t ump_nc_si_config; /* 0x120 */ 300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 302 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 303 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 304 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 305 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 306 307 /* Reserved bits: 226-230 */ 308 309 /* The output pin template BSC_SEL which selects the I2C for this 310 port in the I2C Mux */ 311 uint32_t board; /* 0x124 */ 312 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 313 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 314 315 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 316 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 317 /* Use the PIN_CFG_XXX defines on top */ 318 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 319 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 320 321 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 322 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 323 324 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 325 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 326 327 uint32_t wc_lane_config; /* 0x128 */ 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 333 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 334 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 335 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 336 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 337 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 338 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 339 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 340 341 /* TX lane Polarity swap */ 342 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 343 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 344 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 345 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 346 /* TX lane Polarity swap */ 347 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 348 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 349 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 350 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 351 352 /* Selects the port layout of the board */ 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 358 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 359 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 360 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 361 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000 362}; 363 364 365/**************************************************************************** 366 * Port HW configuration * 367 ****************************************************************************/ 368struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 369 370 uint32_t pci_id; 371 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF 372 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 373 374 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 375 #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 376 377 uint32_t pci_sub_id; 378 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF 379 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 380 381 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 382 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 383 384 uint32_t power_dissipated; 385 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF 386 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 387 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 388 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 389 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 390 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 391 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 392 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 393 394 uint32_t power_consumed; 395 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF 396 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 397 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 398 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 399 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 400 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 401 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 402 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 403 404 uint32_t mac_upper; 405 uint32_t mac_lower; /* 0x140 */ 406 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF 407 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 408 409 410 uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 411 uint32_t iscsi_mac_lower; 412 413 uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */ 414 uint32_t rdma_mac_lower; 415 416 uint32_t serdes_config; 417 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF 418 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 419 420 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 421 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 422 423 424 /* Default values: 2P-64, 4P-32 */ 425 uint32_t reserved; 426 427 uint32_t vf_config; /* 0x15C */ 428 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 430 431 uint32_t mf_pci_id; /* 0x160 */ 432 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 434 435 /* Controls the TX laser of the SFP+ module */ 436 uint32_t sfp_ctrl; /* 0x164 */ 437 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 438 #define PORT_HW_CFG_TX_LASER_SHIFT 0 439 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 440 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 441 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 442 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 443 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 444 445 /* Controls the fault module LED of the SFP+ */ 446 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 447 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 452 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 453 454 /* The output pin TX_DIS that controls the TX laser of the SFP+ 455 module. Use the PIN_CFG_XXX defines on top */ 456 uint32_t e3_sfp_ctrl; /* 0x168 */ 457 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 458 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 459 460 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 461 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 463 464 /* The input pin MOD_ABS that indicates whether SFP+ module is 465 present or not. Use the PIN_CFG_XXX defines on top */ 466 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 467 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 468 469 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 470 module. Use the PIN_CFG_XXX defines on top */ 471 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 472 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 473 474 /* 475 * The input pin which signals module transmit fault. Use the 476 * PIN_CFG_XXX defines on top 477 */ 478 uint32_t e3_cmn_pin_cfg; /* 0x16C */ 479 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 480 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 481 482 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 483 top */ 484 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 485 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 486 487 /* 488 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 489 * defines on top 490 */ 491 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 492 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 493 494 /* The output pin values BSC_SEL which selects the I2C for this port 495 in the I2C Mux */ 496 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 497 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 498 499 500 /* 501 * The input pin I_FAULT which indicate over-current has occurred. 502 * Use the PIN_CFG_XXX defines on top 503 */ 504 uint32_t e3_cmn_pin_cfg1; /* 0x170 */ 505 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 506 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 507 508 /* pause on host ring */ 509 uint32_t generic_features; /* 0x174 */ 510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 511 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 512 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 513 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 514 515 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 516 * LOM recommended and tested value is 0xBEB2. Using a different 517 * value means using a value not tested by BRCM 518 */ 519 uint32_t sfi_tap_values; /* 0x178 */ 520 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 521 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 522 523 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 524 * value is 0x2. LOM recommended and tested value is 0x2. Using a 525 * different value means using a value not tested by BRCM 526 */ 527 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 528 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 529 /* Set non-default values for TXFIR in SFP mode. */ 530 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000 531 #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20 532 533 /* Set non-default values for IPREDRIVER in SFP mode. */ 534 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000 535 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24 536 537 /* Set non-default values for POST2 in SFP mode. */ 538 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000 539 #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28 540 541 uint32_t reserved0[5]; /* 0x17c */ 542 543 uint32_t aeu_int_mask; /* 0x190 */ 544 545 uint32_t media_type; /* 0x194 */ 546 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 547 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 548 549 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 550 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 551 552 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 553 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 554 555 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 556 (not direct mode), those values will not take effect on the 4 XGXS 557 lanes. For some external PHYs (such as 8706 and 8726) the values 558 will be used to configure the external PHY in those cases, not 559 all 4 values are needed. */ 560 uint16_t xgxs_config_rx[4]; /* 0x198 */ 561 uint16_t xgxs_config_tx[4]; /* 0x1A0 */ 562 563 564 /* For storing FCOE mac on shared memory */ 565 uint32_t fcoe_fip_mac_upper; 566 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 567 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 568 uint32_t fcoe_fip_mac_lower; 569 570 uint32_t fcoe_wwn_port_name_upper; 571 uint32_t fcoe_wwn_port_name_lower; 572 573 uint32_t fcoe_wwn_node_name_upper; 574 uint32_t fcoe_wwn_node_name_lower; 575 576 /* wwpn for npiv enabled */ 577 uint32_t wwpn_for_npiv_config; /* 0x1C0 */ 578 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 579 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 580 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 581 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 582 583 /* wwpn for npiv valid addresses */ 584 uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */ 585 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF 586 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 587 588 struct mac_addr wwpn_for_niv_macs[16]; 589 590 /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */ 591 uint32_t Reserved1[14]; 592 593 uint32_t pf_allocation; /* 0x280 */ 594 /* number of vfs per PF, if 0 - sriov disabled */ 595 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF 596 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 597 598 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 599 84833 only */ 600 uint32_t xgbt_phy_cfg; /* 0x284 */ 601 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 602 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 603 604 uint32_t default_cfg; /* 0x288 */ 605 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 606 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 607 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 608 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 609 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 610 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 611 612 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 613 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 614 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 615 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 616 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 617 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 618 619 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 620 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 621 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 622 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 623 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 624 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 625 626 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 627 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 628 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 629 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 630 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 631 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 632 633 /* When KR link is required to be set to force which is not 634 KR-compliant, this parameter determine what is the trigger for it. 635 When GPIO is selected, low input will force the speed. Currently 636 default speed is 1G. In the future, it may be widen to select the 637 forced speed in with another parameter. Note when force-1G is 638 enabled, it override option 56: Link Speed option. */ 639 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 640 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 641 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 642 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 643 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 644 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 645 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 646 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 647 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 648 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 649 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 650 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 651 /* Enable to determine with which GPIO to reset the external phy */ 652 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 653 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 654 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 655 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 656 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 657 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 658 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 659 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 660 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 661 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 662 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 663 664 /* Enable BAM on KR */ 665 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 666 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 667 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 668 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 669 670 /* Enable Common Mode Sense */ 671 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 672 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 673 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 674 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 675 676 /* Determine the Serdes electrical interface */ 677 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 678 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 679 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 680 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 681 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 682 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 683 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 684 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 685 686 /* SFP+ main TAP and post TAP volumes */ 687 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 688 #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28 689 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 690 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 691 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 692 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 693 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 694 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 695 696 uint32_t speed_capability_mask2; /* 0x28C */ 697 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 698 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 699 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 700 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 701 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 702 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 703 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 704 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 705 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 706 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 707 708 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 709 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 710 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 711 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 712 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 713 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 714 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 715 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 716 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 717 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 718 719 720 /* In the case where two media types (e.g. copper and fiber) are 721 present and electrically active at the same time, PHY Selection 722 will determine which of the two PHYs will be designated as the 723 Active PHY and used for a connection to the network. */ 724 uint32_t multi_phy_config; /* 0x290 */ 725 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 726 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 727 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 728 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 729 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 730 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 731 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 732 733 /* When enabled, all second phy nvram parameters will be swapped 734 with the first phy parameters */ 735 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 736 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 737 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 738 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 739 740 741 /* Address of the second external phy */ 742 uint32_t external_phy_config2; /* 0x294 */ 743 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 744 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 745 746 /* The second XGXS external PHY type */ 747 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 748 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 749 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 750 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 751 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 752 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 753 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 754 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 755 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 756 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 757 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 758 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 759 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 760 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 761 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 762 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 763 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 764 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 765 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 766 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 767 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200 768 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 769 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 770 771 772 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 773 8706, 8726 and 8727) not all 4 values are needed. */ 774 uint16_t xgxs_config2_rx[4]; /* 0x296 */ 775 uint16_t xgxs_config2_tx[4]; /* 0x2A0 */ 776 777 uint32_t lane_config; 778 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 779 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 780 /* AN and forced */ 781 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 782 /* forced only */ 783 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 784 /* forced only */ 785 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 786 /* forced only */ 787 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 788 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 789 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 790 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 791 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 792 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 793 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 794 795 /* Indicate whether to swap the external phy polarity */ 796 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 797 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 798 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 799 800 801 uint32_t external_phy_config; 802 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF 803 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 804 805 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 806 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 807 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 808 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 809 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 810 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 811 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 812 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 813 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 814 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 815 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 816 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 817 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 818 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 819 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 820 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 821 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 822 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 823 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 824 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 825 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200 826 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 827 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 828 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 829 830 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 831 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 832 833 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 834 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 835 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 836 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 837 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 838 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 839 840 uint32_t speed_capability_mask; 841 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF 842 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 843 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 844 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 845 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 846 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 847 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 848 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 849 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 850 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 851 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 852 853 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 854 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 855 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 856 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 857 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 858 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 859 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 860 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 861 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 862 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 863 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 864 865 /* A place to hold the original MAC address as a backup */ 866 uint32_t backup_mac_upper; /* 0x2B4 */ 867 uint32_t backup_mac_lower; /* 0x2B8 */ 868 869}; 870 871 872/**************************************************************************** 873 * Shared Feature configuration * 874 ****************************************************************************/ 875struct shared_feat_cfg { /* NVRAM Offset */ 876 877 uint32_t config; /* 0x450 */ 878 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 879 880 /* Use NVRAM values instead of HW default values */ 881 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 882 0x00000002 883 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 884 0x00000000 885 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 886 0x00000002 887 888 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 889 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 890 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 891 892 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 893 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 894 895 /* Override the OTP back to single function mode. When using GPIO, 896 high means only SF, 0 is according to CLP configuration */ 897 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 898 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 899 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 900 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 901 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 902 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 903 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 904 #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500 905 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600 906 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700 907 908 /* Act as if the FCoE license is invalid */ 909 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 910 911 /* Force FLR capability to all ports */ 912 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 913 914 /* Act as if the iSCSI license is invalid */ 915 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 916 #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 917 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 918 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 919 920 /* The interval in seconds between sending LLDP packets. Set to zero 921 to disable the feature */ 922 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 923 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 924 925 /* The assigned device type ID for LLDP usage */ 926 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 927 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 928 929}; 930 931 932/**************************************************************************** 933 * Port Feature configuration * 934 ****************************************************************************/ 935struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 936 937 uint32_t config; 938 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F 939 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 940 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 941 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 942 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 943 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 944 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 945 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 946 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 947 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 948 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 949 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 950 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a 951 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b 952 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c 953 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d 954 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e 955 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f 956 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 957 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 958 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 959 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 960 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 961 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 962 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 963 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 964 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 965 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 966 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 967 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 968 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 969 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 970 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 971 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 972 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 973 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 974 975 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 976 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 977 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 978 979 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 980 #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 981 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 982 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 983 984 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 985 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 986 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 987 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 988 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 989 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 990 991 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 992 #define PORT_FEATURE_EN_SIZE_SHIFT 24 993 #define PORT_FEATURE_WOL_ENABLED 0x01000000 994 #define PORT_FEATURE_MBA_ENABLED 0x02000000 995 #define PORT_FEATURE_MFW_ENABLED 0x04000000 996 997 /* Advertise expansion ROM even if MBA is disabled */ 998 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 999 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 1000 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 1001 1002 /* Check the optic vendor via i2c against a list of approved modules 1003 in a separate nvram image */ 1004 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 1005 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 1006 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 1007 0x00000000 1008 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 1009 0x20000000 1010 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 1011 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 1012 1013 uint32_t wol_config; 1014 /* Default is used when driver sets to "auto" mode */ 1015 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 1016 1017 uint32_t mba_config; 1018 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 1019 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 1020 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 1021 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 1022 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 1023 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 1024 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 1025 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 1026 1027 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 1028 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 1029 1030 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 1031 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 1032 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 1033 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 1034 1035 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 1036 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 1037 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 1038 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 1039 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 1040 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 1041 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 1042 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 1043 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 1044 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 1045 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 1046 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 1047 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 1048 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 1049 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 1050 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 1051 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 1052 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 1053 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 1054 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 1055 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 1056 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1057 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1058 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1059 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1060 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1061 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 1062 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1063 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1064 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 1065 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 1066 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 1067 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 1068 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 1069 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 1070 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 1071 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 1072 1073 uint32_t Reserved0; /* 0x460 */ 1074 1075 uint32_t mba_vlan_cfg; 1076 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF 1077 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1078 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1079 #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000 1080 #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000 1081 #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000 1082 1083 uint32_t Reserved1; 1084 uint32_t smbus_config; 1085 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1086 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1087 1088 uint32_t vf_config; 1089 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F 1090 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1091 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1092 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1093 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1094 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1095 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1096 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1097 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1098 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1099 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1100 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1101 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1102 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1103 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1104 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1105 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1106 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1107 1108 uint32_t link_config; /* Used as HW defaults for the driver */ 1109 1110 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1111 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1112 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1113 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1114 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1115 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1116 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1117 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 1118 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 1119 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 1120 1121 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 1122 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1123 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1124 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000 1125 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000 1126 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1127 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1128 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1129 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1130 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1131 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1132 1133 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1134 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1135 /* (forced) low speed switch (< 10G) */ 1136 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1137 /* (forced) high speed switch (>= 10G) */ 1138 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1139 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1140 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1141 1142 1143 /* The default for MCP link configuration, 1144 uses the same defines as link_config */ 1145 uint32_t mfw_wol_link_cfg; 1146 1147 /* The default for the driver of the second external phy, 1148 uses the same defines as link_config */ 1149 uint32_t link_config2; /* 0x47C */ 1150 1151 /* The default for MCP of the second external phy, 1152 uses the same defines as link_config */ 1153 uint32_t mfw_wol_link_cfg2; /* 0x480 */ 1154 1155 1156 /* EEE power saving mode */ 1157 uint32_t eee_power_mode; /* 0x484 */ 1158 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1159 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1160 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1161 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1162 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1163 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1164 1165 1166 uint32_t Reserved2[16]; /* 0x48C */ 1167}; 1168 1169/**************************************************************************** 1170 * Device Information * 1171 ****************************************************************************/ 1172struct shm_dev_info { /* size */ 1173 1174 uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1175 1176 struct shared_hw_cfg shared_hw_config; /* 40 */ 1177 1178 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1179 1180 struct shared_feat_cfg shared_feature_config; /* 4 */ 1181 1182 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1183 1184}; 1185 1186struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */ 1187 1188 /* Threshold in celcius to start using the fan */ 1189 uint32_t temperature_monitor1; /* 0x4000 */ 1190 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F 1191 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 1192 1193 /* Threshold in celcius to shut down the board */ 1194 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 1195 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 1196 1197 /* EPIO of fan temperature status */ 1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 1200 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 1201 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 1207 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 1208 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 1209 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 1210 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 1211 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 1212 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 1214 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 1215 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 1216 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 1217 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 1218 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 1219 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 1220 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 1221 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 1222 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 1223 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 1224 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 1225 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 1226 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 1227 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 1228 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 1229 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 1230 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 1231 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 1232 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 1233 1234 /* EPIO of shut down temperature status */ 1235 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 1236 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 1237 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 1238 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 1239 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 1240 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 1241 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 1242 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 1243 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 1244 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 1245 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 1246 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 1247 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 1248 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 1249 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 1250 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 1251 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 1252 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 1253 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 1254 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 1255 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 1256 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 1257 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 1258 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 1259 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 1260 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 1261 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 1262 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 1263 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 1264 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 1265 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 1266 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 1267 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 1268 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 1269 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 1270 1271 1272 /* EPIO of shut down temperature status */ 1273 uint32_t temperature_monitor2; /* 0x4004 */ 1274 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF 1275 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 1276 1277 /* Sensor interface - Disabled / BSC / In the future - SMBUS */ 1278 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000 1279 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16 1280 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED 0x00000000 1281 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000 1282 1283 /* On Board Sensor Address */ 1284 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000 1285 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18 1286 1287 /* MFW flavor to be used */ 1288 uint32_t mfw_cfg; /* 0x4008 */ 1289 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF 1290 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 1291 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 1292 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 1293 1294 /* Should NIC data query remain enabled upon last drv unload */ 1295 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 1296 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 1297 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 1298 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 1299 1300 /* Prevent OCBB feature */ 1301 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200 1302 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9 1303 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000 1304 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200 1305 1306 /* Enable DCi support */ 1307 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400 1308 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10 1309 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000 1310 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400 1311 1312 /* Reserved bits: 75-76 */ 1313 1314 /* Hide DCBX feature in CCM/BACS menus */ 1315 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 1316 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 1317 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 1318 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 1319 1320 uint32_t smbus_config; /* 0x400C */ 1321 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF 1322 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 1323 1324 /* Switching regulator loop gain */ 1325 uint32_t board_cfg; /* 0x4010 */ 1326 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F 1327 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 1328 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 1329 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 1330 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 1331 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a 1332 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b 1333 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c 1334 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d 1335 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e 1336 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f 1337 1338 /* whether shadow swim feature is supported */ 1339 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 1340 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 1341 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 1342 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 1343 1344 /* whether to show/hide SRIOV menu in CCM */ 1345 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 1346 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 1347 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 1348 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 1349 1350 /* Overide PCIE revision ID when enabled the, 1351 revision ID will set to B1=='0x11' */ 1352 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400 1353 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10 1354 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000 1355 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400 1356 1357 /* Bypass slicer offset tuning */ 1358 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800 1359 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11 1360 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000 1361 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800 1362 /* Control Revision ID */ 1363 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000 1364 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12 1365 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000 1366 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000 1367 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000 1368 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000 1369 /* Threshold in celcius for max continuous operation */ 1370 uint32_t temperature_report; /* 0x4014 */ 1371 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F 1372 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 1373 1374 /* Threshold in celcius for sensor caution */ 1375 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 1376 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 1377 1378 /* wwn node prefix to be used (unless value is 0) */ 1379 uint32_t wwn_prefix; /* 0x4018 */ 1380 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF 1381 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 1382 1383 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 1384 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 1385 1386 /* wwn port prefix to be used (unless value is 0) */ 1387 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 1388 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 1389 1390 /* wwn port prefix to be used (unless value is 0) */ 1391 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 1392 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 1393 1394 /* General debug nvm cfg */ 1395 uint32_t dbg_cfg_flags; /* 0x401C */ 1396 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF 1397 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 1398 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 1399 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 1400 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 1401 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 1402 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 1403 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 1404 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 1405 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 1406 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 1407 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 1408 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 1409 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 1410 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 1411 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 1412 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 1413 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 1414 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 1415 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 1416 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 1417 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 1418 1419 /* Override Rx signal detect threshold when enabled the threshold 1420 * will be set staticaly 1421 */ 1422 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000 1423 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20 1424 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000 1425 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000 1426 1427 /* Debug signet rx threshold */ 1428 uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */ 1429 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 1430 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 1431 1432 /* Enable IFFE feature */ 1433 uint32_t iffe_features; /* 0x4024 */ 1434 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 1435 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 1436 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 1437 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 1438 1439 /* Allowable port enablement (bitmask for ports 3-1) */ 1440 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E 1441 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 1442 1443 /* Allow iSCSI offload override */ 1444 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 1445 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 1446 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 1447 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 1448 1449 /* Allow FCoE offload override */ 1450 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 1451 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 1452 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 1453 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 1454 1455 /* Tie to adaptor */ 1456 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 1457 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 1458 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 1459 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 1460 1461 /* Currently enabled port(s) (bitmask for ports 3-1) */ 1462 uint32_t current_iffe_mask; /* 0x4028 */ 1463 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E 1464 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 1465 1466 /* Current iSCSI offload */ 1467 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 1468 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 1469 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 1470 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 1471 1472 /* Current FCoE offload */ 1473 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 1474 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 1475 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 1476 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 1477 1478 /* FW set this pin to "0" (assert) these signal if either of its MAC 1479 * or PHY specific threshold values is exceeded. 1480 * Values are standard GPIO/EPIO pins. 1481 */ 1482 uint32_t threshold_pin; /* 0x402C */ 1483 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF 1484 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 1485 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 1486 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 1487 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 1488 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 1489 1490 /* MAC die temperature threshold in Celsius. */ 1491 uint32_t mac_threshold_val; /* 0x4030 */ 1492 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF 1493 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 1494 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 1495 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 1496 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 1497 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 1498 1499 /* PHY die temperature threshold in Celsius. */ 1500 uint32_t phy_threshold_val; /* 0x4034 */ 1501 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF 1502 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 1503 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 1504 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 1505 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 1506 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 1507 1508 /* External pins to communicate with host. 1509 * Values are standard GPIO/EPIO pins. 1510 */ 1511 uint32_t host_pin; /* 0x4038 */ 1512 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF 1513 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 1514 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 1515 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 1516 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 1517 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 1518 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 1519 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 1520 1521 /* Manufacture kit version */ 1522 uint32_t manufacture_ver; /* 0x403C */ 1523 1524 /* Manufacture timestamp */ 1525 uint32_t manufacture_data; /* 0x4040 */ 1526 1527 /* Number of ISCSI/FCOE cfg images */ 1528 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000 1529 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18 1530 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000 1531 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000 1532 1533 /* MCP crash dump trigger */ 1534 uint32_t mcp_crash_dump; /* 0x4044 */ 1535 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF 1536 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0 1537 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000 1538 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001 1539 1540 /* MBI version */ 1541 uint32_t mbi_version; /* 0x4048 */ 1542 1543 /* MBI date */ 1544 uint32_t mbi_date; /* 0x404C */ 1545}; 1546 1547 1548#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1549 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1550#endif 1551 1552#define FUNC_0 0 1553#define FUNC_1 1 1554#define FUNC_2 2 1555#define FUNC_3 3 1556#define FUNC_4 4 1557#define FUNC_5 5 1558#define FUNC_6 6 1559#define FUNC_7 7 1560#define E1_FUNC_MAX 2 1561#define E1H_FUNC_MAX 8 1562#define E2_FUNC_MAX 4 /* per path */ 1563 1564#define VN_0 0 1565#define VN_1 1 1566#define VN_2 2 1567#define VN_3 3 1568#define E1VN_MAX 1 1569#define E1HVN_MAX 4 1570 1571#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1572/* This value (in milliseconds) determines the frequency of the driver 1573 * issuing the PULSE message code. The firmware monitors this periodic 1574 * pulse to determine when to switch to an OS-absent mode. */ 1575#define DRV_PULSE_PERIOD_MS 250 1576 1577/* This value (in milliseconds) determines how long the driver should 1578 * wait for an acknowledgement from the firmware before timing out. Once 1579 * the firmware has timed out, the driver will assume there is no firmware 1580 * running and there won't be any firmware-driver synchronization during a 1581 * driver reset. */ 1582#define FW_ACK_TIME_OUT_MS 5000 1583 1584#define FW_ACK_POLL_TIME_MS 1 1585 1586#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1587 1588#define MFW_TRACE_SIGNATURE 0x54524342 1589 1590/**************************************************************************** 1591 * Driver <-> FW Mailbox * 1592 ****************************************************************************/ 1593struct drv_port_mb { 1594 1595 uint32_t link_status; 1596 /* Driver should update this field on any link change event */ 1597 1598 #define LINK_STATUS_NONE (0<<0) 1599 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1600 #define LINK_STATUS_LINK_UP 0x00000001 1601 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1602 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1603 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1604 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1605 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1606 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1607 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1608 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1609 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1610 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1611 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1612 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1613 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1614 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1615 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1616 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1617 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1618 1619 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1620 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1621 1622 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1623 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1624 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1625 1626 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1627 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1628 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1629 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1630 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1631 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1632 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1633 1634 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1635 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1636 1637 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1638 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1639 1640 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1641 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1642 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1643 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1644 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1645 1646 #define LINK_STATUS_SERDES_LINK 0x00100000 1647 1648 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1649 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1650 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1651 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1652 1653 #define LINK_STATUS_PFC_ENABLED 0x20000000 1654 1655 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1656 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1657 1658 uint32_t port_stx; 1659 1660 uint32_t stat_nig_timer; 1661 1662 /* MCP firmware does not use this field */ 1663 uint32_t ext_phy_fw_version; 1664 1665}; 1666 1667 1668struct drv_func_mb { 1669 1670 uint32_t drv_mb_header; 1671 #define DRV_MSG_CODE_MASK 0xffff0000 1672 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1673 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1674 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1675 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1676 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1677 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1678 #define DRV_MSG_CODE_DCC_OK 0x30000000 1679 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1680 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1681 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1682 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1683 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1684 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1685 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1686 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1687 #define DRV_MSG_CODE_OEM_OK 0x00010000 1688 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000 1689 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000 1690 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000 1691 1692 /* 1693 * The optic module verification command requires bootcode 1694 * v5.0.6 or later, te specific optic module verification command 1695 * requires bootcode v5.2.12 or later 1696 */ 1697 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1698 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1699 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1700 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1701 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1702 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1703 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1704 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1705 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1706 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1707 1708 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1709 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1710 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1711 1712 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1713 1714 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1715 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1716 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1717 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1718 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1719 1720 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1721 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1722 1723 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1724 1725 #define DRV_MSG_CODE_RMMOD 0xdb000000 1726 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1727 1728 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1729 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1730 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1731 1732 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1733 1734 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1735 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1736 1737 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1738 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1739 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1740 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1741 1742 #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000 1743 #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000 1744 1745 #define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000 1746 1747 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1748 1749 #define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000 1750 1751 uint32_t drv_mb_param; 1752 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1753 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1754 1755 #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001 1756 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1757 1758 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1759 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1760 1761 #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001 1762 #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002 1763 #define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003 1764 1765 #define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001 1766 #define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002 1767 #define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003 1768 #define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004 1769 #define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005 1770 1771 uint32_t fw_mb_header; 1772 #define FW_MSG_CODE_MASK 0xffff0000 1773 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1774 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1775 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1776 /* Load common chip is supported from bc 6.0.0 */ 1777 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1778 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1779 1780 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1781 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1782 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1783 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1784 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1785 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1786 #define FW_MSG_CODE_DCC_DONE 0x30100000 1787 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1788 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1789 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1790 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1791 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1792 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1793 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1794 #define FW_MSG_CODE_NO_KEY 0x80f00000 1795 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1796 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1797 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1798 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1799 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1800 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1801 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1802 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1803 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1804 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1805 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1806 1807 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1808 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1809 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1810 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1811 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1812 1813 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1814 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1815 1816 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1817 1818 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1819 1820 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1821 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1822 1823 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1824 1825 #define FW_MSG_CODE_FLR_ACK 0x02000000 1826 #define FW_MSG_CODE_FLR_NACK 0x02100000 1827 1828 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1829 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1830 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1831 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1832 1833 #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000 1834 #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000 1835 1836 #define FW_MSG_CODE_OEM_ACK 0x00010000 1837 #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000 1838 1839 #define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000 1840 1841 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1842 1843 uint32_t fw_mb_param; 1844 1845 #define FW_PARAM_INVALID_IMG 0xffffffff 1846 1847 uint32_t drv_pulse_mb; 1848 #define DRV_PULSE_SEQ_MASK 0x00007fff 1849 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1850 /* 1851 * The system time is in the format of 1852 * (year-2001)*12*32 + month*32 + day. 1853 */ 1854 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1855 /* 1856 * Indicate to the firmware not to go into the 1857 * OS-absent when it is not getting driver pulse. 1858 * This is used for debugging as well for PXE(MBA). 1859 */ 1860 1861 uint32_t mcp_pulse_mb; 1862 #define MCP_PULSE_SEQ_MASK 0x00007fff 1863 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1864 /* Indicates to the driver not to assert due to lack 1865 * of MCP response */ 1866 #define MCP_EVENT_MASK 0xffff0000 1867 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1868 1869 uint32_t iscsi_boot_signature; 1870 uint32_t iscsi_boot_block_offset; 1871 1872 uint32_t drv_status; 1873 #define DRV_STATUS_PMF 0x00000001 1874 #define DRV_STATUS_VF_DISABLED 0x00000002 1875 #define DRV_STATUS_SET_MF_BW 0x00000004 1876 #define DRV_STATUS_LINK_EVENT 0x00000008 1877 1878 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070 1879 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010 1880 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020 1881 #define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040 1882 1883 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080 1884 1885 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1886 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1887 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1888 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1889 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1890 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1891 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1892 1893 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1894 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1895 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1896 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1897 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1898 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1899 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1900 1901 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1902 1903 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1904 1905 uint32_t virt_mac_upper; 1906 #define VIRT_MAC_SIGN_MASK 0xffff0000 1907 #define VIRT_MAC_SIGNATURE 0x564d0000 1908 uint32_t virt_mac_lower; 1909 1910}; 1911 1912 1913/**************************************************************************** 1914 * Management firmware state * 1915 ****************************************************************************/ 1916/* Allocate 440 bytes for management firmware */ 1917#define MGMTFW_STATE_WORD_SIZE 110 1918 1919struct mgmtfw_state { 1920 uint32_t opaque[MGMTFW_STATE_WORD_SIZE]; 1921}; 1922 1923 1924/**************************************************************************** 1925 * Multi-Function configuration * 1926 ****************************************************************************/ 1927struct shared_mf_cfg { 1928 1929 uint32_t clp_mb; 1930 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1931 /* set by CLP */ 1932 #define SHARED_MF_CLP_EXIT 0x00000001 1933 /* set by MCP */ 1934 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1935 1936}; 1937 1938struct port_mf_cfg { 1939 1940 uint32_t dynamic_cfg; /* device control channel */ 1941 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1942 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1943 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1944 1945 uint32_t reserved[1]; 1946 1947}; 1948 1949struct func_mf_cfg { 1950 1951 uint32_t config; 1952 /* E/R/I/D */ 1953 /* function 0 of each port cannot be hidden */ 1954 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1955 1956 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1957 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1958 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1959 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1960 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1961 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1962 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1963 1964 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1965 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1966 1967 #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060 1968 #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000 1969 #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020 1970 #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040 1971 1972 /* PRI */ 1973 /* 0 - low priority, 3 - high priority */ 1974 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1975 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1976 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1977 1978 /* MINBW, MAXBW */ 1979 /* value range - 0..100, increments in 100Mbps */ 1980 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1981 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1982 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1983 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1984 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1985 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1986 1987 uint32_t mac_upper; /* MAC */ 1988 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1989 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1990 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1991 uint32_t mac_lower; 1992 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1993 1994 uint32_t e1hov_tag; /* VNI */ 1995 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1996 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1997 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1998 1999 /* afex default VLAN ID - 12 bits */ 2000 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 2001 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 2002 2003 uint32_t afex_config; 2004 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 2005 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 2006 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 2007 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 2008 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 2009 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 2010 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 2011 2012 uint32_t pf_allocation; 2013 /* number of vfs in function, if 0 - sriov disabled */ 2014 #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF 2015 #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0 2016}; 2017 2018enum mf_cfg_afex_vlan_mode { 2019 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 2020 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 2021 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 2022}; 2023 2024/* This structure is not applicable and should not be accessed on 57711 */ 2025struct func_ext_cfg { 2026 uint32_t func_cfg; 2027 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 2028 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 2029 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 2030 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 2031 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 2032 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 2033 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 2034 2035 uint32_t iscsi_mac_addr_upper; 2036 uint32_t iscsi_mac_addr_lower; 2037 2038 uint32_t fcoe_mac_addr_upper; 2039 uint32_t fcoe_mac_addr_lower; 2040 2041 uint32_t fcoe_wwn_port_name_upper; 2042 uint32_t fcoe_wwn_port_name_lower; 2043 2044 uint32_t fcoe_wwn_node_name_upper; 2045 uint32_t fcoe_wwn_node_name_lower; 2046 2047 uint32_t preserve_data; 2048 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 2049 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 2050 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 2051 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 2052 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 2053 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 2054}; 2055 2056struct mf_cfg { 2057 2058 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 2059 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 2060 /* 0x10*2=0x20 */ 2061 /* for all chips, there are 8 mf functions */ 2062 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 2063 /* 2064 * Extended configuration per function - this array does not exist and 2065 * should not be accessed on 57711 2066 */ 2067 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 2068}; /* 0x224 */ 2069 2070/**************************************************************************** 2071 * Shared Memory Region * 2072 ****************************************************************************/ 2073struct shmem_region { /* SharedMem Offset (size) */ 2074 2075 uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 2076 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 2077 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 2078 /* validity bits */ 2079 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 2080 #define SHR_MEM_VALIDITY_MB 0x00200000 2081 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 2082 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 2083 /* One licensing bit should be set */ 2084 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 2085 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 2086 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 2087 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 2088 /* Active MFW */ 2089 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 2090 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 2091 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 2092 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 2093 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 2094 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 2095 2096 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 2097 2098 license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 2099 2100 /* FW information (for internal FW use) */ 2101 uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */ 2102 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 2103 2104 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 2105 2106 2107#ifdef BMAPI 2108 /* This is a variable length array */ 2109 /* the number of function depends on the chip type */ 2110 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 2111#else 2112 /* the number of function depends on the chip type */ 2113 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 2114#endif /* BMAPI */ 2115 2116}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 2117 2118/**************************************************************************** 2119 * Shared Memory 2 Region * 2120 ****************************************************************************/ 2121/* The fw_flr_ack is actually built in the following way: */ 2122/* 8 bit: PF ack */ 2123/* 64 bit: VF ack */ 2124/* 8 bit: ios_dis_ack */ 2125/* In order to maintain endianity in the mailbox hsi, we want to keep using */ 2126/* uint32_t. The fw must have the VF right after the PF since this is how it */ 2127/* access arrays(it expects always the VF to reside after the PF, and that */ 2128/* makes the calculation much easier for it. ) */ 2129/* In order to answer both limitations, and keep the struct small, the code */ 2130/* will abuse the structure defined here to achieve the actual partition */ 2131/* above */ 2132/****************************************************************************/ 2133struct fw_flr_ack { 2134 uint32_t pf_ack; 2135 uint32_t vf_ack; 2136 uint32_t iov_dis_ack; 2137}; 2138 2139struct fw_flr_mb { 2140 uint32_t aggint; 2141 uint32_t opgen_addr; 2142 struct fw_flr_ack ack; 2143}; 2144 2145struct eee_remote_vals { 2146 uint32_t tx_tw; 2147 uint32_t rx_tw; 2148}; 2149 2150/**** SUPPORT FOR SHMEM ARRRAYS *** 2151 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 2152 * define arrays with storage types smaller then unsigned dwords. 2153 * The macros below add generic support for SHMEM arrays with numeric elements 2154 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 2155 * array with individual bit-filed elements accessed using shifts and masks. 2156 * 2157 */ 2158 2159/* eb is the bitwidth of a single element */ 2160#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 2161#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 2162 2163/* the bit-position macro allows the used to flip the order of the arrays 2164 * elements on a per byte or word boundary. 2165 * 2166 * example: an array with 8 entries each 4 bit wide. This array will fit into 2167 * a single dword. The diagrmas below show the array order of the nibbles. 2168 * 2169 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 2170 * 2171 * | | | | 2172 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 2173 * | | | | 2174 * 2175 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 2176 * 2177 * | | | | 2178 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 2179 * | | | | 2180 * 2181 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 2182 * 2183 * | | | | 2184 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 2185 * | | | | 2186 */ 2187#define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 2188 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 2189 (((i)%((fb)/(eb))) * (eb))) 2190 2191#define SHMEM_ARRAY_GET(a, i, eb, fb) \ 2192 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 2193 SHMEM_ARRAY_MASK(eb)) 2194 2195#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 2196do { \ 2197 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 2198 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2199 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 2200 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2201} while (0) 2202 2203 2204/****START OF DCBX STRUCTURES DECLARATIONS****/ 2205#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 2206#define DCBX_PRI_PG_BITWIDTH 4 2207#define DCBX_PRI_PG_FBITS 8 2208#define DCBX_PRI_PG_GET(a, i) \ 2209 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 2210#define DCBX_PRI_PG_SET(a, i, val) \ 2211 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 2212#define DCBX_MAX_NUM_PG_BW_ENTRIES 8 2213#define DCBX_BW_PG_BITWIDTH 8 2214#define DCBX_PG_BW_GET(a, i) \ 2215 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 2216#define DCBX_PG_BW_SET(a, i, val) \ 2217 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 2218#define DCBX_STRICT_PRI_PG 15 2219#define DCBX_MAX_APP_PROTOCOL 16 2220#define DCBX_MAX_APP_LOCAL 32 2221#define FCOE_APP_IDX 0 2222#define ISCSI_APP_IDX 1 2223#define PREDEFINED_APP_IDX_MAX 2 2224 2225 2226/* Big/Little endian have the same representation. */ 2227struct dcbx_ets_feature { 2228 /* 2229 * For Admin MIB - is this feature supported by the 2230 * driver | For Local MIB - should this feature be enabled. 2231 */ 2232 uint32_t enabled; 2233 uint32_t pg_bw_tbl[2]; 2234 uint32_t pri_pg_tbl[1]; 2235}; 2236 2237/* Driver structure in LE */ 2238struct dcbx_pfc_feature { 2239#ifdef __BIG_ENDIAN 2240 uint8_t pri_en_bitmap; 2241 #define DCBX_PFC_PRI_0 0x01 2242 #define DCBX_PFC_PRI_1 0x02 2243 #define DCBX_PFC_PRI_2 0x04 2244 #define DCBX_PFC_PRI_3 0x08 2245 #define DCBX_PFC_PRI_4 0x10 2246 #define DCBX_PFC_PRI_5 0x20 2247 #define DCBX_PFC_PRI_6 0x40 2248 #define DCBX_PFC_PRI_7 0x80 2249 uint8_t pfc_caps; 2250 uint8_t reserved; 2251 uint8_t enabled; 2252#elif defined(__LITTLE_ENDIAN) 2253 uint8_t enabled; 2254 uint8_t reserved; 2255 uint8_t pfc_caps; 2256 uint8_t pri_en_bitmap; 2257 #define DCBX_PFC_PRI_0 0x01 2258 #define DCBX_PFC_PRI_1 0x02 2259 #define DCBX_PFC_PRI_2 0x04 2260 #define DCBX_PFC_PRI_3 0x08 2261 #define DCBX_PFC_PRI_4 0x10 2262 #define DCBX_PFC_PRI_5 0x20 2263 #define DCBX_PFC_PRI_6 0x40 2264 #define DCBX_PFC_PRI_7 0x80 2265#endif 2266}; 2267 2268struct dcbx_app_priority_entry { 2269#ifdef __BIG_ENDIAN 2270 uint16_t app_id; 2271 uint8_t pri_bitmap; 2272 uint8_t appBitfield; 2273 #define DCBX_APP_ENTRY_VALID 0x01 2274 #define DCBX_APP_ENTRY_SF_MASK 0x30 2275 #define DCBX_APP_ENTRY_SF_SHIFT 4 2276 #define DCBX_APP_SF_ETH_TYPE 0x10 2277 #define DCBX_APP_SF_PORT 0x20 2278 #define DCBX_APP_PRI_0 0x01 2279 #define DCBX_APP_PRI_1 0x02 2280 #define DCBX_APP_PRI_2 0x04 2281 #define DCBX_APP_PRI_3 0x08 2282 #define DCBX_APP_PRI_4 0x10 2283 #define DCBX_APP_PRI_5 0x20 2284 #define DCBX_APP_PRI_6 0x40 2285 #define DCBX_APP_PRI_7 0x80 2286#elif defined(__LITTLE_ENDIAN) 2287 uint8_t appBitfield; 2288 #define DCBX_APP_ENTRY_VALID 0x01 2289 #define DCBX_APP_ENTRY_SF_MASK 0x30 2290 #define DCBX_APP_ENTRY_SF_SHIFT 4 2291 #define DCBX_APP_SF_ETH_TYPE 0x10 2292 #define DCBX_APP_SF_PORT 0x20 2293 uint8_t pri_bitmap; 2294 uint16_t app_id; 2295#endif 2296}; 2297 2298 2299/* FW structure in BE */ 2300struct dcbx_app_priority_feature { 2301#ifdef __BIG_ENDIAN 2302 uint8_t reserved; 2303 uint8_t default_pri; 2304 uint8_t tc_supported; 2305 uint8_t enabled; 2306#elif defined(__LITTLE_ENDIAN) 2307 uint8_t enabled; 2308 uint8_t tc_supported; 2309 uint8_t default_pri; 2310 uint8_t reserved; 2311#endif 2312 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 2313}; 2314 2315/* FW structure in BE */ 2316struct dcbx_features { 2317 /* PG feature */ 2318 struct dcbx_ets_feature ets; 2319 /* PFC feature */ 2320 struct dcbx_pfc_feature pfc; 2321 /* APP feature */ 2322 struct dcbx_app_priority_feature app; 2323}; 2324 2325/* LLDP protocol parameters */ 2326/* FW structure in BE */ 2327struct lldp_params { 2328#ifdef __BIG_ENDIAN 2329 uint8_t msg_fast_tx_interval; 2330 uint8_t msg_tx_hold; 2331 uint8_t msg_tx_interval; 2332 uint8_t admin_status; 2333 #define LLDP_TX_ONLY 0x01 2334 #define LLDP_RX_ONLY 0x02 2335 #define LLDP_TX_RX 0x03 2336 #define LLDP_DISABLED 0x04 2337 uint8_t reserved1; 2338 uint8_t tx_fast; 2339 uint8_t tx_crd_max; 2340 uint8_t tx_crd; 2341#elif defined(__LITTLE_ENDIAN) 2342 uint8_t admin_status; 2343 #define LLDP_TX_ONLY 0x01 2344 #define LLDP_RX_ONLY 0x02 2345 #define LLDP_TX_RX 0x03 2346 #define LLDP_DISABLED 0x04 2347 uint8_t msg_tx_interval; 2348 uint8_t msg_tx_hold; 2349 uint8_t msg_fast_tx_interval; 2350 uint8_t tx_crd; 2351 uint8_t tx_crd_max; 2352 uint8_t tx_fast; 2353 uint8_t reserved1; 2354#endif 2355 #define REM_CHASSIS_ID_STAT_LEN 4 2356 #define REM_PORT_ID_STAT_LEN 4 2357 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 2358 uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 2359 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 2360 uint32_t peer_port_id[REM_PORT_ID_STAT_LEN]; 2361}; 2362 2363struct lldp_dcbx_stat { 2364 #define LOCAL_CHASSIS_ID_STAT_LEN 2 2365 #define LOCAL_PORT_ID_STAT_LEN 2 2366 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 2367 uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 2368 /* Holds local Port ID 8B payload of constant subtype 3. */ 2369 uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN]; 2370 /* Number of DCBX frames transmitted. */ 2371 uint32_t num_tx_dcbx_pkts; 2372 /* Number of DCBX frames received. */ 2373 uint32_t num_rx_dcbx_pkts; 2374}; 2375 2376/* ADMIN MIB - DCBX local machine default configuration. */ 2377struct lldp_admin_mib { 2378 uint32_t ver_cfg_flags; 2379 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 2380 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 2381 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 2382 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 2383 #define DCBX_ETS_RECO_VALID 0x00000010 2384 #define DCBX_ETS_WILLING 0x00000020 2385 #define DCBX_PFC_WILLING 0x00000040 2386 #define DCBX_APP_WILLING 0x00000080 2387 #define DCBX_VERSION_CEE 0x00000100 2388 #define DCBX_VERSION_IEEE 0x00000200 2389 #define DCBX_DCBX_ENABLED 0x00000400 2390 #define DCBX_CEE_VERSION_MASK 0x0000f000 2391 #define DCBX_CEE_VERSION_SHIFT 12 2392 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 2393 #define DCBX_CEE_MAX_VERSION_SHIFT 16 2394 struct dcbx_features features; 2395}; 2396 2397/* REMOTE MIB - remote machine DCBX configuration. */ 2398struct lldp_remote_mib { 2399 uint32_t prefix_seq_num; 2400 uint32_t flags; 2401 #define DCBX_ETS_TLV_RX 0x00000001 2402 #define DCBX_PFC_TLV_RX 0x00000002 2403 #define DCBX_APP_TLV_RX 0x00000004 2404 #define DCBX_ETS_RX_ERROR 0x00000010 2405 #define DCBX_PFC_RX_ERROR 0x00000020 2406 #define DCBX_APP_RX_ERROR 0x00000040 2407 #define DCBX_ETS_REM_WILLING 0x00000100 2408 #define DCBX_PFC_REM_WILLING 0x00000200 2409 #define DCBX_APP_REM_WILLING 0x00000400 2410 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 2411 #define DCBX_REMOTE_MIB_VALID 0x00002000 2412 struct dcbx_features features; 2413 uint32_t suffix_seq_num; 2414}; 2415 2416/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 2417struct lldp_local_mib { 2418 uint32_t prefix_seq_num; 2419 /* Indicates if there is mismatch with negotiation results. */ 2420 uint32_t error; 2421 #define DCBX_LOCAL_ETS_ERROR 0x00000001 2422 #define DCBX_LOCAL_PFC_ERROR 0x00000002 2423 #define DCBX_LOCAL_APP_ERROR 0x00000004 2424 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 2425 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 2426 #define DCBX_REMOTE_MIB_ERROR 0x00000040 2427 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 2428 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 2429 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 2430 struct dcbx_features features; 2431 uint32_t suffix_seq_num; 2432}; 2433 2434struct lldp_local_mib_ext { 2435 uint32_t prefix_seq_num; 2436 /* APP TLV extension - 16 more entries for negotiation results*/ 2437 struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL]; 2438 uint32_t suffix_seq_num; 2439}; 2440/***END OF DCBX STRUCTURES DECLARATIONS***/ 2441 2442/***********************************************************/ 2443/* Elink section */ 2444/***********************************************************/ 2445#define SHMEM_LINK_CONFIG_SIZE 2 2446struct shmem_lfa { 2447 uint32_t req_duplex; 2448 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 2449 #define REQ_DUPLEX_PHY0_SHIFT 0 2450 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 2451 #define REQ_DUPLEX_PHY1_SHIFT 16 2452 uint32_t req_flow_ctrl; 2453 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 2454 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 2455 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 2456 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 2457 uint32_t req_line_speed; /* Also determine AutoNeg */ 2458 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 2459 #define REQ_LINE_SPD_PHY0_SHIFT 0 2460 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 2461 #define REQ_LINE_SPD_PHY1_SHIFT 16 2462 uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 2463 uint32_t additional_config; 2464 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 2465 #define REQ_FC_AUTO_ADV0_SHIFT 0 2466 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 2467 uint32_t lfa_sts; 2468 #define LFA_LINK_FLAP_REASON_OFFSET 0 2469 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 2470 #define LFA_LINK_DOWN 0x1 2471 #define LFA_LOOPBACK_ENABLED 0x2 2472 #define LFA_DUPLEX_MISMATCH 0x3 2473 #define LFA_MFW_IS_TOO_OLD 0x4 2474 #define LFA_LINK_SPEED_MISMATCH 0x5 2475 #define LFA_FLOW_CTRL_MISMATCH 0x6 2476 #define LFA_SPEED_CAP_MISMATCH 0x7 2477 #define LFA_DCC_LFA_DISABLED 0x8 2478 #define LFA_EEE_MISMATCH 0x9 2479 2480 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 2481 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 2482 2483 #define LINK_FLAP_COUNT_OFFSET 16 2484 #define LINK_FLAP_COUNT_MASK 0x00ff0000 2485 2486 #define LFA_FLAGS_MASK 0xff000000 2487 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2488 2489}; 2490 2491/* 2492Used to suppoert NSCI get OS driver version 2493On driver load the version value will be set 2494On driver unload driver value of 0x0 will be set 2495*/ 2496struct os_drv_ver{ 2497 #define DRV_VER_NOT_LOADED 0 2498 /*personalites orrder is importent */ 2499 #define DRV_PERS_ETHERNET 0 2500 #define DRV_PERS_ISCSI 1 2501 #define DRV_PERS_FCOE 2 2502 /*shmem2 struct is constatnt can't add more personalites here*/ 2503 #define MAX_DRV_PERS 3 2504 uint32_t versions[MAX_DRV_PERS]; 2505}; 2506 2507#define OEM_I2C_UUID_STR_ADDR 0x9f 2508#define OEM_I2C_CARD_SKU_STR_ADDR 0x3c 2509#define OEM_I2C_CARD_FN_STR_ADDR 0x48 2510#define OEM_I2C_CARD_NAME_STR_ADDR 0x10e 2511 2512#define OEM_I2C_UUID_STR_LEN 16 2513#define OEM_I2C_CARD_SKU_STR_LEN 12 2514#define OEM_I2C_CARD_FN_STR_LEN 12 2515#define OEM_I2C_CARD_NAME_STR_LEN 128 2516#define OEM_I2C_CARD_VERSION_STR_LEN 36 2517 2518struct oem_i2c_data_t { 2519 uint32_t size; 2520 uint8_t uuid[OEM_I2C_UUID_STR_LEN]; 2521 uint8_t card_sku[OEM_I2C_CARD_SKU_STR_LEN]; 2522 uint8_t card_name[OEM_I2C_CARD_NAME_STR_LEN]; 2523 uint8_t card_ver[OEM_I2C_CARD_VERSION_STR_LEN]; 2524 uint8_t card_fn[OEM_I2C_CARD_FN_STR_LEN]; 2525}; 2526 2527enum curr_cfg_method_e { 2528 CURR_CFG_MET_NONE = 0, /* default config */ 2529 CURR_CFG_MET_OS = 1, 2530 CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */ 2531 CURR_CFG_MET_HP_OTHER = 3, 2532 CURR_CFG_MET_VC_CLP = 4, /* C-Class SM-CLP */ 2533 CURR_CFG_MET_HP_CNU = 5, /* Converged Network Utility */ 2534 CURR_CFG_MET_HP_DCI = 6, /* DCi (BD) changes */ 2535}; 2536 2537#define FC_NPIV_WWPN_SIZE 8 2538#define FC_NPIV_WWNN_SIZE 8 2539struct bdn_npiv_settings { 2540 uint8_t npiv_wwpn[FC_NPIV_WWPN_SIZE]; 2541 uint8_t npiv_wwnn[FC_NPIV_WWNN_SIZE]; 2542}; 2543 2544struct bdn_fc_npiv_cfg { 2545 /* hdr used internally by the MFW */ 2546 uint32_t hdr; 2547 uint32_t num_of_npiv; 2548}; 2549 2550#define MAX_NUMBER_NPIV 64 2551struct bdn_fc_npiv_tbl { 2552 struct bdn_fc_npiv_cfg fc_npiv_cfg; 2553 struct bdn_npiv_settings settings[MAX_NUMBER_NPIV]; 2554}; 2555 2556struct mdump_driver_info { 2557 uint32_t epoc; 2558 uint32_t drv_ver; 2559 uint32_t fw_ver; 2560 2561 uint32_t valid_dump; 2562 #define FIRST_DUMP_VALID (1 << 0) 2563 #define SECOND_DUMP_VALID (1 << 1) 2564 2565 uint32_t flags; 2566 #define ENABLE_ALL_TRIGGERS (0x7fffffff) 2567 #define TRIGGER_MDUMP_ONCE (1 << 31) 2568}; 2569 2570struct shmem2_region { 2571 2572 uint32_t size; /* 0x0000 */ 2573 2574 uint32_t dcc_support; /* 0x0004 */ 2575 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2576 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2577 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2578 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2579 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2580 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2581 2582 uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2583 /* 2584 * For backwards compatibility, if the mf_cfg_addr does not exist 2585 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2586 * end of struct shmem_region 2587 */ 2588 uint32_t mf_cfg_addr; /* 0x0010 */ 2589 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2590 2591 struct fw_flr_mb flr_mb; /* 0x0014 */ 2592 uint32_t dcbx_lldp_params_offset; /* 0x0028 */ 2593 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2594 uint32_t dcbx_neg_res_offset; /* 0x002c */ 2595 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2596 uint32_t dcbx_remote_mib_offset; /* 0x0030 */ 2597 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2598 /* 2599 * The other shmemX_base_addr holds the other path's shmem address 2600 * required for example in case of common phy init, or for path1 to know 2601 * the address of mcp debug trace which is located in offset from shmem 2602 * of path0 2603 */ 2604 uint32_t other_shmem_base_addr; /* 0x0034 */ 2605 uint32_t other_shmem2_base_addr; /* 0x0038 */ 2606 /* 2607 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2608 * which were disabled/flred 2609 */ 2610 uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2611 2612 /* 2613 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2614 * VFs 2615 */ 2616 uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2617 2618 uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2619 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2620 2621 /* 2622 * edebug_driver_if field is used to transfer messages between edebug 2623 * app to the driver through shmem2. 2624 * 2625 * message format: 2626 * bits 0-2 - function number / instance of driver to perform request 2627 * bits 3-5 - op code / is_ack? 2628 * bits 6-63 - data 2629 */ 2630 uint32_t edebug_driver_if[2]; /* 0x0068 */ 2631 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2632 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2633 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2634 2635 uint32_t nvm_retain_bitmap_addr; /* 0x0070 */ 2636 2637 /* afex support of that driver */ 2638 uint32_t afex_driver_support; /* 0x0074 */ 2639 #define SHMEM_AFEX_VERSION_MASK 0x100f 2640 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2641 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2642 2643 /* driver receives addr in scratchpad to which it should respond */ 2644 uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2645 2646 /* 2647 * generic params from MCP to driver (value depends on the msg sent 2648 * to driver 2649 */ 2650 uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2651 uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2652 2653 uint32_t swim_base_addr; /* 0x00a8 */ 2654 uint32_t swim_funcs; /* 0x00ac */ 2655 uint32_t swim_main_cb; /* 0x00b0 */ 2656 2657 /* 2658 * bitmap notifying which VIF profiles stored in nvram are enabled by 2659 * switch 2660 */ 2661 uint32_t afex_profiles_enabled[2]; /* 0x00b4 */ 2662 2663 /* generic flags controlled by the driver */ 2664 uint32_t drv_flags; /* 0x00bc */ 2665 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2666 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2667 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2668 2669 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2670 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2671 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2672 /* Port offset*/ 2673 #define DRV_FLAGS_P0_OFFSET 0 2674 #define DRV_FLAGS_P1_OFFSET 16 2675 #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \ 2676 DRV_FLAGS_P0_OFFSET : \ 2677 DRV_FLAGS_P1_OFFSET) 2678 2679 #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \ 2680 DRV_FLAGS_GET_PORT_OFFSET(_port)) 2681 2682 #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \ 2683 (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port))) 2684 2685 /* pointer to extended dev_info shared data copied from nvm image */ 2686 uint32_t extended_dev_info_shared_addr; /* 0x00c0 */ 2687 uint32_t ncsi_oem_data_addr; /* 0x00c4 */ 2688 2689 uint32_t sensor_data_addr; /* 0x00c8 */ 2690 uint32_t buffer_block_addr; /* 0x00cc */ 2691 uint32_t sensor_data_req_update_interval; /* 0x00d0 */ 2692 uint32_t temperature_in_half_celsius; /* 0x00d4 */ 2693 uint32_t glob_struct_in_host; /* 0x00d8 */ 2694 2695 uint32_t dcbx_neg_res_ext_offset; /* 0x00dc */ 2696 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2697 2698 uint32_t drv_capabilities_flag[E2_FUNC_MAX]; /* 0x00e0 */ 2699 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2700 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2701 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2702 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2703 #define DRV_FLAGS_MTU_MASK 0xffff0000 2704 #define DRV_FLAGS_MTU_SHIFT 16 2705 2706 uint32_t extended_dev_info_shared_cfg_size; /* 0x00f0 */ 2707 2708 uint32_t dcbx_en[PORT_MAX]; /* 0x00f4 */ 2709 2710 /* The offset points to the multi threaded meta structure */ 2711 uint32_t multi_thread_data_offset; /* 0x00fc */ 2712 2713 /* address of DMAable host address holding values from the drivers */ 2714 uint32_t drv_info_host_addr_lo; /* 0x0100 */ 2715 uint32_t drv_info_host_addr_hi; /* 0x0104 */ 2716 2717 /* general values written by the MFW (such as current version) */ 2718 uint32_t drv_info_control; /* 0x0108 */ 2719 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2720 #define DRV_INFO_CONTROL_VER_SHIFT 0 2721 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2722 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2723 uint32_t ibft_host_addr; /* initialized by option ROM */ /* 0x010c */ 2724 2725 struct eee_remote_vals eee_remote_vals[PORT_MAX]; /* 0x0110 */ 2726 uint32_t pf_allocation[E2_FUNC_MAX]; /* 0x0120 */ 2727 #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */ 2728 #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0 2729 2730 /* the status of EEE auto-negotiation 2731 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2732 * bits 19:16 the supported modes for EEE. 2733 * bits 23:20 the speeds advertised for EEE. 2734 * bits 27:24 the speeds the Link partner advertised for EEE. 2735 * The supported/adv. modes in bits 27:19 originate from the 2736 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2737 * bit 28 when 1'b1 EEE was requested. 2738 * bit 29 when 1'b1 tx lpi was requested. 2739 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2740 * 30:29 are 2'b11. 2741 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2742 * value. When 1'b1 those bits contains a value times 16 microseconds. 2743 */ 2744 uint32_t eee_status[PORT_MAX]; /* 0x0130 */ 2745 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2746 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2747 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2748 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2749 #define SHMEM_EEE_100M_ADV (1<<0) 2750 #define SHMEM_EEE_1G_ADV (1<<1) 2751 #define SHMEM_EEE_10G_ADV (1<<2) 2752 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2753 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2754 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2755 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2756 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2757 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2758 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2759 2760 uint32_t sizeof_port_stats; /* 0x0138 */ 2761 2762 /* Link Flap Avoidance */ 2763 uint32_t lfa_host_addr[PORT_MAX]; /* 0x013c */ 2764 2765 /* External PHY temperature in deg C. */ 2766 uint32_t extphy_temps_in_celsius; /* 0x0144 */ 2767 #define EXTPHY1_TEMP_MASK 0x0000ffff 2768 #define EXTPHY1_TEMP_SHIFT 0 2769 #define ON_BOARD_TEMP_MASK 0xffff0000 2770 #define ON_BOARD_TEMP_SHIFT 16 2771 2772 uint32_t ocdata_info_addr; /* Offset 0x148 */ 2773 uint32_t drv_func_info_addr; /* Offset 0x14C */ 2774 uint32_t drv_func_info_size; /* Offset 0x150 */ 2775 uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2776 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001 2777 #define LINK_ATTR_84858 0x00000002 2778 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00 2779 #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8 2780 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000 2781 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000 2782 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000 2783 2784 uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM Offset 0x158 */ 2785 uint32_t fcode_ver; /* Offset 0x15c */ 2786 uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */ 2787 #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */ 2788 /* driver version for each personality*/ 2789 struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */ 2790 2791 /* Flag to the driver that PF's drv_info_host_addr buffer was read */ 2792 uint32_t mfw_drv_indication; /* Offset 0x19c */ 2793 2794 /* We use inidcation for each PF (0..3) */ 2795 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << _pf_) 2796 2797 union { /* For various OEMs */ /* Offset 0x1a0 */ 2798 uint8_t storage_boot_prog[E2_FUNC_MAX]; 2799 #define STORAGE_BOOT_PROG_MASK 0x000000FF 2800 #define STORAGE_BOOT_PROG_NONE 0x00000000 2801 #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002 2802 #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002 2803 #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004 2804 #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008 2805 #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008 2806 #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010 2807 #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020 2808 #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040 2809 #define STORAGE_BOOT_PROG_COMPLETED 0x00000080 2810 2811 uint32_t oem_i2c_data_addr; 2812 }u; 2813 2814 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 2815 /* For PCP values 0-3 use the map lower */ 2816 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 2817 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 2818 */ 2819 uint32_t c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */ 2820 2821 /* For PCP values 4-7 use the map upper */ 2822 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 2823 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 2824 */ 2825 uint32_t c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */ 2826 2827 /* For PCP default value get the MSB byte of the map default */ 2828 uint32_t c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */ 2829 2830 /* FC_NPIV table offset in NVRAM */ 2831 uint32_t fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */ 2832 2833 /* Shows last method that changed configuration of this device */ 2834 enum curr_cfg_method_e curr_cfg; /* 0x1dc */ 2835 2836 /* Storm FW version, shold be kept in the format 0xMMmmbbdd: 2837 * MM - Major, mm - Minor, bb - Build ,dd - Drop 2838 */ 2839 uint32_t netproc_fw_ver; /* 0x1e0 */ 2840 2841 /* Option ROM SMASH CLP version */ 2842 uint32_t clp_ver; /* 0x1e4 */ 2843 2844 uint32_t pcie_bus_num; /* 0x1e8 */ 2845 2846 uint32_t sriov_switch_mode; /* 0x1ec */ 2847 #define SRIOV_SWITCH_MODE_NONE 0x0 2848 #define SRIOV_SWITCH_MODE_VEB 0x1 2849 #define SRIOV_SWITCH_MODE_VEPA 0x2 2850 2851 uint8_t rsrv2[E2_FUNC_MAX]; /* 0x1f0 */ 2852 2853 uint32_t img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */ 2854 2855 uint32_t mtu_size[E2_FUNC_MAX]; /* 0x1f8 */ 2856 2857 uint32_t os_driver_state[E2_FUNC_MAX]; /* 0x208 */ 2858 #define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */ 2859 #define OS_DRIVER_STATE_LOADING 1 /* transition state */ 2860 #define OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */ 2861 #define OS_DRIVER_STATE_ACTIVE 3 /* installed and active */ 2862 2863 /* mini dump driver info */ 2864 struct mdump_driver_info drv_info; /* 0x218 */ 2865 2866 /* 0x22c */ 2867}; 2868 2869 2870struct emac_stats { 2871 uint32_t rx_stat_ifhcinoctets; 2872 uint32_t rx_stat_ifhcinbadoctets; 2873 uint32_t rx_stat_etherstatsfragments; 2874 uint32_t rx_stat_ifhcinucastpkts; 2875 uint32_t rx_stat_ifhcinmulticastpkts; 2876 uint32_t rx_stat_ifhcinbroadcastpkts; 2877 uint32_t rx_stat_dot3statsfcserrors; 2878 uint32_t rx_stat_dot3statsalignmenterrors; 2879 uint32_t rx_stat_dot3statscarriersenseerrors; 2880 uint32_t rx_stat_xonpauseframesreceived; 2881 uint32_t rx_stat_xoffpauseframesreceived; 2882 uint32_t rx_stat_maccontrolframesreceived; 2883 uint32_t rx_stat_xoffstateentered; 2884 uint32_t rx_stat_dot3statsframestoolong; 2885 uint32_t rx_stat_etherstatsjabbers; 2886 uint32_t rx_stat_etherstatsundersizepkts; 2887 uint32_t rx_stat_etherstatspkts64octets; 2888 uint32_t rx_stat_etherstatspkts65octetsto127octets; 2889 uint32_t rx_stat_etherstatspkts128octetsto255octets; 2890 uint32_t rx_stat_etherstatspkts256octetsto511octets; 2891 uint32_t rx_stat_etherstatspkts512octetsto1023octets; 2892 uint32_t rx_stat_etherstatspkts1024octetsto1522octets; 2893 uint32_t rx_stat_etherstatspktsover1522octets; 2894 2895 uint32_t rx_stat_falsecarriererrors; 2896 2897 uint32_t tx_stat_ifhcoutoctets; 2898 uint32_t tx_stat_ifhcoutbadoctets; 2899 uint32_t tx_stat_etherstatscollisions; 2900 uint32_t tx_stat_outxonsent; 2901 uint32_t tx_stat_outxoffsent; 2902 uint32_t tx_stat_flowcontroldone; 2903 uint32_t tx_stat_dot3statssinglecollisionframes; 2904 uint32_t tx_stat_dot3statsmultiplecollisionframes; 2905 uint32_t tx_stat_dot3statsdeferredtransmissions; 2906 uint32_t tx_stat_dot3statsexcessivecollisions; 2907 uint32_t tx_stat_dot3statslatecollisions; 2908 uint32_t tx_stat_ifhcoutucastpkts; 2909 uint32_t tx_stat_ifhcoutmulticastpkts; 2910 uint32_t tx_stat_ifhcoutbroadcastpkts; 2911 uint32_t tx_stat_etherstatspkts64octets; 2912 uint32_t tx_stat_etherstatspkts65octetsto127octets; 2913 uint32_t tx_stat_etherstatspkts128octetsto255octets; 2914 uint32_t tx_stat_etherstatspkts256octetsto511octets; 2915 uint32_t tx_stat_etherstatspkts512octetsto1023octets; 2916 uint32_t tx_stat_etherstatspkts1024octetsto1522octets; 2917 uint32_t tx_stat_etherstatspktsover1522octets; 2918 uint32_t tx_stat_dot3statsinternalmactransmiterrors; 2919}; 2920 2921 2922struct bmac1_stats { 2923 uint32_t tx_stat_gtpkt_lo; 2924 uint32_t tx_stat_gtpkt_hi; 2925 uint32_t tx_stat_gtxpf_lo; 2926 uint32_t tx_stat_gtxpf_hi; 2927 uint32_t tx_stat_gtfcs_lo; 2928 uint32_t tx_stat_gtfcs_hi; 2929 uint32_t tx_stat_gtmca_lo; 2930 uint32_t tx_stat_gtmca_hi; 2931 uint32_t tx_stat_gtbca_lo; 2932 uint32_t tx_stat_gtbca_hi; 2933 uint32_t tx_stat_gtfrg_lo; 2934 uint32_t tx_stat_gtfrg_hi; 2935 uint32_t tx_stat_gtovr_lo; 2936 uint32_t tx_stat_gtovr_hi; 2937 uint32_t tx_stat_gt64_lo; 2938 uint32_t tx_stat_gt64_hi; 2939 uint32_t tx_stat_gt127_lo; 2940 uint32_t tx_stat_gt127_hi; 2941 uint32_t tx_stat_gt255_lo; 2942 uint32_t tx_stat_gt255_hi; 2943 uint32_t tx_stat_gt511_lo; 2944 uint32_t tx_stat_gt511_hi; 2945 uint32_t tx_stat_gt1023_lo; 2946 uint32_t tx_stat_gt1023_hi; 2947 uint32_t tx_stat_gt1518_lo; 2948 uint32_t tx_stat_gt1518_hi; 2949 uint32_t tx_stat_gt2047_lo; 2950 uint32_t tx_stat_gt2047_hi; 2951 uint32_t tx_stat_gt4095_lo; 2952 uint32_t tx_stat_gt4095_hi; 2953 uint32_t tx_stat_gt9216_lo; 2954 uint32_t tx_stat_gt9216_hi; 2955 uint32_t tx_stat_gt16383_lo; 2956 uint32_t tx_stat_gt16383_hi; 2957 uint32_t tx_stat_gtmax_lo; 2958 uint32_t tx_stat_gtmax_hi; 2959 uint32_t tx_stat_gtufl_lo; 2960 uint32_t tx_stat_gtufl_hi; 2961 uint32_t tx_stat_gterr_lo; 2962 uint32_t tx_stat_gterr_hi; 2963 uint32_t tx_stat_gtbyt_lo; 2964 uint32_t tx_stat_gtbyt_hi; 2965 2966 uint32_t rx_stat_gr64_lo; 2967 uint32_t rx_stat_gr64_hi; 2968 uint32_t rx_stat_gr127_lo; 2969 uint32_t rx_stat_gr127_hi; 2970 uint32_t rx_stat_gr255_lo; 2971 uint32_t rx_stat_gr255_hi; 2972 uint32_t rx_stat_gr511_lo; 2973 uint32_t rx_stat_gr511_hi; 2974 uint32_t rx_stat_gr1023_lo; 2975 uint32_t rx_stat_gr1023_hi; 2976 uint32_t rx_stat_gr1518_lo; 2977 uint32_t rx_stat_gr1518_hi; 2978 uint32_t rx_stat_gr2047_lo; 2979 uint32_t rx_stat_gr2047_hi; 2980 uint32_t rx_stat_gr4095_lo; 2981 uint32_t rx_stat_gr4095_hi; 2982 uint32_t rx_stat_gr9216_lo; 2983 uint32_t rx_stat_gr9216_hi; 2984 uint32_t rx_stat_gr16383_lo; 2985 uint32_t rx_stat_gr16383_hi; 2986 uint32_t rx_stat_grmax_lo; 2987 uint32_t rx_stat_grmax_hi; 2988 uint32_t rx_stat_grpkt_lo; 2989 uint32_t rx_stat_grpkt_hi; 2990 uint32_t rx_stat_grfcs_lo; 2991 uint32_t rx_stat_grfcs_hi; 2992 uint32_t rx_stat_grmca_lo; 2993 uint32_t rx_stat_grmca_hi; 2994 uint32_t rx_stat_grbca_lo; 2995 uint32_t rx_stat_grbca_hi; 2996 uint32_t rx_stat_grxcf_lo; 2997 uint32_t rx_stat_grxcf_hi; 2998 uint32_t rx_stat_grxpf_lo; 2999 uint32_t rx_stat_grxpf_hi; 3000 uint32_t rx_stat_grxuo_lo; 3001 uint32_t rx_stat_grxuo_hi; 3002 uint32_t rx_stat_grjbr_lo; 3003 uint32_t rx_stat_grjbr_hi; 3004 uint32_t rx_stat_grovr_lo; 3005 uint32_t rx_stat_grovr_hi; 3006 uint32_t rx_stat_grflr_lo; 3007 uint32_t rx_stat_grflr_hi; 3008 uint32_t rx_stat_grmeg_lo; 3009 uint32_t rx_stat_grmeg_hi; 3010 uint32_t rx_stat_grmeb_lo; 3011 uint32_t rx_stat_grmeb_hi; 3012 uint32_t rx_stat_grbyt_lo; 3013 uint32_t rx_stat_grbyt_hi; 3014 uint32_t rx_stat_grund_lo; 3015 uint32_t rx_stat_grund_hi; 3016 uint32_t rx_stat_grfrg_lo; 3017 uint32_t rx_stat_grfrg_hi; 3018 uint32_t rx_stat_grerb_lo; 3019 uint32_t rx_stat_grerb_hi; 3020 uint32_t rx_stat_grfre_lo; 3021 uint32_t rx_stat_grfre_hi; 3022 uint32_t rx_stat_gripj_lo; 3023 uint32_t rx_stat_gripj_hi; 3024}; 3025 3026struct bmac2_stats { 3027 uint32_t tx_stat_gtpk_lo; /* gtpok */ 3028 uint32_t tx_stat_gtpk_hi; /* gtpok */ 3029 uint32_t tx_stat_gtxpf_lo; /* gtpf */ 3030 uint32_t tx_stat_gtxpf_hi; /* gtpf */ 3031 uint32_t tx_stat_gtpp_lo; /* NEW BMAC2 */ 3032 uint32_t tx_stat_gtpp_hi; /* NEW BMAC2 */ 3033 uint32_t tx_stat_gtfcs_lo; 3034 uint32_t tx_stat_gtfcs_hi; 3035 uint32_t tx_stat_gtuca_lo; /* NEW BMAC2 */ 3036 uint32_t tx_stat_gtuca_hi; /* NEW BMAC2 */ 3037 uint32_t tx_stat_gtmca_lo; 3038 uint32_t tx_stat_gtmca_hi; 3039 uint32_t tx_stat_gtbca_lo; 3040 uint32_t tx_stat_gtbca_hi; 3041 uint32_t tx_stat_gtovr_lo; 3042 uint32_t tx_stat_gtovr_hi; 3043 uint32_t tx_stat_gtfrg_lo; 3044 uint32_t tx_stat_gtfrg_hi; 3045 uint32_t tx_stat_gtpkt1_lo; /* gtpkt */ 3046 uint32_t tx_stat_gtpkt1_hi; /* gtpkt */ 3047 uint32_t tx_stat_gt64_lo; 3048 uint32_t tx_stat_gt64_hi; 3049 uint32_t tx_stat_gt127_lo; 3050 uint32_t tx_stat_gt127_hi; 3051 uint32_t tx_stat_gt255_lo; 3052 uint32_t tx_stat_gt255_hi; 3053 uint32_t tx_stat_gt511_lo; 3054 uint32_t tx_stat_gt511_hi; 3055 uint32_t tx_stat_gt1023_lo; 3056 uint32_t tx_stat_gt1023_hi; 3057 uint32_t tx_stat_gt1518_lo; 3058 uint32_t tx_stat_gt1518_hi; 3059 uint32_t tx_stat_gt2047_lo; 3060 uint32_t tx_stat_gt2047_hi; 3061 uint32_t tx_stat_gt4095_lo; 3062 uint32_t tx_stat_gt4095_hi; 3063 uint32_t tx_stat_gt9216_lo; 3064 uint32_t tx_stat_gt9216_hi; 3065 uint32_t tx_stat_gt16383_lo; 3066 uint32_t tx_stat_gt16383_hi; 3067 uint32_t tx_stat_gtmax_lo; 3068 uint32_t tx_stat_gtmax_hi; 3069 uint32_t tx_stat_gtufl_lo; 3070 uint32_t tx_stat_gtufl_hi; 3071 uint32_t tx_stat_gterr_lo; 3072 uint32_t tx_stat_gterr_hi; 3073 uint32_t tx_stat_gtbyt_lo; 3074 uint32_t tx_stat_gtbyt_hi; 3075 3076 uint32_t rx_stat_gr64_lo; 3077 uint32_t rx_stat_gr64_hi; 3078 uint32_t rx_stat_gr127_lo; 3079 uint32_t rx_stat_gr127_hi; 3080 uint32_t rx_stat_gr255_lo; 3081 uint32_t rx_stat_gr255_hi; 3082 uint32_t rx_stat_gr511_lo; 3083 uint32_t rx_stat_gr511_hi; 3084 uint32_t rx_stat_gr1023_lo; 3085 uint32_t rx_stat_gr1023_hi; 3086 uint32_t rx_stat_gr1518_lo; 3087 uint32_t rx_stat_gr1518_hi; 3088 uint32_t rx_stat_gr2047_lo; 3089 uint32_t rx_stat_gr2047_hi; 3090 uint32_t rx_stat_gr4095_lo; 3091 uint32_t rx_stat_gr4095_hi; 3092 uint32_t rx_stat_gr9216_lo; 3093 uint32_t rx_stat_gr9216_hi; 3094 uint32_t rx_stat_gr16383_lo; 3095 uint32_t rx_stat_gr16383_hi; 3096 uint32_t rx_stat_grmax_lo; 3097 uint32_t rx_stat_grmax_hi; 3098 uint32_t rx_stat_grpkt_lo; 3099 uint32_t rx_stat_grpkt_hi; 3100 uint32_t rx_stat_grfcs_lo; 3101 uint32_t rx_stat_grfcs_hi; 3102 uint32_t rx_stat_gruca_lo; 3103 uint32_t rx_stat_gruca_hi; 3104 uint32_t rx_stat_grmca_lo; 3105 uint32_t rx_stat_grmca_hi; 3106 uint32_t rx_stat_grbca_lo; 3107 uint32_t rx_stat_grbca_hi; 3108 uint32_t rx_stat_grxpf_lo; /* grpf */ 3109 uint32_t rx_stat_grxpf_hi; /* grpf */ 3110 uint32_t rx_stat_grpp_lo; 3111 uint32_t rx_stat_grpp_hi; 3112 uint32_t rx_stat_grxuo_lo; /* gruo */ 3113 uint32_t rx_stat_grxuo_hi; /* gruo */ 3114 uint32_t rx_stat_grjbr_lo; 3115 uint32_t rx_stat_grjbr_hi; 3116 uint32_t rx_stat_grovr_lo; 3117 uint32_t rx_stat_grovr_hi; 3118 uint32_t rx_stat_grxcf_lo; /* grcf */ 3119 uint32_t rx_stat_grxcf_hi; /* grcf */ 3120 uint32_t rx_stat_grflr_lo; 3121 uint32_t rx_stat_grflr_hi; 3122 uint32_t rx_stat_grpok_lo; 3123 uint32_t rx_stat_grpok_hi; 3124 uint32_t rx_stat_grmeg_lo; 3125 uint32_t rx_stat_grmeg_hi; 3126 uint32_t rx_stat_grmeb_lo; 3127 uint32_t rx_stat_grmeb_hi; 3128 uint32_t rx_stat_grbyt_lo; 3129 uint32_t rx_stat_grbyt_hi; 3130 uint32_t rx_stat_grund_lo; 3131 uint32_t rx_stat_grund_hi; 3132 uint32_t rx_stat_grfrg_lo; 3133 uint32_t rx_stat_grfrg_hi; 3134 uint32_t rx_stat_grerb_lo; /* grerrbyt */ 3135 uint32_t rx_stat_grerb_hi; /* grerrbyt */ 3136 uint32_t rx_stat_grfre_lo; /* grfrerr */ 3137 uint32_t rx_stat_grfre_hi; /* grfrerr */ 3138 uint32_t rx_stat_gripj_lo; 3139 uint32_t rx_stat_gripj_hi; 3140}; 3141 3142struct mstat_stats { 3143 struct { 3144 /* OTE MSTAT on E3 has a bug where this register's contents are 3145 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 3146 */ 3147 uint32_t tx_gtxpok_lo; 3148 uint32_t tx_gtxpok_hi; 3149 uint32_t tx_gtxpf_lo; 3150 uint32_t tx_gtxpf_hi; 3151 uint32_t tx_gtxpp_lo; 3152 uint32_t tx_gtxpp_hi; 3153 uint32_t tx_gtfcs_lo; 3154 uint32_t tx_gtfcs_hi; 3155 uint32_t tx_gtuca_lo; 3156 uint32_t tx_gtuca_hi; 3157 uint32_t tx_gtmca_lo; 3158 uint32_t tx_gtmca_hi; 3159 uint32_t tx_gtgca_lo; 3160 uint32_t tx_gtgca_hi; 3161 uint32_t tx_gtpkt_lo; 3162 uint32_t tx_gtpkt_hi; 3163 uint32_t tx_gt64_lo; 3164 uint32_t tx_gt64_hi; 3165 uint32_t tx_gt127_lo; 3166 uint32_t tx_gt127_hi; 3167 uint32_t tx_gt255_lo; 3168 uint32_t tx_gt255_hi; 3169 uint32_t tx_gt511_lo; 3170 uint32_t tx_gt511_hi; 3171 uint32_t tx_gt1023_lo; 3172 uint32_t tx_gt1023_hi; 3173 uint32_t tx_gt1518_lo; 3174 uint32_t tx_gt1518_hi; 3175 uint32_t tx_gt2047_lo; 3176 uint32_t tx_gt2047_hi; 3177 uint32_t tx_gt4095_lo; 3178 uint32_t tx_gt4095_hi; 3179 uint32_t tx_gt9216_lo; 3180 uint32_t tx_gt9216_hi; 3181 uint32_t tx_gt16383_lo; 3182 uint32_t tx_gt16383_hi; 3183 uint32_t tx_gtufl_lo; 3184 uint32_t tx_gtufl_hi; 3185 uint32_t tx_gterr_lo; 3186 uint32_t tx_gterr_hi; 3187 uint32_t tx_gtbyt_lo; 3188 uint32_t tx_gtbyt_hi; 3189 uint32_t tx_collisions_lo; 3190 uint32_t tx_collisions_hi; 3191 uint32_t tx_singlecollision_lo; 3192 uint32_t tx_singlecollision_hi; 3193 uint32_t tx_multiplecollisions_lo; 3194 uint32_t tx_multiplecollisions_hi; 3195 uint32_t tx_deferred_lo; 3196 uint32_t tx_deferred_hi; 3197 uint32_t tx_excessivecollisions_lo; 3198 uint32_t tx_excessivecollisions_hi; 3199 uint32_t tx_latecollisions_lo; 3200 uint32_t tx_latecollisions_hi; 3201 } stats_tx; 3202 3203 struct { 3204 uint32_t rx_gr64_lo; 3205 uint32_t rx_gr64_hi; 3206 uint32_t rx_gr127_lo; 3207 uint32_t rx_gr127_hi; 3208 uint32_t rx_gr255_lo; 3209 uint32_t rx_gr255_hi; 3210 uint32_t rx_gr511_lo; 3211 uint32_t rx_gr511_hi; 3212 uint32_t rx_gr1023_lo; 3213 uint32_t rx_gr1023_hi; 3214 uint32_t rx_gr1518_lo; 3215 uint32_t rx_gr1518_hi; 3216 uint32_t rx_gr2047_lo; 3217 uint32_t rx_gr2047_hi; 3218 uint32_t rx_gr4095_lo; 3219 uint32_t rx_gr4095_hi; 3220 uint32_t rx_gr9216_lo; 3221 uint32_t rx_gr9216_hi; 3222 uint32_t rx_gr16383_lo; 3223 uint32_t rx_gr16383_hi; 3224 uint32_t rx_grpkt_lo; 3225 uint32_t rx_grpkt_hi; 3226 uint32_t rx_grfcs_lo; 3227 uint32_t rx_grfcs_hi; 3228 uint32_t rx_gruca_lo; 3229 uint32_t rx_gruca_hi; 3230 uint32_t rx_grmca_lo; 3231 uint32_t rx_grmca_hi; 3232 uint32_t rx_grbca_lo; 3233 uint32_t rx_grbca_hi; 3234 uint32_t rx_grxpf_lo; 3235 uint32_t rx_grxpf_hi; 3236 uint32_t rx_grxpp_lo; 3237 uint32_t rx_grxpp_hi; 3238 uint32_t rx_grxuo_lo; 3239 uint32_t rx_grxuo_hi; 3240 uint32_t rx_grovr_lo; 3241 uint32_t rx_grovr_hi; 3242 uint32_t rx_grxcf_lo; 3243 uint32_t rx_grxcf_hi; 3244 uint32_t rx_grflr_lo; 3245 uint32_t rx_grflr_hi; 3246 uint32_t rx_grpok_lo; 3247 uint32_t rx_grpok_hi; 3248 uint32_t rx_grbyt_lo; 3249 uint32_t rx_grbyt_hi; 3250 uint32_t rx_grund_lo; 3251 uint32_t rx_grund_hi; 3252 uint32_t rx_grfrg_lo; 3253 uint32_t rx_grfrg_hi; 3254 uint32_t rx_grerb_lo; 3255 uint32_t rx_grerb_hi; 3256 uint32_t rx_grfre_lo; 3257 uint32_t rx_grfre_hi; 3258 3259 uint32_t rx_alignmenterrors_lo; 3260 uint32_t rx_alignmenterrors_hi; 3261 uint32_t rx_falsecarrier_lo; 3262 uint32_t rx_falsecarrier_hi; 3263 uint32_t rx_llfcmsgcnt_lo; 3264 uint32_t rx_llfcmsgcnt_hi; 3265 } stats_rx; 3266}; 3267 3268union mac_stats { 3269 struct emac_stats emac_stats; 3270 struct bmac1_stats bmac1_stats; 3271 struct bmac2_stats bmac2_stats; 3272 struct mstat_stats mstat_stats; 3273}; 3274 3275 3276struct mac_stx { 3277 /* in_bad_octets */ 3278 uint32_t rx_stat_ifhcinbadoctets_hi; 3279 uint32_t rx_stat_ifhcinbadoctets_lo; 3280 3281 /* out_bad_octets */ 3282 uint32_t tx_stat_ifhcoutbadoctets_hi; 3283 uint32_t tx_stat_ifhcoutbadoctets_lo; 3284 3285 /* crc_receive_errors */ 3286 uint32_t rx_stat_dot3statsfcserrors_hi; 3287 uint32_t rx_stat_dot3statsfcserrors_lo; 3288 /* alignment_errors */ 3289 uint32_t rx_stat_dot3statsalignmenterrors_hi; 3290 uint32_t rx_stat_dot3statsalignmenterrors_lo; 3291 /* carrier_sense_errors */ 3292 uint32_t rx_stat_dot3statscarriersenseerrors_hi; 3293 uint32_t rx_stat_dot3statscarriersenseerrors_lo; 3294 /* false_carrier_detections */ 3295 uint32_t rx_stat_falsecarriererrors_hi; 3296 uint32_t rx_stat_falsecarriererrors_lo; 3297 3298 /* runt_packets_received */ 3299 uint32_t rx_stat_etherstatsundersizepkts_hi; 3300 uint32_t rx_stat_etherstatsundersizepkts_lo; 3301 /* jabber_packets_received */ 3302 uint32_t rx_stat_dot3statsframestoolong_hi; 3303 uint32_t rx_stat_dot3statsframestoolong_lo; 3304 3305 /* error_runt_packets_received */ 3306 uint32_t rx_stat_etherstatsfragments_hi; 3307 uint32_t rx_stat_etherstatsfragments_lo; 3308 /* error_jabber_packets_received */ 3309 uint32_t rx_stat_etherstatsjabbers_hi; 3310 uint32_t rx_stat_etherstatsjabbers_lo; 3311 3312 /* control_frames_received */ 3313 uint32_t rx_stat_maccontrolframesreceived_hi; 3314 uint32_t rx_stat_maccontrolframesreceived_lo; 3315 uint32_t rx_stat_mac_xpf_hi; 3316 uint32_t rx_stat_mac_xpf_lo; 3317 uint32_t rx_stat_mac_xcf_hi; 3318 uint32_t rx_stat_mac_xcf_lo; 3319 3320 /* xoff_state_entered */ 3321 uint32_t rx_stat_xoffstateentered_hi; 3322 uint32_t rx_stat_xoffstateentered_lo; 3323 /* pause_xon_frames_received */ 3324 uint32_t rx_stat_xonpauseframesreceived_hi; 3325 uint32_t rx_stat_xonpauseframesreceived_lo; 3326 /* pause_xoff_frames_received */ 3327 uint32_t rx_stat_xoffpauseframesreceived_hi; 3328 uint32_t rx_stat_xoffpauseframesreceived_lo; 3329 /* pause_xon_frames_transmitted */ 3330 uint32_t tx_stat_outxonsent_hi; 3331 uint32_t tx_stat_outxonsent_lo; 3332 /* pause_xoff_frames_transmitted */ 3333 uint32_t tx_stat_outxoffsent_hi; 3334 uint32_t tx_stat_outxoffsent_lo; 3335 /* flow_control_done */ 3336 uint32_t tx_stat_flowcontroldone_hi; 3337 uint32_t tx_stat_flowcontroldone_lo; 3338 3339 /* ether_stats_collisions */ 3340 uint32_t tx_stat_etherstatscollisions_hi; 3341 uint32_t tx_stat_etherstatscollisions_lo; 3342 /* single_collision_transmit_frames */ 3343 uint32_t tx_stat_dot3statssinglecollisionframes_hi; 3344 uint32_t tx_stat_dot3statssinglecollisionframes_lo; 3345 /* multiple_collision_transmit_frames */ 3346 uint32_t tx_stat_dot3statsmultiplecollisionframes_hi; 3347 uint32_t tx_stat_dot3statsmultiplecollisionframes_lo; 3348 /* deferred_transmissions */ 3349 uint32_t tx_stat_dot3statsdeferredtransmissions_hi; 3350 uint32_t tx_stat_dot3statsdeferredtransmissions_lo; 3351 /* excessive_collision_frames */ 3352 uint32_t tx_stat_dot3statsexcessivecollisions_hi; 3353 uint32_t tx_stat_dot3statsexcessivecollisions_lo; 3354 /* late_collision_frames */ 3355 uint32_t tx_stat_dot3statslatecollisions_hi; 3356 uint32_t tx_stat_dot3statslatecollisions_lo; 3357 3358 /* frames_transmitted_64_bytes */ 3359 uint32_t tx_stat_etherstatspkts64octets_hi; 3360 uint32_t tx_stat_etherstatspkts64octets_lo; 3361 /* frames_transmitted_65_127_bytes */ 3362 uint32_t tx_stat_etherstatspkts65octetsto127octets_hi; 3363 uint32_t tx_stat_etherstatspkts65octetsto127octets_lo; 3364 /* frames_transmitted_128_255_bytes */ 3365 uint32_t tx_stat_etherstatspkts128octetsto255octets_hi; 3366 uint32_t tx_stat_etherstatspkts128octetsto255octets_lo; 3367 /* frames_transmitted_256_511_bytes */ 3368 uint32_t tx_stat_etherstatspkts256octetsto511octets_hi; 3369 uint32_t tx_stat_etherstatspkts256octetsto511octets_lo; 3370 /* frames_transmitted_512_1023_bytes */ 3371 uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi; 3372 uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo; 3373 /* frames_transmitted_1024_1522_bytes */ 3374 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi; 3375 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo; 3376 /* frames_transmitted_1523_9022_bytes */ 3377 uint32_t tx_stat_etherstatspktsover1522octets_hi; 3378 uint32_t tx_stat_etherstatspktsover1522octets_lo; 3379 uint32_t tx_stat_mac_2047_hi; 3380 uint32_t tx_stat_mac_2047_lo; 3381 uint32_t tx_stat_mac_4095_hi; 3382 uint32_t tx_stat_mac_4095_lo; 3383 uint32_t tx_stat_mac_9216_hi; 3384 uint32_t tx_stat_mac_9216_lo; 3385 uint32_t tx_stat_mac_16383_hi; 3386 uint32_t tx_stat_mac_16383_lo; 3387 3388 /* internal_mac_transmit_errors */ 3389 uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi; 3390 uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo; 3391 3392 /* if_out_discards */ 3393 uint32_t tx_stat_mac_ufl_hi; 3394 uint32_t tx_stat_mac_ufl_lo; 3395}; 3396 3397 3398#define MAC_STX_IDX_MAX 2 3399 3400struct host_port_stats { 3401 uint32_t host_port_stats_counter; 3402 3403 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 3404 3405 uint32_t brb_drop_hi; 3406 uint32_t brb_drop_lo; 3407 3408 uint32_t not_used; /* obsolete as of MFW 7.2.1 */ 3409 3410 uint32_t pfc_frames_tx_hi; 3411 uint32_t pfc_frames_tx_lo; 3412 uint32_t pfc_frames_rx_hi; 3413 uint32_t pfc_frames_rx_lo; 3414 3415 uint32_t eee_lpi_count_hi; 3416 uint32_t eee_lpi_count_lo; 3417}; 3418 3419 3420struct host_func_stats { 3421 uint32_t host_func_stats_start; 3422 3423 uint32_t total_bytes_received_hi; 3424 uint32_t total_bytes_received_lo; 3425 3426 uint32_t total_bytes_transmitted_hi; 3427 uint32_t total_bytes_transmitted_lo; 3428 3429 uint32_t total_unicast_packets_received_hi; 3430 uint32_t total_unicast_packets_received_lo; 3431 3432 uint32_t total_multicast_packets_received_hi; 3433 uint32_t total_multicast_packets_received_lo; 3434 3435 uint32_t total_broadcast_packets_received_hi; 3436 uint32_t total_broadcast_packets_received_lo; 3437 3438 uint32_t total_unicast_packets_transmitted_hi; 3439 uint32_t total_unicast_packets_transmitted_lo; 3440 3441 uint32_t total_multicast_packets_transmitted_hi; 3442 uint32_t total_multicast_packets_transmitted_lo; 3443 3444 uint32_t total_broadcast_packets_transmitted_hi; 3445 uint32_t total_broadcast_packets_transmitted_lo; 3446 3447 uint32_t valid_bytes_received_hi; 3448 uint32_t valid_bytes_received_lo; 3449 3450 uint32_t host_func_stats_end; 3451}; 3452 3453/* VIC definitions */ 3454#define VICSTATST_UIF_INDEX 2 3455 3456/* 3457 * stats collected for afex. 3458 * NOTE: structure is exactly as expected to be received by the switch. 3459 * order must remain exactly as is unless protocol changes ! 3460 */ 3461struct afex_stats { 3462 uint32_t tx_unicast_frames_hi; 3463 uint32_t tx_unicast_frames_lo; 3464 uint32_t tx_unicast_bytes_hi; 3465 uint32_t tx_unicast_bytes_lo; 3466 uint32_t tx_multicast_frames_hi; 3467 uint32_t tx_multicast_frames_lo; 3468 uint32_t tx_multicast_bytes_hi; 3469 uint32_t tx_multicast_bytes_lo; 3470 uint32_t tx_broadcast_frames_hi; 3471 uint32_t tx_broadcast_frames_lo; 3472 uint32_t tx_broadcast_bytes_hi; 3473 uint32_t tx_broadcast_bytes_lo; 3474 uint32_t tx_frames_discarded_hi; 3475 uint32_t tx_frames_discarded_lo; 3476 uint32_t tx_frames_dropped_hi; 3477 uint32_t tx_frames_dropped_lo; 3478 3479 uint32_t rx_unicast_frames_hi; 3480 uint32_t rx_unicast_frames_lo; 3481 uint32_t rx_unicast_bytes_hi; 3482 uint32_t rx_unicast_bytes_lo; 3483 uint32_t rx_multicast_frames_hi; 3484 uint32_t rx_multicast_frames_lo; 3485 uint32_t rx_multicast_bytes_hi; 3486 uint32_t rx_multicast_bytes_lo; 3487 uint32_t rx_broadcast_frames_hi; 3488 uint32_t rx_broadcast_frames_lo; 3489 uint32_t rx_broadcast_bytes_hi; 3490 uint32_t rx_broadcast_bytes_lo; 3491 uint32_t rx_frames_discarded_hi; 3492 uint32_t rx_frames_discarded_lo; 3493 uint32_t rx_frames_dropped_hi; 3494 uint32_t rx_frames_dropped_lo; 3495}; 3496 3497/* To maintain backward compatibility between FW and drivers, new elements */ 3498/* should be added to the end of the structure. */ 3499 3500/* Per Port Statistics */ 3501struct port_info { 3502 uint32_t size; /* size of this structure (i.e. sizeof(port_info)) */ 3503 uint32_t enabled; /* 0 =Disabled, 1= Enabled */ 3504 uint32_t link_speed; /* multiplier of 100Mb */ 3505 uint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */ 3506 uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/ 3507 uint32_t flex10; /* Flex10 mode enabled. non zero = yes */ 3508 uint32_t rx_drops; /* RX Discards. Counters roll over, never reset */ 3509 uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI. 3510 This is flagged by Consumer as an error. */ 3511 uint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */ 3512 uint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */ 3513 uint32_t rx_mcast_lo; /* RX Multicast Packets */ 3514 uint32_t rx_mcast_hi; /* RX Multicast Packets */ 3515 uint32_t rx_bcast_lo; /* RX Broadcast Packets */ 3516 uint32_t rx_bcast_hi; /* RX Broadcast Packets */ 3517 uint32_t tx_uncast_lo; /* TX Unicast Packets */ 3518 uint32_t tx_uncast_hi; /* TX Unicast Packets */ 3519 uint32_t tx_mcast_lo; /* TX Multicast Packets */ 3520 uint32_t tx_mcast_hi; /* TX Multicast Packets */ 3521 uint32_t tx_bcast_lo; /* TX Broadcast Packets */ 3522 uint32_t tx_bcast_hi; /* TX Broadcast Packets */ 3523 uint32_t tx_errors; /* TX Errors */ 3524 uint32_t tx_discards; /* TX Discards */ 3525 uint32_t rx_frames_lo; /* RX Frames received */ 3526 uint32_t rx_frames_hi; /* RX Frames received */ 3527 uint32_t rx_bytes_lo; /* RX Bytes received */ 3528 uint32_t rx_bytes_hi; /* RX Bytes received */ 3529 uint32_t tx_frames_lo; /* TX Frames sent */ 3530 uint32_t tx_frames_hi; /* TX Frames sent */ 3531 uint32_t tx_bytes_lo; /* TX Bytes sent */ 3532 uint32_t tx_bytes_hi; /* TX Bytes sent */ 3533 uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled. 3534 1:1 bit for link good, 3535 2:1 Set if link changed between last poll. */ 3536 uint32_t tx_pfc_frames_lo; /* PFC Frames sent. */ 3537 uint32_t tx_pfc_frames_hi; /* PFC Frames sent. */ 3538 uint32_t rx_pfc_frames_lo; /* PFC Frames Received. */ 3539 uint32_t rx_pfc_frames_hi; /* PFC Frames Received. */ 3540}; 3541 3542 3543#define BCM_5710_FW_MAJOR_VERSION 7 3544#define BCM_5710_FW_MINOR_VERSION 13 3545#define BCM_5710_FW_REVISION_VERSION 1 3546#define BCM_5710_FW_ENGINEERING_VERSION 0 3547#define BCM_5710_FW_COMPILE_FLAGS 1 3548 3549 3550/* 3551 * attention bits $$KEEP_ENDIANNESS$$ 3552 */ 3553struct atten_sp_status_block 3554{ 3555 uint32_t attn_bits /* 16 bit of attention signal lines */; 3556 uint32_t attn_bits_ack /* 16 bit of attention signal ack */; 3557 uint8_t status_block_id /* status block id */; 3558 uint8_t reserved0 /* resreved for padding */; 3559 uint16_t attn_bits_index /* attention bits running index */; 3560 uint32_t reserved1 /* resreved for padding */; 3561}; 3562 3563 3564/* 3565 * The eth aggregative context of Cstorm 3566 */ 3567struct cstorm_eth_ag_context 3568{ 3569 uint32_t __reserved0[10]; 3570}; 3571 3572 3573/* 3574 * The iscsi aggregative context of Cstorm 3575 */ 3576struct cstorm_iscsi_ag_context 3577{ 3578 uint32_t agg_vars1; 3579 #define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0) /* BitField agg_vars1Various aggregative variables The state of the connection */ 3580 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0 3581 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 3582 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8 3583 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 3584 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9 3585 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 3586 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10 3587 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 3588 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11 3589 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12) /* BitField agg_vars1Various aggregative variables ULP Rx SE counter flag enable */ 3590 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12 3591 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13) /* BitField agg_vars1Various aggregative variables ULP Rx invalidate counter flag enable */ 3592 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13 3593 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14) /* BitField agg_vars1Various aggregative variables Aux 4 counter flag */ 3594 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14 3595 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) /* BitField agg_vars1Various aggregative variables The connection QOS */ 3596 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16 3597 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18) /* BitField agg_vars1Various aggregative variables Enable decision rule for fin_received_cf */ 3598 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18 3599 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 1 */ 3600 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19 3601 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 2 */ 3602 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20 3603 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 3 */ 3604 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21 3605 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 4 */ 3606 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22 3607 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ, 3-GT, 4-GE, 5-LS, 6-LE */ 3608 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23 3609 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */ 3610 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26 3611 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */ 3612 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28 3613 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */ 3614 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30 3615#if defined(__BIG_ENDIAN) 3616 uint8_t __aux1_th /* Aux1 threhsold for the decision */; 3617 uint8_t __aux1_val /* Aux1 aggregation value */; 3618 uint16_t __agg_vars2 /* Various aggregative variables*/; 3619#elif defined(__LITTLE_ENDIAN) 3620 uint16_t __agg_vars2 /* Various aggregative variables*/; 3621 uint8_t __aux1_val /* Aux1 aggregation value */; 3622 uint8_t __aux1_th /* Aux1 threhsold for the decision */; 3623#endif 3624 uint32_t rel_seq /* The sequence to release */; 3625 uint32_t rel_seq_th /* The threshold for the released sequence */; 3626#if defined(__BIG_ENDIAN) 3627 uint16_t hq_cons /* The HQ Consumer */; 3628 uint16_t hq_prod /* The HQ producer */; 3629#elif defined(__LITTLE_ENDIAN) 3630 uint16_t hq_prod /* The HQ producer */; 3631 uint16_t hq_cons /* The HQ Consumer */; 3632#endif 3633#if defined(__BIG_ENDIAN) 3634 uint8_t __reserved62 /* Mask value for the decision algorithm of the general flags */; 3635 uint8_t __reserved61 /* General flags */; 3636 uint8_t __reserved60 /* ORQ consumer updated by the completor */; 3637 uint8_t __reserved59 /* ORQ ULP Rx consumer */; 3638#elif defined(__LITTLE_ENDIAN) 3639 uint8_t __reserved59 /* ORQ ULP Rx consumer */; 3640 uint8_t __reserved60 /* ORQ consumer updated by the completor */; 3641 uint8_t __reserved61 /* General flags */; 3642 uint8_t __reserved62 /* Mask value for the decision algorithm of the general flags */; 3643#endif 3644#if defined(__BIG_ENDIAN) 3645 uint16_t __reserved64 /* RQ consumer kept by the completor */; 3646 uint16_t cq_u_prod /* Ustorm producer of CQ */; 3647#elif defined(__LITTLE_ENDIAN) 3648 uint16_t cq_u_prod /* Ustorm producer of CQ */; 3649 uint16_t __reserved64 /* RQ consumer kept by the completor */; 3650#endif 3651 uint32_t __cq_u_prod1 /* Ustorm producer of CQ 1 */; 3652#if defined(__BIG_ENDIAN) 3653 uint16_t __agg_vars3 /* Various aggregative variables*/; 3654 uint16_t cq_u_pend /* Ustorm pending completions of CQ */; 3655#elif defined(__LITTLE_ENDIAN) 3656 uint16_t cq_u_pend /* Ustorm pending completions of CQ */; 3657 uint16_t __agg_vars3 /* Various aggregative variables*/; 3658#endif 3659#if defined(__BIG_ENDIAN) 3660 uint16_t __aux2_th /* Aux2 threhsold for the decision */; 3661 uint16_t aux2_val /* Aux2 aggregation value */; 3662#elif defined(__LITTLE_ENDIAN) 3663 uint16_t aux2_val /* Aux2 aggregation value */; 3664 uint16_t __aux2_th /* Aux2 threhsold for the decision */; 3665#endif 3666}; 3667 3668 3669/* 3670 * The toe aggregative context of Cstorm 3671 */ 3672struct cstorm_toe_ag_context 3673{ 3674 uint32_t __agg_vars1 /* Various aggregative variables*/; 3675#if defined(__BIG_ENDIAN) 3676 uint8_t __aux1_th /* Aux1 threhsold for the decision */; 3677 uint8_t __aux1_val /* Aux1 aggregation value */; 3678 uint16_t __agg_vars2 /* Various aggregative variables*/; 3679#elif defined(__LITTLE_ENDIAN) 3680 uint16_t __agg_vars2 /* Various aggregative variables*/; 3681 uint8_t __aux1_val /* Aux1 aggregation value */; 3682 uint8_t __aux1_th /* Aux1 threhsold for the decision */; 3683#endif 3684 uint32_t rel_seq /* The sequence to release */; 3685 uint32_t __rel_seq_threshold /* The threshold for the released sequence */; 3686#if defined(__BIG_ENDIAN) 3687 uint16_t __reserved58 /* The HQ Consumer */; 3688 uint16_t bd_prod /* The HQ producer */; 3689#elif defined(__LITTLE_ENDIAN) 3690 uint16_t bd_prod /* The HQ producer */; 3691 uint16_t __reserved58 /* The HQ Consumer */; 3692#endif 3693#if defined(__BIG_ENDIAN) 3694 uint8_t __reserved62 /* Mask value for the decision algorithm of the general flags */; 3695 uint8_t __reserved61 /* General flags */; 3696 uint8_t __reserved60 /* ORQ consumer updated by the completor */; 3697 uint8_t __completion_opcode /* ORQ ULP Rx consumer */; 3698#elif defined(__LITTLE_ENDIAN) 3699 uint8_t __completion_opcode /* ORQ ULP Rx consumer */; 3700 uint8_t __reserved60 /* ORQ consumer updated by the completor */; 3701 uint8_t __reserved61 /* General flags */; 3702 uint8_t __reserved62 /* Mask value for the decision algorithm of the general flags */; 3703#endif 3704#if defined(__BIG_ENDIAN) 3705 uint16_t __reserved64 /* RQ consumer kept by the completor */; 3706 uint16_t __reserved63 /* RQ consumer updated by the ULP RX */; 3707#elif defined(__LITTLE_ENDIAN) 3708 uint16_t __reserved63 /* RQ consumer updated by the ULP RX */; 3709 uint16_t __reserved64 /* RQ consumer kept by the completor */; 3710#endif 3711 uint32_t snd_max /* The ACK sequence number received in the last completed DDP */; 3712#if defined(__BIG_ENDIAN) 3713 uint16_t __agg_vars3 /* Various aggregative variables*/; 3714 uint16_t __reserved67 /* A counter for the number of RQ WQEs with invalidate the USTORM encountered */; 3715#elif defined(__LITTLE_ENDIAN) 3716 uint16_t __reserved67 /* A counter for the number of RQ WQEs with invalidate the USTORM encountered */; 3717 uint16_t __agg_vars3 /* Various aggregative variables*/; 3718#endif 3719#if defined(__BIG_ENDIAN) 3720 uint16_t __aux2_th /* Aux2 threhsold for the decision */; 3721 uint16_t __aux2_val /* Aux2 aggregation value */; 3722#elif defined(__LITTLE_ENDIAN) 3723 uint16_t __aux2_val /* Aux2 aggregation value */; 3724 uint16_t __aux2_th /* Aux2 threhsold for the decision */; 3725#endif 3726}; 3727 3728 3729/* 3730 * dmae command structure 3731 */ 3732struct dmae_cmd 3733{ 3734 uint32_t opcode; 3735 #define DMAE_CMD_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */ 3736 #define DMAE_CMD_SRC_SHIFT 0 3737 #define DMAE_CMD_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 3738 #define DMAE_CMD_DST_SHIFT 1 3739 #define DMAE_CMD_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */ 3740 #define DMAE_CMD_C_DST_SHIFT 3 3741 #define DMAE_CMD_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */ 3742 #define DMAE_CMD_C_TYPE_ENABLE_SHIFT 4 3743 #define DMAE_CMD_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */ 3744 #define DMAE_CMD_C_TYPE_CRC_ENABLE_SHIFT 5 3745 #define DMAE_CMD_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */ 3746 #define DMAE_CMD_C_TYPE_CRC_OFFSET_SHIFT 6 3747 #define DMAE_CMD_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */ 3748 #define DMAE_CMD_ENDIANITY_SHIFT 9 3749 #define DMAE_CMD_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */ 3750 #define DMAE_CMD_PORT_SHIFT 11 3751 #define DMAE_CMD_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */ 3752 #define DMAE_CMD_CRC_RESET_SHIFT 12 3753 #define DMAE_CMD_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */ 3754 #define DMAE_CMD_SRC_RESET_SHIFT 13 3755 #define DMAE_CMD_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */ 3756 #define DMAE_CMD_DST_RESET_SHIFT 14 3757 #define DMAE_CMD_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */ 3758 #define DMAE_CMD_E1HVN_SHIFT 15 3759 #define DMAE_CMD_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */ 3760 #define DMAE_CMD_DST_VN_SHIFT 17 3761 #define DMAE_CMD_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */ 3762 #define DMAE_CMD_C_FUNC_SHIFT 19 3763 #define DMAE_CMD_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */ 3764 #define DMAE_CMD_ERR_POLICY_SHIFT 20 3765 #define DMAE_CMD_RESERVED0 (0x3FF<<22) /* BitField opcode */ 3766 #define DMAE_CMD_RESERVED0_SHIFT 22 3767 uint32_t src_addr_lo /* source address low/grc address */; 3768 uint32_t src_addr_hi /* source address hi */; 3769 uint32_t dst_addr_lo /* dest address low/grc address */; 3770 uint32_t dst_addr_hi /* dest address hi */; 3771#if defined(__BIG_ENDIAN) 3772 uint16_t opcode_iov; 3773 #define DMAE_CMD_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3774 #define DMAE_CMD_SRC_VFID_SHIFT 0 3775 #define DMAE_CMD_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3776 #define DMAE_CMD_SRC_VFPF_SHIFT 6 3777 #define DMAE_CMD_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3778 #define DMAE_CMD_RESERVED1_SHIFT 7 3779 #define DMAE_CMD_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3780 #define DMAE_CMD_DST_VFID_SHIFT 8 3781 #define DMAE_CMD_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3782 #define DMAE_CMD_DST_VFPF_SHIFT 14 3783 #define DMAE_CMD_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3784 #define DMAE_CMD_RESERVED2_SHIFT 15 3785 uint16_t len /* copy length */; 3786#elif defined(__LITTLE_ENDIAN) 3787 uint16_t len /* copy length */; 3788 uint16_t opcode_iov; 3789 #define DMAE_CMD_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3790 #define DMAE_CMD_SRC_VFID_SHIFT 0 3791 #define DMAE_CMD_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3792 #define DMAE_CMD_SRC_VFPF_SHIFT 6 3793 #define DMAE_CMD_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3794 #define DMAE_CMD_RESERVED1_SHIFT 7 3795 #define DMAE_CMD_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3796 #define DMAE_CMD_DST_VFID_SHIFT 8 3797 #define DMAE_CMD_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3798 #define DMAE_CMD_DST_VFPF_SHIFT 14 3799 #define DMAE_CMD_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3800 #define DMAE_CMD_RESERVED2_SHIFT 15 3801#endif 3802 uint32_t comp_addr_lo /* completion address low/grc address */; 3803 uint32_t comp_addr_hi /* completion address hi */; 3804 uint32_t comp_val /* value to write to completion address */; 3805 uint32_t crc32 /* crc32 result */; 3806 uint32_t crc32_c /* crc32_c result */; 3807#if defined(__BIG_ENDIAN) 3808 uint16_t crc16_c /* crc16_c result */; 3809 uint16_t crc16 /* crc16 result */; 3810#elif defined(__LITTLE_ENDIAN) 3811 uint16_t crc16 /* crc16 result */; 3812 uint16_t crc16_c /* crc16_c result */; 3813#endif 3814#if defined(__BIG_ENDIAN) 3815 uint16_t reserved3; 3816 uint16_t crc_t10 /* crc_t10 result */; 3817#elif defined(__LITTLE_ENDIAN) 3818 uint16_t crc_t10 /* crc_t10 result */; 3819 uint16_t reserved3; 3820#endif 3821#if defined(__BIG_ENDIAN) 3822 uint16_t xsum8 /* checksum8 result */; 3823 uint16_t xsum16 /* checksum16 result */; 3824#elif defined(__LITTLE_ENDIAN) 3825 uint16_t xsum16 /* checksum16 result */; 3826 uint16_t xsum8 /* checksum8 result */; 3827#endif 3828}; 3829 3830 3831/* 3832 * common data for all protocols 3833 */ 3834struct doorbell_hdr_t 3835{ 3836 uint8_t data; 3837 #define DOORBELL_HDR_T_RX (0x1<<0) /* BitField data 1 for rx doorbell, 0 for tx doorbell */ 3838 #define DOORBELL_HDR_T_RX_SHIFT 0 3839 #define DOORBELL_HDR_T_DB_TYPE (0x1<<1) /* BitField data 0 for normal doorbell, 1 for advertise wnd doorbell */ 3840 #define DOORBELL_HDR_T_DB_TYPE_SHIFT 1 3841 #define DOORBELL_HDR_T_DPM_SIZE (0x3<<2) /* BitField data rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */ 3842 #define DOORBELL_HDR_T_DPM_SIZE_SHIFT 2 3843 #define DOORBELL_HDR_T_CONN_TYPE (0xF<<4) /* BitField data connection type */ 3844 #define DOORBELL_HDR_T_CONN_TYPE_SHIFT 4 3845}; 3846 3847/* 3848 * Ethernet doorbell 3849 */ 3850struct eth_tx_doorbell 3851{ 3852#if defined(__BIG_ENDIAN) 3853 uint16_t npackets /* number of data bytes that were added in the doorbell */; 3854 uint8_t params; 3855 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3856 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3857 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3858 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3859 #define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3860 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3861 struct doorbell_hdr_t hdr; 3862#elif defined(__LITTLE_ENDIAN) 3863 struct doorbell_hdr_t hdr; 3864 uint8_t params; 3865 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3866 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3867 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3868 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3869 #define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3870 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3871 uint16_t npackets /* number of data bytes that were added in the doorbell */; 3872#endif 3873}; 3874 3875 3876/* 3877 * 3 lines. status block $$KEEP_ENDIANNESS$$ 3878 */ 3879struct hc_status_block_e1x 3880{ 3881 uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */; 3882 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3883 uint32_t rsrv[11]; 3884}; 3885 3886/* 3887 * host status block 3888 */ 3889struct host_hc_status_block_e1x 3890{ 3891 struct hc_status_block_e1x sb /* fast path indices */; 3892}; 3893 3894 3895/* 3896 * 3 lines. status block $$KEEP_ENDIANNESS$$ 3897 */ 3898struct hc_status_block_e2 3899{ 3900 uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */; 3901 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3902 uint32_t reserved[11]; 3903}; 3904 3905/* 3906 * host status block 3907 */ 3908struct host_hc_status_block_e2 3909{ 3910 struct hc_status_block_e2 sb /* fast path indices */; 3911}; 3912 3913 3914/* 3915 * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$ 3916 */ 3917struct hc_sp_status_block 3918{ 3919 uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */; 3920 uint16_t running_index /* Status Block running index */; 3921 uint16_t rsrv; 3922 uint32_t rsrv1; 3923}; 3924 3925/* 3926 * host status block 3927 */ 3928struct host_sp_status_block 3929{ 3930 struct atten_sp_status_block atten_status_block /* attention bits section */; 3931 struct hc_sp_status_block sp_sb /* slow path indices */; 3932}; 3933 3934 3935/* 3936 * IGU driver acknowledgment register 3937 */ 3938struct igu_ack_register 3939{ 3940#if defined(__BIG_ENDIAN) 3941 uint16_t sb_id_and_flags; 3942 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3943 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3944 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3945 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3946 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3947 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3948 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3949 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3950 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3951 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3952 uint16_t status_block_index /* status block index acknowledgement */; 3953#elif defined(__LITTLE_ENDIAN) 3954 uint16_t status_block_index /* status block index acknowledgement */; 3955 uint16_t sb_id_and_flags; 3956 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3957 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3958 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3959 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3960 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3961 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3962 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3963 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3964 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3965 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3966#endif 3967}; 3968 3969 3970/* 3971 * IGU driver acknowledgement register 3972 */ 3973struct igu_backward_compatible 3974{ 3975 uint32_t sb_id_and_flags; 3976 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */ 3977 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3978 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */ 3979 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3980 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3981 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3982 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3983 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3984 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3985 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3986 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */ 3987 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3988 uint32_t reserved_2; 3989}; 3990 3991 3992/* 3993 * IGU driver acknowledgement register 3994 */ 3995struct igu_regular 3996{ 3997 uint32_t sb_id_and_flags; 3998 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */ 3999 #define IGU_REGULAR_SB_INDEX_SHIFT 0 4000 #define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */ 4001 #define IGU_REGULAR_RESERVED0_SHIFT 20 4002 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */ 4003 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 4004 #define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */ 4005 #define IGU_REGULAR_BUPDATE_SHIFT 24 4006 #define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */ 4007 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 4008 #define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */ 4009 #define IGU_REGULAR_RESERVED_1_SHIFT 27 4010 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */ 4011 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 4012 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */ 4013 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 4014 #define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */ 4015 #define IGU_REGULAR_BCLEANUP_SHIFT 31 4016 uint32_t reserved_2; 4017}; 4018 4019/* 4020 * IGU driver acknowledgement register 4021 */ 4022union igu_consprod_reg 4023{ 4024 struct igu_regular regular; 4025 struct igu_backward_compatible backward_compatible; 4026}; 4027 4028 4029/* 4030 * Igu control commands 4031 */ 4032enum igu_ctrl_cmd 4033{ 4034 IGU_CTRL_CMD_TYPE_RD, 4035 IGU_CTRL_CMD_TYPE_WR, 4036 MAX_IGU_CTRL_CMD}; 4037 4038 4039/* 4040 * Control register for the IGU command register 4041 */ 4042struct igu_ctrl_reg 4043{ 4044 uint32_t ctrl_data; 4045 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */ 4046 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 4047 #define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */ 4048 #define IGU_CTRL_REG_FID_SHIFT 12 4049 #define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */ 4050 #define IGU_CTRL_REG_RESERVED_SHIFT 19 4051 #define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */ 4052 #define IGU_CTRL_REG_TYPE_SHIFT 20 4053 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */ 4054 #define IGU_CTRL_REG_UNUSED_SHIFT 21 4055}; 4056 4057 4058/* 4059 * Igu interrupt command 4060 */ 4061enum igu_int_cmd 4062{ 4063 IGU_INT_ENABLE, 4064 IGU_INT_DISABLE, 4065 IGU_INT_NOP, 4066 IGU_INT_NOP2, 4067 MAX_IGU_INT_CMD}; 4068 4069 4070/* 4071 * Igu segments 4072 */ 4073enum igu_seg_access 4074{ 4075 IGU_SEG_ACCESS_NORM, 4076 IGU_SEG_ACCESS_DEF, 4077 IGU_SEG_ACCESS_ATTN, 4078 MAX_IGU_SEG_ACCESS}; 4079 4080 4081/* 4082 * iscsi doorbell 4083 */ 4084struct iscsi_tx_doorbell 4085{ 4086#if defined(__BIG_ENDIAN) 4087 uint16_t reserved /* number of data bytes that were added in the doorbell */; 4088 uint8_t params; 4089 #define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 4090 #define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0 4091 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 4092 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 4093 #define ISCSI_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 4094 #define ISCSI_TX_DOORBELL_SPARE_SHIFT 7 4095 struct doorbell_hdr_t hdr; 4096#elif defined(__LITTLE_ENDIAN) 4097 struct doorbell_hdr_t hdr; 4098 uint8_t params; 4099 #define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 4100 #define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0 4101 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 4102 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 4103 #define ISCSI_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 4104 #define ISCSI_TX_DOORBELL_SPARE_SHIFT 7 4105 uint16_t reserved /* number of data bytes that were added in the doorbell */; 4106#endif 4107}; 4108 4109 4110/* 4111 * Parser parsing flags field 4112 */ 4113struct parsing_flags 4114{ 4115 uint16_t flags; 4116 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */ 4117 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 4118 #define PARSING_FLAGS_INNER_VLAN_EXIST (0x1<<1) /* BitField flagscontext flags 0 or 1 */ 4119 #define PARSING_FLAGS_INNER_VLAN_EXIST_SHIFT 1 4120 #define PARSING_FLAGS_OUTER_VLAN_EXIST (0x1<<2) /* BitField flagscontext flags 0 or 1 */ 4121 #define PARSING_FLAGS_OUTER_VLAN_EXIST_SHIFT 2 4122 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */ 4123 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 4124 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */ 4125 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 4126 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */ 4127 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 4128 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */ 4129 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 4130 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */ 4131 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 4132 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */ 4133 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 4134 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */ 4135 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 4136 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */ 4137 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 4138 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */ 4139 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 4140 #define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */ 4141 #define PARSING_FLAGS_RESERVED0_SHIFT 14 4142}; 4143 4144 4145/* 4146 * Parsing flags for TCP ACK type 4147 */ 4148enum prs_flags_ack_type 4149{ 4150 PRS_FLAG_PUREACK_PIGGY, 4151 PRS_FLAG_PUREACK_PURE, 4152 MAX_PRS_FLAGS_ACK_TYPE}; 4153 4154 4155/* 4156 * Parsing flags for Ethernet address type 4157 */ 4158enum prs_flags_eth_addr_type 4159{ 4160 PRS_FLAG_ETHTYPE_NON_UNICAST, 4161 PRS_FLAG_ETHTYPE_UNICAST, 4162 MAX_PRS_FLAGS_ETH_ADDR_TYPE}; 4163 4164 4165/* 4166 * Parsing flags for over-ethernet protocol 4167 */ 4168enum prs_flags_over_eth 4169{ 4170 PRS_FLAG_OVERETH_UNKNOWN, 4171 PRS_FLAG_OVERETH_IPV4, 4172 PRS_FLAG_OVERETH_IPV6, 4173 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 4174 MAX_PRS_FLAGS_OVER_ETH}; 4175 4176 4177/* 4178 * Parsing flags for over-IP protocol 4179 */ 4180enum prs_flags_over_ip 4181{ 4182 PRS_FLAG_OVERIP_UNKNOWN, 4183 PRS_FLAG_OVERIP_TCP, 4184 PRS_FLAG_OVERIP_UDP, 4185 MAX_PRS_FLAGS_OVER_IP}; 4186 4187 4188/* 4189 * SDM operation gen command (generate aggregative interrupt) 4190 */ 4191struct sdm_op_gen 4192{ 4193 uint32_t command; 4194 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */ 4195 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 4196 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */ 4197 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 4198 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */ 4199 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 4200 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */ 4201 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 4202 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */ 4203 #define SDM_OP_GEN_RESERVED_SHIFT 17 4204}; 4205 4206 4207/* 4208 * Timers connection context 4209 */ 4210struct timers_block_context 4211{ 4212 uint32_t __client0 /* data of client 0 of the timers block*/; 4213 uint32_t __client1 /* data of client 1 of the timers block*/; 4214 uint32_t __client2 /* data of client 2 of the timers block*/; 4215 uint32_t flags; 4216 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */ 4217 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 4218 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */ 4219 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 4220 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */ 4221 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 4222}; 4223 4224 4225/* 4226 * advertise window doorbell 4227 */ 4228struct toe_adv_wnd_doorbell 4229{ 4230#if defined(__BIG_ENDIAN) 4231 uint16_t wnd_sz_lsb /* Less significant bits of advertise window update value */; 4232 uint8_t wnd_sz_msb /* Most significant bits of advertise window update value */; 4233 struct doorbell_hdr_t hdr /* See description of the appropriate type */; 4234#elif defined(__LITTLE_ENDIAN) 4235 struct doorbell_hdr_t hdr /* See description of the appropriate type */; 4236 uint8_t wnd_sz_msb /* Most significant bits of advertise window update value */; 4237 uint16_t wnd_sz_lsb /* Less significant bits of advertise window update value */; 4238#endif 4239}; 4240 4241 4242/* 4243 * toe rx BDs update doorbell 4244 */ 4245struct toe_rx_bds_doorbell 4246{ 4247#if defined(__BIG_ENDIAN) 4248 uint16_t nbds /* BDs update value */; 4249 uint8_t params; 4250 #define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0) /* BitField params reserved */ 4251 #define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0 4252 #define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5) /* BitField params BDs update doorbell opcode (2) */ 4253 #define TOE_RX_BDS_DOORBELL_OPCODE_SHIFT 5 4254 struct doorbell_hdr_t hdr; 4255#elif defined(__LITTLE_ENDIAN) 4256 struct doorbell_hdr_t hdr; 4257 uint8_t params; 4258 #define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0) /* BitField params reserved */ 4259 #define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0 4260 #define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5) /* BitField params BDs update doorbell opcode (2) */ 4261 #define TOE_RX_BDS_DOORBELL_OPCODE_SHIFT 5 4262 uint16_t nbds /* BDs update value */; 4263#endif 4264}; 4265 4266 4267/* 4268 * toe rx bytes and BDs update doorbell 4269 */ 4270struct toe_rx_bytes_and_bds_doorbell 4271{ 4272#if defined(__BIG_ENDIAN) 4273 uint16_t nbytes /* nbytes */; 4274 uint8_t params; 4275 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0) /* BitField params producer delta from the last doorbell */ 4276 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0 4277 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5) /* BitField params rx bytes and BDs update doorbell opcode (1) */ 4278 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE_SHIFT 5 4279 struct doorbell_hdr_t hdr; 4280#elif defined(__LITTLE_ENDIAN) 4281 struct doorbell_hdr_t hdr; 4282 uint8_t params; 4283 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0) /* BitField params producer delta from the last doorbell */ 4284 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0 4285 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5) /* BitField params rx bytes and BDs update doorbell opcode (1) */ 4286 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE_SHIFT 5 4287 uint16_t nbytes /* nbytes */; 4288#endif 4289}; 4290 4291 4292/* 4293 * toe rx bytes doorbell 4294 */ 4295struct toe_rx_byte_doorbell 4296{ 4297#if defined(__BIG_ENDIAN) 4298 uint16_t nbytes_lsb /* bits [0:15] of nbytes */; 4299 uint8_t params; 4300 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0) /* BitField params bits [20:16] of nbytes */ 4301 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0 4302 #define TOE_RX_BYTE_DOORBELL_OPCODE (0x7<<5) /* BitField params rx bytes doorbell opcode (0) */ 4303 #define TOE_RX_BYTE_DOORBELL_OPCODE_SHIFT 5 4304 struct doorbell_hdr_t hdr; 4305#elif defined(__LITTLE_ENDIAN) 4306 struct doorbell_hdr_t hdr; 4307 uint8_t params; 4308 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0) /* BitField params bits [20:16] of nbytes */ 4309 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0 4310 #define TOE_RX_BYTE_DOORBELL_OPCODE (0x7<<5) /* BitField params rx bytes doorbell opcode (0) */ 4311 #define TOE_RX_BYTE_DOORBELL_OPCODE_SHIFT 5 4312 uint16_t nbytes_lsb /* bits [0:15] of nbytes */; 4313#endif 4314}; 4315 4316 4317/* 4318 * toe rx consume GRQ doorbell 4319 */ 4320struct toe_rx_grq_doorbell 4321{ 4322#if defined(__BIG_ENDIAN) 4323 uint16_t nbytes_lsb /* bits [0:15] of nbytes */; 4324 uint8_t params; 4325 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0) /* BitField params bits [20:16] of nbytes */ 4326 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0 4327 #define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5) /* BitField params rx GRQ doorbell opcode (4) */ 4328 #define TOE_RX_GRQ_DOORBELL_OPCODE_SHIFT 5 4329 struct doorbell_hdr_t hdr; 4330#elif defined(__LITTLE_ENDIAN) 4331 struct doorbell_hdr_t hdr; 4332 uint8_t params; 4333 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0) /* BitField params bits [20:16] of nbytes */ 4334 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0 4335 #define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5) /* BitField params rx GRQ doorbell opcode (4) */ 4336 #define TOE_RX_GRQ_DOORBELL_OPCODE_SHIFT 5 4337 uint16_t nbytes_lsb /* bits [0:15] of nbytes */; 4338#endif 4339}; 4340 4341 4342/* 4343 * toe doorbell 4344 */ 4345struct toe_tx_doorbell 4346{ 4347#if defined(__BIG_ENDIAN) 4348 uint16_t nbytes /* number of data bytes that were added in the doorbell */; 4349 uint8_t params; 4350 #define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 4351 #define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0 4352 #define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 4353 #define TOE_TX_DOORBELL_TX_FIN_FLAG_SHIFT 6 4354 #define TOE_TX_DOORBELL_FLUSH (0x1<<7) /* BitField params doorbell queue spare flag */ 4355 #define TOE_TX_DOORBELL_FLUSH_SHIFT 7 4356 struct doorbell_hdr_t hdr; 4357#elif defined(__LITTLE_ENDIAN) 4358 struct doorbell_hdr_t hdr; 4359 uint8_t params; 4360 #define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 4361 #define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0 4362 #define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 4363 #define TOE_TX_DOORBELL_TX_FIN_FLAG_SHIFT 6 4364 #define TOE_TX_DOORBELL_FLUSH (0x1<<7) /* BitField params doorbell queue spare flag */ 4365 #define TOE_TX_DOORBELL_FLUSH_SHIFT 7 4366 uint16_t nbytes /* number of data bytes that were added in the doorbell */; 4367#endif 4368}; 4369 4370 4371/* 4372 * The eth aggregative context of Tstorm 4373 */ 4374struct tstorm_eth_ag_context 4375{ 4376 uint32_t __reserved0[14]; 4377}; 4378 4379 4380/* 4381 * The fcoe extra aggregative context section of Tstorm 4382 */ 4383struct tstorm_fcoe_extra_ag_context_section 4384{ 4385 uint32_t __agg_val1 /* aggregated value 1 */; 4386#if defined(__BIG_ENDIAN) 4387 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/; 4388 uint8_t __agg_val3 /* aggregated value 3 */; 4389 uint16_t __agg_val2 /* aggregated value 2 */; 4390#elif defined(__LITTLE_ENDIAN) 4391 uint16_t __agg_val2 /* aggregated value 2 */; 4392 uint8_t __agg_val3 /* aggregated value 3 */; 4393 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/; 4394#endif 4395#if defined(__BIG_ENDIAN) 4396 uint16_t __agg_val5; 4397 uint8_t __agg_val6; 4398 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 4399#elif defined(__LITTLE_ENDIAN) 4400 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 4401 uint8_t __agg_val6; 4402 uint16_t __agg_val5; 4403#endif 4404 uint32_t __lcq_prod /* Next sequence number to transmit, given by Tx */; 4405 uint32_t rtt_seq /* Rtt recording sequence number */; 4406 uint32_t rtt_time /* Rtt recording real time clock */; 4407 uint32_t __reserved66; 4408 uint32_t wnd_right_edge /* The right edge of the receive window. Updated by the XSTORM when a segment with ACK is transmitted */; 4409 uint32_t tcp_agg_vars1; 4410 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */ 4411 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 4412 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */ 4413 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 4414 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */ 4415 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 4416 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */ 4417 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 4418 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */ 4419 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 4420 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */ 4421 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 4422 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */ 4423 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 4424 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */ 4425 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9 4426 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */ 4427 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 4428 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */ 4429 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 4430 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */ 4431 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 4432 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */ 4433 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 4434 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */ 4435 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 4436 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */ 4437 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 4438 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */ 4439 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 4440 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */ 4441 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 4442 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */ 4443 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 4444 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */ 4445 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 4446 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */ 4447 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 4448 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */ 4449 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 4450 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */ 4451 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 4452 uint32_t snd_max /* Maximum sequence number that was ever transmitted */; 4453 uint32_t __lcq_cons /* Last ACK sequence number sent by the Tx */; 4454 uint32_t __reserved2; 4455}; 4456 4457/* 4458 * The fcoe aggregative context of Tstorm 4459 */ 4460struct tstorm_fcoe_ag_context 4461{ 4462#if defined(__BIG_ENDIAN) 4463 uint16_t ulp_credit; 4464 uint8_t agg_vars1; 4465 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 4466 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 4467 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 4468 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 4469 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 4470 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 4471 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 4472 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 4473 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */ 4474 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4 4475 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */ 4476 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 4477 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */ 4478 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 4479 uint8_t state /* The state of the connection */; 4480#elif defined(__LITTLE_ENDIAN) 4481 uint8_t state /* The state of the connection */; 4482 uint8_t agg_vars1; 4483 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 4484 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 4485 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 4486 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 4487 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 4488 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 4489 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 4490 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 4491 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */ 4492 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4 4493 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */ 4494 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 4495 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */ 4496 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 4497 uint16_t ulp_credit; 4498#endif 4499#if defined(__BIG_ENDIAN) 4500 uint16_t __agg_val4; 4501 uint16_t agg_vars2; 4502 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */ 4503 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 4504 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */ 4505 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 4506 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */ 4507 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2 4508 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */ 4509 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4 4510 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */ 4511 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6 4512 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */ 4513 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8 4514 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */ 4515 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 4516 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */ 4517 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11 4518 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */ 4519 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 4520 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */ 4521 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 4522 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */ 4523 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 4524 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */ 4525 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 4526#elif defined(__LITTLE_ENDIAN) 4527 uint16_t agg_vars2; 4528 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */ 4529 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 4530 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */ 4531 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 4532 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */ 4533 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2 4534 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */ 4535 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4 4536 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */ 4537 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6 4538 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */ 4539 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8 4540 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */ 4541 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 4542 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */ 4543 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11 4544 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */ 4545 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 4546 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */ 4547 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 4548 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */ 4549 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 4550 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */ 4551 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 4552 uint16_t __agg_val4; 4553#endif 4554 struct tstorm_fcoe_extra_ag_context_section __extra_section /* Extra context section */; 4555}; 4556 4557 4558/* 4559 * The iscsi aggregative context section of Tstorm 4560 */ 4561struct tstorm_iscsi_tcp_ag_context_section 4562{ 4563 uint32_t __agg_val1 /* aggregated value 1 */; 4564#if defined(__BIG_ENDIAN) 4565 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/; 4566 uint8_t __agg_val3 /* aggregated value 3 */; 4567 uint16_t __agg_val2 /* aggregated value 2 */; 4568#elif defined(__LITTLE_ENDIAN) 4569 uint16_t __agg_val2 /* aggregated value 2 */; 4570 uint8_t __agg_val3 /* aggregated value 3 */; 4571 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/; 4572#endif 4573#if defined(__BIG_ENDIAN) 4574 uint16_t __agg_val5; 4575 uint8_t __agg_val6; 4576 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 4577#elif defined(__LITTLE_ENDIAN) 4578 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 4579 uint8_t __agg_val6; 4580 uint16_t __agg_val5; 4581#endif 4582 uint32_t snd_nxt /* Next sequence number to transmit, given by Tx */; 4583 uint32_t rtt_seq /* Rtt recording sequence number */; 4584 uint32_t rtt_time /* Rtt recording real time clock */; 4585 uint32_t wnd_right_edge_local; 4586 uint32_t wnd_right_edge /* The right edge of the receive window. Updated by the XSTORM when a segment with ACK is transmitted */; 4587 uint32_t tcp_agg_vars1; 4588 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */ 4589 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 4590 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */ 4591 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 4592 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */ 4593 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 4594 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */ 4595 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 4596 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */ 4597 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 4598 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */ 4599 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 4600 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */ 4601 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 4602 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */ 4603 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 4604 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */ 4605 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 4606 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */ 4607 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 4608 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */ 4609 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 4610 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */ 4611 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 4612 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */ 4613 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 4614 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */ 4615 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 4616 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */ 4617 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 4618 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */ 4619 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 4620 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */ 4621 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 4622 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */ 4623 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 4624 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */ 4625 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 4626 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */ 4627 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 4628 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */ 4629 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 4630 uint32_t snd_max /* Maximum sequence number that was ever transmitted */; 4631 uint32_t snd_una /* Last ACK sequence number sent by the Tx */; 4632 uint32_t __reserved2; 4633}; 4634 4635/* 4636 * The iscsi aggregative context of Tstorm 4637 */ 4638struct tstorm_iscsi_ag_context 4639{ 4640#if defined(__BIG_ENDIAN) 4641 uint16_t ulp_credit; 4642 uint8_t agg_vars1; 4643 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 4644 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 4645 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 4646 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 4647 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 4648 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 4649 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 4650 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 4651 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */ 4652 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 4653 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */ 4654 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 4655 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */ 4656 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7 4657 uint8_t state /* The state of the connection */; 4658#elif defined(__LITTLE_ENDIAN) 4659 uint8_t state /* The state of the connection */; 4660 uint8_t agg_vars1; 4661 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 4662 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 4663 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 4664 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 4665 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 4666 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 4667 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 4668 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 4669 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */ 4670 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 4671 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */ 4672 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 4673 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */ 4674 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7 4675 uint16_t ulp_credit; 4676#endif 4677#if defined(__BIG_ENDIAN) 4678 uint16_t __agg_val4; 4679 uint16_t agg_vars2; 4680 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */ 4681 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0 4682 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */ 4683 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1 4684 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */ 4685 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2 4686 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */ 4687 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4 4688 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */ 4689 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 4690 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */ 4691 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 4692 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */ 4693 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 4694 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */ 4695 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 4696 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */ 4697 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12 4698 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */ 4699 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13 4700 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */ 4701 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 4702 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */ 4703 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 4704#elif defined(__LITTLE_ENDIAN) 4705 uint16_t agg_vars2; 4706 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */ 4707 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0 4708 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */ 4709 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1 4710 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */ 4711 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2 4712 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */ 4713 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4 4714 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */ 4715 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 4716 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */ 4717 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 4718 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */ 4719 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 4720 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */ 4721 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 4722 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */ 4723 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12 4724 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */ 4725 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13 4726 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */ 4727 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 4728 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */ 4729 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 4730 uint16_t __agg_val4; 4731#endif 4732 struct tstorm_iscsi_tcp_ag_context_section tcp /* TCP context section, shared in TOE and iSCSI */; 4733}; 4734 4735 4736/* 4737 * The tcp aggregative context section of Tstorm 4738 */ 4739struct tstorm_tcp_tcp_ag_context_section 4740{ 4741 uint32_t __agg_val1 /* aggregated value 1 */; 4742#if defined(__BIG_ENDIAN) 4743 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/; 4744 uint8_t __agg_val3 /* aggregated value 3 */; 4745 uint16_t __agg_val2 /* aggregated value 2 */; 4746#elif defined(__LITTLE_ENDIAN) 4747 uint16_t __agg_val2 /* aggregated value 2 */; 4748 uint8_t __agg_val3 /* aggregated value 3 */; 4749 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/; 4750#endif 4751#if defined(__BIG_ENDIAN) 4752 uint16_t __agg_val5; 4753 uint8_t __agg_val6; 4754 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 4755#elif defined(__LITTLE_ENDIAN) 4756 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 4757 uint8_t __agg_val6; 4758 uint16_t __agg_val5; 4759#endif 4760 uint32_t snd_nxt /* Next sequence number to transmit, given by Tx */; 4761 uint32_t rtt_seq /* Rtt recording sequence number */; 4762 uint32_t rtt_time /* Rtt recording real time clock */; 4763 uint32_t __reserved66; 4764 uint32_t wnd_right_edge /* The right edge of the receive window. Updated by the XSTORM when a segment with ACK is transmitted */; 4765 uint32_t tcp_agg_vars1; 4766 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */ 4767 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 4768 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */ 4769 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 4770 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */ 4771 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 4772 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */ 4773 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 4774 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */ 4775 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 4776 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */ 4777 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 4778 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */ 4779 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 4780 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */ 4781 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 4782 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */ 4783 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 4784 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */ 4785 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 4786 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */ 4787 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 4788 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */ 4789 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 4790 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */ 4791 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 4792 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */ 4793 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 4794 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */ 4795 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 4796 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */ 4797 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 4798 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */ 4799 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 4800 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */ 4801 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 4802 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */ 4803 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 4804 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */ 4805 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 4806 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */ 4807 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 4808 uint32_t snd_max /* Maximum sequence number that was ever transmitted */; 4809 uint32_t snd_una /* Last ACK sequence number sent by the Tx */; 4810 uint32_t __reserved2; 4811}; 4812 4813 4814/* 4815 * The toe aggregative context section of Tstorm 4816 */ 4817struct tstorm_toe_tcp_ag_context_section 4818{ 4819 uint32_t __agg_val1 /* aggregated value 1 */; 4820#if defined(__BIG_ENDIAN) 4821 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/; 4822 uint8_t __agg_val3 /* aggregated value 3 */; 4823 uint16_t __agg_val2 /* aggregated value 2 */; 4824#elif defined(__LITTLE_ENDIAN) 4825 uint16_t __agg_val2 /* aggregated value 2 */; 4826 uint8_t __agg_val3 /* aggregated value 3 */; 4827 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/; 4828#endif 4829#if defined(__BIG_ENDIAN) 4830 uint16_t __agg_val5; 4831 uint8_t __agg_val6; 4832 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 4833#elif defined(__LITTLE_ENDIAN) 4834 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 4835 uint8_t __agg_val6; 4836 uint16_t __agg_val5; 4837#endif 4838 uint32_t snd_nxt /* Next sequence number to transmit, given by Tx */; 4839 uint32_t rtt_seq /* Rtt recording sequence number */; 4840 uint32_t rtt_time /* Rtt recording real time clock */; 4841 uint32_t __reserved66; 4842 uint32_t wnd_right_edge /* The right edge of the receive window. Updated by the XSTORM when a segment with ACK is transmitted */; 4843 uint32_t tcp_agg_vars1; 4844 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */ 4845 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 4846 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */ 4847 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 4848 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52 (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */ 4849 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52_SHIFT 2 4850 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */ 4851 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 4852 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */ 4853 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN_SHIFT 6 4854 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */ 4855 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 4856 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */ 4857 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 4858 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */ 4859 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 4860 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */ 4861 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE_SHIFT 10 4862 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55 (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */ 4863 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55_SHIFT 11 4864 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */ 4865 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN_SHIFT 12 4866 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */ 4867 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN_SHIFT 13 4868 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56 (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */ 4869 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56_SHIFT 14 4870 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57 (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */ 4871 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57_SHIFT 16 4872 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */ 4873 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 4874 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */ 4875 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 4876 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */ 4877 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 4878 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */ 4879 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 4880 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */ 4881 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 4882 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */ 4883 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 4884 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */ 4885 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 4886 uint32_t snd_max /* Maximum sequence number that was ever transmitted */; 4887 uint32_t snd_una /* Last ACK sequence number sent by the Tx */; 4888 uint32_t __reserved2; 4889}; 4890 4891/* 4892 * The toe aggregative context of Tstorm 4893 */ 4894struct tstorm_toe_ag_context 4895{ 4896#if defined(__BIG_ENDIAN) 4897 uint16_t reserved54; 4898 uint8_t agg_vars1; 4899 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 4900 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 4901 #define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 4902 #define TSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 1 4903 #define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 4904 #define TSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 2 4905 #define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 4906 #define TSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 3 4907 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */ 4908 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 4909 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */ 4910 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 4911 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */ 4912 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 4913 uint8_t __state /* The state of the connection */; 4914#elif defined(__LITTLE_ENDIAN) 4915 uint8_t __state /* The state of the connection */; 4916 uint8_t agg_vars1; 4917 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 4918 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 4919 #define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 4920 #define TSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 1 4921 #define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 4922 #define TSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 2 4923 #define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 4924 #define TSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 3 4925 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */ 4926 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 4927 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */ 4928 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 4929 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */ 4930 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 4931 uint16_t reserved54; 4932#endif 4933#if defined(__BIG_ENDIAN) 4934 uint16_t __agg_val4; 4935 uint16_t agg_vars2; 4936 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */ 4937 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 4938 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */ 4939 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 4940 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */ 4941 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF_SHIFT 2 4942 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */ 4943 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF_SHIFT 4 4944 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */ 4945 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF_SHIFT 6 4946 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */ 4947 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF_SHIFT 8 4948 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */ 4949 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 4950 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */ 4951 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 4952 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */ 4953 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN_SHIFT 12 4954 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */ 4955 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN_SHIFT 13 4956 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */ 4957 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN_SHIFT 14 4958 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */ 4959 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN_SHIFT 15 4960#elif defined(__LITTLE_ENDIAN) 4961 uint16_t agg_vars2; 4962 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */ 4963 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 4964 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */ 4965 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 4966 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */ 4967 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF_SHIFT 2 4968 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */ 4969 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF_SHIFT 4 4970 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */ 4971 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF_SHIFT 6 4972 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */ 4973 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF_SHIFT 8 4974 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */ 4975 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 4976 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */ 4977 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 4978 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */ 4979 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN_SHIFT 12 4980 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */ 4981 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN_SHIFT 13 4982 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */ 4983 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN_SHIFT 14 4984 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */ 4985 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN_SHIFT 15 4986 uint16_t __agg_val4; 4987#endif 4988 struct tstorm_toe_tcp_ag_context_section tcp /* TCP context section, shared in TOE and iSCSI */; 4989}; 4990 4991 4992/* 4993 * The eth aggregative context of Ustorm 4994 */ 4995struct ustorm_eth_ag_context 4996{ 4997 uint32_t __reserved0; 4998#if defined(__BIG_ENDIAN) 4999 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 5000 uint8_t __reserved2; 5001 uint16_t __reserved1; 5002#elif defined(__LITTLE_ENDIAN) 5003 uint16_t __reserved1; 5004 uint8_t __reserved2; 5005 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 5006#endif 5007 uint32_t __reserved3[6]; 5008}; 5009 5010 5011/* 5012 * The fcoe aggregative context of Ustorm 5013 */ 5014struct ustorm_fcoe_ag_context 5015{ 5016#if defined(__BIG_ENDIAN) 5017 uint8_t __aux_counter_flags /* auxiliary counter flags*/; 5018 uint8_t agg_vars2; 5019 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) /* BitField agg_vars2various aggregation variables Set when a message was received from the Tx STORM. For future use. */ 5020 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0 5021 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) /* BitField agg_vars2various aggregation variables Set when a message was received from the Timer. */ 5022 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2 5023 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) /* BitField agg_vars2various aggregation variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5024 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 5025 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision rule of AggVal2. Used in iSCSI. Should be 0 in all other protocols */ 5026 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 5027 uint8_t agg_vars1; 5028 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 0 */ 5029 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 5030 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 1 */ 5031 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 5032 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 2 */ 5033 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 5034 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 3 */ 5035 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 5036 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) /* BitField agg_vars1various aggregation variables Indicates a valid invalidate request. Set by the CMP STORM. */ 5037 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4 5038 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* BitField agg_vars1various aggregation variables Set when a message was received from the CMP STORM. For future use. */ 5039 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6 5040 uint8_t state /* The state of the connection */; 5041#elif defined(__LITTLE_ENDIAN) 5042 uint8_t state /* The state of the connection */; 5043 uint8_t agg_vars1; 5044 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 0 */ 5045 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 5046 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 1 */ 5047 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 5048 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 2 */ 5049 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 5050 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 3 */ 5051 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 5052 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) /* BitField agg_vars1various aggregation variables Indicates a valid invalidate request. Set by the CMP STORM. */ 5053 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4 5054 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* BitField agg_vars1various aggregation variables Set when a message was received from the CMP STORM. For future use. */ 5055 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6 5056 uint8_t agg_vars2; 5057 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) /* BitField agg_vars2various aggregation variables Set when a message was received from the Tx STORM. For future use. */ 5058 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0 5059 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) /* BitField agg_vars2various aggregation variables Set when a message was received from the Timer. */ 5060 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2 5061 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) /* BitField agg_vars2various aggregation variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5062 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 5063 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision rule of AggVal2. Used in iSCSI. Should be 0 in all other protocols */ 5064 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 5065 uint8_t __aux_counter_flags /* auxiliary counter flags*/; 5066#endif 5067#if defined(__BIG_ENDIAN) 5068 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 5069 uint8_t agg_misc2; 5070 uint16_t pbf_tx_seq_ack /* Sequence number of the last sequence transmitted by PBF. */; 5071#elif defined(__LITTLE_ENDIAN) 5072 uint16_t pbf_tx_seq_ack /* Sequence number of the last sequence transmitted by PBF. */; 5073 uint8_t agg_misc2; 5074 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 5075#endif 5076 uint32_t agg_misc4; 5077#if defined(__BIG_ENDIAN) 5078 uint8_t agg_val3_th; 5079 uint8_t agg_val3; 5080 uint16_t agg_misc3; 5081#elif defined(__LITTLE_ENDIAN) 5082 uint16_t agg_misc3; 5083 uint8_t agg_val3; 5084 uint8_t agg_val3_th; 5085#endif 5086 uint32_t expired_task_id /* Timer expiration task id */; 5087 uint32_t agg_misc4_th; 5088#if defined(__BIG_ENDIAN) 5089 uint16_t cq_prod /* CQ producer updated by FW */; 5090 uint16_t cq_cons /* CQ consumer updated by driver via doorbell */; 5091#elif defined(__LITTLE_ENDIAN) 5092 uint16_t cq_cons /* CQ consumer updated by driver via doorbell */; 5093 uint16_t cq_prod /* CQ producer updated by FW */; 5094#endif 5095#if defined(__BIG_ENDIAN) 5096 uint16_t __reserved2; 5097 uint8_t decision_rules; 5098 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */ 5099 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0 5100 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */ 5101 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 5102 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules CQ negative arm indication updated via doorbell */ 5103 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6 5104 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */ 5105 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7 5106 uint8_t decision_rule_enable_bits; 5107 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5108 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0 5109 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5110 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 5111 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5112 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2 5113 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5114 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 5115 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5116 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4 5117 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The flush queues counter flag en. */ 5118 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5 5119 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5120 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 5121 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5122 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 5123#elif defined(__LITTLE_ENDIAN) 5124 uint8_t decision_rule_enable_bits; 5125 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5126 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0 5127 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5128 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 5129 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5130 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2 5131 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5132 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 5133 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5134 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4 5135 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The flush queues counter flag en. */ 5136 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5 5137 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5138 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 5139 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5140 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 5141 uint8_t decision_rules; 5142 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */ 5143 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0 5144 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */ 5145 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 5146 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules CQ negative arm indication updated via doorbell */ 5147 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6 5148 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */ 5149 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7 5150 uint16_t __reserved2; 5151#endif 5152}; 5153 5154 5155/* 5156 * The iscsi aggregative context of Ustorm 5157 */ 5158struct ustorm_iscsi_ag_context 5159{ 5160#if defined(__BIG_ENDIAN) 5161 uint8_t __aux_counter_flags /* auxiliary counter flags*/; 5162 uint8_t agg_vars2; 5163 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) /* BitField agg_vars2various aggregation variables Set when a message was received from the Tx STORM. For future use. */ 5164 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 5165 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) /* BitField agg_vars2various aggregation variables Set when a message was received from the Timer. */ 5166 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 5167 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) /* BitField agg_vars2various aggregation variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5168 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 5169 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision rule of AggVal2. Used in iSCSI. Should be 0 in all other protocols */ 5170 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 5171 uint8_t agg_vars1; 5172 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 0 */ 5173 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 5174 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 1 */ 5175 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 5176 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 2 */ 5177 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 5178 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 3 */ 5179 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 5180 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) /* BitField agg_vars1various aggregation variables Indicates a valid invalidate request. Set by the CMP STORM. */ 5181 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 5182 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* BitField agg_vars1various aggregation variables Set when a message was received from the CMP STORM. For future use. */ 5183 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 5184 uint8_t state /* The state of the connection */; 5185#elif defined(__LITTLE_ENDIAN) 5186 uint8_t state /* The state of the connection */; 5187 uint8_t agg_vars1; 5188 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 0 */ 5189 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 5190 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 1 */ 5191 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 5192 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 2 */ 5193 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 5194 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 3 */ 5195 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 5196 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) /* BitField agg_vars1various aggregation variables Indicates a valid invalidate request. Set by the CMP STORM. */ 5197 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 5198 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* BitField agg_vars1various aggregation variables Set when a message was received from the CMP STORM. For future use. */ 5199 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 5200 uint8_t agg_vars2; 5201 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) /* BitField agg_vars2various aggregation variables Set when a message was received from the Tx STORM. For future use. */ 5202 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 5203 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) /* BitField agg_vars2various aggregation variables Set when a message was received from the Timer. */ 5204 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 5205 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) /* BitField agg_vars2various aggregation variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5206 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 5207 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision rule of AggVal2. Used in iSCSI. Should be 0 in all other protocols */ 5208 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 5209 uint8_t __aux_counter_flags /* auxiliary counter flags*/; 5210#endif 5211#if defined(__BIG_ENDIAN) 5212 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 5213 uint8_t agg_misc2; 5214 uint16_t __cq_local_comp_itt_val /* The local completion ITT to complete. Set by the CMP STORM RO for USTORM. */; 5215#elif defined(__LITTLE_ENDIAN) 5216 uint16_t __cq_local_comp_itt_val /* The local completion ITT to complete. Set by the CMP STORM RO for USTORM. */; 5217 uint8_t agg_misc2; 5218 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 5219#endif 5220 uint32_t agg_misc4; 5221#if defined(__BIG_ENDIAN) 5222 uint8_t agg_val3_th; 5223 uint8_t agg_val3; 5224 uint16_t agg_misc3; 5225#elif defined(__LITTLE_ENDIAN) 5226 uint16_t agg_misc3; 5227 uint8_t agg_val3; 5228 uint8_t agg_val3_th; 5229#endif 5230 uint32_t agg_val1; 5231 uint32_t agg_misc4_th; 5232#if defined(__BIG_ENDIAN) 5233 uint16_t agg_val2_th; 5234 uint16_t agg_val2; 5235#elif defined(__LITTLE_ENDIAN) 5236 uint16_t agg_val2; 5237 uint16_t agg_val2_th; 5238#endif 5239#if defined(__BIG_ENDIAN) 5240 uint16_t __reserved2; 5241 uint8_t decision_rules; 5242 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */ 5243 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 5244 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */ 5245 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 5246 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules */ 5247 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 5248 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */ 5249 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 5250 uint8_t decision_rule_enable_bits; 5251 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5252 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 5253 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5254 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 5255 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5256 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 5257 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5258 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 5259 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The local completion counter flag enable. Enabled by USTORM at the beginning. */ 5260 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 5261 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The flush queues counter flag en. */ 5262 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 5263 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5264 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 5265 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5266 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 5267#elif defined(__LITTLE_ENDIAN) 5268 uint8_t decision_rule_enable_bits; 5269 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5270 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 5271 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5272 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 5273 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5274 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 5275 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5276 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 5277 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The local completion counter flag enable. Enabled by USTORM at the beginning. */ 5278 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 5279 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The flush queues counter flag en. */ 5280 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 5281 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5282 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 5283 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */ 5284 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 5285 uint8_t decision_rules; 5286 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */ 5287 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 5288 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */ 5289 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 5290 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules */ 5291 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 5292 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */ 5293 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 5294 uint16_t __reserved2; 5295#endif 5296}; 5297 5298 5299/* 5300 * The toe aggregative context of Ustorm 5301 */ 5302struct ustorm_toe_ag_context 5303{ 5304#if defined(__BIG_ENDIAN) 5305 uint8_t __aux_counter_flags /* auxiliary counter flags*/; 5306 uint8_t __agg_vars2 /* various aggregation variables*/; 5307 uint8_t __agg_vars1 /* various aggregation variables*/; 5308 uint8_t __state /* The state of the connection */; 5309#elif defined(__LITTLE_ENDIAN) 5310 uint8_t __state /* The state of the connection */; 5311 uint8_t __agg_vars1 /* various aggregation variables*/; 5312 uint8_t __agg_vars2 /* various aggregation variables*/; 5313 uint8_t __aux_counter_flags /* auxiliary counter flags*/; 5314#endif 5315#if defined(__BIG_ENDIAN) 5316 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 5317 uint8_t __agg_misc2; 5318 uint16_t __agg_misc1; 5319#elif defined(__LITTLE_ENDIAN) 5320 uint16_t __agg_misc1; 5321 uint8_t __agg_misc2; 5322 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 5323#endif 5324 uint32_t __agg_misc4; 5325#if defined(__BIG_ENDIAN) 5326 uint8_t __agg_val3_th; 5327 uint8_t __agg_val3; 5328 uint16_t __agg_misc3; 5329#elif defined(__LITTLE_ENDIAN) 5330 uint16_t __agg_misc3; 5331 uint8_t __agg_val3; 5332 uint8_t __agg_val3_th; 5333#endif 5334 uint32_t driver_doorbell_info_ptr_lo /* the host pointer that consist the struct of info updated */; 5335 uint32_t driver_doorbell_info_ptr_hi /* the host pointer that consist the struct of info updated */; 5336#if defined(__BIG_ENDIAN) 5337 uint16_t __agg_val2_th; 5338 uint16_t rq_prod /* The RQ producer */; 5339#elif defined(__LITTLE_ENDIAN) 5340 uint16_t rq_prod /* The RQ producer */; 5341 uint16_t __agg_val2_th; 5342#endif 5343#if defined(__BIG_ENDIAN) 5344 uint16_t __reserved2; 5345 uint8_t decision_rules; 5346 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */ 5347 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 5348 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */ 5349 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 5350 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules */ 5351 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 5352 #define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */ 5353 #define __USTORM_TOE_AG_CONTEXT_RESERVED1_SHIFT 7 5354 uint8_t __decision_rule_enable_bits /* Enable bits for various decision rules*/; 5355#elif defined(__LITTLE_ENDIAN) 5356 uint8_t __decision_rule_enable_bits /* Enable bits for various decision rules*/; 5357 uint8_t decision_rules; 5358 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */ 5359 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 5360 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */ 5361 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 5362 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules */ 5363 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 5364 #define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */ 5365 #define __USTORM_TOE_AG_CONTEXT_RESERVED1_SHIFT 7 5366 uint16_t __reserved2; 5367#endif 5368}; 5369 5370 5371/* 5372 * The eth aggregative context of Xstorm 5373 */ 5374struct xstorm_eth_ag_context 5375{ 5376 uint32_t reserved0; 5377#if defined(__BIG_ENDIAN) 5378 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 5379 uint8_t reserved2; 5380 uint16_t reserved1; 5381#elif defined(__LITTLE_ENDIAN) 5382 uint16_t reserved1; 5383 uint8_t reserved2; 5384 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 5385#endif 5386 uint32_t reserved3[30]; 5387}; 5388 5389 5390/* 5391 * The fcoe aggregative context section of Xstorm 5392 */ 5393struct xstorm_fcoe_extra_ag_context_section 5394{ 5395#if defined(__BIG_ENDIAN) 5396 uint8_t tcp_agg_vars1; 5397 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */ 5398 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0 5399 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */ 5400 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 5401 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */ 5402 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 5403 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */ 5404 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6 5405 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */ 5406 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7 5407 uint8_t __reserved_da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */; 5408 uint16_t __mtu /* MSS used for nagle algorithm and for transmission */; 5409#elif defined(__LITTLE_ENDIAN) 5410 uint16_t __mtu /* MSS used for nagle algorithm and for transmission */; 5411 uint8_t __reserved_da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */; 5412 uint8_t tcp_agg_vars1; 5413 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */ 5414 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0 5415 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */ 5416 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 5417 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */ 5418 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 5419 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */ 5420 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6 5421 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */ 5422 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7 5423#endif 5424 uint32_t snd_nxt /* The current sequence number to send */; 5425 uint32_t __xfrqe_bd_addr_lo /* The Current transmission window in bytes */; 5426 uint32_t __xfrqe_bd_addr_hi /* The current Send UNA sequence number */; 5427 uint32_t __xfrqe_data1 /* The current local advertised window to FE. */; 5428#if defined(__BIG_ENDIAN) 5429 uint8_t __agg_val8_th /* aggregated value 8 - threshold */; 5430 uint8_t __tx_dest /* aggregated value 8 */; 5431 uint16_t tcp_agg_vars2; 5432 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */ 5433 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0 5434 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */ 5435 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1 5436 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */ 5437 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2 5438 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */ 5439 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 5440 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */ 5441 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 5442 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */ 5443 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5 5444 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */ 5445 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6 5446 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */ 5447 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 5448 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */ 5449 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8 5450 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */ 5451 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 5452 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */ 5453 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 5454 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */ 5455 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 5456 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */ 5457 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 5458#elif defined(__LITTLE_ENDIAN) 5459 uint16_t tcp_agg_vars2; 5460 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */ 5461 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0 5462 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */ 5463 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1 5464 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */ 5465 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2 5466 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */ 5467 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 5468 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */ 5469 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 5470 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */ 5471 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5 5472 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */ 5473 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6 5474 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */ 5475 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 5476 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */ 5477 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8 5478 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */ 5479 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 5480 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */ 5481 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 5482 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */ 5483 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 5484 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */ 5485 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 5486 uint8_t __tx_dest /* aggregated value 8 */; 5487 uint8_t __agg_val8_th /* aggregated value 8 - threshold */; 5488#endif 5489 uint32_t __sq_base_addr_lo /* The low page address which the SQ resides in host memory */; 5490 uint32_t __sq_base_addr_hi /* The high page address which the SQ resides in host memory */; 5491 uint32_t __xfrq_base_addr_lo /* The low page address which the XFRQ resides in host memory */; 5492 uint32_t __xfrq_base_addr_hi /* The high page address which the XFRQ resides in host memory */; 5493#if defined(__BIG_ENDIAN) 5494 uint16_t __xfrq_cons /* The XFRQ consumer */; 5495 uint16_t __xfrq_prod /* The XFRQ producer, updated by Ustorm */; 5496#elif defined(__LITTLE_ENDIAN) 5497 uint16_t __xfrq_prod /* The XFRQ producer, updated by Ustorm */; 5498 uint16_t __xfrq_cons /* The XFRQ consumer */; 5499#endif 5500#if defined(__BIG_ENDIAN) 5501 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/; 5502 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/; 5503 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 5504 uint8_t __reserved_force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */; 5505#elif defined(__LITTLE_ENDIAN) 5506 uint8_t __reserved_force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */; 5507 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 5508 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/; 5509 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/; 5510#endif 5511 uint32_t __tcp_agg_vars6 /* Various aggregative variables*/; 5512#if defined(__BIG_ENDIAN) 5513 uint16_t __xfrqe_mng /* Misc aggregated variable 6 */; 5514 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/; 5515#elif defined(__LITTLE_ENDIAN) 5516 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/; 5517 uint16_t __xfrqe_mng /* Misc aggregated variable 6 */; 5518#endif 5519 uint32_t __xfrqe_data0 /* aggregated value 10 */; 5520 uint32_t __agg_val10_th /* aggregated value 10 - threshold */; 5521#if defined(__BIG_ENDIAN) 5522 uint16_t __reserved3; 5523 uint8_t __reserved2; 5524 uint8_t __da_only_cnt /* counts delayed acks and not window updates */; 5525#elif defined(__LITTLE_ENDIAN) 5526 uint8_t __da_only_cnt /* counts delayed acks and not window updates */; 5527 uint8_t __reserved2; 5528 uint16_t __reserved3; 5529#endif 5530}; 5531 5532/* 5533 * The fcoe aggregative context of Xstorm 5534 */ 5535struct xstorm_fcoe_ag_context 5536{ 5537#if defined(__BIG_ENDIAN) 5538 uint16_t agg_val1 /* aggregated value 1 */; 5539 uint8_t agg_vars1; 5540 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 5541 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 5542 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 5543 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 5544 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 5545 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2 5546 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 5547 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3 5548 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */ 5549 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 5550 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */ 5551 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 5552 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables Used for future indication by the Driver on a doorbell */ 5553 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 5554 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */ 5555 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7 5556 uint8_t __state /* The state of the connection */; 5557#elif defined(__LITTLE_ENDIAN) 5558 uint8_t __state /* The state of the connection */; 5559 uint8_t agg_vars1; 5560 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 5561 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 5562 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 5563 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 5564 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 5565 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2 5566 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 5567 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3 5568 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */ 5569 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 5570 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */ 5571 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 5572 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables Used for future indication by the Driver on a doorbell */ 5573 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 5574 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */ 5575 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7 5576 uint16_t agg_val1 /* aggregated value 1 */; 5577#endif 5578#if defined(__BIG_ENDIAN) 5579 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 5580 uint8_t __agg_vars4 /* Various aggregative variables*/; 5581 uint8_t agg_vars3; 5582 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */ 5583 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 5584 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */ 5585 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6 5586 uint8_t agg_vars2; 5587 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */ 5588 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0 5589 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */ 5590 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 5591 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */ 5592 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 5593 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */ 5594 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 5595 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5596 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5 5597 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */ 5598 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 5599#elif defined(__LITTLE_ENDIAN) 5600 uint8_t agg_vars2; 5601 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */ 5602 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0 5603 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */ 5604 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 5605 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */ 5606 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 5607 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */ 5608 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 5609 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5610 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5 5611 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */ 5612 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 5613 uint8_t agg_vars3; 5614 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */ 5615 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 5616 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */ 5617 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6 5618 uint8_t __agg_vars4 /* Various aggregative variables*/; 5619 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 5620#endif 5621 uint32_t more_to_send /* The number of bytes left to send */; 5622#if defined(__BIG_ENDIAN) 5623 uint16_t agg_vars5; 5624 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5625 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0 5626 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */ 5627 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 5628 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */ 5629 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 5630 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5631 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14 5632 uint16_t sq_cons /* The SQ consumer updated by Xstorm after consuming aother WQE */; 5633#elif defined(__LITTLE_ENDIAN) 5634 uint16_t sq_cons /* The SQ consumer updated by Xstorm after consuming aother WQE */; 5635 uint16_t agg_vars5; 5636 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5637 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0 5638 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */ 5639 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 5640 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */ 5641 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 5642 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5643 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14 5644#endif 5645 struct xstorm_fcoe_extra_ag_context_section __extra_section /* Extra context section */; 5646#if defined(__BIG_ENDIAN) 5647 uint16_t agg_vars7; 5648 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5649 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 5650 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* BitField agg_vars7Various aggregative variables auxiliary flag 13 */ 5651 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3 5652 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 18 */ 5653 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4 5654 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5655 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6 5656 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 1 */ 5657 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8 5658 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) /* BitField agg_vars7Various aggregative variables Mask the check of the completion sequence on retransmit */ 5659 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10 5660 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* BitField agg_vars7Various aggregative variables Enable decision rules based on aux1_cf */ 5661 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 5662 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* BitField agg_vars7Various aggregative variables auxiliary flag 10 */ 5663 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12 5664 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* BitField agg_vars7Various aggregative variables auxiliary flag 11 */ 5665 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13 5666 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* BitField agg_vars7Various aggregative variables auxiliary flag 12 */ 5667 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14 5668 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) /* BitField agg_vars7Various aggregative variables auxiliary flag 2 */ 5669 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15 5670 uint8_t agg_val3_th /* Aggregated value 3 - threshold */; 5671 uint8_t agg_vars6; 5672 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5673 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0 5674 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5675 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3 5676 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5677 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6 5678#elif defined(__LITTLE_ENDIAN) 5679 uint8_t agg_vars6; 5680 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5681 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0 5682 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5683 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3 5684 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5685 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6 5686 uint8_t agg_val3_th /* Aggregated value 3 - threshold */; 5687 uint16_t agg_vars7; 5688 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 5689 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 5690 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* BitField agg_vars7Various aggregative variables auxiliary flag 13 */ 5691 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3 5692 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 18 */ 5693 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4 5694 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 5695 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6 5696 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 1 */ 5697 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8 5698 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) /* BitField agg_vars7Various aggregative variables Mask the check of the completion sequence on retransmit */ 5699 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10 5700 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* BitField agg_vars7Various aggregative variables Enable decision rules based on aux1_cf */ 5701 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 5702 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* BitField agg_vars7Various aggregative variables auxiliary flag 10 */ 5703 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12 5704 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* BitField agg_vars7Various aggregative variables auxiliary flag 11 */ 5705 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13 5706 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* BitField agg_vars7Various aggregative variables auxiliary flag 12 */ 5707 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14 5708 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) /* BitField agg_vars7Various aggregative variables auxiliary flag 2 */ 5709 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15 5710#endif 5711#if defined(__BIG_ENDIAN) 5712 uint16_t __agg_val11_th /* aggregated value 11 - threshold */; 5713 uint16_t __agg_val11 /* aggregated value 11 */; 5714#elif defined(__LITTLE_ENDIAN) 5715 uint16_t __agg_val11 /* aggregated value 11 */; 5716 uint16_t __agg_val11_th /* aggregated value 11 - threshold */; 5717#endif 5718#if defined(__BIG_ENDIAN) 5719 uint8_t __reserved1; 5720 uint8_t __agg_val6_th /* aggregated value 6 - threshold */; 5721 uint16_t __agg_val9 /* aggregated value 9 */; 5722#elif defined(__LITTLE_ENDIAN) 5723 uint16_t __agg_val9 /* aggregated value 9 */; 5724 uint8_t __agg_val6_th /* aggregated value 6 - threshold */; 5725 uint8_t __reserved1; 5726#endif 5727#if defined(__BIG_ENDIAN) 5728 uint16_t confq_cons /* CONFQ Consumer */; 5729 uint16_t confq_prod /* CONFQ Producer, updated by Ustorm - AggVal2 */; 5730#elif defined(__LITTLE_ENDIAN) 5731 uint16_t confq_prod /* CONFQ Producer, updated by Ustorm - AggVal2 */; 5732 uint16_t confq_cons /* CONFQ Consumer */; 5733#endif 5734 uint32_t agg_varint8_t; 5735 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 2 */ 5736 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0 5737 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 3 */ 5738 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24 5739#if defined(__BIG_ENDIAN) 5740 uint16_t __cache_wqe_db /* Misc aggregated variable 0 */; 5741 uint16_t sq_prod /* The SQ Producer updated by Xstorm after reading a bunch of WQEs into the context */; 5742#elif defined(__LITTLE_ENDIAN) 5743 uint16_t sq_prod /* The SQ Producer updated by Xstorm after reading a bunch of WQEs into the context */; 5744 uint16_t __cache_wqe_db /* Misc aggregated variable 0 */; 5745#endif 5746#if defined(__BIG_ENDIAN) 5747 uint8_t agg_val3 /* Aggregated value 3 */; 5748 uint8_t agg_val6 /* Aggregated value 6 */; 5749 uint8_t agg_val5_th /* Aggregated value 5 - threshold */; 5750 uint8_t agg_val5 /* Aggregated value 5 */; 5751#elif defined(__LITTLE_ENDIAN) 5752 uint8_t agg_val5 /* Aggregated value 5 */; 5753 uint8_t agg_val5_th /* Aggregated value 5 - threshold */; 5754 uint8_t agg_val6 /* Aggregated value 6 */; 5755 uint8_t agg_val3 /* Aggregated value 3 */; 5756#endif 5757#if defined(__BIG_ENDIAN) 5758 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */; 5759 uint16_t agg_limit1 /* aggregated limit 1 */; 5760#elif defined(__LITTLE_ENDIAN) 5761 uint16_t agg_limit1 /* aggregated limit 1 */; 5762 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */; 5763#endif 5764 uint32_t completion_seq /* The sequence number of the start completion point (BD) */; 5765 uint32_t confq_pbl_base_lo /* The CONFQ PBL base low address resides in host memory */; 5766 uint32_t confq_pbl_base_hi /* The CONFQ PBL base hihj address resides in host memory */; 5767}; 5768 5769 5770/* 5771 * The tcp aggregative context section of Xstorm 5772 */ 5773struct xstorm_tcp_tcp_ag_context_section 5774{ 5775#if defined(__BIG_ENDIAN) 5776 uint8_t tcp_agg_vars1; 5777 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */ 5778 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0 5779 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */ 5780 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 5781 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */ 5782 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 5783 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */ 5784 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6 5785 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */ 5786 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7 5787 uint8_t __da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */; 5788 uint16_t mss /* MSS used for nagle algorithm and for transmission */; 5789#elif defined(__LITTLE_ENDIAN) 5790 uint16_t mss /* MSS used for nagle algorithm and for transmission */; 5791 uint8_t __da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */; 5792 uint8_t tcp_agg_vars1; 5793 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */ 5794 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0 5795 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */ 5796 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 5797 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */ 5798 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 5799 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */ 5800 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6 5801 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */ 5802 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7 5803#endif 5804 uint32_t snd_nxt /* The current sequence number to send */; 5805 uint32_t tx_wnd /* The Current transmission window in bytes */; 5806 uint32_t snd_una /* The current Send UNA sequence number */; 5807 uint32_t local_adv_wnd /* The current local advertised window to FE. */; 5808#if defined(__BIG_ENDIAN) 5809 uint8_t __agg_val8_th /* aggregated value 8 - threshold */; 5810 uint8_t __tx_dest /* aggregated value 8 */; 5811 uint16_t tcp_agg_vars2; 5812 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */ 5813 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 5814 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */ 5815 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 5816 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */ 5817 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 5818 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */ 5819 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 5820 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */ 5821 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 5822 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */ 5823 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 5824 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */ 5825 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 5826 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */ 5827 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 5828 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */ 5829 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 5830 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */ 5831 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 5832 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */ 5833 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 5834 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */ 5835 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 5836 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */ 5837 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 5838#elif defined(__LITTLE_ENDIAN) 5839 uint16_t tcp_agg_vars2; 5840 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */ 5841 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 5842 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */ 5843 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 5844 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */ 5845 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 5846 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */ 5847 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 5848 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */ 5849 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 5850 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */ 5851 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 5852 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */ 5853 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 5854 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */ 5855 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 5856 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */ 5857 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 5858 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */ 5859 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 5860 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */ 5861 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 5862 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */ 5863 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 5864 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */ 5865 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 5866 uint8_t __tx_dest /* aggregated value 8 */; 5867 uint8_t __agg_val8_th /* aggregated value 8 - threshold */; 5868#endif 5869 uint32_t ack_to_far_end /* The ACK sequence to send to far end */; 5870 uint32_t rto_timer /* The RTO timer value */; 5871 uint32_t ka_timer /* The KA timer value */; 5872 uint32_t ts_to_echo /* The time stamp value to echo to far end */; 5873#if defined(__BIG_ENDIAN) 5874 uint16_t __agg_val7_th /* aggregated value 7 - threshold */; 5875 uint16_t __agg_val7 /* aggregated value 7 */; 5876#elif defined(__LITTLE_ENDIAN) 5877 uint16_t __agg_val7 /* aggregated value 7 */; 5878 uint16_t __agg_val7_th /* aggregated value 7 - threshold */; 5879#endif 5880#if defined(__BIG_ENDIAN) 5881 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/; 5882 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/; 5883 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 5884 uint8_t __force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */; 5885#elif defined(__LITTLE_ENDIAN) 5886 uint8_t __force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */; 5887 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 5888 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/; 5889 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/; 5890#endif 5891 uint32_t tcp_agg_vars6; 5892 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux7_cf */ 5893 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0 5894 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux8_cf */ 5895 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1 5896 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux9_cf */ 5897 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2 5898 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux10_cf */ 5899 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3 5900 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 6 */ 5901 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4 5902 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 7 */ 5903 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5 5904 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 5 */ 5905 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6 5906 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 9 */ 5907 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8 5908 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 10 */ 5909 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10 5910 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 11 */ 5911 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12 5912 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 12 */ 5913 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14 5914 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 13 */ 5915 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16 5916 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 14 */ 5917 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18 5918 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 15 */ 5919 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20 5920 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 16 */ 5921 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22 5922 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 17 */ 5923 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24 5924 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */ 5925 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26 5926 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */ 5927 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27 5928 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) /* BitField tcp_agg_vars6Various aggregative variables This flag is set if the Force ACK count is set by the TSTORM. On QM output it is cleared. */ 5929 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28 5930 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) /* BitField tcp_agg_vars6Various aggregative variables Indicates that the connection is in autostop mode */ 5931 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29 5932 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) /* BitField tcp_agg_vars6Various aggregative variables This bit uses like a one shot that the TSTORM fires and the XSTORM arms. Used to allow a single TS update for each transmission */ 5933 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30 5934 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) /* BitField tcp_agg_vars6Various aggregative variables This bit is set by the TSTORM when need to cancel precious fast retransmit */ 5935 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31 5936#if defined(__BIG_ENDIAN) 5937 uint16_t __agg_misc6 /* Misc aggregated variable 6 */; 5938 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/; 5939#elif defined(__LITTLE_ENDIAN) 5940 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/; 5941 uint16_t __agg_misc6 /* Misc aggregated variable 6 */; 5942#endif 5943 uint32_t __agg_val10 /* aggregated value 10 */; 5944 uint32_t __agg_val10_th /* aggregated value 10 - threshold */; 5945#if defined(__BIG_ENDIAN) 5946 uint16_t __reserved3; 5947 uint8_t __reserved2; 5948 uint8_t __da_only_cnt /* counts delayed acks and not window updates */; 5949#elif defined(__LITTLE_ENDIAN) 5950 uint8_t __da_only_cnt /* counts delayed acks and not window updates */; 5951 uint8_t __reserved2; 5952 uint16_t __reserved3; 5953#endif 5954}; 5955 5956/* 5957 * The iscsi aggregative context of Xstorm 5958 */ 5959struct xstorm_iscsi_ag_context 5960{ 5961#if defined(__BIG_ENDIAN) 5962 uint16_t agg_val1 /* aggregated value 1 */; 5963 uint8_t agg_vars1; 5964 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 5965 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 5966 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 5967 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 5968 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 5969 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 5970 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 5971 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 5972 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */ 5973 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 5974 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */ 5975 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 5976 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables Used for future indication by the Driver on a doorbell */ 5977 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 5978 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */ 5979 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 5980 uint8_t state /* The state of the connection */; 5981#elif defined(__LITTLE_ENDIAN) 5982 uint8_t state /* The state of the connection */; 5983 uint8_t agg_vars1; 5984 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 5985 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 5986 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 5987 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 5988 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 5989 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 5990 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 5991 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 5992 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */ 5993 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 5994 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */ 5995 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 5996 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables Used for future indication by the Driver on a doorbell */ 5997 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 5998 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */ 5999 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 6000 uint16_t agg_val1 /* aggregated value 1 */; 6001#endif 6002#if defined(__BIG_ENDIAN) 6003 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 6004 uint8_t __agg_vars4 /* Various aggregative variables*/; 6005 uint8_t agg_vars3; 6006 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */ 6007 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 6008 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */ 6009 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 6010 uint8_t agg_vars2; 6011 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */ 6012 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 6013 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */ 6014 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 6015 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */ 6016 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 6017 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */ 6018 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 6019 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6020 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 6021 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */ 6022 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 6023#elif defined(__LITTLE_ENDIAN) 6024 uint8_t agg_vars2; 6025 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */ 6026 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 6027 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */ 6028 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 6029 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */ 6030 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 6031 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */ 6032 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 6033 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6034 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 6035 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */ 6036 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 6037 uint8_t agg_vars3; 6038 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */ 6039 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 6040 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */ 6041 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 6042 uint8_t __agg_vars4 /* Various aggregative variables*/; 6043 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 6044#endif 6045 uint32_t more_to_send /* The number of bytes left to send */; 6046#if defined(__BIG_ENDIAN) 6047 uint16_t agg_vars5; 6048 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6049 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 6050 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */ 6051 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 6052 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */ 6053 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 6054 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6055 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 6056 uint16_t sq_cons /* aggregated value 4 - threshold */; 6057#elif defined(__LITTLE_ENDIAN) 6058 uint16_t sq_cons /* aggregated value 4 - threshold */; 6059 uint16_t agg_vars5; 6060 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6061 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 6062 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */ 6063 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 6064 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */ 6065 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 6066 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6067 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 6068#endif 6069 struct xstorm_tcp_tcp_ag_context_section tcp /* TCP context section, shared in TOE and ISCSI */; 6070#if defined(__BIG_ENDIAN) 6071 uint16_t agg_vars7; 6072 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 6073 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 6074 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* BitField agg_vars7Various aggregative variables auxiliary flag 13 */ 6075 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 6076 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) /* BitField agg_vars7Various aggregative variables Sync Tstorm and Xstorm */ 6077 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 6078 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6079 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 6080 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 1 */ 6081 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 6082 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) /* BitField agg_vars7Various aggregative variables Mask the check of the completion sequence on retransmit */ 6083 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 6084 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* BitField agg_vars7Various aggregative variables Enable decision rules based on aux1_cf */ 6085 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 6086 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* BitField agg_vars7Various aggregative variables auxiliary flag 10 */ 6087 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 6088 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* BitField agg_vars7Various aggregative variables auxiliary flag 11 */ 6089 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 6090 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* BitField agg_vars7Various aggregative variables auxiliary flag 12 */ 6091 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 6092 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) /* BitField agg_vars7Various aggregative variables auxiliary flag 2 */ 6093 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 6094 uint8_t agg_val3_th /* Aggregated value 3 - threshold */; 6095 uint8_t agg_vars6; 6096 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 6097 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 6098 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 6099 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 6100 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6101 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 6102#elif defined(__LITTLE_ENDIAN) 6103 uint8_t agg_vars6; 6104 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 6105 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 6106 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 6107 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 6108 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6109 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 6110 uint8_t agg_val3_th /* Aggregated value 3 - threshold */; 6111 uint16_t agg_vars7; 6112 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */ 6113 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 6114 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* BitField agg_vars7Various aggregative variables auxiliary flag 13 */ 6115 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 6116 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) /* BitField agg_vars7Various aggregative variables Sync Tstorm and Xstorm */ 6117 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 6118 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6119 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 6120 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 1 */ 6121 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 6122 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) /* BitField agg_vars7Various aggregative variables Mask the check of the completion sequence on retransmit */ 6123 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 6124 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* BitField agg_vars7Various aggregative variables Enable decision rules based on aux1_cf */ 6125 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 6126 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* BitField agg_vars7Various aggregative variables auxiliary flag 10 */ 6127 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 6128 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* BitField agg_vars7Various aggregative variables auxiliary flag 11 */ 6129 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 6130 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* BitField agg_vars7Various aggregative variables auxiliary flag 12 */ 6131 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 6132 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) /* BitField agg_vars7Various aggregative variables auxiliary flag 2 */ 6133 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 6134#endif 6135#if defined(__BIG_ENDIAN) 6136 uint16_t __agg_val11_th /* aggregated value 11 - threshold */; 6137 uint16_t __gen_data /* Used for Iscsi. In connection establishment, it uses as rxMss, and in connection termination, it uses as command Id: 1=L5CM_TX_ACK_ON_FIN_CMD 2=L5CM_SET_MSL_TIMER_CMD 3=L5CM_TX_RST_CMD */; 6138#elif defined(__LITTLE_ENDIAN) 6139 uint16_t __gen_data /* Used for Iscsi. In connection establishment, it uses as rxMss, and in connection termination, it uses as command Id: 1=L5CM_TX_ACK_ON_FIN_CMD 2=L5CM_SET_MSL_TIMER_CMD 3=L5CM_TX_RST_CMD */; 6140 uint16_t __agg_val11_th /* aggregated value 11 - threshold */; 6141#endif 6142#if defined(__BIG_ENDIAN) 6143 uint8_t __reserved1; 6144 uint8_t __agg_val6_th /* aggregated value 6 - threshold */; 6145 uint16_t __agg_val9 /* aggregated value 9 */; 6146#elif defined(__LITTLE_ENDIAN) 6147 uint16_t __agg_val9 /* aggregated value 9 */; 6148 uint8_t __agg_val6_th /* aggregated value 6 - threshold */; 6149 uint8_t __reserved1; 6150#endif 6151#if defined(__BIG_ENDIAN) 6152 uint16_t hq_prod /* The HQ producer threashold to compare the HQ consumer, which is the current HQ producer +1 - AggVal2Th */; 6153 uint16_t hq_cons /* HQ Consumer, updated by Cstorm - AggVal2 */; 6154#elif defined(__LITTLE_ENDIAN) 6155 uint16_t hq_cons /* HQ Consumer, updated by Cstorm - AggVal2 */; 6156 uint16_t hq_prod /* The HQ producer threashold to compare the HQ consumer, which is the current HQ producer +1 - AggVal2Th */; 6157#endif 6158 uint32_t agg_varint8_t; 6159 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 2 */ 6160 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0 6161 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 3 */ 6162 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24 6163#if defined(__BIG_ENDIAN) 6164 uint16_t r2tq_prod /* Misc aggregated variable 0 */; 6165 uint16_t sq_prod /* SQ Producer */; 6166#elif defined(__LITTLE_ENDIAN) 6167 uint16_t sq_prod /* SQ Producer */; 6168 uint16_t r2tq_prod /* Misc aggregated variable 0 */; 6169#endif 6170#if defined(__BIG_ENDIAN) 6171 uint8_t agg_val3 /* Aggregated value 3 */; 6172 uint8_t agg_val6 /* Aggregated value 6 */; 6173 uint8_t agg_val5_th /* Aggregated value 5 - threshold */; 6174 uint8_t agg_val5 /* Aggregated value 5 */; 6175#elif defined(__LITTLE_ENDIAN) 6176 uint8_t agg_val5 /* Aggregated value 5 */; 6177 uint8_t agg_val5_th /* Aggregated value 5 - threshold */; 6178 uint8_t agg_val6 /* Aggregated value 6 */; 6179 uint8_t agg_val3 /* Aggregated value 3 */; 6180#endif 6181#if defined(__BIG_ENDIAN) 6182 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */; 6183 uint16_t agg_limit1 /* aggregated limit 1 */; 6184#elif defined(__LITTLE_ENDIAN) 6185 uint16_t agg_limit1 /* aggregated limit 1 */; 6186 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */; 6187#endif 6188 uint32_t hq_cons_tcp_seq /* TCP sequence of the HQ BD pointed by hq_cons */; 6189 uint32_t exp_stat_sn /* expected status SN, updated by Ustorm */; 6190 uint32_t rst_seq_num /* spare aggregated variable 5 */; 6191}; 6192 6193 6194/* 6195 * The toe aggregative context section of Xstorm 6196 */ 6197struct xstorm_toe_tcp_ag_context_section 6198{ 6199#if defined(__BIG_ENDIAN) 6200 uint8_t tcp_agg_vars1; 6201 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */ 6202 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0 6203 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */ 6204 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 6205 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */ 6206 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 6207 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */ 6208 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6 6209 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */ 6210 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7 6211 uint8_t __da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */; 6212 uint16_t mss /* MSS used for nagle algorithm and for transmission */; 6213#elif defined(__LITTLE_ENDIAN) 6214 uint16_t mss /* MSS used for nagle algorithm and for transmission */; 6215 uint8_t __da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */; 6216 uint8_t tcp_agg_vars1; 6217 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */ 6218 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0 6219 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */ 6220 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 6221 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */ 6222 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 6223 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */ 6224 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6 6225 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */ 6226 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7 6227#endif 6228 uint32_t snd_nxt /* The current sequence number to send */; 6229 uint32_t tx_wnd /* The Current transmission window in bytes */; 6230 uint32_t snd_una /* The current Send UNA sequence number */; 6231 uint32_t local_adv_wnd /* The current local advertised window to FE. */; 6232#if defined(__BIG_ENDIAN) 6233 uint8_t __agg_val8_th /* aggregated value 8 - threshold */; 6234 uint8_t __tx_dest /* aggregated value 8 */; 6235 uint16_t tcp_agg_vars2; 6236 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */ 6237 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 6238 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */ 6239 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 6240 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */ 6241 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 6242 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */ 6243 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 6244 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */ 6245 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 6246 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */ 6247 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 6248 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */ 6249 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 6250 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */ 6251 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 6252 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */ 6253 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 6254 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */ 6255 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 6256 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */ 6257 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 6258 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */ 6259 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 6260 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */ 6261 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 6262#elif defined(__LITTLE_ENDIAN) 6263 uint16_t tcp_agg_vars2; 6264 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */ 6265 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 6266 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */ 6267 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 6268 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */ 6269 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 6270 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */ 6271 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 6272 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */ 6273 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 6274 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */ 6275 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 6276 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */ 6277 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 6278 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */ 6279 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 6280 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */ 6281 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 6282 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */ 6283 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 6284 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */ 6285 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 6286 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */ 6287 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 6288 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */ 6289 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 6290 uint8_t __tx_dest /* aggregated value 8 */; 6291 uint8_t __agg_val8_th /* aggregated value 8 - threshold */; 6292#endif 6293 uint32_t ack_to_far_end /* The ACK sequence to send to far end */; 6294 uint32_t rto_timer /* The RTO timer value */; 6295 uint32_t ka_timer /* The KA timer value */; 6296 uint32_t ts_to_echo /* The time stamp value to echo to far end */; 6297#if defined(__BIG_ENDIAN) 6298 uint16_t __agg_val7_th /* aggregated value 7 - threshold */; 6299 uint16_t __agg_val7 /* aggregated value 7 */; 6300#elif defined(__LITTLE_ENDIAN) 6301 uint16_t __agg_val7 /* aggregated value 7 */; 6302 uint16_t __agg_val7_th /* aggregated value 7 - threshold */; 6303#endif 6304#if defined(__BIG_ENDIAN) 6305 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/; 6306 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/; 6307 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 6308 uint8_t __force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */; 6309#elif defined(__LITTLE_ENDIAN) 6310 uint8_t __force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */; 6311 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/; 6312 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/; 6313 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/; 6314#endif 6315 uint32_t tcp_agg_vars6; 6316 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux7_cf */ 6317 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0 6318 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux8_cf */ 6319 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1 6320 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux9_cf */ 6321 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2 6322 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux10_cf */ 6323 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3 6324 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 6 */ 6325 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4 6326 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 7 */ 6327 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5 6328 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 5 */ 6329 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6 6330 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 9 */ 6331 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8 6332 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 10 */ 6333 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10 6334 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 11 */ 6335 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12 6336 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 12 */ 6337 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14 6338 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 13 */ 6339 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16 6340 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 14 */ 6341 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18 6342 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 15 */ 6343 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20 6344 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 16 */ 6345 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22 6346 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 17 */ 6347 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24 6348 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */ 6349 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26 6350 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */ 6351 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27 6352 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) /* BitField tcp_agg_vars6Various aggregative variables This flag is set if the Force ACK count is set by the TSTORM. On QM output it is cleared. */ 6353 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28 6354 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) /* BitField tcp_agg_vars6Various aggregative variables Indicates that the connection is in autostop mode */ 6355 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29 6356 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) /* BitField tcp_agg_vars6Various aggregative variables This bit uses like a one shot that the TSTORM fires and the XSTORM arms. Used to allow a single TS update for each transmission */ 6357 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30 6358 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) /* BitField tcp_agg_vars6Various aggregative variables This bit is set by the TSTORM when need to cancel precious fast retransmit */ 6359 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31 6360#if defined(__BIG_ENDIAN) 6361 uint16_t __agg_misc6 /* Misc aggregated variable 6 */; 6362 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/; 6363#elif defined(__LITTLE_ENDIAN) 6364 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/; 6365 uint16_t __agg_misc6 /* Misc aggregated variable 6 */; 6366#endif 6367 uint32_t __agg_val10 /* aggregated value 10 */; 6368 uint32_t __agg_val10_th /* aggregated value 10 - threshold */; 6369#if defined(__BIG_ENDIAN) 6370 uint16_t __reserved3; 6371 uint8_t __reserved2; 6372 uint8_t __da_only_cnt /* counts delayed acks and not window updates */; 6373#elif defined(__LITTLE_ENDIAN) 6374 uint8_t __da_only_cnt /* counts delayed acks and not window updates */; 6375 uint8_t __reserved2; 6376 uint16_t __reserved3; 6377#endif 6378}; 6379 6380/* 6381 * The toe aggregative context of Xstorm 6382 */ 6383struct xstorm_toe_ag_context 6384{ 6385#if defined(__BIG_ENDIAN) 6386 uint16_t agg_val1 /* aggregated value 1 */; 6387 uint8_t agg_vars1; 6388 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 6389 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 6390 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 6391 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50_SHIFT 1 6392 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 6393 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 2 6394 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 6395 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 3 6396 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */ 6397 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 6398 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */ 6399 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 6400 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables used to indicate last doorbell for specific connection */ 6401 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_SHIFT 6 6402 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */ 6403 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 6404 uint8_t __state /* The state of the connection */; 6405#elif defined(__LITTLE_ENDIAN) 6406 uint8_t __state /* The state of the connection */; 6407 uint8_t agg_vars1; 6408 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ 6409 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 6410 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ 6411 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50_SHIFT 1 6412 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ 6413 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 2 6414 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ 6415 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 3 6416 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */ 6417 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 6418 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */ 6419 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 6420 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables used to indicate last doorbell for specific connection */ 6421 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_SHIFT 6 6422 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */ 6423 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 6424 uint16_t agg_val1 /* aggregated value 1 */; 6425#endif 6426#if defined(__BIG_ENDIAN) 6427 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 6428 uint8_t __agg_vars4 /* Various aggregative variables*/; 6429 uint8_t agg_vars3; 6430 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */ 6431 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 6432 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */ 6433 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF_SHIFT 6 6434 uint8_t agg_vars2; 6435 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */ 6436 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0 6437 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */ 6438 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN_SHIFT 2 6439 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */ 6440 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 6441 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */ 6442 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 6443 #define XSTORM_TOE_AG_CONTEXT_RESERVED53 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6444 #define XSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 5 6445 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */ 6446 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 6447#elif defined(__LITTLE_ENDIAN) 6448 uint8_t agg_vars2; 6449 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */ 6450 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0 6451 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */ 6452 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN_SHIFT 2 6453 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */ 6454 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 6455 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */ 6456 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 6457 #define XSTORM_TOE_AG_CONTEXT_RESERVED53 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6458 #define XSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 5 6459 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */ 6460 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 6461 uint8_t agg_vars3; 6462 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */ 6463 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 6464 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */ 6465 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF_SHIFT 6 6466 uint8_t __agg_vars4 /* Various aggregative variables*/; 6467 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 6468#endif 6469 uint32_t more_to_send /* The number of bytes left to send */; 6470#if defined(__BIG_ENDIAN) 6471 uint16_t agg_vars5; 6472 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6473 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0 6474 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */ 6475 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 6476 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */ 6477 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 6478 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56 (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6479 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56_SHIFT 14 6480 uint16_t __agg_val4_th /* aggregated value 4 - threshold */; 6481#elif defined(__LITTLE_ENDIAN) 6482 uint16_t __agg_val4_th /* aggregated value 4 - threshold */; 6483 uint16_t agg_vars5; 6484 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6485 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0 6486 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */ 6487 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 6488 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */ 6489 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 6490 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56 (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */ 6491 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56_SHIFT 14 6492#endif 6493 struct xstorm_toe_tcp_ag_context_section tcp /* TCP context section, shared in TOE and ISCSI */; 6494#if defined(__BIG_ENDIAN) 6495 uint16_t __agg_vars7 /* Various aggregative variables*/; 6496 uint8_t __agg_val3_th /* Aggregated value 3 - threshold */; 6497 uint8_t __agg_vars6 /* Various aggregative variables*/; 6498#elif defined(__LITTLE_ENDIAN) 6499 uint8_t __agg_vars6 /* Various aggregative variables*/; 6500 uint8_t __agg_val3_th /* Aggregated value 3 - threshold */; 6501 uint16_t __agg_vars7 /* Various aggregative variables*/; 6502#endif 6503#if defined(__BIG_ENDIAN) 6504 uint16_t __agg_val11_th /* aggregated value 11 - threshold */; 6505 uint16_t __agg_val11 /* aggregated value 11 */; 6506#elif defined(__LITTLE_ENDIAN) 6507 uint16_t __agg_val11 /* aggregated value 11 */; 6508 uint16_t __agg_val11_th /* aggregated value 11 - threshold */; 6509#endif 6510#if defined(__BIG_ENDIAN) 6511 uint8_t __reserved1; 6512 uint8_t __agg_val6_th /* aggregated value 6 - threshold */; 6513 uint16_t __agg_val9 /* aggregated value 9 */; 6514#elif defined(__LITTLE_ENDIAN) 6515 uint16_t __agg_val9 /* aggregated value 9 */; 6516 uint8_t __agg_val6_th /* aggregated value 6 - threshold */; 6517 uint8_t __reserved1; 6518#endif 6519#if defined(__BIG_ENDIAN) 6520 uint16_t __agg_val2_th /* Aggregated value 2 - threshold */; 6521 uint16_t cmp_bd_cons /* BD Consumer from the Completor */; 6522#elif defined(__LITTLE_ENDIAN) 6523 uint16_t cmp_bd_cons /* BD Consumer from the Completor */; 6524 uint16_t __agg_val2_th /* Aggregated value 2 - threshold */; 6525#endif 6526 uint32_t __agg_varint8_t /* Various aggregative variables*/; 6527#if defined(__BIG_ENDIAN) 6528 uint16_t __agg_misc0 /* Misc aggregated variable 0 */; 6529 uint16_t __agg_val4 /* aggregated value 4 */; 6530#elif defined(__LITTLE_ENDIAN) 6531 uint16_t __agg_val4 /* aggregated value 4 */; 6532 uint16_t __agg_misc0 /* Misc aggregated variable 0 */; 6533#endif 6534#if defined(__BIG_ENDIAN) 6535 uint8_t __agg_val3 /* Aggregated value 3 */; 6536 uint8_t __agg_val6 /* Aggregated value 6 */; 6537 uint8_t __agg_val5_th /* Aggregated value 5 - threshold */; 6538 uint8_t __agg_val5 /* Aggregated value 5 */; 6539#elif defined(__LITTLE_ENDIAN) 6540 uint8_t __agg_val5 /* Aggregated value 5 */; 6541 uint8_t __agg_val5_th /* Aggregated value 5 - threshold */; 6542 uint8_t __agg_val6 /* Aggregated value 6 */; 6543 uint8_t __agg_val3 /* Aggregated value 3 */; 6544#endif 6545#if defined(__BIG_ENDIAN) 6546 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */; 6547 uint16_t __bd_ind_max_val /* modulo value for bd_prod */; 6548#elif defined(__LITTLE_ENDIAN) 6549 uint16_t __bd_ind_max_val /* modulo value for bd_prod */; 6550 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */; 6551#endif 6552 uint32_t cmp_bd_start_seq /* The sequence number of the start completion point (BD) */; 6553 uint32_t cmp_bd_page_0_to_31 /* Misc aggregated variable 4 */; 6554 uint32_t cmp_bd_page_32_to_63 /* spare aggregated variable 5 */; 6555}; 6556 6557 6558/* 6559 * doorbell message sent to the chip 6560 */ 6561struct doorbell 6562{ 6563#if defined(__BIG_ENDIAN) 6564 uint16_t zero_fill2 /* driver must zero this field! */; 6565 uint8_t zero_fill1 /* driver must zero this field! */; 6566 struct doorbell_hdr_t header; 6567#elif defined(__LITTLE_ENDIAN) 6568 struct doorbell_hdr_t header; 6569 uint8_t zero_fill1 /* driver must zero this field! */; 6570 uint16_t zero_fill2 /* driver must zero this field! */; 6571#endif 6572}; 6573 6574 6575/* 6576 * doorbell message sent to the chip 6577 */ 6578struct doorbell_set_prod 6579{ 6580#if defined(__BIG_ENDIAN) 6581 uint16_t prod /* Producer index to be set */; 6582 uint8_t zero_fill1 /* driver must zero this field! */; 6583 struct doorbell_hdr_t header; 6584#elif defined(__LITTLE_ENDIAN) 6585 struct doorbell_hdr_t header; 6586 uint8_t zero_fill1 /* driver must zero this field! */; 6587 uint16_t prod /* Producer index to be set */; 6588#endif 6589}; 6590 6591 6592struct regpair_native_t 6593{ 6594 uint32_t lo /* low word for reg-pair */; 6595 uint32_t hi /* high word for reg-pair */; 6596}; 6597 6598 6599struct regpair_t 6600{ 6601 uint32_t lo /* low word for reg-pair */; 6602 uint32_t hi /* high word for reg-pair */; 6603}; 6604 6605 6606/* 6607 * Classify rule opcodes in E2/E3 6608 */ 6609enum classify_rule 6610{ 6611 CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */, 6612 CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */, 6613 CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */, 6614 CLASSIFY_RULE_OPCODE_IMAC_VNI /* Add/remove an Inner MAC-VNI pair entry */, 6615 MAX_CLASSIFY_RULE}; 6616 6617 6618/* 6619 * Classify rule types in E2/E3 6620 */ 6621enum classify_rule_action_type 6622{ 6623 CLASSIFY_RULE_REMOVE, 6624 CLASSIFY_RULE_ADD, 6625 MAX_CLASSIFY_RULE_ACTION_TYPE}; 6626 6627 6628/* 6629 * client init ramrod data $$KEEP_ENDIANNESS$$ 6630 */ 6631struct client_init_general_data 6632{ 6633 uint8_t client_id /* client_id */; 6634 uint8_t statistics_counter_id /* statistics counter id */; 6635 uint8_t statistics_en_flg /* statistics en flg */; 6636 uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */; 6637 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 6638 uint8_t sp_client_id /* the slow path rings client Id. */; 6639 uint16_t mtu /* Host MTU from client config */; 6640 uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */; 6641 uint8_t func_id /* PCI function ID (0-71) */; 6642 uint8_t cos /* The connection cos, if applicable */; 6643 uint8_t traffic_type; 6644 uint8_t fp_hsi_ver /* Hsi version */; 6645 uint8_t reserved0[3]; 6646}; 6647 6648 6649/* 6650 * client init rx data $$KEEP_ENDIANNESS$$ 6651 */ 6652struct client_init_rx_data 6653{ 6654 uint8_t tpa_en; 6655 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */ 6656 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 6657 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */ 6658 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 6659 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */ 6660 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 6661 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */ 6662 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 6663 uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */; 6664 uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */; 6665 uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */; 6666 uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */; 6667 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 6668 uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */; 6669 uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */; 6670 uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */; 6671 uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */; 6672 uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */; 6673 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */; 6674 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */; 6675 uint8_t status_block_id /* rx status block id */; 6676 uint8_t rx_sb_index_number /* status block indices */; 6677 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 6678 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 6679 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 6680 uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */; 6681 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 6682 uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */; 6683 uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */; 6684 struct regpair_t bd_page_base /* BD page base address at the host */; 6685 struct regpair_t sge_page_base /* SGE page base address at the host */; 6686 struct regpair_t cqe_page_base /* Completion queue base address */; 6687 uint8_t is_leading_rss; 6688 uint8_t is_approx_mcast; 6689 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 6690 uint16_t state; 6691 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */ 6692 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 6693 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */ 6694 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 6695 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */ 6696 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 6697 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */ 6698 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 6699 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */ 6700 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 6701 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */ 6702 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 6703 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */ 6704 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 6705 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */ 6706 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 6707 uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */; 6708 uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */; 6709 uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */; 6710 uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */; 6711 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 6712 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 6713 uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket whith will be genratet when this ring is full. for regular flow control set this to 1 */; 6714 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 6715 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 6716 uint8_t handle_ptp_pkts_flg /* If set, this client handles PTP Packets */; 6717 uint8_t reserved6[3]; 6718 uint32_t reserved7; 6719}; 6720 6721/* 6722 * client init tx data $$KEEP_ENDIANNESS$$ 6723 */ 6724struct client_init_tx_data 6725{ 6726 uint8_t enforce_security_flg /* if set, security checks will be made for this connection */; 6727 uint8_t tx_status_block_id /* the number of status block to update */; 6728 uint8_t tx_sb_index_number /* the index to use inside the status block */; 6729 uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */; 6730 uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */; 6731 uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */; 6732 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 6733 struct regpair_t tx_bd_page_base /* BD page base address at the host for TxBdCons */; 6734 uint16_t state; 6735 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */ 6736 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 6737 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */ 6738 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 6739 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */ 6740 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 6741 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */ 6742 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 6743 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */ 6744 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 6745 uint8_t default_vlan_flg /* is default vlan valid for this client. */; 6746 uint8_t force_default_pri_flg /* if set, force default priority */; 6747 uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */; 6748 uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */; 6749 uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */; 6750 uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */; 6751}; 6752 6753/* 6754 * client init ramrod data $$KEEP_ENDIANNESS$$ 6755 */ 6756struct client_init_ramrod_data 6757{ 6758 struct client_init_general_data general /* client init general data */; 6759 struct client_init_rx_data rx /* client init rx data */; 6760 struct client_init_tx_data tx /* client init tx data */; 6761}; 6762 6763 6764/* 6765 * client update ramrod data $$KEEP_ENDIANNESS$$ 6766 */ 6767struct client_update_ramrod_data 6768{ 6769 uint8_t client_id /* the client to update */; 6770 uint8_t func_id /* PCI function ID this client belongs to (0-71) */; 6771 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */; 6772 uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */; 6773 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */; 6774 uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */; 6775 uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */; 6776 uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */; 6777 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 6778 uint8_t activate_change_flg /* If set, activate_flg will be checked */; 6779 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 6780 uint8_t default_vlan_enable_flg; 6781 uint8_t default_vlan_change_flg; 6782 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 6783 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 6784 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 6785 uint8_t silent_vlan_change_flg; 6786 uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */; 6787 uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */; 6788 uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */; 6789 uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */; 6790 uint8_t handle_ptp_pkts_flg /* If set, this client handles PTP Packets */; 6791 uint8_t handle_ptp_pkts_change_flg /* If set, handle_ptp_pkts_flg will be updated. */; 6792 uint16_t reserved1; 6793 uint32_t echo /* echo value to be sent to driver on event ring */; 6794}; 6795 6796 6797/* 6798 * The eth storm context of Cstorm 6799 */ 6800struct cstorm_eth_st_context 6801{ 6802 uint32_t __reserved0[4]; 6803}; 6804 6805 6806struct double_regpair 6807{ 6808 uint32_t regpair0_lo /* low word for reg-pair0 */; 6809 uint32_t regpair0_hi /* high word for reg-pair0 */; 6810 uint32_t regpair1_lo /* low word for reg-pair1 */; 6811 uint32_t regpair1_hi /* high word for reg-pair1 */; 6812}; 6813 6814 6815/* 6816 * 2nd parse bd type used in ethernet tx BDs 6817 */ 6818enum eth_2nd_parse_bd_type 6819{ 6820 ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL, 6821 MAX_ETH_2ND_PARSE_BD_TYPE}; 6822 6823 6824/* 6825 * Ethernet address typesm used in ethernet tx BDs 6826 */ 6827enum eth_addr_type 6828{ 6829 UNKNOWN_ADDRESS, 6830 UNICAST_ADDRESS, 6831 MULTICAST_ADDRESS, 6832 BROADCAST_ADDRESS, 6833 MAX_ETH_ADDR_TYPE}; 6834 6835 6836/* 6837 * $$KEEP_ENDIANNESS$$ 6838 */ 6839struct eth_classify_cmd_header 6840{ 6841 uint8_t cmd_general_data; 6842 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 6843 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 6844 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 6845 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 6846 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR/IMAC_VNI (use enum classify_rule) */ 6847 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 6848 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */ 6849 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 6850 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */ 6851 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 6852 uint8_t func_id /* the function id */; 6853 uint8_t client_id; 6854 uint8_t reserved1; 6855}; 6856 6857 6858/* 6859 * header for eth classification config ramrod $$KEEP_ENDIANNESS$$ 6860 */ 6861struct eth_classify_header 6862{ 6863 uint8_t rule_cnt /* number of rules in classification config ramrod */; 6864 uint8_t reserved0; 6865 uint16_t reserved1; 6866 uint32_t echo /* echo value to be sent to driver on event ring */; 6867}; 6868 6869 6870/* 6871 * Command for adding/removing a Inner-MAC/VNI classification rule $$KEEP_ENDIANNESS$$ 6872 */ 6873struct eth_classify_imac_vni_cmd 6874{ 6875 struct eth_classify_cmd_header header; 6876 uint32_t vni; 6877 uint16_t imac_lsb; 6878 uint16_t imac_mid; 6879 uint16_t imac_msb; 6880 uint16_t reserved1; 6881}; 6882 6883 6884/* 6885 * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$ 6886 */ 6887struct eth_classify_mac_cmd 6888{ 6889 struct eth_classify_cmd_header header; 6890 uint16_t reserved0; 6891 uint16_t inner_mac; 6892 uint16_t mac_lsb; 6893 uint16_t mac_mid; 6894 uint16_t mac_msb; 6895 uint16_t reserved1; 6896}; 6897 6898 6899/* 6900 * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$ 6901 */ 6902struct eth_classify_pair_cmd 6903{ 6904 struct eth_classify_cmd_header header; 6905 uint16_t reserved0; 6906 uint16_t inner_mac; 6907 uint16_t mac_lsb; 6908 uint16_t mac_mid; 6909 uint16_t mac_msb; 6910 uint16_t vlan; 6911}; 6912 6913 6914/* 6915 * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$ 6916 */ 6917struct eth_classify_vlan_cmd 6918{ 6919 struct eth_classify_cmd_header header; 6920 uint32_t reserved0; 6921 uint32_t reserved1; 6922 uint16_t reserved2; 6923 uint16_t vlan; 6924}; 6925 6926/* 6927 * union for eth classification rule $$KEEP_ENDIANNESS$$ 6928 */ 6929union eth_classify_rule_cmd 6930{ 6931 struct eth_classify_mac_cmd mac; 6932 struct eth_classify_vlan_cmd vlan; 6933 struct eth_classify_pair_cmd pair; 6934 struct eth_classify_imac_vni_cmd imac_vni; 6935}; 6936 6937/* 6938 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 6939 */ 6940struct eth_classify_rules_ramrod_data 6941{ 6942 struct eth_classify_header header; 6943 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 6944}; 6945 6946 6947/* 6948 * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$ 6949 */ 6950struct eth_common_ramrod_data 6951{ 6952 uint32_t client_id /* id of this client. (5 bits are used) */; 6953 uint32_t reserved1; 6954}; 6955 6956 6957/* 6958 * The eth storm context of Ustorm 6959 */ 6960struct ustorm_eth_st_context 6961{ 6962 uint32_t reserved0[52]; 6963}; 6964 6965/* 6966 * The eth storm context of Tstorm 6967 */ 6968struct tstorm_eth_st_context 6969{ 6970 uint32_t __reserved0[28]; 6971}; 6972 6973/* 6974 * The eth storm context of Xstorm 6975 */ 6976struct xstorm_eth_st_context 6977{ 6978 uint32_t reserved0[60]; 6979}; 6980 6981/* 6982 * Ethernet connection context 6983 */ 6984struct eth_context 6985{ 6986 struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */; 6987 struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */; 6988 struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */; 6989 struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */; 6990 struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */; 6991 struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */; 6992 struct timers_block_context timers_context /* Timers block context */; 6993 struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */; 6994 struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */; 6995}; 6996 6997 6998/* 6999 * union for sgl and raw data. 7000 */ 7001union eth_sgl_or_raw_data 7002{ 7003 uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */; 7004 uint32_t raw_data[4] /* raw data from Tstorm to the driver. */; 7005}; 7006 7007/* 7008 * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$ 7009 */ 7010struct eth_end_agg_rx_cqe 7011{ 7012 uint8_t type_error_flags; 7013 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 7014 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 7015 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 7016 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 7017 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */ 7018 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 7019 uint8_t reserved1; 7020 uint8_t queue_index /* The aggregation queue index of this packet */; 7021 uint8_t reserved2; 7022 uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */; 7023 uint16_t num_of_coalesced_segs /* Num of coalesced segments. */; 7024 uint16_t pkt_len /* Packet length */; 7025 uint8_t pure_ack_count /* Number of pure acks coalesced. */; 7026 uint8_t reserved3; 7027 uint16_t reserved4; 7028 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 7029 uint32_t padding[8]; 7030}; 7031 7032 7033/* 7034 * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$ 7035 */ 7036struct eth_fast_path_rx_cqe 7037{ 7038 uint8_t type_error_flags; 7039 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 7040 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 7041 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 7042 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 7043 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */ 7044 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 7045 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */ 7046 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 7047 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */ 7048 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 7049 #define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6) /* BitField type_error_flags Is a PTP Timesync Packet */ 7050 #define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6 7051 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7) /* BitField type_error_flags */ 7052 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7 7053 uint8_t status_flags; 7054 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */ 7055 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 7056 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */ 7057 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 7058 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */ 7059 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 7060 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */ 7061 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 7062 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */ 7063 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 7064 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */ 7065 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 7066 uint8_t queue_index /* The aggregation queue index of this packet */; 7067 uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */; 7068 uint32_t rss_hash_result /* RSS toeplitz hash result */; 7069 uint16_t vlan_tag /* Ethernet VLAN tag field */; 7070 uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */; 7071 uint16_t len_on_bd /* Number of bytes placed on the BD */; 7072 struct parsing_flags pars_flags; 7073 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 7074 uint8_t tunn_type /* packet tunneling type */; 7075 uint8_t tunn_inner_hdrs_offset /* Offset to Inner Headers (for tunn_type != TUNN_TYPE_NONE) */; 7076 uint16_t reserved1; 7077 uint32_t tunn_tenant_id /* Tenant ID (for tunn_type != TUNN_TYPE_NONE */; 7078 uint32_t padding[5]; 7079 uint32_t marker /* Used internally by the driver */; 7080}; 7081 7082 7083/* 7084 * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$ 7085 */ 7086struct eth_filter_rules_cmd 7087{ 7088 uint8_t cmd_general_data; 7089 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 7090 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 7091 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 7092 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 7093 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */ 7094 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 7095 uint8_t func_id /* the function id */; 7096 uint8_t client_id /* the client id */; 7097 uint8_t reserved1; 7098 uint16_t state; 7099 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */ 7100 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 7101 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */ 7102 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 7103 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */ 7104 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 7105 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */ 7106 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 7107 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */ 7108 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 7109 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */ 7110 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 7111 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */ 7112 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 7113 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */ 7114 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 7115 uint16_t reserved3; 7116 struct regpair_t reserved4; 7117}; 7118 7119 7120/* 7121 * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$ 7122 */ 7123struct eth_filter_rules_ramrod_data 7124{ 7125 struct eth_classify_header header; 7126 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 7127}; 7128 7129 7130/* 7131 * Hsi version 7132 */ 7133enum eth_fp_hsi_ver 7134{ 7135 ETH_FP_HSI_VER_0 /* Hsi which does not support tunnelling */, 7136 ETH_FP_HSI_VER_1 /* Hsi does support tunnelling */, 7137 ETH_FP_HSI_VER_2 /* Hsi which supports tunneling and UFP */, 7138 MAX_ETH_FP_HSI_VER}; 7139 7140 7141/* 7142 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 7143 */ 7144struct eth_general_rules_ramrod_data 7145{ 7146 struct eth_classify_header header; 7147 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 7148}; 7149 7150 7151/* 7152 * The data for Halt ramrod 7153 */ 7154struct eth_halt_ramrod_data 7155{ 7156 uint32_t client_id /* id of this client. (5 bits are used) */; 7157 uint32_t reserved0; 7158}; 7159 7160 7161/* 7162 * destination and source mac address. 7163 */ 7164struct eth_mac_addresses 7165{ 7166#if defined(__BIG_ENDIAN) 7167 uint16_t dst_mid /* destination mac address 16 middle bits */; 7168 uint16_t dst_lo /* destination mac address 16 low bits */; 7169#elif defined(__LITTLE_ENDIAN) 7170 uint16_t dst_lo /* destination mac address 16 low bits */; 7171 uint16_t dst_mid /* destination mac address 16 middle bits */; 7172#endif 7173#if defined(__BIG_ENDIAN) 7174 uint16_t src_lo /* source mac address 16 low bits */; 7175 uint16_t dst_hi /* destination mac address 16 high bits */; 7176#elif defined(__LITTLE_ENDIAN) 7177 uint16_t dst_hi /* destination mac address 16 high bits */; 7178 uint16_t src_lo /* source mac address 16 low bits */; 7179#endif 7180#if defined(__BIG_ENDIAN) 7181 uint16_t src_hi /* source mac address 16 high bits */; 7182 uint16_t src_mid /* source mac address 16 middle bits */; 7183#elif defined(__LITTLE_ENDIAN) 7184 uint16_t src_mid /* source mac address 16 middle bits */; 7185 uint16_t src_hi /* source mac address 16 high bits */; 7186#endif 7187}; 7188 7189 7190/* 7191 * tunneling related data. $$KEEP_ENDIANNESS$$ 7192 */ 7193struct eth_tunnel_data 7194{ 7195 uint16_t dst_lo /* destination mac address 16 low bits */; 7196 uint16_t dst_mid /* destination mac address 16 middle bits */; 7197 uint16_t dst_hi /* destination mac address 16 high bits */; 7198 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; 7199 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; 7200 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; 7201 uint8_t flags; 7202 #define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ 7203 #define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0 7204 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ 7205 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 7206}; 7207 7208/* 7209 * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). 7210 */ 7211union eth_mac_addr_or_tunnel_data 7212{ 7213 struct eth_mac_addresses mac_addr /* destination and source mac addresses. */; 7214 struct eth_tunnel_data tunnel_data /* tunneling related data. */; 7215}; 7216 7217 7218/* 7219 * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$ 7220 */ 7221struct eth_multicast_rules_cmd 7222{ 7223 uint8_t cmd_general_data; 7224 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 7225 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 7226 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 7227 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 7228 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */ 7229 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 7230 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */ 7231 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 7232 uint8_t func_id /* the function id */; 7233 uint8_t bin_id /* the bin to add this function to (0-255) */; 7234 uint8_t engine_id /* the approximate multicast engine id */; 7235 uint32_t reserved2; 7236 struct regpair_t reserved3; 7237}; 7238 7239 7240/* 7241 * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$ 7242 */ 7243struct eth_multicast_rules_ramrod_data 7244{ 7245 struct eth_classify_header header; 7246 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 7247}; 7248 7249 7250/* 7251 * Place holder for ramrods protocol specific data 7252 */ 7253struct ramrod_data 7254{ 7255 uint32_t data_lo; 7256 uint32_t data_hi; 7257}; 7258 7259/* 7260 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 7261 */ 7262union eth_ramrod_data 7263{ 7264 struct ramrod_data general; 7265}; 7266 7267 7268/* 7269 * RSS toeplitz hash type, as reported in CQE 7270 */ 7271enum eth_rss_hash_type 7272{ 7273 DEFAULT_HASH_TYPE, 7274 IPV4_HASH_TYPE, 7275 TCP_IPV4_HASH_TYPE, 7276 IPV6_HASH_TYPE, 7277 TCP_IPV6_HASH_TYPE, 7278 VLAN_PRI_HASH_TYPE, 7279 E1HOV_PRI_HASH_TYPE, 7280 DSCP_HASH_TYPE, 7281 MAX_ETH_RSS_HASH_TYPE}; 7282 7283 7284/* 7285 * Ethernet RSS mode 7286 */ 7287enum eth_rss_mode 7288{ 7289 ETH_RSS_MODE_DISABLED, 7290 ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 7291 ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS for VXLAN packets) */, 7292 ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field (E1/E1h Only) */, 7293 ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field (E1/E1h Only) */, 7294 ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field (E1/E1h Only) */, 7295 MAX_ETH_RSS_MODE}; 7296 7297 7298/* 7299 * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$ 7300 */ 7301struct eth_rss_update_ramrod_data 7302{ 7303 uint8_t rss_engine_id; 7304 uint8_t rss_mode /* The RSS mode for this function */; 7305 uint16_t capabilities; 7306 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tuple capability */ 7307 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 7308 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tuple capability for TCP */ 7309 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 7310 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tuple capability for UDP */ 7311 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 7312 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tuple capability for VXLAN Tunnels */ 7313 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3 7314 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tuple capability */ 7315 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4 7316 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tuple capability for TCP */ 7317 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5 7318 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tuple capability for UDP */ 7319 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6 7320 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tuple capability for VXLAN Tunnels */ 7321 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7 7322 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8) /* BitField capabilitiesFunction RSS capabilities configuration of Tunnel Inner Headers capability. */ 7323 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8 7324 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */ 7325 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9 7326 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10) /* BitField capabilitiesFunction RSS capabilities */ 7327 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10 7328 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 7329 uint8_t reserved3; 7330 uint16_t reserved4; 7331 uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */; 7332 uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */; 7333 uint32_t echo; 7334 uint32_t reserved5; 7335}; 7336 7337 7338/* 7339 * The eth Rx Buffer Descriptor 7340 */ 7341struct eth_rx_bd 7342{ 7343 uint32_t addr_lo /* Single continuous buffer low pointer */; 7344 uint32_t addr_hi /* Single continuous buffer high pointer */; 7345}; 7346 7347 7348struct eth_rx_bd_next_page 7349{ 7350 uint32_t addr_lo /* Next page low pointer */; 7351 uint32_t addr_hi /* Next page high pointer */; 7352 uint8_t reserved[8]; 7353}; 7354 7355 7356/* 7357 * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$ 7358 */ 7359struct common_ramrod_eth_rx_cqe 7360{ 7361 uint8_t ramrod_type; 7362 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */ 7363 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 7364 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */ 7365 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 7366 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */ 7367 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 7368 uint8_t conn_type /* only 3 bits are used */; 7369 uint16_t reserved1 /* protocol specific data */; 7370 uint32_t conn_and_cmd_data; 7371 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 7372 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 7373 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */ 7374 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 7375 struct ramrod_data protocol_data /* protocol specific data */; 7376 uint32_t echo; 7377 uint32_t reserved2[11]; 7378}; 7379 7380/* 7381 * Rx Last CQE in page (in ETH) 7382 */ 7383struct eth_rx_cqe_next_page 7384{ 7385 uint32_t addr_lo /* Next page low pointer */; 7386 uint32_t addr_hi /* Next page high pointer */; 7387 uint32_t reserved[14]; 7388}; 7389 7390/* 7391 * union for all eth rx cqe types (fix their sizes) 7392 */ 7393union eth_rx_cqe 7394{ 7395 struct eth_fast_path_rx_cqe fast_path_cqe; 7396 struct common_ramrod_eth_rx_cqe ramrod_cqe; 7397 struct eth_rx_cqe_next_page next_page_cqe; 7398 struct eth_end_agg_rx_cqe end_agg_cqe; 7399}; 7400 7401 7402/* 7403 * Values for RX ETH CQE type field 7404 */ 7405enum eth_rx_cqe_type 7406{ 7407 RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */, 7408 RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */, 7409 RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */, 7410 RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */, 7411 MAX_ETH_RX_CQE_TYPE}; 7412 7413 7414/* 7415 * Type of SGL/Raw field in ETH RX fast path CQE 7416 */ 7417enum eth_rx_fp_sel 7418{ 7419 ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */, 7420 ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */, 7421 MAX_ETH_RX_FP_SEL}; 7422 7423 7424/* 7425 * The eth Rx SGE Descriptor 7426 */ 7427struct eth_rx_sge 7428{ 7429 uint32_t addr_lo /* Single continuous buffer low pointer */; 7430 uint32_t addr_hi /* Single continuous buffer high pointer */; 7431}; 7432 7433 7434/* 7435 * common data for all protocols $$KEEP_ENDIANNESS$$ 7436 */ 7437struct spe_hdr_t 7438{ 7439 uint32_t conn_and_cmd_data; 7440 #define SPE_HDR_T_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 7441 #define SPE_HDR_T_CID_SHIFT 0 7442 #define SPE_HDR_T_CMD_ID (0xFFUL<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */ 7443 #define SPE_HDR_T_CMD_ID_SHIFT 24 7444 uint16_t type; 7445 #define SPE_HDR_T_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */ 7446 #define SPE_HDR_T_CONN_TYPE_SHIFT 0 7447 #define SPE_HDR_T_FUNCTION_ID (0xFF<<8) /* BitField type */ 7448 #define SPE_HDR_T_FUNCTION_ID_SHIFT 8 7449 uint16_t reserved1; 7450}; 7451 7452/* 7453 * specific data for ethernet slow path element 7454 */ 7455union eth_specific_data 7456{ 7457 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 7458 struct regpair_t client_update_ramrod_data /* The address of the data for client update ramrod */; 7459 struct regpair_t client_init_ramrod_init_data /* The data for client setup ramrod */; 7460 struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */; 7461 struct regpair_t update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */; 7462 struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */; 7463 struct regpair_t classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */; 7464 struct regpair_t filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */; 7465 struct regpair_t mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */; 7466}; 7467 7468/* 7469 * Ethernet slow path element 7470 */ 7471struct eth_spe 7472{ 7473 struct spe_hdr_t hdr /* common data for all protocols */; 7474 union eth_specific_data data /* data specific to ethernet protocol */; 7475}; 7476 7477 7478/* 7479 * Ethernet command ID for slow path elements 7480 */ 7481enum eth_spqe_cmd_id 7482{ 7483 RAMROD_CMD_ID_ETH_UNUSED, 7484 RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */, 7485 RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */, 7486 RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */, 7487 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */, 7488 RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */, 7489 RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */, 7490 RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */, 7491 RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */, 7492 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 7493 RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 7494 RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 7495 RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */, 7496 RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */, 7497 MAX_ETH_SPQE_CMD_ID}; 7498 7499 7500/* 7501 * eth tpa update command 7502 */ 7503enum eth_tpa_update_command 7504{ 7505 TPA_UPDATE_NONE_COMMAND /* nop command */, 7506 TPA_UPDATE_ENABLE_COMMAND /* enable command */, 7507 TPA_UPDATE_DISABLE_COMMAND /* disable command */, 7508 MAX_ETH_TPA_UPDATE_COMMAND}; 7509 7510 7511/* 7512 * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header 7513 */ 7514enum eth_tunnel_lso_inc_ip_id 7515{ 7516 EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */, 7517 INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */, 7518 MAX_ETH_TUNNEL_LSO_INC_IP_ID}; 7519 7520 7521/* 7522 * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD. 7523 */ 7524enum eth_tunnel_non_lso_csum_location 7525{ 7526 CSUM_ON_PKT /* checksum is on the packet. */, 7527 CSUM_ON_BD /* checksum is on the BD. */, 7528 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION}; 7529 7530 7531/* 7532 * Packet Tunneling Type 7533 */ 7534enum eth_tunn_type 7535{ 7536 TUNN_TYPE_NONE, 7537 TUNN_TYPE_VXLAN, 7538 TUNN_TYPE_L2_GRE /* Ethernet over GRE */, 7539 TUNN_TYPE_IPV4_GRE /* IPv4 over GRE */, 7540 TUNN_TYPE_IPV6_GRE /* IPv6 over GRE */, 7541 TUNN_TYPE_L2_GENEVE /* Ethernet over GENEVE */, 7542 TUNN_TYPE_IPV4_GENEVE /* IPv4 over GENEVE */, 7543 TUNN_TYPE_IPV6_GENEVE /* IPv6 over GENEVE */, 7544 MAX_ETH_TUNN_TYPE}; 7545 7546 7547/* 7548 * Tx regular BD structure $$KEEP_ENDIANNESS$$ 7549 */ 7550struct eth_tx_bd 7551{ 7552 uint32_t addr_lo /* Single continuous buffer low pointer */; 7553 uint32_t addr_hi /* Single continuous buffer high pointer */; 7554 uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */; 7555 uint16_t nbytes /* Size of the data represented by the BD */; 7556 uint8_t reserved[4] /* keeps same size as other eth tx bd types */; 7557}; 7558 7559 7560/* 7561 * structure for easy accessibility to assembler 7562 */ 7563struct eth_tx_bd_flags 7564{ 7565 uint8_t as_bitfield; 7566 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */ 7567 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 7568 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */ 7569 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 7570 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */ 7571 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 7572 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */ 7573 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 7574 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */ 7575 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 7576 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */ 7577 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 7578 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */ 7579 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 7580}; 7581 7582/* 7583 * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$ 7584 */ 7585struct eth_tx_start_bd 7586{ 7587 uint32_t addr_lo /* Single continuous buffer low pointer */; 7588 uint32_t addr_hi /* Single continuous buffer high pointer */; 7589 uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */; 7590 uint16_t nbytes /* Size of the data represented by the BD */; 7591 uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */; 7592 struct eth_tx_bd_flags bd_flags; 7593 uint8_t general_data; 7594 #define ETH_TX_START_BD_HDR_NBDS (0x7<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */ 7595 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 7596 #define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3) /* BitField general_data If set, do not add any additional tags to the packet including MF Tags, Default VLAN or VLAN for the sake of DCB */ 7597 #define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3 7598 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */ 7599 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 7600 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */ 7601 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 7602 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */ 7603 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 7604}; 7605 7606/* 7607 * Tx parsing BD structure for ETH E1/E1h $$KEEP_ENDIANNESS$$ 7608 */ 7609struct eth_tx_parse_bd_e1x 7610{ 7611 uint16_t global_data; 7612 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */ 7613 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 7614 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */ 7615 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 7616 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */ 7617 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 7618 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */ 7619 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 7620 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 7621 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 7622 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */ 7623 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 7624 uint8_t tcp_flags; 7625 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 7626 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 7627 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 7628 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 7629 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 7630 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 7631 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 7632 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 7633 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 7634 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 7635 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 7636 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 7637 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 7638 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 7639 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 7640 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 7641 uint8_t ip_hlen_w /* IP header length in WORDs */; 7642 uint16_t total_hlen_w /* IP+TCP+ETH */; 7643 uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */; 7644 uint16_t lso_mss /* for LSO mode */; 7645 uint16_t ip_id /* for LSO mode */; 7646 uint32_t tcp_send_seq /* for LSO mode */; 7647}; 7648 7649/* 7650 * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$ 7651 */ 7652struct eth_tx_parse_bd_e2 7653{ 7654 union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */; 7655 uint32_t parsing_data; 7656 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */ 7657 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 7658 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */ 7659 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 7660 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */ 7661 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 7662 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */ 7663 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 7664 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */ 7665 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 7666}; 7667 7668/* 7669 * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$ 7670 */ 7671struct eth_tx_parse_2nd_bd 7672{ 7673 uint16_t global_data; 7674 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */ 7675 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 7676 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */ 7677 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 7678 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */ 7679 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 7680 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 7681 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 7682 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */ 7683 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 7684 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */ 7685 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 7686 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */ 7687 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 7688 uint8_t bd_type; 7689 #define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0) /* BitField bd_type Type of bd (use enum eth_2nd_parse_bd_type) */ 7690 #define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0 7691 #define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4) /* BitField bd_type */ 7692 #define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4 7693 uint8_t reserved3; 7694 uint8_t tcp_flags; 7695 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 7696 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 7697 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 7698 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 7699 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 7700 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 7701 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 7702 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 7703 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 7704 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 7705 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 7706 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 7707 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 7708 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 7709 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 7710 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 7711 uint8_t reserved4; 7712 uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */; 7713 uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */; 7714 uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */; 7715 uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */; 7716 uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */; 7717}; 7718 7719/* 7720 * The last BD in the BD memory will hold a pointer to the next BD memory 7721 */ 7722struct eth_tx_next_bd 7723{ 7724 uint32_t addr_lo /* Single continuous buffer low pointer */; 7725 uint32_t addr_hi /* Single continuous buffer high pointer */; 7726 uint8_t reserved[8] /* keeps same size as other eth tx bd types */; 7727}; 7728 7729/* 7730 * union for 4 Bd types 7731 */ 7732union eth_tx_bd_types 7733{ 7734 struct eth_tx_start_bd start_bd /* the first bd in a packets */; 7735 struct eth_tx_bd reg_bd /* the common bd */; 7736 struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */; 7737 struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */; 7738 struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */; 7739 struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */; 7740}; 7741 7742/* 7743 * array of 13 bds as appears in the eth xstorm context 7744 */ 7745struct eth_tx_bds_array 7746{ 7747 union eth_tx_bd_types bds[13]; 7748}; 7749 7750 7751/* 7752 * VLAN mode on TX BDs 7753 */ 7754enum eth_tx_vlan_type 7755{ 7756 X_ETH_NO_VLAN, 7757 X_ETH_OUTBAND_VLAN, 7758 X_ETH_INBAND_VLAN, 7759 X_ETH_FW_ADDED_VLAN /* Driver should not use this! */, 7760 MAX_ETH_TX_VLAN_TYPE}; 7761 7762 7763/* 7764 * Ethernet VLAN filtering mode in E1x 7765 */ 7766enum eth_vlan_filter_mode 7767{ 7768 ETH_VLAN_FILTER_ANY_VLAN /* Dont filter by vlan */, 7769 ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */, 7770 ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */, 7771 MAX_ETH_VLAN_FILTER_MODE}; 7772 7773 7774/* 7775 * MAC filtering configuration command header $$KEEP_ENDIANNESS$$ 7776 */ 7777struct mac_configuration_hdr 7778{ 7779 uint8_t length /* number of entries valid in this command (6 bits) */; 7780 uint8_t offset /* offset of the first entry in the list */; 7781 uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */; 7782 uint32_t echo /* echo value to be sent to driver on event ring */; 7783}; 7784 7785/* 7786 * MAC address in list for ramrod $$KEEP_ENDIANNESS$$ 7787 */ 7788struct mac_configuration_entry 7789{ 7790 uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 7791 uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 7792 uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 7793 uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */; 7794 uint8_t pf_id /* The pf id, for multi function mode */; 7795 uint8_t flags; 7796 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */ 7797 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 7798 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */ 7799 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 7800 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */ 7801 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 7802 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */ 7803 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 7804 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */ 7805 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 7806 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */ 7807 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 7808 uint16_t reserved0; 7809 uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */; 7810}; 7811 7812/* 7813 * MAC filtering configuration command 7814 */ 7815struct mac_configuration_cmd 7816{ 7817 struct mac_configuration_hdr hdr /* header */; 7818 struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */; 7819}; 7820 7821 7822/* 7823 * Set-MAC command type (in E1x) 7824 */ 7825enum set_mac_action_type 7826{ 7827 T_ETH_MAC_COMMAND_INVALIDATE, 7828 T_ETH_MAC_COMMAND_SET, 7829 MAX_SET_MAC_ACTION_TYPE}; 7830 7831 7832/* 7833 * Ethernet TPA Modes 7834 */ 7835enum tpa_mode 7836{ 7837 TPA_LRO /* LRO mode TPA */, 7838 TPA_GRO /* GRO mode TPA */, 7839 MAX_TPA_MODE}; 7840 7841 7842/* 7843 * tpa update ramrod data $$KEEP_ENDIANNESS$$ 7844 */ 7845struct tpa_update_ramrod_data 7846{ 7847 uint8_t update_ipv4 /* none, enable or disable */; 7848 uint8_t update_ipv6 /* none, enable or disable */; 7849 uint8_t client_id /* client init flow control data */; 7850 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 7851 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 7852 uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */; 7853 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 7854 uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */; 7855 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 7856 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 7857 uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */; 7858 uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */; 7859 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 7860 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 7861}; 7862 7863 7864/* 7865 * approximate-match multicast filtering for E1H per function in Tstorm 7866 */ 7867struct tstorm_eth_approximate_match_multicast_filtering 7868{ 7869 uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */; 7870}; 7871 7872 7873/* 7874 * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$ 7875 */ 7876struct tstorm_eth_function_common_config 7877{ 7878 uint16_t config_flags; 7879 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 7880 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 7881 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */ 7882 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 7883 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 7884 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 7885 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */ 7886 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 7887 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */ 7888 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 7889 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */ 7890 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 7891 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */ 7892 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 7893 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 7894 uint8_t reserved1; 7895 uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */; 7896}; 7897 7898 7899/* 7900 * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$ 7901 */ 7902struct tstorm_eth_mac_filter_config 7903{ 7904 uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */; 7905 uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */; 7906 uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */; 7907 uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */; 7908 uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */; 7909 uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. In E1 only vlan_filter[1] is checked. The primary vlan is taken from the CAM target table. */; 7910 uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */; 7911}; 7912 7913 7914/* 7915 * tx only queue init ramrod data $$KEEP_ENDIANNESS$$ 7916 */ 7917struct tx_queue_init_ramrod_data 7918{ 7919 struct client_init_general_data general /* client init general data */; 7920 struct client_init_tx_data tx /* client init tx data */; 7921}; 7922 7923 7924/* 7925 * Three RX producers for ETH 7926 */ 7927struct ustorm_eth_rx_producers 7928{ 7929#if defined(__BIG_ENDIAN) 7930 uint16_t bd_prod /* Producer of the RX BD ring */; 7931 uint16_t cqe_prod /* Producer of the RX CQE ring */; 7932#elif defined(__LITTLE_ENDIAN) 7933 uint16_t cqe_prod /* Producer of the RX CQE ring */; 7934 uint16_t bd_prod /* Producer of the RX BD ring */; 7935#endif 7936#if defined(__BIG_ENDIAN) 7937 uint16_t reserved; 7938 uint16_t sge_prod /* Producer of the RX SGE ring */; 7939#elif defined(__LITTLE_ENDIAN) 7940 uint16_t sge_prod /* Producer of the RX SGE ring */; 7941 uint16_t reserved; 7942#endif 7943}; 7944 7945 7946/* 7947 * ABTS info $$KEEP_ENDIANNESS$$ 7948 */ 7949struct fcoe_abts_info 7950{ 7951 uint16_t aborted_task_id /* Task ID to be aborted */; 7952 uint16_t reserved0; 7953 uint32_t reserved1; 7954}; 7955 7956 7957/* 7958 * Fixed size structure in order to plant it in Union structure $$KEEP_ENDIANNESS$$ 7959 */ 7960struct fcoe_abts_rsp_union 7961{ 7962 uint8_t r_ctl /* Only R_CTL part of the FC header in ABTS ACC or BA_RJT messages is placed */; 7963 uint8_t rsrv[3]; 7964 uint32_t abts_rsp_payload[7] /* The payload of the ABTS ACC (12B) or the BA_RJT (4B) */; 7965}; 7966 7967 7968/* 7969 * 4 regs size $$KEEP_ENDIANNESS$$ 7970 */ 7971struct fcoe_bd_ctx 7972{ 7973 uint32_t buf_addr_hi /* Higher buffer host address */; 7974 uint32_t buf_addr_lo /* Lower buffer host address */; 7975 uint16_t buf_len /* Buffer length (in bytes) */; 7976 uint16_t rsrv0; 7977 uint16_t flags /* BD flags */; 7978 uint16_t rsrv1; 7979}; 7980 7981 7982/* 7983 * FCoE cached sges context $$KEEP_ENDIANNESS$$ 7984 */ 7985struct fcoe_cached_sge_ctx 7986{ 7987 struct regpair_t cur_buf_addr /* Current buffer address (in initialization it is the first cached buffer) */; 7988 uint16_t cur_buf_rem /* Remaining data in current buffer (in bytes) */; 7989 uint16_t second_buf_rem /* Remaining data in second buffer (in bytes) */; 7990 struct regpair_t second_buf_addr /* Second cached buffer address */; 7991}; 7992 7993 7994/* 7995 * Cleanup info $$KEEP_ENDIANNESS$$ 7996 */ 7997struct fcoe_cleanup_info 7998{ 7999 uint16_t cleaned_task_id /* Task ID to be cleaned */; 8000 uint16_t rolled_tx_seq_cnt /* Tx sequence count */; 8001 uint32_t rolled_tx_data_offset /* Tx data offset */; 8002}; 8003 8004 8005/* 8006 * Fcp RSP flags $$KEEP_ENDIANNESS$$ 8007 */ 8008struct fcoe_fcp_rsp_flags 8009{ 8010 uint8_t flags; 8011 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) /* BitField flags */ 8012 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0 8013 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1) /* BitField flags */ 8014 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1 8015 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2) /* BitField flags */ 8016 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2 8017 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3) /* BitField flags */ 8018 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3 8019 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4) /* BitField flags */ 8020 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4 8021 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5) /* BitField flags */ 8022 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5 8023}; 8024 8025/* 8026 * Fcp RSP payload $$KEEP_ENDIANNESS$$ 8027 */ 8028struct fcoe_fcp_rsp_payload 8029{ 8030 struct regpair_t reserved0; 8031 uint32_t fcp_resid; 8032 uint8_t scsi_status_code; 8033 struct fcoe_fcp_rsp_flags fcp_flags; 8034 uint16_t retry_delay_timer; 8035 uint32_t fcp_rsp_len; 8036 uint32_t fcp_sns_len; 8037}; 8038 8039/* 8040 * Fixed size structure in order to plant it in Union structure $$KEEP_ENDIANNESS$$ 8041 */ 8042struct fcoe_fcp_rsp_union 8043{ 8044 struct fcoe_fcp_rsp_payload payload; 8045 struct regpair_t reserved0; 8046}; 8047 8048/* 8049 * FC header $$KEEP_ENDIANNESS$$ 8050 */ 8051struct fcoe_fc_hdr 8052{ 8053 uint8_t s_id[3]; 8054 uint8_t cs_ctl; 8055 uint8_t d_id[3]; 8056 uint8_t r_ctl; 8057 uint16_t seq_cnt; 8058 uint8_t df_ctl; 8059 uint8_t seq_id; 8060 uint8_t f_ctl[3]; 8061 uint8_t type; 8062 uint32_t parameters; 8063 uint16_t rx_id; 8064 uint16_t ox_id; 8065}; 8066 8067/* 8068 * FC header union $$KEEP_ENDIANNESS$$ 8069 */ 8070struct fcoe_mp_rsp_union 8071{ 8072 struct fcoe_fc_hdr fc_hdr /* FC header copied into task context (middle path flows) */; 8073 uint32_t mp_payload_len /* Length of the MP payload that was placed */; 8074 uint32_t rsrv; 8075}; 8076 8077/* 8078 * Completion information $$KEEP_ENDIANNESS$$ 8079 */ 8080union fcoe_comp_flow_info 8081{ 8082 struct fcoe_fcp_rsp_union fcp_rsp /* FCP_RSP payload */; 8083 struct fcoe_abts_rsp_union abts_rsp /* ABTS ACC R_CTL part of the FC header ABTS ACC or BA_RJT payload frame */; 8084 struct fcoe_mp_rsp_union mp_rsp /* FC header copied into task context (middle path flows) */; 8085 uint32_t opaque[8]; 8086}; 8087 8088 8089/* 8090 * External ABTS info $$KEEP_ENDIANNESS$$ 8091 */ 8092struct fcoe_ext_abts_info 8093{ 8094 uint32_t rsrv0[6]; 8095 struct fcoe_abts_info ctx /* ABTS information. Initialized by Xstorm */; 8096}; 8097 8098 8099/* 8100 * External cleanup info $$KEEP_ENDIANNESS$$ 8101 */ 8102struct fcoe_ext_cleanup_info 8103{ 8104 uint32_t rsrv0[6]; 8105 struct fcoe_cleanup_info ctx /* Cleanup information */; 8106}; 8107 8108 8109/* 8110 * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$ 8111 */ 8112struct fcoe_fw_tx_seq_ctx 8113{ 8114 uint32_t data_offset /* The amount of data transmitted so far (equal to FCP_DATA PARAMETER field) */; 8115 uint16_t seq_cnt /* The last SEQ_CNT transmitted */; 8116 uint16_t rsrv0; 8117}; 8118 8119/* 8120 * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$ 8121 */ 8122struct fcoe_ext_fw_tx_seq_ctx 8123{ 8124 uint32_t rsrv0[6]; 8125 struct fcoe_fw_tx_seq_ctx ctx /* TX sequence context */; 8126}; 8127 8128 8129/* 8130 * FCoE multiple sges context $$KEEP_ENDIANNESS$$ 8131 */ 8132struct fcoe_mul_sges_ctx 8133{ 8134 struct regpair_t cur_sge_addr /* Current BD address */; 8135 uint16_t cur_sge_off /* Offset in current BD (in bytes) */; 8136 uint8_t cur_sge_idx /* Current BD index in BD list */; 8137 uint8_t sgl_size /* Total number of BDs */; 8138}; 8139 8140/* 8141 * FCoE external multiple sges context $$KEEP_ENDIANNESS$$ 8142 */ 8143struct fcoe_ext_mul_sges_ctx 8144{ 8145 struct fcoe_mul_sges_ctx mul_sgl /* SGL context */; 8146 struct regpair_t rsrv0; 8147}; 8148 8149 8150/* 8151 * FCP CMD payload $$KEEP_ENDIANNESS$$ 8152 */ 8153struct fcoe_fcp_cmd_payload 8154{ 8155 uint32_t opaque[8]; 8156}; 8157 8158 8159/* 8160 * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$ 8161 */ 8162struct fcoe_fcp_xfr_rdy_payload 8163{ 8164 uint32_t burst_len; 8165 uint32_t data_ro; 8166}; 8167 8168 8169/* 8170 * FC frame $$KEEP_ENDIANNESS$$ 8171 */ 8172struct fcoe_fc_frame 8173{ 8174 struct fcoe_fc_hdr fc_hdr; 8175 uint32_t reserved0[2]; 8176}; 8177 8178 8179/* 8180 * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$ 8181 */ 8182union fcoe_kcqe_params 8183{ 8184 uint32_t reserved0[4]; 8185}; 8186 8187/* 8188 * FCoE KCQ CQE $$KEEP_ENDIANNESS$$ 8189 */ 8190struct fcoe_kcqe 8191{ 8192 uint32_t fcoe_conn_id /* Drivers connection ID (only 16 bits are used) */; 8193 uint32_t completion_status /* 0=command completed successfully, 1=command failed */; 8194 uint32_t fcoe_conn_context_id /* Context ID of the FCoE connection */; 8195 union fcoe_kcqe_params params /* command-specific parameters */; 8196 uint16_t qe_self_seq /* Self identifying sequence number */; 8197 uint8_t op_code /* FCoE KCQ opcode */; 8198 uint8_t flags; 8199 #define FCOE_KCQE_RESERVED0 (0x7<<0) /* BitField flags */ 8200 #define FCOE_KCQE_RESERVED0_SHIFT 0 8201 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) /* BitField flags Everest only - indicates whether this KCQE is a ramrod completion */ 8202 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3 8203 #define FCOE_KCQE_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI,FCoE) */ 8204 #define FCOE_KCQE_LAYER_CODE_SHIFT 4 8205 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) /* BitField flags Indicates whether this KCQE is linked with the next KCQE */ 8206 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 8207}; 8208 8209 8210/* 8211 * FCoE KWQE header $$KEEP_ENDIANNESS$$ 8212 */ 8213struct fcoe_kwqe_header 8214{ 8215 uint8_t op_code /* FCoE KWQE opcode */; 8216 uint8_t flags; 8217 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) /* BitField flags */ 8218 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0 8219 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5) */ 8220 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4 8221 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) /* BitField flags */ 8222 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7 8223}; 8224 8225/* 8226 * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$ 8227 */ 8228struct fcoe_kwqe_init1 8229{ 8230 uint16_t num_tasks /* Number of tasks in global task list */; 8231 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8232 uint32_t task_list_pbl_addr_lo /* Lower 32-bit of Task List page table */; 8233 uint32_t task_list_pbl_addr_hi /* Higher 32-bit of Task List page table */; 8234 uint32_t dummy_buffer_addr_lo /* Lower 32-bit of dummy buffer */; 8235 uint32_t dummy_buffer_addr_hi /* Higher 32-bit of dummy buffer */; 8236 uint16_t sq_num_wqes /* Number of entries in the Send Queue */; 8237 uint16_t rq_num_wqes /* Number of entries in the Receive Queue */; 8238 uint16_t rq_buffer_log_size /* Log of the size of a single buffer (entry) in the RQ */; 8239 uint16_t cq_num_wqes /* Number of entries in the Completion Queue */; 8240 uint16_t mtu /* Max transmission unit */; 8241 uint8_t num_sessions_log /* Log of the number of sessions */; 8242 uint8_t flags; 8243 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) /* BitField flags log of page size value */ 8244 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0 8245 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) /* BitField flags */ 8246 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 8247 #define FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED (0x1<<7) /* BitField flags Special MF mode where classification failure indication from HW is allowed */ 8248 #define FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED_SHIFT 7 8249}; 8250 8251/* 8252 * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$ 8253 */ 8254struct fcoe_kwqe_init2 8255{ 8256 uint8_t hsi_major_version /* Implies on a change broken previous HSI */; 8257 uint8_t hsi_minor_version /* Implies on a change which does not broken previous HSI */; 8258 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8259 uint32_t hash_tbl_pbl_addr_lo /* Lower 32-bit of Hash table PBL */; 8260 uint32_t hash_tbl_pbl_addr_hi /* Higher 32-bit of Hash table PBL */; 8261 uint32_t t2_hash_tbl_addr_lo /* Lower 32-bit of T2 Hash table */; 8262 uint32_t t2_hash_tbl_addr_hi /* Higher 32-bit of T2 Hash table */; 8263 uint32_t t2_ptr_hash_tbl_addr_lo /* Lower 32-bit of T2 ptr Hash table */; 8264 uint32_t t2_ptr_hash_tbl_addr_hi /* Higher 32-bit of T2 ptr Hash table */; 8265 uint32_t free_list_count /* T2 free list count */; 8266}; 8267 8268/* 8269 * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$ 8270 */ 8271struct fcoe_kwqe_init3 8272{ 8273 uint16_t reserved0; 8274 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8275 uint32_t error_bit_map_lo /* 32 lower bits of error bitmap: 1=error, 0=warning */; 8276 uint32_t error_bit_map_hi /* 32 upper bits of error bitmap: 1=error, 0=warning */; 8277 uint8_t perf_config /* 0= no performance acceleration, 1=cached connection, 2=cached tasks, 3=both */; 8278 uint8_t reserved21[3]; 8279 uint32_t reserved2[4]; 8280}; 8281 8282/* 8283 * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$ 8284 */ 8285struct fcoe_kwqe_conn_offload1 8286{ 8287 uint16_t fcoe_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */; 8288 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8289 uint32_t sq_addr_lo /* Lower 32-bit of SQ */; 8290 uint32_t sq_addr_hi /* Higher 32-bit of SQ */; 8291 uint32_t rq_pbl_addr_lo /* Lower 32-bit of RQ page table */; 8292 uint32_t rq_pbl_addr_hi /* Higher 32-bit of RQ page table */; 8293 uint32_t rq_first_pbe_addr_lo /* Lower 32-bit of first RQ pbe */; 8294 uint32_t rq_first_pbe_addr_hi /* Higher 32-bit of first RQ pbe */; 8295 uint16_t rq_prod /* Initial RQ producer */; 8296 uint16_t reserved0; 8297}; 8298 8299/* 8300 * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$ 8301 */ 8302struct fcoe_kwqe_conn_offload2 8303{ 8304 uint16_t tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */; 8305 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8306 uint32_t cq_addr_lo /* Lower 32-bit of CQ */; 8307 uint32_t cq_addr_hi /* Higher 32-bit of CQ */; 8308 uint32_t xferq_addr_lo /* Lower 32-bit of XFERQ */; 8309 uint32_t xferq_addr_hi /* Higher 32-bit of XFERQ */; 8310 uint32_t conn_db_addr_lo /* Lower 32-bit of Conn DB (RQ prod and CQ arm bit) */; 8311 uint32_t conn_db_addr_hi /* Higher 32-bit of Conn DB (RQ prod and CQ arm bit) */; 8312 uint32_t reserved1; 8313}; 8314 8315/* 8316 * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$ 8317 */ 8318struct fcoe_kwqe_conn_offload3 8319{ 8320 uint16_t vlan_tag; 8321 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) /* BitField vlan_tag Vlan id */ 8322 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 8323 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) /* BitField vlan_tag Canonical format indicator */ 8324 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12 8325 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) /* BitField vlan_tag Vlan priority */ 8326 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 8327 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8328 uint8_t s_id[3] /* Source ID, received during FLOGI */; 8329 uint8_t tx_max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by target, received during PLOGI */; 8330 uint8_t d_id[3] /* Destination ID, received after inquiry of the fabric network */; 8331 uint8_t flags; 8332 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) /* BitField flags Supporting multiple N_Port IDs indication, received during FLOGI */ 8333 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0 8334 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution (0 - msec, 1 - nsec), negotiated in PLOGI */ 8335 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1 8336 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) /* BitField flags Continuously increasing SEQ_CNT indication, received during PLOGI */ 8337 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2 8338 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) /* BitField flags Confirmation request supported */ 8339 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3 8340 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) /* BitField flags REC allowed */ 8341 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4 8342 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) /* BitField flags Class 2 valid, received during PLOGI */ 8343 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5 8344 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) /* BitField flags ACK_0 capability supporting by target, received furing PLOGI */ 8345 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 8346 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) /* BitField flags Is inner vlan exist */ 8347 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 8348 uint32_t reserved; 8349 uint32_t confq_first_pbe_addr_lo /* The first page used when handling CONFQ - low address */; 8350 uint32_t confq_first_pbe_addr_hi /* The first page used when handling CONFQ - high address */; 8351 uint16_t tx_total_conc_seqs /* Total concurrent Sequences for all Classes supported by target, received during PLOGI */; 8352 uint16_t rx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by us, sent during FLOGI/PLOGI */; 8353 uint16_t rx_total_conc_seqs /* Total concurrent Sequences for all Classes supported by us, sent during PLOGI */; 8354 uint8_t rx_max_conc_seqs_c3 /* Maximum Concurrent Sequences for Class 3 supported by us, sent during PLOGI */; 8355 uint8_t rx_open_seqs_exch_c3 /* Maximum Open Sequences per Exchange for Class 3 supported by us, sent during PLOGI */; 8356}; 8357 8358/* 8359 * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$ 8360 */ 8361struct fcoe_kwqe_conn_offload4 8362{ 8363 uint8_t e_d_tov_timer_val /* E_D_TOV timer value in milliseconds/20, negotiated in PLOGI */; 8364 uint8_t reserved2; 8365 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8366 uint8_t src_mac_addr_lo[2] /* Lower 16-bit of source MAC address */; 8367 uint8_t src_mac_addr_mid[2] /* Mid 16-bit of source MAC address */; 8368 uint8_t src_mac_addr_hi[2] /* Higher 16-bit of source MAC address */; 8369 uint8_t dst_mac_addr_hi[2] /* Higher 16-bit of destination MAC address */; 8370 uint8_t dst_mac_addr_lo[2] /* Lower 16-bit destination MAC address */; 8371 uint8_t dst_mac_addr_mid[2] /* Mid 16-bit destination MAC address */; 8372 uint32_t lcq_addr_lo /* Lower 32-bit of LCQ */; 8373 uint32_t lcq_addr_hi /* Higher 32-bit of LCQ */; 8374 uint32_t confq_pbl_base_addr_lo /* CONFQ PBL low address */; 8375 uint32_t confq_pbl_base_addr_hi /* CONFQ PBL high address */; 8376}; 8377 8378/* 8379 * FCoE connection enable request $$KEEP_ENDIANNESS$$ 8380 */ 8381struct fcoe_kwqe_conn_enable_disable 8382{ 8383 uint16_t reserved0; 8384 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8385 uint8_t src_mac_addr_lo[2] /* Lower 16-bit of source MAC address (HBAs MAC address) */; 8386 uint8_t src_mac_addr_mid[2] /* Mid 16-bit of source MAC address (HBAs MAC address) */; 8387 uint8_t src_mac_addr_hi[2] /* Higher 16-bit of source MAC address (HBAs MAC address) */; 8388 uint16_t vlan_tag; 8389 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) /* BitField vlan_tagVlan tag Vlan id */ 8390 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 8391 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) /* BitField vlan_tagVlan tag Canonical format indicator */ 8392 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 8393 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) /* BitField vlan_tagVlan tag Vlan priority */ 8394 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 8395 uint8_t dst_mac_addr_lo[2] /* Lower 16-bit of destination MAC address (FCFs MAC address) */; 8396 uint8_t dst_mac_addr_mid[2] /* Mid 16-bit of destination MAC address (FCFs MAC address) */; 8397 uint8_t dst_mac_addr_hi[2] /* Higher 16-bit of destination MAC address (FCFs MAC address) */; 8398 uint16_t reserved1; 8399 uint8_t s_id[3] /* Source ID, received during FLOGI */; 8400 uint8_t vlan_flag /* Vlan flag */; 8401 uint8_t d_id[3] /* Destination ID, received after inquiry of the fabric network */; 8402 uint8_t reserved3; 8403 uint32_t context_id /* Context ID (cid) of the connection */; 8404 uint32_t conn_id /* FCoE Connection ID */; 8405 uint32_t reserved4; 8406}; 8407 8408/* 8409 * FCoE connection destroy request $$KEEP_ENDIANNESS$$ 8410 */ 8411struct fcoe_kwqe_conn_destroy 8412{ 8413 uint16_t reserved0; 8414 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8415 uint32_t context_id /* Context ID (cid) of the connection */; 8416 uint32_t conn_id /* FCoE Connection ID */; 8417 uint32_t reserved1[5]; 8418}; 8419 8420/* 8421 * FCoe destroy request $$KEEP_ENDIANNESS$$ 8422 */ 8423struct fcoe_kwqe_destroy 8424{ 8425 uint16_t reserved0; 8426 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8427 uint32_t reserved1[7]; 8428}; 8429 8430/* 8431 * FCoe statistics request $$KEEP_ENDIANNESS$$ 8432 */ 8433struct fcoe_kwqe_stat 8434{ 8435 uint16_t reserved0; 8436 struct fcoe_kwqe_header hdr /* KWQ WQE header */; 8437 uint32_t stat_params_addr_lo /* Statistics host address */; 8438 uint32_t stat_params_addr_hi /* Statistics host address */; 8439 uint32_t reserved1[5]; 8440}; 8441 8442/* 8443 * FCoE KWQ WQE $$KEEP_ENDIANNESS$$ 8444 */ 8445union fcoe_kwqe 8446{ 8447 struct fcoe_kwqe_init1 init1; 8448 struct fcoe_kwqe_init2 init2; 8449 struct fcoe_kwqe_init3 init3; 8450 struct fcoe_kwqe_conn_offload1 conn_offload1; 8451 struct fcoe_kwqe_conn_offload2 conn_offload2; 8452 struct fcoe_kwqe_conn_offload3 conn_offload3; 8453 struct fcoe_kwqe_conn_offload4 conn_offload4; 8454 struct fcoe_kwqe_conn_enable_disable conn_enable_disable; 8455 struct fcoe_kwqe_conn_destroy conn_destroy; 8456 struct fcoe_kwqe_destroy destroy; 8457 struct fcoe_kwqe_stat statistics; 8458}; 8459 8460 8461/* 8462 * TX SGL context $$KEEP_ENDIANNESS$$ 8463 */ 8464union fcoe_sgl_union_ctx 8465{ 8466 struct fcoe_cached_sge_ctx cached_sge /* Cached SGEs context */; 8467 struct fcoe_ext_mul_sges_ctx sgl /* SGL context */; 8468 uint32_t opaque[5]; 8469}; 8470 8471/* 8472 * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$ 8473 */ 8474struct fcoe_read_flow_info 8475{ 8476 union fcoe_sgl_union_ctx sgl_ctx /* The SGL that would be used for data placement (20 bytes) */; 8477 uint32_t rsrv0[3]; 8478}; 8479 8480 8481/* 8482 * Fcoe stat context $$KEEP_ENDIANNESS$$ 8483 */ 8484struct fcoe_s_stat_ctx 8485{ 8486 uint8_t flags; 8487 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0) /* BitField flags Active Sequence indication (0 - not avtive; 1 - active) */ 8488 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0 8489 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1) /* BitField flags Abort Sequence requested indication */ 8490 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1 8491 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2) /* BitField flags ABTS (on Sequence) protocol complete indication (0 - not completed; 1 -completed by Recipient) */ 8492 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2 8493 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3) /* BitField flags E_D_TOV timeout indication */ 8494 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3 8495 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4) /* BitField flags P_RJT transmitted indication */ 8496 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4 8497 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5) /* BitField flags ACK (EOFt) transmitted indication (0 - not tranmitted; 1 - transmitted) */ 8498 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5 8499 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6) /* BitField flags */ 8500 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6 8501}; 8502 8503/* 8504 * Fcoe rx seq context $$KEEP_ENDIANNESS$$ 8505 */ 8506struct fcoe_rx_seq_ctx 8507{ 8508 uint8_t seq_id /* The Sequence ID */; 8509 struct fcoe_s_stat_ctx s_stat /* The Sequence status */; 8510 uint16_t seq_cnt /* The lowest SEQ_CNT received for the Sequence */; 8511 uint32_t low_exp_ro /* Report on the offset at the beginning of the Sequence */; 8512 uint32_t high_exp_ro /* The highest expected relative offset. The next buffer offset to be received in case of XFER_RDY or in FCP_DATA */; 8513}; 8514 8515 8516/* 8517 * FCoE RX statistics parameters section#0 $$KEEP_ENDIANNESS$$ 8518 */ 8519struct fcoe_rx_stat_params_section0 8520{ 8521 uint32_t fcoe_rx_pkt_cnt /* Number of FCoE packets that were legally received */; 8522 uint32_t fcoe_rx_byte_cnt /* Number of FCoE bytes that were legally received */; 8523}; 8524 8525 8526/* 8527 * FCoE RX statistics parameters section#1 $$KEEP_ENDIANNESS$$ 8528 */ 8529struct fcoe_rx_stat_params_section1 8530{ 8531 uint32_t fcoe_ver_cnt /* Number of packets with wrong FCoE version */; 8532 uint32_t fcoe_rx_drop_pkt_cnt /* Number of FCoE packets that were dropped */; 8533}; 8534 8535 8536/* 8537 * FCoE RX statistics parameters section#2 $$KEEP_ENDIANNESS$$ 8538 */ 8539struct fcoe_rx_stat_params_section2 8540{ 8541 uint32_t fc_crc_cnt /* Number of packets with FC CRC error */; 8542 uint32_t eofa_del_cnt /* Number of packets with EOFa delimiter */; 8543 uint32_t miss_frame_cnt /* Number of missing packets */; 8544 uint32_t seq_timeout_cnt /* Number of sequence timeout expirations (E_D_TOV) */; 8545 uint32_t drop_seq_cnt /* Number of Sequences that were sropped */; 8546 uint32_t fcoe_rx_drop_pkt_cnt /* Number of FCoE packets that were dropped */; 8547 uint32_t fcp_rx_pkt_cnt /* Number of FCP packets that were legally received */; 8548 uint32_t reserved0; 8549}; 8550 8551 8552/* 8553 * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$ 8554 */ 8555union fcoe_rx_wr_union_ctx 8556{ 8557 struct fcoe_read_flow_info read_info /* Data-In/ELS/BLS information */; 8558 union fcoe_comp_flow_info comp_info /* Completion information */; 8559 uint32_t opaque[8]; 8560}; 8561 8562 8563/* 8564 * FCoE SQ element $$KEEP_ENDIANNESS$$ 8565 */ 8566struct fcoe_sqe 8567{ 8568 uint16_t wqe; 8569 #define FCOE_SQE_TASK_ID (0x7FFF<<0) /* BitField wqe The task ID (OX_ID) to be processed */ 8570 #define FCOE_SQE_TASK_ID_SHIFT 0 8571 #define FCOE_SQE_TOGGLE_BIT (0x1<<15) /* BitField wqe Toggle bit updated by the driver */ 8572 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15 8573}; 8574 8575 8576/* 8577 * FCoE TX statistics parameters $$KEEP_ENDIANNESS$$ 8578 */ 8579struct fcoe_tx_stat_params 8580{ 8581 uint32_t fcoe_tx_pkt_cnt /* Number of transmitted FCoE packets */; 8582 uint32_t fcoe_tx_byte_cnt /* Number of transmitted FCoE bytes */; 8583 uint32_t fcp_tx_pkt_cnt /* Number of transmitted FCP packets */; 8584 uint32_t reserved0; 8585}; 8586 8587/* 8588 * FCoE statistics parameters $$KEEP_ENDIANNESS$$ 8589 */ 8590struct fcoe_statistics_params 8591{ 8592 struct fcoe_tx_stat_params tx_stat /* FCoE TX statistics parameters */; 8593 struct fcoe_rx_stat_params_section0 rx_stat0 /* FCoE RX statistics parameters section#0 */; 8594 struct fcoe_rx_stat_params_section1 rx_stat1 /* FCoE RX statistics parameters section#1 */; 8595 struct fcoe_rx_stat_params_section2 rx_stat2 /* FCoE RX statistics parameters section#2 */; 8596}; 8597 8598 8599/* 8600 * 14 regs $$KEEP_ENDIANNESS$$ 8601 */ 8602struct fcoe_tce_tx_only 8603{ 8604 union fcoe_sgl_union_ctx sgl_ctx /* TX SGL context */; 8605 uint32_t rsrv0; 8606}; 8607 8608/* 8609 * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$ 8610 */ 8611union fcoe_tx_wr_rx_rd_union_ctx 8612{ 8613 struct fcoe_fc_frame tx_frame /* Middle-path/ABTS/Data-Out information */; 8614 struct fcoe_fcp_cmd_payload fcp_cmd /* FCP_CMD payload */; 8615 struct fcoe_ext_cleanup_info cleanup /* Task ID to be cleaned */; 8616 struct fcoe_ext_abts_info abts /* Task ID to be aborted */; 8617 struct fcoe_ext_fw_tx_seq_ctx tx_seq /* TX sequence information */; 8618 uint32_t opaque[8]; 8619}; 8620 8621/* 8622 * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$ 8623 */ 8624struct fcoe_tce_tx_wr_rx_rd_const 8625{ 8626 uint8_t init_flags; 8627 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0) /* BitField init_flags Task type - Write / Read / Middle / Unsolicited / ABTS / Cleanup */ 8628 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0 8629 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3) /* BitField init_flags Tape/Disk device indication */ 8630 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3 8631 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4) /* BitField init_flags Class 3/2 indication */ 8632 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4 8633 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5) /* BitField init_flags Num of cached sge (0 - not cached sge) */ 8634 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5 8635 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7) /* BitField init_flags Support REC_TOV flag, for FW use only */ 8636 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7 8637 uint8_t tx_flags; 8638 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write Indication of TX valid task */ 8639 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0 8640 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write The TX state of the task */ 8641 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1 8642 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write */ 8643 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5 8644 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write TX Sequence initiative indication */ 8645 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6 8646 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS (0x1<<7) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write Compelted full tranmission of this task */ 8647 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS_SHIFT 7 8648 uint16_t rsrv3; 8649 uint32_t verify_tx_seq /* Sequence counter snapshot in order to verify target did not send FCP_RSP before the actual transmission of PBF from the SGL */; 8650}; 8651 8652/* 8653 * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$ 8654 */ 8655struct fcoe_tce_tx_wr_rx_rd 8656{ 8657 union fcoe_tx_wr_rx_rd_union_ctx union_ctx /* 32 (8 regs) bytes used for TX only purposes */; 8658 struct fcoe_tce_tx_wr_rx_rd_const const_ctx /* Constant TX_WR_RX_RD */; 8659}; 8660 8661/* 8662 * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$ 8663 */ 8664struct fcoe_tce_rx_wr_tx_rd_const 8665{ 8666 uint32_t data_2_trns /* The maximum amount of data that would be transferred in this task */; 8667 uint32_t init_flags; 8668 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0) /* BitField init_flags The CID of the connection (used by the CHIP) */ 8669 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0 8670 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24) /* BitField init_flags */ 8671 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24 8672}; 8673 8674/* 8675 * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$ 8676 */ 8677struct fcoe_tce_rx_wr_tx_rd_var 8678{ 8679 uint16_t rx_flags; 8680 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0) /* BitField rx_flags */ 8681 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0 8682 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4) /* BitField rx_flags The number of RQ WQEs that were consumed (for sense data only) */ 8683 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4 8684 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7) /* BitField rx_flags Confirmation request indication */ 8685 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7 8686 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8) /* BitField rx_flags The RX state of the task */ 8687 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8 8688 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12) /* BitField rx_flags Indication on expecting to receive the first frame from target */ 8689 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12 8690 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13) /* BitField rx_flags RX Sequence initiative indication */ 8691 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13 8692 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14) /* BitField rx_flags */ 8693 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14 8694 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15) /* BitField rx_flags Indication of RX valid task */ 8695 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15 8696 uint16_t rx_id /* The RX_ID read from incoming frame and to be used in subsequent transmitting frames */; 8697 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy /* Data-In/ELS/BLS information */; 8698}; 8699 8700/* 8701 * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$ 8702 */ 8703struct fcoe_tce_rx_wr_tx_rd 8704{ 8705 struct fcoe_tce_rx_wr_tx_rd_const const_ctx /* The RX_ID read from incoming frame and to be used in subsequent transmitting frames */; 8706 struct fcoe_tce_rx_wr_tx_rd_var var_ctx /* The RX_ID read from incoming frame and to be used in subsequent transmitting frames */; 8707}; 8708 8709/* 8710 * tce_rx_only $$KEEP_ENDIANNESS$$ 8711 */ 8712struct fcoe_tce_rx_only 8713{ 8714 struct fcoe_rx_seq_ctx rx_seq_ctx /* The context of current receiving Sequence */; 8715 union fcoe_rx_wr_union_ctx union_ctx /* Read flow info/ Completion flow info */; 8716}; 8717 8718/* 8719 * task_ctx_entry $$KEEP_ENDIANNESS$$ 8720 */ 8721struct fcoe_task_ctx_entry 8722{ 8723 struct fcoe_tce_tx_only txwr_only /* TX processing shall be the only one to read/write to this section */; 8724 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd /* TX processing shall write and RX shall read from this section */; 8725 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd /* RX processing shall write and TX shall read from this section */; 8726 struct fcoe_tce_rx_only rxwr_only /* RX processing shall be the only one to read/write to this section */; 8727}; 8728 8729 8730/* 8731 * FCoE XFRQ element $$KEEP_ENDIANNESS$$ 8732 */ 8733struct fcoe_xfrqe 8734{ 8735 uint16_t wqe; 8736 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0) /* BitField wqe The task ID (OX_ID) to be processed */ 8737 #define FCOE_XFRQE_TASK_ID_SHIFT 0 8738 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) /* BitField wqe Toggle bit updated by the driver */ 8739 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15 8740}; 8741 8742 8743/* 8744 * Cached SGEs $$KEEP_ENDIANNESS$$ 8745 */ 8746struct common_fcoe_sgl 8747{ 8748 struct fcoe_bd_ctx sge[3]; 8749}; 8750 8751 8752/* 8753 * FCoE SQ\XFRQ element 8754 */ 8755struct fcoe_cached_wqe 8756{ 8757 struct fcoe_sqe sqe /* SQ WQE */; 8758 struct fcoe_xfrqe xfrqe /* XFRQ WQE */; 8759}; 8760 8761 8762/* 8763 * FCoE connection enable\disable params passed by driver to FW in FCoE enable ramrod $$KEEP_ENDIANNESS$$ 8764 */ 8765struct fcoe_conn_enable_disable_ramrod_params 8766{ 8767 struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe; 8768}; 8769 8770 8771/* 8772 * FCoE connection offload params passed by driver to FW in FCoE offload ramrod $$KEEP_ENDIANNESS$$ 8773 */ 8774struct fcoe_conn_offload_ramrod_params 8775{ 8776 struct fcoe_kwqe_conn_offload1 offload_kwqe1; 8777 struct fcoe_kwqe_conn_offload2 offload_kwqe2; 8778 struct fcoe_kwqe_conn_offload3 offload_kwqe3; 8779 struct fcoe_kwqe_conn_offload4 offload_kwqe4; 8780}; 8781 8782 8783struct ustorm_fcoe_mng_ctx 8784{ 8785#if defined(__BIG_ENDIAN) 8786 uint8_t mid_seq_proc_flag /* Middle Sequence received processing */; 8787 uint8_t tce_in_cam_flag /* TCE in CAM indication */; 8788 uint8_t tce_on_ior_flag /* TCE on IOR indication (TCE on IORs but not necessarily in CAM) */; 8789 uint8_t en_cached_tce_flag /* TCE cached functionality enabled indication */; 8790#elif defined(__LITTLE_ENDIAN) 8791 uint8_t en_cached_tce_flag /* TCE cached functionality enabled indication */; 8792 uint8_t tce_on_ior_flag /* TCE on IOR indication (TCE on IORs but not necessarily in CAM) */; 8793 uint8_t tce_in_cam_flag /* TCE in CAM indication */; 8794 uint8_t mid_seq_proc_flag /* Middle Sequence received processing */; 8795#endif 8796#if defined(__BIG_ENDIAN) 8797 uint8_t tce_cam_addr /* CAM address of task context */; 8798 uint8_t cached_conn_flag /* Cached locked connection indication */; 8799 uint16_t rsrv0; 8800#elif defined(__LITTLE_ENDIAN) 8801 uint16_t rsrv0; 8802 uint8_t cached_conn_flag /* Cached locked connection indication */; 8803 uint8_t tce_cam_addr /* CAM address of task context */; 8804#endif 8805#if defined(__BIG_ENDIAN) 8806 uint16_t dma_tce_ram_addr /* RAM address of task context when executing DMA operations (read/write) */; 8807 uint16_t tce_ram_addr /* RAM address of task context (might be in cached table or in scratchpad) */; 8808#elif defined(__LITTLE_ENDIAN) 8809 uint16_t tce_ram_addr /* RAM address of task context (might be in cached table or in scratchpad) */; 8810 uint16_t dma_tce_ram_addr /* RAM address of task context when executing DMA operations (read/write) */; 8811#endif 8812#if defined(__BIG_ENDIAN) 8813 uint16_t ox_id /* Last OX_ID that has been used */; 8814 uint16_t wr_done_seq /* Last task write done in the specific connection */; 8815#elif defined(__LITTLE_ENDIAN) 8816 uint16_t wr_done_seq /* Last task write done in the specific connection */; 8817 uint16_t ox_id /* Last OX_ID that has been used */; 8818#endif 8819 struct regpair_t task_addr /* Last task address in used */; 8820}; 8821 8822/* 8823 * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and used in FCoE context section 8824 */ 8825struct ustorm_fcoe_params 8826{ 8827#if defined(__BIG_ENDIAN) 8828 uint16_t fcoe_conn_id /* The connection ID that would be used by driver to identify the conneciton */; 8829 uint16_t flags; 8830 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) /* BitField flags Supporting multiple N_Port IDs indication, received during FLOGI */ 8831 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0 8832 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution (0 - msec, 1 - nsec), negotiated in PLOGI */ 8833 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1 8834 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) /* BitField flags Continuously increasing SEQ_CNT indication, received during PLOGI */ 8835 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2 8836 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) /* BitField flags Confirmation request supported */ 8837 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3 8838 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) /* BitField flags REC allowed */ 8839 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4 8840 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) /* BitField flags CQ toggle bit */ 8841 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5 8842 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) /* BitField flags XFRQ toggle bit */ 8843 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6 8844 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7) /* BitField flags CONFQ toggle bit */ 8845 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT_SHIFT 7 8846 #define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8) /* BitField flags */ 8847 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 8 8848#elif defined(__LITTLE_ENDIAN) 8849 uint16_t flags; 8850 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) /* BitField flags Supporting multiple N_Port IDs indication, received during FLOGI */ 8851 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0 8852 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution (0 - msec, 1 - nsec), negotiated in PLOGI */ 8853 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1 8854 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) /* BitField flags Continuously increasing SEQ_CNT indication, received during PLOGI */ 8855 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2 8856 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) /* BitField flags Confirmation request supported */ 8857 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3 8858 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) /* BitField flags REC allowed */ 8859 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4 8860 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) /* BitField flags CQ toggle bit */ 8861 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5 8862 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) /* BitField flags XFRQ toggle bit */ 8863 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6 8864 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7) /* BitField flags CONFQ toggle bit */ 8865 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT_SHIFT 7 8866 #define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8) /* BitField flags */ 8867 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 8 8868 uint16_t fcoe_conn_id /* The connection ID that would be used by driver to identify the conneciton */; 8869#endif 8870#if defined(__BIG_ENDIAN) 8871 uint8_t hc_csdm_byte_en /* Host coalescing Cstorm RAM address byte enable */; 8872 uint8_t func_id /* Function id */; 8873 uint8_t port_id /* Port id */; 8874 uint8_t vnic_id /* Vnic id */; 8875#elif defined(__LITTLE_ENDIAN) 8876 uint8_t vnic_id /* Vnic id */; 8877 uint8_t port_id /* Port id */; 8878 uint8_t func_id /* Function id */; 8879 uint8_t hc_csdm_byte_en /* Host coalescing Cstorm RAM address byte enable */; 8880#endif 8881#if defined(__BIG_ENDIAN) 8882 uint16_t rx_total_conc_seqs /* Total concurrent Sequences for all Classes supported by us, sent during PLOGI */; 8883 uint16_t rx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by us, sent during FLOGI/PLOGI */; 8884#elif defined(__LITTLE_ENDIAN) 8885 uint16_t rx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by us, sent during FLOGI/PLOGI */; 8886 uint16_t rx_total_conc_seqs /* Total concurrent Sequences for all Classes supported by us, sent during PLOGI */; 8887#endif 8888#if defined(__BIG_ENDIAN) 8889 uint8_t task_pbe_idx_off /* The first PBE for this specific task list in RAM */; 8890 uint8_t task_in_page_log_size /* Number of tasks in page (log 2) */; 8891 uint16_t rx_max_conc_seqs /* Maximum Concurrent Sequences for Class 3 supported by us, sent during PLOGI */; 8892#elif defined(__LITTLE_ENDIAN) 8893 uint16_t rx_max_conc_seqs /* Maximum Concurrent Sequences for Class 3 supported by us, sent during PLOGI */; 8894 uint8_t task_in_page_log_size /* Number of tasks in page (log 2) */; 8895 uint8_t task_pbe_idx_off /* The first PBE for this specific task list in RAM */; 8896#endif 8897}; 8898 8899/* 8900 * FCoE 16-bits index structure 8901 */ 8902struct fcoe_idx16_fields 8903{ 8904 uint16_t fields; 8905 #define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0) /* BitField fields */ 8906 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0 8907 #define FCOE_IDX16_FIELDS_MSB (0x1<<15) /* BitField fields */ 8908 #define FCOE_IDX16_FIELDS_MSB_SHIFT 15 8909}; 8910 8911/* 8912 * FCoE 16-bits index union 8913 */ 8914union fcoe_idx16_field_union 8915{ 8916 struct fcoe_idx16_fields fields /* Parameters field */; 8917 uint16_t val /* Global value */; 8918}; 8919 8920/* 8921 * Parameters required for placement according to SGL 8922 */ 8923struct ustorm_fcoe_data_place_mng 8924{ 8925#if defined(__BIG_ENDIAN) 8926 uint16_t sge_off; 8927 uint8_t num_sges /* Number of SGEs left to be used on context */; 8928 uint8_t sge_idx /* 0xFF value indicated loading SGL */; 8929#elif defined(__LITTLE_ENDIAN) 8930 uint8_t sge_idx /* 0xFF value indicated loading SGL */; 8931 uint8_t num_sges /* Number of SGEs left to be used on context */; 8932 uint16_t sge_off; 8933#endif 8934}; 8935 8936/* 8937 * Parameters required for placement according to SGL 8938 */ 8939struct ustorm_fcoe_data_place 8940{ 8941 struct ustorm_fcoe_data_place_mng cached_mng /* 0xFF value indicated loading SGL */; 8942 struct fcoe_bd_ctx cached_sge[2]; 8943}; 8944 8945/* 8946 * TX processing shall write and RX processing shall read from this section 8947 */ 8948union fcoe_u_tce_tx_wr_rx_rd_union 8949{ 8950 struct fcoe_abts_info abts /* ABTS information */; 8951 struct fcoe_cleanup_info cleanup /* Cleanup information */; 8952 struct fcoe_fw_tx_seq_ctx tx_seq_ctx /* TX sequence context */; 8953 uint32_t opaque[2]; 8954}; 8955 8956/* 8957 * TX processing shall write and RX processing shall read from this section 8958 */ 8959struct fcoe_u_tce_tx_wr_rx_rd 8960{ 8961 union fcoe_u_tce_tx_wr_rx_rd_union union_ctx /* FW DATA_OUT/CLEANUP information */; 8962 struct fcoe_tce_tx_wr_rx_rd_const const_ctx /* TX processing shall write and RX shall read from this section */; 8963}; 8964 8965struct ustorm_fcoe_tce 8966{ 8967 struct fcoe_u_tce_tx_wr_rx_rd txwr_rxrd /* TX processing shall write and RX shall read from this section */; 8968 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd /* RX processing shall write and TX shall read from this section */; 8969 struct fcoe_tce_rx_only rxwr /* RX processing shall be the only one to read/write to this section */; 8970}; 8971 8972struct ustorm_fcoe_cache_ctx 8973{ 8974 uint32_t rsrv0; 8975 struct ustorm_fcoe_data_place data_place; 8976 struct ustorm_fcoe_tce tce /* Task context */; 8977}; 8978 8979/* 8980 * Ustorm FCoE Storm Context 8981 */ 8982struct ustorm_fcoe_st_context 8983{ 8984 struct ustorm_fcoe_mng_ctx mng_ctx /* Managing the processing of the flow */; 8985 struct ustorm_fcoe_params fcoe_params /* Align to 128 bytes */; 8986 struct regpair_t cq_base_addr /* CQ current page host address */; 8987 struct regpair_t rq_pbl_base /* PBL host address for RQ */; 8988 struct regpair_t rq_cur_page_addr /* RQ current page host address */; 8989 struct regpair_t confq_pbl_base_addr /* Base address of the CONFQ page list */; 8990 struct regpair_t conn_db_base /* Connection data base address in host memory where RQ producer and CQ arm bit reside in */; 8991 struct regpair_t xfrq_base_addr /* XFRQ base host address */; 8992 struct regpair_t lcq_base_addr /* LCQ base host address */; 8993#if defined(__BIG_ENDIAN) 8994 union fcoe_idx16_field_union rq_cons /* RQ consumer advance for each RQ WQE consuming */; 8995 union fcoe_idx16_field_union rq_prod /* RQ producer update by driver and read by FW (should be initialized to RQ size) */; 8996#elif defined(__LITTLE_ENDIAN) 8997 union fcoe_idx16_field_union rq_prod /* RQ producer update by driver and read by FW (should be initialized to RQ size) */; 8998 union fcoe_idx16_field_union rq_cons /* RQ consumer advance for each RQ WQE consuming */; 8999#endif 9000#if defined(__BIG_ENDIAN) 9001 uint16_t xfrq_prod /* XFRQ producer (No consumer is needed since Q can not be overloaded) */; 9002 uint16_t cq_cons /* CQ consumer copy of last update from driver (Q can not be overloaded) */; 9003#elif defined(__LITTLE_ENDIAN) 9004 uint16_t cq_cons /* CQ consumer copy of last update from driver (Q can not be overloaded) */; 9005 uint16_t xfrq_prod /* XFRQ producer (No consumer is needed since Q can not be overloaded) */; 9006#endif 9007#if defined(__BIG_ENDIAN) 9008 uint16_t lcq_cons /* lcq consumer */; 9009 uint16_t hc_cram_address /* Host coalescing Cstorm RAM address */; 9010#elif defined(__LITTLE_ENDIAN) 9011 uint16_t hc_cram_address /* Host coalescing Cstorm RAM address */; 9012 uint16_t lcq_cons /* lcq consumer */; 9013#endif 9014#if defined(__BIG_ENDIAN) 9015 uint16_t sq_xfrq_lcq_confq_size /* SQ/XFRQ/LCQ/CONFQ size */; 9016 uint16_t confq_prod /* CONFQ producer */; 9017#elif defined(__LITTLE_ENDIAN) 9018 uint16_t confq_prod /* CONFQ producer */; 9019 uint16_t sq_xfrq_lcq_confq_size /* SQ/XFRQ/LCQ/CONFQ size */; 9020#endif 9021#if defined(__BIG_ENDIAN) 9022 uint8_t hc_csdm_agg_int /* Host coalescing CSDM aggregative interrupts */; 9023 uint8_t rsrv2; 9024 uint8_t available_rqes /* Available RQEs */; 9025 uint8_t sp_q_flush_cnt /* The remain number of queues to be flushed (in QM) */; 9026#elif defined(__LITTLE_ENDIAN) 9027 uint8_t sp_q_flush_cnt /* The remain number of queues to be flushed (in QM) */; 9028 uint8_t available_rqes /* Available RQEs */; 9029 uint8_t rsrv2; 9030 uint8_t hc_csdm_agg_int /* Host coalescing CSDM aggregative interrupts */; 9031#endif 9032#if defined(__BIG_ENDIAN) 9033 uint16_t num_pend_tasks /* Number of pending tasks */; 9034 uint16_t pbf_ack_ram_addr /* PBF TX sequence ACK ram address */; 9035#elif defined(__LITTLE_ENDIAN) 9036 uint16_t pbf_ack_ram_addr /* PBF TX sequence ACK ram address */; 9037 uint16_t num_pend_tasks /* Number of pending tasks */; 9038#endif 9039 struct ustorm_fcoe_cache_ctx cache_ctx /* Cached context */; 9040}; 9041 9042/* 9043 * The FCoE non-aggregative context of Tstorm 9044 */ 9045struct tstorm_fcoe_st_context 9046{ 9047 struct regpair_t reserved0; 9048 struct regpair_t reserved1; 9049}; 9050 9051/* 9052 * Ethernet context section 9053 */ 9054struct xstorm_fcoe_eth_context_section 9055{ 9056#if defined(__BIG_ENDIAN) 9057 uint8_t remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */; 9058 uint8_t remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */; 9059 uint8_t local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */; 9060 uint8_t local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */; 9061#elif defined(__LITTLE_ENDIAN) 9062 uint8_t local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */; 9063 uint8_t local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */; 9064 uint8_t remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */; 9065 uint8_t remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */; 9066#endif 9067#if defined(__BIG_ENDIAN) 9068 uint8_t remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */; 9069 uint8_t remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */; 9070 uint8_t remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */; 9071 uint8_t remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */; 9072#elif defined(__LITTLE_ENDIAN) 9073 uint8_t remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */; 9074 uint8_t remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */; 9075 uint8_t remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */; 9076 uint8_t remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */; 9077#endif 9078#if defined(__BIG_ENDIAN) 9079 uint16_t reserved_vlan_type /* this field is not an absolute must, but the reseved was here */; 9080 uint16_t params; 9081 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /* BitField params part of PBF Header Builder Command */ 9082 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 9083 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* BitField params Canonical format indicator, part of PBF Header Builder Command */ 9084 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12 9085 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* BitField params part of PBF Header Builder Command */ 9086 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 9087#elif defined(__LITTLE_ENDIAN) 9088 uint16_t params; 9089 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /* BitField params part of PBF Header Builder Command */ 9090 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 9091 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* BitField params Canonical format indicator, part of PBF Header Builder Command */ 9092 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12 9093 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* BitField params part of PBF Header Builder Command */ 9094 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 9095 uint16_t reserved_vlan_type /* this field is not an absolute must, but the reseved was here */; 9096#endif 9097#if defined(__BIG_ENDIAN) 9098 uint8_t local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */; 9099 uint8_t local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */; 9100 uint8_t local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */; 9101 uint8_t local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */; 9102#elif defined(__LITTLE_ENDIAN) 9103 uint8_t local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */; 9104 uint8_t local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */; 9105 uint8_t local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */; 9106 uint8_t local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */; 9107#endif 9108}; 9109 9110/* 9111 * Flags used in FCoE context section - 1 byte 9112 */ 9113struct xstorm_fcoe_context_flags 9114{ 9115 uint8_t flags; 9116 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0) /* BitField flags The current queue in process */ 9117 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0 9118 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2) /* BitField flags Middle of Sequence indication */ 9119 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2 9120 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3) /* BitField flags Indicates whether the SQ is blocked since we are in the middle of ABTS/Cleanup procedure */ 9121 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3 9122 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4) /* BitField flags REC support */ 9123 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4 9124 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5) /* BitField flags SQ toggle bit */ 9125 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5 9126 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6) /* BitField flags XFRQ toggle bit */ 9127 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6 9128 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7) /* BitField flags Are we using VNTag inner vlan - in this case we have to read it on every VNTag version change */ 9129 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7 9130}; 9131 9132struct xstorm_fcoe_tce 9133{ 9134 struct fcoe_tce_tx_only txwr /* TX processing shall be the only one to read/write to this section */; 9135 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd /* TX processing shall write and RX processing shall read from this section */; 9136}; 9137 9138/* 9139 * FCP_DATA parameters required for transmission 9140 */ 9141struct xstorm_fcoe_fcp_data 9142{ 9143 uint32_t io_rem /* IO remainder */; 9144#if defined(__BIG_ENDIAN) 9145 uint16_t cached_sge_off; 9146 uint8_t cached_num_sges /* Number of SGEs on context */; 9147 uint8_t cached_sge_idx /* 0xFF value indicated loading SGL */; 9148#elif defined(__LITTLE_ENDIAN) 9149 uint8_t cached_sge_idx /* 0xFF value indicated loading SGL */; 9150 uint8_t cached_num_sges /* Number of SGEs on context */; 9151 uint16_t cached_sge_off; 9152#endif 9153 uint32_t buf_addr_hi_0 /* Higher buffer host address */; 9154 uint32_t buf_addr_lo_0 /* Lower buffer host address */; 9155#if defined(__BIG_ENDIAN) 9156 uint16_t num_of_pending_tasks /* Num of pending tasks */; 9157 uint16_t buf_len_0 /* Buffer length (in bytes) */; 9158#elif defined(__LITTLE_ENDIAN) 9159 uint16_t buf_len_0 /* Buffer length (in bytes) */; 9160 uint16_t num_of_pending_tasks /* Num of pending tasks */; 9161#endif 9162 uint32_t buf_addr_hi_1 /* Higher buffer host address */; 9163 uint32_t buf_addr_lo_1 /* Lower buffer host address */; 9164#if defined(__BIG_ENDIAN) 9165 uint16_t task_pbe_idx_off /* Task pbe index offset */; 9166 uint16_t buf_len_1 /* Buffer length (in bytes) */; 9167#elif defined(__LITTLE_ENDIAN) 9168 uint16_t buf_len_1 /* Buffer length (in bytes) */; 9169 uint16_t task_pbe_idx_off /* Task pbe index offset */; 9170#endif 9171 uint32_t buf_addr_hi_2 /* Higher buffer host address */; 9172 uint32_t buf_addr_lo_2 /* Lower buffer host address */; 9173#if defined(__BIG_ENDIAN) 9174 uint16_t ox_id /* OX_ID */; 9175 uint16_t buf_len_2 /* Buffer length (in bytes) */; 9176#elif defined(__LITTLE_ENDIAN) 9177 uint16_t buf_len_2 /* Buffer length (in bytes) */; 9178 uint16_t ox_id /* OX_ID */; 9179#endif 9180}; 9181 9182/* 9183 * Continuation of Flags used in FCoE context section - 1 byte 9184 */ 9185struct xstorm_fcoe_context_flags_cont 9186{ 9187 uint8_t flags; 9188 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE (0x1<<0) /* BitField flags CONFQ toggle bit */ 9189 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE_SHIFT 0 9190 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG (0x1<<1) /* BitField flags Is any inner vlan exist */ 9191 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG_SHIFT 1 9192 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED (0x3F<<2) /* BitField flags */ 9193 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED_SHIFT 2 9194}; 9195 9196/* 9197 * vlan configuration 9198 */ 9199struct xstorm_fcoe_vlan_conf 9200{ 9201 uint8_t vlan_conf; 9202 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY (0x7<<0) /* BitField vlan_conf Original inner vlan priority */ 9203 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY_SHIFT 0 9204 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3) /* BitField vlan_conf Original inner vlan flag */ 9205 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3 9206 #define XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY (0x7<<4) /* BitField vlan_conf Original outer vlan priority */ 9207 #define XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY_SHIFT 4 9208 #define XSTORM_FCOE_VLAN_CONF_RESERVED (0x1<<7) /* BitField vlan_conf */ 9209 #define XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 7 9210}; 9211 9212/* 9213 * FCoE 16-bits vlan structure 9214 */ 9215struct fcoe_vlan_fields 9216{ 9217 uint16_t fields; 9218 #define FCOE_VLAN_FIELDS_VID (0xFFF<<0) /* BitField fields */ 9219 #define FCOE_VLAN_FIELDS_VID_SHIFT 0 9220 #define FCOE_VLAN_FIELDS_CLI (0x1<<12) /* BitField fields */ 9221 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12 9222 #define FCOE_VLAN_FIELDS_PRI (0x7<<13) /* BitField fields */ 9223 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13 9224}; 9225 9226/* 9227 * FCoE 16-bits vlan union 9228 */ 9229union fcoe_vlan_field_union 9230{ 9231 struct fcoe_vlan_fields fields /* Parameters field */; 9232 uint16_t val /* Global value */; 9233}; 9234 9235/* 9236 * FCoE 16-bits vlan, vif union 9237 */ 9238union fcoe_vlan_vif_field_union 9239{ 9240 union fcoe_vlan_field_union vlan /* Vlan */; 9241 uint16_t vif /* VIF */; 9242}; 9243 9244/* 9245 * FCoE context section 9246 */ 9247struct xstorm_fcoe_context_section 9248{ 9249#if defined(__BIG_ENDIAN) 9250 uint8_t cs_ctl /* cs ctl */; 9251 uint8_t s_id[3] /* Source ID, received during FLOGI */; 9252#elif defined(__LITTLE_ENDIAN) 9253 uint8_t s_id[3] /* Source ID, received during FLOGI */; 9254 uint8_t cs_ctl /* cs ctl */; 9255#endif 9256#if defined(__BIG_ENDIAN) 9257 uint8_t rctl /* rctl */; 9258 uint8_t d_id[3] /* Destination ID, received after inquiry of the fabric network */; 9259#elif defined(__LITTLE_ENDIAN) 9260 uint8_t d_id[3] /* Destination ID, received after inquiry of the fabric network */; 9261 uint8_t rctl /* rctl */; 9262#endif 9263#if defined(__BIG_ENDIAN) 9264 uint16_t sq_xfrq_lcq_confq_size /* SQ/XFRQ/LCQ/CONFQ size */; 9265 uint16_t tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */; 9266#elif defined(__LITTLE_ENDIAN) 9267 uint16_t tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */; 9268 uint16_t sq_xfrq_lcq_confq_size /* SQ/XFRQ/LCQ/CONFQ size */; 9269#endif 9270 uint32_t lcq_prod /* LCQ producer value */; 9271#if defined(__BIG_ENDIAN) 9272 uint8_t port_id /* Port ID */; 9273 uint8_t func_id /* Function ID */; 9274 uint8_t seq_id /* SEQ ID counter to be used in transmitted FC header */; 9275 struct xstorm_fcoe_context_flags tx_flags; 9276#elif defined(__LITTLE_ENDIAN) 9277 struct xstorm_fcoe_context_flags tx_flags; 9278 uint8_t seq_id /* SEQ ID counter to be used in transmitted FC header */; 9279 uint8_t func_id /* Function ID */; 9280 uint8_t port_id /* Port ID */; 9281#endif 9282#if defined(__BIG_ENDIAN) 9283 uint16_t mtu /* MTU */; 9284 uint8_t func_mode /* Function mode */; 9285 uint8_t vnic_id /* Vnic ID */; 9286#elif defined(__LITTLE_ENDIAN) 9287 uint8_t vnic_id /* Vnic ID */; 9288 uint8_t func_mode /* Function mode */; 9289 uint16_t mtu /* MTU */; 9290#endif 9291 struct regpair_t confq_curr_page_addr /* The current page of CONFQ to be processed */; 9292 struct fcoe_cached_wqe cached_wqe[8] /* Up to 8 SQ/XFRQ WQEs read in one shot */; 9293 struct regpair_t lcq_base_addr /* The page address which the LCQ resides in host memory */; 9294 struct xstorm_fcoe_tce tce /* TX section task context */; 9295 struct xstorm_fcoe_fcp_data fcp_data /* The parameters required for FCP_DATA Sequences transmission */; 9296#if defined(__BIG_ENDIAN) 9297 uint8_t tx_max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by traget, received during PLOGI */; 9298 struct xstorm_fcoe_context_flags_cont tx_flags_cont; 9299 uint8_t dcb_val /* DCB val - let us know if dcb info changes */; 9300 uint8_t data_pb_cmd_size /* Data pb cmd size */; 9301#elif defined(__LITTLE_ENDIAN) 9302 uint8_t data_pb_cmd_size /* Data pb cmd size */; 9303 uint8_t dcb_val /* DCB val - let us know if dcb info changes */; 9304 struct xstorm_fcoe_context_flags_cont tx_flags_cont; 9305 uint8_t tx_max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by traget, received during PLOGI */; 9306#endif 9307#if defined(__BIG_ENDIAN) 9308 uint16_t fcoe_tx_stat_params_ram_addr /* stat Ram Addr */; 9309 uint16_t fcoe_tx_fc_seq_ram_addr /* Tx FC sequence Ram Addr */; 9310#elif defined(__LITTLE_ENDIAN) 9311 uint16_t fcoe_tx_fc_seq_ram_addr /* Tx FC sequence Ram Addr */; 9312 uint16_t fcoe_tx_stat_params_ram_addr /* stat Ram Addr */; 9313#endif 9314#if defined(__BIG_ENDIAN) 9315 uint8_t fcp_cmd_line_credit; 9316 uint8_t eth_hdr_size /* Ethernet header size without eth type */; 9317 uint16_t pbf_addr /* PBF addr */; 9318#elif defined(__LITTLE_ENDIAN) 9319 uint16_t pbf_addr /* PBF addr */; 9320 uint8_t eth_hdr_size /* Ethernet header size without eth type */; 9321 uint8_t fcp_cmd_line_credit; 9322#endif 9323#if defined(__BIG_ENDIAN) 9324 union fcoe_vlan_vif_field_union multi_func_val /* Outer vlan vif union */; 9325 uint8_t page_log_size /* Page log size */; 9326 struct xstorm_fcoe_vlan_conf orig_vlan_conf /* original vlan configuration, used when we switch from dcb enable to dcb disabled */; 9327#elif defined(__LITTLE_ENDIAN) 9328 struct xstorm_fcoe_vlan_conf orig_vlan_conf /* original vlan configuration, used when we switch from dcb enable to dcb disabled */; 9329 uint8_t page_log_size /* Page log size */; 9330 union fcoe_vlan_vif_field_union multi_func_val /* Outer vlan vif union */; 9331#endif 9332#if defined(__BIG_ENDIAN) 9333 uint16_t fcp_cmd_frame_size /* FCP_CMD frame size */; 9334 uint16_t pbf_addr_ff /* PBF addr with ff */; 9335#elif defined(__LITTLE_ENDIAN) 9336 uint16_t pbf_addr_ff /* PBF addr with ff */; 9337 uint16_t fcp_cmd_frame_size /* FCP_CMD frame size */; 9338#endif 9339#if defined(__BIG_ENDIAN) 9340 uint8_t vlan_num /* Vlan number */; 9341 uint8_t cos /* Cos */; 9342 uint8_t cache_xfrq_cons /* Cache xferq consumer */; 9343 uint8_t cache_sq_cons /* Cache sq consumer */; 9344#elif defined(__LITTLE_ENDIAN) 9345 uint8_t cache_sq_cons /* Cache sq consumer */; 9346 uint8_t cache_xfrq_cons /* Cache xferq consumer */; 9347 uint8_t cos /* Cos */; 9348 uint8_t vlan_num /* Vlan number */; 9349#endif 9350 uint32_t verify_tx_seq /* Sequence number of last transmitted sequence in order to verify target did not send FCP_RSP before the actual transmission of PBF from the SGL */; 9351}; 9352 9353/* 9354 * Xstorm FCoE Storm Context 9355 */ 9356struct xstorm_fcoe_st_context 9357{ 9358 struct xstorm_fcoe_eth_context_section eth; 9359 struct xstorm_fcoe_context_section fcoe; 9360}; 9361 9362/* 9363 * Fcoe connection context 9364 */ 9365struct fcoe_context 9366{ 9367 struct ustorm_fcoe_st_context ustorm_st_context /* Ustorm storm context */; 9368 struct tstorm_fcoe_st_context tstorm_st_context /* Tstorm storm context */; 9369 struct xstorm_fcoe_ag_context xstorm_ag_context /* Xstorm aggregative context */; 9370 struct tstorm_fcoe_ag_context tstorm_ag_context /* Tstorm aggregative context */; 9371 struct ustorm_fcoe_ag_context ustorm_ag_context /* Ustorm aggregative context */; 9372 struct timers_block_context timers_context /* Timers block context */; 9373 struct xstorm_fcoe_st_context xstorm_st_context /* Xstorm storm context */; 9374}; 9375 9376 9377/* 9378 * FCoE init params passed by driver to FW in FCoE init ramrod $$KEEP_ENDIANNESS$$ 9379 */ 9380struct fcoe_init_ramrod_params 9381{ 9382 struct fcoe_kwqe_init1 init_kwqe1; 9383 struct fcoe_kwqe_init2 init_kwqe2; 9384 struct fcoe_kwqe_init3 init_kwqe3; 9385 struct regpair_t eq_pbl_base /* Physical address of PBL */; 9386 uint32_t eq_pbl_size /* PBL size */; 9387 uint32_t reserved2; 9388 uint16_t eq_prod /* EQ prdocuer */; 9389 uint16_t sb_num /* Status block number */; 9390 uint8_t sb_id /* Status block id (EQ consumer) */; 9391 uint8_t reserved0; 9392 uint16_t reserved1; 9393}; 9394 9395 9396/* 9397 * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod $$KEEP_ENDIANNESS$$ 9398 */ 9399struct fcoe_stat_ramrod_params 9400{ 9401 struct fcoe_kwqe_stat stat_kwqe; 9402}; 9403 9404 9405/* 9406 * CQ DB CQ producer and pending completion counter 9407 */ 9408struct iscsi_cq_db_prod_pnd_cmpltn_cnt 9409{ 9410#if defined(__BIG_ENDIAN) 9411 uint16_t cntr /* CQ pending completion counter */; 9412 uint16_t prod /* Ustorm CQ producer , updated by Ustorm */; 9413#elif defined(__LITTLE_ENDIAN) 9414 uint16_t prod /* Ustorm CQ producer , updated by Ustorm */; 9415 uint16_t cntr /* CQ pending completion counter */; 9416#endif 9417}; 9418 9419/* 9420 * CQ DB pending completion ITT array 9421 */ 9422struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr 9423{ 9424 struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8] /* CQ pending completion ITT array */; 9425}; 9426 9427/* 9428 * CQ DB pending completion ITT array 9429 */ 9430struct iscsi_cq_db_pnd_comp_itt_arr 9431{ 9432 uint16_t itt[8] /* CQ pending completion ITT array */; 9433}; 9434 9435/* 9436 * Cstorm CQ sequence to notify array, updated by driver 9437 */ 9438struct iscsi_cq_db_sqn_2_notify_arr 9439{ 9440 uint16_t sqn[8] /* Cstorm CQ sequence to notify array, updated by driver */; 9441}; 9442 9443/* 9444 * CQ DB 9445 */ 9446struct iscsi_cq_db 9447{ 9448 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_u_prod_pend_comp_ctr_arr /* Ustorm CQ producer and pending completion counter array, updated by Ustorm */; 9449 struct iscsi_cq_db_pnd_comp_itt_arr cq_c_pend_comp_itt_arr /* Cstorm CQ pending completion ITT array, updated by Cstorm */; 9450 struct iscsi_cq_db_sqn_2_notify_arr cq_drv_sqn_2_notify_arr /* Cstorm CQ sequence to notify array, updated by driver */; 9451 uint32_t reserved[4] /* 16 byte allignment */; 9452}; 9453 9454 9455/* 9456 * iSCSI KCQ CQE parameters 9457 */ 9458union iscsi_kcqe_params 9459{ 9460 uint32_t reserved0[4]; 9461}; 9462 9463/* 9464 * iSCSI KCQ CQE 9465 */ 9466struct iscsi_kcqe 9467{ 9468 uint32_t iscsi_conn_id /* Drivers connection ID (only 16 bits are used) */; 9469 uint32_t completion_status /* 0=command completed successfully, 1=command failed */; 9470 uint32_t iscsi_conn_context_id /* Context ID of the iSCSI connection */; 9471 union iscsi_kcqe_params params /* command-specific parameters */; 9472#if defined(__BIG_ENDIAN) 9473 uint8_t flags; 9474 #define ISCSI_KCQE_RESERVED0 (0x7<<0) /* BitField flags */ 9475 #define ISCSI_KCQE_RESERVED0_SHIFT 0 9476 #define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3) /* BitField flags Everest only - indicates whether this KCQE is a ramrod completion */ 9477 #define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3 9478 #define ISCSI_KCQE_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI) */ 9479 #define ISCSI_KCQE_LAYER_CODE_SHIFT 4 9480 #define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7) /* BitField flags Indicates whether this KCQE is linked with the next KCQE */ 9481 #define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7 9482 uint8_t op_code /* iSCSI KCQ opcode */; 9483 uint16_t qe_self_seq /* Self identifying sequence number */; 9484#elif defined(__LITTLE_ENDIAN) 9485 uint16_t qe_self_seq /* Self identifying sequence number */; 9486 uint8_t op_code /* iSCSI KCQ opcode */; 9487 uint8_t flags; 9488 #define ISCSI_KCQE_RESERVED0 (0x7<<0) /* BitField flags */ 9489 #define ISCSI_KCQE_RESERVED0_SHIFT 0 9490 #define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3) /* BitField flags Everest only - indicates whether this KCQE is a ramrod completion */ 9491 #define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3 9492 #define ISCSI_KCQE_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI) */ 9493 #define ISCSI_KCQE_LAYER_CODE_SHIFT 4 9494 #define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7) /* BitField flags Indicates whether this KCQE is linked with the next KCQE */ 9495 #define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7 9496#endif 9497}; 9498 9499 9500/* 9501 * iSCSI KWQE header 9502 */ 9503struct iscsi_kwqe_header 9504{ 9505#if defined(__BIG_ENDIAN) 9506 uint8_t flags; 9507 #define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) /* BitField flags */ 9508 #define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0 9509 #define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI) */ 9510 #define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4 9511 #define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) /* BitField flags */ 9512 #define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7 9513 uint8_t op_code /* iSCSI KWQE opcode */; 9514#elif defined(__LITTLE_ENDIAN) 9515 uint8_t op_code /* iSCSI KWQE opcode */; 9516 uint8_t flags; 9517 #define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) /* BitField flags */ 9518 #define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0 9519 #define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI) */ 9520 #define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4 9521 #define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) /* BitField flags */ 9522 #define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7 9523#endif 9524}; 9525 9526/* 9527 * iSCSI firmware init request 1 9528 */ 9529struct iscsi_kwqe_init1 9530{ 9531#if defined(__BIG_ENDIAN) 9532 struct iscsi_kwqe_header hdr /* KWQ WQE header */; 9533 uint8_t hsi_version /* HSI version number */; 9534 uint8_t num_cqs /* Number of completion queues */; 9535#elif defined(__LITTLE_ENDIAN) 9536 uint8_t num_cqs /* Number of completion queues */; 9537 uint8_t hsi_version /* HSI version number */; 9538 struct iscsi_kwqe_header hdr /* KWQ WQE header */; 9539#endif 9540 uint32_t dummy_buffer_addr_lo /* Lower 32-bit of dummy buffer - Teton only */; 9541 uint32_t dummy_buffer_addr_hi /* Higher 32-bit of dummy buffer - Teton only */; 9542#if defined(__BIG_ENDIAN) 9543 uint16_t num_ccells_per_conn /* Number of ccells per connection */; 9544 uint16_t num_tasks_per_conn /* Number of tasks per connection */; 9545#elif defined(__LITTLE_ENDIAN) 9546 uint16_t num_tasks_per_conn /* Number of tasks per connection */; 9547 uint16_t num_ccells_per_conn /* Number of ccells per connection */; 9548#endif 9549#if defined(__BIG_ENDIAN) 9550 uint16_t sq_wqes_per_page /* Number of work entries in a single page of SQ */; 9551 uint16_t sq_num_wqes /* Number of entries in the Send Queue */; 9552#elif defined(__LITTLE_ENDIAN) 9553 uint16_t sq_num_wqes /* Number of entries in the Send Queue */; 9554 uint16_t sq_wqes_per_page /* Number of work entries in a single page of SQ */; 9555#endif 9556#if defined(__BIG_ENDIAN) 9557 uint8_t cq_log_wqes_per_page /* Log of number of work entries in a single page of CQ */; 9558 uint8_t flags; 9559 #define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) /* BitField flags page size code */ 9560 #define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0 9561 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) /* BitField flags if set, delayed ack is enabled */ 9562 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4 9563 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) /* BitField flags if set, keep alive is enabled */ 9564 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5 9565 #define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) /* BitField flags */ 9566 #define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6 9567 uint16_t cq_num_wqes /* Number of entries in the Completion Queue */; 9568#elif defined(__LITTLE_ENDIAN) 9569 uint16_t cq_num_wqes /* Number of entries in the Completion Queue */; 9570 uint8_t flags; 9571 #define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) /* BitField flags page size code */ 9572 #define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0 9573 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) /* BitField flags if set, delayed ack is enabled */ 9574 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4 9575 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) /* BitField flags if set, keep alive is enabled */ 9576 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5 9577 #define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) /* BitField flags */ 9578 #define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6 9579 uint8_t cq_log_wqes_per_page /* Log of number of work entries in a single page of CQ */; 9580#endif 9581#if defined(__BIG_ENDIAN) 9582 uint16_t cq_num_pages /* Number of pages in CQ page table */; 9583 uint16_t sq_num_pages /* Number of pages in SQ page table */; 9584#elif defined(__LITTLE_ENDIAN) 9585 uint16_t sq_num_pages /* Number of pages in SQ page table */; 9586 uint16_t cq_num_pages /* Number of pages in CQ page table */; 9587#endif 9588#if defined(__BIG_ENDIAN) 9589 uint16_t rq_buffer_size /* Size of a single buffer (entry) in the RQ */; 9590 uint16_t rq_num_wqes /* Number of entries in the Receive Queue */; 9591#elif defined(__LITTLE_ENDIAN) 9592 uint16_t rq_num_wqes /* Number of entries in the Receive Queue */; 9593 uint16_t rq_buffer_size /* Size of a single buffer (entry) in the RQ */; 9594#endif 9595}; 9596 9597/* 9598 * iSCSI firmware init request 2 9599 */ 9600struct iscsi_kwqe_init2 9601{ 9602#if defined(__BIG_ENDIAN) 9603 struct iscsi_kwqe_header hdr /* KWQ WQE header */; 9604 uint16_t max_cq_sqn /* CQ wraparound value */; 9605#elif defined(__LITTLE_ENDIAN) 9606 uint16_t max_cq_sqn /* CQ wraparound value */; 9607 struct iscsi_kwqe_header hdr /* KWQ WQE header */; 9608#endif 9609 uint32_t error_bit_map[2] /* bit per error type, 0=error, 1=warning */; 9610 uint32_t tcp_keepalive /* TCP keepalive time in seconds */; 9611 uint32_t reserved1[4]; 9612}; 9613 9614/* 9615 * Initial iSCSI connection offload request 1 9616 */ 9617struct iscsi_kwqe_conn_offload1 9618{ 9619#if defined(__BIG_ENDIAN) 9620 struct iscsi_kwqe_header hdr /* KWQ WQE header */; 9621 uint16_t iscsi_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */; 9622#elif defined(__LITTLE_ENDIAN) 9623 uint16_t iscsi_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */; 9624 struct iscsi_kwqe_header hdr /* KWQ WQE header */; 9625#endif 9626 uint32_t sq_page_table_addr_lo /* Lower 32-bit of the SQs page table address */; 9627 uint32_t sq_page_table_addr_hi /* Higher 32-bit of the SQs page table address */; 9628 uint32_t cq_page_table_addr_lo /* Lower 32-bit of the CQs page table address */; 9629 uint32_t cq_page_table_addr_hi /* Higher 32-bit of the CQs page table address */; 9630 uint32_t reserved0[3]; 9631}; 9632 9633/* 9634 * iSCSI Page Table Entry (PTE) 9635 */ 9636struct iscsi_pte 9637{ 9638 uint32_t hi /* Higher 32 bits of address */; 9639 uint32_t lo /* Lower 32 bits of address */; 9640}; 9641 9642/* 9643 * Initial iSCSI connection offload request 2 9644 */ 9645struct iscsi_kwqe_conn_offload2 9646{ 9647#if defined(__BIG_ENDIAN) 9648 struct iscsi_kwqe_header hdr /* KWQE header */; 9649 uint16_t reserved0; 9650#elif defined(__LITTLE_ENDIAN) 9651 uint16_t reserved0; 9652 struct iscsi_kwqe_header hdr /* KWQE header */; 9653#endif 9654 uint32_t rq_page_table_addr_lo /* Lower 32-bits of the RQs page table address */; 9655 uint32_t rq_page_table_addr_hi /* Higher 32-bits of the RQs page table address */; 9656 struct iscsi_pte sq_first_pte /* first SQ page table entry (for FW caching) */; 9657 struct iscsi_pte cq_first_pte /* first CQ page table entry (for FW caching) */; 9658 uint32_t num_additional_wqes /* Everest specific - number of offload3 KWQEs that will follow this KWQE */; 9659}; 9660 9661/* 9662 * Everest specific - Initial iSCSI connection offload request 3 9663 */ 9664struct iscsi_kwqe_conn_offload3 9665{ 9666#if defined(__BIG_ENDIAN) 9667 struct iscsi_kwqe_header hdr /* KWQE header */; 9668 uint16_t reserved0; 9669#elif defined(__LITTLE_ENDIAN) 9670 uint16_t reserved0; 9671 struct iscsi_kwqe_header hdr /* KWQE header */; 9672#endif 9673 uint32_t reserved1; 9674 struct iscsi_pte qp_first_pte[3] /* first page table entry of some iSCSI ring (for FW caching) */; 9675}; 9676 9677/* 9678 * iSCSI connection update request 9679 */ 9680struct iscsi_kwqe_conn_update 9681{ 9682#if defined(__BIG_ENDIAN) 9683 struct iscsi_kwqe_header hdr /* KWQE header */; 9684 uint16_t reserved0; 9685#elif defined(__LITTLE_ENDIAN) 9686 uint16_t reserved0; 9687 struct iscsi_kwqe_header hdr /* KWQE header */; 9688#endif 9689#if defined(__BIG_ENDIAN) 9690 uint8_t session_error_recovery_level /* iSCSI Error Recovery Level negotiated on this connection */; 9691 uint8_t max_outstanding_r2ts /* Maximum number of outstanding R2ts that a target can send for a command */; 9692 uint8_t reserved2; 9693 uint8_t conn_flags; 9694 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0) /* BitField conn_flags 0=off, 1=on */ 9695 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0 9696 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1) /* BitField conn_flags 0=off, 1=on */ 9697 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1 9698 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2) /* BitField conn_flags 0=no, 1=yes */ 9699 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2 9700 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) /* BitField conn_flags 0=no, 1=yes */ 9701 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3 9702 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4) /* BitField conn_flags (use enum tcp_tstorm_ooo) */ 9703 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4 9704 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6) /* BitField conn_flags */ 9705 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6 9706#elif defined(__LITTLE_ENDIAN) 9707 uint8_t conn_flags; 9708 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0) /* BitField conn_flags 0=off, 1=on */ 9709 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0 9710 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1) /* BitField conn_flags 0=off, 1=on */ 9711 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1 9712 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2) /* BitField conn_flags 0=no, 1=yes */ 9713 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2 9714 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) /* BitField conn_flags 0=no, 1=yes */ 9715 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3 9716 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4) /* BitField conn_flags (use enum tcp_tstorm_ooo) */ 9717 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4 9718 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6) /* BitField conn_flags */ 9719 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6 9720 uint8_t reserved2; 9721 uint8_t max_outstanding_r2ts /* Maximum number of outstanding R2ts that a target can send for a command */; 9722 uint8_t session_error_recovery_level /* iSCSI Error Recovery Level negotiated on this connection */; 9723#endif 9724 uint32_t context_id /* Context ID of the iSCSI connection */; 9725 uint32_t max_send_pdu_length /* Maximum length of a PDU that the target can receive */; 9726 uint32_t max_recv_pdu_length /* Maximum length of a PDU that the Initiator can receive */; 9727 uint32_t first_burst_length /* Maximum length of the immediate and unsolicited data that Initiator can send */; 9728 uint32_t max_burst_length /* Maximum length of the data that Initiator and target can send in one burst */; 9729 uint32_t exp_stat_sn /* Expected Status Serial Number */; 9730}; 9731 9732/* 9733 * iSCSI destroy connection request 9734 */ 9735struct iscsi_kwqe_conn_destroy 9736{ 9737#if defined(__BIG_ENDIAN) 9738 struct iscsi_kwqe_header hdr /* KWQ WQE header */; 9739 uint16_t iscsi_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */; 9740#elif defined(__LITTLE_ENDIAN) 9741 uint16_t iscsi_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */; 9742 struct iscsi_kwqe_header hdr /* KWQ WQE header */; 9743#endif 9744 uint32_t context_id /* Context ID of the iSCSI connection */; 9745 uint32_t reserved1[6]; 9746}; 9747 9748/* 9749 * iSCSI KWQ WQE 9750 */ 9751union iscsi_kwqe 9752{ 9753 struct iscsi_kwqe_init1 init1; 9754 struct iscsi_kwqe_init2 init2; 9755 struct iscsi_kwqe_conn_offload1 conn_offload1; 9756 struct iscsi_kwqe_conn_offload2 conn_offload2; 9757 struct iscsi_kwqe_conn_offload3 conn_offload3; 9758 struct iscsi_kwqe_conn_update conn_update; 9759 struct iscsi_kwqe_conn_destroy conn_destroy; 9760}; 9761 9762 9763struct iscsi_rq_db 9764{ 9765#if defined(__BIG_ENDIAN) 9766 uint16_t reserved1; 9767 uint16_t rq_prod; 9768#elif defined(__LITTLE_ENDIAN) 9769 uint16_t rq_prod; 9770 uint16_t reserved1; 9771#endif 9772 uint32_t __fw_hdr[15] /* Used by FW for partial header placement */; 9773}; 9774 9775 9776struct iscsi_sq_db 9777{ 9778#if defined(__BIG_ENDIAN) 9779 uint16_t reserved0 /* Pad structure size to 16 bytes */; 9780 uint16_t sq_prod; 9781#elif defined(__LITTLE_ENDIAN) 9782 uint16_t sq_prod; 9783 uint16_t reserved0 /* Pad structure size to 16 bytes */; 9784#endif 9785 uint32_t reserved1[3] /* Pad structure size to 16 bytes */; 9786}; 9787 9788 9789/* 9790 * Tstorm Tcp flags 9791 */ 9792struct tstorm_l5cm_tcp_flags 9793{ 9794 uint16_t flags; 9795 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0) /* BitField flags */ 9796 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0 9797 #define TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN (0x1<<12) /* BitField flags */ 9798 #define TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN_SHIFT 12 9799 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13) /* BitField flags */ 9800 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13 9801 #define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14) /* BitField flags */ 9802 #define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14 9803}; 9804 9805 9806/* 9807 * Cstorm iSCSI Storm Context 9808 */ 9809struct cstorm_iscsi_st_context 9810{ 9811 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr /* Cstorm CQ producer and CQ pending completion array, updated by Cstorm */; 9812 struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr /* Cstorm CQ producer sequence, updated by Cstorm */; 9813 struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr /* Event Coalescing CQ sequence to notify driver, copied by Cstorm from CQ DB that is updated by Driver */; 9814 struct regpair_t hq_pbl_base /* HQ PBL base */; 9815 struct regpair_t hq_curr_pbe /* HQ current PBE */; 9816 struct regpair_t task_pbl_base /* Task Context Entry PBL base */; 9817 struct regpair_t cq_db_base /* pointer to CQ DB array. each CQ DB entry consists of CQ PBL, arm bit and idx to notify */; 9818#if defined(__BIG_ENDIAN) 9819 uint16_t hq_bd_itt /* copied from HQ BD */; 9820 uint16_t iscsi_conn_id; 9821#elif defined(__LITTLE_ENDIAN) 9822 uint16_t iscsi_conn_id; 9823 uint16_t hq_bd_itt /* copied from HQ BD */; 9824#endif 9825 uint32_t hq_bd_data_segment_len /* copied from HQ BD */; 9826 uint32_t hq_bd_buffer_offset /* copied from HQ BD */; 9827#if defined(__BIG_ENDIAN) 9828 uint8_t rsrv; 9829 uint8_t cq_proc_en_bit_map /* CQ processing enable bit map, 1 bit per CQ */; 9830 uint8_t cq_pend_comp_itt_valid_bit_map /* CQ pending completion ITT valid bit map, 1 bit per CQ */; 9831 uint8_t hq_bd_opcode /* copied from HQ BD */; 9832#elif defined(__LITTLE_ENDIAN) 9833 uint8_t hq_bd_opcode /* copied from HQ BD */; 9834 uint8_t cq_pend_comp_itt_valid_bit_map /* CQ pending completion ITT valid bit map, 1 bit per CQ */; 9835 uint8_t cq_proc_en_bit_map /* CQ processing enable bit map, 1 bit per CQ */; 9836 uint8_t rsrv; 9837#endif 9838 uint32_t hq_tcp_seq /* TCP sequence of next BD to release */; 9839#if defined(__BIG_ENDIAN) 9840 uint16_t flags; 9841 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) /* BitField flags */ 9842 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 9843 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) /* BitField flags */ 9844 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 9845 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) /* BitField flags copied from HQ BD */ 9846 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 9847 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) /* BitField flags copied from HQ BD */ 9848 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 9849 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) /* BitField flags calculated using HQ BD opcode and write flag */ 9850 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 9851 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) /* BitField flags */ 9852 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 9853 uint16_t hq_cons /* HQ consumer */; 9854#elif defined(__LITTLE_ENDIAN) 9855 uint16_t hq_cons /* HQ consumer */; 9856 uint16_t flags; 9857 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) /* BitField flags */ 9858 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 9859 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) /* BitField flags */ 9860 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 9861 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) /* BitField flags copied from HQ BD */ 9862 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 9863 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) /* BitField flags copied from HQ BD */ 9864 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 9865 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) /* BitField flags calculated using HQ BD opcode and write flag */ 9866 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 9867 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) /* BitField flags */ 9868 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 9869#endif 9870 struct regpair_t rsrv1; 9871}; 9872 9873 9874/* 9875 * SCSI read/write SQ WQE 9876 */ 9877struct iscsi_cmd_pdu_hdr_little_endian 9878{ 9879#if defined(__BIG_ENDIAN) 9880 uint8_t opcode; 9881 uint8_t op_attr; 9882 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) /* BitField op_attr Attributes of the SCSI command. To be sent with the outgoing command PDU. */ 9883 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0 9884 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) /* BitField op_attr */ 9885 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3 9886 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) /* BitField op_attr Write bit. Initiator is expected to send the data to the target */ 9887 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5 9888 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) /* BitField op_attr Read bit. Data from target is expected */ 9889 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6 9890 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* BitField op_attr Final bit. Firmware can change this bit based on the command before putting it into the outgoing PDU. */ 9891 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 9892 uint16_t rsrv0; 9893#elif defined(__LITTLE_ENDIAN) 9894 uint16_t rsrv0; 9895 uint8_t op_attr; 9896 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) /* BitField op_attr Attributes of the SCSI command. To be sent with the outgoing command PDU. */ 9897 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0 9898 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) /* BitField op_attr */ 9899 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3 9900 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) /* BitField op_attr Write bit. Initiator is expected to send the data to the target */ 9901 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5 9902 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) /* BitField op_attr Read bit. Data from target is expected */ 9903 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6 9904 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* BitField op_attr Final bit. Firmware can change this bit based on the command before putting it into the outgoing PDU. */ 9905 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 9906 uint8_t opcode; 9907#endif 9908 uint32_t data_fields; 9909 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ 9910 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 9911 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ 9912 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 9913 struct regpair_t lun; 9914 uint32_t itt; 9915 uint32_t expected_data_transfer_length; 9916 uint32_t cmd_sn; 9917 uint32_t exp_stat_sn; 9918 uint32_t scsi_command_block[4]; 9919}; 9920 9921 9922/* 9923 * Buffer per connection, used in Tstorm 9924 */ 9925struct iscsi_conn_buf 9926{ 9927 struct regpair_t reserved[8]; 9928}; 9929 9930 9931/* 9932 * iSCSI context region, used only in iSCSI 9933 */ 9934struct ustorm_iscsi_rq_db 9935{ 9936 struct regpair_t pbl_base /* Pointer to the rq page base list. */; 9937 struct regpair_t curr_pbe /* Pointer to the current rq page base. */; 9938}; 9939 9940/* 9941 * iSCSI context region, used only in iSCSI 9942 */ 9943struct ustorm_iscsi_r2tq_db 9944{ 9945 struct regpair_t pbl_base /* Pointer to the r2tq page base list. */; 9946 struct regpair_t curr_pbe /* Pointer to the current r2tq page base. */; 9947}; 9948 9949/* 9950 * iSCSI context region, used only in iSCSI 9951 */ 9952struct ustorm_iscsi_cq_db 9953{ 9954#if defined(__BIG_ENDIAN) 9955 uint16_t cq_sn /* CQ serial number */; 9956 uint16_t prod /* CQ producer */; 9957#elif defined(__LITTLE_ENDIAN) 9958 uint16_t prod /* CQ producer */; 9959 uint16_t cq_sn /* CQ serial number */; 9960#endif 9961 struct regpair_t curr_pbe /* Pointer to the current cq page base. */; 9962}; 9963 9964/* 9965 * iSCSI context region, used only in iSCSI 9966 */ 9967struct rings_db 9968{ 9969 struct ustorm_iscsi_rq_db rq /* RQ db. */; 9970 struct ustorm_iscsi_r2tq_db r2tq /* R2TQ db. */; 9971 struct ustorm_iscsi_cq_db cq[8] /* CQ db. */; 9972#if defined(__BIG_ENDIAN) 9973 uint16_t rq_prod /* RQ prod */; 9974 uint16_t r2tq_prod /* R2TQ producer. */; 9975#elif defined(__LITTLE_ENDIAN) 9976 uint16_t r2tq_prod /* R2TQ producer. */; 9977 uint16_t rq_prod /* RQ prod */; 9978#endif 9979 struct regpair_t cq_pbl_base /* Pointer to the cq page base list. */; 9980}; 9981 9982/* 9983 * iSCSI context region, used only in iSCSI 9984 */ 9985struct ustorm_iscsi_placement_db 9986{ 9987 uint32_t sgl_base_lo /* SGL base address lo */; 9988 uint32_t sgl_base_hi /* SGL base address hi */; 9989 uint32_t local_sge_0_address_hi /* SGE address hi */; 9990 uint32_t local_sge_0_address_lo /* SGE address lo */; 9991#if defined(__BIG_ENDIAN) 9992 uint16_t curr_sge_offset /* Current offset in the SGE */; 9993 uint16_t local_sge_0_size /* SGE size */; 9994#elif defined(__LITTLE_ENDIAN) 9995 uint16_t local_sge_0_size /* SGE size */; 9996 uint16_t curr_sge_offset /* Current offset in the SGE */; 9997#endif 9998 uint32_t local_sge_1_address_hi /* SGE address hi */; 9999 uint32_t local_sge_1_address_lo /* SGE address lo */; 10000#if defined(__BIG_ENDIAN) 10001 uint8_t exp_padding_2b /* Number of padding bytes not yet processed */; 10002 uint8_t nal_len_3b /* Non 4 byte aligned bytes in the previous iteration */; 10003 uint16_t local_sge_1_size /* SGE size */; 10004#elif defined(__LITTLE_ENDIAN) 10005 uint16_t local_sge_1_size /* SGE size */; 10006 uint8_t nal_len_3b /* Non 4 byte aligned bytes in the previous iteration */; 10007 uint8_t exp_padding_2b /* Number of padding bytes not yet processed */; 10008#endif 10009#if defined(__BIG_ENDIAN) 10010 uint8_t sgl_size /* Number of SGEs remaining till end of SGL */; 10011 uint8_t local_sge_index_2b /* Index to the local SGE currently used */; 10012 uint16_t reserved7; 10013#elif defined(__LITTLE_ENDIAN) 10014 uint16_t reserved7; 10015 uint8_t local_sge_index_2b /* Index to the local SGE currently used */; 10016 uint8_t sgl_size /* Number of SGEs remaining till end of SGL */; 10017#endif 10018 uint32_t rem_pdu /* Number of bytes remaining in PDU */; 10019 uint32_t place_db_bitfield_1; 10020 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0) /* BitField place_db_bitfield_1place_db_bitfield_1 Number of bytes remaining in PDU payload */ 10021 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0 10022 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24) /* BitField place_db_bitfield_1place_db_bitfield_1 Temp task context - determines the CQ index for CQE placement */ 10023 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24 10024 uint32_t place_db_bitfield_2; 10025 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0) /* BitField place_db_bitfield_2place_db_bitfield_2 Bytes to truncate from the payload. */ 10026 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0 10027 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24) /* BitField place_db_bitfield_2place_db_bitfield_2 Sge index on host */ 10028 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24 10029 uint32_t nal; 10030 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0) /* BitField nalNon aligned db Number of bytes remaining in local SGEs */ 10031 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0 10032 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24) /* BitField nalNon aligned db Number of digest bytes not yet processed */ 10033 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24 10034}; 10035 10036/* 10037 * Ustorm iSCSI Storm Context 10038 */ 10039struct ustorm_iscsi_st_context 10040{ 10041 uint32_t exp_stat_sn /* Expected status sequence number, incremented with each response/middle path/unsolicited received. */; 10042 uint32_t exp_data_sn /* Expected Data sequence number, incremented with each data in */; 10043 struct rings_db ring /* rq, r2tq ,cq */; 10044 struct regpair_t task_pbl_base /* Task PBL base will be read from RAM to context */; 10045 struct regpair_t tce_phy_addr /* Pointer to the task context physical address */; 10046 struct ustorm_iscsi_placement_db place_db; 10047 uint32_t reserved8 /* reserved */; 10048 uint32_t rem_rcv_len /* Temp task context - Remaining bytes to end of task */; 10049#if defined(__BIG_ENDIAN) 10050 uint16_t hdr_itt /* field copied from PDU header */; 10051 uint16_t iscsi_conn_id; 10052#elif defined(__LITTLE_ENDIAN) 10053 uint16_t iscsi_conn_id; 10054 uint16_t hdr_itt /* field copied from PDU header */; 10055#endif 10056 uint32_t nal_bytes /* nal bytes read from BRB */; 10057#if defined(__BIG_ENDIAN) 10058 uint8_t hdr_second_byte_union /* field copied from PDU header */; 10059 uint8_t bitfield_0; 10060 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) /* BitField bitfield_0bitfield_0 marks that processing of payload has started */ 10061 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 10062 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) /* BitField bitfield_0bitfield_0 marks that fence is need on the next CQE */ 10063 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 10064 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) /* BitField bitfield_0bitfield_0 marks that a RESET should be sent to CRC machine. Used in NAL condition in the beginning of a PDU. */ 10065 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2 10066 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) /* BitField bitfield_0bitfield_0 reserved */ 10067 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3 10068 uint8_t task_pdu_cache_index; 10069 uint8_t task_pbe_cache_index; 10070#elif defined(__LITTLE_ENDIAN) 10071 uint8_t task_pbe_cache_index; 10072 uint8_t task_pdu_cache_index; 10073 uint8_t bitfield_0; 10074 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) /* BitField bitfield_0bitfield_0 marks that processing of payload has started */ 10075 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 10076 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) /* BitField bitfield_0bitfield_0 marks that fence is need on the next CQE */ 10077 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 10078 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) /* BitField bitfield_0bitfield_0 marks that a RESET should be sent to CRC machine. Used in NAL condition in the beginning of a PDU. */ 10079 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2 10080 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) /* BitField bitfield_0bitfield_0 reserved */ 10081 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3 10082 uint8_t hdr_second_byte_union /* field copied from PDU header */; 10083#endif 10084#if defined(__BIG_ENDIAN) 10085 uint16_t reserved3 /* reserved */; 10086 uint8_t reserved2 /* reserved */; 10087 uint8_t acDecrement /* Manage the AC decrement that should be done by USDM */; 10088#elif defined(__LITTLE_ENDIAN) 10089 uint8_t acDecrement /* Manage the AC decrement that should be done by USDM */; 10090 uint8_t reserved2 /* reserved */; 10091 uint16_t reserved3 /* reserved */; 10092#endif 10093 uint32_t task_stat /* counts dataIn for read and holds data outs, r2t for write */; 10094#if defined(__BIG_ENDIAN) 10095 uint8_t hdr_opcode /* field copied from PDU header */; 10096 uint8_t num_cqs /* Number of CQs supported by this connection */; 10097 uint16_t reserved5 /* reserved */; 10098#elif defined(__LITTLE_ENDIAN) 10099 uint16_t reserved5 /* reserved */; 10100 uint8_t num_cqs /* Number of CQs supported by this connection */; 10101 uint8_t hdr_opcode /* field copied from PDU header */; 10102#endif 10103 uint32_t negotiated_rx; 10104 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0) /* BitField negotiated_rx */ 10105 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0 10106 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24) /* BitField negotiated_rx */ 10107 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24 10108 uint32_t negotiated_rx_and_flags; 10109 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0) /* BitField negotiated_rx_and_flags Negotiated maximum length of sequence */ 10110 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0 10111 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24) /* BitField negotiated_rx_and_flags Marks that unvalid CQE was already posted or PDU header was cachaed in RAM */ 10112 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24 10113 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25) /* BitField negotiated_rx_and_flags Header digest support enable */ 10114 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25 10115 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26) /* BitField negotiated_rx_and_flags Data digest support enable */ 10116 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26 10117 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27) /* BitField negotiated_rx_and_flags */ 10118 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27 10119 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28) /* BitField negotiated_rx_and_flags temp task context */ 10120 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28 10121 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29) /* BitField negotiated_rx_and_flags Task type: 0 = slow-path (non-RW) 1 = read 2 = write */ 10122 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29 10123 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31) /* BitField negotiated_rx_and_flags Set if all data is acked */ 10124 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31 10125}; 10126 10127/* 10128 * TCP context region, shared in TOE, RDMA and ISCSI 10129 */ 10130struct tstorm_tcp_st_context_section 10131{ 10132 uint32_t flags1; 10133 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0) /* BitField flags1various state flags 20b only, Smoothed Rount Trip Time */ 10134 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0 10135 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24) /* BitField flags1various state flags PAWS asserted as invalid in KA flow */ 10136 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24 10137 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25) /* BitField flags1various state flags Timestamps supported on this connection */ 10138 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25 10139 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26) /* BitField flags1various state flags */ 10140 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26 10141 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27) /* BitField flags1various state flags stop receiving rx payload */ 10142 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27 10143 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28) /* BitField flags1various state flags Keep Alive enabled */ 10144 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28 10145 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29) /* BitField flags1various state flags First Retransmition Timout Estimation */ 10146 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29 10147 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30) /* BitField flags1various state flags per connection flag, signals whether to check if rt count exceeds max_seg_retransmit */ 10148 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30 10149 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31) /* BitField flags1various state flags last isle ends with FIN. FIN is counted as 1 byte for isle end sequence */ 10150 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31 10151 uint32_t flags2; 10152 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0) /* BitField flags2various state flags 20b only, Round Trip Time variation */ 10153 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0 10154 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24) /* BitField flags2various state flags */ 10155 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24 10156 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25) /* BitField flags2various state flags per GOS flags, but duplicated for each context */ 10157 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25 10158 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26) /* BitField flags2various state flags keep alive packet was sent */ 10159 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26 10160 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27) /* BitField flags2various state flags persist packet was sent */ 10161 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27 10162 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28) /* BitField flags2various state flags determines wheather or not to update l2 statistics */ 10163 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28 10164 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29) /* BitField flags2various state flags determines wheather or not to update l4 statistics */ 10165 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29 10166 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30) /* BitField flags2various state flags possible blind-in-window RST attack detected */ 10167 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30 10168 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31) /* BitField flags2various state flags possible blind-in-window SYN attack detected */ 10169 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31 10170#if defined(__BIG_ENDIAN) 10171 uint16_t mss; 10172 uint8_t tcp_sm_state /* 3b only, Tcp state machine state */; 10173 uint8_t rto_exp /* 3b only, Exponential Backoff index */; 10174#elif defined(__LITTLE_ENDIAN) 10175 uint8_t rto_exp /* 3b only, Exponential Backoff index */; 10176 uint8_t tcp_sm_state /* 3b only, Tcp state machine state */; 10177 uint16_t mss; 10178#endif 10179 uint32_t rcv_nxt /* Receive sequence: next expected */; 10180 uint32_t timestamp_recent /* last timestamp from segTS */; 10181 uint32_t timestamp_recent_time /* time at which timestamp_recent has been set */; 10182 uint32_t cwnd /* Congestion window */; 10183 uint32_t ss_thresh /* Slow Start Threshold */; 10184 uint32_t cwnd_accum /* Congestion window accumilation */; 10185 uint32_t prev_seg_seq /* Sequence number used for last sndWnd update (was: snd_wnd_l1) */; 10186 uint32_t expected_rel_seq /* the last update of rel_seq */; 10187 uint32_t recover /* Recording of sndMax when we enter retransmit */; 10188#if defined(__BIG_ENDIAN) 10189 uint8_t retransmit_count /* Number of times a packet was retransmitted */; 10190 uint8_t ka_max_probe_count /* Keep Alive maximum probe counter */; 10191 uint8_t persist_probe_count /* Persist probe counter */; 10192 uint8_t ka_probe_count /* Keep Alive probe counter */; 10193#elif defined(__LITTLE_ENDIAN) 10194 uint8_t ka_probe_count /* Keep Alive probe counter */; 10195 uint8_t persist_probe_count /* Persist probe counter */; 10196 uint8_t ka_max_probe_count /* Keep Alive maximum probe counter */; 10197 uint8_t retransmit_count /* Number of times a packet was retransmitted */; 10198#endif 10199#if defined(__BIG_ENDIAN) 10200 uint8_t statistics_counter_id /* The ID of the statistics client for counting common/L2 statistics */; 10201 uint8_t ooo_support_mode; 10202 uint8_t snd_wnd_scale /* 4b only, Far-end window (Snd.Wind.Scale) scale */; 10203 uint8_t dup_ack_count /* Duplicate Ack Counter */; 10204#elif defined(__LITTLE_ENDIAN) 10205 uint8_t dup_ack_count /* Duplicate Ack Counter */; 10206 uint8_t snd_wnd_scale /* 4b only, Far-end window (Snd.Wind.Scale) scale */; 10207 uint8_t ooo_support_mode; 10208 uint8_t statistics_counter_id /* The ID of the statistics client for counting common/L2 statistics */; 10209#endif 10210 uint32_t retransmit_start_time /* Used by retransmit as a recording of start time */; 10211 uint32_t ka_timeout /* Keep Alive timeout */; 10212 uint32_t ka_interval /* Keep Alive interval */; 10213 uint32_t isle_start_seq /* First Out-of-order isle start sequence */; 10214 uint32_t isle_end_seq /* First Out-of-order isle end sequence */; 10215#if defined(__BIG_ENDIAN) 10216 uint16_t second_isle_address /* address of the second isle (if exists) in internal RAM */; 10217 uint16_t recent_seg_wnd /* Last far end window received (not scaled!) */; 10218#elif defined(__LITTLE_ENDIAN) 10219 uint16_t recent_seg_wnd /* Last far end window received (not scaled!) */; 10220 uint16_t second_isle_address /* address of the second isle (if exists) in internal RAM */; 10221#endif 10222#if defined(__BIG_ENDIAN) 10223 uint8_t max_isles_ever_happened /* for statistics only - max number of isles ever happened on this connection */; 10224 uint8_t isles_number /* number of isles */; 10225 uint16_t last_isle_address /* address of the last isle (if exists) in internal RAM */; 10226#elif defined(__LITTLE_ENDIAN) 10227 uint16_t last_isle_address /* address of the last isle (if exists) in internal RAM */; 10228 uint8_t isles_number /* number of isles */; 10229 uint8_t max_isles_ever_happened /* for statistics only - max number of isles ever happened on this connection */; 10230#endif 10231 uint32_t max_rt_time; 10232#if defined(__BIG_ENDIAN) 10233 uint16_t lsb_mac_address /* TX source MAC LSB-16 */; 10234 uint16_t vlan_id /* Connection-configured VLAN ID */; 10235#elif defined(__LITTLE_ENDIAN) 10236 uint16_t vlan_id /* Connection-configured VLAN ID */; 10237 uint16_t lsb_mac_address /* TX source MAC LSB-16 */; 10238#endif 10239#if defined(__BIG_ENDIAN) 10240 uint16_t msb_mac_address /* TX source MAC MSB-16 */; 10241 uint16_t mid_mac_address /* TX source MAC MID-16 */; 10242#elif defined(__LITTLE_ENDIAN) 10243 uint16_t mid_mac_address /* TX source MAC MID-16 */; 10244 uint16_t msb_mac_address /* TX source MAC MSB-16 */; 10245#endif 10246 uint32_t rightmost_received_seq /* The maximum sequence ever received - used for The New Patent */; 10247}; 10248 10249/* 10250 * Termination variables 10251 */ 10252struct iscsi_term_vars 10253{ 10254 uint8_t BitMap; 10255 #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0) /* BitField BitMap tcp state for the termination process */ 10256 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0 10257 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) /* BitField BitMap fin received sticky bit */ 10258 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 10259 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) /* BitField BitMap ack on fin received stick bit */ 10260 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 10261 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6) /* BitField BitMap termination on chip ( option2 ) */ 10262 #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6 10263 #define ISCSI_TERM_VARS_RSRV (0x1<<7) /* BitField BitMap */ 10264 #define ISCSI_TERM_VARS_RSRV_SHIFT 7 10265}; 10266 10267/* 10268 * iSCSI context region, used only in iSCSI 10269 */ 10270struct tstorm_iscsi_st_context_section 10271{ 10272 uint32_t nalPayload /* Non-aligned payload */; 10273 uint32_t b2nh /* Number of bytes to next iSCSI header */; 10274#if defined(__BIG_ENDIAN) 10275 uint16_t rq_cons /* RQ consumer */; 10276 uint8_t flags; 10277 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) /* BitField flags header digest enable, set at login stage */ 10278 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 10279 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) /* BitField flags data digest enable, set at login stage */ 10280 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 10281 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) /* BitField flags partial header flow indication */ 10282 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 10283 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) /* BitField flags */ 10284 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 10285 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) /* BitField flags */ 10286 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 10287 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) /* BitField flags Non-aligned length */ 10288 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5 10289 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) /* BitField flags */ 10290 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7 10291 uint8_t hdr_bytes_2_fetch /* Number of bytes left to fetch to complete iSCSI header */; 10292#elif defined(__LITTLE_ENDIAN) 10293 uint8_t hdr_bytes_2_fetch /* Number of bytes left to fetch to complete iSCSI header */; 10294 uint8_t flags; 10295 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) /* BitField flags header digest enable, set at login stage */ 10296 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 10297 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) /* BitField flags data digest enable, set at login stage */ 10298 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 10299 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) /* BitField flags partial header flow indication */ 10300 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 10301 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) /* BitField flags */ 10302 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 10303 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) /* BitField flags */ 10304 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 10305 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) /* BitField flags Non-aligned length */ 10306 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5 10307 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) /* BitField flags */ 10308 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7 10309 uint16_t rq_cons /* RQ consumer */; 10310#endif 10311 struct regpair_t rq_db_phy_addr; 10312#if defined(__BIG_ENDIAN) 10313 struct iscsi_term_vars term_vars /* Termination variables */; 10314 uint8_t rsrv1; 10315 uint16_t iscsi_conn_id; 10316#elif defined(__LITTLE_ENDIAN) 10317 uint16_t iscsi_conn_id; 10318 uint8_t rsrv1; 10319 struct iscsi_term_vars term_vars /* Termination variables */; 10320#endif 10321 uint32_t process_nxt /* next TCP sequence to be processed by the iSCSI layer. */; 10322}; 10323 10324/* 10325 * The iSCSI non-aggregative context of Tstorm 10326 */ 10327struct tstorm_iscsi_st_context 10328{ 10329 struct tstorm_tcp_st_context_section tcp /* TCP context region, shared in TOE, RDMA and iSCSI */; 10330 struct tstorm_iscsi_st_context_section iscsi /* iSCSI context region, used only in iSCSI */; 10331}; 10332 10333/* 10334 * Ethernet context section, shared in TOE, RDMA and ISCSI 10335 */ 10336struct xstorm_eth_context_section 10337{ 10338#if defined(__BIG_ENDIAN) 10339 uint8_t remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */; 10340 uint8_t remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */; 10341 uint8_t local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */; 10342 uint8_t local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */; 10343#elif defined(__LITTLE_ENDIAN) 10344 uint8_t local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */; 10345 uint8_t local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */; 10346 uint8_t remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */; 10347 uint8_t remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */; 10348#endif 10349#if defined(__BIG_ENDIAN) 10350 uint8_t remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */; 10351 uint8_t remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */; 10352 uint8_t remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */; 10353 uint8_t remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */; 10354#elif defined(__LITTLE_ENDIAN) 10355 uint8_t remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */; 10356 uint8_t remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */; 10357 uint8_t remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */; 10358 uint8_t remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */; 10359#endif 10360#if defined(__BIG_ENDIAN) 10361 uint16_t reserved_vlan_type /* this field is not an absolute must, but the reseved was here */; 10362 uint16_t vlan_params; 10363 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /* BitField vlan_params part of PBF Header Builder Command */ 10364 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 10365 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* BitField vlan_params Canonical format indicator, part of PBF Header Builder Command */ 10366 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 10367 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* BitField vlan_params part of PBF Header Builder Command */ 10368 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 10369#elif defined(__LITTLE_ENDIAN) 10370 uint16_t vlan_params; 10371 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /* BitField vlan_params part of PBF Header Builder Command */ 10372 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 10373 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* BitField vlan_params Canonical format indicator, part of PBF Header Builder Command */ 10374 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 10375 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* BitField vlan_params part of PBF Header Builder Command */ 10376 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 10377 uint16_t reserved_vlan_type /* this field is not an absolute must, but the reseved was here */; 10378#endif 10379#if defined(__BIG_ENDIAN) 10380 uint8_t local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */; 10381 uint8_t local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */; 10382 uint8_t local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */; 10383 uint8_t local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */; 10384#elif defined(__LITTLE_ENDIAN) 10385 uint8_t local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */; 10386 uint8_t local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */; 10387 uint8_t local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */; 10388 uint8_t local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */; 10389#endif 10390}; 10391 10392/* 10393 * IpV4 context section, shared in TOE, RDMA and ISCSI 10394 */ 10395struct xstorm_ip_v4_context_section 10396{ 10397#if defined(__BIG_ENDIAN) 10398 uint16_t __pbf_hdr_cmd_rsvd_id; 10399 uint16_t __pbf_hdr_cmd_rsvd_flags_offset; 10400#elif defined(__LITTLE_ENDIAN) 10401 uint16_t __pbf_hdr_cmd_rsvd_flags_offset; 10402 uint16_t __pbf_hdr_cmd_rsvd_id; 10403#endif 10404#if defined(__BIG_ENDIAN) 10405 uint8_t __pbf_hdr_cmd_rsvd_ver_ihl; 10406 uint8_t tos /* Type Of Service, used in PBF Header Builder Command */; 10407 uint16_t __pbf_hdr_cmd_rsvd_length; 10408#elif defined(__LITTLE_ENDIAN) 10409 uint16_t __pbf_hdr_cmd_rsvd_length; 10410 uint8_t tos /* Type Of Service, used in PBF Header Builder Command */; 10411 uint8_t __pbf_hdr_cmd_rsvd_ver_ihl; 10412#endif 10413 uint32_t ip_local_addr /* used in PBF Header Builder Command */; 10414#if defined(__BIG_ENDIAN) 10415 uint8_t ttl /* Time to live, used in PBF Header Builder Command */; 10416 uint8_t __pbf_hdr_cmd_rsvd_protocol; 10417 uint16_t __pbf_hdr_cmd_rsvd_csum; 10418#elif defined(__LITTLE_ENDIAN) 10419 uint16_t __pbf_hdr_cmd_rsvd_csum; 10420 uint8_t __pbf_hdr_cmd_rsvd_protocol; 10421 uint8_t ttl /* Time to live, used in PBF Header Builder Command */; 10422#endif 10423 uint32_t __pbf_hdr_cmd_rsvd_1 /* places the ip_remote_addr field in the proper place in the regpair */; 10424 uint32_t ip_remote_addr /* used in PBF Header Builder Command */; 10425}; 10426 10427/* 10428 * context section, shared in TOE, RDMA and ISCSI 10429 */ 10430struct xstorm_padded_ip_v4_context_section 10431{ 10432 struct xstorm_ip_v4_context_section ip_v4; 10433 uint32_t reserved1[4]; 10434}; 10435 10436/* 10437 * IpV6 context section, shared in TOE, RDMA and ISCSI 10438 */ 10439struct xstorm_ip_v6_context_section 10440{ 10441#if defined(__BIG_ENDIAN) 10442 uint16_t pbf_hdr_cmd_rsvd_payload_len; 10443 uint8_t pbf_hdr_cmd_rsvd_nxt_hdr; 10444 uint8_t hop_limit /* used in PBF Header Builder Command */; 10445#elif defined(__LITTLE_ENDIAN) 10446 uint8_t hop_limit /* used in PBF Header Builder Command */; 10447 uint8_t pbf_hdr_cmd_rsvd_nxt_hdr; 10448 uint16_t pbf_hdr_cmd_rsvd_payload_len; 10449#endif 10450 uint32_t priority_flow_label; 10451 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0) /* BitField priority_flow_label used in PBF Header Builder Command */ 10452 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0 10453 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20) /* BitField priority_flow_label used in PBF Header Builder Command */ 10454 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20 10455 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28) /* BitField priority_flow_label */ 10456 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28 10457 uint32_t ip_local_addr_lo_hi /* second 32 bits of Ip local Address, used in PBF Header Builder Command */; 10458 uint32_t ip_local_addr_lo_lo /* first 32 bits of Ip local Address, used in PBF Header Builder Command */; 10459 uint32_t ip_local_addr_hi_hi /* fourth 32 bits of Ip local Address, used in PBF Header Builder Command */; 10460 uint32_t ip_local_addr_hi_lo /* third 32 bits of Ip local Address, used in PBF Header Builder Command */; 10461 uint32_t ip_remote_addr_lo_hi /* second 32 bits of Ip remoteinsation Address, used in PBF Header Builder Command */; 10462 uint32_t ip_remote_addr_lo_lo /* first 32 bits of Ip remoteinsation Address, used in PBF Header Builder Command */; 10463 uint32_t ip_remote_addr_hi_hi /* fourth 32 bits of Ip remoteinsation Address, used in PBF Header Builder Command */; 10464 uint32_t ip_remote_addr_hi_lo /* third 32 bits of Ip remoteinsation Address, used in PBF Header Builder Command */; 10465}; 10466 10467union xstorm_ip_context_section_types 10468{ 10469 struct xstorm_padded_ip_v4_context_section padded_ip_v4; 10470 struct xstorm_ip_v6_context_section ip_v6; 10471}; 10472 10473/* 10474 * TCP context section, shared in TOE, RDMA and ISCSI 10475 */ 10476struct xstorm_tcp_context_section 10477{ 10478 uint32_t snd_max; 10479#if defined(__BIG_ENDIAN) 10480 uint16_t remote_port /* used in PBF Header Builder Command */; 10481 uint16_t local_port /* used in PBF Header Builder Command */; 10482#elif defined(__LITTLE_ENDIAN) 10483 uint16_t local_port /* used in PBF Header Builder Command */; 10484 uint16_t remote_port /* used in PBF Header Builder Command */; 10485#endif 10486#if defined(__BIG_ENDIAN) 10487 uint8_t original_nagle_1b; 10488 uint8_t ts_enabled /* Only 1 bit is used */; 10489 uint16_t tcp_params; 10490 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) /* BitField tcp_paramsTcp parameters for ease of pbf command construction */ 10491 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 10492 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) /* BitField tcp_paramsTcp parameters */ 10493 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 10494 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) /* BitField tcp_paramsTcp parameters */ 10495 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 10496 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) /* BitField tcp_paramsTcp parameters Selective Ack Enabled */ 10497 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 10498 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) /* BitField tcp_paramsTcp parameters window smaller than initial window was advertised to far end */ 10499 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11 10500 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) /* BitField tcp_paramsTcp parameters */ 10501 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 10502 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) /* BitField tcp_paramsTcp parameters */ 10503 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 10504 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) /* BitField tcp_paramsTcp parameters */ 10505 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 10506#elif defined(__LITTLE_ENDIAN) 10507 uint16_t tcp_params; 10508 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) /* BitField tcp_paramsTcp parameters for ease of pbf command construction */ 10509 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 10510 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) /* BitField tcp_paramsTcp parameters */ 10511 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 10512 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) /* BitField tcp_paramsTcp parameters */ 10513 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 10514 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) /* BitField tcp_paramsTcp parameters Selective Ack Enabled */ 10515 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 10516 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) /* BitField tcp_paramsTcp parameters window smaller than initial window was advertised to far end */ 10517 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11 10518 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) /* BitField tcp_paramsTcp parameters */ 10519 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 10520 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) /* BitField tcp_paramsTcp parameters */ 10521 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 10522 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) /* BitField tcp_paramsTcp parameters */ 10523 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 10524 uint8_t ts_enabled /* Only 1 bit is used */; 10525 uint8_t original_nagle_1b; 10526#endif 10527#if defined(__BIG_ENDIAN) 10528 uint16_t pseudo_csum /* the precaluclated pseudo checksum header for pbf command construction */; 10529 uint16_t window_scaling_factor /* local_adv_wnd by this variable to reach the advertised window to far end */; 10530#elif defined(__LITTLE_ENDIAN) 10531 uint16_t window_scaling_factor /* local_adv_wnd by this variable to reach the advertised window to far end */; 10532 uint16_t pseudo_csum /* the precaluclated pseudo checksum header for pbf command construction */; 10533#endif 10534#if defined(__BIG_ENDIAN) 10535 uint16_t reserved2 /* The ID of the statistics client for counting common/L2 statistics */; 10536 uint8_t statistics_counter_id /* The ID of the statistics client for counting common/L2 statistics */; 10537 uint8_t statistics_params; 10538 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) /* BitField statistics_paramsTcp parameters set by the driver, determines wheather or not to update l2 statistics */ 10539 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 10540 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) /* BitField statistics_paramsTcp parameters set by the driver, determines wheather or not to update l4 statistics */ 10541 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 10542 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) /* BitField statistics_paramsTcp parameters */ 10543 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2 10544#elif defined(__LITTLE_ENDIAN) 10545 uint8_t statistics_params; 10546 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) /* BitField statistics_paramsTcp parameters set by the driver, determines wheather or not to update l2 statistics */ 10547 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 10548 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) /* BitField statistics_paramsTcp parameters set by the driver, determines wheather or not to update l4 statistics */ 10549 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 10550 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) /* BitField statistics_paramsTcp parameters */ 10551 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2 10552 uint8_t statistics_counter_id /* The ID of the statistics client for counting common/L2 statistics */; 10553 uint16_t reserved2 /* The ID of the statistics client for counting common/L2 statistics */; 10554#endif 10555 uint32_t ts_time_diff /* Time Stamp Offload, used in PBF Header Builder Command */; 10556 uint32_t __next_timer_expir /* Last Packet Real Time Clock Stamp */; 10557}; 10558 10559/* 10560 * Common context section, shared in TOE, RDMA and ISCSI 10561 */ 10562struct xstorm_common_context_section 10563{ 10564 struct xstorm_eth_context_section ethernet; 10565 union xstorm_ip_context_section_types ip_union; 10566 struct xstorm_tcp_context_section tcp; 10567#if defined(__BIG_ENDIAN) 10568 uint8_t __dcb_val; 10569 uint8_t flags; 10570 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) /* BitField flagsTcp parameters part of the tx switching state machine */ 10571 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0 10572 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) /* BitField flagsTcp parameters determines to which voq credit will be returned */ 10573 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1 10574 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) /* BitField flagsTcp parameters Flag that states wether inner valn was provided by the OS */ 10575 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4 10576 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) /* BitField flagsTcp parameters original priority given from the OS */ 10577 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5 10578 uint8_t outer_tag_flags; 10579 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0) /* BitField outer_tag_flagsTcp parameters Priority of outer tag in case of DCB enabled */ 10580 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0 10581 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3) /* BitField outer_tag_flagsTcp parameters Priority of outer tag in case of DCB disabled */ 10582 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI_SHIFT 3 10583 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6) /* BitField outer_tag_flagsTcp parameters */ 10584 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED_SHIFT 6 10585 uint8_t ip_version_1b; 10586#elif defined(__LITTLE_ENDIAN) 10587 uint8_t ip_version_1b; 10588 uint8_t outer_tag_flags; 10589 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0) /* BitField outer_tag_flagsTcp parameters Priority of outer tag in case of DCB enabled */ 10590 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0 10591 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3) /* BitField outer_tag_flagsTcp parameters Priority of outer tag in case of DCB disabled */ 10592 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI_SHIFT 3 10593 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6) /* BitField outer_tag_flagsTcp parameters */ 10594 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED_SHIFT 6 10595 uint8_t flags; 10596 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) /* BitField flagsTcp parameters part of the tx switching state machine */ 10597 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0 10598 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) /* BitField flagsTcp parameters determines to which voq credit will be returned */ 10599 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1 10600 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) /* BitField flagsTcp parameters Flag that states wether inner valn was provided by the OS */ 10601 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4 10602 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) /* BitField flagsTcp parameters original priority given from the OS */ 10603 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5 10604 uint8_t __dcb_val; 10605#endif 10606}; 10607 10608/* 10609 * Flags used in ISCSI context section 10610 */ 10611struct xstorm_iscsi_context_flags 10612{ 10613 uint8_t flags; 10614 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0) /* BitField flags */ 10615 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0 10616 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1) /* BitField flags */ 10617 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1 10618 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2) /* BitField flags */ 10619 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2 10620 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3) /* BitField flags */ 10621 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3 10622 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4) /* BitField flags */ 10623 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4 10624 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5) /* BitField flags */ 10625 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5 10626 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6) /* BitField flags */ 10627 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6 10628 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7) /* BitField flags */ 10629 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7 10630}; 10631 10632struct iscsi_task_context_entry_x 10633{ 10634 uint32_t data_out_buffer_offset; 10635 uint32_t itt; 10636 uint32_t data_sn; 10637}; 10638 10639struct iscsi_task_context_entry_xuc_x_write_only 10640{ 10641 uint32_t tx_r2t_sn /* Xstorm increments for every data-out seq sent. */; 10642}; 10643 10644struct iscsi_task_context_entry_xuc_xu_write_both 10645{ 10646 uint32_t sgl_base_lo; 10647 uint32_t sgl_base_hi; 10648#if defined(__BIG_ENDIAN) 10649 uint8_t sgl_size; 10650 uint8_t sge_index; 10651 uint16_t sge_offset; 10652#elif defined(__LITTLE_ENDIAN) 10653 uint16_t sge_offset; 10654 uint8_t sge_index; 10655 uint8_t sgl_size; 10656#endif 10657}; 10658 10659/* 10660 * iSCSI context section 10661 */ 10662struct xstorm_iscsi_context_section 10663{ 10664 uint32_t first_burst_length; 10665 uint32_t max_send_pdu_length; 10666 struct regpair_t sq_pbl_base; 10667 struct regpair_t sq_curr_pbe; 10668 struct regpair_t hq_pbl_base; 10669 struct regpair_t hq_curr_pbe_base; 10670 struct regpair_t r2tq_pbl_base; 10671 struct regpair_t r2tq_curr_pbe_base; 10672 struct regpair_t task_pbl_base; 10673#if defined(__BIG_ENDIAN) 10674 uint16_t data_out_count; 10675 struct xstorm_iscsi_context_flags flags; 10676 uint8_t task_pbl_cache_idx /* All-ones value stands for PBL not cached */; 10677#elif defined(__LITTLE_ENDIAN) 10678 uint8_t task_pbl_cache_idx /* All-ones value stands for PBL not cached */; 10679 struct xstorm_iscsi_context_flags flags; 10680 uint16_t data_out_count; 10681#endif 10682 uint32_t seq_more_2_send; 10683 uint32_t pdu_more_2_send; 10684 struct iscsi_task_context_entry_x temp_tce_x; 10685 struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr; 10686 struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr; 10687 struct regpair_t lun; 10688 uint32_t exp_data_transfer_len_ttt /* Overloaded with ttt in multi-pdu sequences flow. */; 10689 uint32_t pdu_data_2_rxmit; 10690 uint32_t rxmit_bytes_2_dr; 10691#if defined(__BIG_ENDIAN) 10692 uint16_t rxmit_sge_offset; 10693 uint16_t hq_rxmit_cons; 10694#elif defined(__LITTLE_ENDIAN) 10695 uint16_t hq_rxmit_cons; 10696 uint16_t rxmit_sge_offset; 10697#endif 10698#if defined(__BIG_ENDIAN) 10699 uint16_t r2tq_cons; 10700 uint8_t rxmit_flags; 10701 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) /* BitField rxmit_flags */ 10702 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 10703 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) /* BitField rxmit_flags */ 10704 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 10705 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) /* BitField rxmit_flags */ 10706 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 10707 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) /* BitField rxmit_flags */ 10708 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 10709 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) /* BitField rxmit_flags */ 10710 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 10711 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) /* BitField rxmit_flags */ 10712 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 10713 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) /* BitField rxmit_flags */ 10714 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 10715 uint8_t rxmit_sge_idx; 10716#elif defined(__LITTLE_ENDIAN) 10717 uint8_t rxmit_sge_idx; 10718 uint8_t rxmit_flags; 10719 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) /* BitField rxmit_flags */ 10720 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 10721 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) /* BitField rxmit_flags */ 10722 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 10723 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) /* BitField rxmit_flags */ 10724 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 10725 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) /* BitField rxmit_flags */ 10726 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 10727 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) /* BitField rxmit_flags */ 10728 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 10729 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) /* BitField rxmit_flags */ 10730 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 10731 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) /* BitField rxmit_flags */ 10732 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 10733 uint16_t r2tq_cons; 10734#endif 10735 uint32_t hq_rxmit_tcp_seq; 10736}; 10737 10738/* 10739 * Xstorm iSCSI Storm Context 10740 */ 10741struct xstorm_iscsi_st_context 10742{ 10743 struct xstorm_common_context_section common; 10744 struct xstorm_iscsi_context_section iscsi; 10745}; 10746 10747/* 10748 * Iscsi connection context 10749 */ 10750struct iscsi_context 10751{ 10752 struct ustorm_iscsi_st_context ustorm_st_context /* Ustorm storm context */; 10753 struct tstorm_iscsi_st_context tstorm_st_context /* Tstorm storm context */; 10754 struct xstorm_iscsi_ag_context xstorm_ag_context /* Xstorm aggregative context */; 10755 struct tstorm_iscsi_ag_context tstorm_ag_context /* Tstorm aggregative context */; 10756 struct cstorm_iscsi_ag_context cstorm_ag_context /* Cstorm aggregative context */; 10757 struct ustorm_iscsi_ag_context ustorm_ag_context /* Ustorm aggregative context */; 10758 struct timers_block_context timers_context /* Timers block context */; 10759 struct regpair_t upb_context /* UPb context */; 10760 struct xstorm_iscsi_st_context xstorm_st_context /* Xstorm storm context */; 10761 struct regpair_t xpb_context /* XPb context (inside the PBF) */; 10762 struct cstorm_iscsi_st_context cstorm_st_context /* Cstorm storm context */; 10763}; 10764 10765 10766/* 10767 * PDU header of an iSCSI DATA-OUT 10768 */ 10769struct iscsi_data_pdu_hdr_little_endian 10770{ 10771#if defined(__BIG_ENDIAN) 10772 uint8_t opcode; 10773 uint8_t op_attr; 10774 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* BitField op_attr */ 10775 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 10776 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* BitField op_attr */ 10777 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 10778 uint16_t rsrv0; 10779#elif defined(__LITTLE_ENDIAN) 10780 uint16_t rsrv0; 10781 uint8_t op_attr; 10782 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* BitField op_attr */ 10783 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 10784 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* BitField op_attr */ 10785 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 10786 uint8_t opcode; 10787#endif 10788 uint32_t data_fields; 10789 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ 10790 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 10791 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ 10792 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 10793 struct regpair_t lun; 10794 uint32_t itt; 10795 uint32_t ttt; 10796 uint32_t rsrv2; 10797 uint32_t exp_stat_sn; 10798 uint32_t rsrv3; 10799 uint32_t data_sn; 10800 uint32_t buffer_offset; 10801 uint32_t rsrv4; 10802}; 10803 10804 10805/* 10806 * PDU header of an iSCSI login request 10807 */ 10808struct iscsi_login_req_hdr_little_endian 10809{ 10810#if defined(__BIG_ENDIAN) 10811 uint8_t opcode; 10812 uint8_t op_attr; 10813 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) /* BitField op_attr */ 10814 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0 10815 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) /* BitField op_attr */ 10816 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2 10817 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) /* BitField op_attr */ 10818 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4 10819 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* BitField op_attr */ 10820 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 10821 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) /* BitField op_attr */ 10822 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7 10823 uint8_t version_max; 10824 uint8_t version_min; 10825#elif defined(__LITTLE_ENDIAN) 10826 uint8_t version_min; 10827 uint8_t version_max; 10828 uint8_t op_attr; 10829 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) /* BitField op_attr */ 10830 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0 10831 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) /* BitField op_attr */ 10832 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2 10833 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) /* BitField op_attr */ 10834 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4 10835 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* BitField op_attr */ 10836 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 10837 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) /* BitField op_attr */ 10838 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7 10839 uint8_t opcode; 10840#endif 10841 uint32_t data_fields; 10842 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ 10843 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 10844 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ 10845 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 10846 uint32_t isid_lo; 10847#if defined(__BIG_ENDIAN) 10848 uint16_t isid_hi; 10849 uint16_t tsih; 10850#elif defined(__LITTLE_ENDIAN) 10851 uint16_t tsih; 10852 uint16_t isid_hi; 10853#endif 10854 uint32_t itt; 10855#if defined(__BIG_ENDIAN) 10856 uint16_t cid; 10857 uint16_t rsrv1; 10858#elif defined(__LITTLE_ENDIAN) 10859 uint16_t rsrv1; 10860 uint16_t cid; 10861#endif 10862 uint32_t cmd_sn; 10863 uint32_t exp_stat_sn; 10864 uint32_t rsrv2[4]; 10865}; 10866 10867/* 10868 * PDU header of an iSCSI logout request 10869 */ 10870struct iscsi_logout_req_hdr_little_endian 10871{ 10872#if defined(__BIG_ENDIAN) 10873 uint8_t opcode; 10874 uint8_t op_attr; 10875 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) /* BitField op_attr */ 10876 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0 10877 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* BitField op_attr this value must be 1 */ 10878 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 10879 uint16_t rsrv0; 10880#elif defined(__LITTLE_ENDIAN) 10881 uint16_t rsrv0; 10882 uint8_t op_attr; 10883 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) /* BitField op_attr */ 10884 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0 10885 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* BitField op_attr this value must be 1 */ 10886 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 10887 uint8_t opcode; 10888#endif 10889 uint32_t data_fields; 10890 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ 10891 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 10892 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ 10893 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 10894 uint32_t rsrv2[2]; 10895 uint32_t itt; 10896#if defined(__BIG_ENDIAN) 10897 uint16_t cid; 10898 uint16_t rsrv1; 10899#elif defined(__LITTLE_ENDIAN) 10900 uint16_t rsrv1; 10901 uint16_t cid; 10902#endif 10903 uint32_t cmd_sn; 10904 uint32_t exp_stat_sn; 10905 uint32_t rsrv3[4]; 10906}; 10907 10908/* 10909 * PDU header of an iSCSI TMF request 10910 */ 10911struct iscsi_tmf_req_hdr_little_endian 10912{ 10913#if defined(__BIG_ENDIAN) 10914 uint8_t opcode; 10915 uint8_t op_attr; 10916 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) /* BitField op_attr */ 10917 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0 10918 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* BitField op_attr this value must be 1 */ 10919 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 10920 uint16_t rsrv0; 10921#elif defined(__LITTLE_ENDIAN) 10922 uint16_t rsrv0; 10923 uint8_t op_attr; 10924 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) /* BitField op_attr */ 10925 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0 10926 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* BitField op_attr this value must be 1 */ 10927 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 10928 uint8_t opcode; 10929#endif 10930 uint32_t data_fields; 10931 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ 10932 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 10933 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ 10934 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 10935 struct regpair_t lun; 10936 uint32_t itt; 10937 uint32_t referenced_task_tag; 10938 uint32_t cmd_sn; 10939 uint32_t exp_stat_sn; 10940 uint32_t ref_cmd_sn; 10941 uint32_t exp_data_sn; 10942 uint32_t rsrv2[2]; 10943}; 10944 10945/* 10946 * PDU header of an iSCSI Text request 10947 */ 10948struct iscsi_text_req_hdr_little_endian 10949{ 10950#if defined(__BIG_ENDIAN) 10951 uint8_t opcode; 10952 uint8_t op_attr; 10953 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) /* BitField op_attr */ 10954 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 10955 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* BitField op_attr */ 10956 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 10957 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) /* BitField op_attr */ 10958 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7 10959 uint16_t rsrv0; 10960#elif defined(__LITTLE_ENDIAN) 10961 uint16_t rsrv0; 10962 uint8_t op_attr; 10963 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) /* BitField op_attr */ 10964 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 10965 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* BitField op_attr */ 10966 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 10967 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) /* BitField op_attr */ 10968 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7 10969 uint8_t opcode; 10970#endif 10971 uint32_t data_fields; 10972 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ 10973 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 10974 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ 10975 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 10976 struct regpair_t lun; 10977 uint32_t itt; 10978 uint32_t ttt; 10979 uint32_t cmd_sn; 10980 uint32_t exp_stat_sn; 10981 uint32_t rsrv3[4]; 10982}; 10983 10984/* 10985 * PDU header of an iSCSI Nop-Out 10986 */ 10987struct iscsi_nop_out_hdr_little_endian 10988{ 10989#if defined(__BIG_ENDIAN) 10990 uint8_t opcode; 10991 uint8_t op_attr; 10992 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* BitField op_attr */ 10993 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 10994 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) /* BitField op_attr this reserved bit must be set to 1 */ 10995 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7 10996 uint16_t rsrv0; 10997#elif defined(__LITTLE_ENDIAN) 10998 uint16_t rsrv0; 10999 uint8_t op_attr; 11000 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* BitField op_attr */ 11001 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 11002 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) /* BitField op_attr this reserved bit must be set to 1 */ 11003 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7 11004 uint8_t opcode; 11005#endif 11006 uint32_t data_fields; 11007 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ 11008 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 11009 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ 11010 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 11011 struct regpair_t lun; 11012 uint32_t itt; 11013 uint32_t ttt; 11014 uint32_t cmd_sn; 11015 uint32_t exp_stat_sn; 11016 uint32_t rsrv3[4]; 11017}; 11018 11019/* 11020 * iscsi pdu headers in little endian form. 11021 */ 11022union iscsi_pdu_headers_little_endian 11023{ 11024 uint32_t fullHeaderSize[12] /* The full size of the header. protects the union size */; 11025 struct iscsi_cmd_pdu_hdr_little_endian command_pdu_hdr /* PDU header of an iSCSI command - read,write */; 11026 struct iscsi_data_pdu_hdr_little_endian data_out_pdu_hdr /* PDU header of an iSCSI DATA-IN and DATA-OUT PDU */; 11027 struct iscsi_login_req_hdr_little_endian login_req_pdu_hdr /* PDU header of an iSCSI Login request */; 11028 struct iscsi_logout_req_hdr_little_endian logout_req_pdu_hdr /* PDU header of an iSCSI Logout request */; 11029 struct iscsi_tmf_req_hdr_little_endian tmf_req_pdu_hdr /* PDU header of an iSCSI TMF request */; 11030 struct iscsi_text_req_hdr_little_endian text_req_pdu_hdr /* PDU header of an iSCSI Text request */; 11031 struct iscsi_nop_out_hdr_little_endian nop_out_pdu_hdr /* PDU header of an iSCSI Nop-Out */; 11032}; 11033 11034struct iscsi_hq_bd 11035{ 11036 union iscsi_pdu_headers_little_endian pdu_header; 11037#if defined(__BIG_ENDIAN) 11038 uint16_t reserved1; 11039 uint16_t lcl_cmp_flg; 11040#elif defined(__LITTLE_ENDIAN) 11041 uint16_t lcl_cmp_flg; 11042 uint16_t reserved1; 11043#endif 11044 uint32_t sgl_base_lo; 11045 uint32_t sgl_base_hi; 11046#if defined(__BIG_ENDIAN) 11047 uint8_t sgl_size; 11048 uint8_t sge_index; 11049 uint16_t sge_offset; 11050#elif defined(__LITTLE_ENDIAN) 11051 uint16_t sge_offset; 11052 uint8_t sge_index; 11053 uint8_t sgl_size; 11054#endif 11055}; 11056 11057 11058/* 11059 * CQE data for L2 OOO connection $$KEEP_ENDIANNESS$$ 11060 */ 11061struct iscsi_l2_ooo_data 11062{ 11063 uint32_t iscsi_cid /* iSCSI context ID */; 11064 uint8_t drop_isle /* isle number of the first isle to drop */; 11065 uint8_t drop_size /* number of isles to drop */; 11066 uint8_t ooo_opcode /* Out Of Order opcode (use enum tcp_ooo_event */; 11067 uint8_t ooo_isle /* OOO isle number to add the packet to */; 11068 uint8_t reserved[8]; 11069}; 11070 11071 11072struct iscsi_task_context_entry_xuc_c_write_only 11073{ 11074 uint32_t total_data_acked /* Xstorm inits to zero. C increments. U validates */; 11075}; 11076 11077struct iscsi_task_context_r2t_table_entry 11078{ 11079 uint32_t ttt; 11080 uint32_t desired_data_len; 11081}; 11082 11083struct iscsi_task_context_entry_xuc_u_write_only 11084{ 11085 uint32_t exp_r2t_sn /* Xstorm inits to zero. U increments. */; 11086 struct iscsi_task_context_r2t_table_entry r2t_table[4] /* U updates. X reads */; 11087#if defined(__BIG_ENDIAN) 11088 uint16_t data_in_count /* X inits to zero. U increments. */; 11089 uint8_t cq_id /* X inits to zero. U uses. */; 11090 uint8_t valid_1b /* X sets. U resets. */; 11091#elif defined(__LITTLE_ENDIAN) 11092 uint8_t valid_1b /* X sets. U resets. */; 11093 uint8_t cq_id /* X inits to zero. U uses. */; 11094 uint16_t data_in_count /* X inits to zero. U increments. */; 11095#endif 11096}; 11097 11098struct iscsi_task_context_entry_xuc 11099{ 11100 struct iscsi_task_context_entry_xuc_c_write_only write_c /* Cstorm only inits data here, without further change by any storm. */; 11101 uint32_t exp_data_transfer_len /* Xstorm only inits data here. */; 11102 struct iscsi_task_context_entry_xuc_x_write_only write_x /* only Xstorm writes data here. */; 11103 uint32_t lun_lo /* Xstorm only inits data here. */; 11104 struct iscsi_task_context_entry_xuc_xu_write_both write_xu /* Both X and U update this struct, but in different flow. */; 11105 uint32_t lun_hi /* Xstorm only inits data here. */; 11106 struct iscsi_task_context_entry_xuc_u_write_only write_u /* Ustorm only inits data here, without further change by any storm. */; 11107}; 11108 11109struct iscsi_task_context_entry_u 11110{ 11111 uint32_t exp_r2t_buff_offset; 11112 uint32_t rem_rcv_len; 11113 uint32_t exp_data_sn; 11114}; 11115 11116struct iscsi_task_context_entry 11117{ 11118 struct iscsi_task_context_entry_x tce_x; 11119#if defined(__BIG_ENDIAN) 11120 uint16_t data_out_count; 11121 uint16_t rsrv0; 11122#elif defined(__LITTLE_ENDIAN) 11123 uint16_t rsrv0; 11124 uint16_t data_out_count; 11125#endif 11126 struct iscsi_task_context_entry_xuc tce_xuc; 11127 struct iscsi_task_context_entry_u tce_u; 11128 uint32_t rsrv1[7] /* increase the size to 128 bytes */; 11129}; 11130 11131 11132struct iscsi_task_context_entry_xuc_x_init_only 11133{ 11134 struct regpair_t lun /* X inits. U validates */; 11135 uint32_t exp_data_transfer_len /* Xstorm inits to SQ WQE data. U validates */; 11136}; 11137 11138 11139/* 11140 * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$ 11141 */ 11142struct afex_vif_list_ramrod_data 11143{ 11144 uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */; 11145 uint8_t func_bit_map /* the function bit map to set */; 11146 uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */; 11147 uint8_t func_to_clear /* the func id to clear in case of clear func mode */; 11148 uint8_t echo; 11149 uint16_t reserved1; 11150}; 11151 11152 11153/* 11154 * $$KEEP_ENDIANNESS$$ 11155 */ 11156struct c2s_pri_trans_table_entry 11157{ 11158 uint8_t val[MAX_VLAN_PRIORITIES] /* Inner to outer vlan priority translation table entry for current PF */; 11159}; 11160 11161 11162/* 11163 * cfc delete event data $$KEEP_ENDIANNESS$$ 11164 */ 11165struct cfc_del_event_data 11166{ 11167 uint32_t cid /* cid of deleted connection */; 11168 uint32_t reserved0; 11169 uint32_t reserved1; 11170}; 11171 11172 11173/* 11174 * per-port SAFC demo variables 11175 */ 11176struct cmng_flags_per_port 11177{ 11178 uint32_t cmng_enables; 11179 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */ 11180 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 11181 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */ 11182 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 11183 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */ 11184 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 11185 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */ 11186 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 11187 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */ 11188 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 11189 uint32_t __reserved1; 11190}; 11191 11192 11193/* 11194 * per-port rate shaping variables 11195 */ 11196struct rate_shaping_vars_per_port 11197{ 11198 uint32_t rs_periodic_timeout /* timeout of periodic timer */; 11199 uint32_t rs_threshold /* threshold, below which we start to stop queues */; 11200}; 11201 11202/* 11203 * per-port fairness variables 11204 */ 11205struct fairness_vars_per_port 11206{ 11207 uint32_t upper_bound /* Quota for a protocol/vnic */; 11208 uint32_t fair_threshold /* almost-empty threshold */; 11209 uint32_t fairness_timeout /* timeout of fairness timer */; 11210 uint32_t reserved0; 11211}; 11212 11213/* 11214 * per-port SAFC variables 11215 */ 11216struct safc_struct_per_port 11217{ 11218#if defined(__BIG_ENDIAN) 11219 uint16_t __reserved1; 11220 uint8_t __reserved0; 11221 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 11222#elif defined(__LITTLE_ENDIAN) 11223 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 11224 uint8_t __reserved0; 11225 uint16_t __reserved1; 11226#endif 11227 uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */; 11228 uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */; 11229}; 11230 11231/* 11232 * Per-port congestion management variables 11233 */ 11234struct cmng_struct_per_port 11235{ 11236 struct rate_shaping_vars_per_port rs_vars; 11237 struct fairness_vars_per_port fair_vars; 11238 struct safc_struct_per_port safc_vars; 11239 struct cmng_flags_per_port flags; 11240}; 11241 11242/* 11243 * a single rate shaping counter. can be used as protocol or vnic counter 11244 */ 11245struct rate_shaping_counter 11246{ 11247 uint32_t quota /* Quota for a protocol/vnic */; 11248#if defined(__BIG_ENDIAN) 11249 uint16_t __reserved0; 11250 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 11251#elif defined(__LITTLE_ENDIAN) 11252 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 11253 uint16_t __reserved0; 11254#endif 11255}; 11256 11257/* 11258 * per-vnic rate shaping variables 11259 */ 11260struct rate_shaping_vars_per_vn 11261{ 11262 struct rate_shaping_counter vn_counter /* per-vnic counter */; 11263}; 11264 11265/* 11266 * per-vnic fairness variables 11267 */ 11268struct fairness_vars_per_vn 11269{ 11270 uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */; 11271 uint32_t vn_credit_delta /* used for incrementing the credit */; 11272 uint32_t __reserved0; 11273}; 11274 11275/* 11276 * cmng port init state 11277 */ 11278struct cmng_vnic 11279{ 11280 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 11281 struct fairness_vars_per_vn vnic_min_rate[4]; 11282}; 11283 11284/* 11285 * cmng port init state 11286 */ 11287struct cmng_init 11288{ 11289 struct cmng_struct_per_port port; 11290 struct cmng_vnic vnic; 11291}; 11292 11293 11294/* 11295 * driver parameters for congestion management init, all rates are in Mbps 11296 */ 11297struct cmng_init_input 11298{ 11299 uint32_t port_rate; 11300 uint16_t vnic_min_rate[4] /* rates are in Mbps */; 11301 uint16_t vnic_max_rate[4] /* rates are in Mbps */; 11302 uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */; 11303 uint16_t cos_to_pause_mask[MAX_COS_NUMBER]; 11304 struct cmng_flags_per_port flags; 11305}; 11306 11307 11308/* 11309 * Protocol-common command ID for slow path elements 11310 */ 11311enum common_spqe_cmd_id 11312{ 11313 RAMROD_CMD_ID_COMMON_UNUSED, 11314 RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */, 11315 RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */, 11316 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */, 11317 RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */, 11318 RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 11319 RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */, 11320 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 11321 RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 11322 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */, 11323 RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 11324 MAX_COMMON_SPQE_CMD_ID}; 11325 11326 11327/* 11328 * Per-protocol connection types 11329 */ 11330enum connection_type 11331{ 11332 ETH_CONNECTION_TYPE /* Ethernet */, 11333 TOE_CONNECTION_TYPE /* TOE */, 11334 RDMA_CONNECTION_TYPE /* RDMA */, 11335 ISCSI_CONNECTION_TYPE /* iSCSI */, 11336 FCOE_CONNECTION_TYPE /* FCoE */, 11337 RESERVED_CONNECTION_TYPE_0, 11338 RESERVED_CONNECTION_TYPE_1, 11339 RESERVED_CONNECTION_TYPE_2, 11340 NONE_CONNECTION_TYPE /* General- used for common slow path */, 11341 MAX_CONNECTION_TYPE}; 11342 11343 11344/* 11345 * Cos modes 11346 */ 11347enum cos_mode 11348{ 11349 OVERRIDE_COS /* Firmware deduce cos according to DCB */, 11350 STATIC_COS /* Firmware has constant queues per CoS */, 11351 FW_WRR /* Firmware keep fairness between different CoSes */, 11352 MAX_COS_MODE}; 11353 11354 11355/* 11356 * Dynamic HC counters set by the driver 11357 */ 11358struct hc_dynamic_drv_counter 11359{ 11360 uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */; 11361}; 11362 11363/* 11364 * zone A per-queue data 11365 */ 11366struct cstorm_queue_zone_data 11367{ 11368 struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */; 11369 struct regpair_t reserved[2]; 11370}; 11371 11372 11373/* 11374 * Vf-PF channel data in cstorm ram (non-triggered zone) 11375 */ 11376struct vf_pf_channel_zone_data 11377{ 11378 uint32_t msg_addr_lo /* the message address on VF memory */; 11379 uint32_t msg_addr_hi /* the message address on VF memory */; 11380}; 11381 11382/* 11383 * zone for VF non-triggered data 11384 */ 11385struct non_trigger_vf_zone 11386{ 11387 struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */; 11388}; 11389 11390/* 11391 * Vf-PF channel trigger zone in cstorm ram 11392 */ 11393struct vf_pf_channel_zone_trigger 11394{ 11395 uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */; 11396}; 11397 11398/* 11399 * zone that triggers the in-bound interrupt 11400 */ 11401struct trigger_vf_zone 11402{ 11403#if defined(__BIG_ENDIAN) 11404 uint16_t reserved1; 11405 uint8_t reserved0; 11406 struct vf_pf_channel_zone_trigger vf_pf_channel; 11407#elif defined(__LITTLE_ENDIAN) 11408 struct vf_pf_channel_zone_trigger vf_pf_channel; 11409 uint8_t reserved0; 11410 uint16_t reserved1; 11411#endif 11412 uint32_t reserved2; 11413}; 11414 11415/* 11416 * zone B per-VF data 11417 */ 11418struct cstorm_vf_zone_data 11419{ 11420 struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */; 11421 struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */; 11422}; 11423 11424 11425/* 11426 * Dynamic host coalescing init parameters, per state machine 11427 */ 11428struct dynamic_hc_sm_config 11429{ 11430 uint32_t threshold[3] /* thresholds of number of outstanding bytes */; 11431 uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */; 11432 uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */; 11433 uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */; 11434 uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */; 11435 uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */; 11436}; 11437 11438/* 11439 * Dynamic host coalescing init parameters 11440 */ 11441struct dynamic_hc_config 11442{ 11443 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */; 11444}; 11445 11446 11447struct e2_integ_data 11448{ 11449#if defined(__BIG_ENDIAN) 11450 uint8_t flags; 11451 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 11452 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 11453 #define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 11454 #define E2_INTEG_DATA_LB_TX_SHIFT 1 11455 #define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 11456 #define E2_INTEG_DATA_COS_TX_SHIFT 2 11457 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 11458 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 11459 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 11460 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 11461 #define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 11462 #define E2_INTEG_DATA_RESERVED_SHIFT 5 11463 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 11464 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 11465 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 11466#elif defined(__LITTLE_ENDIAN) 11467 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 11468 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 11469 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 11470 uint8_t flags; 11471 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 11472 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 11473 #define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 11474 #define E2_INTEG_DATA_LB_TX_SHIFT 1 11475 #define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 11476 #define E2_INTEG_DATA_COS_TX_SHIFT 2 11477 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 11478 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 11479 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 11480 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 11481 #define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 11482 #define E2_INTEG_DATA_RESERVED_SHIFT 5 11483#endif 11484#if defined(__BIG_ENDIAN) 11485 uint16_t reserved3; 11486 uint8_t reserved2; 11487 uint8_t ramEn /* context area reserved for reading enable bit from ram */; 11488#elif defined(__LITTLE_ENDIAN) 11489 uint8_t ramEn /* context area reserved for reading enable bit from ram */; 11490 uint8_t reserved2; 11491 uint16_t reserved3; 11492#endif 11493}; 11494 11495 11496/* 11497 * set mac event data $$KEEP_ENDIANNESS$$ 11498 */ 11499struct eth_event_data 11500{ 11501 uint32_t echo /* set mac echo data to return to driver */; 11502 uint32_t reserved0; 11503 uint32_t reserved1; 11504}; 11505 11506 11507/* 11508 * pf-vf event data $$KEEP_ENDIANNESS$$ 11509 */ 11510struct vf_pf_event_data 11511{ 11512 uint8_t vf_id /* VF ID (0-63) */; 11513 uint8_t reserved0; 11514 uint16_t reserved1; 11515 uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */; 11516 uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */; 11517}; 11518 11519/* 11520 * VF FLR event data $$KEEP_ENDIANNESS$$ 11521 */ 11522struct vf_flr_event_data 11523{ 11524 uint8_t vf_id /* VF ID (0-63) */; 11525 uint8_t reserved0; 11526 uint16_t reserved1; 11527 uint32_t reserved2; 11528 uint32_t reserved3; 11529}; 11530 11531/* 11532 * malicious VF event data $$KEEP_ENDIANNESS$$ 11533 */ 11534struct malicious_vf_event_data 11535{ 11536 uint8_t vf_id /* VF ID (0-63) */; 11537 uint8_t err_id /* reason for malicious notification */; 11538 uint16_t reserved1; 11539 uint32_t reserved2; 11540 uint32_t reserved3; 11541}; 11542 11543/* 11544 * vif list event data $$KEEP_ENDIANNESS$$ 11545 */ 11546struct vif_list_event_data 11547{ 11548 uint8_t func_bit_map /* bit map of pf indice */; 11549 uint8_t echo; 11550 uint16_t reserved0; 11551 uint32_t reserved1; 11552 uint32_t reserved2; 11553}; 11554 11555/* 11556 * function update event data $$KEEP_ENDIANNESS$$ 11557 */ 11558struct function_update_event_data 11559{ 11560 uint8_t echo; 11561 uint8_t reserved; 11562 uint16_t reserved0; 11563 uint32_t reserved1; 11564 uint32_t reserved2; 11565}; 11566 11567/* 11568 * union for all event ring message types 11569 */ 11570union event_data 11571{ 11572 struct vf_pf_event_data vf_pf_event /* vf-pf event data */; 11573 struct eth_event_data eth_event /* set mac event data */; 11574 struct cfc_del_event_data cfc_del_event /* cfc delete event data */; 11575 struct vf_flr_event_data vf_flr_event /* vf flr event data */; 11576 struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */; 11577 struct vif_list_event_data vif_list_event /* vif list event data */; 11578 struct function_update_event_data function_update_event /* function update event data */; 11579}; 11580 11581 11582/* 11583 * per PF event ring data 11584 */ 11585struct event_ring_data 11586{ 11587 struct regpair_native_t base_addr /* ring base address */; 11588#if defined(__BIG_ENDIAN) 11589 uint8_t index_id /* index ID within the status block */; 11590 uint8_t sb_id /* status block ID */; 11591 uint16_t producer /* event ring producer */; 11592#elif defined(__LITTLE_ENDIAN) 11593 uint16_t producer /* event ring producer */; 11594 uint8_t sb_id /* status block ID */; 11595 uint8_t index_id /* index ID within the status block */; 11596#endif 11597 uint32_t reserved0; 11598}; 11599 11600 11601/* 11602 * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$ 11603 */ 11604struct event_ring_msg 11605{ 11606 uint8_t opcode; 11607 uint8_t error /* error on the mesasage */; 11608 uint16_t reserved1; 11609 union event_data data /* message data (96 bits data) */; 11610}; 11611 11612/* 11613 * event ring next page element (128 bits) 11614 */ 11615struct event_ring_next 11616{ 11617 struct regpair_t addr /* Address of the next page of the ring */; 11618 uint32_t reserved[2]; 11619}; 11620 11621/* 11622 * union for event ring element types (each element is 128 bits) 11623 */ 11624union event_ring_elem 11625{ 11626 struct event_ring_msg message /* event ring message */; 11627 struct event_ring_next next_page /* event ring next page */; 11628}; 11629 11630 11631/* 11632 * Common event ring opcodes 11633 */ 11634enum event_ring_opcode 11635{ 11636 EVENT_RING_OPCODE_VF_PF_CHANNEL, 11637 EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */, 11638 EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */, 11639 EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */, 11640 EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 11641 EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */, 11642 EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 11643 EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 11644 EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */, 11645 EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */, 11646 EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */, 11647 EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */, 11648 EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */, 11649 EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */, 11650 EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */, 11651 EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */, 11652 EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 11653 EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 11654 EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 11655 MAX_EVENT_RING_OPCODE}; 11656 11657 11658/* 11659 * Modes for fairness algorithm 11660 */ 11661enum fairness_mode 11662{ 11663 FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */, 11664 FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */, 11665 MAX_FAIRNESS_MODE}; 11666 11667 11668/* 11669 * Priority and cos $$KEEP_ENDIANNESS$$ 11670 */ 11671struct priority_cos 11672{ 11673 uint8_t priority /* Priority */; 11674 uint8_t cos /* Cos */; 11675 uint16_t reserved1; 11676}; 11677 11678/* 11679 * The data for flow control configuration $$KEEP_ENDIANNESS$$ 11680 */ 11681struct flow_control_configuration 11682{ 11683 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */; 11684 uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */; 11685 uint8_t dcb_version /* DCB version Increase by one on each DCB update */; 11686 uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */; 11687 uint8_t reserved1; 11688 uint32_t reserved2; 11689 uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES] /* Indicates the updated DCB outer tag priority per protocol */; 11690}; 11691 11692 11693/* 11694 * $$KEEP_ENDIANNESS$$ 11695 */ 11696struct function_start_data 11697{ 11698 uint8_t function_mode /* the function mode */; 11699 uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode. (E2/E3 Only) */; 11700 uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */; 11701 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 11702 uint8_t path_id; 11703 uint8_t network_cos_mode /* The cos mode for network traffic. */; 11704 uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */; 11705 uint8_t no_added_tags /* If set, the mfTag length is always zero (used in UFP) */; 11706 uint16_t reserved0; 11707 uint32_t reserved1; 11708 uint8_t inner_clss_vxlan /* Classification type for VXLAN */; 11709 uint8_t inner_clss_l2gre /* If set, classification on the inner MAC/VLAN of L2GRE tunneled packets is enabled */; 11710 uint8_t inner_clss_l2geneve /* If set, classification on the inner MAC/(VLAN or VNI) of L2GENEVE tunneled packets is enabled */; 11711 uint8_t inner_rss /* If set, RSS on the inner headers of tunneled packets is enabled */; 11712 uint16_t vxlan_dst_port /* UDP Destination Port to be recognised as VXLAN tunneled packets (0 is disabled) */; 11713 uint16_t geneve_dst_port /* UDP Destination Port to be recognised as GENEVE tunneled packets (0 is disabled) */; 11714 uint8_t sd_accept_mf_clss_fail /* If set, accept packets that fail Multi-Function Switch-Dependent classification. Only one VNIC on the port can have this set to 1 */; 11715 uint8_t sd_accept_mf_clss_fail_match_ethtype /* If set, accepted packets must match the ethertype of sd_clss_fail_ethtype */; 11716 uint16_t sd_accept_mf_clss_fail_ethtype /* Ethertype to match in the case of sd_accept_mf_clss_fail_match_ethtype */; 11717 uint16_t sd_vlan_eth_type /* Value of ether-type to use in the case of switch dependent multi-function mode. Setting this to 0 uses the default value of 0x8100 */; 11718 uint8_t sd_vlan_force_pri_flg /* If set, the SD Vlan Priority is forced to the value of the sd_vlan_pri_force_val field regardless of the DCB or inband VLAN priority. */; 11719 uint8_t sd_vlan_force_pri_val /* value to force SD Vlan Priority if sd_vlan_pri_force_flg is set */; 11720 uint8_t c2s_pri_tt_valid /* When set, c2s_pri_trans_table is valid */; 11721 uint8_t c2s_pri_default /* This value will be the sVlan pri value in case no Cvlan is present */; 11722 uint8_t reserved2[6]; 11723 struct c2s_pri_trans_table_entry c2s_pri_trans_table /* Inner to outer vlan priority translation table entry for current PF */; 11724}; 11725 11726 11727/* 11728 * $$KEEP_ENDIANNESS$$ 11729 */ 11730struct function_update_data 11731{ 11732 uint8_t vif_id_change_flg /* If set, vif_id will be checked */; 11733 uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */; 11734 uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */; 11735 uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */; 11736 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 11737 uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */; 11738 uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */; 11739 uint8_t network_cos_mode /* The cos mode for network traffic. */; 11740 uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */; 11741 uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */; 11742 uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */; 11743 uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */; 11744 uint8_t echo; 11745 uint8_t update_tunn_cfg_flg /* If set, tunneling config for the function will be updated according to the following fields */; 11746 uint8_t inner_clss_vxlan /* Classification type for VXLAN */; 11747 uint8_t inner_clss_l2gre /* If set, classification on the inner MAC/VLAN of L2GRE tunneled packets is enabled */; 11748 uint8_t inner_clss_l2geneve /* If set, classification on the inner MAC/(VLAN or VNI) of L2GENEVE tunneled packets is enabled */; 11749 uint8_t inner_rss /* If set, RSS on the inner headers of tunneled packets is enabled */; 11750 uint16_t vxlan_dst_port /* UDP Destination Port to be recognised as VXLAN tunneled packets (0 is disabled) */; 11751 uint16_t geneve_dst_port /* UDP Destination Port to be recognised as GENEVE tunneled packets (0 is disabled) */; 11752 uint8_t sd_vlan_force_pri_change_flg /* If set, the SD VLAN Priority Fixed configuration is updated from fields sd_vlan_pri_force_flg and sd_vlan_pri_force_val */; 11753 uint8_t sd_vlan_force_pri_flg /* If set, the SD Vlan Priority is forced to the value of the sd_vlan_pri_force_val field regardless of the DCB or inband VLAN priority. */; 11754 uint8_t sd_vlan_force_pri_val /* value to force SD Vlan Priority if sd_vlan_pri_force_flg is set */; 11755 uint8_t sd_vlan_tag_change_flg /* If set, the SD VLAN Tag is changed according to the field sd_vlan_tag */; 11756 uint8_t sd_vlan_eth_type_change_flg /* If set, the SD VLAN Ethertype is changed according to the field sd_vlan_eth_type */; 11757 uint8_t reserved1; 11758 uint16_t sd_vlan_tag /* New value of Outer Vlan in case of switch depended multi-function mode */; 11759 uint16_t sd_vlan_eth_type /* New value of ether-type in the case of switch dependent multi-function mode. Setting this to 0 restores the default value of 0x8100 */; 11760 uint16_t reserved0; 11761 uint32_t reserved2; 11762}; 11763 11764 11765/* 11766 * FW version stored in the Xstorm RAM 11767 */ 11768struct fw_version 11769{ 11770#if defined(__BIG_ENDIAN) 11771 uint8_t engineering /* firmware current engineering version */; 11772 uint8_t revision /* firmware current revision version */; 11773 uint8_t minor /* firmware current minor version */; 11774 uint8_t major /* firmware current major version */; 11775#elif defined(__LITTLE_ENDIAN) 11776 uint8_t major /* firmware current major version */; 11777 uint8_t minor /* firmware current minor version */; 11778 uint8_t revision /* firmware current revision version */; 11779 uint8_t engineering /* firmware current engineering version */; 11780#endif 11781 uint32_t flags; 11782 #define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 11783 #define FW_VERSION_OPTIMIZED_SHIFT 0 11784 #define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */ 11785 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 11786 #define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 0 - E1, 1 - E1H */ 11787 #define FW_VERSION_CHIP_VERSION_SHIFT 2 11788 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */ 11789 #define __FW_VERSION_RESERVED_SHIFT 4 11790}; 11791 11792 11793/* 11794 * Dynamic Host-Coalescing - Driver(host) counters 11795 */ 11796struct hc_dynamic_sb_drv_counters 11797{ 11798 uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */; 11799}; 11800 11801 11802/* 11803 * 2 bytes. configuration/state parameters for a single protocol index 11804 */ 11805struct hc_index_data 11806{ 11807#if defined(__BIG_ENDIAN) 11808 uint8_t flags; 11809 #define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 11810 #define HC_INDEX_DATA_SM_ID_SHIFT 0 11811 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 11812 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 11813 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 11814 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 11815 #define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 11816 #define HC_INDEX_DATA_RESERVE_SHIFT 3 11817 uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 11818#elif defined(__LITTLE_ENDIAN) 11819 uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 11820 uint8_t flags; 11821 #define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 11822 #define HC_INDEX_DATA_SM_ID_SHIFT 0 11823 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 11824 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 11825 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 11826 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 11827 #define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 11828 #define HC_INDEX_DATA_RESERVE_SHIFT 3 11829#endif 11830}; 11831 11832 11833/* 11834 * HC state-machine 11835 */ 11836struct hc_status_block_sm 11837{ 11838#if defined(__BIG_ENDIAN) 11839 uint8_t igu_seg_id; 11840 uint8_t igu_sb_id /* sb_id within the IGU */; 11841 uint8_t timer_value /* Determines the time_to_expire */; 11842 uint8_t __flags; 11843#elif defined(__LITTLE_ENDIAN) 11844 uint8_t __flags; 11845 uint8_t timer_value /* Determines the time_to_expire */; 11846 uint8_t igu_sb_id /* sb_id within the IGU */; 11847 uint8_t igu_seg_id; 11848#endif 11849 uint32_t time_to_expire /* The time in which it expects to wake up */; 11850}; 11851 11852/* 11853 * hold PCI identification variables- used in various places in firmware 11854 */ 11855struct pci_entity 11856{ 11857#if defined(__BIG_ENDIAN) 11858 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 11859 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 11860 uint8_t vnic_id /* Virtual NIC ID (0-3) */; 11861 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 11862#elif defined(__LITTLE_ENDIAN) 11863 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 11864 uint8_t vnic_id /* Virtual NIC ID (0-3) */; 11865 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 11866 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 11867#endif 11868}; 11869 11870/* 11871 * The fast-path status block meta-data, common to all chips 11872 */ 11873struct hc_sb_data 11874{ 11875 struct regpair_native_t host_sb_addr /* Host status block address */; 11876 struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */; 11877 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 11878#if defined(__BIG_ENDIAN) 11879 uint8_t rsrv0; 11880 uint8_t state; 11881 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 11882 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 11883#elif defined(__LITTLE_ENDIAN) 11884 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 11885 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 11886 uint8_t state; 11887 uint8_t rsrv0; 11888#endif 11889 struct regpair_native_t rsrv1[2]; 11890}; 11891 11892 11893/* 11894 * Segment types for host coaslescing 11895 */ 11896enum hc_segment 11897{ 11898 HC_REGULAR_SEGMENT, 11899 HC_DEFAULT_SEGMENT, 11900 MAX_HC_SEGMENT}; 11901 11902 11903/* 11904 * The fast-path status block meta-data 11905 */ 11906struct hc_sp_status_block_data 11907{ 11908 struct regpair_native_t host_sb_addr /* Host status block address */; 11909#if defined(__BIG_ENDIAN) 11910 uint8_t rsrv1; 11911 uint8_t state; 11912 uint8_t igu_seg_id /* segment id of the IGU */; 11913 uint8_t igu_sb_id /* sb_id within the IGU */; 11914#elif defined(__LITTLE_ENDIAN) 11915 uint8_t igu_sb_id /* sb_id within the IGU */; 11916 uint8_t igu_seg_id /* segment id of the IGU */; 11917 uint8_t state; 11918 uint8_t rsrv1; 11919#endif 11920 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 11921}; 11922 11923 11924/* 11925 * The fast-path status block meta-data 11926 */ 11927struct hc_status_block_data_e1x 11928{ 11929 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */; 11930 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 11931}; 11932 11933 11934/* 11935 * The fast-path status block meta-data 11936 */ 11937struct hc_status_block_data_e2 11938{ 11939 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */; 11940 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 11941}; 11942 11943 11944/* 11945 * IGU block operartion modes (in Everest2) 11946 */ 11947enum igu_mode 11948{ 11949 HC_IGU_BC_MODE /* Backward compatible mode */, 11950 HC_IGU_NBC_MODE /* Non-backward compatible mode */, 11951 MAX_IGU_MODE}; 11952 11953 11954/* 11955 * Inner Headers Classification Type 11956 */ 11957enum inner_clss_type 11958{ 11959 INNER_CLSS_DISABLED /* Inner Classification Disabled */, 11960 INNER_CLSS_USE_VLAN /* Inner Classification using MAC/Inner VLAN */, 11961 INNER_CLSS_USE_VNI /* Inner Classification using MAC/VNI (Only for VXLAN and GENEVE) */, 11962 MAX_INNER_CLSS_TYPE}; 11963 11964 11965/* 11966 * IP versions 11967 */ 11968enum ip_ver 11969{ 11970 IP_V4, 11971 IP_V6, 11972 MAX_IP_VER}; 11973 11974 11975/* 11976 * Malicious VF error ID 11977 */ 11978enum malicious_vf_error_id 11979{ 11980 MALICIOUS_VF_NO_ERROR /* Zero placeholder value */, 11981 VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */, 11982 ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */, 11983 ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */, 11984 ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */, 11985 ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */, 11986 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */, 11987 ETH_TOO_MANY_BDS /* Tx packet has too many BDs */, 11988 ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */, 11989 ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */, 11990 ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */, 11991 ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */, 11992 ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */, 11993 ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */, 11994 ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */, 11995 MAX_MALICIOUS_VF_ERROR_ID}; 11996 11997 11998/* 11999 * Multi-function modes 12000 */ 12001enum mf_mode 12002{ 12003 SINGLE_FUNCTION, 12004 MULTI_FUNCTION_SD /* Switch dependent (vlan based) */, 12005 MULTI_FUNCTION_SI /* Switch independent (mac based) */, 12006 MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */, 12007 MAX_MF_MODE}; 12008 12009 12010/* 12011 * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$ 12012 */ 12013struct tstorm_per_pf_stats 12014{ 12015 struct regpair_t rcv_error_bytes /* number of bytes received with errors */; 12016}; 12017 12018/* 12019 * $$KEEP_ENDIANNESS$$ 12020 */ 12021struct per_pf_stats 12022{ 12023 struct tstorm_per_pf_stats tstorm_pf_statistics; 12024}; 12025 12026 12027/* 12028 * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$ 12029 */ 12030struct tstorm_per_port_stats 12031{ 12032 uint32_t mac_discard /* number of packets with mac errors */; 12033 uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */; 12034 uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */; 12035 uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */; 12036 uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */; 12037 uint32_t reserved; 12038}; 12039 12040/* 12041 * $$KEEP_ENDIANNESS$$ 12042 */ 12043struct per_port_stats 12044{ 12045 struct tstorm_per_port_stats tstorm_port_statistics; 12046}; 12047 12048 12049/* 12050 * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$ 12051 */ 12052struct tstorm_per_queue_stats 12053{ 12054 struct regpair_t rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */; 12055 uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */; 12056 uint32_t checksum_discard /* number of total packets received with checksum error */; 12057 struct regpair_t rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */; 12058 uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */; 12059 uint32_t pkts_too_big_discard /* number of too long packets received */; 12060 struct regpair_t rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */; 12061 uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */; 12062 uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */; 12063 uint16_t no_buff_discard; 12064 uint16_t reserved0; 12065 uint32_t reserved1; 12066}; 12067 12068/* 12069 * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$ 12070 */ 12071struct ustorm_per_queue_stats 12072{ 12073 struct regpair_t ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */; 12074 struct regpair_t mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */; 12075 struct regpair_t bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */; 12076 uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 12077 uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 12078 uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 12079 uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */; 12080 struct regpair_t coalesced_bytes /* the number of bytes coalesced in all aggregations */; 12081 uint32_t coalesced_events /* the number of aggregations */; 12082 uint32_t coalesced_aborts /* the number of exception which avoid aggregation */; 12083}; 12084 12085/* 12086 * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$ 12087 */ 12088struct xstorm_per_queue_stats 12089{ 12090 struct regpair_t ucast_bytes_sent /* number of total bytes sent without errors */; 12091 struct regpair_t mcast_bytes_sent /* number of total bytes sent without errors */; 12092 struct regpair_t bcast_bytes_sent /* number of total bytes sent without errors */; 12093 uint32_t ucast_pkts_sent /* number of total packets sent without errors */; 12094 uint32_t mcast_pkts_sent /* number of total packets sent without errors */; 12095 uint32_t bcast_pkts_sent /* number of total packets sent without errors */; 12096 uint32_t error_drop_pkts /* number of total packets drooped due to errors */; 12097}; 12098 12099/* 12100 * $$KEEP_ENDIANNESS$$ 12101 */ 12102struct per_queue_stats 12103{ 12104 struct tstorm_per_queue_stats tstorm_queue_statistics; 12105 struct ustorm_per_queue_stats ustorm_queue_statistics; 12106 struct xstorm_per_queue_stats xstorm_queue_statistics; 12107}; 12108 12109 12110/* 12111 * FW version stored in first line of pram $$KEEP_ENDIANNESS$$ 12112 */ 12113struct pram_fw_version 12114{ 12115 uint8_t major /* firmware current major version */; 12116 uint8_t minor /* firmware current minor version */; 12117 uint8_t revision /* firmware current revision version */; 12118 uint8_t engineering /* firmware current engineering version */; 12119 uint8_t flags; 12120 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 12121 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 12122 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */ 12123 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 12124 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */ 12125 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 12126 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 0 - E1, 1 - E1H */ 12127 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 12128 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */ 12129 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 12130}; 12131 12132 12133/* 12134 * Ethernet slow path element 12135 */ 12136union protocol_common_specific_data 12137{ 12138 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 12139 struct regpair_t phy_address /* SPE physical address */; 12140 struct regpair_t mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */; 12141 struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */; 12142}; 12143 12144/* 12145 * The send queue element 12146 */ 12147struct protocol_common_spe 12148{ 12149 struct spe_hdr_t hdr /* SPE header */; 12150 union protocol_common_specific_data data /* data specific to common protocol */; 12151}; 12152 12153 12154/* 12155 * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$ 12156 */ 12157struct set_timesync_ramrod_data 12158{ 12159 uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */; 12160 uint8_t offset_cmd /* Timesync Offset Command */; 12161 uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */; 12162 uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */; 12163 uint32_t drift_adjust_period /* Drift Adjust Period (in us) */; 12164 struct regpair_t offset_delta /* Timesync Offset Delta (in ns) */; 12165}; 12166 12167 12168/* 12169 * The send queue element 12170 */ 12171struct slow_path_element 12172{ 12173 struct spe_hdr_t hdr /* common data for all protocols */; 12174 struct regpair_t protocol_data /* additional data specific to the protocol */; 12175}; 12176 12177 12178/* 12179 * Protocol-common statistics counter $$KEEP_ENDIANNESS$$ 12180 */ 12181struct stats_counter 12182{ 12183 uint16_t xstats_counter /* xstorm statistics counter */; 12184 uint16_t reserved0; 12185 uint32_t reserved1; 12186 uint16_t tstats_counter /* tstorm statistics counter */; 12187 uint16_t reserved2; 12188 uint32_t reserved3; 12189 uint16_t ustats_counter /* ustorm statistics counter */; 12190 uint16_t reserved4; 12191 uint32_t reserved5; 12192 uint16_t cstats_counter /* ustorm statistics counter */; 12193 uint16_t reserved6; 12194 uint32_t reserved7; 12195}; 12196 12197 12198/* 12199 * $$KEEP_ENDIANNESS$$ 12200 */ 12201struct stats_query_entry 12202{ 12203 uint8_t kind; 12204 uint8_t index /* queue index */; 12205 uint16_t funcID /* the func the statistic will send to */; 12206 uint32_t reserved; 12207 struct regpair_t address /* pxp address */; 12208}; 12209 12210/* 12211 * statistic command $$KEEP_ENDIANNESS$$ 12212 */ 12213struct stats_query_cmd_group 12214{ 12215 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 12216}; 12217 12218 12219/* 12220 * statistic command header $$KEEP_ENDIANNESS$$ 12221 */ 12222struct stats_query_header 12223{ 12224 uint8_t cmd_num /* command number */; 12225 uint8_t reserved0; 12226 uint16_t drv_stats_counter; 12227 uint32_t reserved1; 12228 struct regpair_t stats_counters_addrs /* stats counter */; 12229}; 12230 12231 12232/* 12233 * Types of statistcis query entry 12234 */ 12235enum stats_query_type 12236{ 12237 STATS_TYPE_QUEUE, 12238 STATS_TYPE_PORT, 12239 STATS_TYPE_PF, 12240 STATS_TYPE_TOE, 12241 STATS_TYPE_FCOE, 12242 MAX_STATS_QUERY_TYPE}; 12243 12244 12245/* 12246 * Indicate of the function status block state 12247 */ 12248enum status_block_state 12249{ 12250 SB_DISABLED, 12251 SB_ENABLED, 12252 SB_CLEANED, 12253 MAX_STATUS_BLOCK_STATE}; 12254 12255 12256/* 12257 * Storm IDs (including attentions for IGU related enums) 12258 */ 12259enum storm_id 12260{ 12261 USTORM_ID, 12262 CSTORM_ID, 12263 XSTORM_ID, 12264 TSTORM_ID, 12265 ATTENTION_ID, 12266 MAX_STORM_ID}; 12267 12268 12269/* 12270 * Taffic types used in ETS and flow control algorithms 12271 */ 12272enum traffic_type 12273{ 12274 LLFC_TRAFFIC_TYPE_NW /* Networking */, 12275 LLFC_TRAFFIC_TYPE_FCOE /* FCoE */, 12276 LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */, 12277 MAX_TRAFFIC_TYPE}; 12278 12279 12280/* 12281 * zone A per-queue data 12282 */ 12283struct tstorm_queue_zone_data 12284{ 12285 struct regpair_t reserved[4]; 12286}; 12287 12288 12289/* 12290 * zone B per-VF data 12291 */ 12292struct tstorm_vf_zone_data 12293{ 12294 struct regpair_t reserved; 12295}; 12296 12297 12298/* 12299 * Add or Subtract Value for Set Timesync Ramrod 12300 */ 12301enum ts_add_sub_value 12302{ 12303 TS_SUB_VALUE /* Subtract Value */, 12304 TS_ADD_VALUE /* Add Value */, 12305 MAX_TS_ADD_SUB_VALUE}; 12306 12307 12308/* 12309 * Drift-Adjust Commands for Set Timesync Ramrod 12310 */ 12311enum ts_drift_adjust_cmd 12312{ 12313 TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */, 12314 TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */, 12315 TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */, 12316 MAX_TS_DRIFT_ADJUST_CMD}; 12317 12318 12319/* 12320 * Offset Commands for Set Timesync Ramrod 12321 */ 12322enum ts_offset_cmd 12323{ 12324 TS_OFFSET_KEEP /* Keep Offset at current values */, 12325 TS_OFFSET_INC /* Increase Offset by Offset Delta */, 12326 TS_OFFSET_DEC /* Decrease Offset by Offset Delta */, 12327 MAX_TS_OFFSET_CMD}; 12328 12329 12330/* 12331 * Input for measuring Pci Latency 12332 */ 12333struct t_measure_pci_latency_ctrl 12334{ 12335 struct regpair_t read_addr /* Address to read from */; 12336#if defined(__BIG_ENDIAN) 12337 uint8_t sleep /* Measure including a thread sleep */; 12338 uint8_t enable /* Enable PCI Latency measurements */; 12339 uint8_t func_id /* Function ID */; 12340 uint8_t read_size /* Amount of bytes to read */; 12341#elif defined(__LITTLE_ENDIAN) 12342 uint8_t read_size /* Amount of bytes to read */; 12343 uint8_t func_id /* Function ID */; 12344 uint8_t enable /* Enable PCI Latency measurements */; 12345 uint8_t sleep /* Measure including a thread sleep */; 12346#endif 12347#if defined(__BIG_ENDIAN) 12348 uint16_t num_meas /* Number of measurements to make */; 12349 uint8_t reserved; 12350 uint8_t period_10us /* Number of 10s of microseconds to wait between measurements */; 12351#elif defined(__LITTLE_ENDIAN) 12352 uint8_t period_10us /* Number of 10s of microseconds to wait between measurements */; 12353 uint8_t reserved; 12354 uint16_t num_meas /* Number of measurements to make */; 12355#endif 12356}; 12357 12358 12359/* 12360 * Input for measuring Pci Latency 12361 */ 12362struct t_measure_pci_latency_data 12363{ 12364#if defined(__BIG_ENDIAN) 12365 uint16_t max_time_ns /* Maximum Time for a read (in ns) */; 12366 uint16_t min_time_ns /* Minimum Time for a read (in ns) */; 12367#elif defined(__LITTLE_ENDIAN) 12368 uint16_t min_time_ns /* Minimum Time for a read (in ns) */; 12369 uint16_t max_time_ns /* Maximum Time for a read (in ns) */; 12370#endif 12371#if defined(__BIG_ENDIAN) 12372 uint16_t reserved; 12373 uint16_t num_reads /* Number of reads - Used for Average */; 12374#elif defined(__LITTLE_ENDIAN) 12375 uint16_t num_reads /* Number of reads - Used for Average */; 12376 uint16_t reserved; 12377#endif 12378 struct regpair_t sum_time_ns /* Sum of all the reads (in ns) - Used for Average */; 12379}; 12380 12381 12382/* 12383 * zone A per-queue data 12384 */ 12385struct ustorm_queue_zone_data 12386{ 12387 struct ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */; 12388 struct regpair_t reserved[3]; 12389}; 12390 12391 12392/* 12393 * zone B per-VF data 12394 */ 12395struct ustorm_vf_zone_data 12396{ 12397 struct regpair_t reserved; 12398}; 12399 12400 12401/* 12402 * data per VF-PF channel 12403 */ 12404struct vf_pf_channel_data 12405{ 12406#if defined(__BIG_ENDIAN) 12407 uint16_t reserved0; 12408 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 12409 uint8_t state /* channel state (ready / waiting for ack) */; 12410#elif defined(__LITTLE_ENDIAN) 12411 uint8_t state /* channel state (ready / waiting for ack) */; 12412 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 12413 uint16_t reserved0; 12414#endif 12415 uint32_t reserved1; 12416}; 12417 12418 12419/* 12420 * State of VF-PF channel 12421 */ 12422enum vf_pf_channel_state 12423{ 12424 VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */, 12425 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */, 12426 MAX_VF_PF_CHANNEL_STATE}; 12427 12428 12429/* 12430 * vif_list_rule_kind 12431 */ 12432enum vif_list_rule_kind 12433{ 12434 VIF_LIST_RULE_SET, 12435 VIF_LIST_RULE_GET, 12436 VIF_LIST_RULE_CLEAR_ALL, 12437 VIF_LIST_RULE_CLEAR_FUNC, 12438 MAX_VIF_LIST_RULE_KIND}; 12439 12440 12441/* 12442 * zone A per-queue data 12443 */ 12444struct xstorm_queue_zone_data 12445{ 12446 struct regpair_t reserved[4]; 12447}; 12448 12449 12450/* 12451 * zone B per-VF data 12452 */ 12453struct xstorm_vf_zone_data 12454{ 12455 struct regpair_t reserved; 12456}; 12457 12458 12459/* 12460 * Out-of-order states 12461 */ 12462enum tcp_ooo_event 12463{ 12464 TCP_EVENT_ADD_PEN=0, 12465 TCP_EVENT_ADD_NEW_ISLE=1, 12466 TCP_EVENT_ADD_ISLE_RIGHT=2, 12467 TCP_EVENT_ADD_ISLE_LEFT=3, 12468 TCP_EVENT_JOIN=4, 12469 TCP_EVENT_NOP=5, 12470 MAX_TCP_OOO_EVENT}; 12471 12472 12473/* 12474 * OOO support modes 12475 */ 12476enum tcp_tstorm_ooo 12477{ 12478 TCP_TSTORM_OOO_DROP_AND_PROC_ACK, 12479 TCP_TSTORM_OOO_SEND_PURE_ACK, 12480 TCP_TSTORM_OOO_SUPPORTED, 12481 MAX_TCP_TSTORM_OOO}; 12482 12483 12484/* 12485 * toe statistics collected by the Cstorm (per port) 12486 */ 12487struct cstorm_toe_stats 12488{ 12489 uint32_t no_tx_cqes /* count the number of time storm find that there are no more CQEs */; 12490 uint32_t reserved; 12491}; 12492 12493 12494/* 12495 * The toe storm context of Cstorm 12496 */ 12497struct cstorm_toe_st_context 12498{ 12499 uint32_t bds_ring_page_base_addr_lo /* Base address of next page in host bds ring */; 12500 uint32_t bds_ring_page_base_addr_hi /* Base address of next page in host bds ring */; 12501 uint32_t free_seq /* Sequnce number of the last byte that was free including */; 12502 uint32_t __last_rel_to_notify /* Accumulated release size for the next Chimney completion msg */; 12503#if defined(__BIG_ENDIAN) 12504 uint16_t __rss_params_ram_line /* The ram line containing the rss params */; 12505 uint16_t bd_cons /* The bd s ring consumer */; 12506#elif defined(__LITTLE_ENDIAN) 12507 uint16_t bd_cons /* The bd s ring consumer */; 12508 uint16_t __rss_params_ram_line /* The ram line containing the rss params */; 12509#endif 12510 uint32_t cpu_id /* CPU id for sending completion for TSS (only 8 bits are used) */; 12511 uint32_t prev_snd_max /* last snd_max that was used for dynamic HC producer update */; 12512 uint32_t __reserved4 /* reserved */; 12513}; 12514 12515/* 12516 * Cstorm Toe Storm Aligned Context 12517 */ 12518struct cstorm_toe_st_aligned_context 12519{ 12520 struct cstorm_toe_st_context context /* context */; 12521}; 12522 12523 12524/* 12525 * prefetched isle bd 12526 */ 12527struct ustorm_toe_prefetched_isle_bd 12528{ 12529 uint32_t __addr_lo /* receive payload base address - Single continuous buffer (page) pointer */; 12530 uint32_t __addr_hi /* receive payload base address - Single continuous buffer (page) pointer */; 12531#if defined(__BIG_ENDIAN) 12532 uint8_t __reserved1 /* reserved */; 12533 uint8_t __isle_num /* isle_number of the pre-fetched BD */; 12534 uint16_t __buf_un_used /* Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is not valid */; 12535#elif defined(__LITTLE_ENDIAN) 12536 uint16_t __buf_un_used /* Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is not valid */; 12537 uint8_t __isle_num /* isle_number of the pre-fetched BD */; 12538 uint8_t __reserved1 /* reserved */; 12539#endif 12540}; 12541 12542/* 12543 * ring params 12544 */ 12545struct ustorm_toe_ring_params 12546{ 12547 uint32_t rq_cons_addr_lo /* A pointer to the next to consume application bd */; 12548 uint32_t rq_cons_addr_hi /* A pointer to the next to consume application bd */; 12549#if defined(__BIG_ENDIAN) 12550 uint8_t __rq_local_cons /* consumer of the local rq ring */; 12551 uint8_t __rq_local_prod /* producer of the local rq ring */; 12552 uint16_t rq_cons /* RQ consumer is the index of the next to consume application bd */; 12553#elif defined(__LITTLE_ENDIAN) 12554 uint16_t rq_cons /* RQ consumer is the index of the next to consume application bd */; 12555 uint8_t __rq_local_prod /* producer of the local rq ring */; 12556 uint8_t __rq_local_cons /* consumer of the local rq ring */; 12557#endif 12558}; 12559 12560/* 12561 * prefetched bd 12562 */ 12563struct ustorm_toe_prefetched_bd 12564{ 12565 uint32_t __addr_lo /* receive payload base address - Single continuous buffer (page) pointer */; 12566 uint32_t __addr_hi /* receive payload base address - Single continuous buffer (page) pointer */; 12567#if defined(__BIG_ENDIAN) 12568 uint16_t flags; 12569 #define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0) /* BitField flagsbd command flags this bd is the beginning of an application buffer */ 12570 #define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0 12571 #define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1) /* BitField flagsbd command flags this bd is the end of an application buffer */ 12572 #define __USTORM_TOE_PREFETCHED_BD_END_SHIFT 1 12573 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2) /* BitField flagsbd command flags this application buffer must not be partially completed */ 12574 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH_SHIFT 2 12575 #define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3) /* BitField flagsbd command flags this application buffer is part of a bigger buffer and this buffer is not the last */ 12576 #define USTORM_TOE_PREFETCHED_BD_SPLIT_SHIFT 3 12577 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */ 12578 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1_SHIFT 4 12579 uint16_t __buf_un_used /* Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is not valid */; 12580#elif defined(__LITTLE_ENDIAN) 12581 uint16_t __buf_un_used /* Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is not valid */; 12582 uint16_t flags; 12583 #define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0) /* BitField flagsbd command flags this bd is the beginning of an application buffer */ 12584 #define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0 12585 #define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1) /* BitField flagsbd command flags this bd is the end of an application buffer */ 12586 #define __USTORM_TOE_PREFETCHED_BD_END_SHIFT 1 12587 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2) /* BitField flagsbd command flags this application buffer must not be partially completed */ 12588 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH_SHIFT 2 12589 #define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3) /* BitField flagsbd command flags this application buffer is part of a bigger buffer and this buffer is not the last */ 12590 #define USTORM_TOE_PREFETCHED_BD_SPLIT_SHIFT 3 12591 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */ 12592 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1_SHIFT 4 12593#endif 12594}; 12595 12596/* 12597 * Ustorm Toe Storm Context 12598 */ 12599struct ustorm_toe_st_context 12600{ 12601 uint32_t __pen_rq_placed /* Number of bytes that were placed in the RQ and not completed yet. */; 12602 uint32_t pen_grq_placed_bytes /* The number of in-order bytes (peninsula) that were placed in the GRQ (excluding bytes that were already copied to RQ BDs or RQ dummy BDs) */; 12603#if defined(__BIG_ENDIAN) 12604 uint8_t flags2; 12605 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0) /* BitField flags2various state flags we will ignore grq push unless it is ping pong test */ 12606 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0 12607 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1) /* BitField flags2various state flags indicates if push timer is set */ 12608 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG_SHIFT 1 12609 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2) /* BitField flags2various state flags indicates if RSS update is supported */ 12610 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED_SHIFT 2 12611 #define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3) /* BitField flags2various state flags */ 12612 #define USTORM_TOE_ST_CONTEXT_RESERVED0_SHIFT 3 12613 uint8_t __indirection_shift /* Offset in bits of the cupid of this connection on the 64Bits fetched from internal memoy */; 12614 uint16_t indirection_ram_offset /* address offset in internal memory from the beginning of the table consisting the cpu id of this connection (Only 12 bits are used) */; 12615#elif defined(__LITTLE_ENDIAN) 12616 uint16_t indirection_ram_offset /* address offset in internal memory from the beginning of the table consisting the cpu id of this connection (Only 12 bits are used) */; 12617 uint8_t __indirection_shift /* Offset in bits of the cupid of this connection on the 64Bits fetched from internal memoy */; 12618 uint8_t flags2; 12619 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0) /* BitField flags2various state flags we will ignore grq push unless it is ping pong test */ 12620 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0 12621 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1) /* BitField flags2various state flags indicates if push timer is set */ 12622 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG_SHIFT 1 12623 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2) /* BitField flags2various state flags indicates if RSS update is supported */ 12624 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED_SHIFT 2 12625 #define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3) /* BitField flags2various state flags */ 12626 #define USTORM_TOE_ST_CONTEXT_RESERVED0_SHIFT 3 12627#endif 12628 uint32_t __rq_available_bytes; 12629#if defined(__BIG_ENDIAN) 12630 uint8_t isles_counter /* signals that dca is enabled */; 12631 uint8_t __push_timer_state /* indicates if push timer is set */; 12632 uint16_t rcv_indication_size /* The chip will release the current GRQ buffer to the driver when it knows that the driver has no knowledge of other GRQ payload that it can indicate and the current GRQ buffer has at least RcvIndicationSize bytes. */; 12633#elif defined(__LITTLE_ENDIAN) 12634 uint16_t rcv_indication_size /* The chip will release the current GRQ buffer to the driver when it knows that the driver has no knowledge of other GRQ payload that it can indicate and the current GRQ buffer has at least RcvIndicationSize bytes. */; 12635 uint8_t __push_timer_state /* indicates if push timer is set */; 12636 uint8_t isles_counter /* signals that dca is enabled */; 12637#endif 12638 uint32_t __min_expiration_time /* if the timer will expire before this time it will be considered as a race */; 12639 uint32_t initial_rcv_wnd /* the maximal advertized window */; 12640 uint32_t __bytes_cons /* the last rq_available_bytes producer that was read from host - used to know how many bytes were added */; 12641 uint32_t __prev_consumed_grq_bytes /* the last rq_available_bytes producer that was read from host - used to know how many bytes were added */; 12642 uint32_t prev_rcv_win_right_edge /* siquence of the last bytes that can be received - used to know how many bytes were added */; 12643 uint32_t rcv_nxt /* Receive sequence: next expected - of the right most received packet */; 12644 struct ustorm_toe_prefetched_isle_bd __isle_bd /* prefetched bd for the isle */; 12645 struct ustorm_toe_ring_params pen_ring_params /* peninsula ring params */; 12646 struct ustorm_toe_prefetched_bd __pen_bd_0 /* peninsula prefetched bd for the peninsula */; 12647 struct ustorm_toe_prefetched_bd __pen_bd_1 /* peninsula prefetched bd for the peninsula */; 12648 struct ustorm_toe_prefetched_bd __pen_bd_2 /* peninsula prefetched bd for the peninsula */; 12649 struct ustorm_toe_prefetched_bd __pen_bd_3 /* peninsula prefetched bd for the peninsula */; 12650 struct ustorm_toe_prefetched_bd __pen_bd_4 /* peninsula prefetched bd for the peninsula */; 12651 struct ustorm_toe_prefetched_bd __pen_bd_5 /* peninsula prefetched bd for the peninsula */; 12652 struct ustorm_toe_prefetched_bd __pen_bd_6 /* peninsula prefetched bd for the peninsula */; 12653 struct ustorm_toe_prefetched_bd __pen_bd_7 /* peninsula prefetched bd for the peninsula */; 12654 struct ustorm_toe_prefetched_bd __pen_bd_8 /* peninsula prefetched bd for the peninsula */; 12655 struct ustorm_toe_prefetched_bd __pen_bd_9 /* peninsula prefetched bd for the peninsula */; 12656 uint32_t __reserved3 /* reserved */; 12657}; 12658 12659/* 12660 * Ustorm Toe Storm Aligned Context 12661 */ 12662struct ustorm_toe_st_aligned_context 12663{ 12664 struct ustorm_toe_st_context context /* context */; 12665}; 12666 12667/* 12668 * TOE context region, used only in TOE 12669 */ 12670struct tstorm_toe_st_context_section 12671{ 12672 uint32_t reserved0[3]; 12673}; 12674 12675/* 12676 * The TOE non-aggregative context of Tstorm 12677 */ 12678struct tstorm_toe_st_context 12679{ 12680 struct tstorm_tcp_st_context_section tcp /* TCP context region, shared in TOE, RDMA and ISCSI */; 12681 struct tstorm_toe_st_context_section toe /* TOE context region, used only in TOE */; 12682}; 12683 12684/* 12685 * The TOE non-aggregative aligned context of Tstorm 12686 */ 12687struct tstorm_toe_st_aligned_context 12688{ 12689 struct tstorm_toe_st_context context /* context */; 12690 uint8_t padding[16] /* padding to 64 byte aligned */; 12691}; 12692 12693/* 12694 * TOE context section 12695 */ 12696struct xstorm_toe_context_section 12697{ 12698 uint32_t tx_bd_page_base_lo /* BD page base address at the host for TxBdCons */; 12699 uint32_t tx_bd_page_base_hi /* BD page base address at the host for TxBdCons */; 12700#if defined(__BIG_ENDIAN) 12701 uint16_t tx_bd_offset /* The offset within the BD */; 12702 uint16_t tx_bd_cons /* The transmit BD cons pointer to the host ring */; 12703#elif defined(__LITTLE_ENDIAN) 12704 uint16_t tx_bd_cons /* The transmit BD cons pointer to the host ring */; 12705 uint16_t tx_bd_offset /* The offset within the BD */; 12706#endif 12707#if defined(__BIG_ENDIAN) 12708 uint16_t bd_prod; 12709 uint16_t seqMismatchCnt; 12710#elif defined(__LITTLE_ENDIAN) 12711 uint16_t seqMismatchCnt; 12712 uint16_t bd_prod; 12713#endif 12714 uint32_t driver_doorbell_info_ptr_lo; 12715 uint32_t driver_doorbell_info_ptr_hi; 12716}; 12717 12718/* 12719 * Xstorm Toe Storm Context 12720 */ 12721struct xstorm_toe_st_context 12722{ 12723 struct xstorm_common_context_section common; 12724 struct xstorm_toe_context_section toe; 12725}; 12726 12727/* 12728 * Xstorm Toe Storm Aligned Context 12729 */ 12730struct xstorm_toe_st_aligned_context 12731{ 12732 struct xstorm_toe_st_context context /* context */; 12733}; 12734 12735/* 12736 * Ethernet connection context 12737 */ 12738struct toe_context 12739{ 12740 struct ustorm_toe_st_aligned_context ustorm_st_context /* Ustorm storm context */; 12741 struct tstorm_toe_st_aligned_context tstorm_st_context /* Tstorm storm context */; 12742 struct xstorm_toe_ag_context xstorm_ag_context /* Xstorm aggregative context */; 12743 struct tstorm_toe_ag_context tstorm_ag_context /* Tstorm aggregative context */; 12744 struct cstorm_toe_ag_context cstorm_ag_context /* Cstorm aggregative context */; 12745 struct ustorm_toe_ag_context ustorm_ag_context /* Ustorm aggregative context */; 12746 struct timers_block_context timers_context /* Timers block context */; 12747 struct xstorm_toe_st_aligned_context xstorm_st_context /* Xstorm storm context */; 12748 struct cstorm_toe_st_aligned_context cstorm_st_context /* Cstorm storm context */; 12749}; 12750 12751 12752/* 12753 * ramrod data for toe protocol initiate offload ramrod (CQE) 12754 */ 12755struct toe_initiate_offload_ramrod_data 12756{ 12757 uint32_t flags; 12758 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED (0x1<<0) /* BitField flags error in searcher configuration */ 12759 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED_SHIFT 0 12760 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE (0x1<<1) /* BitField flags license errors */ 12761 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE_SHIFT 1 12762 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0 (0x3FFFFFFF<<2) /* BitField flags */ 12763 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 2 12764 uint32_t reserved1; 12765}; 12766 12767 12768/* 12769 * union for ramrod data for TOE protocol (CQE) (force size of 16 bits) 12770 */ 12771struct toe_init_ramrod_data 12772{ 12773#if defined(__BIG_ENDIAN) 12774 uint16_t reserved1; 12775 uint8_t reserved0; 12776 uint8_t rss_num /* the rss num in its rqr to complete this ramrod */; 12777#elif defined(__LITTLE_ENDIAN) 12778 uint8_t rss_num /* the rss num in its rqr to complete this ramrod */; 12779 uint8_t reserved0; 12780 uint16_t reserved1; 12781#endif 12782 uint32_t reserved2; 12783}; 12784 12785 12786/* 12787 * next page pointer bd used in toe CQs and tx/rx bd chains 12788 */ 12789struct toe_page_addr_bd 12790{ 12791 uint32_t addr_lo /* page pointer */; 12792 uint32_t addr_hi /* page pointer */; 12793 uint8_t reserved[8] /* resereved for driver use */; 12794}; 12795 12796 12797/* 12798 * union for ramrod data for TOE protocol (CQE) (force size of 16 bits) 12799 */ 12800union toe_ramrod_data 12801{ 12802 struct ramrod_data general; 12803 struct toe_initiate_offload_ramrod_data initiate_offload; 12804}; 12805 12806 12807/* 12808 * TOE_RX_CQES_OPCODE_RSS_UPD results 12809 */ 12810enum toe_rss_update_opcode 12811{ 12812 TOE_RSS_UPD_QUIET, 12813 TOE_RSS_UPD_SLEEPING, 12814 TOE_RSS_UPD_DELAYED, 12815 MAX_TOE_RSS_UPDATE_OPCODE}; 12816 12817 12818/* 12819 * union for ramrod data for TOE protocol (CQE) (force size of 16 bits) 12820 */ 12821struct toe_rss_update_ramrod_data 12822{ 12823 uint8_t indirection_table[128] /* RSS indirection table */; 12824#if defined(__BIG_ENDIAN) 12825 uint16_t reserved0; 12826 uint16_t toe_rss_bitmap /* The bitmap specifies which toe rss chains to complete the ramrod on (0 bitmap is not valid option). The port is gleaned from the CID */; 12827#elif defined(__LITTLE_ENDIAN) 12828 uint16_t toe_rss_bitmap /* The bitmap specifies which toe rss chains to complete the ramrod on (0 bitmap is not valid option). The port is gleaned from the CID */; 12829 uint16_t reserved0; 12830#endif 12831 uint32_t reserved1; 12832}; 12833 12834 12835/* 12836 * The toe Rx Buffer Descriptor 12837 */ 12838struct toe_rx_bd 12839{ 12840 uint32_t addr_lo /* receive payload base address - Single continuous buffer (page) pointer */; 12841 uint32_t addr_hi /* receive payload base address - Single continuous buffer (page) pointer */; 12842#if defined(__BIG_ENDIAN) 12843 uint16_t flags; 12844 #define TOE_RX_BD_START (0x1<<0) /* BitField flagsbd command flags this bd is the beginning of an application buffer */ 12845 #define TOE_RX_BD_START_SHIFT 0 12846 #define TOE_RX_BD_END (0x1<<1) /* BitField flagsbd command flags this bd is the end of an application buffer */ 12847 #define TOE_RX_BD_END_SHIFT 1 12848 #define TOE_RX_BD_NO_PUSH (0x1<<2) /* BitField flagsbd command flags this application buffer must not be partially completed */ 12849 #define TOE_RX_BD_NO_PUSH_SHIFT 2 12850 #define TOE_RX_BD_SPLIT (0x1<<3) /* BitField flagsbd command flags this application buffer is part of a bigger buffer and this buffer is not the last */ 12851 #define TOE_RX_BD_SPLIT_SHIFT 3 12852 #define TOE_RX_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */ 12853 #define TOE_RX_BD_RESERVED1_SHIFT 4 12854 uint16_t size /* Size of the buffer pointed by the BD */; 12855#elif defined(__LITTLE_ENDIAN) 12856 uint16_t size /* Size of the buffer pointed by the BD */; 12857 uint16_t flags; 12858 #define TOE_RX_BD_START (0x1<<0) /* BitField flagsbd command flags this bd is the beginning of an application buffer */ 12859 #define TOE_RX_BD_START_SHIFT 0 12860 #define TOE_RX_BD_END (0x1<<1) /* BitField flagsbd command flags this bd is the end of an application buffer */ 12861 #define TOE_RX_BD_END_SHIFT 1 12862 #define TOE_RX_BD_NO_PUSH (0x1<<2) /* BitField flagsbd command flags this application buffer must not be partially completed */ 12863 #define TOE_RX_BD_NO_PUSH_SHIFT 2 12864 #define TOE_RX_BD_SPLIT (0x1<<3) /* BitField flagsbd command flags this application buffer is part of a bigger buffer and this buffer is not the last */ 12865 #define TOE_RX_BD_SPLIT_SHIFT 3 12866 #define TOE_RX_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */ 12867 #define TOE_RX_BD_RESERVED1_SHIFT 4 12868#endif 12869 uint32_t dbg_bytes_prod /* a cyclic parameter that caounts how many byte were available for placement till no not including this bd */; 12870}; 12871 12872 12873/* 12874 * ramrod data for toe protocol General rx completion 12875 */ 12876struct toe_rx_completion_ramrod_data 12877{ 12878#if defined(__BIG_ENDIAN) 12879 uint16_t reserved0; 12880 uint16_t hash_value /* information for ustorm to use in completion */; 12881#elif defined(__LITTLE_ENDIAN) 12882 uint16_t hash_value /* information for ustorm to use in completion */; 12883 uint16_t reserved0; 12884#endif 12885 uint32_t reserved1; 12886}; 12887 12888 12889/* 12890 * OOO params in union for TOE rx cqe data 12891 */ 12892struct toe_rx_cqe_ooo_params 12893{ 12894 uint32_t ooo_params; 12895 #define TOE_RX_CQE_OOO_PARAMS_NBYTES (0xFFFFFF<<0) /* BitField ooo_paramsdata params for OOO cqe connection nbytes */ 12896 #define TOE_RX_CQE_OOO_PARAMS_NBYTES_SHIFT 0 12897 #define TOE_RX_CQE_OOO_PARAMS_ISLE_NUM (0xFF<<24) /* BitField ooo_paramsdata params for OOO cqe isle number for OOO completions */ 12898 #define TOE_RX_CQE_OOO_PARAMS_ISLE_NUM_SHIFT 24 12899}; 12900 12901/* 12902 * in order params in union for TOE rx cqe data 12903 */ 12904struct toe_rx_cqe_in_order_params 12905{ 12906 uint32_t in_order_params; 12907 #define TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES (0xFFFFFFFF<<0) /* BitField in_order_paramsdata params for in order cqe connection nbytes */ 12908 #define TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES_SHIFT 0 12909}; 12910 12911/* 12912 * union for TOE rx cqe data 12913 */ 12914union toe_rx_cqe_data_union 12915{ 12916 struct toe_rx_cqe_ooo_params ooo_params /* data params for OOO cqe - nbytes and isle number */; 12917 struct toe_rx_cqe_in_order_params in_order_params /* data params for in order cqe - nbytes */; 12918 uint32_t raw_data /* global data param */; 12919}; 12920 12921/* 12922 * The toe Rx cq element 12923 */ 12924struct toe_rx_cqe 12925{ 12926 uint32_t params1; 12927 #define TOE_RX_CQE_CID (0xFFFFFF<<0) /* BitField params1completion cid and opcode connection id */ 12928 #define TOE_RX_CQE_CID_SHIFT 0 12929 #define TOE_RX_CQE_COMPLETION_OPCODE (0xFF<<24) /* BitField params1completion cid and opcode completion opcode - use enum toe_rx_cqe_type or toe_rss_update_opcode */ 12930 #define TOE_RX_CQE_COMPLETION_OPCODE_SHIFT 24 12931 union toe_rx_cqe_data_union data /* completion cid and opcode */; 12932}; 12933 12934 12935/* 12936 * toe rx doorbell data in host memory 12937 */ 12938struct toe_rx_db_data 12939{ 12940 uint32_t rcv_win_right_edge /* siquence of the last bytes that can be received */; 12941 uint32_t bytes_prod /* cyclic counter of posted bytes */; 12942#if defined(__BIG_ENDIAN) 12943 uint8_t reserved1 /* reserved */; 12944 uint8_t flags; 12945 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0) /* BitField flags ustorm ignores window updates when this flag is set */ 12946 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0 12947 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1) /* BitField flags indicates if to set push timer due to partially filled receive request after offload */ 12948 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF_SHIFT 1 12949 #define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2) /* BitField flags */ 12950 #define TOE_RX_DB_DATA_RESERVED0_SHIFT 2 12951 uint16_t bds_prod /* cyclic counter of bds to post */; 12952#elif defined(__LITTLE_ENDIAN) 12953 uint16_t bds_prod /* cyclic counter of bds to post */; 12954 uint8_t flags; 12955 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0) /* BitField flags ustorm ignores window updates when this flag is set */ 12956 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0 12957 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1) /* BitField flags indicates if to set push timer due to partially filled receive request after offload */ 12958 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF_SHIFT 1 12959 #define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2) /* BitField flags */ 12960 #define TOE_RX_DB_DATA_RESERVED0_SHIFT 2 12961 uint8_t reserved1 /* reserved */; 12962#endif 12963 uint32_t consumed_grq_bytes /* cyclic counter of consumed grq bytes */; 12964}; 12965 12966 12967/* 12968 * The toe Rx Generic Buffer Descriptor 12969 */ 12970struct toe_rx_grq_bd 12971{ 12972 uint32_t addr_lo /* receive payload base address - Single continuous buffer (page) pointer */; 12973 uint32_t addr_hi /* receive payload base address - Single continuous buffer (page) pointer */; 12974}; 12975 12976 12977/* 12978 * toe slow path element 12979 */ 12980union toe_spe_data 12981{ 12982 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 12983 struct regpair_t phys_addr /* used in initiate offload ramrod */; 12984 struct toe_rx_completion_ramrod_data rx_completion /* used in all ramrods that have a general rx completion */; 12985 struct toe_init_ramrod_data toe_init /* used in toe init ramrod */; 12986}; 12987 12988/* 12989 * toe slow path element 12990 */ 12991struct toe_spe 12992{ 12993 struct spe_hdr_t hdr /* common data for all protocols */; 12994 union toe_spe_data toe_data /* data specific to toe protocol */; 12995}; 12996 12997 12998/* 12999 * TOE slow path opcodes (opcode 0 is illegal) - includes commands and completions 13000 */ 13001enum toe_sq_opcode_type 13002{ 13003 CMP_OPCODE_TOE_GA=1, 13004 CMP_OPCODE_TOE_GR=2, 13005 CMP_OPCODE_TOE_GNI=3, 13006 CMP_OPCODE_TOE_GAIR=4, 13007 CMP_OPCODE_TOE_GAIL=5, 13008 CMP_OPCODE_TOE_GRI=6, 13009 CMP_OPCODE_TOE_GJ=7, 13010 CMP_OPCODE_TOE_DGI=8, 13011 CMP_OPCODE_TOE_CMP=9, 13012 CMP_OPCODE_TOE_REL=10, 13013 CMP_OPCODE_TOE_SKP=11, 13014 CMP_OPCODE_TOE_URG=12, 13015 CMP_OPCODE_TOE_RT_TO=13, 13016 CMP_OPCODE_TOE_KA_TO=14, 13017 CMP_OPCODE_TOE_MAX_RT=15, 13018 CMP_OPCODE_TOE_DBT_RE=16, 13019 CMP_OPCODE_TOE_SYN=17, 13020 CMP_OPCODE_TOE_OPT_ERR=18, 13021 CMP_OPCODE_TOE_FW2_TO=19, 13022 CMP_OPCODE_TOE_2WY_CLS=20, 13023 CMP_OPCODE_TOE_TX_CMP=21, 13024 RAMROD_OPCODE_TOE_INIT=32, 13025 RAMROD_OPCODE_TOE_RSS_UPDATE=33, 13026 RAMROD_OPCODE_TOE_TERMINATE_RING=34, 13027 CMP_OPCODE_TOE_RST_RCV=48, 13028 CMP_OPCODE_TOE_FIN_RCV=49, 13029 CMP_OPCODE_TOE_FIN_UPL=50, 13030 CMP_OPCODE_TOE_SRC_ERR=51, 13031 CMP_OPCODE_TOE_LCN_ERR=52, 13032 RAMROD_OPCODE_TOE_INITIATE_OFFLOAD=80, 13033 RAMROD_OPCODE_TOE_SEARCHER_DELETE=81, 13034 RAMROD_OPCODE_TOE_TERMINATE=82, 13035 RAMROD_OPCODE_TOE_QUERY=83, 13036 RAMROD_OPCODE_TOE_RESET_SEND=84, 13037 RAMROD_OPCODE_TOE_INVALIDATE=85, 13038 RAMROD_OPCODE_TOE_EMPTY_RAMROD=86, 13039 RAMROD_OPCODE_TOE_UPDATE=87, 13040 MAX_TOE_SQ_OPCODE_TYPE}; 13041 13042 13043/* 13044 * Toe statistics collected by the Xstorm (per port) 13045 */ 13046struct xstorm_toe_stats_section 13047{ 13048 uint32_t tcp_out_segments; 13049 uint32_t tcp_retransmitted_segments; 13050 struct regpair_t ip_out_octets; 13051 uint32_t ip_out_requests; 13052 uint32_t reserved; 13053}; 13054 13055/* 13056 * Toe statistics collected by the Xstorm (per port) 13057 */ 13058struct xstorm_toe_stats 13059{ 13060 struct xstorm_toe_stats_section statistics[2] /* 0 - ipv4 , 1 - ipv6 */; 13061 uint32_t reserved[2]; 13062}; 13063 13064/* 13065 * Toe statistics collected by the Tstorm (per port) 13066 */ 13067struct tstorm_toe_stats_section 13068{ 13069 uint32_t ip_in_receives; 13070 uint32_t ip_in_delivers; 13071 struct regpair_t ip_in_octets; 13072 uint32_t tcp_in_errors /* all discards except discards already counted by Ipv4 stats */; 13073 uint32_t ip_in_header_errors /* IP checksum */; 13074 uint32_t ip_in_discards /* no resources */; 13075 uint32_t ip_in_truncated_packets; 13076}; 13077 13078/* 13079 * Toe statistics collected by the Tstorm (per port) 13080 */ 13081struct tstorm_toe_stats 13082{ 13083 struct tstorm_toe_stats_section statistics[2] /* 0 - ipv4 , 1 - ipv6 */; 13084 uint32_t reserved[2]; 13085}; 13086 13087/* 13088 * Eth statistics query structure for the eth_stats_query ramrod 13089 */ 13090struct toe_stats_query 13091{ 13092 struct xstorm_toe_stats xstorm_toe /* Xstorm Toe statistics structure */; 13093 struct tstorm_toe_stats tstorm_toe /* Tstorm Toe statistics structure */; 13094 struct cstorm_toe_stats cstorm_toe /* Cstorm Toe statistics structure */; 13095}; 13096 13097 13098/* 13099 * The toe Tx Buffer Descriptor 13100 */ 13101struct toe_tx_bd 13102{ 13103 uint32_t addr_lo /* tranasmit payload base address - Single continuous buffer (page) pointer */; 13104 uint32_t addr_hi /* tranasmit payload base address - Single continuous buffer (page) pointer */; 13105#if defined(__BIG_ENDIAN) 13106 uint16_t flags; 13107 #define TOE_TX_BD_PUSH (0x1<<0) /* BitField flagsbd command flags End of data flag */ 13108 #define TOE_TX_BD_PUSH_SHIFT 0 13109 #define TOE_TX_BD_NOTIFY (0x1<<1) /* BitField flagsbd command flags notify driver with released data bytes including this bd */ 13110 #define TOE_TX_BD_NOTIFY_SHIFT 1 13111 #define TOE_TX_BD_FIN (0x1<<2) /* BitField flagsbd command flags send fin request */ 13112 #define TOE_TX_BD_FIN_SHIFT 2 13113 #define TOE_TX_BD_LARGE_IO (0x1<<3) /* BitField flagsbd command flags this bd is part of an application buffer larger than mss */ 13114 #define TOE_TX_BD_LARGE_IO_SHIFT 3 13115 #define TOE_TX_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */ 13116 #define TOE_TX_BD_RESERVED1_SHIFT 4 13117 uint16_t size /* Size of the data represented by the BD */; 13118#elif defined(__LITTLE_ENDIAN) 13119 uint16_t size /* Size of the data represented by the BD */; 13120 uint16_t flags; 13121 #define TOE_TX_BD_PUSH (0x1<<0) /* BitField flagsbd command flags End of data flag */ 13122 #define TOE_TX_BD_PUSH_SHIFT 0 13123 #define TOE_TX_BD_NOTIFY (0x1<<1) /* BitField flagsbd command flags notify driver with released data bytes including this bd */ 13124 #define TOE_TX_BD_NOTIFY_SHIFT 1 13125 #define TOE_TX_BD_FIN (0x1<<2) /* BitField flagsbd command flags send fin request */ 13126 #define TOE_TX_BD_FIN_SHIFT 2 13127 #define TOE_TX_BD_LARGE_IO (0x1<<3) /* BitField flagsbd command flags this bd is part of an application buffer larger than mss */ 13128 #define TOE_TX_BD_LARGE_IO_SHIFT 3 13129 #define TOE_TX_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */ 13130 #define TOE_TX_BD_RESERVED1_SHIFT 4 13131#endif 13132 uint32_t nextBdStartSeq; 13133}; 13134 13135 13136/* 13137 * The toe Tx cqe 13138 */ 13139struct toe_tx_cqe 13140{ 13141 uint32_t params; 13142 #define TOE_TX_CQE_CID (0xFFFFFF<<0) /* BitField paramscompletion cid and opcode connection id */ 13143 #define TOE_TX_CQE_CID_SHIFT 0 13144 #define TOE_TX_CQE_COMPLETION_OPCODE (0xFF<<24) /* BitField paramscompletion cid and opcode completion opcode (use enum toe_tx_cqe_type) */ 13145 #define TOE_TX_CQE_COMPLETION_OPCODE_SHIFT 24 13146 uint32_t len /* the more2release in Bytes */; 13147}; 13148 13149 13150/* 13151 * toe tx doorbell data in host memory 13152 */ 13153struct toe_tx_db_data 13154{ 13155 uint32_t bytes_prod_seq /* greatest sequence the chip can transmit */; 13156#if defined(__BIG_ENDIAN) 13157 uint16_t flags; 13158 #define TOE_TX_DB_DATA_FIN (0x1<<0) /* BitField flags flag for post FIN request */ 13159 #define TOE_TX_DB_DATA_FIN_SHIFT 0 13160 #define TOE_TX_DB_DATA_FLUSH (0x1<<1) /* BitField flags flag for last doorbell - flushing doorbell queue */ 13161 #define TOE_TX_DB_DATA_FLUSH_SHIFT 1 13162 #define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2) /* BitField flags */ 13163 #define TOE_TX_DB_DATA_RESERVE_SHIFT 2 13164 uint16_t bds_prod /* cyclic counter of posted bds */; 13165#elif defined(__LITTLE_ENDIAN) 13166 uint16_t bds_prod /* cyclic counter of posted bds */; 13167 uint16_t flags; 13168 #define TOE_TX_DB_DATA_FIN (0x1<<0) /* BitField flags flag for post FIN request */ 13169 #define TOE_TX_DB_DATA_FIN_SHIFT 0 13170 #define TOE_TX_DB_DATA_FLUSH (0x1<<1) /* BitField flags flag for last doorbell - flushing doorbell queue */ 13171 #define TOE_TX_DB_DATA_FLUSH_SHIFT 1 13172 #define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2) /* BitField flags */ 13173 #define TOE_TX_DB_DATA_RESERVE_SHIFT 2 13174#endif 13175}; 13176 13177 13178/* 13179 * sturct used in update ramrod. Driver notifies chip which fields have changed via the bitmap $$KEEP_ENDIANNESS$$ 13180 */ 13181struct toe_update_ramrod_cached_params 13182{ 13183 uint16_t changed_fields; 13184 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED (0x1<<0) /* BitField changed_fieldsbitmap for indicating changed fields */ 13185 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED_SHIFT 0 13186 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED (0x1<<1) /* BitField changed_fieldsbitmap for indicating changed fields */ 13187 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED_SHIFT 1 13188 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED (0x1<<2) /* BitField changed_fieldsbitmap for indicating changed fields */ 13189 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 2 13190 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED (0x1<<3) /* BitField changed_fieldsbitmap for indicating changed fields */ 13191 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED_SHIFT 3 13192 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED (0x1<<4) /* BitField changed_fieldsbitmap for indicating changed fields */ 13193 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED_SHIFT 4 13194 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED (0x1<<5) /* BitField changed_fieldsbitmap for indicating changed fields */ 13195 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 5 13196 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED (0x1<<6) /* BitField changed_fieldsbitmap for indicating changed fields */ 13197 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED_SHIFT 6 13198 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED (0x1<<7) /* BitField changed_fieldsbitmap for indicating changed fields */ 13199 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED_SHIFT 7 13200 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED (0x1<<8) /* BitField changed_fieldsbitmap for indicating changed fields */ 13201 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED_SHIFT 8 13202 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED (0x1<<9) /* BitField changed_fieldsbitmap for indicating changed fields */ 13203 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED_SHIFT 9 13204 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED (0x1<<10) /* BitField changed_fieldsbitmap for indicating changed fields */ 13205 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED_SHIFT 10 13206 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED (0x1<<11) /* BitField changed_fieldsbitmap for indicating changed fields */ 13207 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED_SHIFT 11 13208 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED (0x1<<12) /* BitField changed_fieldsbitmap for indicating changed fields */ 13209 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED_SHIFT 12 13210 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED (0x1<<13) /* BitField changed_fieldsbitmap for indicating changed fields */ 13211 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED_SHIFT 13 13212 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED (0x1<<14) /* BitField changed_fieldsbitmap for indicating changed fields */ 13213 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED_SHIFT 14 13214 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED (0x1<<15) /* BitField changed_fieldsbitmap for indicating changed fields */ 13215 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 15 13216 uint8_t ka_restart /* Only 1 bit is used */; 13217 uint8_t retransmit_restart /* Only 1 bit is used */; 13218 uint8_t dest_addr[6]; 13219 uint16_t mss; 13220 uint32_t ka_timeout; 13221 uint32_t ka_interval; 13222 uint32_t max_rt; 13223 uint32_t flow_label /* Only 20 bits are used */; 13224 uint16_t rcv_indication_size; 13225 uint8_t enable_keepalive /* Only 1 bit is used */; 13226 uint8_t enable_nagle /* Only 1 bit is used */; 13227 uint8_t ttl; 13228 uint8_t hop_limit; 13229 uint8_t tos; 13230 uint8_t traffic_class; 13231 uint8_t ka_max_probe_count; 13232 uint8_t user_priority /* Only 4 bits are used */; 13233 uint16_t reserved2; 13234 uint32_t initial_rcv_wnd; 13235 uint32_t reserved1; 13236}; 13237 13238 13239/* 13240 * rx rings pause data for E1h only 13241 */ 13242struct ustorm_toe_rx_pause_data_e1h 13243{ 13244#if defined(__BIG_ENDIAN) 13245 uint16_t grq_thr_low /* number of remaining grqes under which, we send pause message */; 13246 uint16_t cq_thr_low /* number of remaining cqes under which, we send pause message */; 13247#elif defined(__LITTLE_ENDIAN) 13248 uint16_t cq_thr_low /* number of remaining cqes under which, we send pause message */; 13249 uint16_t grq_thr_low /* number of remaining grqes under which, we send pause message */; 13250#endif 13251#if defined(__BIG_ENDIAN) 13252 uint16_t grq_thr_high /* number of remaining grqes above which, we send un-pause message */; 13253 uint16_t cq_thr_high /* number of remaining cqes above which, we send un-pause message */; 13254#elif defined(__LITTLE_ENDIAN) 13255 uint16_t cq_thr_high /* number of remaining cqes above which, we send un-pause message */; 13256 uint16_t grq_thr_high /* number of remaining grqes above which, we send un-pause message */; 13257#endif 13258}; 13259 13260 13261#endif /* ECORE_HSI_H */ 13262 13263