bnxt.h revision 309377
1/*- 2 * Broadcom NetXtreme-C/E network driver. 3 * 4 * Copyright (c) 2016 Broadcom, All Rights Reserved. 5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/11/sys/dev/bnxt/bnxt.h 309377 2016-12-01 23:37:17Z shurd $"); 31 32#ifndef _BNXT_H 33#define _BNXT_H 34 35#include <sys/types.h> 36#include <sys/bus.h> 37#include <sys/bus_dma.h> 38#include <sys/socket.h> 39#include <sys/sysctl.h> 40#include <sys/taskqueue.h> 41 42#include <net/ethernet.h> 43#include <net/if.h> 44#include <net/if_var.h> 45#include <net/iflib.h> 46 47#include "hsi_struct_def.h" 48 49/* PCI IDs */ 50#define BROADCOM_VENDOR_ID 0x14E4 51 52#define BCM57301 0x16c8 53#define BCM57302 0x16c9 54#define BCM57304 0x16ca 55#define BCM57311 0x16ce 56#define BCM57312 0x16cf 57#define BCM57314 0x16df 58#define BCM57402 0x16d0 59#define BCM57402_NPAR 0x16d4 60#define BCM57404 0x16d1 61#define BCM57404_NPAR 0x16e7 62#define BCM57406 0x16d2 63#define BCM57406_NPAR 0x16e8 64#define BCM57407 0x16d5 65#define BCM57407_NPAR 0x16ea 66#define BCM57407_SFP 0x16e9 67#define BCM57412 0x16d6 68#define BCM57412_NPAR1 0x16de 69#define BCM57412_NPAR2 0x16eb 70#define BCM57414 0x16d7 71#define BCM57414_NPAR1 0x16ec 72#define BCM57414_NPAR2 0x16ed 73#define BCM57416 0x16d8 74#define BCM57416_NPAR1 0x16ee 75#define BCM57416_NPAR2 0x16ef 76#define BCM57416_SFP 0x16e3 77#define BCM57417 0x16d9 78#define BCM57417_NPAR1 0x16c0 79#define BCM57417_NPAR2 0x16cc 80#define BCM57417_SFP 0x16e2 81#define BCM58700 0x16cd 82#define NETXTREME_C_VF1 0x16cb 83#define NETXTREME_C_VF2 0x16e1 84#define NETXTREME_C_VF3 0x16e5 85#define NETXTREME_E_VF1 0x16c1 86#define NETXTREME_E_VF2 0x16d3 87#define NETXTREME_E_VF3 0x16dc 88 89#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 90 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 91 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 92 93#define BNXT_MAX_MTU 9000 94 95/* Completion related defines */ 96#define CMP_VALID(cmp, v_bit) \ 97 ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) ) 98 99#define NEXT_CP_CONS_V(ring, cons, v_bit) do { \ 100 if (__predict_false(++(cons) == (ring)->ring_size)) \ 101 ((cons) = 0, (v_bit) = !v_bit); \ 102} while (0) 103 104#define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \ 105 0 : idx + 1) 106 107#define CMPL_PREFETCH_NEXT(cpr, idx) \ 108 __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\ 109 (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \ 110 ((cpr)->ring.ring_size - 1)]) 111 112/* 113 * If we update the index, a write barrier is needed after the write to ensure 114 * the completion ring has space before the RX/TX ring does. Since we can't 115 * make the RX and AG doorbells covered by the same barrier without remapping 116 * MSI-X vectors, we create the barrier over the enture doorbell bar. 117 * TODO: Remap the MSI-X vectors to allow a barrier to only cover the doorbells 118 * for a single ring group. 119 * 120 * A barrier of just the size of the write is used to ensure the ordering 121 * remains correct and no writes are lost. 122 */ 123#define BNXT_CP_DISABLE_DB(ring) do { \ 124 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 125 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 126 BUS_SPACE_BARRIER_WRITE); \ 127 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 128 (ring)->softc->doorbell_bar.handle, 0, \ 129 (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ 130 bus_space_write_4((ring)->softc->doorbell_bar.tag, \ 131 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ 132 htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_MASK)); \ 133} while (0) 134 135#define BNXT_CP_ENABLE_DB(ring) do { \ 136 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 137 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 138 BUS_SPACE_BARRIER_WRITE); \ 139 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 140 (ring)->softc->doorbell_bar.handle, 0, \ 141 (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ 142 bus_space_write_4((ring)->softc->doorbell_bar.tag, \ 143 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ 144 htole32(CMPL_DOORBELL_KEY_CMPL)); \ 145} while (0) 146 147#define BNXT_CP_IDX_ENABLE_DB(ring, cons) do { \ 148 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 149 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 150 BUS_SPACE_BARRIER_WRITE); \ 151 bus_space_write_4((ring)->softc->doorbell_bar.tag, \ 152 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ 153 htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_IDX_VALID | \ 154 (cons))); \ 155 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 156 (ring)->softc->doorbell_bar.handle, 0, \ 157 (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ 158} while (0) 159 160#define BNXT_CP_IDX_DISABLE_DB(ring, cons) do { \ 161 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 162 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 163 BUS_SPACE_BARRIER_WRITE); \ 164 bus_space_write_4((ring)->softc->doorbell_bar.tag, \ 165 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ 166 htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_IDX_VALID | \ 167 CMPL_DOORBELL_MASK | (cons))); \ 168 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 169 (ring)->softc->doorbell_bar.handle, 0, \ 170 (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ 171} while (0) 172 173#define BNXT_TX_DB(ring, idx) do { \ 174 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 175 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 176 BUS_SPACE_BARRIER_WRITE); \ 177 bus_space_write_4( \ 178 (ring)->softc->doorbell_bar.tag, \ 179 (ring)->softc->doorbell_bar.handle, \ 180 (ring)->doorbell, htole32(TX_DOORBELL_KEY_TX | (idx))); \ 181} while (0) 182 183#define BNXT_RX_DB(ring, idx) do { \ 184 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 185 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 186 BUS_SPACE_BARRIER_WRITE); \ 187 bus_space_write_4( \ 188 (ring)->softc->doorbell_bar.tag, \ 189 (ring)->softc->doorbell_bar.handle, \ 190 (ring)->doorbell, htole32(RX_DOORBELL_KEY_RX | (idx))); \ 191} while (0) 192 193/* Lock macros */ 194#define BNXT_HWRM_LOCK_INIT(_softc, _name) \ 195 mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF) 196#define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock) 197#define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock) 198#define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock) 199#define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ 200 MA_OWNED) 201 202/* Chip info */ 203#define BNXT_TSO_SIZE UINT16_MAX 204 205/* NVRAM access */ 206enum bnxt_nvm_directory_type { 207 BNX_DIR_TYPE_UNUSED = 0, 208 BNX_DIR_TYPE_PKG_LOG = 1, 209 BNX_DIR_TYPE_UPDATE = 2, 210 BNX_DIR_TYPE_CHIMP_PATCH = 3, 211 BNX_DIR_TYPE_BOOTCODE = 4, 212 BNX_DIR_TYPE_VPD = 5, 213 BNX_DIR_TYPE_EXP_ROM_MBA = 6, 214 BNX_DIR_TYPE_AVS = 7, 215 BNX_DIR_TYPE_PCIE = 8, 216 BNX_DIR_TYPE_PORT_MACRO = 9, 217 BNX_DIR_TYPE_APE_FW = 10, 218 BNX_DIR_TYPE_APE_PATCH = 11, 219 BNX_DIR_TYPE_KONG_FW = 12, 220 BNX_DIR_TYPE_KONG_PATCH = 13, 221 BNX_DIR_TYPE_BONO_FW = 14, 222 BNX_DIR_TYPE_BONO_PATCH = 15, 223 BNX_DIR_TYPE_TANG_FW = 16, 224 BNX_DIR_TYPE_TANG_PATCH = 17, 225 BNX_DIR_TYPE_BOOTCODE_2 = 18, 226 BNX_DIR_TYPE_CCM = 19, 227 BNX_DIR_TYPE_PCI_CFG = 20, 228 BNX_DIR_TYPE_TSCF_UCODE = 21, 229 BNX_DIR_TYPE_ISCSI_BOOT = 22, 230 BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, 231 BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, 232 BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, 233 BNX_DIR_TYPE_EXT_PHY = 27, 234 BNX_DIR_TYPE_SHARED_CFG = 40, 235 BNX_DIR_TYPE_PORT_CFG = 41, 236 BNX_DIR_TYPE_FUNC_CFG = 42, 237 BNX_DIR_TYPE_MGMT_CFG = 48, 238 BNX_DIR_TYPE_MGMT_DATA = 49, 239 BNX_DIR_TYPE_MGMT_WEB_DATA = 50, 240 BNX_DIR_TYPE_MGMT_WEB_META = 51, 241 BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, 242 BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 243}; 244 245enum bnxnvm_pkglog_field_index { 246 BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, 247 BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, 248 BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, 249 BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, 250 BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, 251 BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, 252 BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 253}; 254 255#define BNX_DIR_ORDINAL_FIRST 0 256#define BNX_DIR_EXT_NONE 0 257 258struct bnxt_bar_info { 259 struct resource *res; 260 bus_space_tag_t tag; 261 bus_space_handle_t handle; 262 bus_size_t size; 263 int rid; 264}; 265 266struct bnxt_link_info { 267 uint8_t media_type; 268 uint8_t transceiver; 269 uint8_t phy_addr; 270 uint8_t phy_link_status; 271 uint8_t wire_speed; 272 uint8_t loop_back; 273 uint8_t link_up; 274 uint8_t last_link_up; 275 uint8_t duplex; 276 uint8_t last_duplex; 277 uint8_t pause; 278 uint8_t last_pause; 279 uint8_t auto_pause; 280 uint8_t force_pause; 281 uint8_t duplex_setting; 282 uint8_t auto_mode; 283#define PHY_VER_LEN 3 284 uint8_t phy_ver[PHY_VER_LEN]; 285 uint8_t phy_type; 286 uint16_t link_speed; 287 uint16_t support_speeds; 288 uint16_t auto_link_speeds; 289 uint16_t auto_link_speed; 290 uint16_t force_link_speed; 291 uint32_t preemphasis; 292 293 /* copy of requested setting */ 294 uint8_t autoneg; 295#define BNXT_AUTONEG_SPEED 1 296#define BNXT_AUTONEG_FLOW_CTRL 2 297 uint8_t req_duplex; 298 uint8_t req_flow_ctrl; 299 uint16_t req_link_speed; 300}; 301 302enum bnxt_cp_type { 303 BNXT_DEFAULT, 304 BNXT_TX, 305 BNXT_RX, 306 BNXT_SHARED 307}; 308 309struct bnxt_cos_queue { 310 uint8_t id; 311 uint8_t profile; 312}; 313 314struct bnxt_func_info { 315 uint32_t fw_fid; 316 uint8_t mac_addr[ETHER_ADDR_LEN]; 317 uint16_t max_rsscos_ctxs; 318 uint16_t max_cp_rings; 319 uint16_t max_tx_rings; 320 uint16_t max_rx_rings; 321 uint16_t max_hw_ring_grps; 322 uint16_t max_irqs; 323 uint16_t max_l2_ctxs; 324 uint16_t max_vnics; 325 uint16_t max_stat_ctxs; 326}; 327 328struct bnxt_pf_info { 329#define BNXT_FIRST_PF_FID 1 330#define BNXT_FIRST_VF_FID 128 331 uint8_t port_id; 332 uint32_t first_vf_id; 333 uint16_t active_vfs; 334 uint16_t max_vfs; 335 uint32_t max_encap_records; 336 uint32_t max_decap_records; 337 uint32_t max_tx_em_flows; 338 uint32_t max_tx_wm_flows; 339 uint32_t max_rx_em_flows; 340 uint32_t max_rx_wm_flows; 341 unsigned long *vf_event_bmap; 342 uint16_t hwrm_cmd_req_pages; 343 void *hwrm_cmd_req_addr[4]; 344 bus_addr_t hwrm_cmd_req_dma_addr[4]; 345}; 346 347struct bnxt_vf_info { 348 uint16_t fw_fid; 349 uint8_t mac_addr[ETHER_ADDR_LEN]; 350 uint16_t max_rsscos_ctxs; 351 uint16_t max_cp_rings; 352 uint16_t max_tx_rings; 353 uint16_t max_rx_rings; 354 uint16_t max_hw_ring_grps; 355 uint16_t max_l2_ctxs; 356 uint16_t max_irqs; 357 uint16_t max_vnics; 358 uint16_t max_stat_ctxs; 359 uint32_t vlan; 360#define BNXT_VF_QOS 0x1 361#define BNXT_VF_SPOOFCHK 0x2 362#define BNXT_VF_LINK_FORCED 0x4 363#define BNXT_VF_LINK_UP 0x8 364 uint32_t flags; 365 uint32_t func_flags; /* func cfg flags */ 366 uint32_t min_tx_rate; 367 uint32_t max_tx_rate; 368 void *hwrm_cmd_req_addr; 369 bus_addr_t hwrm_cmd_req_dma_addr; 370}; 371 372#define BNXT_FLAG_VF (1<<1) 373 374#define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF)) 375#define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) 376 377struct bnxt_vlan_tag { 378 SLIST_ENTRY(bnxt_vlan_tag) next; 379 uint16_t tpid; 380 uint16_t tag; 381}; 382 383struct bnxt_vnic_info { 384 uint16_t id; 385 uint16_t def_ring_grp; 386 uint16_t cos_rule; 387 uint16_t lb_rule; 388 uint16_t mru; 389 390 uint32_t rx_mask; 391 bool vlan_only; 392 struct iflib_dma_info mc_list; 393 int mc_list_count; 394#define BNXT_MAX_MC_ADDRS 16 395 396 uint32_t flags; 397#define BNXT_VNIC_FLAG_DEFAULT 0x01 398#define BNXT_VNIC_FLAG_BD_STALL 0x02 399#define BNXT_VNIC_FLAG_VLAN_STRIP 0x04 400 401 uint64_t filter_id; 402 uint32_t flow_id; 403 404 uint16_t rss_id; 405 uint32_t rss_hash_type; 406 uint8_t rss_hash_key[HW_HASH_KEY_SIZE]; 407 struct iflib_dma_info rss_hash_key_tbl; 408 struct iflib_dma_info rss_grp_tbl; 409 SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags; 410 struct iflib_dma_info vlan_tag_list; 411}; 412 413struct bnxt_grp_info { 414 uint16_t stats_ctx; 415 uint16_t grp_id; 416 uint16_t rx_ring_id; 417 uint16_t cp_ring_id; 418 uint16_t ag_ring_id; 419}; 420 421struct bnxt_ring { 422 uint64_t paddr; 423 vm_offset_t doorbell; 424 caddr_t vaddr; 425 struct bnxt_softc *softc; 426 uint32_t ring_size; /* Must be a power of two */ 427 uint16_t id; /* Logical ID */ 428 uint16_t phys_id; 429}; 430 431struct bnxt_cp_ring { 432 struct bnxt_ring ring; 433 struct if_irq irq; 434 uint32_t cons; 435 bool v_bit; /* Value of valid bit */ 436 struct ctx_hw_stats *stats; 437 uint32_t stats_ctx_id; 438 uint32_t last_idx; /* Used by RX rings only 439 * set to the last read pidx 440 */ 441}; 442 443struct bnxt_full_tpa_start { 444 struct rx_tpa_start_cmpl low; 445 struct rx_tpa_start_cmpl_hi high; 446}; 447 448/* All the version information for the part */ 449#define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */ 450#define BNXT_NAME_SIZE 17 451struct bnxt_ver_info { 452 uint8_t hwrm_if_major; 453 uint8_t hwrm_if_minor; 454 uint8_t hwrm_if_update; 455 char hwrm_if_ver[BNXT_VERSTR_SIZE]; 456 char driver_hwrm_if_ver[BNXT_VERSTR_SIZE]; 457 char hwrm_fw_ver[BNXT_VERSTR_SIZE]; 458 char mgmt_fw_ver[BNXT_VERSTR_SIZE]; 459 char netctrl_fw_ver[BNXT_VERSTR_SIZE]; 460 char roce_fw_ver[BNXT_VERSTR_SIZE]; 461 char phy_ver[BNXT_VERSTR_SIZE]; 462 char pkg_ver[64]; 463 464 char hwrm_fw_name[BNXT_NAME_SIZE]; 465 char mgmt_fw_name[BNXT_NAME_SIZE]; 466 char netctrl_fw_name[BNXT_NAME_SIZE]; 467 char roce_fw_name[BNXT_NAME_SIZE]; 468 char phy_vendor[BNXT_NAME_SIZE]; 469 char phy_partnumber[BNXT_NAME_SIZE]; 470 471 uint16_t chip_num; 472 uint8_t chip_rev; 473 uint8_t chip_metal; 474 uint8_t chip_bond_id; 475 uint8_t chip_type; 476 477 uint8_t hwrm_min_major; 478 uint8_t hwrm_min_minor; 479 uint8_t hwrm_min_update; 480 481 struct sysctl_ctx_list ver_ctx; 482 struct sysctl_oid *ver_oid; 483}; 484 485struct bnxt_nvram_info { 486 uint16_t mfg_id; 487 uint16_t device_id; 488 uint32_t sector_size; 489 uint32_t size; 490 uint32_t reserved_size; 491 uint32_t available_size; 492 493 struct sysctl_ctx_list nvm_ctx; 494 struct sysctl_oid *nvm_oid; 495}; 496 497struct bnxt_softc { 498 device_t dev; 499 if_ctx_t ctx; 500 if_softc_ctx_t scctx; 501 if_shared_ctx_t sctx; 502 struct ifmedia *media; 503 504 struct bnxt_bar_info hwrm_bar; 505 struct bnxt_bar_info doorbell_bar; 506 struct bnxt_link_info link_info; 507#define BNXT_FLAG_NPAR 1 508 uint32_t flags; 509 uint32_t total_msix; 510 511 struct bnxt_func_info func; 512 struct bnxt_pf_info pf; 513 struct bnxt_vf_info vf; 514 515 uint16_t hwrm_cmd_seq; 516 uint32_t hwrm_cmd_timeo; /* milliseconds */ 517 struct iflib_dma_info hwrm_cmd_resp; 518 /* Interrupt info for HWRM */ 519 struct if_irq irq; 520 struct mtx hwrm_lock; 521 uint16_t hwrm_max_req_len; 522 523#define BNXT_MAX_QUEUE 8 524 uint8_t max_tc; 525 struct bnxt_cos_queue q_info[BNXT_MAX_QUEUE]; 526 527 struct iflib_dma_info hw_rx_port_stats; 528 struct iflib_dma_info hw_tx_port_stats; 529 struct rx_port_stats *rx_port_stats; 530 struct tx_port_stats *tx_port_stats; 531 532 int num_cp_rings; 533 534 struct bnxt_ring *tx_rings; 535 struct bnxt_cp_ring *tx_cp_rings; 536 struct iflib_dma_info tx_stats; 537 int ntxqsets; 538 539 struct bnxt_vnic_info vnic_info; 540 struct bnxt_ring *ag_rings; 541 struct bnxt_ring *rx_rings; 542 struct bnxt_cp_ring *rx_cp_rings; 543 struct bnxt_grp_info *grp_info; 544 struct iflib_dma_info rx_stats; 545 int nrxqsets; 546 547 struct bnxt_cp_ring def_cp_ring; 548 struct iflib_dma_info def_cp_ring_mem; 549 struct grouptask def_cp_task; 550 551 struct sysctl_ctx_list hw_stats; 552 struct sysctl_oid *hw_stats_oid; 553 554 struct bnxt_full_tpa_start *tpa_start; 555 struct bnxt_ver_info *ver_info; 556 struct bnxt_nvram_info *nvm_info; 557}; 558 559struct bnxt_filter_info { 560 STAILQ_ENTRY(bnxt_filter_info) next; 561 uint64_t fw_l2_filter_id; 562#define INVALID_MAC_INDEX ((uint16_t)-1) 563 uint16_t mac_index; 564 565 /* Filter Characteristics */ 566 uint32_t flags; 567 uint32_t enables; 568 uint8_t l2_addr[ETHER_ADDR_LEN]; 569 uint8_t l2_addr_mask[ETHER_ADDR_LEN]; 570 uint16_t l2_ovlan; 571 uint16_t l2_ovlan_mask; 572 uint16_t l2_ivlan; 573 uint16_t l2_ivlan_mask; 574 uint8_t t_l2_addr[ETHER_ADDR_LEN]; 575 uint8_t t_l2_addr_mask[ETHER_ADDR_LEN]; 576 uint16_t t_l2_ovlan; 577 uint16_t t_l2_ovlan_mask; 578 uint16_t t_l2_ivlan; 579 uint16_t t_l2_ivlan_mask; 580 uint8_t tunnel_type; 581 uint16_t mirror_vnic_id; 582 uint32_t vni; 583 uint8_t pri_hint; 584 uint64_t l2_filter_id_hint; 585}; 586 587/* Function declarations */ 588void bnxt_report_link(struct bnxt_softc *softc); 589bool bnxt_check_hwrm_version(struct bnxt_softc *softc); 590 591#endif /* _BNXT_H */ 592