if_ath_rx.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/sys/dev/ath/if_ath_rx.c 330897 2018-03-14 03:19:51Z eadler $"); 34 35/* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42#include "opt_inet.h" 43#include "opt_ath.h" 44/* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51#include "opt_ah.h" 52#include "opt_wlan.h" 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/sysctl.h> 57#include <sys/mbuf.h> 58#include <sys/malloc.h> 59#include <sys/lock.h> 60#include <sys/mutex.h> 61#include <sys/kernel.h> 62#include <sys/socket.h> 63#include <sys/sockio.h> 64#include <sys/errno.h> 65#include <sys/callout.h> 66#include <sys/bus.h> 67#include <sys/endian.h> 68#include <sys/kthread.h> 69#include <sys/taskqueue.h> 70#include <sys/priv.h> 71#include <sys/module.h> 72#include <sys/ktr.h> 73#include <sys/smp.h> /* for mp_ncpus */ 74 75#include <machine/bus.h> 76 77#include <net/if.h> 78#include <net/if_var.h> 79#include <net/if_dl.h> 80#include <net/if_media.h> 81#include <net/if_types.h> 82#include <net/if_arp.h> 83#include <net/ethernet.h> 84#include <net/if_llc.h> 85 86#include <net80211/ieee80211_var.h> 87#include <net80211/ieee80211_regdomain.h> 88#ifdef IEEE80211_SUPPORT_SUPERG 89#include <net80211/ieee80211_superg.h> 90#endif 91#ifdef IEEE80211_SUPPORT_TDMA 92#include <net80211/ieee80211_tdma.h> 93#endif 94 95#include <net/bpf.h> 96 97#ifdef INET 98#include <netinet/in.h> 99#include <netinet/if_ether.h> 100#endif 101 102#include <dev/ath/if_athvar.h> 103#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 104#include <dev/ath/ath_hal/ah_diagcodes.h> 105 106#include <dev/ath/if_ath_debug.h> 107#include <dev/ath/if_ath_misc.h> 108#include <dev/ath/if_ath_tsf.h> 109#include <dev/ath/if_ath_tx.h> 110#include <dev/ath/if_ath_sysctl.h> 111#include <dev/ath/if_ath_led.h> 112#include <dev/ath/if_ath_keycache.h> 113#include <dev/ath/if_ath_rx.h> 114#include <dev/ath/if_ath_beacon.h> 115#include <dev/ath/if_athdfs.h> 116#include <dev/ath/if_ath_descdma.h> 117 118#ifdef ATH_TX99_DIAG 119#include <dev/ath/ath_tx99/ath_tx99.h> 120#endif 121 122#ifdef ATH_DEBUG_ALQ 123#include <dev/ath/if_ath_alq.h> 124#endif 125 126#include <dev/ath/if_ath_lna_div.h> 127 128/* 129 * Calculate the receive filter according to the 130 * operating mode and state: 131 * 132 * o always accept unicast, broadcast, and multicast traffic 133 * o accept PHY error frames when hardware doesn't have MIB support 134 * to count and we need them for ANI (sta mode only until recently) 135 * and we are not scanning (ANI is disabled) 136 * NB: older hal's add rx filter bits out of sight and we need to 137 * blindly preserve them 138 * o probe request frames are accepted only when operating in 139 * hostap, adhoc, mesh, or monitor modes 140 * o enable promiscuous mode 141 * - when in monitor mode 142 * - if interface marked PROMISC (assumes bridge setting is filtered) 143 * o accept beacons: 144 * - when operating in station mode for collecting rssi data when 145 * the station is otherwise quiet, or 146 * - when operating in adhoc mode so the 802.11 layer creates 147 * node table entries for peers, 148 * - when scanning 149 * - when doing s/w beacon miss (e.g. for ap+sta) 150 * - when operating in ap mode in 11g to detect overlapping bss that 151 * require protection 152 * - when operating in mesh mode to detect neighbors 153 * o accept control frames: 154 * - when in monitor mode 155 * XXX HT protection for 11n 156 */ 157u_int32_t 158ath_calcrxfilter(struct ath_softc *sc) 159{ 160 struct ieee80211com *ic = &sc->sc_ic; 161 u_int32_t rfilt; 162 163 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 164 if (!sc->sc_needmib && !sc->sc_scanning) 165 rfilt |= HAL_RX_FILTER_PHYERR; 166 if (ic->ic_opmode != IEEE80211_M_STA) 167 rfilt |= HAL_RX_FILTER_PROBEREQ; 168 /* XXX ic->ic_monvaps != 0? */ 169 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0) 170 rfilt |= HAL_RX_FILTER_PROM; 171 172 /* 173 * Only listen to all beacons if we're scanning. 174 * 175 * Otherwise we only really need to hear beacons from 176 * our own BSSID. 177 * 178 * IBSS? software beacon miss? Just receive all beacons. 179 * We need to hear beacons/probe requests from everyone so 180 * we can merge ibss. 181 */ 182 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 183 rfilt |= HAL_RX_FILTER_BEACON; 184 } else if (ic->ic_opmode == IEEE80211_M_STA) { 185 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 186 rfilt |= HAL_RX_FILTER_MYBEACON; 187 } else { /* scanning, non-mybeacon chips */ 188 rfilt |= HAL_RX_FILTER_BEACON; 189 } 190 } 191 192 /* 193 * NB: We don't recalculate the rx filter when 194 * ic_protmode changes; otherwise we could do 195 * this only when ic_protmode != NONE. 196 */ 197 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 198 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 199 rfilt |= HAL_RX_FILTER_BEACON; 200 201 /* 202 * Enable hardware PS-POLL RX only for hostap mode; 203 * STA mode sends PS-POLL frames but never 204 * receives them. 205 */ 206 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 207 0, NULL) == HAL_OK && 208 ic->ic_opmode == IEEE80211_M_HOSTAP) 209 rfilt |= HAL_RX_FILTER_PSPOLL; 210 211 if (sc->sc_nmeshvaps) { 212 rfilt |= HAL_RX_FILTER_BEACON; 213 if (sc->sc_hasbmatch) 214 rfilt |= HAL_RX_FILTER_BSSID; 215 else 216 rfilt |= HAL_RX_FILTER_PROM; 217 } 218 if (ic->ic_opmode == IEEE80211_M_MONITOR) 219 rfilt |= HAL_RX_FILTER_CONTROL; 220 221 /* 222 * Enable RX of compressed BAR frames only when doing 223 * 802.11n. Required for A-MPDU. 224 */ 225 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 226 rfilt |= HAL_RX_FILTER_COMPBAR; 227 228 /* 229 * Enable radar PHY errors if requested by the 230 * DFS module. 231 */ 232 if (sc->sc_dodfs) 233 rfilt |= HAL_RX_FILTER_PHYRADAR; 234 235 /* 236 * Enable spectral PHY errors if requested by the 237 * spectral module. 238 */ 239 if (sc->sc_dospectral) 240 rfilt |= HAL_RX_FILTER_PHYRADAR; 241 242 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n", 243 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]); 244 return rfilt; 245} 246 247static int 248ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 249{ 250 struct ath_hal *ah = sc->sc_ah; 251 int error; 252 struct mbuf *m; 253 struct ath_desc *ds; 254 255 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 256 257 m = bf->bf_m; 258 if (m == NULL) { 259 /* 260 * NB: by assigning a page to the rx dma buffer we 261 * implicitly satisfy the Atheros requirement that 262 * this buffer be cache-line-aligned and sized to be 263 * multiple of the cache line size. Not doing this 264 * causes weird stuff to happen (for the 5210 at least). 265 */ 266 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 267 if (m == NULL) { 268 DPRINTF(sc, ATH_DEBUG_ANY, 269 "%s: no mbuf/cluster\n", __func__); 270 sc->sc_stats.ast_rx_nombuf++; 271 return ENOMEM; 272 } 273 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 274 275 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 276 bf->bf_dmamap, m, 277 bf->bf_segs, &bf->bf_nseg, 278 BUS_DMA_NOWAIT); 279 if (error != 0) { 280 DPRINTF(sc, ATH_DEBUG_ANY, 281 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 282 __func__, error); 283 sc->sc_stats.ast_rx_busdma++; 284 m_freem(m); 285 return error; 286 } 287 KASSERT(bf->bf_nseg == 1, 288 ("multi-segment packet; nseg %u", bf->bf_nseg)); 289 bf->bf_m = m; 290 } 291 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 292 293 /* 294 * Setup descriptors. For receive we always terminate 295 * the descriptor list with a self-linked entry so we'll 296 * not get overrun under high load (as can happen with a 297 * 5212 when ANI processing enables PHY error frames). 298 * 299 * To insure the last descriptor is self-linked we create 300 * each descriptor as self-linked and add it to the end. As 301 * each additional descriptor is added the previous self-linked 302 * entry is ``fixed'' naturally. This should be safe even 303 * if DMA is happening. When processing RX interrupts we 304 * never remove/process the last, self-linked, entry on the 305 * descriptor list. This insures the hardware always has 306 * someplace to write a new frame. 307 */ 308 /* 309 * 11N: we can no longer afford to self link the last descriptor. 310 * MAC acknowledges BA status as long as it copies frames to host 311 * buffer (or rx fifo). This can incorrectly acknowledge packets 312 * to a sender if last desc is self-linked. 313 */ 314 ds = bf->bf_desc; 315 if (sc->sc_rxslink) 316 ds->ds_link = bf->bf_daddr; /* link to self */ 317 else 318 ds->ds_link = 0; /* terminate the list */ 319 ds->ds_data = bf->bf_segs[0].ds_addr; 320 ath_hal_setuprxdesc(ah, ds 321 , m->m_len /* buffer size */ 322 , 0 323 ); 324 325 if (sc->sc_rxlink != NULL) 326 *sc->sc_rxlink = bf->bf_daddr; 327 sc->sc_rxlink = &ds->ds_link; 328 return 0; 329} 330 331/* 332 * Intercept management frames to collect beacon rssi data 333 * and to do ibss merges. 334 */ 335void 336ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 337 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) 338{ 339 struct ieee80211vap *vap = ni->ni_vap; 340 struct ath_softc *sc = vap->iv_ic->ic_softc; 341 uint64_t tsf_beacon_old, tsf_beacon; 342 uint64_t nexttbtt; 343 int64_t tsf_delta; 344 int32_t tsf_delta_bmiss; 345 int32_t tsf_remainder; 346 uint64_t tsf_beacon_target; 347 int tsf_intval; 348 349 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 350 tsf_beacon_old |= le32dec(ni->ni_tstamp.data); 351 352#define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 353 tsf_intval = 1; 354 if (ni->ni_intval > 0) { 355 tsf_intval = TU_TO_TSF(ni->ni_intval); 356 } 357#undef TU_TO_TSF 358 359 /* 360 * Call up first so subsequent work can use information 361 * potentially stored in the node (e.g. for ibss merge). 362 */ 363 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf); 364 switch (subtype) { 365 case IEEE80211_FC0_SUBTYPE_BEACON: 366 367 /* 368 * Only do the following processing if it's for 369 * the current BSS. 370 * 371 * In scan and IBSS mode we receive all beacons, 372 * which means we need to filter out stuff 373 * that isn't for us or we'll end up constantly 374 * trying to sync / merge to BSSes that aren't 375 * actually us. 376 */ 377 if (IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) { 378 /* update rssi statistics for use by the hal */ 379 /* XXX unlocked check against vap->iv_bss? */ 380 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 381 382 383 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 384 tsf_beacon |= le32dec(ni->ni_tstamp.data); 385 386 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 387 388 /* 389 * Let's calculate the delta and remainder, so we can see 390 * if the beacon timer from the AP is varying by more than 391 * a few TU. (Which would be a huge, huge problem.) 392 */ 393 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 394 395 tsf_delta_bmiss = tsf_delta / tsf_intval; 396 397 /* 398 * If our delta is greater than half the beacon interval, 399 * let's round the bmiss value up to the next beacon 400 * interval. Ie, we're running really, really early 401 * on the next beacon. 402 */ 403 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 404 tsf_delta_bmiss ++; 405 406 tsf_beacon_target = tsf_beacon_old + 407 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 408 409 /* 410 * The remainder using '%' is between 0 .. intval-1. 411 * If we're actually running too fast, then the remainder 412 * will be some large number just under intval-1. 413 * So we need to look at whether we're running 414 * before or after the target beacon interval 415 * and if we are, modify how we do the remainder 416 * calculation. 417 */ 418 if (tsf_beacon < tsf_beacon_target) { 419 tsf_remainder = 420 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 421 } else { 422 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 423 } 424 425 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu, new_tsf=%llu, target_tsf=%llu, delta=%lld, bmiss=%d, remainder=%d\n", 426 __func__, 427 (unsigned long long) tsf_beacon_old, 428 (unsigned long long) tsf_beacon, 429 (unsigned long long) tsf_beacon_target, 430 (long long) tsf_delta, 431 tsf_delta_bmiss, 432 tsf_remainder); 433 434 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu, nexttbtt=%llu, delta=%d\n", 435 __func__, 436 (unsigned long long) tsf_beacon, 437 (unsigned long long) nexttbtt, 438 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 439 440 /* We only do syncbeacon on STA VAPs; not on IBSS */ 441 if (vap->iv_opmode == IEEE80211_M_STA && 442 sc->sc_syncbeacon && 443 ni == vap->iv_bss && 444 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 445 DPRINTF(sc, ATH_DEBUG_BEACON, 446 "%s: syncbeacon=1; syncing\n", 447 __func__); 448 /* 449 * Resync beacon timers using the tsf of the beacon 450 * frame we just received. 451 */ 452 ath_beacon_config(sc, vap); 453 sc->sc_syncbeacon = 0; 454 } 455 } 456 457 /* fall thru... */ 458 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 459 if (vap->iv_opmode == IEEE80211_M_IBSS && 460 vap->iv_state == IEEE80211_S_RUN && 461 ieee80211_ibss_merge_check(ni)) { 462 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 463 uint64_t tsf = ath_extend_tsf(sc, rstamp, 464 ath_hal_gettsf64(sc->sc_ah)); 465 /* 466 * Handle ibss merge as needed; check the tsf on the 467 * frame before attempting the merge. The 802.11 spec 468 * says the station should change it's bssid to match 469 * the oldest station with the same ssid, where oldest 470 * is determined by the tsf. Note that hardware 471 * reconfiguration happens through callback to 472 * ath_newstate as the state machine will go from 473 * RUN -> RUN when this happens. 474 */ 475 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 476 DPRINTF(sc, ATH_DEBUG_STATE, 477 "ibss merge, rstamp %u tsf %ju " 478 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 479 (uintmax_t)ni->ni_tstamp.tsf); 480 (void) ieee80211_ibss_merge(ni); 481 } 482 } 483 break; 484 } 485} 486 487#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 488static void 489ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m, 490 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 491{ 492 493 /* Fill in the extension bitmap */ 494 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 495 496 /* Fill in the vendor header */ 497 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 498 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 499 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 500 501 /* XXX what should this be? */ 502 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 503 sc->sc_rx_th.wr_vh.vh_skip_len = 504 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 505 506 /* General version info */ 507 sc->sc_rx_th.wr_v.vh_version = 1; 508 509 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 510 511 /* rssi */ 512 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 513 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 514 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 515 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 516 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 517 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 518 519 /* evm */ 520 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 521 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 522 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 523 /* These are only populated from the AR9300 or later */ 524 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 525 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 526 527 /* direction */ 528 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 529 530 /* RX rate */ 531 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 532 533 /* RX flags */ 534 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 535 536 if (rs->rs_isaggr) 537 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 538 if (rs->rs_moreaggr) 539 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 540 541 /* phyerr info */ 542 if (rs->rs_status & HAL_RXERR_PHY) { 543 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 544 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 545 } else { 546 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 547 } 548 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 549 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 550} 551#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 552 553static void 554ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 555 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 556{ 557#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 558#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 559#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 560#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 561 const HAL_RATE_TABLE *rt; 562 uint8_t rix; 563 564 rt = sc->sc_currates; 565 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 566 rix = rt->rateCodeToIndex[rs->rs_rate]; 567 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 568 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 569#ifdef AH_SUPPORT_AR5416 570 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 571 if (rs->rs_status & HAL_RXERR_PHY) { 572 /* 573 * PHY error - make sure the channel flags 574 * reflect the actual channel configuration, 575 * not the received frame. 576 */ 577 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 578 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 579 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 580 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 581 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 582 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 583 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 584 struct ieee80211com *ic = &sc->sc_ic; 585 586 if ((rs->rs_flags & HAL_RX_2040) == 0) 587 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 588 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 589 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 590 else 591 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 592 if ((rs->rs_flags & HAL_RX_GI) == 0) 593 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 594 } 595 596#endif 597 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 598 if (rs->rs_status & HAL_RXERR_CRC) 599 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 600 /* XXX propagate other error flags from descriptor */ 601 sc->sc_rx_th.wr_antnoise = nf; 602 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 603 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 604#undef CHAN_HT 605#undef CHAN_HT20 606#undef CHAN_HT40U 607#undef CHAN_HT40D 608} 609 610static void 611ath_handle_micerror(struct ieee80211com *ic, 612 struct ieee80211_frame *wh, int keyix) 613{ 614 struct ieee80211_node *ni; 615 616 /* XXX recheck MIC to deal w/ chips that lie */ 617 /* XXX discard MIC errors on !data frames */ 618 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 619 if (ni != NULL) { 620 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 621 ieee80211_free_node(ni); 622 } 623} 624 625/* 626 * Process a single packet. 627 * 628 * The mbuf must already be synced, unmapped and removed from bf->bf_m 629 * by this stage. 630 * 631 * The mbuf must be consumed by this routine - either passed up the 632 * net80211 stack, put on the holding queue, or freed. 633 */ 634int 635ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 636 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 637 struct mbuf *m) 638{ 639 uint64_t rstamp; 640 int len, type; 641 struct ieee80211com *ic = &sc->sc_ic; 642 struct ieee80211_node *ni; 643 int is_good = 0; 644 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 645 646 /* 647 * Calculate the correct 64 bit TSF given 648 * the TSF64 register value and rs_tstamp. 649 */ 650 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 651 652 /* These aren't specifically errors */ 653#ifdef AH_SUPPORT_AR5416 654 if (rs->rs_flags & HAL_RX_GI) 655 sc->sc_stats.ast_rx_halfgi++; 656 if (rs->rs_flags & HAL_RX_2040) 657 sc->sc_stats.ast_rx_2040++; 658 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 659 sc->sc_stats.ast_rx_pre_crc_err++; 660 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 661 sc->sc_stats.ast_rx_post_crc_err++; 662 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 663 sc->sc_stats.ast_rx_decrypt_busy_err++; 664 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 665 sc->sc_stats.ast_rx_hi_rx_chain++; 666 if (rs->rs_flags & HAL_RX_STBC) 667 sc->sc_stats.ast_rx_stbc++; 668#endif /* AH_SUPPORT_AR5416 */ 669 670 if (rs->rs_status != 0) { 671 if (rs->rs_status & HAL_RXERR_CRC) 672 sc->sc_stats.ast_rx_crcerr++; 673 if (rs->rs_status & HAL_RXERR_FIFO) 674 sc->sc_stats.ast_rx_fifoerr++; 675 if (rs->rs_status & HAL_RXERR_PHY) { 676 sc->sc_stats.ast_rx_phyerr++; 677 /* Process DFS radar events */ 678 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 679 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 680 /* Now pass it to the radar processing code */ 681 ath_dfs_process_phy_err(sc, m, rstamp, rs); 682 } 683 684 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 685 if (rs->rs_phyerr < 64) 686 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 687 goto rx_error; /* NB: don't count in ierrors */ 688 } 689 if (rs->rs_status & HAL_RXERR_DECRYPT) { 690 /* 691 * Decrypt error. If the error occurred 692 * because there was no hardware key, then 693 * let the frame through so the upper layers 694 * can process it. This is necessary for 5210 695 * parts which have no way to setup a ``clear'' 696 * key cache entry. 697 * 698 * XXX do key cache faulting 699 */ 700 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 701 goto rx_accept; 702 sc->sc_stats.ast_rx_badcrypt++; 703 } 704 /* 705 * Similar as above - if the failure was a keymiss 706 * just punt it up to the upper layers for now. 707 */ 708 if (rs->rs_status & HAL_RXERR_KEYMISS) { 709 sc->sc_stats.ast_rx_keymiss++; 710 goto rx_accept; 711 } 712 if (rs->rs_status & HAL_RXERR_MIC) { 713 sc->sc_stats.ast_rx_badmic++; 714 /* 715 * Do minimal work required to hand off 716 * the 802.11 header for notification. 717 */ 718 /* XXX frag's and qos frames */ 719 len = rs->rs_datalen; 720 if (len >= sizeof (struct ieee80211_frame)) { 721 ath_handle_micerror(ic, 722 mtod(m, struct ieee80211_frame *), 723 sc->sc_splitmic ? 724 rs->rs_keyix-32 : rs->rs_keyix); 725 } 726 } 727 counter_u64_add(ic->ic_ierrors, 1); 728rx_error: 729 /* 730 * Cleanup any pending partial frame. 731 */ 732 if (re->m_rxpending != NULL) { 733 m_freem(re->m_rxpending); 734 re->m_rxpending = NULL; 735 } 736 /* 737 * When a tap is present pass error frames 738 * that have been requested. By default we 739 * pass decrypt+mic errors but others may be 740 * interesting (e.g. crc). 741 */ 742 if (ieee80211_radiotap_active(ic) && 743 (rs->rs_status & sc->sc_monpass)) { 744 /* NB: bpf needs the mbuf length setup */ 745 len = rs->rs_datalen; 746 m->m_pkthdr.len = m->m_len = len; 747 ath_rx_tap(sc, m, rs, rstamp, nf); 748#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 749 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 750#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 751 ieee80211_radiotap_rx_all(ic, m); 752 } 753 /* XXX pass MIC errors up for s/w reclaculation */ 754 m_freem(m); m = NULL; 755 goto rx_next; 756 } 757rx_accept: 758 len = rs->rs_datalen; 759 m->m_len = len; 760 761 if (rs->rs_more) { 762 /* 763 * Frame spans multiple descriptors; save 764 * it for the next completed descriptor, it 765 * will be used to construct a jumbogram. 766 */ 767 if (re->m_rxpending != NULL) { 768 /* NB: max frame size is currently 2 clusters */ 769 sc->sc_stats.ast_rx_toobig++; 770 m_freem(re->m_rxpending); 771 } 772 m->m_pkthdr.len = len; 773 re->m_rxpending = m; 774 m = NULL; 775 goto rx_next; 776 } else if (re->m_rxpending != NULL) { 777 /* 778 * This is the second part of a jumbogram, 779 * chain it to the first mbuf, adjust the 780 * frame length, and clear the rxpending state. 781 */ 782 re->m_rxpending->m_next = m; 783 re->m_rxpending->m_pkthdr.len += len; 784 m = re->m_rxpending; 785 re->m_rxpending = NULL; 786 } else { 787 /* 788 * Normal single-descriptor receive; setup packet length. 789 */ 790 m->m_pkthdr.len = len; 791 } 792 793 /* 794 * Validate rs->rs_antenna. 795 * 796 * Some users w/ AR9285 NICs have reported crashes 797 * here because rs_antenna field is bogusly large. 798 * Let's enforce the maximum antenna limit of 8 799 * (and it shouldn't be hard coded, but that's a 800 * separate problem) and if there's an issue, print 801 * out an error and adjust rs_antenna to something 802 * sensible. 803 * 804 * This code should be removed once the actual 805 * root cause of the issue has been identified. 806 * For example, it may be that the rs_antenna 807 * field is only valid for the last frame of 808 * an aggregate and it just happens that it is 809 * "mostly" right. (This is a general statement - 810 * the majority of the statistics are only valid 811 * for the last frame in an aggregate. 812 */ 813 if (rs->rs_antenna > 7) { 814 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 815 __func__, rs->rs_antenna); 816#ifdef ATH_DEBUG 817 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 818#endif /* ATH_DEBUG */ 819 rs->rs_antenna = 0; /* XXX better than nothing */ 820 } 821 822 /* 823 * If this is an AR9285/AR9485, then the receive and LNA 824 * configuration is stored in RSSI[2] / EXTRSSI[2]. 825 * We can extract this out to build a much better 826 * receive antenna profile. 827 * 828 * Yes, this just blurts over the above RX antenna field 829 * for now. It's fine, the AR9285 doesn't really use 830 * that. 831 * 832 * Later on we should store away the fine grained LNA 833 * information and keep separate counters just for 834 * that. It'll help when debugging the AR9285/AR9485 835 * combined diversity code. 836 */ 837 if (sc->sc_rx_lnamixer) { 838 rs->rs_antenna = 0; 839 840 /* Bits 0:1 - the LNA configuration used */ 841 rs->rs_antenna |= 842 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 843 >> HAL_RX_LNA_CFG_USED_S); 844 845 /* Bit 2 - the external RX antenna switch */ 846 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 847 rs->rs_antenna |= 0x4; 848 } 849 850 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 851 852 /* 853 * Populate the rx status block. When there are bpf 854 * listeners we do the additional work to provide 855 * complete status. Otherwise we fill in only the 856 * material required by ieee80211_input. Note that 857 * noise setting is filled in above. 858 */ 859 if (ieee80211_radiotap_active(ic)) { 860 ath_rx_tap(sc, m, rs, rstamp, nf); 861#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 862 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 863#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 864 } 865 866 /* 867 * From this point on we assume the frame is at least 868 * as large as ieee80211_frame_min; verify that. 869 */ 870 if (len < IEEE80211_MIN_LEN) { 871 if (!ieee80211_radiotap_active(ic)) { 872 DPRINTF(sc, ATH_DEBUG_RECV, 873 "%s: short packet %d\n", __func__, len); 874 sc->sc_stats.ast_rx_tooshort++; 875 } else { 876 /* NB: in particular this captures ack's */ 877 ieee80211_radiotap_rx_all(ic, m); 878 } 879 m_freem(m); m = NULL; 880 goto rx_next; 881 } 882 883 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 884 const HAL_RATE_TABLE *rt = sc->sc_currates; 885 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 886 887 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 888 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 889 } 890 891 m_adj(m, -IEEE80211_CRC_LEN); 892 893 /* 894 * Locate the node for sender, track state, and then 895 * pass the (referenced) node up to the 802.11 layer 896 * for its use. 897 */ 898 ni = ieee80211_find_rxnode_withkey(ic, 899 mtod(m, const struct ieee80211_frame_min *), 900 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 901 IEEE80211_KEYIX_NONE : rs->rs_keyix); 902 sc->sc_lastrs = rs; 903 904#ifdef AH_SUPPORT_AR5416 905 if (rs->rs_isaggr) 906 sc->sc_stats.ast_rx_agg++; 907#endif /* AH_SUPPORT_AR5416 */ 908 909 if (ni != NULL) { 910 /* 911 * Only punt packets for ampdu reorder processing for 912 * 11n nodes; net80211 enforces that M_AMPDU is only 913 * set for 11n nodes. 914 */ 915 if (ni->ni_flags & IEEE80211_NODE_HT) 916 m->m_flags |= M_AMPDU; 917 918 /* 919 * Sending station is known, dispatch directly. 920 */ 921 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 922 ieee80211_free_node(ni); 923 m = NULL; 924 /* 925 * Arrange to update the last rx timestamp only for 926 * frames from our ap when operating in station mode. 927 * This assumes the rx key is always setup when 928 * associated. 929 */ 930 if (ic->ic_opmode == IEEE80211_M_STA && 931 rs->rs_keyix != HAL_RXKEYIX_INVALID) 932 is_good = 1; 933 } else { 934 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 935 m = NULL; 936 } 937 938 /* 939 * At this point we have passed the frame up the stack; thus 940 * the mbuf is no longer ours. 941 */ 942 943 /* 944 * Track rx rssi and do any rx antenna management. 945 */ 946 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 947 if (sc->sc_diversity) { 948 /* 949 * When using fast diversity, change the default rx 950 * antenna if diversity chooses the other antenna 3 951 * times in a row. 952 */ 953 if (sc->sc_defant != rs->rs_antenna) { 954 if (++sc->sc_rxotherant >= 3) 955 ath_setdefantenna(sc, rs->rs_antenna); 956 } else 957 sc->sc_rxotherant = 0; 958 } 959 960 /* Handle slow diversity if enabled */ 961 if (sc->sc_dolnadiv) { 962 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 963 } 964 965 if (sc->sc_softled) { 966 /* 967 * Blink for any data frame. Otherwise do a 968 * heartbeat-style blink when idle. The latter 969 * is mainly for station mode where we depend on 970 * periodic beacon frames to trigger the poll event. 971 */ 972 if (type == IEEE80211_FC0_TYPE_DATA) { 973 const HAL_RATE_TABLE *rt = sc->sc_currates; 974 ath_led_event(sc, 975 rt->rateCodeToIndex[rs->rs_rate]); 976 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 977 ath_led_event(sc, 0); 978 } 979rx_next: 980 /* 981 * Debugging - complain if we didn't NULL the mbuf pointer 982 * here. 983 */ 984 if (m != NULL) { 985 device_printf(sc->sc_dev, 986 "%s: mbuf %p should've been freed!\n", 987 __func__, 988 m); 989 } 990 return (is_good); 991} 992 993#define ATH_RX_MAX 128 994 995/* 996 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 997 * the EDMA code does. 998 * 999 * XXX TODO: then, do all of the RX list management stuff inside 1000 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 1001 * code is doing it right. 1002 */ 1003static void 1004ath_rx_proc(struct ath_softc *sc, int resched) 1005{ 1006#define PA2DESC(_sc, _pa) \ 1007 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1008 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1009 struct ath_buf *bf; 1010 struct ath_hal *ah = sc->sc_ah; 1011#ifdef IEEE80211_SUPPORT_SUPERG 1012 struct ieee80211com *ic = &sc->sc_ic; 1013#endif 1014 struct ath_desc *ds; 1015 struct ath_rx_status *rs; 1016 struct mbuf *m; 1017 int ngood; 1018 HAL_STATUS status; 1019 int16_t nf; 1020 u_int64_t tsf; 1021 int npkts = 0; 1022 int kickpcu = 0; 1023 int ret; 1024 1025 /* XXX we must not hold the ATH_LOCK here */ 1026 ATH_UNLOCK_ASSERT(sc); 1027 ATH_PCU_UNLOCK_ASSERT(sc); 1028 1029 ATH_PCU_LOCK(sc); 1030 sc->sc_rxproc_cnt++; 1031 kickpcu = sc->sc_kickpcu; 1032 ATH_PCU_UNLOCK(sc); 1033 1034 ATH_LOCK(sc); 1035 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1036 ATH_UNLOCK(sc); 1037 1038 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1039 ngood = 0; 1040 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1041 sc->sc_stats.ast_rx_noise = nf; 1042 tsf = ath_hal_gettsf64(ah); 1043 do { 1044 /* 1045 * Don't process too many packets at a time; give the 1046 * TX thread time to also run - otherwise the TX 1047 * latency can jump by quite a bit, causing throughput 1048 * degredation. 1049 */ 1050 if (!kickpcu && npkts >= ATH_RX_MAX) 1051 break; 1052 1053 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1054 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1055 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__); 1056 break; 1057 } else if (bf == NULL) { 1058 /* 1059 * End of List: 1060 * this can happen for non-self-linked RX chains 1061 */ 1062 sc->sc_stats.ast_rx_hitqueueend++; 1063 break; 1064 } 1065 m = bf->bf_m; 1066 if (m == NULL) { /* NB: shouldn't happen */ 1067 /* 1068 * If mbuf allocation failed previously there 1069 * will be no mbuf; try again to re-populate it. 1070 */ 1071 /* XXX make debug msg */ 1072 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__); 1073 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1074 goto rx_proc_next; 1075 } 1076 ds = bf->bf_desc; 1077 if (ds->ds_link == bf->bf_daddr) { 1078 /* NB: never process the self-linked entry at the end */ 1079 sc->sc_stats.ast_rx_hitqueueend++; 1080 break; 1081 } 1082 /* XXX sync descriptor memory */ 1083 /* 1084 * Must provide the virtual address of the current 1085 * descriptor, the physical address, and the virtual 1086 * address of the next descriptor in the h/w chain. 1087 * This allows the HAL to look ahead to see if the 1088 * hardware is done with a descriptor by checking the 1089 * done bit in the following descriptor and the address 1090 * of the current descriptor the DMA engine is working 1091 * on. All this is necessary because of our use of 1092 * a self-linked list to avoid rx overruns. 1093 */ 1094 rs = &bf->bf_status.ds_rxstat; 1095 status = ath_hal_rxprocdesc(ah, ds, 1096 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1097#ifdef ATH_DEBUG 1098 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1099 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1100#endif 1101 1102#ifdef ATH_DEBUG_ALQ 1103 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1104 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1105 sc->sc_rx_statuslen, (char *) ds); 1106#endif /* ATH_DEBUG_ALQ */ 1107 1108 if (status == HAL_EINPROGRESS) 1109 break; 1110 1111 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1112 npkts++; 1113 1114 /* 1115 * Process a single frame. 1116 */ 1117 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1118 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1119 bf->bf_m = NULL; 1120 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1121 ngood++; 1122rx_proc_next: 1123 /* 1124 * If there's a holding buffer, insert that onto 1125 * the RX list; the hardware is now definitely not pointing 1126 * to it now. 1127 */ 1128 ret = 0; 1129 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1130 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1131 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1132 bf_list); 1133 ret = ath_rxbuf_init(sc, 1134 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1135 } 1136 /* 1137 * Next, throw our buffer into the holding entry. The hardware 1138 * may use the descriptor to read the link pointer before 1139 * DMAing the next descriptor in to write out a packet. 1140 */ 1141 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1142 } while (ret == 0); 1143 1144 /* rx signal state monitoring */ 1145 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1146 if (ngood) 1147 sc->sc_lastrx = tsf; 1148 1149 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1150 /* Queue DFS tasklet if needed */ 1151 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1152 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1153 1154 /* 1155 * Now that all the RX frames were handled that 1156 * need to be handled, kick the PCU if there's 1157 * been an RXEOL condition. 1158 */ 1159 if (resched && kickpcu) { 1160 ATH_PCU_LOCK(sc); 1161 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1162 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1163 __func__, npkts); 1164 1165 /* 1166 * Go through the process of fully tearing down 1167 * the RX buffers and reinitialising them. 1168 * 1169 * There's a hardware bug that causes the RX FIFO 1170 * to get confused under certain conditions and 1171 * constantly write over the same frame, leading 1172 * the RX driver code here to get heavily confused. 1173 */ 1174 /* 1175 * XXX Has RX DMA stopped enough here to just call 1176 * ath_startrecv()? 1177 * XXX Do we need to use the holding buffer to restart 1178 * RX DMA by appending entries to the final 1179 * descriptor? Quite likely. 1180 */ 1181#if 1 1182 ath_startrecv(sc); 1183#else 1184 /* 1185 * Disabled for now - it'd be nice to be able to do 1186 * this in order to limit the amount of CPU time spent 1187 * reinitialising the RX side (and thus minimise RX 1188 * drops) however there's a hardware issue that 1189 * causes things to get too far out of whack. 1190 */ 1191 /* 1192 * XXX can we hold the PCU lock here? 1193 * Are there any net80211 buffer calls involved? 1194 */ 1195 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1196 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1197 ath_hal_rxena(ah); /* enable recv descriptors */ 1198 ath_mode_init(sc); /* set filters, etc. */ 1199 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1200#endif 1201 1202 ath_hal_intrset(ah, sc->sc_imask); 1203 sc->sc_kickpcu = 0; 1204 ATH_PCU_UNLOCK(sc); 1205 } 1206 1207#ifdef IEEE80211_SUPPORT_SUPERG 1208 if (resched) 1209 ieee80211_ff_age_all(ic, 100); 1210#endif 1211 1212 /* 1213 * Put the hardware to sleep again if we're done with it. 1214 */ 1215 ATH_LOCK(sc); 1216 ath_power_restore_power_state(sc); 1217 ATH_UNLOCK(sc); 1218 1219 /* 1220 * If we hit the maximum number of frames in this round, 1221 * reschedule for another immediate pass. This gives 1222 * the TX and TX completion routines time to run, which 1223 * will reduce latency. 1224 */ 1225 if (npkts >= ATH_RX_MAX) 1226 sc->sc_rx.recv_sched(sc, resched); 1227 1228 ATH_PCU_LOCK(sc); 1229 sc->sc_rxproc_cnt--; 1230 ATH_PCU_UNLOCK(sc); 1231} 1232#undef PA2DESC 1233#undef ATH_RX_MAX 1234 1235/* 1236 * Only run the RX proc if it's not already running. 1237 * Since this may get run as part of the reset/flush path, 1238 * the task can't clash with an existing, running tasklet. 1239 */ 1240static void 1241ath_legacy_rx_tasklet(void *arg, int npending) 1242{ 1243 struct ath_softc *sc = arg; 1244 1245 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1246 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1247 ATH_PCU_LOCK(sc); 1248 if (sc->sc_inreset_cnt > 0) { 1249 device_printf(sc->sc_dev, 1250 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1251 ATH_PCU_UNLOCK(sc); 1252 return; 1253 } 1254 ATH_PCU_UNLOCK(sc); 1255 1256 ath_rx_proc(sc, 1); 1257} 1258 1259static void 1260ath_legacy_flushrecv(struct ath_softc *sc) 1261{ 1262 1263 ath_rx_proc(sc, 0); 1264} 1265 1266static void 1267ath_legacy_flush_rxpending(struct ath_softc *sc) 1268{ 1269 1270 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1271 1272 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1273 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1274 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1275 } 1276 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1277 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1278 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1279 } 1280} 1281 1282static int 1283ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1284{ 1285 struct ath_buf *bf; 1286 1287 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1288 /* 1289 * If there are RX holding buffers, free them here and return 1290 * them to the list. 1291 * 1292 * XXX should just verify that bf->bf_m is NULL, as it must 1293 * be at this point! 1294 */ 1295 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1296 if (bf != NULL) { 1297 if (bf->bf_m != NULL) 1298 m_freem(bf->bf_m); 1299 bf->bf_m = NULL; 1300 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1301 (void) ath_rxbuf_init(sc, bf); 1302 } 1303 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1304 1305 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1306 if (bf != NULL) { 1307 if (bf->bf_m != NULL) 1308 m_freem(bf->bf_m); 1309 bf->bf_m = NULL; 1310 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1311 (void) ath_rxbuf_init(sc, bf); 1312 } 1313 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1314 1315 return (0); 1316} 1317 1318/* 1319 * Disable the receive h/w in preparation for a reset. 1320 */ 1321static void 1322ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1323{ 1324#define PA2DESC(_sc, _pa) \ 1325 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1326 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1327 struct ath_hal *ah = sc->sc_ah; 1328 1329 ATH_RX_LOCK(sc); 1330 1331 ath_hal_stoppcurecv(ah); /* disable PCU */ 1332 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1333 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1334 /* 1335 * TODO: see if this particular DELAY() is required; it may be 1336 * masking some missing FIFO flush or DMA sync. 1337 */ 1338#if 0 1339 if (dodelay) 1340#endif 1341 DELAY(3000); /* 3ms is long enough for 1 frame */ 1342#ifdef ATH_DEBUG 1343 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1344 struct ath_buf *bf; 1345 u_int ix; 1346 1347 device_printf(sc->sc_dev, 1348 "%s: rx queue %p, link %p\n", 1349 __func__, 1350 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1351 sc->sc_rxlink); 1352 ix = 0; 1353 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1354 struct ath_desc *ds = bf->bf_desc; 1355 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1356 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1357 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1358 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1359 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1360 ix++; 1361 } 1362 } 1363#endif 1364 1365 (void) ath_legacy_flush_rxpending(sc); 1366 (void) ath_legacy_flush_rxholdbf(sc); 1367 1368 sc->sc_rxlink = NULL; /* just in case */ 1369 1370 ATH_RX_UNLOCK(sc); 1371#undef PA2DESC 1372} 1373 1374/* 1375 * XXX TODO: something was calling startrecv without calling 1376 * stoprecv. Let's figure out what/why. It was showing up 1377 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1378 */ 1379 1380/* 1381 * Enable the receive h/w following a reset. 1382 */ 1383static int 1384ath_legacy_startrecv(struct ath_softc *sc) 1385{ 1386 struct ath_hal *ah = sc->sc_ah; 1387 struct ath_buf *bf; 1388 1389 ATH_RX_LOCK(sc); 1390 1391 /* 1392 * XXX should verify these are already all NULL! 1393 */ 1394 sc->sc_rxlink = NULL; 1395 (void) ath_legacy_flush_rxpending(sc); 1396 (void) ath_legacy_flush_rxholdbf(sc); 1397 1398 /* 1399 * Re-chain all of the buffers in the RX buffer list. 1400 */ 1401 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1402 int error = ath_rxbuf_init(sc, bf); 1403 if (error != 0) { 1404 DPRINTF(sc, ATH_DEBUG_RECV, 1405 "%s: ath_rxbuf_init failed %d\n", 1406 __func__, error); 1407 return error; 1408 } 1409 } 1410 1411 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1412 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1413 ath_hal_rxena(ah); /* enable recv descriptors */ 1414 ath_mode_init(sc); /* set filters, etc. */ 1415 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1416 1417 ATH_RX_UNLOCK(sc); 1418 return 0; 1419} 1420 1421static int 1422ath_legacy_dma_rxsetup(struct ath_softc *sc) 1423{ 1424 int error; 1425 1426 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1427 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1428 if (error != 0) 1429 return (error); 1430 1431 return (0); 1432} 1433 1434static int 1435ath_legacy_dma_rxteardown(struct ath_softc *sc) 1436{ 1437 1438 if (sc->sc_rxdma.dd_desc_len != 0) 1439 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1440 return (0); 1441} 1442 1443static void 1444ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1445{ 1446 1447 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1448} 1449 1450static void 1451ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1452 int dosched) 1453{ 1454 1455 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1456} 1457 1458void 1459ath_recv_setup_legacy(struct ath_softc *sc) 1460{ 1461 1462 /* Sensible legacy defaults */ 1463 /* 1464 * XXX this should be changed to properly support the 1465 * exact RX descriptor size for each HAL. 1466 */ 1467 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1468 1469 sc->sc_rx.recv_start = ath_legacy_startrecv; 1470 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1471 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1472 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1473 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1474 1475 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1476 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1477 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1478 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1479} 1480