ata-intel.c revision 331722
1/*- 2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/dev/ata/chipsets/ata-intel.c 331722 2018-03-29 02:50:57Z eadler $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include <dev/ata/ata-all.h> 50#include <dev/ata/ata-pci.h> 51#include <ata_if.h> 52 53/* local prototypes */ 54static int ata_intel_chipinit(device_t dev); 55static int ata_intel_chipdeinit(device_t dev); 56static int ata_intel_ch_attach(device_t dev); 57static void ata_intel_reset(device_t dev); 58static int ata_intel_old_setmode(device_t dev, int target, int mode); 59static int ata_intel_new_setmode(device_t dev, int target, int mode); 60static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61static int ata_intel_sata_getrev(device_t dev, int target); 62static int ata_intel_sata_status(device_t dev); 63static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75static int ata_intel_sata_sidpr_test(device_t dev); 76static int ata_intel_31244_ch_attach(device_t dev); 77static int ata_intel_31244_ch_detach(device_t dev); 78static int ata_intel_31244_status(device_t dev); 79static void ata_intel_31244_tf_write(struct ata_request *request); 80static void ata_intel_31244_reset(device_t dev); 81 82/* misc defines */ 83#define INTEL_ICH5 2 84#define INTEL_6CH 4 85#define INTEL_6CH2 8 86#define INTEL_ICH7 16 87 88struct ata_intel_data { 89 struct mtx lock; 90 u_char smap[4]; 91}; 92 93#define ATA_INTEL_SMAP(ctlr, ch) \ 94 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 95#define ATA_INTEL_LOCK(ctlr) \ 96 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 97#define ATA_INTEL_UNLOCK(ctlr) \ 98 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 99 100/* 101 * Intel chipset support functions 102 */ 103static int 104ata_intel_probe(device_t dev) 105{ 106 struct ata_pci_controller *ctlr = device_get_softc(dev); 107 static const struct ata_chip_id ids[] = 108 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 109 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 110 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 111 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 114 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 115 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 116 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 117 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 118 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 119 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 120 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 121 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 122 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 123 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 124 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 125 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 126 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 127 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 128 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 129 { ATA_I82801FB_S1, 0, 0, 0, ATA_SA150, "ICH6" }, 130 { ATA_I82801FB_R1, 0, 0, 0, ATA_SA150, "ICH6" }, 131 { ATA_I82801FBM, 0, 0, 0, ATA_SA150, "ICH6M" }, 132 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 133 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 134 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 135 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 136 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 137 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 138 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 139 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 140 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 141 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 142 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 143 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 144 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 145 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 146 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 147 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 148 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 149 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 150 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 151 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 152 { ATA_IBP_S1, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak" }, 153 { ATA_IBP_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak" }, 154 { ATA_IBP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak" }, 155 { ATA_IBP_S4, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak-M" }, 156 { ATA_IBP_S5, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak-M" }, 157 { ATA_IBP_S6, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak-M" }, 158 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" }, 159 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" }, 160 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 161 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 162 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA600, "Patsburg" }, 163 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 164 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" }, 165 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" }, 166 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 167 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 168 { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" }, 169 { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" }, 170 { ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 171 { ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 172 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" }, 173 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" }, 174 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" }, 175 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" }, 176 { ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" }, 177 { ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" }, 178 { ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" }, 179 { ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" }, 180 { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" }, 181 { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" }, 182 { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" }, 183 { ATA_WELLS_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" }, 184 { ATA_LPTLP_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" }, 185 { ATA_LPTLP_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" }, 186 { ATA_LPTLP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 187 { ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 188 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 189 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 190 { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 191 { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 192 { 0, 0, 0, 0, 0, 0}}; 193 194 if (pci_get_vendor(dev) != ATA_INTEL_ID) 195 return ENXIO; 196 197 if (!(ctlr->chip = ata_match_chip(dev, ids))) 198 return ENXIO; 199 200 ata_set_desc(dev); 201 ctlr->chipinit = ata_intel_chipinit; 202 ctlr->chipdeinit = ata_intel_chipdeinit; 203 return (BUS_PROBE_LOW_PRIORITY); 204} 205 206static int 207ata_intel_chipinit(device_t dev) 208{ 209 struct ata_pci_controller *ctlr = device_get_softc(dev); 210 struct ata_intel_data *data; 211 212 if (ata_setup_interrupt(dev, ata_generic_intr)) 213 return ENXIO; 214 215 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 216 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 217 ctlr->chipset_data = (void *)data; 218 219 /* good old PIIX needs special treatment (not implemented) */ 220 if (ctlr->chip->chipid == ATA_I82371FB) { 221 ctlr->setmode = ata_intel_old_setmode; 222 } 223 224 /* the intel 31244 needs special care if in DPA mode */ 225 else if (ctlr->chip->chipid == ATA_I31244) { 226 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 227 ctlr->r_type2 = SYS_RES_MEMORY; 228 ctlr->r_rid2 = PCIR_BAR(0); 229 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 230 &ctlr->r_rid2, 231 RF_ACTIVE))) 232 return ENXIO; 233 ctlr->channels = 4; 234 ctlr->ch_attach = ata_intel_31244_ch_attach; 235 ctlr->ch_detach = ata_intel_31244_ch_detach; 236 ctlr->reset = ata_intel_31244_reset; 237 } 238 ctlr->setmode = ata_sata_setmode; 239 ctlr->getrev = ata_sata_getrev; 240 } 241 /* SCH */ 242 else if (ctlr->chip->chipid == ATA_ISCH) { 243 ctlr->channels = 1; 244 ctlr->ch_attach = ata_intel_ch_attach; 245 ctlr->ch_detach = ata_pci_ch_detach; 246 ctlr->setmode = ata_intel_sch_setmode; 247 } 248 /* non SATA intel chips goes here */ 249 else if (ctlr->chip->max_dma < ATA_SA150) { 250 ctlr->channels = ctlr->chip->cfg2; 251 ctlr->ch_attach = ata_intel_ch_attach; 252 ctlr->ch_detach = ata_pci_ch_detach; 253 ctlr->setmode = ata_intel_new_setmode; 254 } 255 256 /* SATA parts can be either compat or AHCI */ 257 else { 258 /* force all ports active "the legacy way" */ 259 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 260 261 ctlr->ch_attach = ata_intel_ch_attach; 262 ctlr->ch_detach = ata_pci_ch_detach; 263 ctlr->reset = ata_intel_reset; 264 265 /* BAR(5) may point to SATA interface registers */ 266 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 267 ctlr->r_type2 = SYS_RES_MEMORY; 268 ctlr->r_rid2 = PCIR_BAR(5); 269 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 270 &ctlr->r_rid2, RF_ACTIVE); 271 if (ctlr->r_res2 != NULL) { 272 /* Set SCRAE bit to enable registers access. */ 273 pci_write_config(dev, 0x94, 274 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 275 /* Set Ports Implemented register bits. */ 276 ATA_OUTL(ctlr->r_res2, 0x0C, 277 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 278 } 279 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 280 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 281 pci_get_subvendor(dev) != 0x106b) { 282 ctlr->r_type2 = SYS_RES_IOPORT; 283 ctlr->r_rid2 = PCIR_BAR(5); 284 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 285 &ctlr->r_rid2, RF_ACTIVE); 286 } 287 if (ctlr->r_res2 != NULL || 288 (ctlr->chip->cfg1 & INTEL_ICH5)) 289 ctlr->getrev = ata_intel_sata_getrev; 290 ctlr->setmode = ata_sata_setmode; 291 } 292 return 0; 293} 294 295static int 296ata_intel_chipdeinit(device_t dev) 297{ 298 struct ata_pci_controller *ctlr = device_get_softc(dev); 299 struct ata_intel_data *data; 300 301 data = ctlr->chipset_data; 302 mtx_destroy(&data->lock); 303 free(data, M_ATAPCI); 304 ctlr->chipset_data = NULL; 305 return (0); 306} 307 308static int 309ata_intel_ch_attach(device_t dev) 310{ 311 struct ata_pci_controller *ctlr; 312 struct ata_channel *ch; 313 u_char *smap; 314 u_int map; 315 316 /* setup the usual register normal pci style */ 317 if (ata_pci_ch_attach(dev)) 318 return (ENXIO); 319 320 ctlr = device_get_softc(device_get_parent(dev)); 321 ch = device_get_softc(dev); 322 323 /* if r_res2 is valid it points to SATA interface registers */ 324 if (ctlr->r_res2) { 325 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 326 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 327 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 328 ch->r_io[ATA_IDX_DATA].offset = 0x04; 329 } 330 331 ch->flags |= ATA_ALWAYS_DMASTAT; 332 if (ctlr->chip->max_dma >= ATA_SA150) { 333 smap = ATA_INTEL_SMAP(ctlr, ch); 334 map = pci_read_config(device_get_parent(dev), 0x90, 1); 335 if (ctlr->chip->cfg1 & INTEL_ICH5) { 336 map &= 0x07; 337 if ((map & 0x04) == 0) { 338 ch->flags |= ATA_SATA; 339 ch->flags |= ATA_NO_SLAVE; 340 smap[0] = (map & 0x01) ^ ch->unit; 341 smap[1] = 0; 342 } else if ((map & 0x02) == 0 && ch->unit == 0) { 343 ch->flags |= ATA_SATA; 344 smap[0] = (map & 0x01) ? 1 : 0; 345 smap[1] = (map & 0x01) ? 0 : 1; 346 } else if ((map & 0x02) != 0 && ch->unit == 1) { 347 ch->flags |= ATA_SATA; 348 smap[0] = (map & 0x01) ? 1 : 0; 349 smap[1] = (map & 0x01) ? 0 : 1; 350 } 351 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 352 ch->flags |= ATA_SATA; 353 ch->flags |= ATA_NO_SLAVE; 354 smap[0] = (ch->unit == 0) ? 0 : 1; 355 smap[1] = 0; 356 } else { 357 map &= 0x03; 358 if (map == 0x00) { 359 ch->flags |= ATA_SATA; 360 smap[0] = (ch->unit == 0) ? 0 : 1; 361 smap[1] = (ch->unit == 0) ? 2 : 3; 362 } else if (map == 0x02 && ch->unit == 0) { 363 ch->flags |= ATA_SATA; 364 smap[0] = 0; 365 smap[1] = 2; 366 } else if (map == 0x01 && ch->unit == 1) { 367 ch->flags |= ATA_SATA; 368 smap[0] = 1; 369 smap[1] = 3; 370 } 371 } 372 if (ch->flags & ATA_SATA) { 373 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 374 ch->hw.pm_read = ata_intel_sata_cscr_read; 375 ch->hw.pm_write = ata_intel_sata_cscr_write; 376 } else if (ctlr->r_res2) { 377 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 378 ch->hw.pm_read = ata_intel_sata_ahci_read; 379 ch->hw.pm_write = ata_intel_sata_ahci_write; 380 } else if (ata_intel_sata_sidpr_test(dev)) { 381 ch->hw.pm_read = ata_intel_sata_sidpr_read; 382 ch->hw.pm_write = ata_intel_sata_sidpr_write; 383 } 384 } 385 if (ch->hw.pm_write != NULL) { 386 ch->flags |= ATA_PERIODIC_POLL; 387 ch->hw.status = ata_intel_sata_status; 388 ata_sata_scr_write(ch, 0, 389 ATA_SERROR, 0xffffffff); 390 if ((ch->flags & ATA_NO_SLAVE) == 0) { 391 ata_sata_scr_write(ch, 1, 392 ATA_SERROR, 0xffffffff); 393 } 394 } 395 } else 396 ctlr->setmode = ata_intel_new_setmode; 397 if (ctlr->chip->max_dma >= ATA_SA600) 398 ch->flags |= ATA_USE_16BIT; 399 } else if (ctlr->chip->chipid != ATA_ISCH) 400 ch->flags |= ATA_CHECKS_CABLE; 401 return (0); 402} 403 404static void 405ata_intel_reset(device_t dev) 406{ 407 device_t parent = device_get_parent(dev); 408 struct ata_pci_controller *ctlr = device_get_softc(parent); 409 struct ata_channel *ch = device_get_softc(dev); 410 int mask, pshift, timeout, devs; 411 u_char *smap; 412 uint16_t pcs; 413 414 /* In combined mode, skip SATA stuff for PATA channel. */ 415 if ((ch->flags & ATA_SATA) == 0) 416 return (ata_generic_reset(dev)); 417 418 /* Do hard-reset on respective SATA ports. */ 419 smap = ATA_INTEL_SMAP(ctlr, ch); 420 mask = 1 << smap[0]; 421 if ((ch->flags & ATA_NO_SLAVE) == 0) 422 mask |= (1 << smap[1]); 423 pci_write_config(parent, 0x92, 424 pci_read_config(parent, 0x92, 2) & ~mask, 2); 425 DELAY(100); 426 pci_write_config(parent, 0x92, 427 pci_read_config(parent, 0x92, 2) | mask, 2); 428 429 /* Wait up to 1 sec for "connect well". */ 430 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 431 pshift = 8; 432 else 433 pshift = 4; 434 for (timeout = 0; timeout < 100 ; timeout++) { 435 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 436 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 437 break; 438 ata_udelay(10000); 439 } 440 441 if (bootverbose) 442 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 443 /* If any device found, do soft-reset. */ 444 if (ch->hw.pm_read != NULL) { 445 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 446 if ((ch->flags & ATA_NO_SLAVE) == 0) 447 devs |= ata_sata_phy_reset(dev, 1, 2) ? 448 ATA_ATA_SLAVE : 0; 449 } else { 450 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 451 if ((ch->flags & ATA_NO_SLAVE) == 0) 452 devs |= (pcs & (1 << smap[1])) ? 453 ATA_ATA_SLAVE : 0; 454 } 455 if (devs) { 456 ata_generic_reset(dev); 457 /* Reset may give fake slave when only ATAPI master present. */ 458 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 459 } else 460 ch->devices = 0; 461} 462 463static int 464ata_intel_old_setmode(device_t dev, int target, int mode) 465{ 466 device_t parent = device_get_parent(dev); 467 struct ata_pci_controller *ctlr = device_get_softc(parent); 468 469 mode = min(mode, ctlr->chip->max_dma); 470 return (mode); 471} 472 473static int 474ata_intel_new_setmode(device_t dev, int target, int mode) 475{ 476 device_t parent = device_get_parent(dev); 477 struct ata_pci_controller *ctlr = device_get_softc(parent); 478 struct ata_channel *ch = device_get_softc(dev); 479 int devno = (ch->unit << 1) + target; 480 int piomode; 481 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 482 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 483 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 484 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 485 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 486 u_int32_t mask40 = 0, new40 = 0; 487 u_int8_t mask44 = 0, new44 = 0; 488 static const uint8_t timings[] = 489 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 490 static const uint8_t utimings[] = 491 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 492 493 /* In combined mode, skip PATA stuff for SATA channel. */ 494 if (ch->flags & ATA_SATA) 495 return (ata_sata_setmode(dev, target, mode)); 496 497 mode = min(mode, ctlr->chip->max_dma); 498 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 499 !(reg54 & (0x10 << devno))) { 500 ata_print_cable(dev, "controller"); 501 mode = ATA_UDMA2; 502 } 503 /* Enable/disable UDMA and set timings. */ 504 if (mode >= ATA_UDMA0) { 505 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 506 pci_write_config(parent, 0x4a, 507 (reg4a & ~(0x3 << (devno << 2))) | 508 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 509 piomode = ATA_PIO4; 510 } else { 511 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 512 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 513 piomode = mode; 514 } 515 reg54 |= 0x0400; 516 /* Set UDMA reference clock (33/66/133MHz). */ 517 reg54 &= ~(0x1001 << devno); 518 if (mode >= ATA_UDMA5) 519 reg54 |= (0x1000 << devno); 520 else if (mode >= ATA_UDMA3) 521 reg54 |= (0x1 << devno); 522 pci_write_config(parent, 0x54, reg54, 2); 523 /* Allow PIO/WDMA timing controls. */ 524 reg40 &= ~0x00ff00ff; 525 reg40 |= 0x40774077; 526 /* Set PIO/WDMA timings. */ 527 if (target == 0) { 528 mask40 = 0x3300; 529 new40 = timings[ata_mode2idx(piomode)] << 8; 530 } else { 531 mask44 = 0x0f; 532 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 533 (timings[ata_mode2idx(piomode)] & 0x03); 534 } 535 if (ch->unit) { 536 mask40 <<= 16; 537 new40 <<= 16; 538 mask44 <<= 4; 539 new44 <<= 4; 540 } 541 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 542 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 543 return (mode); 544} 545 546static int 547ata_intel_sch_setmode(device_t dev, int target, int mode) 548{ 549 device_t parent = device_get_parent(dev); 550 struct ata_pci_controller *ctlr = device_get_softc(parent); 551 u_int8_t dtim = 0x80 + (target << 2); 552 u_int32_t tim = pci_read_config(parent, dtim, 4); 553 int piomode; 554 555 mode = min(mode, ctlr->chip->max_dma); 556 if (mode >= ATA_UDMA0) { 557 tim |= (0x1 << 31); 558 tim &= ~(0x7 << 16); 559 tim |= ((mode & ATA_MODE_MASK) << 16); 560 piomode = ATA_PIO4; 561 } else if (mode >= ATA_WDMA0) { 562 tim &= ~(0x1 << 31); 563 tim &= ~(0x3 << 8); 564 tim |= ((mode & ATA_MODE_MASK) << 8); 565 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 566 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 567 } else 568 piomode = mode; 569 tim &= ~(0x7); 570 tim |= (piomode & 0x7); 571 pci_write_config(parent, dtim, tim, 4); 572 return (mode); 573} 574 575static int 576ata_intel_sata_getrev(device_t dev, int target) 577{ 578 struct ata_channel *ch = device_get_softc(dev); 579 uint32_t status; 580 581 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 582 return ((status & 0x0f0) >> 4); 583 return (0xff); 584} 585 586static int 587ata_intel_sata_status(device_t dev) 588{ 589 struct ata_channel *ch = device_get_softc(dev); 590 591 ata_sata_phy_check_events(dev, 0); 592 if ((ch->flags & ATA_NO_SLAVE) == 0) 593 ata_sata_phy_check_events(dev, 1); 594 595 return ata_pci_status(dev); 596} 597 598static int 599ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 600{ 601 struct ata_pci_controller *ctlr; 602 struct ata_channel *ch; 603 device_t parent; 604 u_char *smap; 605 int offset; 606 607 parent = device_get_parent(dev); 608 ctlr = device_get_softc(parent); 609 ch = device_get_softc(dev); 610 port = (port == 1) ? 1 : 0; 611 smap = ATA_INTEL_SMAP(ctlr, ch); 612 offset = 0x100 + smap[port] * 0x80; 613 switch (reg) { 614 case ATA_SSTATUS: 615 reg = 0x28; 616 break; 617 case ATA_SCONTROL: 618 reg = 0x2c; 619 break; 620 case ATA_SERROR: 621 reg = 0x30; 622 break; 623 default: 624 return (EINVAL); 625 } 626 *result = ATA_INL(ctlr->r_res2, offset + reg); 627 return (0); 628} 629 630static int 631ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 632{ 633 struct ata_pci_controller *ctlr; 634 struct ata_channel *ch; 635 device_t parent; 636 u_char *smap; 637 638 parent = device_get_parent(dev); 639 ctlr = device_get_softc(parent); 640 ch = device_get_softc(dev); 641 smap = ATA_INTEL_SMAP(ctlr, ch); 642 port = (port == 1) ? 1 : 0; 643 switch (reg) { 644 case ATA_SSTATUS: 645 reg = 0; 646 break; 647 case ATA_SERROR: 648 reg = 1; 649 break; 650 case ATA_SCONTROL: 651 reg = 2; 652 break; 653 default: 654 return (EINVAL); 655 } 656 ATA_INTEL_LOCK(ctlr); 657 pci_write_config(parent, 0xa0, 658 0x50 + smap[port] * 0x10 + reg * 4, 4); 659 *result = pci_read_config(parent, 0xa4, 4); 660 ATA_INTEL_UNLOCK(ctlr); 661 return (0); 662} 663 664static int 665ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 666{ 667 struct ata_pci_controller *ctlr; 668 struct ata_channel *ch; 669 device_t parent; 670 671 parent = device_get_parent(dev); 672 ctlr = device_get_softc(parent); 673 ch = device_get_softc(dev); 674 port = (port == 1) ? 1 : 0; 675 switch (reg) { 676 case ATA_SSTATUS: 677 reg = 0; 678 break; 679 case ATA_SCONTROL: 680 reg = 1; 681 break; 682 case ATA_SERROR: 683 reg = 2; 684 break; 685 default: 686 return (EINVAL); 687 } 688 ATA_INTEL_LOCK(ctlr); 689 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 690 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 691 ATA_INTEL_UNLOCK(ctlr); 692 return (0); 693} 694 695static int 696ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 697{ 698 struct ata_pci_controller *ctlr; 699 struct ata_channel *ch; 700 device_t parent; 701 u_char *smap; 702 int offset; 703 704 parent = device_get_parent(dev); 705 ctlr = device_get_softc(parent); 706 ch = device_get_softc(dev); 707 port = (port == 1) ? 1 : 0; 708 smap = ATA_INTEL_SMAP(ctlr, ch); 709 offset = 0x100 + smap[port] * 0x80; 710 switch (reg) { 711 case ATA_SSTATUS: 712 reg = 0x28; 713 break; 714 case ATA_SCONTROL: 715 reg = 0x2c; 716 break; 717 case ATA_SERROR: 718 reg = 0x30; 719 break; 720 default: 721 return (EINVAL); 722 } 723 ATA_OUTL(ctlr->r_res2, offset + reg, value); 724 return (0); 725} 726 727static int 728ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 729{ 730 struct ata_pci_controller *ctlr; 731 struct ata_channel *ch; 732 device_t parent; 733 u_char *smap; 734 735 parent = device_get_parent(dev); 736 ctlr = device_get_softc(parent); 737 ch = device_get_softc(dev); 738 smap = ATA_INTEL_SMAP(ctlr, ch); 739 port = (port == 1) ? 1 : 0; 740 switch (reg) { 741 case ATA_SSTATUS: 742 reg = 0; 743 break; 744 case ATA_SERROR: 745 reg = 1; 746 break; 747 case ATA_SCONTROL: 748 reg = 2; 749 break; 750 default: 751 return (EINVAL); 752 } 753 ATA_INTEL_LOCK(ctlr); 754 pci_write_config(parent, 0xa0, 755 0x50 + smap[port] * 0x10 + reg * 4, 4); 756 pci_write_config(parent, 0xa4, value, 4); 757 ATA_INTEL_UNLOCK(ctlr); 758 return (0); 759} 760 761static int 762ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 763{ 764 struct ata_pci_controller *ctlr; 765 struct ata_channel *ch; 766 device_t parent; 767 768 parent = device_get_parent(dev); 769 ctlr = device_get_softc(parent); 770 ch = device_get_softc(dev); 771 port = (port == 1) ? 1 : 0; 772 switch (reg) { 773 case ATA_SSTATUS: 774 reg = 0; 775 break; 776 case ATA_SCONTROL: 777 reg = 1; 778 break; 779 case ATA_SERROR: 780 reg = 2; 781 break; 782 default: 783 return (EINVAL); 784 } 785 ATA_INTEL_LOCK(ctlr); 786 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 787 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 788 ATA_INTEL_UNLOCK(ctlr); 789 return (0); 790} 791 792static int 793ata_intel_sata_sidpr_test(device_t dev) 794{ 795 struct ata_channel *ch = device_get_softc(dev); 796 int port; 797 uint32_t val; 798 799 port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1; 800 for (; port >= 0; port--) { 801 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 802 if ((val & ATA_SC_IPM_MASK) == 803 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 804 return (1); 805 val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER; 806 ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val); 807 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 808 if ((val & ATA_SC_IPM_MASK) == 809 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 810 return (1); 811 } 812 if (bootverbose) 813 device_printf(dev, 814 "SControl registers are not functional: %08x\n", val); 815 return (0); 816} 817 818static int 819ata_intel_31244_ch_attach(device_t dev) 820{ 821 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 822 struct ata_channel *ch = device_get_softc(dev); 823 int i; 824 int ch_offset; 825 826 ata_pci_dmainit(dev); 827 828 ch_offset = 0x200 + ch->unit * 0x200; 829 830 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 831 ch->r_io[i].res = ctlr->r_res2; 832 833 /* setup ATA registers */ 834 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 835 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 836 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 837 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 838 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 839 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 840 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 841 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 842 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 843 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 844 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 845 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 846 847 /* setup DMA registers */ 848 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 849 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 850 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 851 852 /* setup SATA registers */ 853 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 854 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 855 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 856 857 ch->flags |= ATA_NO_SLAVE; 858 ch->flags |= ATA_SATA; 859 ata_pci_hw(dev); 860 ch->hw.status = ata_intel_31244_status; 861 ch->hw.tf_write = ata_intel_31244_tf_write; 862 863 /* enable PHY state change interrupt */ 864 ATA_OUTL(ctlr->r_res2, 0x4, 865 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 866 return 0; 867} 868 869static int 870ata_intel_31244_ch_detach(device_t dev) 871{ 872 873 ata_pci_dmafini(dev); 874 return (0); 875} 876 877static int 878ata_intel_31244_status(device_t dev) 879{ 880 /* do we have any PHY events ? */ 881 ata_sata_phy_check_events(dev, -1); 882 883 /* any drive action to take care of ? */ 884 return ata_pci_status(dev); 885} 886 887static void 888ata_intel_31244_tf_write(struct ata_request *request) 889{ 890 struct ata_channel *ch = device_get_softc(request->parent); 891 892 if (request->flags & ATA_R_48BIT) { 893 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 894 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 895 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 896 (request->u.ata.lba & 0x00ff)); 897 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 898 ((request->u.ata.lba >> 8) & 0x00ff)); 899 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 900 ((request->u.ata.lba >> 16) & 0x00ff)); 901 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 902 } 903 else { 904 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 905 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 906 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 907 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 908 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 909 ATA_IDX_OUTB(ch, ATA_DRIVE, 910 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 911 ((request->u.ata.lba >> 24) & 0x0f)); 912 } 913} 914 915static void 916ata_intel_31244_reset(device_t dev) 917{ 918 struct ata_channel *ch = device_get_softc(dev); 919 920 if (ata_sata_phy_reset(dev, -1, 1)) 921 ata_generic_reset(dev); 922 else 923 ch->devices = 0; 924} 925 926ATA_DECLARE_DRIVER(ata_intel); 927