if_alc.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/sys/dev/alc/if_alc.c 330897 2018-03-14 03:19:51Z eadler $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/mbuf.h> 43#include <sys/module.h> 44#include <sys/mutex.h> 45#include <sys/rman.h> 46#include <sys/queue.h> 47#include <sys/socket.h> 48#include <sys/sockio.h> 49#include <sys/sysctl.h> 50#include <sys/taskqueue.h> 51 52#include <net/bpf.h> 53#include <net/if.h> 54#include <net/if_var.h> 55#include <net/if_arp.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_llc.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61#include <net/if_vlan_var.h> 62 63#include <netinet/in.h> 64#include <netinet/in_systm.h> 65#include <netinet/ip.h> 66#include <netinet/tcp.h> 67 68#include <dev/mii/mii.h> 69#include <dev/mii/miivar.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <machine/bus.h> 75#include <machine/in_cksum.h> 76 77#include <dev/alc/if_alcreg.h> 78#include <dev/alc/if_alcvar.h> 79 80/* "device miibus" required. See GENERIC if you get errors here. */ 81#include "miibus_if.h" 82#undef ALC_USE_CUSTOM_CSUM 83 84#ifdef ALC_USE_CUSTOM_CSUM 85#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 86#else 87#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 88#endif 89 90MODULE_DEPEND(alc, pci, 1, 1, 1); 91MODULE_DEPEND(alc, ether, 1, 1, 1); 92MODULE_DEPEND(alc, miibus, 1, 1, 1); 93 94/* Tunables. */ 95static int msi_disable = 0; 96static int msix_disable = 0; 97TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 98TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 99 100/* 101 * Devices supported by this driver. 102 */ 103static struct alc_ident alc_ident_table[] = { 104 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 105 "Atheros AR8131 PCIe Gigabit Ethernet" }, 106 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 107 "Atheros AR8132 PCIe Fast Ethernet" }, 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 109 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 111 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 113 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 115 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 117 "Atheros AR8161 PCIe Gigabit Ethernet" }, 118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 119 "Atheros AR8162 PCIe Fast Ethernet" }, 120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 121 "Atheros AR8171 PCIe Gigabit Ethernet" }, 122 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 123 "Atheros AR8172 PCIe Fast Ethernet" }, 124 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 125 "Killer E2200 Gigabit Ethernet" }, 126 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 127 "Killer E2400 Gigabit Ethernet" }, 128 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 129 "Killer E2500 Gigabit Ethernet" }, 130 { 0, 0, 0, NULL} 131}; 132 133static void alc_aspm(struct alc_softc *, int, int); 134static void alc_aspm_813x(struct alc_softc *, int); 135static void alc_aspm_816x(struct alc_softc *, int); 136static int alc_attach(device_t); 137static int alc_check_boundary(struct alc_softc *); 138static void alc_config_msi(struct alc_softc *); 139static int alc_detach(device_t); 140static void alc_disable_l0s_l1(struct alc_softc *); 141static int alc_dma_alloc(struct alc_softc *); 142static void alc_dma_free(struct alc_softc *); 143static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 144static void alc_dsp_fixup(struct alc_softc *, int); 145static int alc_encap(struct alc_softc *, struct mbuf **); 146static struct alc_ident * 147 alc_find_ident(device_t); 148#ifndef __NO_STRICT_ALIGNMENT 149static struct mbuf * 150 alc_fixup_rx(struct ifnet *, struct mbuf *); 151#endif 152static void alc_get_macaddr(struct alc_softc *); 153static void alc_get_macaddr_813x(struct alc_softc *); 154static void alc_get_macaddr_816x(struct alc_softc *); 155static void alc_get_macaddr_par(struct alc_softc *); 156static void alc_init(void *); 157static void alc_init_cmb(struct alc_softc *); 158static void alc_init_locked(struct alc_softc *); 159static void alc_init_rr_ring(struct alc_softc *); 160static int alc_init_rx_ring(struct alc_softc *); 161static void alc_init_smb(struct alc_softc *); 162static void alc_init_tx_ring(struct alc_softc *); 163static void alc_int_task(void *, int); 164static int alc_intr(void *); 165static int alc_ioctl(struct ifnet *, u_long, caddr_t); 166static void alc_mac_config(struct alc_softc *); 167static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 168static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 169static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 170static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 171static int alc_miibus_readreg(device_t, int, int); 172static void alc_miibus_statchg(device_t); 173static int alc_miibus_writereg(device_t, int, int, int); 174static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 175static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 176static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 177static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 178static int alc_mediachange(struct ifnet *); 179static int alc_mediachange_locked(struct alc_softc *); 180static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 181static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 182static void alc_osc_reset(struct alc_softc *); 183static void alc_phy_down(struct alc_softc *); 184static void alc_phy_reset(struct alc_softc *); 185static void alc_phy_reset_813x(struct alc_softc *); 186static void alc_phy_reset_816x(struct alc_softc *); 187static int alc_probe(device_t); 188static void alc_reset(struct alc_softc *); 189static int alc_resume(device_t); 190static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 191static int alc_rxintr(struct alc_softc *, int); 192static void alc_rxfilter(struct alc_softc *); 193static void alc_rxvlan(struct alc_softc *); 194static void alc_setlinkspeed(struct alc_softc *); 195static void alc_setwol(struct alc_softc *); 196static void alc_setwol_813x(struct alc_softc *); 197static void alc_setwol_816x(struct alc_softc *); 198static int alc_shutdown(device_t); 199static void alc_start(struct ifnet *); 200static void alc_start_locked(struct ifnet *); 201static void alc_start_queue(struct alc_softc *); 202static void alc_stats_clear(struct alc_softc *); 203static void alc_stats_update(struct alc_softc *); 204static void alc_stop(struct alc_softc *); 205static void alc_stop_mac(struct alc_softc *); 206static void alc_stop_queue(struct alc_softc *); 207static int alc_suspend(device_t); 208static void alc_sysctl_node(struct alc_softc *); 209static void alc_tick(void *); 210static void alc_txeof(struct alc_softc *); 211static void alc_watchdog(struct alc_softc *); 212static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 213static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 214static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 215 216static device_method_t alc_methods[] = { 217 /* Device interface. */ 218 DEVMETHOD(device_probe, alc_probe), 219 DEVMETHOD(device_attach, alc_attach), 220 DEVMETHOD(device_detach, alc_detach), 221 DEVMETHOD(device_shutdown, alc_shutdown), 222 DEVMETHOD(device_suspend, alc_suspend), 223 DEVMETHOD(device_resume, alc_resume), 224 225 /* MII interface. */ 226 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 227 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 228 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 229 230 { NULL, NULL } 231}; 232 233static driver_t alc_driver = { 234 "alc", 235 alc_methods, 236 sizeof(struct alc_softc) 237}; 238 239static devclass_t alc_devclass; 240 241DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 242DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 243 244static struct resource_spec alc_res_spec_mem[] = { 245 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 246 { -1, 0, 0 } 247}; 248 249static struct resource_spec alc_irq_spec_legacy[] = { 250 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 251 { -1, 0, 0 } 252}; 253 254static struct resource_spec alc_irq_spec_msi[] = { 255 { SYS_RES_IRQ, 1, RF_ACTIVE }, 256 { -1, 0, 0 } 257}; 258 259static struct resource_spec alc_irq_spec_msix[] = { 260 { SYS_RES_IRQ, 1, RF_ACTIVE }, 261 { -1, 0, 0 } 262}; 263 264static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 265 266static int 267alc_miibus_readreg(device_t dev, int phy, int reg) 268{ 269 struct alc_softc *sc; 270 int v; 271 272 sc = device_get_softc(dev); 273 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 274 v = alc_mii_readreg_816x(sc, phy, reg); 275 else 276 v = alc_mii_readreg_813x(sc, phy, reg); 277 return (v); 278} 279 280static uint32_t 281alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 282{ 283 uint32_t v; 284 int i; 285 286 /* 287 * For AR8132 fast ethernet controller, do not report 1000baseT 288 * capability to mii(4). Even though AR8132 uses the same 289 * model/revision number of F1 gigabit PHY, the PHY has no 290 * ability to establish 1000baseT link. 291 */ 292 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 293 reg == MII_EXTSR) 294 return (0); 295 296 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 297 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 298 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 299 DELAY(5); 300 v = CSR_READ_4(sc, ALC_MDIO); 301 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 302 break; 303 } 304 305 if (i == 0) { 306 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 307 return (0); 308 } 309 310 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 311} 312 313static uint32_t 314alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 315{ 316 uint32_t clk, v; 317 int i; 318 319 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 320 clk = MDIO_CLK_25_128; 321 else 322 clk = MDIO_CLK_25_4; 323 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 324 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 325 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 326 DELAY(5); 327 v = CSR_READ_4(sc, ALC_MDIO); 328 if ((v & MDIO_OP_BUSY) == 0) 329 break; 330 } 331 332 if (i == 0) { 333 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 334 return (0); 335 } 336 337 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 338} 339 340static int 341alc_miibus_writereg(device_t dev, int phy, int reg, int val) 342{ 343 struct alc_softc *sc; 344 int v; 345 346 sc = device_get_softc(dev); 347 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 348 v = alc_mii_writereg_816x(sc, phy, reg, val); 349 else 350 v = alc_mii_writereg_813x(sc, phy, reg, val); 351 return (v); 352} 353 354static uint32_t 355alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 356{ 357 uint32_t v; 358 int i; 359 360 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 361 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 362 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 363 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 364 DELAY(5); 365 v = CSR_READ_4(sc, ALC_MDIO); 366 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 367 break; 368 } 369 370 if (i == 0) 371 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 372 373 return (0); 374} 375 376static uint32_t 377alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 378{ 379 uint32_t clk, v; 380 int i; 381 382 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 383 clk = MDIO_CLK_25_128; 384 else 385 clk = MDIO_CLK_25_4; 386 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 387 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 388 MDIO_SUP_PREAMBLE | clk); 389 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 390 DELAY(5); 391 v = CSR_READ_4(sc, ALC_MDIO); 392 if ((v & MDIO_OP_BUSY) == 0) 393 break; 394 } 395 396 if (i == 0) 397 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 398 399 return (0); 400} 401 402static void 403alc_miibus_statchg(device_t dev) 404{ 405 struct alc_softc *sc; 406 struct mii_data *mii; 407 struct ifnet *ifp; 408 uint32_t reg; 409 410 sc = device_get_softc(dev); 411 412 mii = device_get_softc(sc->alc_miibus); 413 ifp = sc->alc_ifp; 414 if (mii == NULL || ifp == NULL || 415 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 416 return; 417 418 sc->alc_flags &= ~ALC_FLAG_LINK; 419 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 420 (IFM_ACTIVE | IFM_AVALID)) { 421 switch (IFM_SUBTYPE(mii->mii_media_active)) { 422 case IFM_10_T: 423 case IFM_100_TX: 424 sc->alc_flags |= ALC_FLAG_LINK; 425 break; 426 case IFM_1000_T: 427 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 428 sc->alc_flags |= ALC_FLAG_LINK; 429 break; 430 default: 431 break; 432 } 433 } 434 /* Stop Rx/Tx MACs. */ 435 alc_stop_mac(sc); 436 437 /* Program MACs with resolved speed/duplex/flow-control. */ 438 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 439 alc_start_queue(sc); 440 alc_mac_config(sc); 441 /* Re-enable Tx/Rx MACs. */ 442 reg = CSR_READ_4(sc, ALC_MAC_CFG); 443 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 444 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 445 } 446 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 447 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 448} 449 450static uint32_t 451alc_miidbg_readreg(struct alc_softc *sc, int reg) 452{ 453 454 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 455 reg); 456 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 457 ALC_MII_DBG_DATA)); 458} 459 460static uint32_t 461alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 462{ 463 464 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 465 reg); 466 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 467 ALC_MII_DBG_DATA, val)); 468} 469 470static uint32_t 471alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 472{ 473 uint32_t clk, v; 474 int i; 475 476 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 477 EXT_MDIO_DEVADDR(devaddr)); 478 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 479 clk = MDIO_CLK_25_128; 480 else 481 clk = MDIO_CLK_25_4; 482 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 483 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 484 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 485 DELAY(5); 486 v = CSR_READ_4(sc, ALC_MDIO); 487 if ((v & MDIO_OP_BUSY) == 0) 488 break; 489 } 490 491 if (i == 0) { 492 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 493 devaddr, reg); 494 return (0); 495 } 496 497 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 498} 499 500static uint32_t 501alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 502{ 503 uint32_t clk, v; 504 int i; 505 506 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 507 EXT_MDIO_DEVADDR(devaddr)); 508 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 509 clk = MDIO_CLK_25_128; 510 else 511 clk = MDIO_CLK_25_4; 512 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 513 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 514 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 515 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 516 DELAY(5); 517 v = CSR_READ_4(sc, ALC_MDIO); 518 if ((v & MDIO_OP_BUSY) == 0) 519 break; 520 } 521 522 if (i == 0) 523 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 524 devaddr, reg); 525 526 return (0); 527} 528 529static void 530alc_dsp_fixup(struct alc_softc *sc, int media) 531{ 532 uint16_t agc, len, val; 533 534 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 535 return; 536 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 537 return; 538 539 /* 540 * Vendor PHY magic. 541 * 1000BT/AZ, wrong cable length 542 */ 543 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 544 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 545 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 546 EXT_CLDCTL6_CAB_LEN_MASK; 547 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 548 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 549 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 550 agc > DBG_AGC_LONG1G_LIMT) || 551 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 552 agc > DBG_AGC_LONG1G_LIMT)) { 553 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 554 DBG_AZ_ANADECT_LONG); 555 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 556 MII_EXT_ANEG_AFE); 557 val |= ANEG_AFEE_10BT_100M_TH; 558 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 559 val); 560 } else { 561 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 562 DBG_AZ_ANADECT_DEFAULT); 563 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 564 MII_EXT_ANEG_AFE); 565 val &= ~ANEG_AFEE_10BT_100M_TH; 566 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 567 val); 568 } 569 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 570 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 571 if (media == IFM_1000_T) { 572 /* 573 * Giga link threshold, raise the tolerance of 574 * noise 50%. 575 */ 576 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 577 val &= ~DBG_MSE20DB_TH_MASK; 578 val |= (DBG_MSE20DB_TH_HI << 579 DBG_MSE20DB_TH_SHIFT); 580 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 581 } else if (media == IFM_100_TX) 582 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 583 DBG_MSE16DB_UP); 584 } 585 } else { 586 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 587 val &= ~ANEG_AFEE_10BT_100M_TH; 588 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 589 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 590 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 591 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 592 DBG_MSE16DB_DOWN); 593 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 594 val &= ~DBG_MSE20DB_TH_MASK; 595 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 596 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 597 } 598 } 599} 600 601static void 602alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 603{ 604 struct alc_softc *sc; 605 struct mii_data *mii; 606 607 sc = ifp->if_softc; 608 ALC_LOCK(sc); 609 if ((ifp->if_flags & IFF_UP) == 0) { 610 ALC_UNLOCK(sc); 611 return; 612 } 613 mii = device_get_softc(sc->alc_miibus); 614 615 mii_pollstat(mii); 616 ifmr->ifm_status = mii->mii_media_status; 617 ifmr->ifm_active = mii->mii_media_active; 618 ALC_UNLOCK(sc); 619} 620 621static int 622alc_mediachange(struct ifnet *ifp) 623{ 624 struct alc_softc *sc; 625 int error; 626 627 sc = ifp->if_softc; 628 ALC_LOCK(sc); 629 error = alc_mediachange_locked(sc); 630 ALC_UNLOCK(sc); 631 632 return (error); 633} 634 635static int 636alc_mediachange_locked(struct alc_softc *sc) 637{ 638 struct mii_data *mii; 639 struct mii_softc *miisc; 640 int error; 641 642 ALC_LOCK_ASSERT(sc); 643 644 mii = device_get_softc(sc->alc_miibus); 645 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 646 PHY_RESET(miisc); 647 error = mii_mediachg(mii); 648 649 return (error); 650} 651 652static struct alc_ident * 653alc_find_ident(device_t dev) 654{ 655 struct alc_ident *ident; 656 uint16_t vendor, devid; 657 658 vendor = pci_get_vendor(dev); 659 devid = pci_get_device(dev); 660 for (ident = alc_ident_table; ident->name != NULL; ident++) { 661 if (vendor == ident->vendorid && devid == ident->deviceid) 662 return (ident); 663 } 664 665 return (NULL); 666} 667 668static int 669alc_probe(device_t dev) 670{ 671 struct alc_ident *ident; 672 673 ident = alc_find_ident(dev); 674 if (ident != NULL) { 675 device_set_desc(dev, ident->name); 676 return (BUS_PROBE_DEFAULT); 677 } 678 679 return (ENXIO); 680} 681 682static void 683alc_get_macaddr(struct alc_softc *sc) 684{ 685 686 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 687 alc_get_macaddr_816x(sc); 688 else 689 alc_get_macaddr_813x(sc); 690} 691 692static void 693alc_get_macaddr_813x(struct alc_softc *sc) 694{ 695 uint32_t opt; 696 uint16_t val; 697 int eeprom, i; 698 699 eeprom = 0; 700 opt = CSR_READ_4(sc, ALC_OPT_CFG); 701 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 702 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 703 /* 704 * EEPROM found, let TWSI reload EEPROM configuration. 705 * This will set ethernet address of controller. 706 */ 707 eeprom++; 708 switch (sc->alc_ident->deviceid) { 709 case DEVICEID_ATHEROS_AR8131: 710 case DEVICEID_ATHEROS_AR8132: 711 if ((opt & OPT_CFG_CLK_ENB) == 0) { 712 opt |= OPT_CFG_CLK_ENB; 713 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 714 CSR_READ_4(sc, ALC_OPT_CFG); 715 DELAY(1000); 716 } 717 break; 718 case DEVICEID_ATHEROS_AR8151: 719 case DEVICEID_ATHEROS_AR8151_V2: 720 case DEVICEID_ATHEROS_AR8152_B: 721 case DEVICEID_ATHEROS_AR8152_B2: 722 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 723 ALC_MII_DBG_ADDR, 0x00); 724 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 725 ALC_MII_DBG_DATA); 726 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 727 ALC_MII_DBG_DATA, val & 0xFF7F); 728 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 729 ALC_MII_DBG_ADDR, 0x3B); 730 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 731 ALC_MII_DBG_DATA); 732 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 733 ALC_MII_DBG_DATA, val | 0x0008); 734 DELAY(20); 735 break; 736 } 737 738 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 739 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 740 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 741 CSR_READ_4(sc, ALC_WOL_CFG); 742 743 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 744 TWSI_CFG_SW_LD_START); 745 for (i = 100; i > 0; i--) { 746 DELAY(1000); 747 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 748 TWSI_CFG_SW_LD_START) == 0) 749 break; 750 } 751 if (i == 0) 752 device_printf(sc->alc_dev, 753 "reloading EEPROM timeout!\n"); 754 } else { 755 if (bootverbose) 756 device_printf(sc->alc_dev, "EEPROM not found!\n"); 757 } 758 if (eeprom != 0) { 759 switch (sc->alc_ident->deviceid) { 760 case DEVICEID_ATHEROS_AR8131: 761 case DEVICEID_ATHEROS_AR8132: 762 if ((opt & OPT_CFG_CLK_ENB) != 0) { 763 opt &= ~OPT_CFG_CLK_ENB; 764 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 765 CSR_READ_4(sc, ALC_OPT_CFG); 766 DELAY(1000); 767 } 768 break; 769 case DEVICEID_ATHEROS_AR8151: 770 case DEVICEID_ATHEROS_AR8151_V2: 771 case DEVICEID_ATHEROS_AR8152_B: 772 case DEVICEID_ATHEROS_AR8152_B2: 773 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 774 ALC_MII_DBG_ADDR, 0x00); 775 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 776 ALC_MII_DBG_DATA); 777 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 778 ALC_MII_DBG_DATA, val | 0x0080); 779 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_ADDR, 0x3B); 781 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_DATA); 783 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 784 ALC_MII_DBG_DATA, val & 0xFFF7); 785 DELAY(20); 786 break; 787 } 788 } 789 790 alc_get_macaddr_par(sc); 791} 792 793static void 794alc_get_macaddr_816x(struct alc_softc *sc) 795{ 796 uint32_t reg; 797 int i, reloaded; 798 799 reloaded = 0; 800 /* Try to reload station address via TWSI. */ 801 for (i = 100; i > 0; i--) { 802 reg = CSR_READ_4(sc, ALC_SLD); 803 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 804 break; 805 DELAY(1000); 806 } 807 if (i != 0) { 808 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 809 for (i = 100; i > 0; i--) { 810 DELAY(1000); 811 reg = CSR_READ_4(sc, ALC_SLD); 812 if ((reg & SLD_START) == 0) 813 break; 814 } 815 if (i != 0) 816 reloaded++; 817 else if (bootverbose) 818 device_printf(sc->alc_dev, 819 "reloading station address via TWSI timed out!\n"); 820 } 821 822 /* Try to reload station address from EEPROM or FLASH. */ 823 if (reloaded == 0) { 824 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 825 if ((reg & (EEPROM_LD_EEPROM_EXIST | 826 EEPROM_LD_FLASH_EXIST)) != 0) { 827 for (i = 100; i > 0; i--) { 828 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 829 if ((reg & (EEPROM_LD_PROGRESS | 830 EEPROM_LD_START)) == 0) 831 break; 832 DELAY(1000); 833 } 834 if (i != 0) { 835 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 836 EEPROM_LD_START); 837 for (i = 100; i > 0; i--) { 838 DELAY(1000); 839 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 840 if ((reg & EEPROM_LD_START) == 0) 841 break; 842 } 843 } else if (bootverbose) 844 device_printf(sc->alc_dev, 845 "reloading EEPROM/FLASH timed out!\n"); 846 } 847 } 848 849 alc_get_macaddr_par(sc); 850} 851 852static void 853alc_get_macaddr_par(struct alc_softc *sc) 854{ 855 uint32_t ea[2]; 856 857 ea[0] = CSR_READ_4(sc, ALC_PAR0); 858 ea[1] = CSR_READ_4(sc, ALC_PAR1); 859 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 860 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 861 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 862 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 863 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 864 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 865} 866 867static void 868alc_disable_l0s_l1(struct alc_softc *sc) 869{ 870 uint32_t pmcfg; 871 872 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 873 /* Another magic from vendor. */ 874 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 875 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 876 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 877 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 878 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 879 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 880 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 881 } 882} 883 884static void 885alc_phy_reset(struct alc_softc *sc) 886{ 887 888 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 889 alc_phy_reset_816x(sc); 890 else 891 alc_phy_reset_813x(sc); 892} 893 894static void 895alc_phy_reset_813x(struct alc_softc *sc) 896{ 897 uint16_t data; 898 899 /* Reset magic from Linux. */ 900 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 901 CSR_READ_2(sc, ALC_GPHY_CFG); 902 DELAY(10 * 1000); 903 904 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 905 GPHY_CFG_SEL_ANA_RESET); 906 CSR_READ_2(sc, ALC_GPHY_CFG); 907 DELAY(10 * 1000); 908 909 /* DSP fixup, Vendor magic. */ 910 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 911 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 912 ALC_MII_DBG_ADDR, 0x000A); 913 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 914 ALC_MII_DBG_DATA); 915 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 916 ALC_MII_DBG_DATA, data & 0xDFFF); 917 } 918 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 919 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 920 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 921 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 922 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 923 ALC_MII_DBG_ADDR, 0x003B); 924 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 925 ALC_MII_DBG_DATA); 926 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 927 ALC_MII_DBG_DATA, data & 0xFFF7); 928 DELAY(20 * 1000); 929 } 930 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 931 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 932 ALC_MII_DBG_ADDR, 0x0029); 933 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 934 ALC_MII_DBG_DATA, 0x929D); 935 } 936 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 937 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 938 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 939 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 940 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 941 ALC_MII_DBG_ADDR, 0x0029); 942 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 943 ALC_MII_DBG_DATA, 0xB6DD); 944 } 945 946 /* Load DSP codes, vendor magic. */ 947 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 948 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 949 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 950 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 951 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 952 ALC_MII_DBG_DATA, data); 953 954 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 955 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 956 ANA_SERDES_EN_LCKDT; 957 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 958 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 959 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 960 ALC_MII_DBG_DATA, data); 961 962 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 963 ANA_LONG_CABLE_TH_100_MASK) | 964 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 965 ANA_SHORT_CABLE_TH_100_SHIFT) | 966 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 967 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 968 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 969 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 970 ALC_MII_DBG_DATA, data); 971 972 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 973 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 974 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 975 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 976 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 977 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 978 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 979 ALC_MII_DBG_DATA, data); 980 981 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 982 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 983 ANA_OEN_125M; 984 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 985 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 986 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 987 ALC_MII_DBG_DATA, data); 988 DELAY(1000); 989 990 /* Disable hibernation. */ 991 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 992 0x0029); 993 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 994 ALC_MII_DBG_DATA); 995 data &= ~0x8000; 996 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 997 data); 998 999 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1000 0x000B); 1001 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1002 ALC_MII_DBG_DATA); 1003 data &= ~0x8000; 1004 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1005 data); 1006} 1007 1008static void 1009alc_phy_reset_816x(struct alc_softc *sc) 1010{ 1011 uint32_t val; 1012 1013 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1014 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1015 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1016 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1017 val |= GPHY_CFG_SEL_ANA_RESET; 1018#ifdef notyet 1019 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1020#else 1021 /* Disable PHY hibernation. */ 1022 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1023#endif 1024 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1025 DELAY(10); 1026 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1027 DELAY(800); 1028 1029 /* Vendor PHY magic. */ 1030#ifdef notyet 1031 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1032 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1033 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1034 EXT_VDRVBIAS_DEFAULT); 1035#else 1036 /* Disable PHY hibernation. */ 1037 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1038 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1039 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1040 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1041 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1042#endif 1043 1044 /* XXX Disable EEE. */ 1045 val = CSR_READ_4(sc, ALC_LPI_CTL); 1046 val &= ~LPI_CTL_ENB; 1047 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1048 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1049 1050 /* PHY power saving. */ 1051 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1052 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1053 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1054 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1055 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1056 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1057 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1058 1059 /* RTL8139C, 120m issue. */ 1060 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1061 ANEG_NLP78_120M_DEFAULT); 1062 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1063 ANEG_S3DIG10_DEFAULT); 1064 1065 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1066 /* Turn off half amplitude. */ 1067 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1068 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1069 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1070 /* Turn off Green feature. */ 1071 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1072 val |= DBG_GREENCFG2_BP_GREEN; 1073 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1074 /* Turn off half bias. */ 1075 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1076 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1077 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1078 } 1079} 1080 1081static void 1082alc_phy_down(struct alc_softc *sc) 1083{ 1084 uint32_t gphy; 1085 1086 switch (sc->alc_ident->deviceid) { 1087 case DEVICEID_ATHEROS_AR8161: 1088 case DEVICEID_ATHEROS_E2200: 1089 case DEVICEID_ATHEROS_E2400: 1090 case DEVICEID_ATHEROS_E2500: 1091 case DEVICEID_ATHEROS_AR8162: 1092 case DEVICEID_ATHEROS_AR8171: 1093 case DEVICEID_ATHEROS_AR8172: 1094 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1095 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1096 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1097 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1098 GPHY_CFG_SEL_ANA_RESET; 1099 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1100 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1101 break; 1102 case DEVICEID_ATHEROS_AR8151: 1103 case DEVICEID_ATHEROS_AR8151_V2: 1104 case DEVICEID_ATHEROS_AR8152_B: 1105 case DEVICEID_ATHEROS_AR8152_B2: 1106 /* 1107 * GPHY power down caused more problems on AR8151 v2.0. 1108 * When driver is reloaded after GPHY power down, 1109 * accesses to PHY/MAC registers hung the system. Only 1110 * cold boot recovered from it. I'm not sure whether 1111 * AR8151 v1.0 also requires this one though. I don't 1112 * have AR8151 v1.0 controller in hand. 1113 * The only option left is to isolate the PHY and 1114 * initiates power down the PHY which in turn saves 1115 * more power when driver is unloaded. 1116 */ 1117 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1118 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1119 break; 1120 default: 1121 /* Force PHY down. */ 1122 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1123 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1124 GPHY_CFG_PWDOWN_HW); 1125 DELAY(1000); 1126 break; 1127 } 1128} 1129 1130static void 1131alc_aspm(struct alc_softc *sc, int init, int media) 1132{ 1133 1134 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1135 alc_aspm_816x(sc, init); 1136 else 1137 alc_aspm_813x(sc, media); 1138} 1139 1140static void 1141alc_aspm_813x(struct alc_softc *sc, int media) 1142{ 1143 uint32_t pmcfg; 1144 uint16_t linkcfg; 1145 1146 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1147 return; 1148 1149 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1150 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1151 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1152 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1153 PCIER_LINK_CTL); 1154 else 1155 linkcfg = 0; 1156 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1157 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1158 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1159 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1160 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1161 1162 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1163 /* Disable extended sync except AR8152 B v1.0 */ 1164 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1165 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1166 sc->alc_rev == ATHEROS_AR8152_B_V10) 1167 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1168 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1169 linkcfg); 1170 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1171 PM_CFG_HOTRST); 1172 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1173 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1174 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1175 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1176 PM_CFG_PM_REQ_TIMER_SHIFT); 1177 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1178 } 1179 1180 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1181 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1182 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1183 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1184 pmcfg |= PM_CFG_ASPM_L1_ENB; 1185 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1186 if (sc->alc_ident->deviceid == 1187 DEVICEID_ATHEROS_AR8152_B) 1188 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1189 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1190 PM_CFG_SERDES_PLL_L1_ENB | 1191 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1192 pmcfg |= PM_CFG_CLK_SWH_L1; 1193 if (media == IFM_100_TX || media == IFM_1000_T) { 1194 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1195 switch (sc->alc_ident->deviceid) { 1196 case DEVICEID_ATHEROS_AR8152_B: 1197 pmcfg |= (7 << 1198 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1199 break; 1200 case DEVICEID_ATHEROS_AR8152_B2: 1201 case DEVICEID_ATHEROS_AR8151_V2: 1202 pmcfg |= (4 << 1203 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1204 break; 1205 default: 1206 pmcfg |= (15 << 1207 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1208 break; 1209 } 1210 } 1211 } else { 1212 pmcfg |= PM_CFG_SERDES_L1_ENB | 1213 PM_CFG_SERDES_PLL_L1_ENB | 1214 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1215 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1216 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1217 } 1218 } else { 1219 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1220 PM_CFG_SERDES_PLL_L1_ENB); 1221 pmcfg |= PM_CFG_CLK_SWH_L1; 1222 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1223 pmcfg |= PM_CFG_ASPM_L1_ENB; 1224 } 1225 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1226} 1227 1228static void 1229alc_aspm_816x(struct alc_softc *sc, int init) 1230{ 1231 uint32_t pmcfg; 1232 1233 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1234 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1235 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1236 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1237 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1238 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1239 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1240 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1241 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1242 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1243 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1244 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1245 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1246 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1247 (sc->alc_rev & 0x01) != 0) 1248 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1249 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1250 /* Link up, enable both L0s, L1s. */ 1251 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1252 PM_CFG_MAC_ASPM_CHK; 1253 } else { 1254 if (init != 0) 1255 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1256 PM_CFG_MAC_ASPM_CHK; 1257 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1258 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1259 } 1260 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1261} 1262 1263static void 1264alc_init_pcie(struct alc_softc *sc) 1265{ 1266 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1267 uint32_t cap, ctl, val; 1268 int state; 1269 1270 /* Clear data link and flow-control protocol error. */ 1271 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1272 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1273 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1274 1275 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1276 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1277 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1278 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1279 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1280 PCIE_PHYMISC_FORCE_RCV_DET); 1281 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1282 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1283 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1284 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1285 PCIE_PHYMISC2_SERDES_TH_MASK); 1286 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1287 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1288 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1289 } 1290 /* Disable ASPM L0S and L1. */ 1291 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1292 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1293 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1294 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1295 sc->alc_rcb = DMA_CFG_RCB_128; 1296 if (bootverbose) 1297 device_printf(sc->alc_dev, "RCB %u bytes\n", 1298 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1299 state = ctl & PCIEM_LINK_CTL_ASPMC; 1300 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1301 sc->alc_flags |= ALC_FLAG_L0S; 1302 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1303 sc->alc_flags |= ALC_FLAG_L1S; 1304 if (bootverbose) 1305 device_printf(sc->alc_dev, "ASPM %s %s\n", 1306 aspm_state[state], 1307 state == 0 ? "disabled" : "enabled"); 1308 alc_disable_l0s_l1(sc); 1309 } else { 1310 if (bootverbose) 1311 device_printf(sc->alc_dev, 1312 "no ASPM support\n"); 1313 } 1314 } else { 1315 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1316 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1317 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1318 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1319 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1320 (sc->alc_rev & 0x01) != 0) { 1321 if ((val & MASTER_WAKEN_25M) == 0 || 1322 (val & MASTER_CLK_SEL_DIS) == 0) { 1323 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1324 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1325 } 1326 } else { 1327 if ((val & MASTER_WAKEN_25M) == 0 || 1328 (val & MASTER_CLK_SEL_DIS) != 0) { 1329 val |= MASTER_WAKEN_25M; 1330 val &= ~MASTER_CLK_SEL_DIS; 1331 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1332 } 1333 } 1334 } 1335 alc_aspm(sc, 1, IFM_UNKNOWN); 1336} 1337 1338static void 1339alc_config_msi(struct alc_softc *sc) 1340{ 1341 uint32_t ctl, mod; 1342 1343 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1344 /* 1345 * It seems interrupt moderation is controlled by 1346 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1347 * Driver uses RX interrupt moderation parameter to 1348 * program ALC_MSI_RETRANS_TIMER register. 1349 */ 1350 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1351 ctl &= ~MSI_RETRANS_TIMER_MASK; 1352 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1353 mod = ALC_USECS(sc->alc_int_rx_mod); 1354 if (mod == 0) 1355 mod = 1; 1356 ctl |= mod; 1357 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1358 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1359 MSI_RETRANS_MASK_SEL_STD); 1360 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1361 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1362 MSI_RETRANS_MASK_SEL_LINE); 1363 else 1364 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1365 } 1366} 1367 1368static int 1369alc_attach(device_t dev) 1370{ 1371 struct alc_softc *sc; 1372 struct ifnet *ifp; 1373 int base, error, i, msic, msixc; 1374 uint16_t burst; 1375 1376 error = 0; 1377 sc = device_get_softc(dev); 1378 sc->alc_dev = dev; 1379 sc->alc_rev = pci_get_revid(dev); 1380 1381 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1382 MTX_DEF); 1383 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1384 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1385 sc->alc_ident = alc_find_ident(dev); 1386 1387 /* Map the device. */ 1388 pci_enable_busmaster(dev); 1389 sc->alc_res_spec = alc_res_spec_mem; 1390 sc->alc_irq_spec = alc_irq_spec_legacy; 1391 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1392 if (error != 0) { 1393 device_printf(dev, "cannot allocate memory resources.\n"); 1394 goto fail; 1395 } 1396 1397 /* Set PHY address. */ 1398 sc->alc_phyaddr = ALC_PHY_ADDR; 1399 1400 /* 1401 * One odd thing is AR8132 uses the same PHY hardware(F1 1402 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1403 * the PHY supports 1000Mbps but that's not true. The PHY 1404 * used in AR8132 can't establish gigabit link even if it 1405 * shows the same PHY model/revision number of AR8131. 1406 */ 1407 switch (sc->alc_ident->deviceid) { 1408 case DEVICEID_ATHEROS_E2200: 1409 case DEVICEID_ATHEROS_E2400: 1410 case DEVICEID_ATHEROS_E2500: 1411 sc->alc_flags |= ALC_FLAG_E2X00; 1412 /* FALLTHROUGH */ 1413 case DEVICEID_ATHEROS_AR8161: 1414 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1415 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1416 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1417 /* FALLTHROUGH */ 1418 case DEVICEID_ATHEROS_AR8171: 1419 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1420 break; 1421 case DEVICEID_ATHEROS_AR8162: 1422 case DEVICEID_ATHEROS_AR8172: 1423 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1424 break; 1425 case DEVICEID_ATHEROS_AR8152_B: 1426 case DEVICEID_ATHEROS_AR8152_B2: 1427 sc->alc_flags |= ALC_FLAG_APS; 1428 /* FALLTHROUGH */ 1429 case DEVICEID_ATHEROS_AR8132: 1430 sc->alc_flags |= ALC_FLAG_FASTETHER; 1431 break; 1432 case DEVICEID_ATHEROS_AR8151: 1433 case DEVICEID_ATHEROS_AR8151_V2: 1434 sc->alc_flags |= ALC_FLAG_APS; 1435 /* FALLTHROUGH */ 1436 default: 1437 break; 1438 } 1439 sc->alc_flags |= ALC_FLAG_JUMBO; 1440 1441 /* 1442 * It seems that AR813x/AR815x has silicon bug for SMB. In 1443 * addition, Atheros said that enabling SMB wouldn't improve 1444 * performance. However I think it's bad to access lots of 1445 * registers to extract MAC statistics. 1446 */ 1447 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1448 /* 1449 * Don't use Tx CMB. It is known to have silicon bug. 1450 */ 1451 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1452 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1453 MASTER_CHIP_REV_SHIFT; 1454 if (bootverbose) { 1455 device_printf(dev, "PCI device revision : 0x%04x\n", 1456 sc->alc_rev); 1457 device_printf(dev, "Chip id/revision : 0x%04x\n", 1458 sc->alc_chip_rev); 1459 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1460 device_printf(dev, "AR816x revision : 0x%x\n", 1461 AR816X_REV(sc->alc_rev)); 1462 } 1463 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1464 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1465 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1466 1467 /* Initialize DMA parameters. */ 1468 sc->alc_dma_rd_burst = 0; 1469 sc->alc_dma_wr_burst = 0; 1470 sc->alc_rcb = DMA_CFG_RCB_64; 1471 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1472 sc->alc_flags |= ALC_FLAG_PCIE; 1473 sc->alc_expcap = base; 1474 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1475 sc->alc_dma_rd_burst = 1476 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1477 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1478 if (bootverbose) { 1479 device_printf(dev, "Read request size : %u bytes.\n", 1480 alc_dma_burst[sc->alc_dma_rd_burst]); 1481 device_printf(dev, "TLP payload size : %u bytes.\n", 1482 alc_dma_burst[sc->alc_dma_wr_burst]); 1483 } 1484 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1485 sc->alc_dma_rd_burst = 3; 1486 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1487 sc->alc_dma_wr_burst = 3; 1488 /* 1489 * Force maximum payload size to 128 bytes for 1490 * E2200/E2400/E2500. 1491 * Otherwise it triggers DMA write error. 1492 */ 1493 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0) 1494 sc->alc_dma_wr_burst = 0; 1495 alc_init_pcie(sc); 1496 } 1497 1498 /* Reset PHY. */ 1499 alc_phy_reset(sc); 1500 1501 /* Reset the ethernet controller. */ 1502 alc_stop_mac(sc); 1503 alc_reset(sc); 1504 1505 /* Allocate IRQ resources. */ 1506 msixc = pci_msix_count(dev); 1507 msic = pci_msi_count(dev); 1508 if (bootverbose) { 1509 device_printf(dev, "MSIX count : %d\n", msixc); 1510 device_printf(dev, "MSI count : %d\n", msic); 1511 } 1512 if (msixc > 1) 1513 msixc = 1; 1514 if (msic > 1) 1515 msic = 1; 1516 /* 1517 * Prefer MSIX over MSI. 1518 * AR816x controller has a silicon bug that MSI interrupt 1519 * does not assert if PCIM_CMD_INTxDIS bit of command 1520 * register is set. pci(4) was taught to handle that case. 1521 */ 1522 if (msix_disable == 0 || msi_disable == 0) { 1523 if (msix_disable == 0 && msixc > 0 && 1524 pci_alloc_msix(dev, &msixc) == 0) { 1525 if (msic == 1) { 1526 device_printf(dev, 1527 "Using %d MSIX message(s).\n", msixc); 1528 sc->alc_flags |= ALC_FLAG_MSIX; 1529 sc->alc_irq_spec = alc_irq_spec_msix; 1530 } else 1531 pci_release_msi(dev); 1532 } 1533 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1534 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1535 if (msic == 1) { 1536 device_printf(dev, 1537 "Using %d MSI message(s).\n", msic); 1538 sc->alc_flags |= ALC_FLAG_MSI; 1539 sc->alc_irq_spec = alc_irq_spec_msi; 1540 } else 1541 pci_release_msi(dev); 1542 } 1543 } 1544 1545 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1546 if (error != 0) { 1547 device_printf(dev, "cannot allocate IRQ resources.\n"); 1548 goto fail; 1549 } 1550 1551 /* Create device sysctl node. */ 1552 alc_sysctl_node(sc); 1553 1554 if ((error = alc_dma_alloc(sc)) != 0) 1555 goto fail; 1556 1557 /* Load station address. */ 1558 alc_get_macaddr(sc); 1559 1560 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1561 if (ifp == NULL) { 1562 device_printf(dev, "cannot allocate ifnet structure.\n"); 1563 error = ENXIO; 1564 goto fail; 1565 } 1566 1567 ifp->if_softc = sc; 1568 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1569 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1570 ifp->if_ioctl = alc_ioctl; 1571 ifp->if_start = alc_start; 1572 ifp->if_init = alc_init; 1573 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 1574 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1575 IFQ_SET_READY(&ifp->if_snd); 1576 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1577 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 1578 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1579 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1580 sc->alc_flags |= ALC_FLAG_PM; 1581 sc->alc_pmcap = base; 1582 } 1583 ifp->if_capenable = ifp->if_capabilities; 1584 1585 /* Set up MII bus. */ 1586 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1587 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1588 MIIF_DOPAUSE); 1589 if (error != 0) { 1590 device_printf(dev, "attaching PHYs failed\n"); 1591 goto fail; 1592 } 1593 1594 ether_ifattach(ifp, sc->alc_eaddr); 1595 1596 /* VLAN capability setup. */ 1597 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1598 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1599 ifp->if_capenable = ifp->if_capabilities; 1600 /* 1601 * XXX 1602 * It seems enabling Tx checksum offloading makes more trouble. 1603 * Sometimes the controller does not receive any frames when 1604 * Tx checksum offloading is enabled. I'm not sure whether this 1605 * is a bug in Tx checksum offloading logic or I got broken 1606 * sample boards. To safety, don't enable Tx checksum offloading 1607 * by default but give chance to users to toggle it if they know 1608 * their controllers work without problems. 1609 * Fortunately, Tx checksum offloading for AR816x family 1610 * seems to work. 1611 */ 1612 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1613 ifp->if_capenable &= ~IFCAP_TXCSUM; 1614 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1615 } 1616 1617 /* Tell the upper layer(s) we support long frames. */ 1618 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1619 1620 /* Create local taskq. */ 1621 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1622 taskqueue_thread_enqueue, &sc->alc_tq); 1623 if (sc->alc_tq == NULL) { 1624 device_printf(dev, "could not create taskqueue.\n"); 1625 ether_ifdetach(ifp); 1626 error = ENXIO; 1627 goto fail; 1628 } 1629 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1630 device_get_nameunit(sc->alc_dev)); 1631 1632 alc_config_msi(sc); 1633 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1634 msic = ALC_MSIX_MESSAGES; 1635 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1636 msic = ALC_MSI_MESSAGES; 1637 else 1638 msic = 1; 1639 for (i = 0; i < msic; i++) { 1640 error = bus_setup_intr(dev, sc->alc_irq[i], 1641 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1642 &sc->alc_intrhand[i]); 1643 if (error != 0) 1644 break; 1645 } 1646 if (error != 0) { 1647 device_printf(dev, "could not set up interrupt handler.\n"); 1648 taskqueue_free(sc->alc_tq); 1649 sc->alc_tq = NULL; 1650 ether_ifdetach(ifp); 1651 goto fail; 1652 } 1653 1654fail: 1655 if (error != 0) 1656 alc_detach(dev); 1657 1658 return (error); 1659} 1660 1661static int 1662alc_detach(device_t dev) 1663{ 1664 struct alc_softc *sc; 1665 struct ifnet *ifp; 1666 int i, msic; 1667 1668 sc = device_get_softc(dev); 1669 1670 ifp = sc->alc_ifp; 1671 if (device_is_attached(dev)) { 1672 ether_ifdetach(ifp); 1673 ALC_LOCK(sc); 1674 alc_stop(sc); 1675 ALC_UNLOCK(sc); 1676 callout_drain(&sc->alc_tick_ch); 1677 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1678 } 1679 1680 if (sc->alc_tq != NULL) { 1681 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1682 taskqueue_free(sc->alc_tq); 1683 sc->alc_tq = NULL; 1684 } 1685 1686 if (sc->alc_miibus != NULL) { 1687 device_delete_child(dev, sc->alc_miibus); 1688 sc->alc_miibus = NULL; 1689 } 1690 bus_generic_detach(dev); 1691 alc_dma_free(sc); 1692 1693 if (ifp != NULL) { 1694 if_free(ifp); 1695 sc->alc_ifp = NULL; 1696 } 1697 1698 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1699 msic = ALC_MSIX_MESSAGES; 1700 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1701 msic = ALC_MSI_MESSAGES; 1702 else 1703 msic = 1; 1704 for (i = 0; i < msic; i++) { 1705 if (sc->alc_intrhand[i] != NULL) { 1706 bus_teardown_intr(dev, sc->alc_irq[i], 1707 sc->alc_intrhand[i]); 1708 sc->alc_intrhand[i] = NULL; 1709 } 1710 } 1711 if (sc->alc_res[0] != NULL) 1712 alc_phy_down(sc); 1713 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1714 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1715 pci_release_msi(dev); 1716 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1717 mtx_destroy(&sc->alc_mtx); 1718 1719 return (0); 1720} 1721 1722#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1723 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1724#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1725 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1726 1727static void 1728alc_sysctl_node(struct alc_softc *sc) 1729{ 1730 struct sysctl_ctx_list *ctx; 1731 struct sysctl_oid_list *child, *parent; 1732 struct sysctl_oid *tree; 1733 struct alc_hw_stats *stats; 1734 int error; 1735 1736 stats = &sc->alc_stats; 1737 ctx = device_get_sysctl_ctx(sc->alc_dev); 1738 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1739 1740 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1741 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1742 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1743 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1744 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1745 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1746 /* Pull in device tunables. */ 1747 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1748 error = resource_int_value(device_get_name(sc->alc_dev), 1749 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1750 if (error == 0) { 1751 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1752 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1753 device_printf(sc->alc_dev, "int_rx_mod value out of " 1754 "range; using default: %d\n", 1755 ALC_IM_RX_TIMER_DEFAULT); 1756 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1757 } 1758 } 1759 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1760 error = resource_int_value(device_get_name(sc->alc_dev), 1761 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1762 if (error == 0) { 1763 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1764 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1765 device_printf(sc->alc_dev, "int_tx_mod value out of " 1766 "range; using default: %d\n", 1767 ALC_IM_TX_TIMER_DEFAULT); 1768 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1769 } 1770 } 1771 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1772 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1773 sysctl_hw_alc_proc_limit, "I", 1774 "max number of Rx events to process"); 1775 /* Pull in device tunables. */ 1776 sc->alc_process_limit = ALC_PROC_DEFAULT; 1777 error = resource_int_value(device_get_name(sc->alc_dev), 1778 device_get_unit(sc->alc_dev), "process_limit", 1779 &sc->alc_process_limit); 1780 if (error == 0) { 1781 if (sc->alc_process_limit < ALC_PROC_MIN || 1782 sc->alc_process_limit > ALC_PROC_MAX) { 1783 device_printf(sc->alc_dev, 1784 "process_limit value out of range; " 1785 "using default: %d\n", ALC_PROC_DEFAULT); 1786 sc->alc_process_limit = ALC_PROC_DEFAULT; 1787 } 1788 } 1789 1790 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1791 NULL, "ALC statistics"); 1792 parent = SYSCTL_CHILDREN(tree); 1793 1794 /* Rx statistics. */ 1795 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1796 NULL, "Rx MAC statistics"); 1797 child = SYSCTL_CHILDREN(tree); 1798 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1799 &stats->rx_frames, "Good frames"); 1800 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1801 &stats->rx_bcast_frames, "Good broadcast frames"); 1802 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1803 &stats->rx_mcast_frames, "Good multicast frames"); 1804 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1805 &stats->rx_pause_frames, "Pause control frames"); 1806 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1807 &stats->rx_control_frames, "Control frames"); 1808 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1809 &stats->rx_crcerrs, "CRC errors"); 1810 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1811 &stats->rx_lenerrs, "Frames with length mismatched"); 1812 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1813 &stats->rx_bytes, "Good octets"); 1814 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1815 &stats->rx_bcast_bytes, "Good broadcast octets"); 1816 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1817 &stats->rx_mcast_bytes, "Good multicast octets"); 1818 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1819 &stats->rx_runts, "Too short frames"); 1820 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1821 &stats->rx_fragments, "Fragmented frames"); 1822 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1823 &stats->rx_pkts_64, "64 bytes frames"); 1824 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1825 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1826 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1827 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1828 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1829 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1830 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1831 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1832 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1833 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1834 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1835 &stats->rx_pkts_1519_max, "1519 to max frames"); 1836 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1837 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1838 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1839 &stats->rx_fifo_oflows, "FIFO overflows"); 1840 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1841 &stats->rx_rrs_errs, "Return status write-back errors"); 1842 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1843 &stats->rx_alignerrs, "Alignment errors"); 1844 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1845 &stats->rx_pkts_filtered, 1846 "Frames dropped due to address filtering"); 1847 1848 /* Tx statistics. */ 1849 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1850 NULL, "Tx MAC statistics"); 1851 child = SYSCTL_CHILDREN(tree); 1852 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1853 &stats->tx_frames, "Good frames"); 1854 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1855 &stats->tx_bcast_frames, "Good broadcast frames"); 1856 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1857 &stats->tx_mcast_frames, "Good multicast frames"); 1858 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1859 &stats->tx_pause_frames, "Pause control frames"); 1860 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1861 &stats->tx_control_frames, "Control frames"); 1862 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1863 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1864 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1865 &stats->tx_excess_defer, "Frames with derferrals"); 1866 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1867 &stats->tx_bytes, "Good octets"); 1868 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1869 &stats->tx_bcast_bytes, "Good broadcast octets"); 1870 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1871 &stats->tx_mcast_bytes, "Good multicast octets"); 1872 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1873 &stats->tx_pkts_64, "64 bytes frames"); 1874 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1875 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1876 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1877 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1878 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1879 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1880 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1881 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1882 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1883 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1884 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1885 &stats->tx_pkts_1519_max, "1519 to max frames"); 1886 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1887 &stats->tx_single_colls, "Single collisions"); 1888 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1889 &stats->tx_multi_colls, "Multiple collisions"); 1890 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1891 &stats->tx_late_colls, "Late collisions"); 1892 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1893 &stats->tx_excess_colls, "Excessive collisions"); 1894 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1895 &stats->tx_underrun, "FIFO underruns"); 1896 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1897 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1898 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1899 &stats->tx_lenerrs, "Frames with length mismatched"); 1900 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1901 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1902} 1903 1904#undef ALC_SYSCTL_STAT_ADD32 1905#undef ALC_SYSCTL_STAT_ADD64 1906 1907struct alc_dmamap_arg { 1908 bus_addr_t alc_busaddr; 1909}; 1910 1911static void 1912alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1913{ 1914 struct alc_dmamap_arg *ctx; 1915 1916 if (error != 0) 1917 return; 1918 1919 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1920 1921 ctx = (struct alc_dmamap_arg *)arg; 1922 ctx->alc_busaddr = segs[0].ds_addr; 1923} 1924 1925/* 1926 * Normal and high Tx descriptors shares single Tx high address. 1927 * Four Rx descriptor/return rings and CMB shares the same Rx 1928 * high address. 1929 */ 1930static int 1931alc_check_boundary(struct alc_softc *sc) 1932{ 1933 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1934 1935 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1936 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1937 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1938 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1939 1940 /* 4GB boundary crossing is not allowed. */ 1941 if ((ALC_ADDR_HI(rx_ring_end) != 1942 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1943 (ALC_ADDR_HI(rr_ring_end) != 1944 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1945 (ALC_ADDR_HI(cmb_end) != 1946 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1947 (ALC_ADDR_HI(tx_ring_end) != 1948 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1949 return (EFBIG); 1950 /* 1951 * Make sure Rx return descriptor/Rx descriptor/CMB use 1952 * the same high address. 1953 */ 1954 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1955 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1956 return (EFBIG); 1957 1958 return (0); 1959} 1960 1961static int 1962alc_dma_alloc(struct alc_softc *sc) 1963{ 1964 struct alc_txdesc *txd; 1965 struct alc_rxdesc *rxd; 1966 bus_addr_t lowaddr; 1967 struct alc_dmamap_arg ctx; 1968 int error, i; 1969 1970 lowaddr = BUS_SPACE_MAXADDR; 1971again: 1972 /* Create parent DMA tag. */ 1973 error = bus_dma_tag_create( 1974 bus_get_dma_tag(sc->alc_dev), /* parent */ 1975 1, 0, /* alignment, boundary */ 1976 lowaddr, /* lowaddr */ 1977 BUS_SPACE_MAXADDR, /* highaddr */ 1978 NULL, NULL, /* filter, filterarg */ 1979 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1980 0, /* nsegments */ 1981 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1982 0, /* flags */ 1983 NULL, NULL, /* lockfunc, lockarg */ 1984 &sc->alc_cdata.alc_parent_tag); 1985 if (error != 0) { 1986 device_printf(sc->alc_dev, 1987 "could not create parent DMA tag.\n"); 1988 goto fail; 1989 } 1990 1991 /* Create DMA tag for Tx descriptor ring. */ 1992 error = bus_dma_tag_create( 1993 sc->alc_cdata.alc_parent_tag, /* parent */ 1994 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1995 BUS_SPACE_MAXADDR, /* lowaddr */ 1996 BUS_SPACE_MAXADDR, /* highaddr */ 1997 NULL, NULL, /* filter, filterarg */ 1998 ALC_TX_RING_SZ, /* maxsize */ 1999 1, /* nsegments */ 2000 ALC_TX_RING_SZ, /* maxsegsize */ 2001 0, /* flags */ 2002 NULL, NULL, /* lockfunc, lockarg */ 2003 &sc->alc_cdata.alc_tx_ring_tag); 2004 if (error != 0) { 2005 device_printf(sc->alc_dev, 2006 "could not create Tx ring DMA tag.\n"); 2007 goto fail; 2008 } 2009 2010 /* Create DMA tag for Rx free descriptor ring. */ 2011 error = bus_dma_tag_create( 2012 sc->alc_cdata.alc_parent_tag, /* parent */ 2013 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2014 BUS_SPACE_MAXADDR, /* lowaddr */ 2015 BUS_SPACE_MAXADDR, /* highaddr */ 2016 NULL, NULL, /* filter, filterarg */ 2017 ALC_RX_RING_SZ, /* maxsize */ 2018 1, /* nsegments */ 2019 ALC_RX_RING_SZ, /* maxsegsize */ 2020 0, /* flags */ 2021 NULL, NULL, /* lockfunc, lockarg */ 2022 &sc->alc_cdata.alc_rx_ring_tag); 2023 if (error != 0) { 2024 device_printf(sc->alc_dev, 2025 "could not create Rx ring DMA tag.\n"); 2026 goto fail; 2027 } 2028 /* Create DMA tag for Rx return descriptor ring. */ 2029 error = bus_dma_tag_create( 2030 sc->alc_cdata.alc_parent_tag, /* parent */ 2031 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2032 BUS_SPACE_MAXADDR, /* lowaddr */ 2033 BUS_SPACE_MAXADDR, /* highaddr */ 2034 NULL, NULL, /* filter, filterarg */ 2035 ALC_RR_RING_SZ, /* maxsize */ 2036 1, /* nsegments */ 2037 ALC_RR_RING_SZ, /* maxsegsize */ 2038 0, /* flags */ 2039 NULL, NULL, /* lockfunc, lockarg */ 2040 &sc->alc_cdata.alc_rr_ring_tag); 2041 if (error != 0) { 2042 device_printf(sc->alc_dev, 2043 "could not create Rx return ring DMA tag.\n"); 2044 goto fail; 2045 } 2046 2047 /* Create DMA tag for coalescing message block. */ 2048 error = bus_dma_tag_create( 2049 sc->alc_cdata.alc_parent_tag, /* parent */ 2050 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2051 BUS_SPACE_MAXADDR, /* lowaddr */ 2052 BUS_SPACE_MAXADDR, /* highaddr */ 2053 NULL, NULL, /* filter, filterarg */ 2054 ALC_CMB_SZ, /* maxsize */ 2055 1, /* nsegments */ 2056 ALC_CMB_SZ, /* maxsegsize */ 2057 0, /* flags */ 2058 NULL, NULL, /* lockfunc, lockarg */ 2059 &sc->alc_cdata.alc_cmb_tag); 2060 if (error != 0) { 2061 device_printf(sc->alc_dev, 2062 "could not create CMB DMA tag.\n"); 2063 goto fail; 2064 } 2065 /* Create DMA tag for status message block. */ 2066 error = bus_dma_tag_create( 2067 sc->alc_cdata.alc_parent_tag, /* parent */ 2068 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2069 BUS_SPACE_MAXADDR, /* lowaddr */ 2070 BUS_SPACE_MAXADDR, /* highaddr */ 2071 NULL, NULL, /* filter, filterarg */ 2072 ALC_SMB_SZ, /* maxsize */ 2073 1, /* nsegments */ 2074 ALC_SMB_SZ, /* maxsegsize */ 2075 0, /* flags */ 2076 NULL, NULL, /* lockfunc, lockarg */ 2077 &sc->alc_cdata.alc_smb_tag); 2078 if (error != 0) { 2079 device_printf(sc->alc_dev, 2080 "could not create SMB DMA tag.\n"); 2081 goto fail; 2082 } 2083 2084 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2085 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2086 (void **)&sc->alc_rdata.alc_tx_ring, 2087 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2088 &sc->alc_cdata.alc_tx_ring_map); 2089 if (error != 0) { 2090 device_printf(sc->alc_dev, 2091 "could not allocate DMA'able memory for Tx ring.\n"); 2092 goto fail; 2093 } 2094 ctx.alc_busaddr = 0; 2095 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2096 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2097 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2098 if (error != 0 || ctx.alc_busaddr == 0) { 2099 device_printf(sc->alc_dev, 2100 "could not load DMA'able memory for Tx ring.\n"); 2101 goto fail; 2102 } 2103 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2104 2105 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2106 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2107 (void **)&sc->alc_rdata.alc_rx_ring, 2108 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2109 &sc->alc_cdata.alc_rx_ring_map); 2110 if (error != 0) { 2111 device_printf(sc->alc_dev, 2112 "could not allocate DMA'able memory for Rx ring.\n"); 2113 goto fail; 2114 } 2115 ctx.alc_busaddr = 0; 2116 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2117 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2118 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2119 if (error != 0 || ctx.alc_busaddr == 0) { 2120 device_printf(sc->alc_dev, 2121 "could not load DMA'able memory for Rx ring.\n"); 2122 goto fail; 2123 } 2124 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2125 2126 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2127 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2128 (void **)&sc->alc_rdata.alc_rr_ring, 2129 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2130 &sc->alc_cdata.alc_rr_ring_map); 2131 if (error != 0) { 2132 device_printf(sc->alc_dev, 2133 "could not allocate DMA'able memory for Rx return ring.\n"); 2134 goto fail; 2135 } 2136 ctx.alc_busaddr = 0; 2137 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2138 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2139 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2140 if (error != 0 || ctx.alc_busaddr == 0) { 2141 device_printf(sc->alc_dev, 2142 "could not load DMA'able memory for Tx ring.\n"); 2143 goto fail; 2144 } 2145 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2146 2147 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2148 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2149 (void **)&sc->alc_rdata.alc_cmb, 2150 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2151 &sc->alc_cdata.alc_cmb_map); 2152 if (error != 0) { 2153 device_printf(sc->alc_dev, 2154 "could not allocate DMA'able memory for CMB.\n"); 2155 goto fail; 2156 } 2157 ctx.alc_busaddr = 0; 2158 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2159 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2160 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2161 if (error != 0 || ctx.alc_busaddr == 0) { 2162 device_printf(sc->alc_dev, 2163 "could not load DMA'able memory for CMB.\n"); 2164 goto fail; 2165 } 2166 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2167 2168 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2169 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2170 (void **)&sc->alc_rdata.alc_smb, 2171 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2172 &sc->alc_cdata.alc_smb_map); 2173 if (error != 0) { 2174 device_printf(sc->alc_dev, 2175 "could not allocate DMA'able memory for SMB.\n"); 2176 goto fail; 2177 } 2178 ctx.alc_busaddr = 0; 2179 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2180 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2181 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2182 if (error != 0 || ctx.alc_busaddr == 0) { 2183 device_printf(sc->alc_dev, 2184 "could not load DMA'able memory for CMB.\n"); 2185 goto fail; 2186 } 2187 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2188 2189 /* Make sure we've not crossed 4GB boundary. */ 2190 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2191 (error = alc_check_boundary(sc)) != 0) { 2192 device_printf(sc->alc_dev, "4GB boundary crossed, " 2193 "switching to 32bit DMA addressing mode.\n"); 2194 alc_dma_free(sc); 2195 /* 2196 * Limit max allowable DMA address space to 32bit 2197 * and try again. 2198 */ 2199 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2200 goto again; 2201 } 2202 2203 /* 2204 * Create Tx buffer parent tag. 2205 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2206 * so it needs separate parent DMA tag as parent DMA address 2207 * space could be restricted to be within 32bit address space 2208 * by 4GB boundary crossing. 2209 */ 2210 error = bus_dma_tag_create( 2211 bus_get_dma_tag(sc->alc_dev), /* parent */ 2212 1, 0, /* alignment, boundary */ 2213 BUS_SPACE_MAXADDR, /* lowaddr */ 2214 BUS_SPACE_MAXADDR, /* highaddr */ 2215 NULL, NULL, /* filter, filterarg */ 2216 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2217 0, /* nsegments */ 2218 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2219 0, /* flags */ 2220 NULL, NULL, /* lockfunc, lockarg */ 2221 &sc->alc_cdata.alc_buffer_tag); 2222 if (error != 0) { 2223 device_printf(sc->alc_dev, 2224 "could not create parent buffer DMA tag.\n"); 2225 goto fail; 2226 } 2227 2228 /* Create DMA tag for Tx buffers. */ 2229 error = bus_dma_tag_create( 2230 sc->alc_cdata.alc_buffer_tag, /* parent */ 2231 1, 0, /* alignment, boundary */ 2232 BUS_SPACE_MAXADDR, /* lowaddr */ 2233 BUS_SPACE_MAXADDR, /* highaddr */ 2234 NULL, NULL, /* filter, filterarg */ 2235 ALC_TSO_MAXSIZE, /* maxsize */ 2236 ALC_MAXTXSEGS, /* nsegments */ 2237 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2238 0, /* flags */ 2239 NULL, NULL, /* lockfunc, lockarg */ 2240 &sc->alc_cdata.alc_tx_tag); 2241 if (error != 0) { 2242 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2243 goto fail; 2244 } 2245 2246 /* Create DMA tag for Rx buffers. */ 2247 error = bus_dma_tag_create( 2248 sc->alc_cdata.alc_buffer_tag, /* parent */ 2249 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2250 BUS_SPACE_MAXADDR, /* lowaddr */ 2251 BUS_SPACE_MAXADDR, /* highaddr */ 2252 NULL, NULL, /* filter, filterarg */ 2253 MCLBYTES, /* maxsize */ 2254 1, /* nsegments */ 2255 MCLBYTES, /* maxsegsize */ 2256 0, /* flags */ 2257 NULL, NULL, /* lockfunc, lockarg */ 2258 &sc->alc_cdata.alc_rx_tag); 2259 if (error != 0) { 2260 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2261 goto fail; 2262 } 2263 /* Create DMA maps for Tx buffers. */ 2264 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2265 txd = &sc->alc_cdata.alc_txdesc[i]; 2266 txd->tx_m = NULL; 2267 txd->tx_dmamap = NULL; 2268 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2269 &txd->tx_dmamap); 2270 if (error != 0) { 2271 device_printf(sc->alc_dev, 2272 "could not create Tx dmamap.\n"); 2273 goto fail; 2274 } 2275 } 2276 /* Create DMA maps for Rx buffers. */ 2277 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2278 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2279 device_printf(sc->alc_dev, 2280 "could not create spare Rx dmamap.\n"); 2281 goto fail; 2282 } 2283 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2284 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2285 rxd->rx_m = NULL; 2286 rxd->rx_dmamap = NULL; 2287 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2288 &rxd->rx_dmamap); 2289 if (error != 0) { 2290 device_printf(sc->alc_dev, 2291 "could not create Rx dmamap.\n"); 2292 goto fail; 2293 } 2294 } 2295 2296fail: 2297 return (error); 2298} 2299 2300static void 2301alc_dma_free(struct alc_softc *sc) 2302{ 2303 struct alc_txdesc *txd; 2304 struct alc_rxdesc *rxd; 2305 int i; 2306 2307 /* Tx buffers. */ 2308 if (sc->alc_cdata.alc_tx_tag != NULL) { 2309 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2310 txd = &sc->alc_cdata.alc_txdesc[i]; 2311 if (txd->tx_dmamap != NULL) { 2312 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2313 txd->tx_dmamap); 2314 txd->tx_dmamap = NULL; 2315 } 2316 } 2317 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2318 sc->alc_cdata.alc_tx_tag = NULL; 2319 } 2320 /* Rx buffers */ 2321 if (sc->alc_cdata.alc_rx_tag != NULL) { 2322 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2323 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2324 if (rxd->rx_dmamap != NULL) { 2325 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2326 rxd->rx_dmamap); 2327 rxd->rx_dmamap = NULL; 2328 } 2329 } 2330 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2331 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2332 sc->alc_cdata.alc_rx_sparemap); 2333 sc->alc_cdata.alc_rx_sparemap = NULL; 2334 } 2335 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2336 sc->alc_cdata.alc_rx_tag = NULL; 2337 } 2338 /* Tx descriptor ring. */ 2339 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2340 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2341 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2342 sc->alc_cdata.alc_tx_ring_map); 2343 if (sc->alc_rdata.alc_tx_ring != NULL) 2344 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2345 sc->alc_rdata.alc_tx_ring, 2346 sc->alc_cdata.alc_tx_ring_map); 2347 sc->alc_rdata.alc_tx_ring_paddr = 0; 2348 sc->alc_rdata.alc_tx_ring = NULL; 2349 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2350 sc->alc_cdata.alc_tx_ring_tag = NULL; 2351 } 2352 /* Rx ring. */ 2353 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2354 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2355 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2356 sc->alc_cdata.alc_rx_ring_map); 2357 if (sc->alc_rdata.alc_rx_ring != NULL) 2358 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2359 sc->alc_rdata.alc_rx_ring, 2360 sc->alc_cdata.alc_rx_ring_map); 2361 sc->alc_rdata.alc_rx_ring_paddr = 0; 2362 sc->alc_rdata.alc_rx_ring = NULL; 2363 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2364 sc->alc_cdata.alc_rx_ring_tag = NULL; 2365 } 2366 /* Rx return ring. */ 2367 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2368 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2369 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2370 sc->alc_cdata.alc_rr_ring_map); 2371 if (sc->alc_rdata.alc_rr_ring != NULL) 2372 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2373 sc->alc_rdata.alc_rr_ring, 2374 sc->alc_cdata.alc_rr_ring_map); 2375 sc->alc_rdata.alc_rr_ring_paddr = 0; 2376 sc->alc_rdata.alc_rr_ring = NULL; 2377 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2378 sc->alc_cdata.alc_rr_ring_tag = NULL; 2379 } 2380 /* CMB block */ 2381 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2382 if (sc->alc_rdata.alc_cmb_paddr != 0) 2383 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2384 sc->alc_cdata.alc_cmb_map); 2385 if (sc->alc_rdata.alc_cmb != NULL) 2386 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2387 sc->alc_rdata.alc_cmb, 2388 sc->alc_cdata.alc_cmb_map); 2389 sc->alc_rdata.alc_cmb_paddr = 0; 2390 sc->alc_rdata.alc_cmb = NULL; 2391 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2392 sc->alc_cdata.alc_cmb_tag = NULL; 2393 } 2394 /* SMB block */ 2395 if (sc->alc_cdata.alc_smb_tag != NULL) { 2396 if (sc->alc_rdata.alc_smb_paddr != 0) 2397 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2398 sc->alc_cdata.alc_smb_map); 2399 if (sc->alc_rdata.alc_smb != NULL) 2400 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2401 sc->alc_rdata.alc_smb, 2402 sc->alc_cdata.alc_smb_map); 2403 sc->alc_rdata.alc_smb_paddr = 0; 2404 sc->alc_rdata.alc_smb = NULL; 2405 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2406 sc->alc_cdata.alc_smb_tag = NULL; 2407 } 2408 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2409 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2410 sc->alc_cdata.alc_buffer_tag = NULL; 2411 } 2412 if (sc->alc_cdata.alc_parent_tag != NULL) { 2413 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2414 sc->alc_cdata.alc_parent_tag = NULL; 2415 } 2416} 2417 2418static int 2419alc_shutdown(device_t dev) 2420{ 2421 2422 return (alc_suspend(dev)); 2423} 2424 2425/* 2426 * Note, this driver resets the link speed to 10/100Mbps by 2427 * restarting auto-negotiation in suspend/shutdown phase but we 2428 * don't know whether that auto-negotiation would succeed or not 2429 * as driver has no control after powering off/suspend operation. 2430 * If the renegotiation fail WOL may not work. Running at 1Gbps 2431 * will draw more power than 375mA at 3.3V which is specified in 2432 * PCI specification and that would result in complete 2433 * shutdowning power to ethernet controller. 2434 * 2435 * TODO 2436 * Save current negotiated media speed/duplex/flow-control to 2437 * softc and restore the same link again after resuming. PHY 2438 * handling such as power down/resetting to 100Mbps may be better 2439 * handled in suspend method in phy driver. 2440 */ 2441static void 2442alc_setlinkspeed(struct alc_softc *sc) 2443{ 2444 struct mii_data *mii; 2445 int aneg, i; 2446 2447 mii = device_get_softc(sc->alc_miibus); 2448 mii_pollstat(mii); 2449 aneg = 0; 2450 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2451 (IFM_ACTIVE | IFM_AVALID)) { 2452 switch IFM_SUBTYPE(mii->mii_media_active) { 2453 case IFM_10_T: 2454 case IFM_100_TX: 2455 return; 2456 case IFM_1000_T: 2457 aneg++; 2458 break; 2459 default: 2460 break; 2461 } 2462 } 2463 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2464 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2465 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2466 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2467 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2468 DELAY(1000); 2469 if (aneg != 0) { 2470 /* 2471 * Poll link state until alc(4) get a 10/100Mbps link. 2472 */ 2473 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2474 mii_pollstat(mii); 2475 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2476 == (IFM_ACTIVE | IFM_AVALID)) { 2477 switch (IFM_SUBTYPE( 2478 mii->mii_media_active)) { 2479 case IFM_10_T: 2480 case IFM_100_TX: 2481 alc_mac_config(sc); 2482 return; 2483 default: 2484 break; 2485 } 2486 } 2487 ALC_UNLOCK(sc); 2488 pause("alclnk", hz); 2489 ALC_LOCK(sc); 2490 } 2491 if (i == MII_ANEGTICKS_GIGE) 2492 device_printf(sc->alc_dev, 2493 "establishing a link failed, WOL may not work!"); 2494 } 2495 /* 2496 * No link, force MAC to have 100Mbps, full-duplex link. 2497 * This is the last resort and may/may not work. 2498 */ 2499 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2500 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2501 alc_mac_config(sc); 2502} 2503 2504static void 2505alc_setwol(struct alc_softc *sc) 2506{ 2507 2508 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2509 alc_setwol_816x(sc); 2510 else 2511 alc_setwol_813x(sc); 2512} 2513 2514static void 2515alc_setwol_813x(struct alc_softc *sc) 2516{ 2517 struct ifnet *ifp; 2518 uint32_t reg, pmcs; 2519 uint16_t pmstat; 2520 2521 ALC_LOCK_ASSERT(sc); 2522 2523 alc_disable_l0s_l1(sc); 2524 ifp = sc->alc_ifp; 2525 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2526 /* Disable WOL. */ 2527 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2528 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2529 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2530 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2531 /* Force PHY power down. */ 2532 alc_phy_down(sc); 2533 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2534 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2535 return; 2536 } 2537 2538 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2539 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2540 alc_setlinkspeed(sc); 2541 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2542 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2543 } 2544 2545 pmcs = 0; 2546 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2547 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2548 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2549 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2550 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2551 MAC_CFG_BCAST); 2552 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2553 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2554 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2555 reg |= MAC_CFG_RX_ENB; 2556 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2557 2558 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2559 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2560 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2561 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2562 /* WOL disabled, PHY power down. */ 2563 alc_phy_down(sc); 2564 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2565 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2566 } 2567 /* Request PME. */ 2568 pmstat = pci_read_config(sc->alc_dev, 2569 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2570 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2571 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2572 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2573 pci_write_config(sc->alc_dev, 2574 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2575} 2576 2577static void 2578alc_setwol_816x(struct alc_softc *sc) 2579{ 2580 struct ifnet *ifp; 2581 uint32_t gphy, mac, master, pmcs, reg; 2582 uint16_t pmstat; 2583 2584 ALC_LOCK_ASSERT(sc); 2585 2586 ifp = sc->alc_ifp; 2587 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2588 master &= ~MASTER_CLK_SEL_DIS; 2589 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2590 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2591 GPHY_CFG_PHY_PLL_ON); 2592 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2593 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2594 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2595 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2596 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2597 } else { 2598 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2599 gphy |= GPHY_CFG_EXT_RESET; 2600 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2601 alc_setlinkspeed(sc); 2602 } 2603 pmcs = 0; 2604 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2605 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2606 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2607 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2608 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2609 MAC_CFG_BCAST); 2610 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2611 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2612 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2613 mac |= MAC_CFG_RX_ENB; 2614 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2615 ANEG_S3DIG10_SL); 2616 } 2617 2618 /* Enable OSC. */ 2619 reg = CSR_READ_4(sc, ALC_MISC); 2620 reg &= ~MISC_INTNLOSC_OPEN; 2621 CSR_WRITE_4(sc, ALC_MISC, reg); 2622 reg |= MISC_INTNLOSC_OPEN; 2623 CSR_WRITE_4(sc, ALC_MISC, reg); 2624 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2625 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2626 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2627 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2628 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2629 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2630 2631 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2632 /* Request PME. */ 2633 pmstat = pci_read_config(sc->alc_dev, 2634 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2635 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2636 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2637 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2638 pci_write_config(sc->alc_dev, 2639 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2640 } 2641} 2642 2643static int 2644alc_suspend(device_t dev) 2645{ 2646 struct alc_softc *sc; 2647 2648 sc = device_get_softc(dev); 2649 2650 ALC_LOCK(sc); 2651 alc_stop(sc); 2652 alc_setwol(sc); 2653 ALC_UNLOCK(sc); 2654 2655 return (0); 2656} 2657 2658static int 2659alc_resume(device_t dev) 2660{ 2661 struct alc_softc *sc; 2662 struct ifnet *ifp; 2663 uint16_t pmstat; 2664 2665 sc = device_get_softc(dev); 2666 2667 ALC_LOCK(sc); 2668 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2669 /* Disable PME and clear PME status. */ 2670 pmstat = pci_read_config(sc->alc_dev, 2671 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2672 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2673 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2674 pci_write_config(sc->alc_dev, 2675 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2676 } 2677 } 2678 /* Reset PHY. */ 2679 alc_phy_reset(sc); 2680 ifp = sc->alc_ifp; 2681 if ((ifp->if_flags & IFF_UP) != 0) { 2682 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2683 alc_init_locked(sc); 2684 } 2685 ALC_UNLOCK(sc); 2686 2687 return (0); 2688} 2689 2690static int 2691alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2692{ 2693 struct alc_txdesc *txd, *txd_last; 2694 struct tx_desc *desc; 2695 struct mbuf *m; 2696 struct ip *ip; 2697 struct tcphdr *tcp; 2698 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2699 bus_dmamap_t map; 2700 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2701 int error, idx, nsegs, prod; 2702 2703 ALC_LOCK_ASSERT(sc); 2704 2705 M_ASSERTPKTHDR((*m_head)); 2706 2707 m = *m_head; 2708 ip = NULL; 2709 tcp = NULL; 2710 ip_off = poff = 0; 2711 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2712 /* 2713 * AR81[3567]x requires offset of TCP/UDP header in its 2714 * Tx descriptor to perform Tx checksum offloading. TSO 2715 * also requires TCP header offset and modification of 2716 * IP/TCP header. This kind of operation takes many CPU 2717 * cycles on FreeBSD so fast host CPU is required to get 2718 * smooth TSO performance. 2719 */ 2720 struct ether_header *eh; 2721 2722 if (M_WRITABLE(m) == 0) { 2723 /* Get a writable copy. */ 2724 m = m_dup(*m_head, M_NOWAIT); 2725 /* Release original mbufs. */ 2726 m_freem(*m_head); 2727 if (m == NULL) { 2728 *m_head = NULL; 2729 return (ENOBUFS); 2730 } 2731 *m_head = m; 2732 } 2733 2734 ip_off = sizeof(struct ether_header); 2735 m = m_pullup(m, ip_off); 2736 if (m == NULL) { 2737 *m_head = NULL; 2738 return (ENOBUFS); 2739 } 2740 eh = mtod(m, struct ether_header *); 2741 /* 2742 * Check if hardware VLAN insertion is off. 2743 * Additional check for LLC/SNAP frame? 2744 */ 2745 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2746 ip_off = sizeof(struct ether_vlan_header); 2747 m = m_pullup(m, ip_off); 2748 if (m == NULL) { 2749 *m_head = NULL; 2750 return (ENOBUFS); 2751 } 2752 } 2753 m = m_pullup(m, ip_off + sizeof(struct ip)); 2754 if (m == NULL) { 2755 *m_head = NULL; 2756 return (ENOBUFS); 2757 } 2758 ip = (struct ip *)(mtod(m, char *) + ip_off); 2759 poff = ip_off + (ip->ip_hl << 2); 2760 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2761 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2762 if (m == NULL) { 2763 *m_head = NULL; 2764 return (ENOBUFS); 2765 } 2766 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2767 m = m_pullup(m, poff + (tcp->th_off << 2)); 2768 if (m == NULL) { 2769 *m_head = NULL; 2770 return (ENOBUFS); 2771 } 2772 /* 2773 * Due to strict adherence of Microsoft NDIS 2774 * Large Send specification, hardware expects 2775 * a pseudo TCP checksum inserted by upper 2776 * stack. Unfortunately the pseudo TCP 2777 * checksum that NDIS refers to does not include 2778 * TCP payload length so driver should recompute 2779 * the pseudo checksum here. Hopefully this 2780 * wouldn't be much burden on modern CPUs. 2781 * 2782 * Reset IP checksum and recompute TCP pseudo 2783 * checksum as NDIS specification said. 2784 */ 2785 ip = (struct ip *)(mtod(m, char *) + ip_off); 2786 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2787 ip->ip_sum = 0; 2788 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2789 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2790 } 2791 *m_head = m; 2792 } 2793 2794 prod = sc->alc_cdata.alc_tx_prod; 2795 txd = &sc->alc_cdata.alc_txdesc[prod]; 2796 txd_last = txd; 2797 map = txd->tx_dmamap; 2798 2799 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2800 *m_head, txsegs, &nsegs, 0); 2801 if (error == EFBIG) { 2802 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2803 if (m == NULL) { 2804 m_freem(*m_head); 2805 *m_head = NULL; 2806 return (ENOMEM); 2807 } 2808 *m_head = m; 2809 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2810 *m_head, txsegs, &nsegs, 0); 2811 if (error != 0) { 2812 m_freem(*m_head); 2813 *m_head = NULL; 2814 return (error); 2815 } 2816 } else if (error != 0) 2817 return (error); 2818 if (nsegs == 0) { 2819 m_freem(*m_head); 2820 *m_head = NULL; 2821 return (EIO); 2822 } 2823 2824 /* Check descriptor overrun. */ 2825 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2826 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2827 return (ENOBUFS); 2828 } 2829 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2830 2831 m = *m_head; 2832 cflags = TD_ETHERNET; 2833 vtag = 0; 2834 desc = NULL; 2835 idx = 0; 2836 /* Configure VLAN hardware tag insertion. */ 2837 if ((m->m_flags & M_VLANTAG) != 0) { 2838 vtag = htons(m->m_pkthdr.ether_vtag); 2839 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2840 cflags |= TD_INS_VLAN_TAG; 2841 } 2842 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2843 /* Request TSO and set MSS. */ 2844 cflags |= TD_TSO | TD_TSO_DESCV1; 2845 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2846 TD_MSS_MASK; 2847 /* Set TCP header offset. */ 2848 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2849 TD_TCPHDR_OFFSET_MASK; 2850 /* 2851 * AR81[3567]x requires the first buffer should 2852 * only hold IP/TCP header data. Payload should 2853 * be handled in other descriptors. 2854 */ 2855 hdrlen = poff + (tcp->th_off << 2); 2856 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2857 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2858 desc->flags = htole32(cflags); 2859 desc->addr = htole64(txsegs[0].ds_addr); 2860 sc->alc_cdata.alc_tx_cnt++; 2861 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2862 if (m->m_len - hdrlen > 0) { 2863 /* Handle remaining payload of the first fragment. */ 2864 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2865 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2866 vtag)); 2867 desc->flags = htole32(cflags); 2868 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2869 sc->alc_cdata.alc_tx_cnt++; 2870 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2871 } 2872 /* Handle remaining fragments. */ 2873 idx = 1; 2874 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2875 /* Configure Tx checksum offload. */ 2876#ifdef ALC_USE_CUSTOM_CSUM 2877 cflags |= TD_CUSTOM_CSUM; 2878 /* Set checksum start offset. */ 2879 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2880 TD_PLOAD_OFFSET_MASK; 2881 /* Set checksum insertion position of TCP/UDP. */ 2882 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2883 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2884#else 2885 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2886 cflags |= TD_IPCSUM; 2887 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2888 cflags |= TD_TCPCSUM; 2889 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2890 cflags |= TD_UDPCSUM; 2891 /* Set TCP/UDP header offset. */ 2892 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2893 TD_L4HDR_OFFSET_MASK; 2894#endif 2895 } 2896 for (; idx < nsegs; idx++) { 2897 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2898 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2899 desc->flags = htole32(cflags); 2900 desc->addr = htole64(txsegs[idx].ds_addr); 2901 sc->alc_cdata.alc_tx_cnt++; 2902 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2903 } 2904 /* Update producer index. */ 2905 sc->alc_cdata.alc_tx_prod = prod; 2906 2907 /* Finally set EOP on the last descriptor. */ 2908 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2909 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2910 desc->flags |= htole32(TD_EOP); 2911 2912 /* Swap dmamap of the first and the last. */ 2913 txd = &sc->alc_cdata.alc_txdesc[prod]; 2914 map = txd_last->tx_dmamap; 2915 txd_last->tx_dmamap = txd->tx_dmamap; 2916 txd->tx_dmamap = map; 2917 txd->tx_m = m; 2918 2919 return (0); 2920} 2921 2922static void 2923alc_start(struct ifnet *ifp) 2924{ 2925 struct alc_softc *sc; 2926 2927 sc = ifp->if_softc; 2928 ALC_LOCK(sc); 2929 alc_start_locked(ifp); 2930 ALC_UNLOCK(sc); 2931} 2932 2933static void 2934alc_start_locked(struct ifnet *ifp) 2935{ 2936 struct alc_softc *sc; 2937 struct mbuf *m_head; 2938 int enq; 2939 2940 sc = ifp->if_softc; 2941 2942 ALC_LOCK_ASSERT(sc); 2943 2944 /* Reclaim transmitted frames. */ 2945 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2946 alc_txeof(sc); 2947 2948 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2949 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2950 return; 2951 2952 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2953 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2954 if (m_head == NULL) 2955 break; 2956 /* 2957 * Pack the data into the transmit ring. If we 2958 * don't have room, set the OACTIVE flag and wait 2959 * for the NIC to drain the ring. 2960 */ 2961 if (alc_encap(sc, &m_head)) { 2962 if (m_head == NULL) 2963 break; 2964 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2965 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2966 break; 2967 } 2968 2969 enq++; 2970 /* 2971 * If there's a BPF listener, bounce a copy of this frame 2972 * to him. 2973 */ 2974 ETHER_BPF_MTAP(ifp, m_head); 2975 } 2976 2977 if (enq > 0) { 2978 /* Sync descriptors. */ 2979 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2980 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2981 /* Kick. Assume we're using normal Tx priority queue. */ 2982 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2983 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 2984 (uint16_t)sc->alc_cdata.alc_tx_prod); 2985 else 2986 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2987 (sc->alc_cdata.alc_tx_prod << 2988 MBOX_TD_PROD_LO_IDX_SHIFT) & 2989 MBOX_TD_PROD_LO_IDX_MASK); 2990 /* Set a timeout in case the chip goes out to lunch. */ 2991 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2992 } 2993} 2994 2995static void 2996alc_watchdog(struct alc_softc *sc) 2997{ 2998 struct ifnet *ifp; 2999 3000 ALC_LOCK_ASSERT(sc); 3001 3002 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3003 return; 3004 3005 ifp = sc->alc_ifp; 3006 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3007 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3008 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3009 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3010 alc_init_locked(sc); 3011 return; 3012 } 3013 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3014 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3015 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3016 alc_init_locked(sc); 3017 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3018 alc_start_locked(ifp); 3019} 3020 3021static int 3022alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3023{ 3024 struct alc_softc *sc; 3025 struct ifreq *ifr; 3026 struct mii_data *mii; 3027 int error, mask; 3028 3029 sc = ifp->if_softc; 3030 ifr = (struct ifreq *)data; 3031 error = 0; 3032 switch (cmd) { 3033 case SIOCSIFMTU: 3034 if (ifr->ifr_mtu < ETHERMIN || 3035 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3036 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3037 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3038 ifr->ifr_mtu > ETHERMTU)) 3039 error = EINVAL; 3040 else if (ifp->if_mtu != ifr->ifr_mtu) { 3041 ALC_LOCK(sc); 3042 ifp->if_mtu = ifr->ifr_mtu; 3043 /* AR81[3567]x has 13 bits MSS field. */ 3044 if (ifp->if_mtu > ALC_TSO_MTU && 3045 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3046 ifp->if_capenable &= ~IFCAP_TSO4; 3047 ifp->if_hwassist &= ~CSUM_TSO; 3048 VLAN_CAPABILITIES(ifp); 3049 } 3050 ALC_UNLOCK(sc); 3051 } 3052 break; 3053 case SIOCSIFFLAGS: 3054 ALC_LOCK(sc); 3055 if ((ifp->if_flags & IFF_UP) != 0) { 3056 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3057 ((ifp->if_flags ^ sc->alc_if_flags) & 3058 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3059 alc_rxfilter(sc); 3060 else 3061 alc_init_locked(sc); 3062 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3063 alc_stop(sc); 3064 sc->alc_if_flags = ifp->if_flags; 3065 ALC_UNLOCK(sc); 3066 break; 3067 case SIOCADDMULTI: 3068 case SIOCDELMULTI: 3069 ALC_LOCK(sc); 3070 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3071 alc_rxfilter(sc); 3072 ALC_UNLOCK(sc); 3073 break; 3074 case SIOCSIFMEDIA: 3075 case SIOCGIFMEDIA: 3076 mii = device_get_softc(sc->alc_miibus); 3077 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3078 break; 3079 case SIOCSIFCAP: 3080 ALC_LOCK(sc); 3081 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3082 if ((mask & IFCAP_TXCSUM) != 0 && 3083 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3084 ifp->if_capenable ^= IFCAP_TXCSUM; 3085 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3086 ifp->if_hwassist |= ALC_CSUM_FEATURES; 3087 else 3088 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 3089 } 3090 if ((mask & IFCAP_TSO4) != 0 && 3091 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3092 ifp->if_capenable ^= IFCAP_TSO4; 3093 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 3094 /* AR81[3567]x has 13 bits MSS field. */ 3095 if (ifp->if_mtu > ALC_TSO_MTU) { 3096 ifp->if_capenable &= ~IFCAP_TSO4; 3097 ifp->if_hwassist &= ~CSUM_TSO; 3098 } else 3099 ifp->if_hwassist |= CSUM_TSO; 3100 } else 3101 ifp->if_hwassist &= ~CSUM_TSO; 3102 } 3103 if ((mask & IFCAP_WOL_MCAST) != 0 && 3104 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 3105 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3106 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3107 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3108 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3109 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3110 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3111 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3112 alc_rxvlan(sc); 3113 } 3114 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3115 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3116 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3117 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3118 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3119 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3120 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3121 ifp->if_capenable &= 3122 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3123 ALC_UNLOCK(sc); 3124 VLAN_CAPABILITIES(ifp); 3125 break; 3126 default: 3127 error = ether_ioctl(ifp, cmd, data); 3128 break; 3129 } 3130 3131 return (error); 3132} 3133 3134static void 3135alc_mac_config(struct alc_softc *sc) 3136{ 3137 struct mii_data *mii; 3138 uint32_t reg; 3139 3140 ALC_LOCK_ASSERT(sc); 3141 3142 mii = device_get_softc(sc->alc_miibus); 3143 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3144 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3145 MAC_CFG_SPEED_MASK); 3146 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3147 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3148 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3149 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3150 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3151 /* Reprogram MAC with resolved speed/duplex. */ 3152 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3153 case IFM_10_T: 3154 case IFM_100_TX: 3155 reg |= MAC_CFG_SPEED_10_100; 3156 break; 3157 case IFM_1000_T: 3158 reg |= MAC_CFG_SPEED_1000; 3159 break; 3160 } 3161 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3162 reg |= MAC_CFG_FULL_DUPLEX; 3163 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3164 reg |= MAC_CFG_TX_FC; 3165 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3166 reg |= MAC_CFG_RX_FC; 3167 } 3168 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3169} 3170 3171static void 3172alc_stats_clear(struct alc_softc *sc) 3173{ 3174 struct smb sb, *smb; 3175 uint32_t *reg; 3176 int i; 3177 3178 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3179 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3180 sc->alc_cdata.alc_smb_map, 3181 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3182 smb = sc->alc_rdata.alc_smb; 3183 /* Update done, clear. */ 3184 smb->updated = 0; 3185 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3186 sc->alc_cdata.alc_smb_map, 3187 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3188 } else { 3189 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3190 reg++) { 3191 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3192 i += sizeof(uint32_t); 3193 } 3194 /* Read Tx statistics. */ 3195 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3196 reg++) { 3197 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3198 i += sizeof(uint32_t); 3199 } 3200 } 3201} 3202 3203static void 3204alc_stats_update(struct alc_softc *sc) 3205{ 3206 struct alc_hw_stats *stat; 3207 struct smb sb, *smb; 3208 struct ifnet *ifp; 3209 uint32_t *reg; 3210 int i; 3211 3212 ALC_LOCK_ASSERT(sc); 3213 3214 ifp = sc->alc_ifp; 3215 stat = &sc->alc_stats; 3216 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3217 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3218 sc->alc_cdata.alc_smb_map, 3219 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3220 smb = sc->alc_rdata.alc_smb; 3221 if (smb->updated == 0) 3222 return; 3223 } else { 3224 smb = &sb; 3225 /* Read Rx statistics. */ 3226 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3227 reg++) { 3228 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3229 i += sizeof(uint32_t); 3230 } 3231 /* Read Tx statistics. */ 3232 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3233 reg++) { 3234 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3235 i += sizeof(uint32_t); 3236 } 3237 } 3238 3239 /* Rx stats. */ 3240 stat->rx_frames += smb->rx_frames; 3241 stat->rx_bcast_frames += smb->rx_bcast_frames; 3242 stat->rx_mcast_frames += smb->rx_mcast_frames; 3243 stat->rx_pause_frames += smb->rx_pause_frames; 3244 stat->rx_control_frames += smb->rx_control_frames; 3245 stat->rx_crcerrs += smb->rx_crcerrs; 3246 stat->rx_lenerrs += smb->rx_lenerrs; 3247 stat->rx_bytes += smb->rx_bytes; 3248 stat->rx_runts += smb->rx_runts; 3249 stat->rx_fragments += smb->rx_fragments; 3250 stat->rx_pkts_64 += smb->rx_pkts_64; 3251 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3252 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3253 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3254 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3255 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3256 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3257 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3258 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3259 stat->rx_rrs_errs += smb->rx_rrs_errs; 3260 stat->rx_alignerrs += smb->rx_alignerrs; 3261 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3262 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3263 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3264 3265 /* Tx stats. */ 3266 stat->tx_frames += smb->tx_frames; 3267 stat->tx_bcast_frames += smb->tx_bcast_frames; 3268 stat->tx_mcast_frames += smb->tx_mcast_frames; 3269 stat->tx_pause_frames += smb->tx_pause_frames; 3270 stat->tx_excess_defer += smb->tx_excess_defer; 3271 stat->tx_control_frames += smb->tx_control_frames; 3272 stat->tx_deferred += smb->tx_deferred; 3273 stat->tx_bytes += smb->tx_bytes; 3274 stat->tx_pkts_64 += smb->tx_pkts_64; 3275 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3276 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3277 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3278 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3279 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3280 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3281 stat->tx_single_colls += smb->tx_single_colls; 3282 stat->tx_multi_colls += smb->tx_multi_colls; 3283 stat->tx_late_colls += smb->tx_late_colls; 3284 stat->tx_excess_colls += smb->tx_excess_colls; 3285 stat->tx_underrun += smb->tx_underrun; 3286 stat->tx_desc_underrun += smb->tx_desc_underrun; 3287 stat->tx_lenerrs += smb->tx_lenerrs; 3288 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3289 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3290 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3291 3292 /* Update counters in ifnet. */ 3293 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3294 3295 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3296 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3297 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3298 3299 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3300 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3301 3302 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3303 3304 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3305 smb->rx_crcerrs + smb->rx_lenerrs + 3306 smb->rx_runts + smb->rx_pkts_truncated + 3307 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3308 smb->rx_alignerrs); 3309 3310 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3311 /* Update done, clear. */ 3312 smb->updated = 0; 3313 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3314 sc->alc_cdata.alc_smb_map, 3315 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3316 } 3317} 3318 3319static int 3320alc_intr(void *arg) 3321{ 3322 struct alc_softc *sc; 3323 uint32_t status; 3324 3325 sc = (struct alc_softc *)arg; 3326 3327 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3328 if ((status & ALC_INTRS) == 0) 3329 return (FILTER_STRAY); 3330 /* Disable interrupts. */ 3331 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3332 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3333 3334 return (FILTER_HANDLED); 3335} 3336 3337static void 3338alc_int_task(void *arg, int pending) 3339{ 3340 struct alc_softc *sc; 3341 struct ifnet *ifp; 3342 uint32_t status; 3343 int more; 3344 3345 sc = (struct alc_softc *)arg; 3346 ifp = sc->alc_ifp; 3347 3348 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3349 ALC_LOCK(sc); 3350 if (sc->alc_morework != 0) { 3351 sc->alc_morework = 0; 3352 status |= INTR_RX_PKT; 3353 } 3354 if ((status & ALC_INTRS) == 0) 3355 goto done; 3356 3357 /* Acknowledge interrupts but still disable interrupts. */ 3358 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3359 3360 more = 0; 3361 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3362 if ((status & INTR_RX_PKT) != 0) { 3363 more = alc_rxintr(sc, sc->alc_process_limit); 3364 if (more == EAGAIN) 3365 sc->alc_morework = 1; 3366 else if (more == EIO) { 3367 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3368 alc_init_locked(sc); 3369 ALC_UNLOCK(sc); 3370 return; 3371 } 3372 } 3373 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3374 INTR_TXQ_TO_RST)) != 0) { 3375 if ((status & INTR_DMA_RD_TO_RST) != 0) 3376 device_printf(sc->alc_dev, 3377 "DMA read error! -- resetting\n"); 3378 if ((status & INTR_DMA_WR_TO_RST) != 0) 3379 device_printf(sc->alc_dev, 3380 "DMA write error! -- resetting\n"); 3381 if ((status & INTR_TXQ_TO_RST) != 0) 3382 device_printf(sc->alc_dev, 3383 "TxQ reset! -- resetting\n"); 3384 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3385 alc_init_locked(sc); 3386 ALC_UNLOCK(sc); 3387 return; 3388 } 3389 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3390 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3391 alc_start_locked(ifp); 3392 } 3393 3394 if (more == EAGAIN || 3395 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3396 ALC_UNLOCK(sc); 3397 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3398 return; 3399 } 3400 3401done: 3402 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3403 /* Re-enable interrupts if we're running. */ 3404 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3405 } 3406 ALC_UNLOCK(sc); 3407} 3408 3409static void 3410alc_txeof(struct alc_softc *sc) 3411{ 3412 struct ifnet *ifp; 3413 struct alc_txdesc *txd; 3414 uint32_t cons, prod; 3415 int prog; 3416 3417 ALC_LOCK_ASSERT(sc); 3418 3419 ifp = sc->alc_ifp; 3420 3421 if (sc->alc_cdata.alc_tx_cnt == 0) 3422 return; 3423 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3424 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3425 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3426 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3427 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3428 prod = sc->alc_rdata.alc_cmb->cons; 3429 } else { 3430 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3431 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3432 else { 3433 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3434 /* Assume we're using normal Tx priority queue. */ 3435 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3436 MBOX_TD_CONS_LO_IDX_SHIFT; 3437 } 3438 } 3439 cons = sc->alc_cdata.alc_tx_cons; 3440 /* 3441 * Go through our Tx list and free mbufs for those 3442 * frames which have been transmitted. 3443 */ 3444 for (prog = 0; cons != prod; prog++, 3445 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3446 if (sc->alc_cdata.alc_tx_cnt <= 0) 3447 break; 3448 prog++; 3449 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3450 sc->alc_cdata.alc_tx_cnt--; 3451 txd = &sc->alc_cdata.alc_txdesc[cons]; 3452 if (txd->tx_m != NULL) { 3453 /* Reclaim transmitted mbufs. */ 3454 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3455 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3456 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3457 txd->tx_dmamap); 3458 m_freem(txd->tx_m); 3459 txd->tx_m = NULL; 3460 } 3461 } 3462 3463 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3464 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3465 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3466 sc->alc_cdata.alc_tx_cons = cons; 3467 /* 3468 * Unarm watchdog timer only when there is no pending 3469 * frames in Tx queue. 3470 */ 3471 if (sc->alc_cdata.alc_tx_cnt == 0) 3472 sc->alc_watchdog_timer = 0; 3473} 3474 3475static int 3476alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3477{ 3478 struct mbuf *m; 3479 bus_dma_segment_t segs[1]; 3480 bus_dmamap_t map; 3481 int nsegs; 3482 3483 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3484 if (m == NULL) 3485 return (ENOBUFS); 3486 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3487#ifndef __NO_STRICT_ALIGNMENT 3488 m_adj(m, sizeof(uint64_t)); 3489#endif 3490 3491 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3492 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3493 m_freem(m); 3494 return (ENOBUFS); 3495 } 3496 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3497 3498 if (rxd->rx_m != NULL) { 3499 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3500 BUS_DMASYNC_POSTREAD); 3501 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3502 } 3503 map = rxd->rx_dmamap; 3504 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3505 sc->alc_cdata.alc_rx_sparemap = map; 3506 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3507 BUS_DMASYNC_PREREAD); 3508 rxd->rx_m = m; 3509 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3510 return (0); 3511} 3512 3513static int 3514alc_rxintr(struct alc_softc *sc, int count) 3515{ 3516 struct ifnet *ifp; 3517 struct rx_rdesc *rrd; 3518 uint32_t nsegs, status; 3519 int rr_cons, prog; 3520 3521 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3522 sc->alc_cdata.alc_rr_ring_map, 3523 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3524 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3525 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3526 rr_cons = sc->alc_cdata.alc_rr_cons; 3527 ifp = sc->alc_ifp; 3528 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 3529 if (count-- <= 0) 3530 break; 3531 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3532 status = le32toh(rrd->status); 3533 if ((status & RRD_VALID) == 0) 3534 break; 3535 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3536 if (nsegs == 0) { 3537 /* This should not happen! */ 3538 device_printf(sc->alc_dev, 3539 "unexpected segment count -- resetting\n"); 3540 return (EIO); 3541 } 3542 alc_rxeof(sc, rrd); 3543 /* Clear Rx return status. */ 3544 rrd->status = 0; 3545 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3546 sc->alc_cdata.alc_rx_cons += nsegs; 3547 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3548 prog += nsegs; 3549 } 3550 3551 if (prog > 0) { 3552 /* Update the consumer index. */ 3553 sc->alc_cdata.alc_rr_cons = rr_cons; 3554 /* Sync Rx return descriptors. */ 3555 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3556 sc->alc_cdata.alc_rr_ring_map, 3557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3558 /* 3559 * Sync updated Rx descriptors such that controller see 3560 * modified buffer addresses. 3561 */ 3562 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3563 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3564 /* 3565 * Let controller know availability of new Rx buffers. 3566 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3567 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3568 * only when Rx buffer pre-fetching is required. In 3569 * addition we already set ALC_RX_RD_FREE_THRESH to 3570 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3571 * it still seems that pre-fetching needs more 3572 * experimentation. 3573 */ 3574 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3575 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3576 (uint16_t)sc->alc_cdata.alc_rx_cons); 3577 else 3578 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3579 sc->alc_cdata.alc_rx_cons); 3580 } 3581 3582 return (count > 0 ? 0 : EAGAIN); 3583} 3584 3585#ifndef __NO_STRICT_ALIGNMENT 3586static struct mbuf * 3587alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 3588{ 3589 struct mbuf *n; 3590 int i; 3591 uint16_t *src, *dst; 3592 3593 src = mtod(m, uint16_t *); 3594 dst = src - 3; 3595 3596 if (m->m_next == NULL) { 3597 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3598 *dst++ = *src++; 3599 m->m_data -= 6; 3600 return (m); 3601 } 3602 /* 3603 * Append a new mbuf to received mbuf chain and copy ethernet 3604 * header from the mbuf chain. This can save lots of CPU 3605 * cycles for jumbo frame. 3606 */ 3607 MGETHDR(n, M_NOWAIT, MT_DATA); 3608 if (n == NULL) { 3609 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3610 m_freem(m); 3611 return (NULL); 3612 } 3613 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3614 m->m_data += ETHER_HDR_LEN; 3615 m->m_len -= ETHER_HDR_LEN; 3616 n->m_len = ETHER_HDR_LEN; 3617 M_MOVE_PKTHDR(n, m); 3618 n->m_next = m; 3619 return (n); 3620} 3621#endif 3622 3623/* Receive a frame. */ 3624static void 3625alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3626{ 3627 struct alc_rxdesc *rxd; 3628 struct ifnet *ifp; 3629 struct mbuf *mp, *m; 3630 uint32_t rdinfo, status, vtag; 3631 int count, nsegs, rx_cons; 3632 3633 ifp = sc->alc_ifp; 3634 status = le32toh(rrd->status); 3635 rdinfo = le32toh(rrd->rdinfo); 3636 rx_cons = RRD_RD_IDX(rdinfo); 3637 nsegs = RRD_RD_CNT(rdinfo); 3638 3639 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3640 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3641 /* 3642 * We want to pass the following frames to upper 3643 * layer regardless of error status of Rx return 3644 * ring. 3645 * 3646 * o IP/TCP/UDP checksum is bad. 3647 * o frame length and protocol specific length 3648 * does not match. 3649 * 3650 * Force network stack compute checksum for 3651 * errored frames. 3652 */ 3653 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3654 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3655 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3656 return; 3657 } 3658 3659 for (count = 0; count < nsegs; count++, 3660 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3661 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3662 mp = rxd->rx_m; 3663 /* Add a new receive buffer to the ring. */ 3664 if (alc_newbuf(sc, rxd) != 0) { 3665 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3666 /* Reuse Rx buffers. */ 3667 if (sc->alc_cdata.alc_rxhead != NULL) 3668 m_freem(sc->alc_cdata.alc_rxhead); 3669 break; 3670 } 3671 3672 /* 3673 * Assume we've received a full sized frame. 3674 * Actual size is fixed when we encounter the end of 3675 * multi-segmented frame. 3676 */ 3677 mp->m_len = sc->alc_buf_size; 3678 3679 /* Chain received mbufs. */ 3680 if (sc->alc_cdata.alc_rxhead == NULL) { 3681 sc->alc_cdata.alc_rxhead = mp; 3682 sc->alc_cdata.alc_rxtail = mp; 3683 } else { 3684 mp->m_flags &= ~M_PKTHDR; 3685 sc->alc_cdata.alc_rxprev_tail = 3686 sc->alc_cdata.alc_rxtail; 3687 sc->alc_cdata.alc_rxtail->m_next = mp; 3688 sc->alc_cdata.alc_rxtail = mp; 3689 } 3690 3691 if (count == nsegs - 1) { 3692 /* Last desc. for this frame. */ 3693 m = sc->alc_cdata.alc_rxhead; 3694 m->m_flags |= M_PKTHDR; 3695 /* 3696 * It seems that L1C/L2C controller has no way 3697 * to tell hardware to strip CRC bytes. 3698 */ 3699 m->m_pkthdr.len = 3700 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3701 if (nsegs > 1) { 3702 /* Set last mbuf size. */ 3703 mp->m_len = sc->alc_cdata.alc_rxlen - 3704 (nsegs - 1) * sc->alc_buf_size; 3705 /* Remove the CRC bytes in chained mbufs. */ 3706 if (mp->m_len <= ETHER_CRC_LEN) { 3707 sc->alc_cdata.alc_rxtail = 3708 sc->alc_cdata.alc_rxprev_tail; 3709 sc->alc_cdata.alc_rxtail->m_len -= 3710 (ETHER_CRC_LEN - mp->m_len); 3711 sc->alc_cdata.alc_rxtail->m_next = NULL; 3712 m_freem(mp); 3713 } else { 3714 mp->m_len -= ETHER_CRC_LEN; 3715 } 3716 } else 3717 m->m_len = m->m_pkthdr.len; 3718 m->m_pkthdr.rcvif = ifp; 3719 /* 3720 * Due to hardware bugs, Rx checksum offloading 3721 * was intentionally disabled. 3722 */ 3723 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3724 (status & RRD_VLAN_TAG) != 0) { 3725 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3726 m->m_pkthdr.ether_vtag = ntohs(vtag); 3727 m->m_flags |= M_VLANTAG; 3728 } 3729#ifndef __NO_STRICT_ALIGNMENT 3730 m = alc_fixup_rx(ifp, m); 3731 if (m != NULL) 3732#endif 3733 { 3734 /* Pass it on. */ 3735 ALC_UNLOCK(sc); 3736 (*ifp->if_input)(ifp, m); 3737 ALC_LOCK(sc); 3738 } 3739 } 3740 } 3741 /* Reset mbuf chains. */ 3742 ALC_RXCHAIN_RESET(sc); 3743} 3744 3745static void 3746alc_tick(void *arg) 3747{ 3748 struct alc_softc *sc; 3749 struct mii_data *mii; 3750 3751 sc = (struct alc_softc *)arg; 3752 3753 ALC_LOCK_ASSERT(sc); 3754 3755 mii = device_get_softc(sc->alc_miibus); 3756 mii_tick(mii); 3757 alc_stats_update(sc); 3758 /* 3759 * alc(4) does not rely on Tx completion interrupts to reclaim 3760 * transferred buffers. Instead Tx completion interrupts are 3761 * used to hint for scheduling Tx task. So it's necessary to 3762 * release transmitted buffers by kicking Tx completion 3763 * handler. This limits the maximum reclamation delay to a hz. 3764 */ 3765 alc_txeof(sc); 3766 alc_watchdog(sc); 3767 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3768} 3769 3770static void 3771alc_osc_reset(struct alc_softc *sc) 3772{ 3773 uint32_t reg; 3774 3775 reg = CSR_READ_4(sc, ALC_MISC3); 3776 reg &= ~MISC3_25M_BY_SW; 3777 reg |= MISC3_25M_NOTO_INTNL; 3778 CSR_WRITE_4(sc, ALC_MISC3, reg); 3779 3780 reg = CSR_READ_4(sc, ALC_MISC); 3781 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3782 /* 3783 * Restore over-current protection default value. 3784 * This value could be reset by MAC reset. 3785 */ 3786 reg &= ~MISC_PSW_OCP_MASK; 3787 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3788 reg &= ~MISC_INTNLOSC_OPEN; 3789 CSR_WRITE_4(sc, ALC_MISC, reg); 3790 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3791 reg = CSR_READ_4(sc, ALC_MISC2); 3792 reg &= ~MISC2_CALB_START; 3793 CSR_WRITE_4(sc, ALC_MISC2, reg); 3794 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3795 3796 } else { 3797 reg &= ~MISC_INTNLOSC_OPEN; 3798 /* Disable isolate for revision A devices. */ 3799 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3800 reg &= ~MISC_ISO_ENB; 3801 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3802 CSR_WRITE_4(sc, ALC_MISC, reg); 3803 } 3804 3805 DELAY(20); 3806} 3807 3808static void 3809alc_reset(struct alc_softc *sc) 3810{ 3811 uint32_t pmcfg, reg; 3812 int i; 3813 3814 pmcfg = 0; 3815 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3816 /* Reset workaround. */ 3817 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3818 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3819 (sc->alc_rev & 0x01) != 0) { 3820 /* Disable L0s/L1s before reset. */ 3821 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3822 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3823 != 0) { 3824 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3825 PM_CFG_ASPM_L1_ENB); 3826 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3827 } 3828 } 3829 } 3830 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3831 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3832 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3833 3834 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3835 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3836 DELAY(10); 3837 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3838 break; 3839 } 3840 if (i == 0) 3841 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3842 } 3843 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3844 DELAY(10); 3845 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3846 break; 3847 } 3848 if (i == 0) 3849 device_printf(sc->alc_dev, "master reset timeout!\n"); 3850 3851 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3852 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3853 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3854 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3855 break; 3856 DELAY(10); 3857 } 3858 if (i == 0) 3859 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3860 3861 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3862 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3863 (sc->alc_rev & 0x01) != 0) { 3864 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3865 reg |= MASTER_CLK_SEL_DIS; 3866 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3867 /* Restore L0s/L1s config. */ 3868 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3869 != 0) 3870 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3871 } 3872 3873 alc_osc_reset(sc); 3874 reg = CSR_READ_4(sc, ALC_MISC3); 3875 reg &= ~MISC3_25M_BY_SW; 3876 reg |= MISC3_25M_NOTO_INTNL; 3877 CSR_WRITE_4(sc, ALC_MISC3, reg); 3878 reg = CSR_READ_4(sc, ALC_MISC); 3879 reg &= ~MISC_INTNLOSC_OPEN; 3880 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3881 reg &= ~MISC_ISO_ENB; 3882 CSR_WRITE_4(sc, ALC_MISC, reg); 3883 DELAY(20); 3884 } 3885 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3886 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3887 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3888 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3889 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3890 SERDES_PHY_CLK_SLOWDOWN); 3891} 3892 3893static void 3894alc_init(void *xsc) 3895{ 3896 struct alc_softc *sc; 3897 3898 sc = (struct alc_softc *)xsc; 3899 ALC_LOCK(sc); 3900 alc_init_locked(sc); 3901 ALC_UNLOCK(sc); 3902} 3903 3904static void 3905alc_init_locked(struct alc_softc *sc) 3906{ 3907 struct ifnet *ifp; 3908 struct mii_data *mii; 3909 uint8_t eaddr[ETHER_ADDR_LEN]; 3910 bus_addr_t paddr; 3911 uint32_t reg, rxf_hi, rxf_lo; 3912 3913 ALC_LOCK_ASSERT(sc); 3914 3915 ifp = sc->alc_ifp; 3916 mii = device_get_softc(sc->alc_miibus); 3917 3918 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3919 return; 3920 /* 3921 * Cancel any pending I/O. 3922 */ 3923 alc_stop(sc); 3924 /* 3925 * Reset the chip to a known state. 3926 */ 3927 alc_reset(sc); 3928 3929 /* Initialize Rx descriptors. */ 3930 if (alc_init_rx_ring(sc) != 0) { 3931 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3932 alc_stop(sc); 3933 return; 3934 } 3935 alc_init_rr_ring(sc); 3936 alc_init_tx_ring(sc); 3937 alc_init_cmb(sc); 3938 alc_init_smb(sc); 3939 3940 /* Enable all clocks. */ 3941 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3942 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3943 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3944 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3945 CLK_GATING_RXMAC_ENB); 3946 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3947 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3948 IDLE_DECISN_TIMER_DEFAULT_1MS); 3949 } else 3950 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3951 3952 /* Reprogram the station address. */ 3953 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3954 CSR_WRITE_4(sc, ALC_PAR0, 3955 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3956 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3957 /* 3958 * Clear WOL status and disable all WOL feature as WOL 3959 * would interfere Rx operation under normal environments. 3960 */ 3961 CSR_READ_4(sc, ALC_WOL_CFG); 3962 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3963 /* Set Tx descriptor base addresses. */ 3964 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3965 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3966 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3967 /* We don't use high priority ring. */ 3968 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3969 /* Set Tx descriptor counter. */ 3970 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3971 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3972 /* Set Rx descriptor base addresses. */ 3973 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3974 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3975 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3976 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3977 /* We use one Rx ring. */ 3978 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3979 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3980 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3981 } 3982 /* Set Rx descriptor counter. */ 3983 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3984 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3985 3986 /* 3987 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3988 * if it do not fit the buffer size. Rx return descriptor holds 3989 * a counter that indicates how many fragments were made by the 3990 * hardware. The buffer size should be multiple of 8 bytes. 3991 * Since hardware has limit on the size of buffer size, always 3992 * use the maximum value. 3993 * For strict-alignment architectures make sure to reduce buffer 3994 * size by 8 bytes to make room for alignment fixup. 3995 */ 3996#ifndef __NO_STRICT_ALIGNMENT 3997 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3998#else 3999 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4000#endif 4001 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4002 4003 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4004 /* Set Rx return descriptor base addresses. */ 4005 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4006 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4007 /* We use one Rx return ring. */ 4008 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4009 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4010 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4011 } 4012 /* Set Rx return descriptor counter. */ 4013 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4014 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4015 paddr = sc->alc_rdata.alc_cmb_paddr; 4016 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4017 paddr = sc->alc_rdata.alc_smb_paddr; 4018 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4019 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4020 4021 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4022 /* Reconfigure SRAM - Vendor magic. */ 4023 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4024 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4025 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4026 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4027 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4028 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4029 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4030 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4031 } 4032 4033 /* Tell hardware that we're ready to load DMA blocks. */ 4034 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4035 4036 /* Configure interrupt moderation timer. */ 4037 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4038 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4039 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4040 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4041 /* 4042 * We don't want to automatic interrupt clear as task queue 4043 * for the interrupt should know interrupt status. 4044 */ 4045 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4046 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4047 reg |= MASTER_SA_TIMER_ENB; 4048 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4049 reg |= MASTER_IM_RX_TIMER_ENB; 4050 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4051 ALC_USECS(sc->alc_int_tx_mod) != 0) 4052 reg |= MASTER_IM_TX_TIMER_ENB; 4053 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4054 /* 4055 * Disable interrupt re-trigger timer. We don't want automatic 4056 * re-triggering of un-ACKed interrupts. 4057 */ 4058 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4059 /* Configure CMB. */ 4060 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4061 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4062 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4063 ALC_USECS(sc->alc_int_tx_mod)); 4064 } else { 4065 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4066 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4067 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4068 } else 4069 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4070 } 4071 /* 4072 * Hardware can be configured to issue SMB interrupt based 4073 * on programmed interval. Since there is a callout that is 4074 * invoked for every hz in driver we use that instead of 4075 * relying on periodic SMB interrupt. 4076 */ 4077 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4078 /* Clear MAC statistics. */ 4079 alc_stats_clear(sc); 4080 4081 /* 4082 * Always use maximum frame size that controller can support. 4083 * Otherwise received frames that has larger frame length 4084 * than alc(4) MTU would be silently dropped in hardware. This 4085 * would make path-MTU discovery hard as sender wouldn't get 4086 * any responses from receiver. alc(4) supports 4087 * multi-fragmented frames on Rx path so it has no issue on 4088 * assembling fragmented frames. Using maximum frame size also 4089 * removes the need to reinitialize hardware when interface 4090 * MTU configuration was changed. 4091 * 4092 * Be conservative in what you do, be liberal in what you 4093 * accept from others - RFC 793. 4094 */ 4095 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4096 4097 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4098 /* Disable header split(?) */ 4099 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4100 4101 /* Configure IPG/IFG parameters. */ 4102 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4103 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4104 IPG_IFG_IPGT_MASK) | 4105 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4106 IPG_IFG_MIFG_MASK) | 4107 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4108 IPG_IFG_IPG1_MASK) | 4109 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4110 IPG_IFG_IPG2_MASK)); 4111 /* Set parameters for half-duplex media. */ 4112 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4113 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4114 HDPX_CFG_LCOL_MASK) | 4115 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4116 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4117 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4118 HDPX_CFG_ABEBT_MASK) | 4119 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4120 HDPX_CFG_JAMIPG_MASK)); 4121 } 4122 4123 /* 4124 * Set TSO/checksum offload threshold. For frames that is 4125 * larger than this threshold, hardware wouldn't do 4126 * TSO/checksum offloading. 4127 */ 4128 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4129 TSO_OFFLOAD_THRESH_MASK; 4130 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4131 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4132 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4133 /* Configure TxQ. */ 4134 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4135 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4136 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4137 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4138 reg >>= 1; 4139 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4140 TXQ_CFG_TD_BURST_MASK; 4141 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4142 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4143 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4144 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4145 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4146 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4147 HQTD_CFG_BURST_ENB); 4148 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4149 reg = WRR_PRI_RESTRICT_NONE; 4150 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4151 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4152 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4153 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4154 CSR_WRITE_4(sc, ALC_WRR, reg); 4155 } else { 4156 /* Configure Rx free descriptor pre-fetching. */ 4157 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4158 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4159 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4160 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4161 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4162 } 4163 4164 /* 4165 * Configure flow control parameters. 4166 * XON : 80% of Rx FIFO 4167 * XOFF : 30% of Rx FIFO 4168 */ 4169 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4170 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4171 reg &= SRAM_RX_FIFO_LEN_MASK; 4172 reg *= 8; 4173 if (reg > 8 * 1024) 4174 reg -= RX_FIFO_PAUSE_816X_RSVD; 4175 else 4176 reg -= RX_BUF_SIZE_MAX; 4177 reg /= 8; 4178 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4179 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4180 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4181 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4182 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4183 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4184 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4185 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4186 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4187 rxf_hi = (reg * 8) / 10; 4188 rxf_lo = (reg * 3) / 10; 4189 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4190 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4191 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4192 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4193 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4194 } 4195 4196 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4197 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4198 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4199 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4200 } 4201 4202 /* Configure RxQ. */ 4203 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4204 RXQ_CFG_RD_BURST_MASK; 4205 reg |= RXQ_CFG_RSS_MODE_DIS; 4206 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4207 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4208 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4209 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4210 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4211 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4212 } else { 4213 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4214 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4215 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4216 } 4217 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4218 4219 /* Configure DMA parameters. */ 4220 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4221 reg |= sc->alc_rcb; 4222 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4223 reg |= DMA_CFG_CMB_ENB; 4224 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4225 reg |= DMA_CFG_SMB_ENB; 4226 else 4227 reg |= DMA_CFG_SMB_DIS; 4228 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4229 DMA_CFG_RD_BURST_SHIFT; 4230 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4231 DMA_CFG_WR_BURST_SHIFT; 4232 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4233 DMA_CFG_RD_DELAY_CNT_MASK; 4234 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4235 DMA_CFG_WR_DELAY_CNT_MASK; 4236 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4237 switch (AR816X_REV(sc->alc_rev)) { 4238 case AR816X_REV_A0: 4239 case AR816X_REV_A1: 4240 reg |= DMA_CFG_RD_CHNL_SEL_2; 4241 break; 4242 case AR816X_REV_B0: 4243 /* FALLTHROUGH */ 4244 default: 4245 reg |= DMA_CFG_RD_CHNL_SEL_4; 4246 break; 4247 } 4248 } 4249 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4250 4251 /* 4252 * Configure Tx/Rx MACs. 4253 * - Auto-padding for short frames. 4254 * - Enable CRC generation. 4255 * Actual reconfiguration of MAC for resolved speed/duplex 4256 * is followed after detection of link establishment. 4257 * AR813x/AR815x always does checksum computation regardless 4258 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4259 * have bug in protocol field in Rx return structure so 4260 * these controllers can't handle fragmented frames. Disable 4261 * Rx checksum offloading until there is a newer controller 4262 * that has sane implementation. 4263 */ 4264 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4265 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4266 MAC_CFG_PREAMBLE_MASK); 4267 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4268 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4269 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4270 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4271 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4272 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4273 reg |= MAC_CFG_SPEED_10_100; 4274 else 4275 reg |= MAC_CFG_SPEED_1000; 4276 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4277 4278 /* Set up the receive filter. */ 4279 alc_rxfilter(sc); 4280 alc_rxvlan(sc); 4281 4282 /* Acknowledge all pending interrupts and clear it. */ 4283 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4284 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4285 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4286 4287 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4288 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4289 4290 sc->alc_flags &= ~ALC_FLAG_LINK; 4291 /* Switch to the current media. */ 4292 alc_mediachange_locked(sc); 4293 4294 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4295} 4296 4297static void 4298alc_stop(struct alc_softc *sc) 4299{ 4300 struct ifnet *ifp; 4301 struct alc_txdesc *txd; 4302 struct alc_rxdesc *rxd; 4303 uint32_t reg; 4304 int i; 4305 4306 ALC_LOCK_ASSERT(sc); 4307 /* 4308 * Mark the interface down and cancel the watchdog timer. 4309 */ 4310 ifp = sc->alc_ifp; 4311 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4312 sc->alc_flags &= ~ALC_FLAG_LINK; 4313 callout_stop(&sc->alc_tick_ch); 4314 sc->alc_watchdog_timer = 0; 4315 alc_stats_update(sc); 4316 /* Disable interrupts. */ 4317 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4318 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4319 /* Disable DMA. */ 4320 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4321 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4322 reg |= DMA_CFG_SMB_DIS; 4323 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4324 DELAY(1000); 4325 /* Stop Rx/Tx MACs. */ 4326 alc_stop_mac(sc); 4327 /* Disable interrupts which might be touched in taskq handler. */ 4328 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4329 /* Disable L0s/L1s */ 4330 alc_aspm(sc, 0, IFM_UNKNOWN); 4331 /* Reclaim Rx buffers that have been processed. */ 4332 if (sc->alc_cdata.alc_rxhead != NULL) 4333 m_freem(sc->alc_cdata.alc_rxhead); 4334 ALC_RXCHAIN_RESET(sc); 4335 /* 4336 * Free Tx/Rx mbufs still in the queues. 4337 */ 4338 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4339 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4340 if (rxd->rx_m != NULL) { 4341 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4342 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4343 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4344 rxd->rx_dmamap); 4345 m_freem(rxd->rx_m); 4346 rxd->rx_m = NULL; 4347 } 4348 } 4349 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4350 txd = &sc->alc_cdata.alc_txdesc[i]; 4351 if (txd->tx_m != NULL) { 4352 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4353 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4354 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4355 txd->tx_dmamap); 4356 m_freem(txd->tx_m); 4357 txd->tx_m = NULL; 4358 } 4359 } 4360} 4361 4362static void 4363alc_stop_mac(struct alc_softc *sc) 4364{ 4365 uint32_t reg; 4366 int i; 4367 4368 alc_stop_queue(sc); 4369 /* Disable Rx/Tx MAC. */ 4370 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4371 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4372 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4373 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4374 } 4375 for (i = ALC_TIMEOUT; i > 0; i--) { 4376 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4377 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4378 break; 4379 DELAY(10); 4380 } 4381 if (i == 0) 4382 device_printf(sc->alc_dev, 4383 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4384} 4385 4386static void 4387alc_start_queue(struct alc_softc *sc) 4388{ 4389 uint32_t qcfg[] = { 4390 0, 4391 RXQ_CFG_QUEUE0_ENB, 4392 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4393 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4394 RXQ_CFG_ENB 4395 }; 4396 uint32_t cfg; 4397 4398 ALC_LOCK_ASSERT(sc); 4399 4400 /* Enable RxQ. */ 4401 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4402 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4403 cfg &= ~RXQ_CFG_ENB; 4404 cfg |= qcfg[1]; 4405 } else 4406 cfg |= RXQ_CFG_QUEUE0_ENB; 4407 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4408 /* Enable TxQ. */ 4409 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4410 cfg |= TXQ_CFG_ENB; 4411 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4412} 4413 4414static void 4415alc_stop_queue(struct alc_softc *sc) 4416{ 4417 uint32_t reg; 4418 int i; 4419 4420 /* Disable RxQ. */ 4421 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4422 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4423 if ((reg & RXQ_CFG_ENB) != 0) { 4424 reg &= ~RXQ_CFG_ENB; 4425 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4426 } 4427 } else { 4428 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4429 reg &= ~RXQ_CFG_QUEUE0_ENB; 4430 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4431 } 4432 } 4433 /* Disable TxQ. */ 4434 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4435 if ((reg & TXQ_CFG_ENB) != 0) { 4436 reg &= ~TXQ_CFG_ENB; 4437 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4438 } 4439 DELAY(40); 4440 for (i = ALC_TIMEOUT; i > 0; i--) { 4441 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4442 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4443 break; 4444 DELAY(10); 4445 } 4446 if (i == 0) 4447 device_printf(sc->alc_dev, 4448 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4449} 4450 4451static void 4452alc_init_tx_ring(struct alc_softc *sc) 4453{ 4454 struct alc_ring_data *rd; 4455 struct alc_txdesc *txd; 4456 int i; 4457 4458 ALC_LOCK_ASSERT(sc); 4459 4460 sc->alc_cdata.alc_tx_prod = 0; 4461 sc->alc_cdata.alc_tx_cons = 0; 4462 sc->alc_cdata.alc_tx_cnt = 0; 4463 4464 rd = &sc->alc_rdata; 4465 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4466 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4467 txd = &sc->alc_cdata.alc_txdesc[i]; 4468 txd->tx_m = NULL; 4469 } 4470 4471 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4472 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4473} 4474 4475static int 4476alc_init_rx_ring(struct alc_softc *sc) 4477{ 4478 struct alc_ring_data *rd; 4479 struct alc_rxdesc *rxd; 4480 int i; 4481 4482 ALC_LOCK_ASSERT(sc); 4483 4484 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4485 sc->alc_morework = 0; 4486 rd = &sc->alc_rdata; 4487 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4488 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4489 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4490 rxd->rx_m = NULL; 4491 rxd->rx_desc = &rd->alc_rx_ring[i]; 4492 if (alc_newbuf(sc, rxd) != 0) 4493 return (ENOBUFS); 4494 } 4495 4496 /* 4497 * Since controller does not update Rx descriptors, driver 4498 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4499 * is enough to ensure coherence. 4500 */ 4501 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4502 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4503 /* Let controller know availability of new Rx buffers. */ 4504 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4505 4506 return (0); 4507} 4508 4509static void 4510alc_init_rr_ring(struct alc_softc *sc) 4511{ 4512 struct alc_ring_data *rd; 4513 4514 ALC_LOCK_ASSERT(sc); 4515 4516 sc->alc_cdata.alc_rr_cons = 0; 4517 ALC_RXCHAIN_RESET(sc); 4518 4519 rd = &sc->alc_rdata; 4520 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4521 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4522 sc->alc_cdata.alc_rr_ring_map, 4523 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4524} 4525 4526static void 4527alc_init_cmb(struct alc_softc *sc) 4528{ 4529 struct alc_ring_data *rd; 4530 4531 ALC_LOCK_ASSERT(sc); 4532 4533 rd = &sc->alc_rdata; 4534 bzero(rd->alc_cmb, ALC_CMB_SZ); 4535 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4536 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4537} 4538 4539static void 4540alc_init_smb(struct alc_softc *sc) 4541{ 4542 struct alc_ring_data *rd; 4543 4544 ALC_LOCK_ASSERT(sc); 4545 4546 rd = &sc->alc_rdata; 4547 bzero(rd->alc_smb, ALC_SMB_SZ); 4548 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4549 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4550} 4551 4552static void 4553alc_rxvlan(struct alc_softc *sc) 4554{ 4555 struct ifnet *ifp; 4556 uint32_t reg; 4557 4558 ALC_LOCK_ASSERT(sc); 4559 4560 ifp = sc->alc_ifp; 4561 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4562 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4563 reg |= MAC_CFG_VLAN_TAG_STRIP; 4564 else 4565 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4566 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4567} 4568 4569static void 4570alc_rxfilter(struct alc_softc *sc) 4571{ 4572 struct ifnet *ifp; 4573 struct ifmultiaddr *ifma; 4574 uint32_t crc; 4575 uint32_t mchash[2]; 4576 uint32_t rxcfg; 4577 4578 ALC_LOCK_ASSERT(sc); 4579 4580 ifp = sc->alc_ifp; 4581 4582 bzero(mchash, sizeof(mchash)); 4583 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4584 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4585 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4586 rxcfg |= MAC_CFG_BCAST; 4587 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4588 if ((ifp->if_flags & IFF_PROMISC) != 0) 4589 rxcfg |= MAC_CFG_PROMISC; 4590 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4591 rxcfg |= MAC_CFG_ALLMULTI; 4592 mchash[0] = 0xFFFFFFFF; 4593 mchash[1] = 0xFFFFFFFF; 4594 goto chipit; 4595 } 4596 4597 if_maddr_rlock(ifp); 4598 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 4599 if (ifma->ifma_addr->sa_family != AF_LINK) 4600 continue; 4601 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 4602 ifma->ifma_addr), ETHER_ADDR_LEN); 4603 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4604 } 4605 if_maddr_runlock(ifp); 4606 4607chipit: 4608 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4609 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4610 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4611} 4612 4613static int 4614sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4615{ 4616 int error, value; 4617 4618 if (arg1 == NULL) 4619 return (EINVAL); 4620 value = *(int *)arg1; 4621 error = sysctl_handle_int(oidp, &value, 0, req); 4622 if (error || req->newptr == NULL) 4623 return (error); 4624 if (value < low || value > high) 4625 return (EINVAL); 4626 *(int *)arg1 = value; 4627 4628 return (0); 4629} 4630 4631static int 4632sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4633{ 4634 return (sysctl_int_range(oidp, arg1, arg2, req, 4635 ALC_PROC_MIN, ALC_PROC_MAX)); 4636} 4637 4638static int 4639sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4640{ 4641 4642 return (sysctl_int_range(oidp, arg1, arg2, req, 4643 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4644} 4645