ahci.c revision 331493
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/11/sys/dev/ahci/ahci.c 331493 2018-03-24 18:42:45Z ian $"); 31 32#include <sys/param.h> 33#include <sys/module.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/conf.h> 38#include <sys/endian.h> 39#include <sys/malloc.h> 40#include <sys/lock.h> 41#include <sys/mutex.h> 42#include <machine/stdarg.h> 43#include <machine/resource.h> 44#include <machine/bus.h> 45#include <sys/rman.h> 46#include "ahci.h" 47 48#include <cam/cam.h> 49#include <cam/cam_ccb.h> 50#include <cam/cam_sim.h> 51#include <cam/cam_xpt_sim.h> 52#include <cam/cam_debug.h> 53 54/* local prototypes */ 55static void ahci_intr(void *data); 56static void ahci_intr_one(void *data); 57static void ahci_intr_one_edge(void *data); 58static int ahci_ch_init(device_t dev); 59static int ahci_ch_deinit(device_t dev); 60static int ahci_ch_suspend(device_t dev); 61static int ahci_ch_resume(device_t dev); 62static void ahci_ch_pm(void *arg); 63static void ahci_ch_intr(void *arg); 64static void ahci_ch_intr_direct(void *arg); 65static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 66static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb); 67static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 68static void ahci_execute_transaction(struct ahci_slot *slot); 69static void ahci_timeout(struct ahci_slot *slot); 70static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 71static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 72static void ahci_dmainit(device_t dev); 73static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 74static void ahci_dmafini(device_t dev); 75static void ahci_slotsalloc(device_t dev); 76static void ahci_slotsfree(device_t dev); 77static void ahci_reset(struct ahci_channel *ch); 78static void ahci_start(struct ahci_channel *ch, int fbs); 79static void ahci_stop(struct ahci_channel *ch); 80static void ahci_clo(struct ahci_channel *ch); 81static void ahci_start_fr(struct ahci_channel *ch); 82static void ahci_stop_fr(struct ahci_channel *ch); 83 84static int ahci_sata_connect(struct ahci_channel *ch); 85static int ahci_sata_phy_reset(struct ahci_channel *ch); 86static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0); 87 88static void ahci_issue_recovery(struct ahci_channel *ch); 89static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb); 90static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb); 91 92static void ahciaction(struct cam_sim *sim, union ccb *ccb); 93static void ahcipoll(struct cam_sim *sim); 94 95static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 96 97#define recovery_type spriv_field0 98#define RECOVERY_NONE 0 99#define RECOVERY_READ_LOG 1 100#define RECOVERY_REQUEST_SENSE 2 101#define recovery_slot spriv_field1 102 103int 104ahci_ctlr_setup(device_t dev) 105{ 106 struct ahci_controller *ctlr = device_get_softc(dev); 107 /* Clear interrupts */ 108 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 109 /* Configure CCC */ 110 if (ctlr->ccc) { 111 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 112 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 113 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 114 (4 << AHCI_CCCC_CC_SHIFT) | 115 AHCI_CCCC_EN); 116 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 117 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 118 if (bootverbose) { 119 device_printf(dev, 120 "CCC with %dms/4cmd enabled on vector %d\n", 121 ctlr->ccc, ctlr->cccv); 122 } 123 } 124 /* Enable AHCI interrupts */ 125 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 126 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 127 return (0); 128} 129 130int 131ahci_ctlr_reset(device_t dev) 132{ 133 struct ahci_controller *ctlr = device_get_softc(dev); 134 int timeout; 135 136 /* Enable AHCI mode */ 137 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 138 /* Reset AHCI controller */ 139 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 140 for (timeout = 1000; timeout > 0; timeout--) { 141 DELAY(1000); 142 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 143 break; 144 } 145 if (timeout == 0) { 146 device_printf(dev, "AHCI controller reset failure\n"); 147 return (ENXIO); 148 } 149 /* Reenable AHCI mode */ 150 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 151 152 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) { 153 /* 154 * Restore capability field. 155 * This is write to a read-only register to restore its state. 156 * On fully standard-compliant hardware this is not needed and 157 * this operation shall not take place. See ahci_pci.c for 158 * platforms using this quirk. 159 */ 160 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps); 161 } 162 163 return (0); 164} 165 166 167int 168ahci_attach(device_t dev) 169{ 170 struct ahci_controller *ctlr = device_get_softc(dev); 171 int error, i, speed, unit; 172 uint32_t u, version; 173 device_t child; 174 175 ctlr->dev = dev; 176 ctlr->ccc = 0; 177 resource_int_value(device_get_name(dev), 178 device_get_unit(dev), "ccc", &ctlr->ccc); 179 180 /* Setup our own memory management for channels. */ 181 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 182 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 183 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 184 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 185 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 186 ahci_free_mem(dev); 187 return (error); 188 } 189 if ((error = rman_manage_region(&ctlr->sc_iomem, 190 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 191 ahci_free_mem(dev); 192 rman_fini(&ctlr->sc_iomem); 193 return (error); 194 } 195 /* Get the HW capabilities */ 196 version = ATA_INL(ctlr->r_mem, AHCI_VS); 197 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 198 if (version >= 0x00010200) 199 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 200 if (ctlr->caps & AHCI_CAP_EMS) 201 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 202 203 if (ctlr->quirks & AHCI_Q_FORCE_PI) { 204 /* 205 * Enable ports. 206 * The spec says that BIOS sets up bits corresponding to 207 * available ports. On platforms where this information 208 * is missing, the driver can define available ports on its own. 209 */ 210 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1; 211 int nmask = (1 << nports) - 1; 212 213 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask); 214 device_printf(dev, "Forcing PI to %d ports (mask = %x)\n", 215 nports, nmask); 216 } 217 218 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 219 220 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 221 if ((ctlr->quirks & AHCI_Q_ALTSIG) && 222 (ctlr->caps & AHCI_CAP_SPM) == 0) 223 ctlr->quirks |= AHCI_Q_NOBSYRES; 224 225 if (ctlr->quirks & AHCI_Q_1CH) { 226 ctlr->caps &= ~AHCI_CAP_NPMASK; 227 ctlr->ichannels &= 0x01; 228 } 229 if (ctlr->quirks & AHCI_Q_2CH) { 230 ctlr->caps &= ~AHCI_CAP_NPMASK; 231 ctlr->caps |= 1; 232 ctlr->ichannels &= 0x03; 233 } 234 if (ctlr->quirks & AHCI_Q_4CH) { 235 ctlr->caps &= ~AHCI_CAP_NPMASK; 236 ctlr->caps |= 3; 237 ctlr->ichannels &= 0x0f; 238 } 239 ctlr->channels = MAX(flsl(ctlr->ichannels), 240 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 241 if (ctlr->quirks & AHCI_Q_NOPMP) 242 ctlr->caps &= ~AHCI_CAP_SPM; 243 if (ctlr->quirks & AHCI_Q_NONCQ) 244 ctlr->caps &= ~AHCI_CAP_SNCQ; 245 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 246 ctlr->ccc = 0; 247 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 248 249 /* Create controller-wide DMA tag. */ 250 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 251 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 252 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 253 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 254 0, NULL, NULL, &ctlr->dma_tag)) { 255 ahci_free_mem(dev); 256 rman_fini(&ctlr->sc_iomem); 257 return (ENXIO); 258 } 259 260 ahci_ctlr_setup(dev); 261 262 /* Setup interrupts. */ 263 if ((error = ahci_setup_interrupt(dev)) != 0) { 264 bus_dma_tag_destroy(ctlr->dma_tag); 265 ahci_free_mem(dev); 266 rman_fini(&ctlr->sc_iomem); 267 return (error); 268 } 269 270 i = 0; 271 for (u = ctlr->ichannels; u != 0; u >>= 1) 272 i += (u & 1); 273 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 274 resource_int_value(device_get_name(dev), device_get_unit(dev), 275 "direct", &ctlr->direct); 276 /* Announce HW capabilities. */ 277 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 278 device_printf(dev, 279 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 280 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 281 ((version >> 4) & 0xf0) + (version & 0x0f), 282 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 283 ((speed == 1) ? "1.5":((speed == 2) ? "3": 284 ((speed == 3) ? "6":"?"))), 285 (ctlr->caps & AHCI_CAP_SPM) ? 286 "supported" : "not supported", 287 (ctlr->caps & AHCI_CAP_FBSS) ? 288 " with FBS" : ""); 289 if (ctlr->quirks != 0) { 290 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 291 AHCI_Q_BIT_STRING); 292 } 293 if (bootverbose) { 294 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 295 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 296 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 297 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 298 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 299 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 300 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 301 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 302 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 303 ((speed == 1) ? "1.5":((speed == 2) ? "3": 304 ((speed == 3) ? "6":"?")))); 305 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 306 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 307 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 308 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 309 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 310 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 311 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 312 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 313 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 314 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 315 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 316 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 317 } 318 if (bootverbose && version >= 0x00010200) { 319 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 320 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 321 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 322 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 323 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 324 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 325 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 326 } 327 /* Attach all channels on this controller */ 328 for (unit = 0; unit < ctlr->channels; unit++) { 329 child = device_add_child(dev, "ahcich", -1); 330 if (child == NULL) { 331 device_printf(dev, "failed to add channel device\n"); 332 continue; 333 } 334 device_set_ivars(child, (void *)(intptr_t)unit); 335 if ((ctlr->ichannels & (1 << unit)) == 0) 336 device_disable(child); 337 } 338 if (ctlr->caps & AHCI_CAP_EMS) { 339 child = device_add_child(dev, "ahciem", -1); 340 if (child == NULL) 341 device_printf(dev, "failed to add enclosure device\n"); 342 else 343 device_set_ivars(child, (void *)(intptr_t)-1); 344 } 345 bus_generic_attach(dev); 346 return (0); 347} 348 349int 350ahci_detach(device_t dev) 351{ 352 struct ahci_controller *ctlr = device_get_softc(dev); 353 int i; 354 355 /* Detach & delete all children */ 356 device_delete_children(dev); 357 358 /* Free interrupts. */ 359 for (i = 0; i < ctlr->numirqs; i++) { 360 if (ctlr->irqs[i].r_irq) { 361 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 362 ctlr->irqs[i].handle); 363 bus_release_resource(dev, SYS_RES_IRQ, 364 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 365 } 366 } 367 bus_dma_tag_destroy(ctlr->dma_tag); 368 /* Free memory. */ 369 rman_fini(&ctlr->sc_iomem); 370 ahci_free_mem(dev); 371 return (0); 372} 373 374void 375ahci_free_mem(device_t dev) 376{ 377 struct ahci_controller *ctlr = device_get_softc(dev); 378 379 /* Release memory resources */ 380 if (ctlr->r_mem) 381 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 382 if (ctlr->r_msix_table) 383 bus_release_resource(dev, SYS_RES_MEMORY, 384 ctlr->r_msix_tab_rid, ctlr->r_msix_table); 385 if (ctlr->r_msix_pba) 386 bus_release_resource(dev, SYS_RES_MEMORY, 387 ctlr->r_msix_pba_rid, ctlr->r_msix_pba); 388 389 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL; 390} 391 392int 393ahci_setup_interrupt(device_t dev) 394{ 395 struct ahci_controller *ctlr = device_get_softc(dev); 396 int i; 397 398 /* Check for single MSI vector fallback. */ 399 if (ctlr->numirqs > 1 && 400 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 401 device_printf(dev, "Falling back to one MSI\n"); 402 ctlr->numirqs = 1; 403 } 404 405 /* Ensure we don't overrun irqs. */ 406 if (ctlr->numirqs > AHCI_MAX_IRQS) { 407 device_printf(dev, "Too many irqs %d > %d (clamping)\n", 408 ctlr->numirqs, AHCI_MAX_IRQS); 409 ctlr->numirqs = AHCI_MAX_IRQS; 410 } 411 412 /* Allocate all IRQs. */ 413 for (i = 0; i < ctlr->numirqs; i++) { 414 ctlr->irqs[i].ctlr = ctlr; 415 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 416 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi) 417 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 418 else if (ctlr->numirqs == 1 || i >= ctlr->channels || 419 (ctlr->ccc && i == ctlr->cccv)) 420 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 421 else if (ctlr->channels > ctlr->numirqs && 422 i == ctlr->numirqs - 1) 423 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 424 else 425 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 426 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 427 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 428 device_printf(dev, "unable to map interrupt\n"); 429 return (ENXIO); 430 } 431 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 432 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 433 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 434 ahci_intr_one), 435 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 436 /* SOS XXX release r_irq */ 437 device_printf(dev, "unable to setup interrupt\n"); 438 return (ENXIO); 439 } 440 if (ctlr->numirqs > 1) { 441 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 442 ctlr->irqs[i].handle, 443 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 444 "ch%d" : "%d", i); 445 } 446 } 447 return (0); 448} 449 450/* 451 * Common case interrupt handler. 452 */ 453static void 454ahci_intr(void *data) 455{ 456 struct ahci_controller_irq *irq = data; 457 struct ahci_controller *ctlr = irq->ctlr; 458 u_int32_t is, ise = 0; 459 void *arg; 460 int unit; 461 462 if (irq->mode == AHCI_IRQ_MODE_ALL) { 463 unit = 0; 464 if (ctlr->ccc) 465 is = ctlr->ichannels; 466 else 467 is = ATA_INL(ctlr->r_mem, AHCI_IS); 468 } else { /* AHCI_IRQ_MODE_AFTER */ 469 unit = irq->r_irq_rid - 1; 470 is = ATA_INL(ctlr->r_mem, AHCI_IS); 471 is &= (0xffffffff << unit); 472 } 473 /* CCC interrupt is edge triggered. */ 474 if (ctlr->ccc) 475 ise = 1 << ctlr->cccv; 476 /* Some controllers have edge triggered IS. */ 477 if (ctlr->quirks & AHCI_Q_EDGEIS) 478 ise |= is; 479 if (ise != 0) 480 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 481 for (; unit < ctlr->channels; unit++) { 482 if ((is & (1 << unit)) != 0 && 483 (arg = ctlr->interrupt[unit].argument)) { 484 ctlr->interrupt[unit].function(arg); 485 } 486 } 487 /* AHCI declares level triggered IS. */ 488 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 489 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 490 ATA_RBL(ctlr->r_mem, AHCI_IS); 491} 492 493/* 494 * Simplified interrupt handler for multivector MSI mode. 495 */ 496static void 497ahci_intr_one(void *data) 498{ 499 struct ahci_controller_irq *irq = data; 500 struct ahci_controller *ctlr = irq->ctlr; 501 void *arg; 502 int unit; 503 504 unit = irq->r_irq_rid - 1; 505 if ((arg = ctlr->interrupt[unit].argument)) 506 ctlr->interrupt[unit].function(arg); 507 /* AHCI declares level triggered IS. */ 508 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 509 ATA_RBL(ctlr->r_mem, AHCI_IS); 510} 511 512static void 513ahci_intr_one_edge(void *data) 514{ 515 struct ahci_controller_irq *irq = data; 516 struct ahci_controller *ctlr = irq->ctlr; 517 void *arg; 518 int unit; 519 520 unit = irq->r_irq_rid - 1; 521 /* Some controllers have edge triggered IS. */ 522 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 523 if ((arg = ctlr->interrupt[unit].argument)) 524 ctlr->interrupt[unit].function(arg); 525 ATA_RBL(ctlr->r_mem, AHCI_IS); 526} 527 528struct resource * 529ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 530 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 531{ 532 struct ahci_controller *ctlr = device_get_softc(dev); 533 struct resource *res; 534 rman_res_t st; 535 int offset, size, unit; 536 537 unit = (intptr_t)device_get_ivars(child); 538 res = NULL; 539 switch (type) { 540 case SYS_RES_MEMORY: 541 if (unit >= 0) { 542 offset = AHCI_OFFSET + (unit << 7); 543 size = 128; 544 } else if (*rid == 0) { 545 offset = AHCI_EM_CTL; 546 size = 4; 547 } else { 548 offset = (ctlr->emloc & 0xffff0000) >> 14; 549 size = (ctlr->emloc & 0x0000ffff) << 2; 550 if (*rid != 1) { 551 if (*rid == 2 && (ctlr->capsem & 552 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 553 offset += size; 554 else 555 break; 556 } 557 } 558 st = rman_get_start(ctlr->r_mem); 559 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 560 st + offset + size - 1, size, RF_ACTIVE, child); 561 if (res) { 562 bus_space_handle_t bsh; 563 bus_space_tag_t bst; 564 bsh = rman_get_bushandle(ctlr->r_mem); 565 bst = rman_get_bustag(ctlr->r_mem); 566 bus_space_subregion(bst, bsh, offset, 128, &bsh); 567 rman_set_bushandle(res, bsh); 568 rman_set_bustag(res, bst); 569 } 570 break; 571 case SYS_RES_IRQ: 572 if (*rid == ATA_IRQ_RID) 573 res = ctlr->irqs[0].r_irq; 574 break; 575 } 576 return (res); 577} 578 579int 580ahci_release_resource(device_t dev, device_t child, int type, int rid, 581 struct resource *r) 582{ 583 584 switch (type) { 585 case SYS_RES_MEMORY: 586 rman_release_resource(r); 587 return (0); 588 case SYS_RES_IRQ: 589 if (rid != ATA_IRQ_RID) 590 return (ENOENT); 591 return (0); 592 } 593 return (EINVAL); 594} 595 596int 597ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 598 int flags, driver_filter_t *filter, driver_intr_t *function, 599 void *argument, void **cookiep) 600{ 601 struct ahci_controller *ctlr = device_get_softc(dev); 602 int unit = (intptr_t)device_get_ivars(child); 603 604 if (filter != NULL) { 605 printf("ahci.c: we cannot use a filter here\n"); 606 return (EINVAL); 607 } 608 ctlr->interrupt[unit].function = function; 609 ctlr->interrupt[unit].argument = argument; 610 return (0); 611} 612 613int 614ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 615 void *cookie) 616{ 617 struct ahci_controller *ctlr = device_get_softc(dev); 618 int unit = (intptr_t)device_get_ivars(child); 619 620 ctlr->interrupt[unit].function = NULL; 621 ctlr->interrupt[unit].argument = NULL; 622 return (0); 623} 624 625int 626ahci_print_child(device_t dev, device_t child) 627{ 628 int retval, channel; 629 630 retval = bus_print_child_header(dev, child); 631 channel = (int)(intptr_t)device_get_ivars(child); 632 if (channel >= 0) 633 retval += printf(" at channel %d", channel); 634 retval += bus_print_child_footer(dev, child); 635 return (retval); 636} 637 638int 639ahci_child_location_str(device_t dev, device_t child, char *buf, 640 size_t buflen) 641{ 642 int channel; 643 644 channel = (int)(intptr_t)device_get_ivars(child); 645 if (channel >= 0) 646 snprintf(buf, buflen, "channel=%d", channel); 647 return (0); 648} 649 650bus_dma_tag_t 651ahci_get_dma_tag(device_t dev, device_t child) 652{ 653 struct ahci_controller *ctlr = device_get_softc(dev); 654 655 return (ctlr->dma_tag); 656} 657 658static int 659ahci_ch_probe(device_t dev) 660{ 661 662 device_set_desc_copy(dev, "AHCI channel"); 663 return (BUS_PROBE_DEFAULT); 664} 665 666static int 667ahci_ch_attach(device_t dev) 668{ 669 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 670 struct ahci_channel *ch = device_get_softc(dev); 671 struct cam_devq *devq; 672 int rid, error, i, sata_rev = 0; 673 u_int32_t version; 674 675 ch->dev = dev; 676 ch->unit = (intptr_t)device_get_ivars(dev); 677 ch->caps = ctlr->caps; 678 ch->caps2 = ctlr->caps2; 679 ch->start = ctlr->ch_start; 680 ch->quirks = ctlr->quirks; 681 ch->vendorid = ctlr->vendorid; 682 ch->deviceid = ctlr->deviceid; 683 ch->subvendorid = ctlr->subvendorid; 684 ch->subdeviceid = ctlr->subdeviceid; 685 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 686 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 687 ch->pm_level = 0; 688 resource_int_value(device_get_name(dev), 689 device_get_unit(dev), "pm_level", &ch->pm_level); 690 STAILQ_INIT(&ch->doneq); 691 if (ch->pm_level > 3) 692 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 693 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 694 /* JMicron external ports (0) sometimes limited */ 695 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0) 696 sata_rev = 1; 697 if (ch->quirks & AHCI_Q_SATA2) 698 sata_rev = 2; 699 resource_int_value(device_get_name(dev), 700 device_get_unit(dev), "sata_rev", &sata_rev); 701 for (i = 0; i < 16; i++) { 702 ch->user[i].revision = sata_rev; 703 ch->user[i].mode = 0; 704 ch->user[i].bytecount = 8192; 705 ch->user[i].tags = ch->numslots; 706 ch->user[i].caps = 0; 707 ch->curr[i] = ch->user[i]; 708 if (ch->pm_level) { 709 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 710 CTS_SATA_CAPS_H_APST | 711 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 712 } 713 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 714 CTS_SATA_CAPS_H_AN; 715 } 716 rid = 0; 717 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 718 &rid, RF_ACTIVE))) 719 return (ENXIO); 720 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 721 version = ATA_INL(ctlr->r_mem, AHCI_VS); 722 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 723 ch->chcaps |= AHCI_P_CMD_FBSCP; 724 if (ch->caps2 & AHCI_CAP2_SDS) 725 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP); 726 if (bootverbose) { 727 device_printf(dev, "Caps:%s%s%s%s%s%s\n", 728 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 729 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 730 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 731 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 732 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"", 733 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":""); 734 } 735 ahci_dmainit(dev); 736 ahci_slotsalloc(dev); 737 mtx_lock(&ch->mtx); 738 ahci_ch_init(dev); 739 rid = ATA_IRQ_RID; 740 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 741 &rid, RF_SHAREABLE | RF_ACTIVE))) { 742 device_printf(dev, "Unable to map interrupt\n"); 743 error = ENXIO; 744 goto err0; 745 } 746 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 747 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 748 ch, &ch->ih))) { 749 device_printf(dev, "Unable to setup interrupt\n"); 750 error = ENXIO; 751 goto err1; 752 } 753 /* Create the device queue for our SIM. */ 754 devq = cam_simq_alloc(ch->numslots); 755 if (devq == NULL) { 756 device_printf(dev, "Unable to allocate simq\n"); 757 error = ENOMEM; 758 goto err1; 759 } 760 /* Construct SIM entry */ 761 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 762 device_get_unit(dev), (struct mtx *)&ch->mtx, 763 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots), 764 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 765 devq); 766 if (ch->sim == NULL) { 767 cam_simq_free(devq); 768 device_printf(dev, "unable to allocate sim\n"); 769 error = ENOMEM; 770 goto err1; 771 } 772 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 773 device_printf(dev, "unable to register xpt bus\n"); 774 error = ENXIO; 775 goto err2; 776 } 777 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 778 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 779 device_printf(dev, "unable to create path\n"); 780 error = ENXIO; 781 goto err3; 782 } 783 if (ch->pm_level > 3) { 784 callout_reset(&ch->pm_timer, 785 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 786 ahci_ch_pm, ch); 787 } 788 mtx_unlock(&ch->mtx); 789 return (0); 790 791err3: 792 xpt_bus_deregister(cam_sim_path(ch->sim)); 793err2: 794 cam_sim_free(ch->sim, /*free_devq*/TRUE); 795err1: 796 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 797err0: 798 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 799 mtx_unlock(&ch->mtx); 800 mtx_destroy(&ch->mtx); 801 return (error); 802} 803 804static int 805ahci_ch_detach(device_t dev) 806{ 807 struct ahci_channel *ch = device_get_softc(dev); 808 809 mtx_lock(&ch->mtx); 810 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 811 /* Forget about reset. */ 812 if (ch->resetting) { 813 ch->resetting = 0; 814 xpt_release_simq(ch->sim, TRUE); 815 } 816 xpt_free_path(ch->path); 817 xpt_bus_deregister(cam_sim_path(ch->sim)); 818 cam_sim_free(ch->sim, /*free_devq*/TRUE); 819 mtx_unlock(&ch->mtx); 820 821 if (ch->pm_level > 3) 822 callout_drain(&ch->pm_timer); 823 callout_drain(&ch->reset_timer); 824 bus_teardown_intr(dev, ch->r_irq, ch->ih); 825 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 826 827 ahci_ch_deinit(dev); 828 ahci_slotsfree(dev); 829 ahci_dmafini(dev); 830 831 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 832 mtx_destroy(&ch->mtx); 833 return (0); 834} 835 836static int 837ahci_ch_init(device_t dev) 838{ 839 struct ahci_channel *ch = device_get_softc(dev); 840 uint64_t work; 841 842 /* Disable port interrupts */ 843 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 844 /* Setup work areas */ 845 work = ch->dma.work_bus + AHCI_CL_OFFSET; 846 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 847 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 848 work = ch->dma.rfis_bus; 849 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 850 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 851 /* Activate the channel and power/spin up device */ 852 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 853 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 854 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 855 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 856 ahci_start_fr(ch); 857 ahci_start(ch, 1); 858 return (0); 859} 860 861static int 862ahci_ch_deinit(device_t dev) 863{ 864 struct ahci_channel *ch = device_get_softc(dev); 865 866 /* Disable port interrupts. */ 867 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 868 /* Reset command register. */ 869 ahci_stop(ch); 870 ahci_stop_fr(ch); 871 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 872 /* Allow everything, including partial and slumber modes. */ 873 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 874 /* Request slumber mode transition and give some time to get there. */ 875 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 876 DELAY(100); 877 /* Disable PHY. */ 878 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 879 return (0); 880} 881 882static int 883ahci_ch_suspend(device_t dev) 884{ 885 struct ahci_channel *ch = device_get_softc(dev); 886 887 mtx_lock(&ch->mtx); 888 xpt_freeze_simq(ch->sim, 1); 889 /* Forget about reset. */ 890 if (ch->resetting) { 891 ch->resetting = 0; 892 callout_stop(&ch->reset_timer); 893 xpt_release_simq(ch->sim, TRUE); 894 } 895 while (ch->oslots) 896 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 897 ahci_ch_deinit(dev); 898 mtx_unlock(&ch->mtx); 899 return (0); 900} 901 902static int 903ahci_ch_resume(device_t dev) 904{ 905 struct ahci_channel *ch = device_get_softc(dev); 906 907 mtx_lock(&ch->mtx); 908 ahci_ch_init(dev); 909 ahci_reset(ch); 910 xpt_release_simq(ch->sim, TRUE); 911 mtx_unlock(&ch->mtx); 912 return (0); 913} 914 915devclass_t ahcich_devclass; 916static device_method_t ahcich_methods[] = { 917 DEVMETHOD(device_probe, ahci_ch_probe), 918 DEVMETHOD(device_attach, ahci_ch_attach), 919 DEVMETHOD(device_detach, ahci_ch_detach), 920 DEVMETHOD(device_suspend, ahci_ch_suspend), 921 DEVMETHOD(device_resume, ahci_ch_resume), 922 DEVMETHOD_END 923}; 924static driver_t ahcich_driver = { 925 "ahcich", 926 ahcich_methods, 927 sizeof(struct ahci_channel) 928}; 929DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL); 930 931struct ahci_dc_cb_args { 932 bus_addr_t maddr; 933 int error; 934}; 935 936static void 937ahci_dmainit(device_t dev) 938{ 939 struct ahci_channel *ch = device_get_softc(dev); 940 struct ahci_dc_cb_args dcba; 941 size_t rfsize; 942 943 /* Command area. */ 944 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 945 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 946 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 947 0, NULL, NULL, &ch->dma.work_tag)) 948 goto error; 949 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 950 BUS_DMA_ZERO, &ch->dma.work_map)) 951 goto error; 952 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 953 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 954 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 955 goto error; 956 } 957 ch->dma.work_bus = dcba.maddr; 958 /* FIS receive area. */ 959 if (ch->chcaps & AHCI_P_CMD_FBSCP) 960 rfsize = 4096; 961 else 962 rfsize = 256; 963 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 964 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 965 NULL, NULL, rfsize, 1, rfsize, 966 0, NULL, NULL, &ch->dma.rfis_tag)) 967 goto error; 968 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 969 &ch->dma.rfis_map)) 970 goto error; 971 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 972 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 973 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 974 goto error; 975 } 976 ch->dma.rfis_bus = dcba.maddr; 977 /* Data area. */ 978 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 979 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 980 NULL, NULL, 981 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 982 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 983 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 984 goto error; 985 } 986 return; 987 988error: 989 device_printf(dev, "WARNING - DMA initialization failed\n"); 990 ahci_dmafini(dev); 991} 992 993static void 994ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 995{ 996 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 997 998 if (!(dcba->error = error)) 999 dcba->maddr = segs[0].ds_addr; 1000} 1001 1002static void 1003ahci_dmafini(device_t dev) 1004{ 1005 struct ahci_channel *ch = device_get_softc(dev); 1006 1007 if (ch->dma.data_tag) { 1008 bus_dma_tag_destroy(ch->dma.data_tag); 1009 ch->dma.data_tag = NULL; 1010 } 1011 if (ch->dma.rfis_bus) { 1012 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1013 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1014 ch->dma.rfis_bus = 0; 1015 ch->dma.rfis = NULL; 1016 } 1017 if (ch->dma.work_bus) { 1018 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1019 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1020 ch->dma.work_bus = 0; 1021 ch->dma.work = NULL; 1022 } 1023 if (ch->dma.work_tag) { 1024 bus_dma_tag_destroy(ch->dma.work_tag); 1025 ch->dma.work_tag = NULL; 1026 } 1027} 1028 1029static void 1030ahci_slotsalloc(device_t dev) 1031{ 1032 struct ahci_channel *ch = device_get_softc(dev); 1033 int i; 1034 1035 /* Alloc and setup command/dma slots */ 1036 bzero(ch->slot, sizeof(ch->slot)); 1037 for (i = 0; i < ch->numslots; i++) { 1038 struct ahci_slot *slot = &ch->slot[i]; 1039 1040 slot->ch = ch; 1041 slot->slot = i; 1042 slot->state = AHCI_SLOT_EMPTY; 1043 slot->ccb = NULL; 1044 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1045 1046 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1047 device_printf(ch->dev, "FAILURE - create data_map\n"); 1048 } 1049} 1050 1051static void 1052ahci_slotsfree(device_t dev) 1053{ 1054 struct ahci_channel *ch = device_get_softc(dev); 1055 int i; 1056 1057 /* Free all dma slots */ 1058 for (i = 0; i < ch->numslots; i++) { 1059 struct ahci_slot *slot = &ch->slot[i]; 1060 1061 callout_drain(&slot->timeout); 1062 if (slot->dma.data_map) { 1063 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1064 slot->dma.data_map = NULL; 1065 } 1066 } 1067} 1068 1069static int 1070ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr) 1071{ 1072 1073 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1074 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1075 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1076 union ccb *ccb; 1077 1078 if (bootverbose) { 1079 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1080 device_printf(ch->dev, "CONNECT requested\n"); 1081 else 1082 device_printf(ch->dev, "DISCONNECT requested\n"); 1083 } 1084 ahci_reset(ch); 1085 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1086 return (0); 1087 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1088 cam_sim_path(ch->sim), 1089 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1090 xpt_free_ccb(ccb); 1091 return (0); 1092 } 1093 xpt_rescan(ccb); 1094 return (1); 1095 } 1096 return (0); 1097} 1098 1099static void 1100ahci_cpd_check_events(struct ahci_channel *ch) 1101{ 1102 u_int32_t status; 1103 union ccb *ccb; 1104 device_t dev; 1105 1106 if (ch->pm_level == 0) 1107 return; 1108 1109 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1110 if ((status & AHCI_P_CMD_CPD) == 0) 1111 return; 1112 1113 if (bootverbose) { 1114 dev = ch->dev; 1115 if (status & AHCI_P_CMD_CPS) { 1116 device_printf(dev, "COLD CONNECT requested\n"); 1117 } else 1118 device_printf(dev, "COLD DISCONNECT requested\n"); 1119 } 1120 ahci_reset(ch); 1121 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1122 return; 1123 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1124 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1125 xpt_free_ccb(ccb); 1126 return; 1127 } 1128 xpt_rescan(ccb); 1129} 1130 1131static void 1132ahci_notify_events(struct ahci_channel *ch, u_int32_t status) 1133{ 1134 struct cam_path *dpath; 1135 int i; 1136 1137 if (ch->caps & AHCI_CAP_SSNTF) 1138 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1139 if (bootverbose) 1140 device_printf(ch->dev, "SNTF 0x%04x\n", status); 1141 for (i = 0; i < 16; i++) { 1142 if ((status & (1 << i)) == 0) 1143 continue; 1144 if (xpt_create_path(&dpath, NULL, 1145 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1146 xpt_async(AC_SCSI_AEN, dpath, NULL); 1147 xpt_free_path(dpath); 1148 } 1149 } 1150} 1151 1152static void 1153ahci_done(struct ahci_channel *ch, union ccb *ccb) 1154{ 1155 1156 mtx_assert(&ch->mtx, MA_OWNED); 1157 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1158 ch->batch == 0) { 1159 xpt_done(ccb); 1160 return; 1161 } 1162 1163 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1164} 1165 1166static void 1167ahci_ch_intr(void *arg) 1168{ 1169 struct ahci_channel *ch = (struct ahci_channel *)arg; 1170 uint32_t istatus; 1171 1172 /* Read interrupt statuses. */ 1173 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1174 1175 mtx_lock(&ch->mtx); 1176 ahci_ch_intr_main(ch, istatus); 1177 mtx_unlock(&ch->mtx); 1178} 1179 1180static void 1181ahci_ch_intr_direct(void *arg) 1182{ 1183 struct ahci_channel *ch = (struct ahci_channel *)arg; 1184 struct ccb_hdr *ccb_h; 1185 uint32_t istatus; 1186 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq); 1187 1188 /* Read interrupt statuses. */ 1189 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1190 1191 mtx_lock(&ch->mtx); 1192 ch->batch = 1; 1193 ahci_ch_intr_main(ch, istatus); 1194 ch->batch = 0; 1195 /* 1196 * Prevent the possibility of issues caused by processing the queue 1197 * while unlocked below by moving the contents to a local queue. 1198 */ 1199 STAILQ_CONCAT(&tmp_doneq, &ch->doneq); 1200 mtx_unlock(&ch->mtx); 1201 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) { 1202 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe); 1203 xpt_done_direct((union ccb *)ccb_h); 1204 } 1205} 1206 1207static void 1208ahci_ch_pm(void *arg) 1209{ 1210 struct ahci_channel *ch = (struct ahci_channel *)arg; 1211 uint32_t work; 1212 1213 if (ch->numrslots != 0) 1214 return; 1215 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1216 if (ch->pm_level == 4) 1217 work |= AHCI_P_CMD_PARTIAL; 1218 else 1219 work |= AHCI_P_CMD_SLUMBER; 1220 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1221} 1222 1223static void 1224ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1225{ 1226 uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1227 enum ahci_err_type et; 1228 int i, ccs, port, reset = 0; 1229 1230 /* Clear interrupt statuses. */ 1231 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1232 /* Read command statuses. */ 1233 if (ch->numtslots != 0) 1234 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1235 else 1236 cstatus = 0; 1237 if (ch->numrslots != ch->numtslots) 1238 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1239 /* Read SNTF in one of possible ways. */ 1240 if ((istatus & AHCI_P_IX_SDB) && 1241 (ch->pm_present || ch->curr[0].atapi != 0)) { 1242 if (ch->caps & AHCI_CAP_SSNTF) 1243 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1244 else if (ch->fbs_enabled) { 1245 u_int8_t *fis = ch->dma.rfis + 0x58; 1246 1247 for (i = 0; i < 16; i++) { 1248 if (fis[1] & 0x80) { 1249 fis[1] &= 0x7f; 1250 sntf |= 1 << i; 1251 } 1252 fis += 256; 1253 } 1254 } else { 1255 u_int8_t *fis = ch->dma.rfis + 0x58; 1256 1257 if (fis[1] & 0x80) 1258 sntf = (1 << (fis[1] & 0x0f)); 1259 } 1260 } 1261 /* Process PHY events */ 1262 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1263 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1264 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1265 if (serr) { 1266 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1267 reset = ahci_phy_check_events(ch, serr); 1268 } 1269 } 1270 /* Process cold presence detection events */ 1271 if ((istatus & AHCI_P_IX_CPD) && !reset) 1272 ahci_cpd_check_events(ch); 1273 /* Process command errors */ 1274 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1275 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1276 if (ch->quirks & AHCI_Q_NOCCS) { 1277 /* 1278 * ASMedia chips sometimes report failed commands as 1279 * completed. Count all running commands as failed. 1280 */ 1281 cstatus |= ch->rslots; 1282 1283 /* They also report wrong CCS, so try to guess one. */ 1284 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1; 1285 } else { 1286 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & 1287 AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 1288 } 1289//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1290// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1291// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1292 port = -1; 1293 if (ch->fbs_enabled) { 1294 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1295 if (fbs & AHCI_P_FBS_SDE) { 1296 port = (fbs & AHCI_P_FBS_DWE) 1297 >> AHCI_P_FBS_DWE_SHIFT; 1298 } else { 1299 for (i = 0; i < 16; i++) { 1300 if (ch->numrslotspd[i] == 0) 1301 continue; 1302 if (port == -1) 1303 port = i; 1304 else if (port != i) { 1305 port = -2; 1306 break; 1307 } 1308 } 1309 } 1310 } 1311 err = ch->rslots & cstatus; 1312 } else { 1313 ccs = 0; 1314 err = 0; 1315 port = -1; 1316 } 1317 /* Complete all successful commands. */ 1318 ok = ch->rslots & ~cstatus; 1319 for (i = 0; i < ch->numslots; i++) { 1320 if ((ok >> i) & 1) 1321 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1322 } 1323 /* On error, complete the rest of commands with error statuses. */ 1324 if (err) { 1325 if (ch->frozen) { 1326 union ccb *fccb = ch->frozen; 1327 ch->frozen = NULL; 1328 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1329 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1330 xpt_freeze_devq(fccb->ccb_h.path, 1); 1331 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1332 } 1333 ahci_done(ch, fccb); 1334 } 1335 for (i = 0; i < ch->numslots; i++) { 1336 /* XXX: reqests in loading state. */ 1337 if (((err >> i) & 1) == 0) 1338 continue; 1339 if (port >= 0 && 1340 ch->slot[i].ccb->ccb_h.target_id != port) 1341 continue; 1342 if (istatus & AHCI_P_IX_TFE) { 1343 if (port != -2) { 1344 /* Task File Error */ 1345 if (ch->numtslotspd[ 1346 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1347 /* Untagged operation. */ 1348 if (i == ccs) 1349 et = AHCI_ERR_TFE; 1350 else 1351 et = AHCI_ERR_INNOCENT; 1352 } else { 1353 /* Tagged operation. */ 1354 et = AHCI_ERR_NCQ; 1355 } 1356 } else { 1357 et = AHCI_ERR_TFE; 1358 ch->fatalerr = 1; 1359 } 1360 } else if (istatus & AHCI_P_IX_IF) { 1361 if (ch->numtslots == 0 && i != ccs && port != -2) 1362 et = AHCI_ERR_INNOCENT; 1363 else 1364 et = AHCI_ERR_SATA; 1365 } else 1366 et = AHCI_ERR_INVALID; 1367 ahci_end_transaction(&ch->slot[i], et); 1368 } 1369 /* 1370 * We can't reinit port if there are some other 1371 * commands active, use resume to complete them. 1372 */ 1373 if (ch->rslots != 0 && !ch->recoverycmd) 1374 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1375 } 1376 /* Process NOTIFY events */ 1377 if (sntf) 1378 ahci_notify_events(ch, sntf); 1379} 1380 1381/* Must be called with channel locked. */ 1382static int 1383ahci_check_collision(struct ahci_channel *ch, union ccb *ccb) 1384{ 1385 int t = ccb->ccb_h.target_id; 1386 1387 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1388 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1389 /* Tagged command while we have no supported tag free. */ 1390 if (((~ch->oslots) & (0xffffffff >> (32 - 1391 ch->curr[t].tags))) == 0) 1392 return (1); 1393 /* If we have FBS */ 1394 if (ch->fbs_enabled) { 1395 /* Tagged command while untagged are active. */ 1396 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1397 return (1); 1398 } else { 1399 /* Tagged command while untagged are active. */ 1400 if (ch->numrslots != 0 && ch->numtslots == 0) 1401 return (1); 1402 /* Tagged command while tagged to other target is active. */ 1403 if (ch->numtslots != 0 && 1404 ch->taggedtarget != ccb->ccb_h.target_id) 1405 return (1); 1406 } 1407 } else { 1408 /* If we have FBS */ 1409 if (ch->fbs_enabled) { 1410 /* Untagged command while tagged are active. */ 1411 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1412 return (1); 1413 } else { 1414 /* Untagged command while tagged are active. */ 1415 if (ch->numrslots != 0 && ch->numtslots != 0) 1416 return (1); 1417 } 1418 } 1419 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1420 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1421 /* Atomic command while anything active. */ 1422 if (ch->numrslots != 0) 1423 return (1); 1424 } 1425 /* We have some atomic command running. */ 1426 if (ch->aslots != 0) 1427 return (1); 1428 return (0); 1429} 1430 1431/* Must be called with channel locked. */ 1432static void 1433ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb) 1434{ 1435 struct ahci_slot *slot; 1436 int tag, tags; 1437 1438 /* Choose empty slot. */ 1439 tags = ch->numslots; 1440 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1441 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1442 tags = ch->curr[ccb->ccb_h.target_id].tags; 1443 if (ch->lastslot + 1 < tags) 1444 tag = ffs(~(ch->oslots >> (ch->lastslot + 1))); 1445 else 1446 tag = 0; 1447 if (tag == 0 || tag + ch->lastslot >= tags) 1448 tag = ffs(~ch->oslots) - 1; 1449 else 1450 tag += ch->lastslot; 1451 ch->lastslot = tag; 1452 /* Occupy chosen slot. */ 1453 slot = &ch->slot[tag]; 1454 slot->ccb = ccb; 1455 /* Stop PM timer. */ 1456 if (ch->numrslots == 0 && ch->pm_level > 3) 1457 callout_stop(&ch->pm_timer); 1458 /* Update channel stats. */ 1459 ch->oslots |= (1 << tag); 1460 ch->numrslots++; 1461 ch->numrslotspd[ccb->ccb_h.target_id]++; 1462 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1463 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1464 ch->numtslots++; 1465 ch->numtslotspd[ccb->ccb_h.target_id]++; 1466 ch->taggedtarget = ccb->ccb_h.target_id; 1467 } 1468 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1469 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1470 ch->aslots |= (1 << tag); 1471 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1472 slot->state = AHCI_SLOT_LOADING; 1473 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1474 ahci_dmasetprd, slot, 0); 1475 } else { 1476 slot->dma.nsegs = 0; 1477 ahci_execute_transaction(slot); 1478 } 1479} 1480 1481/* Locked by busdma engine. */ 1482static void 1483ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1484{ 1485 struct ahci_slot *slot = arg; 1486 struct ahci_channel *ch = slot->ch; 1487 struct ahci_cmd_tab *ctp; 1488 struct ahci_dma_prd *prd; 1489 int i; 1490 1491 if (error) { 1492 device_printf(ch->dev, "DMA load error\n"); 1493 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1494 return; 1495 } 1496 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1497 /* Get a piece of the workspace for this request */ 1498 ctp = (struct ahci_cmd_tab *) 1499 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1500 /* Fill S/G table */ 1501 prd = &ctp->prd_tab[0]; 1502 for (i = 0; i < nsegs; i++) { 1503 prd[i].dba = htole64(segs[i].ds_addr); 1504 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1505 } 1506 slot->dma.nsegs = nsegs; 1507 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1508 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1509 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1510 ahci_execute_transaction(slot); 1511} 1512 1513/* Must be called with channel locked. */ 1514static void 1515ahci_execute_transaction(struct ahci_slot *slot) 1516{ 1517 struct ahci_channel *ch = slot->ch; 1518 struct ahci_cmd_tab *ctp; 1519 struct ahci_cmd_list *clp; 1520 union ccb *ccb = slot->ccb; 1521 int port = ccb->ccb_h.target_id & 0x0f; 1522 int fis_size, i, softreset; 1523 uint8_t *fis = ch->dma.rfis + 0x40; 1524 uint8_t val; 1525 1526 /* Get a piece of the workspace for this request */ 1527 ctp = (struct ahci_cmd_tab *) 1528 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1529 /* Setup the FIS for this request */ 1530 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) { 1531 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1532 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1533 return; 1534 } 1535 /* Setup the command list entry */ 1536 clp = (struct ahci_cmd_list *) 1537 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1538 clp->cmd_flags = htole16( 1539 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1540 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1541 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1542 (fis_size / sizeof(u_int32_t)) | 1543 (port << 12)); 1544 clp->prd_length = htole16(slot->dma.nsegs); 1545 /* Special handling for Soft Reset command. */ 1546 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1547 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1548 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1549 softreset = 1; 1550 /* Kick controller into sane state */ 1551 ahci_stop(ch); 1552 ahci_clo(ch); 1553 ahci_start(ch, 0); 1554 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1555 } else { 1556 softreset = 2; 1557 /* Prepare FIS receive area for check. */ 1558 for (i = 0; i < 20; i++) 1559 fis[i] = 0xff; 1560 } 1561 } else 1562 softreset = 0; 1563 clp->bytecount = 0; 1564 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1565 (AHCI_CT_SIZE * slot->slot)); 1566 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1567 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1568 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1569 BUS_DMASYNC_PREREAD); 1570 /* Set ACTIVE bit for NCQ commands. */ 1571 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1572 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1573 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1574 } 1575 /* If FBS is enabled, set PMP port. */ 1576 if (ch->fbs_enabled) { 1577 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1578 (port << AHCI_P_FBS_DEV_SHIFT)); 1579 } 1580 /* Issue command to the controller. */ 1581 slot->state = AHCI_SLOT_RUNNING; 1582 ch->rslots |= (1 << slot->slot); 1583 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1584 /* Device reset commands doesn't interrupt. Poll them. */ 1585 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1586 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1587 int count, timeout = ccb->ccb_h.timeout * 100; 1588 enum ahci_err_type et = AHCI_ERR_NONE; 1589 1590 for (count = 0; count < timeout; count++) { 1591 DELAY(10); 1592 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1593 break; 1594 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1595 softreset != 1) { 1596#if 0 1597 device_printf(ch->dev, 1598 "Poll error on slot %d, TFD: %04x\n", 1599 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1600#endif 1601 et = AHCI_ERR_TFE; 1602 break; 1603 } 1604 /* Workaround for ATI SB600/SB700 chipsets. */ 1605 if (ccb->ccb_h.target_id == 15 && 1606 (ch->quirks & AHCI_Q_ATI_PMP_BUG) && 1607 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1608 et = AHCI_ERR_TIMEOUT; 1609 break; 1610 } 1611 } 1612 1613 /* 1614 * Marvell HBAs with non-RAID firmware do not wait for 1615 * readiness after soft reset, so we have to wait here. 1616 * Marvell RAIDs do not have this problem, but instead 1617 * sometimes forget to update FIS receive area, breaking 1618 * this wait. 1619 */ 1620 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && 1621 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 && 1622 softreset == 2 && et == AHCI_ERR_NONE) { 1623 for ( ; count < timeout; count++) { 1624 bus_dmamap_sync(ch->dma.rfis_tag, 1625 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD); 1626 val = fis[2]; 1627 bus_dmamap_sync(ch->dma.rfis_tag, 1628 ch->dma.rfis_map, BUS_DMASYNC_PREREAD); 1629 if ((val & ATA_S_BUSY) == 0) 1630 break; 1631 DELAY(10); 1632 } 1633 } 1634 1635 if (timeout && (count >= timeout)) { 1636 device_printf(ch->dev, "Poll timeout on slot %d port %d\n", 1637 slot->slot, port); 1638 device_printf(ch->dev, "is %08x cs %08x ss %08x " 1639 "rs %08x tfd %02x serr %08x cmd %08x\n", 1640 ATA_INL(ch->r_mem, AHCI_P_IS), 1641 ATA_INL(ch->r_mem, AHCI_P_CI), 1642 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1643 ATA_INL(ch->r_mem, AHCI_P_TFD), 1644 ATA_INL(ch->r_mem, AHCI_P_SERR), 1645 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1646 et = AHCI_ERR_TIMEOUT; 1647 } 1648 1649 /* Kick controller into sane state and enable FBS. */ 1650 if (softreset == 2) 1651 ch->eslots |= (1 << slot->slot); 1652 ahci_end_transaction(slot, et); 1653 return; 1654 } 1655 /* Start command execution timeout */ 1656 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2, 1657 0, (timeout_t*)ahci_timeout, slot, 0); 1658 return; 1659} 1660 1661/* Must be called with channel locked. */ 1662static void 1663ahci_process_timeout(struct ahci_channel *ch) 1664{ 1665 int i; 1666 1667 mtx_assert(&ch->mtx, MA_OWNED); 1668 /* Handle the rest of commands. */ 1669 for (i = 0; i < ch->numslots; i++) { 1670 /* Do we have a running request on slot? */ 1671 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1672 continue; 1673 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1674 } 1675} 1676 1677/* Must be called with channel locked. */ 1678static void 1679ahci_rearm_timeout(struct ahci_channel *ch) 1680{ 1681 int i; 1682 1683 mtx_assert(&ch->mtx, MA_OWNED); 1684 for (i = 0; i < ch->numslots; i++) { 1685 struct ahci_slot *slot = &ch->slot[i]; 1686 1687 /* Do we have a running request on slot? */ 1688 if (slot->state < AHCI_SLOT_RUNNING) 1689 continue; 1690 if ((ch->toslots & (1 << i)) == 0) 1691 continue; 1692 callout_reset_sbt(&slot->timeout, 1693 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1694 (timeout_t*)ahci_timeout, slot, 0); 1695 } 1696} 1697 1698/* Locked by callout mechanism. */ 1699static void 1700ahci_timeout(struct ahci_slot *slot) 1701{ 1702 struct ahci_channel *ch = slot->ch; 1703 device_t dev = ch->dev; 1704 uint32_t sstatus; 1705 int ccs; 1706 int i; 1707 1708 /* Check for stale timeout. */ 1709 if (slot->state < AHCI_SLOT_RUNNING) 1710 return; 1711 1712 /* Check if slot was not being executed last time we checked. */ 1713 if (slot->state < AHCI_SLOT_EXECUTING) { 1714 /* Check if slot started executing. */ 1715 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1716 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1717 >> AHCI_P_CMD_CCS_SHIFT; 1718 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1719 ch->fbs_enabled || ch->wrongccs) 1720 slot->state = AHCI_SLOT_EXECUTING; 1721 else if ((ch->rslots & (1 << ccs)) == 0) { 1722 ch->wrongccs = 1; 1723 slot->state = AHCI_SLOT_EXECUTING; 1724 } 1725 1726 callout_reset_sbt(&slot->timeout, 1727 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1728 (timeout_t*)ahci_timeout, slot, 0); 1729 return; 1730 } 1731 1732 device_printf(dev, "Timeout on slot %d port %d\n", 1733 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1734 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1735 "serr %08x cmd %08x\n", 1736 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1737 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1738 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1739 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1740 1741 /* Handle frozen command. */ 1742 if (ch->frozen) { 1743 union ccb *fccb = ch->frozen; 1744 ch->frozen = NULL; 1745 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1746 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1747 xpt_freeze_devq(fccb->ccb_h.path, 1); 1748 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1749 } 1750 ahci_done(ch, fccb); 1751 } 1752 if (!ch->fbs_enabled && !ch->wrongccs) { 1753 /* Without FBS we know real timeout source. */ 1754 ch->fatalerr = 1; 1755 /* Handle command with timeout. */ 1756 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1757 /* Handle the rest of commands. */ 1758 for (i = 0; i < ch->numslots; i++) { 1759 /* Do we have a running request on slot? */ 1760 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1761 continue; 1762 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1763 } 1764 } else { 1765 /* With FBS we wait for other commands timeout and pray. */ 1766 if (ch->toslots == 0) 1767 xpt_freeze_simq(ch->sim, 1); 1768 ch->toslots |= (1 << slot->slot); 1769 if ((ch->rslots & ~ch->toslots) == 0) 1770 ahci_process_timeout(ch); 1771 else 1772 device_printf(dev, " ... waiting for slots %08x\n", 1773 ch->rslots & ~ch->toslots); 1774 } 1775} 1776 1777/* Must be called with channel locked. */ 1778static void 1779ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1780{ 1781 struct ahci_channel *ch = slot->ch; 1782 union ccb *ccb = slot->ccb; 1783 struct ahci_cmd_list *clp; 1784 int lastto; 1785 uint32_t sig; 1786 1787 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1788 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1789 clp = (struct ahci_cmd_list *) 1790 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1791 /* Read result registers to the result struct 1792 * May be incorrect if several commands finished same time, 1793 * so read only when sure or have to. 1794 */ 1795 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1796 struct ata_res *res = &ccb->ataio.res; 1797 1798 if ((et == AHCI_ERR_TFE) || 1799 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1800 u_int8_t *fis = ch->dma.rfis + 0x40; 1801 1802 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1803 BUS_DMASYNC_POSTREAD); 1804 if (ch->fbs_enabled) { 1805 fis += ccb->ccb_h.target_id * 256; 1806 res->status = fis[2]; 1807 res->error = fis[3]; 1808 } else { 1809 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1810 1811 res->status = tfd; 1812 res->error = tfd >> 8; 1813 } 1814 res->lba_low = fis[4]; 1815 res->lba_mid = fis[5]; 1816 res->lba_high = fis[6]; 1817 res->device = fis[7]; 1818 res->lba_low_exp = fis[8]; 1819 res->lba_mid_exp = fis[9]; 1820 res->lba_high_exp = fis[10]; 1821 res->sector_count = fis[12]; 1822 res->sector_count_exp = fis[13]; 1823 1824 /* 1825 * Some weird controllers do not return signature in 1826 * FIS receive area. Read it from PxSIG register. 1827 */ 1828 if ((ch->quirks & AHCI_Q_ALTSIG) && 1829 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1830 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1831 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 1832 res->lba_high = sig >> 24; 1833 res->lba_mid = sig >> 16; 1834 res->lba_low = sig >> 8; 1835 res->sector_count = sig; 1836 } 1837 } else 1838 bzero(res, sizeof(*res)); 1839 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1840 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1841 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1842 ccb->ataio.resid = 1843 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 1844 } 1845 } else { 1846 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1847 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1848 ccb->csio.resid = 1849 ccb->csio.dxfer_len - le32toh(clp->bytecount); 1850 } 1851 } 1852 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1853 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1854 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1855 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1856 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1857 } 1858 if (et != AHCI_ERR_NONE) 1859 ch->eslots |= (1 << slot->slot); 1860 /* In case of error, freeze device for proper recovery. */ 1861 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 1862 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1863 xpt_freeze_devq(ccb->ccb_h.path, 1); 1864 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1865 } 1866 /* Set proper result status. */ 1867 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1868 switch (et) { 1869 case AHCI_ERR_NONE: 1870 ccb->ccb_h.status |= CAM_REQ_CMP; 1871 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1872 ccb->csio.scsi_status = SCSI_STATUS_OK; 1873 break; 1874 case AHCI_ERR_INVALID: 1875 ch->fatalerr = 1; 1876 ccb->ccb_h.status |= CAM_REQ_INVALID; 1877 break; 1878 case AHCI_ERR_INNOCENT: 1879 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1880 break; 1881 case AHCI_ERR_TFE: 1882 case AHCI_ERR_NCQ: 1883 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1884 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1885 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1886 } else { 1887 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1888 } 1889 break; 1890 case AHCI_ERR_SATA: 1891 ch->fatalerr = 1; 1892 if (!ch->recoverycmd) { 1893 xpt_freeze_simq(ch->sim, 1); 1894 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1895 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1896 } 1897 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1898 break; 1899 case AHCI_ERR_TIMEOUT: 1900 if (!ch->recoverycmd) { 1901 xpt_freeze_simq(ch->sim, 1); 1902 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1903 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1904 } 1905 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1906 break; 1907 default: 1908 ch->fatalerr = 1; 1909 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1910 } 1911 /* Free slot. */ 1912 ch->oslots &= ~(1 << slot->slot); 1913 ch->rslots &= ~(1 << slot->slot); 1914 ch->aslots &= ~(1 << slot->slot); 1915 slot->state = AHCI_SLOT_EMPTY; 1916 slot->ccb = NULL; 1917 /* Update channel stats. */ 1918 ch->numrslots--; 1919 ch->numrslotspd[ccb->ccb_h.target_id]--; 1920 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1921 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1922 ch->numtslots--; 1923 ch->numtslotspd[ccb->ccb_h.target_id]--; 1924 } 1925 /* Cancel timeout state if request completed normally. */ 1926 if (et != AHCI_ERR_TIMEOUT) { 1927 lastto = (ch->toslots == (1 << slot->slot)); 1928 ch->toslots &= ~(1 << slot->slot); 1929 if (lastto) 1930 xpt_release_simq(ch->sim, TRUE); 1931 } 1932 /* If it was first request of reset sequence and there is no error, 1933 * proceed to second request. */ 1934 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1935 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1936 (ccb->ataio.cmd.control & ATA_A_RESET) && 1937 et == AHCI_ERR_NONE) { 1938 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1939 ahci_begin_transaction(ch, ccb); 1940 return; 1941 } 1942 /* If it was our READ LOG command - process it. */ 1943 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 1944 ahci_process_read_log(ch, ccb); 1945 /* If it was our REQUEST SENSE command - process it. */ 1946 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 1947 ahci_process_request_sense(ch, ccb); 1948 /* If it was NCQ or ATAPI command error, put result on hold. */ 1949 } else if (et == AHCI_ERR_NCQ || 1950 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 1951 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 1952 ch->hold[slot->slot] = ccb; 1953 ch->numhslots++; 1954 } else 1955 ahci_done(ch, ccb); 1956 /* If we have no other active commands, ... */ 1957 if (ch->rslots == 0) { 1958 /* if there was fatal error - reset port. */ 1959 if (ch->toslots != 0 || ch->fatalerr) { 1960 ahci_reset(ch); 1961 } else { 1962 /* if we have slots in error, we can reinit port. */ 1963 if (ch->eslots != 0) { 1964 ahci_stop(ch); 1965 ahci_clo(ch); 1966 ahci_start(ch, 1); 1967 } 1968 /* if there commands on hold, we can do READ LOG. */ 1969 if (!ch->recoverycmd && ch->numhslots) 1970 ahci_issue_recovery(ch); 1971 } 1972 /* If all the rest of commands are in timeout - give them chance. */ 1973 } else if ((ch->rslots & ~ch->toslots) == 0 && 1974 et != AHCI_ERR_TIMEOUT) 1975 ahci_rearm_timeout(ch); 1976 /* Unfreeze frozen command. */ 1977 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) { 1978 union ccb *fccb = ch->frozen; 1979 ch->frozen = NULL; 1980 ahci_begin_transaction(ch, fccb); 1981 xpt_release_simq(ch->sim, TRUE); 1982 } 1983 /* Start PM timer. */ 1984 if (ch->numrslots == 0 && ch->pm_level > 3 && 1985 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1986 callout_schedule(&ch->pm_timer, 1987 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1988 } 1989} 1990 1991static void 1992ahci_issue_recovery(struct ahci_channel *ch) 1993{ 1994 union ccb *ccb; 1995 struct ccb_ataio *ataio; 1996 struct ccb_scsiio *csio; 1997 int i; 1998 1999 /* Find some held command. */ 2000 for (i = 0; i < ch->numslots; i++) { 2001 if (ch->hold[i]) 2002 break; 2003 } 2004 ccb = xpt_alloc_ccb_nowait(); 2005 if (ccb == NULL) { 2006 device_printf(ch->dev, "Unable to allocate recovery command\n"); 2007completeall: 2008 /* We can't do anything -- complete held commands. */ 2009 for (i = 0; i < ch->numslots; i++) { 2010 if (ch->hold[i] == NULL) 2011 continue; 2012 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2013 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2014 ahci_done(ch, ch->hold[i]); 2015 ch->hold[i] = NULL; 2016 ch->numhslots--; 2017 } 2018 ahci_reset(ch); 2019 return; 2020 } 2021 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2022 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2023 /* READ LOG */ 2024 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2025 ccb->ccb_h.func_code = XPT_ATA_IO; 2026 ccb->ccb_h.flags = CAM_DIR_IN; 2027 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2028 ataio = &ccb->ataio; 2029 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2030 if (ataio->data_ptr == NULL) { 2031 xpt_free_ccb(ccb); 2032 device_printf(ch->dev, 2033 "Unable to allocate memory for READ LOG command\n"); 2034 goto completeall; 2035 } 2036 ataio->dxfer_len = 512; 2037 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2038 ataio->cmd.flags = CAM_ATAIO_48BIT; 2039 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2040 ataio->cmd.sector_count = 1; 2041 ataio->cmd.sector_count_exp = 0; 2042 ataio->cmd.lba_low = 0x10; 2043 ataio->cmd.lba_mid = 0; 2044 ataio->cmd.lba_mid_exp = 0; 2045 } else { 2046 /* REQUEST SENSE */ 2047 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2048 ccb->ccb_h.recovery_slot = i; 2049 ccb->ccb_h.func_code = XPT_SCSI_IO; 2050 ccb->ccb_h.flags = CAM_DIR_IN; 2051 ccb->ccb_h.status = 0; 2052 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2053 csio = &ccb->csio; 2054 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2055 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2056 csio->cdb_len = 6; 2057 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2058 csio->cdb_io.cdb_bytes[0] = 0x03; 2059 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2060 } 2061 /* Freeze SIM while doing recovery. */ 2062 ch->recoverycmd = 1; 2063 xpt_freeze_simq(ch->sim, 1); 2064 ahci_begin_transaction(ch, ccb); 2065} 2066 2067static void 2068ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb) 2069{ 2070 uint8_t *data; 2071 struct ata_res *res; 2072 int i; 2073 2074 ch->recoverycmd = 0; 2075 2076 data = ccb->ataio.data_ptr; 2077 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2078 (data[0] & 0x80) == 0) { 2079 for (i = 0; i < ch->numslots; i++) { 2080 if (!ch->hold[i]) 2081 continue; 2082 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2083 continue; 2084 if ((data[0] & 0x1F) == i) { 2085 res = &ch->hold[i]->ataio.res; 2086 res->status = data[2]; 2087 res->error = data[3]; 2088 res->lba_low = data[4]; 2089 res->lba_mid = data[5]; 2090 res->lba_high = data[6]; 2091 res->device = data[7]; 2092 res->lba_low_exp = data[8]; 2093 res->lba_mid_exp = data[9]; 2094 res->lba_high_exp = data[10]; 2095 res->sector_count = data[12]; 2096 res->sector_count_exp = data[13]; 2097 } else { 2098 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2099 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2100 } 2101 ahci_done(ch, ch->hold[i]); 2102 ch->hold[i] = NULL; 2103 ch->numhslots--; 2104 } 2105 } else { 2106 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2107 device_printf(ch->dev, "Error while READ LOG EXT\n"); 2108 else if ((data[0] & 0x80) == 0) { 2109 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n"); 2110 } 2111 for (i = 0; i < ch->numslots; i++) { 2112 if (!ch->hold[i]) 2113 continue; 2114 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2115 continue; 2116 ahci_done(ch, ch->hold[i]); 2117 ch->hold[i] = NULL; 2118 ch->numhslots--; 2119 } 2120 } 2121 free(ccb->ataio.data_ptr, M_AHCI); 2122 xpt_free_ccb(ccb); 2123 xpt_release_simq(ch->sim, TRUE); 2124} 2125 2126static void 2127ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb) 2128{ 2129 int i; 2130 2131 ch->recoverycmd = 0; 2132 2133 i = ccb->ccb_h.recovery_slot; 2134 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2135 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2136 } else { 2137 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2138 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2139 } 2140 ahci_done(ch, ch->hold[i]); 2141 ch->hold[i] = NULL; 2142 ch->numhslots--; 2143 xpt_free_ccb(ccb); 2144 xpt_release_simq(ch->sim, TRUE); 2145} 2146 2147static void 2148ahci_start(struct ahci_channel *ch, int fbs) 2149{ 2150 u_int32_t cmd; 2151 2152 /* Run the channel start callback, if any. */ 2153 if (ch->start) 2154 ch->start(ch); 2155 2156 /* Clear SATA error register */ 2157 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2158 /* Clear any interrupts pending on this channel */ 2159 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2160 /* Configure FIS-based switching if supported. */ 2161 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2162 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2163 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2164 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2165 } 2166 /* Start operations on this channel */ 2167 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2168 cmd &= ~AHCI_P_CMD_PMA; 2169 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2170 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2171} 2172 2173static void 2174ahci_stop(struct ahci_channel *ch) 2175{ 2176 u_int32_t cmd; 2177 int timeout; 2178 2179 /* Kill all activity on this channel */ 2180 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2181 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2182 /* Wait for activity stop. */ 2183 timeout = 0; 2184 do { 2185 DELAY(10); 2186 if (timeout++ > 50000) { 2187 device_printf(ch->dev, "stopping AHCI engine failed\n"); 2188 break; 2189 } 2190 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2191 ch->eslots = 0; 2192} 2193 2194static void 2195ahci_clo(struct ahci_channel *ch) 2196{ 2197 u_int32_t cmd; 2198 int timeout; 2199 2200 /* Issue Command List Override if supported */ 2201 if (ch->caps & AHCI_CAP_SCLO) { 2202 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2203 cmd |= AHCI_P_CMD_CLO; 2204 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2205 timeout = 0; 2206 do { 2207 DELAY(10); 2208 if (timeout++ > 50000) { 2209 device_printf(ch->dev, "executing CLO failed\n"); 2210 break; 2211 } 2212 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2213 } 2214} 2215 2216static void 2217ahci_stop_fr(struct ahci_channel *ch) 2218{ 2219 u_int32_t cmd; 2220 int timeout; 2221 2222 /* Kill all FIS reception on this channel */ 2223 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2224 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2225 /* Wait for FIS reception stop. */ 2226 timeout = 0; 2227 do { 2228 DELAY(10); 2229 if (timeout++ > 50000) { 2230 device_printf(ch->dev, "stopping AHCI FR engine failed\n"); 2231 break; 2232 } 2233 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2234} 2235 2236static void 2237ahci_start_fr(struct ahci_channel *ch) 2238{ 2239 u_int32_t cmd; 2240 2241 /* Start FIS reception on this channel */ 2242 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2243 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2244} 2245 2246static int 2247ahci_wait_ready(struct ahci_channel *ch, int t, int t0) 2248{ 2249 int timeout = 0; 2250 uint32_t val; 2251 2252 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2253 (ATA_S_BUSY | ATA_S_DRQ)) { 2254 if (timeout > t) { 2255 if (t != 0) { 2256 device_printf(ch->dev, 2257 "AHCI reset: device not ready after %dms " 2258 "(tfd = %08x)\n", 2259 MAX(t, 0) + t0, val); 2260 } 2261 return (EBUSY); 2262 } 2263 DELAY(1000); 2264 timeout++; 2265 } 2266 if (bootverbose) 2267 device_printf(ch->dev, "AHCI reset: device ready after %dms\n", 2268 timeout + t0); 2269 return (0); 2270} 2271 2272static void 2273ahci_reset_to(void *arg) 2274{ 2275 struct ahci_channel *ch = arg; 2276 2277 if (ch->resetting == 0) 2278 return; 2279 ch->resetting--; 2280 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0, 2281 (310 - ch->resetting) * 100) == 0) { 2282 ch->resetting = 0; 2283 ahci_start(ch, 1); 2284 xpt_release_simq(ch->sim, TRUE); 2285 return; 2286 } 2287 if (ch->resetting == 0) { 2288 ahci_clo(ch); 2289 ahci_start(ch, 1); 2290 xpt_release_simq(ch->sim, TRUE); 2291 return; 2292 } 2293 callout_schedule(&ch->reset_timer, hz / 10); 2294} 2295 2296static void 2297ahci_reset(struct ahci_channel *ch) 2298{ 2299 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev)); 2300 int i; 2301 2302 xpt_freeze_simq(ch->sim, 1); 2303 if (bootverbose) 2304 device_printf(ch->dev, "AHCI reset...\n"); 2305 /* Forget about previous reset. */ 2306 if (ch->resetting) { 2307 ch->resetting = 0; 2308 callout_stop(&ch->reset_timer); 2309 xpt_release_simq(ch->sim, TRUE); 2310 } 2311 /* Requeue freezed command. */ 2312 if (ch->frozen) { 2313 union ccb *fccb = ch->frozen; 2314 ch->frozen = NULL; 2315 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2316 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2317 xpt_freeze_devq(fccb->ccb_h.path, 1); 2318 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2319 } 2320 ahci_done(ch, fccb); 2321 } 2322 /* Kill the engine and requeue all running commands. */ 2323 ahci_stop(ch); 2324 for (i = 0; i < ch->numslots; i++) { 2325 /* Do we have a running request on slot? */ 2326 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2327 continue; 2328 /* XXX; Commands in loading state. */ 2329 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2330 } 2331 for (i = 0; i < ch->numslots; i++) { 2332 if (!ch->hold[i]) 2333 continue; 2334 ahci_done(ch, ch->hold[i]); 2335 ch->hold[i] = NULL; 2336 ch->numhslots--; 2337 } 2338 if (ch->toslots != 0) 2339 xpt_release_simq(ch->sim, TRUE); 2340 ch->eslots = 0; 2341 ch->toslots = 0; 2342 ch->wrongccs = 0; 2343 ch->fatalerr = 0; 2344 /* Tell the XPT about the event */ 2345 xpt_async(AC_BUS_RESET, ch->path, NULL); 2346 /* Disable port interrupts */ 2347 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2348 /* Reset and reconnect PHY, */ 2349 if (!ahci_sata_phy_reset(ch)) { 2350 if (bootverbose) 2351 device_printf(ch->dev, 2352 "AHCI reset: device not found\n"); 2353 ch->devices = 0; 2354 /* Enable wanted port interrupts */ 2355 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2356 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2357 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2358 xpt_release_simq(ch->sim, TRUE); 2359 return; 2360 } 2361 if (bootverbose) 2362 device_printf(ch->dev, "AHCI reset: device found\n"); 2363 /* Wait for clearing busy status. */ 2364 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) { 2365 if (dumping) 2366 ahci_clo(ch); 2367 else 2368 ch->resetting = 310; 2369 } 2370 ch->devices = 1; 2371 /* Enable wanted port interrupts */ 2372 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2373 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2374 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2375 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2376 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2377 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2378 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2379 if (ch->resetting) 2380 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch); 2381 else { 2382 ahci_start(ch, 1); 2383 xpt_release_simq(ch->sim, TRUE); 2384 } 2385} 2386 2387static int 2388ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2389{ 2390 u_int8_t *fis = &ctp->cfis[0]; 2391 2392 bzero(fis, 20); 2393 fis[0] = 0x27; /* host to device */ 2394 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2395 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2396 fis[1] |= 0x80; 2397 fis[2] = ATA_PACKET_CMD; 2398 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2399 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2400 fis[3] = ATA_F_DMA; 2401 else { 2402 fis[5] = ccb->csio.dxfer_len; 2403 fis[6] = ccb->csio.dxfer_len >> 8; 2404 } 2405 fis[7] = ATA_D_LBA; 2406 fis[15] = ATA_A_4BIT; 2407 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2408 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2409 ctp->acmd, ccb->csio.cdb_len); 2410 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2411 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2412 fis[1] |= 0x80; 2413 fis[2] = ccb->ataio.cmd.command; 2414 fis[3] = ccb->ataio.cmd.features; 2415 fis[4] = ccb->ataio.cmd.lba_low; 2416 fis[5] = ccb->ataio.cmd.lba_mid; 2417 fis[6] = ccb->ataio.cmd.lba_high; 2418 fis[7] = ccb->ataio.cmd.device; 2419 fis[8] = ccb->ataio.cmd.lba_low_exp; 2420 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2421 fis[10] = ccb->ataio.cmd.lba_high_exp; 2422 fis[11] = ccb->ataio.cmd.features_exp; 2423 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2424 fis[12] = tag << 3; 2425 } else { 2426 fis[12] = ccb->ataio.cmd.sector_count; 2427 } 2428 fis[13] = ccb->ataio.cmd.sector_count_exp; 2429 fis[15] = ATA_A_4BIT; 2430 } else { 2431 fis[15] = ccb->ataio.cmd.control; 2432 } 2433 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) { 2434 fis[16] = ccb->ataio.aux & 0xff; 2435 fis[17] = (ccb->ataio.aux >> 8) & 0xff; 2436 fis[18] = (ccb->ataio.aux >> 16) & 0xff; 2437 fis[19] = (ccb->ataio.aux >> 24) & 0xff; 2438 } 2439 return (20); 2440} 2441 2442static int 2443ahci_sata_connect(struct ahci_channel *ch) 2444{ 2445 u_int32_t status; 2446 int timeout, found = 0; 2447 2448 /* Wait up to 100ms for "connect well" */ 2449 for (timeout = 0; timeout < 1000 ; timeout++) { 2450 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2451 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2452 found = 1; 2453 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2454 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2455 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2456 break; 2457 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2458 if (bootverbose) { 2459 device_printf(ch->dev, "SATA offline status=%08x\n", 2460 status); 2461 } 2462 return (0); 2463 } 2464 if (found == 0 && timeout >= 100) 2465 break; 2466 DELAY(100); 2467 } 2468 if (timeout >= 1000 || !found) { 2469 if (bootverbose) { 2470 device_printf(ch->dev, 2471 "SATA connect timeout time=%dus status=%08x\n", 2472 timeout * 100, status); 2473 } 2474 return (0); 2475 } 2476 if (bootverbose) { 2477 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2478 timeout * 100, status); 2479 } 2480 /* Clear SATA error register */ 2481 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2482 return (1); 2483} 2484 2485static int 2486ahci_sata_phy_reset(struct ahci_channel *ch) 2487{ 2488 int sata_rev; 2489 uint32_t val; 2490 2491 if (ch->listening) { 2492 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2493 val |= AHCI_P_CMD_SUD; 2494 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2495 ch->listening = 0; 2496 } 2497 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2498 if (sata_rev == 1) 2499 val = ATA_SC_SPD_SPEED_GEN1; 2500 else if (sata_rev == 2) 2501 val = ATA_SC_SPD_SPEED_GEN2; 2502 else if (sata_rev == 3) 2503 val = ATA_SC_SPD_SPEED_GEN3; 2504 else 2505 val = 0; 2506 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2507 ATA_SC_DET_RESET | val | 2508 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2509 DELAY(1000); 2510 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2511 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2512 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2513 if (!ahci_sata_connect(ch)) { 2514 if (ch->caps & AHCI_CAP_SSS) { 2515 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2516 val &= ~AHCI_P_CMD_SUD; 2517 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2518 ch->listening = 1; 2519 } else if (ch->pm_level > 0) 2520 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2521 return (0); 2522 } 2523 return (1); 2524} 2525 2526static int 2527ahci_check_ids(struct ahci_channel *ch, union ccb *ccb) 2528{ 2529 2530 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2531 ccb->ccb_h.status = CAM_TID_INVALID; 2532 ahci_done(ch, ccb); 2533 return (-1); 2534 } 2535 if (ccb->ccb_h.target_lun != 0) { 2536 ccb->ccb_h.status = CAM_LUN_INVALID; 2537 ahci_done(ch, ccb); 2538 return (-1); 2539 } 2540 return (0); 2541} 2542 2543static void 2544ahciaction(struct cam_sim *sim, union ccb *ccb) 2545{ 2546 struct ahci_channel *ch; 2547 2548 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2549 ccb->ccb_h.func_code)); 2550 2551 ch = (struct ahci_channel *)cam_sim_softc(sim); 2552 switch (ccb->ccb_h.func_code) { 2553 /* Common cases first */ 2554 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2555 case XPT_SCSI_IO: 2556 if (ahci_check_ids(ch, ccb)) 2557 return; 2558 if (ch->devices == 0 || 2559 (ch->pm_present == 0 && 2560 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2561 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2562 break; 2563 } 2564 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2565 /* Check for command collision. */ 2566 if (ahci_check_collision(ch, ccb)) { 2567 /* Freeze command. */ 2568 ch->frozen = ccb; 2569 /* We have only one frozen slot, so freeze simq also. */ 2570 xpt_freeze_simq(ch->sim, 1); 2571 return; 2572 } 2573 ahci_begin_transaction(ch, ccb); 2574 return; 2575 case XPT_ABORT: /* Abort the specified CCB */ 2576 /* XXX Implement */ 2577 ccb->ccb_h.status = CAM_REQ_INVALID; 2578 break; 2579 case XPT_SET_TRAN_SETTINGS: 2580 { 2581 struct ccb_trans_settings *cts = &ccb->cts; 2582 struct ahci_device *d; 2583 2584 if (ahci_check_ids(ch, ccb)) 2585 return; 2586 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2587 d = &ch->curr[ccb->ccb_h.target_id]; 2588 else 2589 d = &ch->user[ccb->ccb_h.target_id]; 2590 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2591 d->revision = cts->xport_specific.sata.revision; 2592 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2593 d->mode = cts->xport_specific.sata.mode; 2594 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2595 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2596 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2597 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2598 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2599 ch->pm_present = cts->xport_specific.sata.pm_present; 2600 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2601 d->atapi = cts->xport_specific.sata.atapi; 2602 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2603 d->caps = cts->xport_specific.sata.caps; 2604 ccb->ccb_h.status = CAM_REQ_CMP; 2605 break; 2606 } 2607 case XPT_GET_TRAN_SETTINGS: 2608 /* Get default/user set transfer settings for the target */ 2609 { 2610 struct ccb_trans_settings *cts = &ccb->cts; 2611 struct ahci_device *d; 2612 uint32_t status; 2613 2614 if (ahci_check_ids(ch, ccb)) 2615 return; 2616 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2617 d = &ch->curr[ccb->ccb_h.target_id]; 2618 else 2619 d = &ch->user[ccb->ccb_h.target_id]; 2620 cts->protocol = PROTO_UNSPECIFIED; 2621 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2622 cts->transport = XPORT_SATA; 2623 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2624 cts->proto_specific.valid = 0; 2625 cts->xport_specific.sata.valid = 0; 2626 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2627 (ccb->ccb_h.target_id == 15 || 2628 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2629 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2630 if (status & 0x0f0) { 2631 cts->xport_specific.sata.revision = 2632 (status & 0x0f0) >> 4; 2633 cts->xport_specific.sata.valid |= 2634 CTS_SATA_VALID_REVISION; 2635 } 2636 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2637 if (ch->pm_level) { 2638 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2639 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2640 if (ch->caps2 & AHCI_CAP2_APST) 2641 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2642 } 2643 if ((ch->caps & AHCI_CAP_SNCQ) && 2644 (ch->quirks & AHCI_Q_NOAA) == 0) 2645 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2646 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2647 cts->xport_specific.sata.caps &= 2648 ch->user[ccb->ccb_h.target_id].caps; 2649 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2650 } else { 2651 cts->xport_specific.sata.revision = d->revision; 2652 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2653 cts->xport_specific.sata.caps = d->caps; 2654 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2655 } 2656 cts->xport_specific.sata.mode = d->mode; 2657 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2658 cts->xport_specific.sata.bytecount = d->bytecount; 2659 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2660 cts->xport_specific.sata.pm_present = ch->pm_present; 2661 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2662 cts->xport_specific.sata.tags = d->tags; 2663 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2664 cts->xport_specific.sata.atapi = d->atapi; 2665 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2666 ccb->ccb_h.status = CAM_REQ_CMP; 2667 break; 2668 } 2669 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2670 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2671 ahci_reset(ch); 2672 ccb->ccb_h.status = CAM_REQ_CMP; 2673 break; 2674 case XPT_TERM_IO: /* Terminate the I/O process */ 2675 /* XXX Implement */ 2676 ccb->ccb_h.status = CAM_REQ_INVALID; 2677 break; 2678 case XPT_PATH_INQ: /* Path routing inquiry */ 2679 { 2680 struct ccb_pathinq *cpi = &ccb->cpi; 2681 2682 cpi->version_num = 1; /* XXX??? */ 2683 cpi->hba_inquiry = PI_SDTR_ABLE; 2684 if (ch->caps & AHCI_CAP_SNCQ) 2685 cpi->hba_inquiry |= PI_TAG_ABLE; 2686 if (ch->caps & AHCI_CAP_SPM) 2687 cpi->hba_inquiry |= PI_SATAPM; 2688 cpi->target_sprt = 0; 2689 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 2690 if ((ch->quirks & AHCI_Q_NOAUX) == 0) 2691 cpi->hba_misc |= PIM_ATA_EXT; 2692 cpi->hba_eng_cnt = 0; 2693 if (ch->caps & AHCI_CAP_SPM) 2694 cpi->max_target = 15; 2695 else 2696 cpi->max_target = 0; 2697 cpi->max_lun = 0; 2698 cpi->initiator_id = 0; 2699 cpi->bus_id = cam_sim_bus(sim); 2700 cpi->base_transfer_speed = 150000; 2701 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2702 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2703 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2704 cpi->unit_number = cam_sim_unit(sim); 2705 cpi->transport = XPORT_SATA; 2706 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2707 cpi->protocol = PROTO_ATA; 2708 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2709 cpi->maxio = MAXPHYS; 2710 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2711 if (ch->quirks & AHCI_Q_MAXIO_64K) 2712 cpi->maxio = min(cpi->maxio, 128 * 512); 2713 cpi->hba_vendor = ch->vendorid; 2714 cpi->hba_device = ch->deviceid; 2715 cpi->hba_subvendor = ch->subvendorid; 2716 cpi->hba_subdevice = ch->subdeviceid; 2717 cpi->ccb_h.status = CAM_REQ_CMP; 2718 break; 2719 } 2720 default: 2721 ccb->ccb_h.status = CAM_REQ_INVALID; 2722 break; 2723 } 2724 ahci_done(ch, ccb); 2725} 2726 2727static void 2728ahcipoll(struct cam_sim *sim) 2729{ 2730 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2731 uint32_t istatus; 2732 2733 /* Read interrupt statuses and process if any. */ 2734 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 2735 if (istatus != 0) 2736 ahci_ch_intr_main(ch, istatus); 2737 if (ch->resetting != 0 && 2738 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2739 ch->resetpolldiv = 1000; 2740 ahci_reset_to(ch); 2741 } 2742} 2743 2744devclass_t ahci_devclass; 2745 2746MODULE_VERSION(ahci, 1); 2747MODULE_DEPEND(ahci, cam, 1, 1, 1); 2748