agp_intel.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/11/sys/dev/agp/agp_intel.c 330897 2018-03-14 03:19:51Z eadler $"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/malloc.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/bus.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/proc.h> 41 42#include <dev/agp/agppriv.h> 43#include <dev/agp/agpreg.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46 47#include <vm/vm.h> 48#include <vm/vm_object.h> 49#include <vm/pmap.h> 50 51#define MAX_APSIZE 0x3f /* 256 MB */ 52 53struct agp_intel_softc { 54 struct agp_softc agp; 55 u_int32_t initial_aperture; /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 u_int aperture_mask; 58 u_int32_t current_aperture; /* current aperture size */ 59}; 60 61static const char* 62agp_intel_match(device_t dev) 63{ 64 if (pci_get_class(dev) != PCIC_BRIDGE 65 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 66 return (NULL); 67 68 if (agp_find_caps(dev) == 0) 69 return (NULL); 70 71 switch (pci_get_devid(dev)) { 72 /* Intel -- vendor 0x8086 */ 73 case 0x71808086: 74 return ("Intel 82443LX (440 LX) host to PCI bridge"); 75 case 0x71908086: 76 return ("Intel 82443BX (440 BX) host to PCI bridge"); 77 case 0x71a08086: 78 return ("Intel 82443GX host to PCI bridge"); 79 case 0x71a18086: 80 return ("Intel 82443GX host to AGP bridge"); 81 case 0x11308086: 82 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 83 case 0x25008086: 84 case 0x25018086: 85 return ("Intel 82820 host to AGP bridge"); 86 case 0x35758086: 87 return ("Intel 82830 host to AGP bridge"); 88 case 0x1a218086: 89 return ("Intel 82840 host to AGP bridge"); 90 case 0x1a308086: 91 return ("Intel 82845 host to AGP bridge"); 92 case 0x25308086: 93 return ("Intel 82850 host to AGP bridge"); 94 case 0x33408086: 95 return ("Intel 82855 host to AGP bridge"); 96 case 0x25318086: 97 return ("Intel 82860 host to AGP bridge"); 98 case 0x25708086: 99 return ("Intel 82865 host to AGP bridge"); 100 case 0x255d8086: 101 return ("Intel E7205 host to AGP bridge"); 102 case 0x25508086: 103 return ("Intel E7505 host to AGP bridge"); 104 case 0x25788086: 105 return ("Intel 82875P host to AGP bridge"); 106 case 0x25608086: 107 return ("Intel 82845G host to AGP bridge"); 108 case 0x35808086: 109 return ("Intel 82855GM host to AGP bridge"); 110 } 111 112 return (NULL); 113} 114 115static int 116agp_intel_probe(device_t dev) 117{ 118 const char *desc; 119 120 if (resource_disabled("agp", device_get_unit(dev))) 121 return (ENXIO); 122 desc = agp_intel_match(dev); 123 if (desc) { 124 device_set_desc(dev, desc); 125 return (BUS_PROBE_DEFAULT); 126 } 127 128 return (ENXIO); 129} 130 131static void 132agp_intel_commit_gatt(device_t dev) 133{ 134 struct agp_intel_softc *sc; 135 u_int32_t type; 136 u_int32_t value; 137 138 sc = device_get_softc(dev); 139 type = pci_get_devid(dev); 140 141 /* Install the gatt. */ 142 pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4); 143 144 /* Enable the GLTB and setup the control register. */ 145 switch (type) { 146 case 0x71908086: /* 440LX/EX */ 147 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 148 break; 149 case 0x71808086: /* 440BX */ 150 /* 151 * XXX: Should be 0xa080? Bit 9 is undefined, and 152 * bit 13 being on and bit 15 being clear is illegal. 153 */ 154 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 155 break; 156 default: 157 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 158 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 159 } 160 161 /* Enable aperture accesses. */ 162 switch (type) { 163 case 0x25008086: /* i820 */ 164 case 0x25018086: /* i820 */ 165 pci_write_config(dev, AGP_INTEL_I820_RDCR, 166 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 167 | (1 << 1)), 1); 168 break; 169 case 0x1a308086: /* i845 */ 170 case 0x25608086: /* i845G */ 171 case 0x33408086: /* i855 */ 172 case 0x35808086: /* i855GM */ 173 case 0x25708086: /* i865 */ 174 case 0x25788086: /* i875P */ 175 pci_write_config(dev, AGP_INTEL_I845_AGPM, 176 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) 177 | (1 << 1)), 1); 178 break; 179 case 0x1a218086: /* i840 */ 180 case 0x25308086: /* i850 */ 181 case 0x25318086: /* i860 */ 182 case 0x255d8086: /* E7205 */ 183 case 0x25508086: /* E7505 */ 184 pci_write_config(dev, AGP_INTEL_MCHCFG, 185 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 186 | (1 << 9)), 2); 187 break; 188 default: /* Intel Generic (maybe) */ 189 pci_write_config(dev, AGP_INTEL_NBXCFG, 190 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 191 & ~(1 << 10)) | (1 << 9), 4); 192 } 193 194 /* Clear errors. */ 195 switch (type) { 196 case 0x1a218086: /* i840 */ 197 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 198 break; 199 case 0x25008086: /* i820 */ 200 case 0x25018086: /* i820 */ 201 case 0x1a308086: /* i845 */ 202 case 0x25608086: /* i845G */ 203 case 0x25308086: /* i850 */ 204 case 0x33408086: /* i855 */ 205 case 0x25318086: /* i860 */ 206 case 0x25708086: /* i865 */ 207 case 0x25788086: /* i875P */ 208 case 0x255d8086: /* E7205 */ 209 case 0x25508086: /* E7505 */ 210 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 211 break; 212 default: /* Intel Generic (maybe) */ 213 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 214 } 215} 216 217static int 218agp_intel_attach(device_t dev) 219{ 220 struct agp_intel_softc *sc; 221 struct agp_gatt *gatt; 222 u_int32_t value; 223 int error; 224 225 sc = device_get_softc(dev); 226 227 error = agp_generic_attach(dev); 228 if (error) 229 return (error); 230 231 /* Determine maximum supported aperture size. */ 232 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 233 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 234 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 235 MAX_APSIZE; 236 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 237 sc->current_aperture = sc->initial_aperture = AGP_GET_APERTURE(dev); 238 239 for (;;) { 240 gatt = agp_alloc_gatt(dev); 241 if (gatt) 242 break; 243 244 /* 245 * Probably contigmalloc failure. Try reducing the 246 * aperture so that the gatt size reduces. 247 */ 248 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 249 agp_generic_detach(dev); 250 return (ENOMEM); 251 } 252 } 253 sc->gatt = gatt; 254 255 agp_intel_commit_gatt(dev); 256 257 return (0); 258} 259 260static int 261agp_intel_detach(device_t dev) 262{ 263 struct agp_intel_softc *sc; 264 u_int32_t reg; 265 266 sc = device_get_softc(dev); 267 268 agp_free_cdev(dev); 269 270 /* Disable aperture accesses. */ 271 switch (pci_get_devid(dev)) { 272 case 0x25008086: /* i820 */ 273 case 0x25018086: /* i820 */ 274 reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1); 275 printf("%s: set RDCR to %02x\n", __func__, reg & 0xff); 276 pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1); 277 break; 278 case 0x1a308086: /* i845 */ 279 case 0x25608086: /* i845G */ 280 case 0x33408086: /* i855 */ 281 case 0x35808086: /* i855GM */ 282 case 0x25708086: /* i865 */ 283 case 0x25788086: /* i875P */ 284 reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1); 285 printf("%s: set AGPM to %02x\n", __func__, reg & 0xff); 286 pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1); 287 break; 288 case 0x1a218086: /* i840 */ 289 case 0x25308086: /* i850 */ 290 case 0x25318086: /* i860 */ 291 case 0x255d8086: /* E7205 */ 292 case 0x25508086: /* E7505 */ 293 reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9); 294 printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff); 295 pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2); 296 break; 297 default: /* Intel Generic (maybe) */ 298 reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9); 299 printf("%s: set NBXCFG to %08x\n", __func__, reg); 300 pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4); 301 } 302 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 303 AGP_SET_APERTURE(dev, sc->initial_aperture); 304 agp_free_gatt(sc->gatt); 305 agp_free_res(dev); 306 307 return (0); 308} 309 310static int 311agp_intel_resume(device_t dev) 312{ 313 struct agp_intel_softc *sc; 314 sc = device_get_softc(dev); 315 316 AGP_SET_APERTURE(dev, sc->current_aperture); 317 agp_intel_commit_gatt(dev); 318 return (bus_generic_resume(dev)); 319} 320 321static u_int32_t 322agp_intel_get_aperture(device_t dev) 323{ 324 struct agp_intel_softc *sc; 325 u_int32_t apsize; 326 327 sc = device_get_softc(dev); 328 329 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 330 331 /* 332 * The size is determined by the number of low bits of 333 * register APBASE which are forced to zero. The low 22 bits 334 * are always forced to zero and each zero bit in the apsize 335 * field just read forces the corresponding bit in the 27:22 336 * to be zero. We calculate the aperture size accordingly. 337 */ 338 return ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1); 339} 340 341static int 342agp_intel_set_aperture(device_t dev, u_int32_t aperture) 343{ 344 struct agp_intel_softc *sc; 345 u_int32_t apsize; 346 347 sc = device_get_softc(dev); 348 349 /* 350 * Reverse the magic from get_aperture. 351 */ 352 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 353 354 /* 355 * Double check for sanity. 356 */ 357 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 358 return (EINVAL); 359 360 sc->current_aperture = apsize; 361 362 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 363 364 return (0); 365} 366 367static int 368agp_intel_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 369{ 370 struct agp_intel_softc *sc; 371 372 sc = device_get_softc(dev); 373 374 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 375 return (EINVAL); 376 377 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 378 return (0); 379} 380 381static int 382agp_intel_unbind_page(device_t dev, vm_offset_t offset) 383{ 384 struct agp_intel_softc *sc; 385 386 sc = device_get_softc(dev); 387 388 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 389 return (EINVAL); 390 391 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 392 return (0); 393} 394 395static void 396agp_intel_flush_tlb(device_t dev) 397{ 398 u_int32_t val; 399 400 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 401 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 402 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 403} 404 405static device_method_t agp_intel_methods[] = { 406 /* Device interface */ 407 DEVMETHOD(device_probe, agp_intel_probe), 408 DEVMETHOD(device_attach, agp_intel_attach), 409 DEVMETHOD(device_detach, agp_intel_detach), 410 DEVMETHOD(device_shutdown, bus_generic_shutdown), 411 DEVMETHOD(device_suspend, bus_generic_suspend), 412 DEVMETHOD(device_resume, agp_intel_resume), 413 414 /* AGP interface */ 415 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 416 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 417 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 418 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 419 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 420 DEVMETHOD(agp_enable, agp_generic_enable), 421 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 422 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 423 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 424 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 425 426 { 0, 0 } 427}; 428 429static driver_t agp_intel_driver = { 430 "agp", 431 agp_intel_methods, 432 sizeof(struct agp_intel_softc), 433}; 434 435static devclass_t agp_devclass; 436 437DRIVER_MODULE(agp_intel, hostb, agp_intel_driver, agp_devclass, 0, 0); 438MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 439MODULE_DEPEND(agp_intel, pci, 1, 1, 1); 440