rpi2.dts revision 314522
1251881Speter/* 2251881Speter * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@bluezbox.com> 3251881Speter * 4251881Speter * Redistribution and use in source and binary forms, with or without 5251881Speter * modification, are permitted provided that the following conditions 6251881Speter * are met: 7251881Speter * 1. Redistributions of source code must retain the above copyright 8251881Speter * notice, this list of conditions and the following disclaimer. 9251881Speter * 2. Redistributions in binary form must reproduce the above copyright 10251881Speter * notice, this list of conditions and the following disclaimer in the 11251881Speter * documentation and/or other materials provided with the distribution. 12251881Speter * 13251881Speter * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14251881Speter * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15251881Speter * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16251881Speter * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17251881Speter * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18251881Speter * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19251881Speter * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20251881Speter * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21251881Speter * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22251881Speter * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23251881Speter * SUCH DAMAGE. 24251881Speter * 25251881Speter * $FreeBSD: stable/11/sys/boot/fdt/dts/arm/rpi2.dts 314522 2017-03-01 21:48:15Z ian $ 26251881Speter */ 27251881Speter/dts-v1/; 28251881Speter 29251881Speter/include/ "bcm2836.dtsi" 30251881Speter 31251881Speter/ { 32251881Speter model = "Raspberry Pi 2 Model B"; 33251881Speter compatible = "brcm,bcm2709"; 34251881Speter 35251881Speter memreserve = <0x08000000 0x08000000>; /* Set by VideoCore */ 36251881Speter 37251881Speter cpus { 38251881Speter #address-cells = <1>; 39251881Speter #size-cells = <0>; 40251881Speter cpu@0 { 41251881Speter compatible = "arm,cortex-a7"; 42251881Speter device_type = "cpu"; 43299742Sdim reg = <0xf00>; /* CPU ID=0xf00 */ 44251881Speter clock-frequency = <800000000>; /* 800MHz */ 45251881Speter }; 46251881Speter cpu@1 { 47251881Speter compatible = "arm,cortex-a7"; 48251881Speter device_type = "cpu"; 49251881Speter reg = <0xf01>; /* CPU ID=0xf01 */ 50251881Speter clock-frequency = <800000000>; /* 800MHz */ 51251881Speter }; 52251881Speter cpu@2 { 53251881Speter compatible = "arm,cortex-a7"; 54251881Speter device_type = "cpu"; 55251881Speter reg = <0xf02>; /* CPU ID=0xf02 */ 56251881Speter clock-frequency = <800000000>; /* 800MHz */ 57251881Speter }; 58251881Speter cpu@3 { 59251881Speter compatible = "arm,cortex-a7"; 60251881Speter device_type = "cpu"; 61251881Speter reg = <0xf03>; /* CPU ID=0xf03 */ 62251881Speter clock-frequency = <800000000>; /* 800MHz */ 63251881Speter }; 64251881Speter }; 65251881Speter 66251881Speter memory { 67251881Speter device_type = "memory"; 68251881Speter reg = <0 0x8000000>; /* 128MB, Set by VideoCore */ 69251881Speter 70251881Speter }; 71251881Speter 72251881Speter system { 73251881Speter revision = <0>; /* Set by VideoCore */ 74251881Speter serial = <0 0>; /* Set by VideoCore */ 75251881Speter }; 76251881Speter 77299742Sdim axi { 78299742Sdim gpio: gpio { 79299742Sdim /* BSC0 */ 80299742Sdim pins_bsc0_a: bsc0_a { 81299742Sdim broadcom,function = "ALT0"; 82251881Speter }; 83299742Sdim 84299742Sdim pins_bsc0_b: bsc0_b { 85299742Sdim broadcom,function = "ALT0"; 86299742Sdim }; 87299742Sdim 88299742Sdim pins_bsc0_c: bsc0_c { 89299742Sdim broadcom,function = "ALT1"; 90299742Sdim }; 91299742Sdim 92299742Sdim /* BSC1 */ 93299742Sdim pins_bsc1_a: bsc1_a { 94299742Sdim broadcom,function = "ALT0"; 95299742Sdim }; 96251881Speter 97251881Speter pins_bsc1_b: bsc1_b { 98251881Speter broadcom,function = "ALT2"; 99251881Speter }; 100251881Speter 101251881Speter /* GPCLK0 */ 102251881Speter pins_gpclk0_a: gpclk0_a { 103251881Speter broadcom,function = "ALT0"; 104251881Speter }; 105251881Speter 106251881Speter pins_gpclk0_b: gpclk0_b { 107251881Speter broadcom,function = "ALT5"; 108299742Sdim }; 109299742Sdim 110299742Sdim pins_gpclk0_c: gpclk0_c { 111299742Sdim broadcom,function = "ALT0"; 112299742Sdim }; 113299742Sdim 114299742Sdim pins_gpclk0_d: gpclk0_d { 115299742Sdim broadcom,function = "ALT0"; 116299742Sdim }; 117299742Sdim 118299742Sdim /* GPCLK1 */ 119299742Sdim pins_gpclk1_a: gpclk1_a { 120299742Sdim broadcom,function = "ALT0"; 121299742Sdim }; 122299742Sdim 123299742Sdim pins_gpclk1_b: gpclk1_b { 124251881Speter broadcom,function = "ALT5"; 125251881Speter }; 126251881Speter 127251881Speter pins_gpclk1_c: gpclk1_c { 128251881Speter broadcom,function = "ALT0"; 129251881Speter }; 130251881Speter 131251881Speter pins_gpclk1_d: gpclk1_d { 132251881Speter broadcom,function = "ALT0"; 133 }; 134 135 /* GPCLK2 */ 136 pins_gpclk2_a: gpclk2_a { 137 broadcom,function = "ALT0"; 138 }; 139 140 pins_gpclk2_b: gpclk2_b { 141 broadcom,function = "ALT0"; 142 }; 143 144 /* SPI0 */ 145 pins_spi0_a: spi0_a { 146 broadcom,function = "ALT0"; 147 }; 148 149 pins_spi0_b: spi0_b { 150 broadcom,function = "ALT0"; 151 }; 152 153 /* PWM */ 154 pins_pwm0_a: pwm0_a { 155 broadcom,function = "ALT0"; 156 }; 157 158 pins_pwm0_b: pwm0_b { 159 broadcom,function = "ALT5"; 160 }; 161 162 pins_pwm0_c: pwm0_c { 163 broadcom,function = "ALT0"; 164 }; 165 166 pins_pwm1_a: pwm1_a { 167 broadcom,function = "ALT0"; 168 }; 169 170 pins_pwm1_b: pwm1_b { 171 broadcom,function = "ALT5"; 172 }; 173 174 pins_pwm1_c: pwm1_c { 175 broadcom,function = "ALT0"; 176 }; 177 178 pins_pwm1_d: pwm1_d { 179 broadcom,function = "ALT0"; 180 }; 181 182 /* UART0 */ 183 pins_uart0_a: uart0_a { 184 broadcom,function = "ALT0"; 185 }; 186 187 pins_uart0_b: uart0_b { 188 broadcom,function = "ALT3"; 189 }; 190 191 pins_uart0_c: uart0_c { 192 broadcom,function = "ALT2"; 193 }; 194 195 pins_uart0_fc_a: uart0_fc_a { 196 broadcom,function = "ALT3"; 197 }; 198 199 pins_uart0_fc_b: uart0_fc_b { 200 broadcom,function = "ALT3"; 201 }; 202 203 pins_uart0_fc_c: uart0_fc_c { 204 broadcom,function = "ALT2"; 205 }; 206 207 /* PCM */ 208 pins_pcm_a: pcm_a { 209 broadcom,function = "ALT0"; 210 }; 211 212 pins_pcm_b: pcm_b { 213 broadcom,function = "ALT2"; 214 }; 215 216 /* Secondary Address Bus */ 217 pins_sm_addr_a: sm_addr_a { 218 broadcom,function = "ALT1"; 219 }; 220 221 pins_sm_addr_b: sm_addr_b { 222 broadcom,function = "ALT1"; 223 }; 224 225 pins_sm_ctl_a: sm_ctl_a { 226 broadcom,function = "ALT1"; 227 }; 228 229 pins_sm_ctl_b: sm_ctl_b { 230 broadcom,function = "ALT1"; 231 }; 232 233 pins_sm_data_8bit_a: sm_data_8bit_a { 234 broadcom,function = "ALT1"; 235 }; 236 237 pins_sm_data_8bit_b: sm_data_8bit_b { 238 broadcom,function = "ALT1"; 239 }; 240 241 pins_sm_data_16bit: sm_data_16bit { 242 broadcom,function = "ALT1"; 243 }; 244 245 pins_sm_data_18bit: sm_data_18bit { 246 broadcom,function = "ALT1"; 247 }; 248 249 /* BSCSL */ 250 pins_bscsl: bscsl { 251 broadcom,function = "ALT3"; 252 }; 253 254 /* SPISL */ 255 pins_spisl: spisl { 256 broadcom,function = "ALT3"; 257 }; 258 259 /* SPI1 */ 260 pins_spi1: spi1 { 261 broadcom,function = "ALT4"; 262 }; 263 264 /* UART1 */ 265 pins_uart1_a: uart1_a { 266 broadcom,function = "ALT5"; 267 }; 268 269 pins_uart1_b: uart1_b { 270 broadcom,function = "ALT5"; 271 }; 272 273 pins_uart1_c: uart1_c { 274 broadcom,function = "ALT5"; 275 }; 276 277 pins_uart1_fc_a: uart1_fc_a { 278 broadcom,function = "ALT5"; 279 }; 280 281 pins_uart1_fc_b: uart1_fc_b { 282 broadcom,function = "ALT5"; 283 }; 284 285 pins_uart1_fc_c: uart1_fc_c { 286 broadcom,function = "ALT5"; 287 }; 288 289 /* SPI2 */ 290 pins_spi2: spi2 { 291 broadcom,function = "ALT4"; 292 }; 293 294 /* ARM JTAG */ 295 pins_arm_jtag_trst: arm_jtag_trst { 296 broadcom,function = "ALT4"; 297 }; 298 299 pins_arm_jtag_a: arm_jtag_a { 300 broadcom,function = "ALT5"; 301 }; 302 303 pins_arm_jtag_b: arm_jtag_b { 304 broadcom,function = "ALT4"; 305 }; 306 307 /* Reserved */ 308 pins_reserved: reserved { 309 broadcom,function = "ALT3"; 310 }; 311 }; 312 usb { 313 hub { 314 compatible = "usb,hub", "usb,device"; 315 reg = <0x00000001>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 ethernet: ethernet { 319 compatible = "net,ethernet", 320 "usb,device"; 321 reg = <0x00000001>; 322 mac-address = [00 00 00 00 00 00]; 323 }; 324 }; 325 326 }; 327 }; 328 329 display { 330 compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb"; 331 332 broadcom,vc-mailbox = <&vc_mbox>; 333 broadcom,vc-channel = <1>; 334 335 broadcom,width = <0>; /* Set by VideoCore */ 336 broadcom,height = <0>; /* Set by VideoCore */ 337 broadcom,depth = <0>; /* Set by VideoCore */ 338 }; 339 340 rpi_ft5406 { 341 compatible = "rpi,rpi-ft5406"; 342 status = "okay"; 343 }; 344 345 leds { 346 compatible = "gpio-leds"; 347 348 pwr { 349 label = "pwr"; 350 gpios = <&gpio 35 0>; 351 }; 352 353 act { 354 label = "act"; 355 gpios = <&gpio 47 0>; 356 }; 357 }; 358 359 power: regulator { 360 compatible = "broadcom,bcm2835-power-mgr", 361 "broadcom,bcm2708-power-mgr", 362 "simple-bus"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 366 broadcom,vc-mailbox = <&vc_mbox>; 367 broadcom,vc-channel = <0>; 368 369 regulator-name = "VideoCore"; 370 regulator-min-microvolt = <5000000>; 371 regulator-max-microvolt = <5000000>; 372 regulator-always-on = <1>; 373 374 sd_card_power: regulator@0 { 375 compatible = "broadcom,bcm2835-power-dev", 376 "broadcom,bcm2708-power-dev"; 377 reg = <0>; 378 379 vin-supply = <&power>; 380 regulator-name = "SD Card"; 381 regulator-min-microvolt = <3300000>; 382 regulator-max-microvolt = <3300000>; 383 }; 384 385 /* This is for the controller itself, not the root port */ 386 usb_hcd_power: regulator@3 { 387 compatible = "broadcom,bcm2835-power-dev", 388 "broadcom,bcm2708-power-dev"; 389 reg = <3>; 390 391 vin-supply = <&power>; 392 regulator-name = "USB HCD"; 393 regulator-min-microvolt = <5000000>; 394 regulator-max-microvolt = <5000000>; 395 }; 396 }; 397 398 aliases { 399 uart0 = &uart0; 400 ethernet0 = ðernet; 401 }; 402 403 chosen { 404 bootargs = ""; /* Set by VideoCore */ 405 stdin = "uart0"; 406 stdout = "uart0"; 407 }; 408 409 __overrides__ { 410 cache_line_size = <&vchiq>, "cache-line-size:0"; 411 }; 412}; 413