zy7_slcr.c revision 314503
1/*- 2 * Copyright (c) 2013 Thomas Skibo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/arm/xilinx/zy7_slcr.c 314503 2017-03-01 18:53:05Z ian $ 27 */ 28 29/* 30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff. 31 * In the future, maybe MIO control, clock control, etc. could go here. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: stable/11/sys/arm/xilinx/zy7_slcr.c 314503 2017-03-01 18:53:05Z ian $"); 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/conf.h> 43#include <sys/kernel.h> 44#include <sys/module.h> 45#include <sys/lock.h> 46#include <sys/mutex.h> 47#include <sys/resource.h> 48#include <sys/sysctl.h> 49#include <sys/rman.h> 50 51#include <machine/bus.h> 52#include <machine/resource.h> 53#include <machine/stdarg.h> 54 55#include <dev/ofw/ofw_bus.h> 56#include <dev/ofw/ofw_bus_subr.h> 57 58#include <arm/xilinx/zy7_slcr.h> 59 60struct zy7_slcr_softc { 61 device_t dev; 62 struct mtx sc_mtx; 63 struct resource *mem_res; 64}; 65 66static struct zy7_slcr_softc *zy7_slcr_softc_p; 67extern void (*zynq7_cpu_reset); 68 69#define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 70#define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 71#define ZSLCR_LOCK_INIT(sc) \ 72 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 73 "zy7_slcr", MTX_DEF) 74#define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 75 76#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) 77#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) 78 79#define ZYNQ_DEFAULT_PS_CLK_FREQUENCY 33333333 /* 33.3 Mhz */ 80 81SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000"); 82 83static char zynq_bootmode[64]; 84SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0, 85 "Zynq boot mode"); 86 87static char zynq_pssid[100]; 88SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0, 89 "Zynq PSS IDCODE"); 90 91static uint32_t zynq_reboot_status; 92SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status, 93 0, "Zynq REBOOT_STATUS register"); 94 95static int ps_clk_frequency; 96SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency, 97 0, "Zynq PS_CLK Frequency"); 98 99static int io_pll_frequency; 100SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency, 101 0, "Zynq IO PLL Frequency"); 102 103static int arm_pll_frequency; 104SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD, 105 &arm_pll_frequency, 0, "Zynq ARM PLL Frequency"); 106 107static int ddr_pll_frequency; 108SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD, 109 &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency"); 110 111static void 112zy7_slcr_unlock(struct zy7_slcr_softc *sc) 113{ 114 115 /* Unlock SLCR with magic number. */ 116 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); 117} 118 119static void 120zy7_slcr_lock(struct zy7_slcr_softc *sc) 121{ 122 123 /* Lock SLCR with magic number. */ 124 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); 125} 126 127static void 128zy7_slcr_cpu_reset(void) 129{ 130 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 131 132 /* Unlock SLCR registers. */ 133 zy7_slcr_unlock(sc); 134 135 /* This has something to do with a work-around so the fsbl will load 136 * the bitstream after soft-reboot. It's very important. 137 */ 138 WR4(sc, ZY7_SLCR_REBOOT_STAT, 139 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff); 140 141 /* Soft reset */ 142 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); 143 144 for (;;) 145 ; 146} 147 148/* Assert PL resets and disable level shifters in preparation of programming 149 * the PL (FPGA) section. Called from zy7_devcfg.c. 150 */ 151void 152zy7_slcr_preload_pl(void) 153{ 154 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 155 156 if (!sc) 157 return; 158 159 ZSLCR_LOCK(sc); 160 161 /* Unlock SLCR registers. */ 162 zy7_slcr_unlock(sc); 163 164 /* Assert top level output resets. */ 165 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); 166 167 /* Disable all level shifters. */ 168 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); 169 170 /* Lock SLCR registers. */ 171 zy7_slcr_lock(sc); 172 173 ZSLCR_UNLOCK(sc); 174} 175 176/* After PL configuration, enable level shifters and deassert top-level 177 * PL resets. Called from zy7_devcfg.c. Optionally, the level shifters 178 * can be left disabled but that's rare of an FPGA application. That option 179 * is controlled by a sysctl in the devcfg driver. 180 */ 181void 182zy7_slcr_postload_pl(int en_level_shifters) 183{ 184 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 185 186 if (!sc) 187 return; 188 189 ZSLCR_LOCK(sc); 190 191 /* Unlock SLCR registers. */ 192 zy7_slcr_unlock(sc); 193 194 if (en_level_shifters) 195 /* Enable level shifters. */ 196 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); 197 198 /* Deassert top level output resets. */ 199 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); 200 201 /* Lock SLCR registers. */ 202 zy7_slcr_lock(sc); 203 204 ZSLCR_UNLOCK(sc); 205} 206 207/* Override cgem_set_refclk() in gigabit ethernet driver 208 * (sys/dev/cadence/if_cgem.c). This function is called to 209 * request a change in the gem's reference clock speed. 210 */ 211int 212cgem_set_ref_clk(int unit, int frequency) 213{ 214 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 215 int div0, div1; 216 217 if (!sc) 218 return (-1); 219 220 /* Find suitable divisor pairs. Round result to nearest khz 221 * to test for match. 222 */ 223 for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) { 224 div0 = (io_pll_frequency + div1 * frequency / 2) / 225 div1 / frequency; 226 if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX && 227 ((io_pll_frequency / div0 / div1) + 500) / 1000 == 228 (frequency + 500) / 1000) 229 break; 230 } 231 232 if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX) 233 return (-1); 234 235 ZSLCR_LOCK(sc); 236 237 /* Unlock SLCR registers. */ 238 zy7_slcr_unlock(sc); 239 240 /* Modify GEM reference clock. */ 241 WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL, 242 (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) | 243 (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) | 244 ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL | 245 ZY7_SLCR_GEM_CLK_CTRL_CLKACT); 246 247 /* Lock SLCR registers. */ 248 zy7_slcr_lock(sc); 249 250 ZSLCR_UNLOCK(sc); 251 252 return (0); 253} 254 255/* 256 * PL clocks management function 257 */ 258int 259zy7_pl_fclk_set_source(int unit, int source) 260{ 261 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 262 uint32_t reg; 263 264 if (!sc) 265 return (-1); 266 267 ZSLCR_LOCK(sc); 268 269 /* Unlock SLCR registers. */ 270 zy7_slcr_unlock(sc); 271 272 /* Modify FPGAx source. */ 273 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 274 reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK); 275 reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT); 276 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); 277 278 /* Lock SLCR registers. */ 279 zy7_slcr_lock(sc); 280 281 ZSLCR_UNLOCK(sc); 282 283 return (0); 284} 285 286int 287zy7_pl_fclk_get_source(int unit) 288{ 289 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 290 uint32_t reg; 291 int source; 292 293 if (!sc) 294 return (-1); 295 296 ZSLCR_LOCK(sc); 297 298 /* Modify GEM reference clock. */ 299 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 300 source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >> 301 ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT; 302 303 /* ZY7_PL_FCLK_SRC_IO is actually b0x */ 304 if ((source & 2) == 0) 305 source = ZY7_PL_FCLK_SRC_IO; 306 307 ZSLCR_UNLOCK(sc); 308 309 return (source); 310} 311 312int 313zy7_pl_fclk_set_freq(int unit, int frequency) 314{ 315 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 316 int div0, div1; 317 int base_frequency; 318 uint32_t reg; 319 int source; 320 321 if (!sc) 322 return (-1); 323 324 source = zy7_pl_fclk_get_source(unit); 325 switch (source) { 326 case ZY7_PL_FCLK_SRC_IO: 327 base_frequency = io_pll_frequency; 328 break; 329 330 case ZY7_PL_FCLK_SRC_ARM: 331 base_frequency = arm_pll_frequency; 332 break; 333 334 case ZY7_PL_FCLK_SRC_DDR: 335 base_frequency = ddr_pll_frequency; 336 break; 337 338 default: 339 return (-1); 340 } 341 342 /* Find suitable divisor pairs. Round result to nearest khz 343 * to test for match. 344 */ 345 for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) { 346 div0 = (base_frequency + div1 * frequency / 2) / 347 div1 / frequency; 348 if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX && 349 ((base_frequency / div0 / div1) + 500) / 1000 == 350 (frequency + 500) / 1000) 351 break; 352 } 353 354 if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX) 355 return (-1); 356 357 ZSLCR_LOCK(sc); 358 359 /* Unlock SLCR registers. */ 360 zy7_slcr_unlock(sc); 361 362 /* Modify FPGAx reference clock. */ 363 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 364 reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK | 365 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK); 366 reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) | 367 (div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT); 368 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); 369 370 /* Lock SLCR registers. */ 371 zy7_slcr_lock(sc); 372 373 ZSLCR_UNLOCK(sc); 374 375 return (base_frequency / div0 / div1); 376} 377 378int 379zy7_pl_fclk_get_freq(int unit) 380{ 381 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 382 int div0, div1; 383 int base_frequency; 384 int frequency; 385 uint32_t reg; 386 int source; 387 388 if (!sc) 389 return (-1); 390 391 source = zy7_pl_fclk_get_source(unit); 392 switch (source) { 393 case ZY7_PL_FCLK_SRC_IO: 394 base_frequency = io_pll_frequency; 395 break; 396 397 case ZY7_PL_FCLK_SRC_ARM: 398 base_frequency = arm_pll_frequency; 399 break; 400 401 case ZY7_PL_FCLK_SRC_DDR: 402 base_frequency = ddr_pll_frequency; 403 break; 404 405 default: 406 return (-1); 407 } 408 409 ZSLCR_LOCK(sc); 410 411 /* Modify FPGAx reference clock. */ 412 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 413 div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >> 414 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT; 415 div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >> 416 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT; 417 418 ZSLCR_UNLOCK(sc); 419 420 if (div0 == 0) 421 div0 = 1; 422 423 if (div1 == 0) 424 div1 = 1; 425 426 frequency = (base_frequency / div0 / div1); 427 /* Round to KHz */ 428 frequency = (frequency + 500) / 1000; 429 frequency = frequency * 1000; 430 431 return (frequency); 432} 433 434int 435zy7_pl_fclk_enable(int unit) 436{ 437 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 438 439 if (!sc) 440 return (-1); 441 442 ZSLCR_LOCK(sc); 443 444 /* Unlock SLCR registers. */ 445 zy7_slcr_unlock(sc); 446 447 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); 448 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0); 449 450 /* Lock SLCR registers. */ 451 zy7_slcr_lock(sc); 452 453 ZSLCR_UNLOCK(sc); 454 455 return (0); 456} 457 458int 459zy7_pl_fclk_disable(int unit) 460{ 461 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 462 463 if (!sc) 464 return (-1); 465 466 ZSLCR_LOCK(sc); 467 468 /* Unlock SLCR registers. */ 469 zy7_slcr_unlock(sc); 470 471 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); 472 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1); 473 474 /* Lock SLCR registers. */ 475 zy7_slcr_lock(sc); 476 477 ZSLCR_UNLOCK(sc); 478 479 return (0); 480} 481 482int 483zy7_pl_fclk_enabled(int unit) 484{ 485 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 486 uint32_t reg; 487 488 if (!sc) 489 return (-1); 490 491 ZSLCR_LOCK(sc); 492 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit)); 493 ZSLCR_UNLOCK(sc); 494 495 return !(reg & 1); 496} 497 498int 499zy7_pl_level_shifters_enabled() 500{ 501 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 502 503 uint32_t reg; 504 505 if (!sc) 506 return (-1); 507 508 ZSLCR_LOCK(sc); 509 reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN); 510 ZSLCR_UNLOCK(sc); 511 512 return (reg == ZY7_SLCR_LVL_SHFTR_EN_ALL); 513} 514 515void 516zy7_pl_level_shifters_enable() 517{ 518 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 519 520 if (!sc) 521 return; 522 523 ZSLCR_LOCK(sc); 524 zy7_slcr_unlock(sc); 525 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); 526 zy7_slcr_lock(sc); 527 ZSLCR_UNLOCK(sc); 528} 529 530void 531zy7_pl_level_shifters_disable() 532{ 533 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 534 535 if (!sc) 536 return; 537 538 ZSLCR_LOCK(sc); 539 zy7_slcr_unlock(sc); 540 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); 541 zy7_slcr_lock(sc); 542 ZSLCR_UNLOCK(sc); 543} 544 545static int 546zy7_slcr_probe(device_t dev) 547{ 548 549 if (!ofw_bus_status_okay(dev)) 550 return (ENXIO); 551 552 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr")) 553 return (ENXIO); 554 555 device_set_desc(dev, "Zynq-7000 slcr block"); 556 return (0); 557} 558 559static int 560zy7_slcr_attach(device_t dev) 561{ 562 struct zy7_slcr_softc *sc = device_get_softc(dev); 563 int rid; 564 phandle_t node; 565 pcell_t cell; 566 uint32_t bootmode; 567 uint32_t pss_idcode; 568 uint32_t arm_pll_ctrl; 569 uint32_t ddr_pll_ctrl; 570 uint32_t io_pll_ctrl; 571 static char *bootdev_names[] = { 572 "JTAG", "Quad-SPI", "NOR", "(3?)", 573 "NAND", "SD Card", "(6?)", "(7?)" 574 }; 575 576 /* Allow only one attach. */ 577 if (zy7_slcr_softc_p != NULL) 578 return (ENXIO); 579 580 sc->dev = dev; 581 582 ZSLCR_LOCK_INIT(sc); 583 584 /* Get memory resource. */ 585 rid = 0; 586 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 587 RF_ACTIVE); 588 if (sc->mem_res == NULL) { 589 device_printf(dev, "could not allocate memory resources.\n"); 590 return (ENOMEM); 591 } 592 593 /* Hook up cpu_reset. */ 594 zy7_slcr_softc_p = sc; 595 zynq7_cpu_reset = zy7_slcr_cpu_reset; 596 597 /* Read info and set sysctls. */ 598 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE); 599 snprintf(zynq_bootmode, sizeof(zynq_bootmode), 600 "0x%x: boot device: %s", bootmode, 601 bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]); 602 603 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE); 604 snprintf(zynq_pssid, sizeof(zynq_pssid), 605 "0x%x: manufacturer: 0x%x device: 0x%x " 606 "family: 0x%x sub-family: 0x%x rev: 0x%x", 607 pss_idcode, 608 (pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >> 609 ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT, 610 (pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >> 611 ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT, 612 (pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >> 613 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT, 614 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >> 615 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT, 616 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >> 617 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT); 618 619 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT); 620 621 /* Derive PLL frequencies from PS_CLK. */ 622 node = ofw_bus_get_node(dev); 623 if (OF_getencprop(node, "clock-frequency", &cell, sizeof(cell)) > 0) 624 ps_clk_frequency = cell; 625 else 626 ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY; 627 628 arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL); 629 ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL); 630 io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL); 631 632 /* Determine ARM PLL frequency. */ 633 if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 && 634 (arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) || 635 ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 && 636 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0)) 637 /* PLL is bypassed. */ 638 arm_pll_frequency = ps_clk_frequency; 639 else 640 arm_pll_frequency = ps_clk_frequency * 641 ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >> 642 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT); 643 644 /* Determine DDR PLL frequency. */ 645 if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 && 646 (ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) || 647 ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 && 648 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0)) 649 /* PLL is bypassed. */ 650 ddr_pll_frequency = ps_clk_frequency; 651 else 652 ddr_pll_frequency = ps_clk_frequency * 653 ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >> 654 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT); 655 656 /* Determine IO PLL frequency. */ 657 if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 && 658 (io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) || 659 ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 && 660 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0)) 661 /* PLL is bypassed. */ 662 io_pll_frequency = ps_clk_frequency; 663 else 664 io_pll_frequency = ps_clk_frequency * 665 ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >> 666 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT); 667 668 /* Lock SLCR registers. */ 669 zy7_slcr_lock(sc); 670 671 return (0); 672} 673 674static int 675zy7_slcr_detach(device_t dev) 676{ 677 struct zy7_slcr_softc *sc = device_get_softc(dev); 678 679 bus_generic_detach(dev); 680 681 /* Release memory resource. */ 682 if (sc->mem_res != NULL) 683 bus_release_resource(dev, SYS_RES_MEMORY, 684 rman_get_rid(sc->mem_res), sc->mem_res); 685 686 zy7_slcr_softc_p = NULL; 687 zynq7_cpu_reset = NULL; 688 689 ZSLCR_LOCK_DESTROY(sc); 690 691 return (0); 692} 693 694static device_method_t zy7_slcr_methods[] = { 695 /* device_if */ 696 DEVMETHOD(device_probe, zy7_slcr_probe), 697 DEVMETHOD(device_attach, zy7_slcr_attach), 698 DEVMETHOD(device_detach, zy7_slcr_detach), 699 700 DEVMETHOD_END 701}; 702 703static driver_t zy7_slcr_driver = { 704 "zy7_slcr", 705 zy7_slcr_methods, 706 sizeof(struct zy7_slcr_softc), 707}; 708static devclass_t zy7_slcr_devclass; 709 710DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0); 711MODULE_VERSION(zy7_slcr, 1); 712