ti_sdhci.c revision 314508
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/arm/ti/ti_sdhci.c 314508 2017-03-01 20:22:25Z ian $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/gpio.h> 35#include <sys/kernel.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/resource.h> 39#include <sys/rman.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <machine/intr.h> 46 47#include <dev/ofw/ofw_bus.h> 48#include <dev/ofw/ofw_bus_subr.h> 49 50#include <dev/mmc/bridge.h> 51#include <dev/mmc/mmcreg.h> 52#include <dev/mmc/mmcbrvar.h> 53 54#include <dev/sdhci/sdhci.h> 55#include <dev/sdhci/sdhci_fdt_gpio.h> 56#include "sdhci_if.h" 57 58#include <arm/ti/ti_cpuid.h> 59#include <arm/ti/ti_prcm.h> 60#include <arm/ti/ti_hwmods.h> 61#include "gpio_if.h" 62 63struct ti_sdhci_softc { 64 device_t dev; 65 struct sdhci_fdt_gpio * gpio; 66 struct resource * mem_res; 67 struct resource * irq_res; 68 void * intr_cookie; 69 struct sdhci_slot slot; 70 clk_ident_t mmchs_clk_id; 71 uint32_t mmchs_reg_off; 72 uint32_t sdhci_reg_off; 73 uint32_t baseclk_hz; 74 uint32_t wp_gpio_pin; 75 uint32_t cmd_and_mode; 76 uint32_t sdhci_clkdiv; 77 boolean_t disable_highspeed; 78 boolean_t force_card_present; 79 boolean_t disable_readonly; 80}; 81 82/* 83 * Table of supported FDT compat strings. 84 * 85 * Note that "ti,mmchs" is our own invention, and should be phased out in favor 86 * of the documented names. 87 * 88 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 89 */ 90static struct ofw_compat_data compat_data[] = { 91 {"ti,omap3-hsmmc", 1}, 92 {"ti,omap4-hsmmc", 1}, 93 {"ti,mmchs", 1}, 94 {NULL, 0}, 95}; 96 97/* 98 * The MMCHS hardware has a few control and status registers at the beginning of 99 * the device's memory map, followed by the standard sdhci register block. 100 * Different SoCs have the register blocks at different offsets from the 101 * beginning of the device. Define some constants to map out the registers we 102 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 103 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 104 */ 105#define OMAP3_MMCHS_REG_OFFSET 0x000 106#define OMAP4_MMCHS_REG_OFFSET 0x100 107#define AM335X_MMCHS_REG_OFFSET 0x100 108#define SDHCI_REG_OFFSET 0x100 109 110#define MMCHS_SYSCONFIG 0x010 111#define MMCHS_SYSCONFIG_RESET (1 << 1) 112#define MMCHS_SYSSTATUS 0x014 113#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 114#define MMCHS_CON 0x02C 115#define MMCHS_CON_DW8 (1 << 5) 116#define MMCHS_CON_DVAL_8_4MS (3 << 9) 117#define MMCHS_CON_OD (1 << 0) 118#define MMCHS_SYSCTL 0x12C 119#define MMCHS_SYSCTL_CLKD_MASK 0x3FF 120#define MMCHS_SYSCTL_CLKD_SHIFT 6 121#define MMCHS_SD_CAPA 0x140 122#define MMCHS_SD_CAPA_VS18 (1 << 26) 123#define MMCHS_SD_CAPA_VS30 (1 << 25) 124#define MMCHS_SD_CAPA_VS33 (1 << 24) 125 126static inline uint32_t 127ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 128{ 129 130 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 131} 132 133static inline void 134ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 135{ 136 137 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 138} 139 140static inline uint32_t 141RD4(struct ti_sdhci_softc *sc, bus_size_t off) 142{ 143 144 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 145} 146 147static inline void 148WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 149{ 150 151 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 152} 153 154static uint8_t 155ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 156{ 157 struct ti_sdhci_softc *sc = device_get_softc(dev); 158 159 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 160} 161 162static uint16_t 163ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 164{ 165 struct ti_sdhci_softc *sc = device_get_softc(dev); 166 uint32_t clkdiv, val32; 167 168 /* 169 * The MMCHS hardware has a non-standard interpretation of the sdclock 170 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 171 * but doesn't split them into low:high fields. Instead they're a 172 * single number in the range 0..1023 and the number is exactly the 173 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 174 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking 175 * here extracts the MMCHS representation from the hardware word, cleans 176 * those bits out, applies the 2N adjustment, and plugs the result into 177 * the bit positions for the 2.0 or 3.0 divisor in the returned register 178 * value. The ti_sdhci_write_2() routine performs the opposite 179 * transformation when the SDHCI driver writes to the register. 180 */ 181 if (off == SDHCI_CLOCK_CONTROL) { 182 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 183 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & 184 MMCHS_SYSCTL_CLKD_MASK) / 2; 185 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); 186 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 187 if (slot->version >= SDHCI_SPEC_300) 188 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & 189 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; 190 return (val32 & 0xffff); 191 } 192 193 /* 194 * Standard 32-bit handling of command and transfer mode. 195 */ 196 if (off == SDHCI_TRANSFER_MODE) { 197 return (sc->cmd_and_mode >> 16); 198 } else if (off == SDHCI_COMMAND_FLAGS) { 199 return (sc->cmd_and_mode & 0x0000ffff); 200 } 201 202 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 203} 204 205static uint32_t 206ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 207{ 208 struct ti_sdhci_softc *sc = device_get_softc(dev); 209 uint32_t val32; 210 211 val32 = RD4(sc, off); 212 213 /* 214 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip 215 * that flag from the returned capabilities. 216 */ 217 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) 218 val32 &= ~SDHCI_CAN_DO_HISPD; 219 220 /* 221 * Force the card-present state if necessary. 222 */ 223 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 224 val32 |= SDHCI_CARD_PRESENT; 225 226 return (val32); 227} 228 229static void 230ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 231 uint32_t *data, bus_size_t count) 232{ 233 struct ti_sdhci_softc *sc = device_get_softc(dev); 234 235 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 236} 237 238static void 239ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 240 uint8_t val) 241{ 242 struct ti_sdhci_softc *sc = device_get_softc(dev); 243 uint32_t val32; 244 245 val32 = RD4(sc, off & ~3); 246 val32 &= ~(0xff << (off & 3) * 8); 247 val32 |= (val << (off & 3) * 8); 248 249 WR4(sc, off & ~3, val32); 250} 251 252static void 253ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 254 uint16_t val) 255{ 256 struct ti_sdhci_softc *sc = device_get_softc(dev); 257 uint32_t clkdiv, val32; 258 259 /* 260 * Translate between the hardware and SDHCI 2.0 or 3.0 representations 261 * of the clock divisor. See the comments in ti_sdhci_read_2() for 262 * details. 263 */ 264 if (off == SDHCI_CLOCK_CONTROL) { 265 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 266 if (slot->version >= SDHCI_SPEC_300) 267 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & 268 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 269 clkdiv *= 2; 270 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) 271 clkdiv = MMCHS_SYSCTL_CLKD_MASK; 272 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 273 val32 &= 0xffff0000; 274 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << 275 MMCHS_SYSCTL_CLKD_SHIFT); 276 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; 277 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 278 return; 279 } 280 281 /* 282 * Standard 32-bit handling of command and transfer mode. 283 */ 284 if (off == SDHCI_TRANSFER_MODE) { 285 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 286 ((uint32_t)val & 0x0000ffff); 287 return; 288 } else if (off == SDHCI_COMMAND_FLAGS) { 289 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 290 ((uint32_t)val << 16); 291 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 292 return; 293 } 294 295 val32 = RD4(sc, off & ~3); 296 val32 &= ~(0xffff << (off & 3) * 8); 297 val32 |= ((val & 0xffff) << (off & 3) * 8); 298 WR4(sc, off & ~3, val32); 299} 300 301static void 302ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 303 uint32_t val) 304{ 305 struct ti_sdhci_softc *sc = device_get_softc(dev); 306 307 WR4(sc, off, val); 308} 309 310static void 311ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 312 uint32_t *data, bus_size_t count) 313{ 314 struct ti_sdhci_softc *sc = device_get_softc(dev); 315 316 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 317} 318 319static void 320ti_sdhci_intr(void *arg) 321{ 322 struct ti_sdhci_softc *sc = arg; 323 324 sdhci_generic_intr(&sc->slot); 325} 326 327static int 328ti_sdhci_update_ios(device_t brdev, device_t reqdev) 329{ 330 struct ti_sdhci_softc *sc = device_get_softc(brdev); 331 struct sdhci_slot *slot; 332 struct mmc_ios *ios; 333 uint32_t val32, newval32; 334 335 slot = device_get_ivars(reqdev); 336 ios = &slot->host.ios; 337 338 /* 339 * There is an 8-bit-bus bit in the MMCHS control register which, when 340 * set, overrides the 1 vs 4 bit setting in the standard SDHCI 341 * registers. Set that bit first according to whether an 8-bit bus is 342 * requested, then let the standard driver handle everything else. 343 */ 344 val32 = ti_mmchs_read_4(sc, MMCHS_CON); 345 newval32 = val32; 346 347 if (ios->bus_width == bus_width_8) 348 newval32 |= MMCHS_CON_DW8; 349 else 350 newval32 &= ~MMCHS_CON_DW8; 351 352 if (ios->bus_mode == opendrain) 353 newval32 |= MMCHS_CON_OD; 354 else /* if (ios->bus_mode == pushpull) */ 355 newval32 &= ~MMCHS_CON_OD; 356 357 if (newval32 != val32) 358 ti_mmchs_write_4(sc, MMCHS_CON, newval32); 359 360 return (sdhci_generic_update_ios(brdev, reqdev)); 361} 362 363static int 364ti_sdhci_get_ro(device_t brdev, device_t reqdev) 365{ 366 struct ti_sdhci_softc *sc = device_get_softc(brdev); 367 368 if (sc->disable_readonly) 369 return (0); 370 371 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 372} 373 374static bool 375ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) 376{ 377 struct ti_sdhci_softc *sc = device_get_softc(dev); 378 379 return (sdhci_fdt_gpio_get_present(sc->gpio)); 380} 381 382static int 383ti_sdhci_detach(device_t dev) 384{ 385 386 /* sdhci_fdt_gpio_teardown(sc->gpio); */ 387 388 return (EBUSY); 389} 390 391static void 392ti_sdhci_hw_init(device_t dev) 393{ 394 struct ti_sdhci_softc *sc = device_get_softc(dev); 395 uint32_t regval; 396 unsigned long timeout; 397 398 /* Enable the controller and interface/functional clocks */ 399 if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) { 400 device_printf(dev, "Error: failed to enable MMC clock\n"); 401 return; 402 } 403 404 /* Get the frequency of the source clock */ 405 if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id, 406 &sc->baseclk_hz) != 0) { 407 device_printf(dev, "Error: failed to get source clock freq\n"); 408 return; 409 } 410 411 /* Issue a softreset to the controller */ 412 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 413 timeout = 1000; 414 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 415 MMCHS_SYSSTATUS_RESETDONE)) { 416 if (--timeout == 0) { 417 device_printf(dev, 418 "Error: Controller reset operation timed out\n"); 419 break; 420 } 421 DELAY(100); 422 } 423 424 /* 425 * Reset the command and data state machines and also other aspects of 426 * the controller such as bus clock and power. 427 * 428 * If we read the software reset register too fast after writing it we 429 * can get back a zero that means the reset hasn't started yet rather 430 * than that the reset is complete. Per TI recommendations, work around 431 * it by reading until we see the reset bit asserted, then read until 432 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk 433 * so that the main sdhci driver uses this same logic in its resets. 434 */ 435 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 436 timeout = 10000; 437 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 438 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) { 439 if (--timeout == 0) { 440 break; 441 } 442 DELAY(1); 443 } 444 timeout = 10000; 445 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 446 SDHCI_RESET_ALL)) { 447 if (--timeout == 0) { 448 device_printf(dev, 449 "Error: Software reset operation timed out\n"); 450 break; 451 } 452 DELAY(100); 453 } 454 455 /* 456 * The attach() routine has examined fdt data and set flags in 457 * slot.host.caps to reflect what voltages we can handle. Set those 458 * values in the CAPA register. The manual says that these values can 459 * only be set once, "before initialization" whatever that means, and 460 * that they survive a reset. So maybe doing this will be a no-op if 461 * u-boot has already initialized the hardware. 462 */ 463 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 464 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 465 regval |= MMCHS_SD_CAPA_VS18; 466 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 467 regval |= MMCHS_SD_CAPA_VS30; 468 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 469 470 /* Set initial host configuration (1-bit, std speed, pwr off). */ 471 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 472 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 473 474 /* Set the initial controller configuration. */ 475 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 476} 477 478static int 479ti_sdhci_attach(device_t dev) 480{ 481 struct ti_sdhci_softc *sc = device_get_softc(dev); 482 int rid, err; 483 pcell_t prop; 484 phandle_t node; 485 486 sc->dev = dev; 487 488 /* 489 * Get the MMCHS device id from FDT. If it's not there use the newbus 490 * unit number (which will work as long as the devices are in order and 491 * none are skipped in the fdt). Note that this is a property we made 492 * up and added in freebsd, it doesn't exist in the published bindings. 493 */ 494 node = ofw_bus_get_node(dev); 495 sc->mmchs_clk_id = ti_hwmods_get_clock(dev); 496 if (sc->mmchs_clk_id == INVALID_CLK_IDENT) { 497 device_printf(dev, "failed to get clock based on hwmods property\n"); 498 } 499 500 /* 501 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 502 * device, and only 1p8v on other devices unless an external transceiver 503 * is used. The only way we could know about a transceiver is fdt data. 504 * Note that we have to do this before calling ti_sdhci_hw_init() so 505 * that it can set the right values in the CAPA register, which can only 506 * be done once and never reset. 507 */ 508 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 509 if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) { 510 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 511 } 512 513 /* 514 * Set the offset from the device's memory start to the MMCHS registers. 515 * Also for OMAP4 disable high speed mode due to erratum ID i626. 516 */ 517 switch (ti_chip()) { 518#ifdef SOC_OMAP4 519 case CHIP_OMAP_4: 520 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 521 sc->disable_highspeed = true; 522 break; 523#endif 524#ifdef SOC_TI_AM335X 525 case CHIP_AM335X: 526 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 527 break; 528#endif 529 default: 530 panic("Unknown OMAP device\n"); 531 } 532 533 /* 534 * The standard SDHCI registers are at a fixed offset (the same on all 535 * SoCs) beyond the MMCHS registers. 536 */ 537 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 538 539 /* Resource setup. */ 540 rid = 0; 541 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 542 RF_ACTIVE); 543 if (!sc->mem_res) { 544 device_printf(dev, "cannot allocate memory window\n"); 545 err = ENXIO; 546 goto fail; 547 } 548 549 rid = 0; 550 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 551 RF_ACTIVE); 552 if (!sc->irq_res) { 553 device_printf(dev, "cannot allocate interrupt\n"); 554 err = ENXIO; 555 goto fail; 556 } 557 558 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 559 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 560 device_printf(dev, "cannot setup interrupt handler\n"); 561 err = ENXIO; 562 goto fail; 563 } 564 565 /* 566 * Set up handling of card-detect and write-protect gpio lines. 567 * 568 * If there is no write protect info in the fdt data, fall back to the 569 * historical practice of assuming that the card is writable. This 570 * works around bad fdt data from the upstream source. The alternative 571 * would be to trust the sdhci controller's PRESENT_STATE register WP 572 * bit, but it may say write protect is in effect when it's not if the 573 * pinmux setup doesn't route the WP signal into the sdchi block. 574 */ 575 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot); 576 577 if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable")) 578 sc->disable_readonly = true; 579 580 /* Initialise the MMCHS hardware. */ 581 ti_sdhci_hw_init(dev); 582 583 /* 584 * The capabilities register can only express base clock frequencies in 585 * the range of 0-63MHz for a v2.0 controller. Since our clock runs 586 * faster than that, the hardware sets the frequency to zero in the 587 * register. When the register contains zero, the sdhci driver expects 588 * slot.max_clk to already have the right value in it. 589 */ 590 sc->slot.max_clk = sc->baseclk_hz; 591 592 /* 593 * The MMCHS timeout counter is based on the output sdclock. Tell the 594 * sdhci driver to recalculate the timeout clock whenever the output 595 * sdclock frequency changes. 596 */ 597 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 598 599 /* 600 * The MMCHS hardware shifts the 136-bit response data (in violation of 601 * the spec), so tell the sdhci driver not to do the same in software. 602 */ 603 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 604 605 /* 606 * Reset bits are broken, have to wait to see the bits asserted 607 * before waiting to see them de-asserted. 608 */ 609 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED; 610 611 /* 612 * DMA is not really broken, I just haven't implemented it yet. 613 */ 614 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 615 616 /* 617 * Set up the hardware and go. Note that this sets many of the 618 * slot.host.* fields, so we have to do this before overriding any of 619 * those values based on fdt data, below. 620 */ 621 sdhci_init_slot(dev, &sc->slot, 0); 622 623 /* 624 * The SDHCI controller doesn't realize it, but we can support 8-bit 625 * even though we're not a v3.0 controller. If there's an fdt bus-width 626 * property, honor it. 627 */ 628 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 629 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 630 MMC_CAP_8_BIT_DATA); 631 switch (prop) { 632 case 8: 633 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 634 /* FALLTHROUGH */ 635 case 4: 636 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 637 break; 638 case 1: 639 break; 640 default: 641 device_printf(dev, "Bad bus-width value %u\n", prop); 642 break; 643 } 644 } 645 646 /* 647 * If the slot is flagged with the non-removable property, set our flag 648 * to always force the SDHCI_CARD_PRESENT bit on. 649 */ 650 node = ofw_bus_get_node(dev); 651 if (OF_hasprop(node, "non-removable")) 652 sc->force_card_present = true; 653 654 bus_generic_probe(dev); 655 bus_generic_attach(dev); 656 657 sdhci_start_slot(&sc->slot); 658 659 return (0); 660 661fail: 662 if (sc->intr_cookie) 663 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 664 if (sc->irq_res) 665 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 666 if (sc->mem_res) 667 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 668 669 return (err); 670} 671 672static int 673ti_sdhci_probe(device_t dev) 674{ 675 676 if (!ofw_bus_status_okay(dev)) 677 return (ENXIO); 678 679 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 680 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 681 return (BUS_PROBE_DEFAULT); 682 } 683 684 return (ENXIO); 685} 686 687static device_method_t ti_sdhci_methods[] = { 688 /* Device interface */ 689 DEVMETHOD(device_probe, ti_sdhci_probe), 690 DEVMETHOD(device_attach, ti_sdhci_attach), 691 DEVMETHOD(device_detach, ti_sdhci_detach), 692 693 /* Bus interface */ 694 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 695 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 696 DEVMETHOD(bus_print_child, bus_generic_print_child), 697 698 /* MMC bridge interface */ 699 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 700 DEVMETHOD(mmcbr_request, sdhci_generic_request), 701 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 702 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 703 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 704 705 /* SDHCI registers accessors */ 706 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 707 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 708 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 709 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 710 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 711 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 712 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 713 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 714 DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present), 715 716 DEVMETHOD_END 717}; 718 719static devclass_t ti_sdhci_devclass; 720 721static driver_t ti_sdhci_driver = { 722 "sdhci_ti", 723 ti_sdhci_methods, 724 sizeof(struct ti_sdhci_softc), 725}; 726 727DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0); 728MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); 729DRIVER_MODULE(mmc, sdhci_ti, mmc_driver, mmc_devclass, NULL, NULL); 730MODULE_DEPEND(sdhci_ti, mmc, 1, 1, 1); 731